See Vitis™ Development Environment on xilinx.com
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Contributions to Vitis-Tutorials are welcome!
Send your PRs to the branch that matches the version of the tool you created and verified with the tutorial
- Provide a clear answer to "What does this PR do?".
- Read General Rules below.
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git commit -s. - Add Legal information to the pull request comment.
- Send your PR.
- Includes
README.mdfile (s) with technical details to communicate the intention of the tutorial, including detailed descriptions of the build flows, all necessary tools with version information, and development system setup information. - Only source code and scripts are allowed. Binary files or compressed big-size files should be uploaded to a file server with a link added in the tutorial.
- Make the tutorial user-oriented, robust, and reusable for end users, even at the cost of writing more code in the background.
- Provide necessary information for a general legal review, make sure the code allows the license that Vitis tutorials support.
| Tutorial | Description |
| Versal Custom Thin Platform Extensible System | Versal VCK190 System Example Design based on a thin custom platform (Minimal clocks and AXI exposed to PL) including HLS/RTL kernels and AI Engine kernel using a full Makefile build-flow. |
| DSP Design on AI Engine with GUI and Makefile Flows | This tutorial implements a FIR filter from the Vitis DSP Library into the AI Engine domain, either with Makefile or GUI based flows. The design runs on the VCK190 board. The host application applies XRT APIs and Petalinux. |
| Vitis HLS Optimization Techniques on Embedded Boards | This tutorial illustrates some C/C++ code optimization techniques for high performance with Vitis HLS. Some HLS are also implemented into ZCU102 or VCK190 target boards with the Vitis HW Acceleration flow. |
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