diff --git a/README.md b/README.md index c8e67b5..cb392e5 100644 --- a/README.md +++ b/README.md @@ -9,7 +9,7 @@ How to build Store linux-renesas_4.14.bbappend to the following path. /meta-rcar-gen3/recipes-kernel Store patches to the following path. - /meta-rcar-gen3/recipes-kernel/linux/linux-renesas/salvator-x + /meta-rcar-gen3/recipes-kernel/linux/linux-renesas/ 2. building with bitbake diff --git a/meta-rcar-gen3/recipes-kernel/linux/linux-renesas/salvator-x/0001-drm-rcar-du-Add-DU-CMM-support.patch b/meta-rcar-gen3/recipes-kernel/linux/linux-renesas/0001-drm-rcar-du-Add-DU-CMM-support.patch similarity index 78% rename from meta-rcar-gen3/recipes-kernel/linux/linux-renesas/salvator-x/0001-drm-rcar-du-Add-DU-CMM-support.patch rename to meta-rcar-gen3/recipes-kernel/linux/linux-renesas/0001-drm-rcar-du-Add-DU-CMM-support.patch index dc2a330..c1810fc 100644 --- a/meta-rcar-gen3/recipes-kernel/linux/linux-renesas/salvator-x/0001-drm-rcar-du-Add-DU-CMM-support.patch +++ b/meta-rcar-gen3/recipes-kernel/linux/linux-renesas/0001-drm-rcar-du-Add-DU-CMM-support.patch @@ -1,6 +1,6 @@ -From b40cf655f1d6b420bcdd53b6a1276acf21ef0737 Mon Sep 17 00:00:00 2001 +From bd8b21ee9ea9dbf231238d8e593367298ef0f0c9 Mon Sep 17 00:00:00 2001 From: Sojiro Kusunoki -Date: Mon, 11 Jun 2018 16:18:50 +0900 +Date: Tue, 23 Oct 2018 12:15:08 +0900 Subject: [PATCH] drm: rcar-du: Add DU CMM support Signed-off-by: Sojiro Kusunoki @@ -9,38 +9,39 @@ Signed-off-by: Sojiro Kusunoki arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 5 + .../arm64/boot/dts/renesas/r8a7795-salvator-xs.dts | 5 + arch/arm64/boot/dts/renesas/r8a7795.dtsi | 27 +- - arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts | 5 +- + arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts | 4 + .../arm64/boot/dts/renesas/r8a7796-salvator-xs.dts | 4 + arch/arm64/boot/dts/renesas/r8a7796.dtsi | 24 +- .../arm64/boot/dts/renesas/r8a77965-salvator-x.dts | 4 + .../boot/dts/renesas/r8a77965-salvator-xs.dts | 4 + arch/arm64/boot/dts/renesas/r8a77965.dtsi | 24 +- arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts | 6 +- - arch/arm64/boot/dts/renesas/r8a77990.dtsi | 21 +- + arch/arm64/boot/dts/renesas/r8a77990.dtsi | 19 +- drivers/clk/renesas/r8a7795-cpg-mssr.c | 4 + drivers/clk/renesas/r8a7796-cpg-mssr.c | 3 + drivers/clk/renesas/r8a77965-cpg-mssr.c | 3 + drivers/clk/renesas/r8a77990-cpg-mssr.c | 2 + drivers/gpu/drm/rcar-du/Makefile | 2 + - drivers/gpu/drm/rcar-du/rcar_du_cmm.c | 1770 ++++++++++++++++++++ - drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 24 + - drivers/gpu/drm/rcar-du/rcar_du_crtc.h | 32 + - drivers/gpu/drm/rcar-du/rcar_du_drv.c | 53 +- - drivers/gpu/drm/rcar-du/rcar_du_drv.h | 12 +- + drivers/gpu/drm/rcar-du/rcar_du_cmm.c | 1758 ++++++++++++++++++++ + drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 26 + + drivers/gpu/drm/rcar-du/rcar_du_crtc.h | 31 + + drivers/gpu/drm/rcar-du/rcar_du_drv.c | 54 +- + drivers/gpu/drm/rcar-du/rcar_du_drv.h | 7 + drivers/gpu/drm/rcar-du/rcar_du_group.c | 5 + - drivers/gpu/drm/rcar-du/rcar_du_regs.h | 92 + + drivers/gpu/drm/rcar-du/rcar_du_regs.h | 90 + + drivers/gpu/drm/rcar-du/rcar_lvds.c | 13 + include/uapi/drm/rcar_du_drm.h | 131 +- - 25 files changed, 2232 insertions(+), 35 deletions(-) + 26 files changed, 2229 insertions(+), 31 deletions(-) create mode 100644 drivers/gpu/drm/rcar-du/rcar_du_cmm.c diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts -index 39436cc..6e13a5e 100644 +index 212e1f6..6cc6fd3 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts -@@ -96,11 +96,16 @@ +@@ -95,11 +95,16 @@ + <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>, <&cpg CPG_MOD 721>, - <&cpg CPG_MOD 727>, + <&cpg CPG_MOD 711>, + <&cpg CPG_MOD 710>, + <&cpg CPG_MOD 709>, @@ -49,19 +50,19 @@ index 39436cc..6e13a5e 100644 <&x21_clk>, <&x22_clk>, <&versaclock5 2>; - clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0", + clock-names = "du.0", "du.1", "du.2", "du.3", + "cmm.0", "cmm.1", "cmm.2", "cmm.3", "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3"; + }; - ports { diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts -index a971e93..ebd4a15 100644 +index 6156bcc..cda48e4 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts -@@ -96,11 +96,16 @@ +@@ -95,11 +95,16 @@ + <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>, <&cpg CPG_MOD 721>, - <&cpg CPG_MOD 727>, + <&cpg CPG_MOD 711>, + <&cpg CPG_MOD 710>, + <&cpg CPG_MOD 709>, @@ -70,19 +71,19 @@ index a971e93..ebd4a15 100644 <&x21_clk>, <&x22_clk>, <&versaclock5 2>; - clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0", + clock-names = "du.0", "du.1", "du.2", "du.3", + "cmm.0", "cmm.1", "cmm.2", "cmm.3", "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3"; + }; - ports { diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts -index 84d946c..02923f1 100644 +index b37b1de..aaefd18 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts -@@ -96,11 +96,16 @@ +@@ -95,11 +95,16 @@ + <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>, <&cpg CPG_MOD 721>, - <&cpg CPG_MOD 727>, + <&cpg CPG_MOD 711>, + <&cpg CPG_MOD 710>, + <&cpg CPG_MOD 709>, @@ -91,292 +92,278 @@ index 84d946c..02923f1 100644 <&x21_clk>, <&x22_clk>, <&versaclock6 2>; - clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0", + clock-names = "du.0", "du.1", "du.2", "du.3", + "cmm.0", "cmm.1", "cmm.2", "cmm.3", "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3"; + }; - ports { diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi -index 5bfb001..eb8b1ff 100644 +index 1c8e713..e2116f5 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi -@@ -3457,8 +3457,13 @@ +@@ -3521,8 +3521,13 @@ + du: display@feb00000 { compatible = "renesas,du-r8a7795"; - reg = <0 0xfeb00000 0 0x80000>, -- <0 0xfeb90000 0 0x14>; -- reg-names = "du", "lvds.0"; -+ <0 0xfeb90000 0 0x14>, +- reg = <0 0xfeb00000 0 0x80000>; +- reg-names = "du"; ++ reg = <0 0xfeb00000 0 0x80000>, + <0 0xfea40000 0 0x00001000>, + <0 0xfea50000 0 0x00001000>, + <0 0xfea60000 0 0x00001000>, + <0 0xfea70000 0 0x00001000>; -+ reg-names = "du", "lvds.0", ++ reg-names = "du", + "cmm.0", "cmm.1", "cmm.2", "cmm.3"; interrupts = , , , -@@ -3467,14 +3472,24 @@ +@@ -3530,13 +3535,23 @@ + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>, - <&cpg CPG_MOD 721>, -- <&cpg CPG_MOD 727>; -- clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0"; -+ <&cpg CPG_MOD 727>, +- <&cpg CPG_MOD 721>; +- clock-names = "du.0", "du.1", "du.2", "du.3"; ++ <&cpg CPG_MOD 721>, + <&cpg CPG_MOD 711>, + <&cpg CPG_MOD 710>, + <&cpg CPG_MOD 709>, + <&cpg CPG_MOD 708>; -+ clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0", ++ clock-names = "du.0", "du.1", "du.2", "du.3", + "cmm.0", "cmm.1", "cmm.2", "cmm.3"; resets = <&cpg 724>, <&cpg 724>, <&cpg 722>, - <&cpg 722>, -- <&cpg 727>; -- reset-names = "du.0", "du.1", "du.2", "du.3", "lvds.0"; -+ <&cpg 727>, +- <&cpg 722>; +- reset-names = "du.0", "du.1", "du.2", "du.3"; ++ <&cpg 722>, + <&cpg 711>, + <&cpg 710>, + <&cpg 709>, + <&cpg 708>; -+ reset-names = "du.0", "du.1", "du.2", "du.3", "lvds.0", ++ reset-names = "du.0", "du.1", "du.2", "du.3", + "cmm.0", "cmm.1", "cmm.2", "cmm.3"; vsps = <&vspd0 0 &vspd1 0 &vspd2 0 &vspd0 1>; status = "disabled"; diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts -index a2ce432..76f4807 100644 +index 8e4f264..fb0808c 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts -@@ -85,12 +85,15 @@ +@@ -84,10 +84,14 @@ + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>, - <&cpg CPG_MOD 727>, + <&cpg CPG_MOD 711>, + <&cpg CPG_MOD 710>, + <&cpg CPG_MOD 709>, <&versaclock5 1>, <&x21_clk>, <&versaclock5 2>; - clock-names = "du.0", "du.1", "du.2", "lvds.0", + clock-names = "du.0", "du.1", "du.2", + "cmm.0", "cmm.1", "cmm.2", "dclkin.0", "dclkin.1", "dclkin.2"; -- - ports { - port@2 { - endpoint { + }; + diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts -index 38d0161..1bf2628 100644 +index 2f4bd3a..d44116f2 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts +++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts -@@ -85,10 +85,14 @@ +@@ -94,10 +94,14 @@ + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>, - <&cpg CPG_MOD 727>, + <&cpg CPG_MOD 711>, + <&cpg CPG_MOD 710>, + <&cpg CPG_MOD 709>, <&versaclock6 1>, <&x21_clk>, <&versaclock6 2>; - clock-names = "du.0", "du.1", "du.2", "lvds.0", + clock-names = "du.0", "du.1", "du.2", + "cmm.0", "cmm.1", "cmm.2", "dclkin.0", "dclkin.1", "dclkin.2"; + }; - ports { diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi -index 4797a63..145bbe5 100644 +index f25b476..98f8537 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi -@@ -3231,21 +3231,33 @@ +@@ -3196,19 +3196,31 @@ + du: display@feb00000 { compatible = "renesas,du-r8a7796"; - reg = <0 0xfeb00000 0 0x70000>, -- <0 0xfeb90000 0 0x14>; -- reg-names = "du", "lvds.0"; -+ <0 0xfeb90000 0 0x14>, +- reg = <0 0xfeb00000 0 0x70000>; +- reg-names = "du"; ++ reg = <0 0xfeb00000 0 0x70000>, + <0 0xfea40000 0 0x00001000>, + <0 0xfea50000 0 0x00001000>, + <0 0xfea60000 0 0x00001000>; -+ reg-names = "du", "lvds.0", ++ reg-names = "du", + "cmm.0", "cmm.1", "cmm.2"; interrupts = , , ; clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 722>, -- <&cpg CPG_MOD 727>; -- clock-names = "du.0", "du.1", "du.2", "lvds.0"; -+ <&cpg CPG_MOD 727>, +- <&cpg CPG_MOD 722>; +- clock-names = "du.0", "du.1", "du.2"; ++ <&cpg CPG_MOD 722>, + <&cpg CPG_MOD 711>, + <&cpg CPG_MOD 710>, + <&cpg CPG_MOD 709>; -+ clock-names = "du.0", "du.1", "du.2", "lvds.0", ++ clock-names = "du.0", "du.1", "du.2", + "cmm.0", "cmm.1", "cmm.2"; resets = <&cpg 724>, <&cpg 724>, - <&cpg 722>, -- <&cpg 727>; -- reset-names = "du.0", "du.1", "du.2", "lvds.0"; -+ <&cpg 727>, +- <&cpg 722>; +- reset-names = "du.0", "du.1", "du.2"; ++ <&cpg 722>, + <&cpg 711>, + <&cpg 710>, + <&cpg 709>; -+ reset-names = "du.0", "du.1", "du.2", "lvds.0", ++ reset-names = "du.0", "du.1", "du.2", + "cmm.0", "cmm.1", "cmm.2"; status = "disabled"; vsps = <&vspd0 &vspd1 &vspd2>; diff --git a/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts -index 53e7260..1b3f4f1 100644 +index 6c04a58..62d4f3c 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts -@@ -80,10 +80,14 @@ +@@ -76,10 +76,14 @@ + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 721>, - <&cpg CPG_MOD 727>, + <&cpg CPG_MOD 711>, + <&cpg CPG_MOD 710>, + <&cpg CPG_MOD 708>, <&versaclock5 1>, <&x21_clk>, <&versaclock5 2>; - clock-names = "du.0", "du.1", "du.3", "lvds.0", + clock-names = "du.0", "du.1", "du.3", + "cmm.0", "cmm.1", "cmm.3", "dclkin.0", "dclkin.1", "dclkin.3"; + }; - ports { diff --git a/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts -index 41f6b05..f47ee2f 100644 +index 5e6b1e5..45c16bf 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts +++ b/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts -@@ -80,10 +80,14 @@ +@@ -76,10 +76,14 @@ + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 721>, - <&cpg CPG_MOD 727>, + <&cpg CPG_MOD 711>, + <&cpg CPG_MOD 710>, + <&cpg CPG_MOD 708>, <&versaclock6 1>, <&x21_clk>, <&versaclock6 2>; - clock-names = "du.0", "du.1", "du.3", "lvds.0", + clock-names = "du.0", "du.1", "du.3", + "cmm.0", "cmm.1", "cmm.3", "dclkin.0", "dclkin.1", "dclkin.3"; + }; - ports { diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi -index b3890cf..b12ff04 100644 +index d86bf9e..7113c3c 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi -@@ -2492,21 +2492,33 @@ +@@ -2382,19 +2382,31 @@ + du: display@feb00000 { compatible = "renesas,du-r8a77965"; - reg = <0 0xfeb00000 0 0x80000>, -- <0 0xfeb90000 0 0x14>; -- reg-names = "du", "lvds.0"; -+ <0 0xfeb90000 0 0x14>, +- reg = <0 0xfeb00000 0 0x80000>; +- reg-names = "du"; ++ reg = <0 0xfeb00000 0 0x80000>, + <0 0xfea40000 0 0x00001000>, + <0 0xfea50000 0 0x00001000>, + <0 0xfea70000 0 0x00001000>; -+ reg-names = "du", "lvds.0", ++ reg-names = "du", + "cmm.0", "cmm.1", "cmm.3"; interrupts = , , ; clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 721>, -- <&cpg CPG_MOD 727>; -- clock-names = "du.0", "du.1", "du.3", "lvds.0"; -+ <&cpg CPG_MOD 727>, +- <&cpg CPG_MOD 721>; +- clock-names = "du.0", "du.1", "du.3"; ++ <&cpg CPG_MOD 721>, + <&cpg CPG_MOD 711>, + <&cpg CPG_MOD 710>, + <&cpg CPG_MOD 708>; -+ clock-names = "du.0", "du.1", "du.3", "lvds.0", ++ clock-names = "du.0", "du.1", "du.3", + "cmm.0", "cmm.1", "cmm.3"; resets = <&cpg 724>, <&cpg 724>, - <&cpg 722>, -- <&cpg 727>; -- reset-names = "du.0", "du.1", "du.3", "lvds.0"; -+ <&cpg 727>, +- <&cpg 722>; +- reset-names = "du.0", "du.1", "du.3"; ++ <&cpg 722>, + <&cpg 711>, + <&cpg 710>, + <&cpg 708>; -+ reset-names = "du.0", "du.1", "du.3", "lvds.0", ++ reset-names = "du.0", "du.1", "du.3", + "cmm.0", "cmm.1", "cmm.3"; status = "disabled"; vsps = <&vspd0 0 &vspd1 0 &vspd0 1>; diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts -index c17f350..1410680 100644 +index 10a3403..64ca3604 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts +++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts -@@ -370,9 +370,11 @@ - <&cpg CPG_MOD 727>, - <&cpg CPG_MOD 727>, - <&x13_clk>, -- <&extal_clk>; -+ <&extal_clk>, +@@ -451,8 +451,10 @@ + + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, +- <&x13_clk>; +- clock-names = "du.0", "du.1", "dclkin.0"; ++ <&x13_clk>, + <&cpg CPG_MOD 711>, + <&cpg CPG_MOD 710>; - clock-names = "du.0", "du.1", "lvds.0", "lvds.1", -- "dclkin.0", "extal"; -+ "dclkin.0", "extal", "cmm.0", "cmm.1"; ++ clock-names = "du.0", "du.1", "dclkin.0", "cmm.0", "cmm.1"; + }; - ports { - port@0 { + &ehci0 { diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi -index 7c7ae9a..861570b 100644 +index 242de2c..2d02532 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi -@@ -1933,20 +1933,29 @@ +@@ -1898,16 +1898,23 @@ + + du: display@feb00000 { compatible = "renesas,du-r8a77990"; - reg = <0 0xfeb00000 0 0x40000>, - <0 0xfeb90000 0 0x100>, -- <0 0xfeb90100 0 0x100>; -- reg-names = "du", "lvds.0", "lvds.1"; -+ <0 0xfeb90100 0 0x100>, +- reg = <0 0xfeb00000 0 0x40000>; +- reg-names = "du"; ++ reg = <0 0xfeb00000 0 0x40000>, + <0 0xfea40000 0 0x00001000>, + <0 0xfea50000 0 0x00001000>; -+ reg-names = "du", "lvds.0", "lvds.1", ++ reg-names = "du", + "cmm.0", "cmm.1"; interrupts = , ; clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 727>, -- <&cpg CPG_MOD 727>; -- clock-names = "du.0", "du.1", "lvds.0","lvds.1"; -+ <&cpg CPG_MOD 727>, +- <&cpg CPG_MOD 723>; +- clock-names = "du.0", "du.1"; ++ <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 711>, + <&cpg CPG_MOD 710>; -+ clock-names = "du.0", "du.1", "lvds.0","lvds.1", -+ "cmm.0", "cmm.1"; ++ clock-names = "du.0", "du.1", "cmm.0", "cmm.1"; resets = <&cpg 724>, - <&cpg 724>, - <&cpg 727>, -- <&cpg 726>; -- reset-names = "du.0", "du.1", "lvds.0","lvds.1"; -+ <&cpg 726>, +- <&cpg 724>; +- reset-names = "du.0", "du.1"; ++ <&cpg 724>, + <&cpg 711>, + <&cpg 710>; -+ reset-names = "du.0", "du.1", "lvds.0","lvds.1", -+ "cmm.0", "cmm.1"; ++ reset-names = "du.0", "du.1", "cmm.0", "cmm.1"; + vsps = <&vspd0 0 &vspd1 0>; status = "disabled"; - vsps = <&vspd0 &vspd1>; diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c -index 370fb08..08c80b5 100644 +index f6569a3..5a0db21 100644 --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c -@@ -208,6 +208,10 @@ enum clk_ids { - DEF_MOD("ehci0", 703, R8A7795_CLK_S3D4), - DEF_MOD("hsusb", 704, R8A7795_CLK_S3D4), - DEF_MOD("hsusb3", 705, R8A7795_CLK_S3D4), +@@ -206,6 +206,10 @@ enum clk_ids { + DEF_MOD("ehci0", 703, R8A7795_CLK_S3D2), + DEF_MOD("hsusb", 704, R8A7795_CLK_S3D2), + DEF_MOD("hsusb3", 705, R8A7795_CLK_S3D2), + DEF_MOD("cmm3", 708, R8A7795_CLK_S2D1), + DEF_MOD("cmm2", 709, R8A7795_CLK_S2D1), + DEF_MOD("cmm1", 710, R8A7795_CLK_S2D1), @@ -385,13 +372,13 @@ index 370fb08..08c80b5 100644 DEF_MOD("csi20", 714, R8A7795_CLK_CSI0), DEF_MOD("csi41", 715, R8A7795_CLK_CSI0), diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c -index b7dbf7d..583d385 100644 +index e26f81c..a829449 100644 --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c -@@ -187,6 +187,9 @@ enum clk_ids { - DEF_MOD("ehci1", 702, R8A7796_CLK_S3D4), - DEF_MOD("ehci0", 703, R8A7796_CLK_S3D4), - DEF_MOD("hsusb", 704, R8A7796_CLK_S3D4), +@@ -185,6 +185,9 @@ enum clk_ids { + DEF_MOD("ehci1", 702, R8A7796_CLK_S3D2), + DEF_MOD("ehci0", 703, R8A7796_CLK_S3D2), + DEF_MOD("hsusb", 704, R8A7796_CLK_S3D2), + DEF_MOD("cmm2", 709, R8A7796_CLK_S2D1), + DEF_MOD("cmm1", 710, R8A7796_CLK_S2D1), + DEF_MOD("cmm0", 711, R8A7796_CLK_S2D1), @@ -399,51 +386,51 @@ index b7dbf7d..583d385 100644 DEF_MOD("csi40", 716, R8A7796_CLK_CSI0), DEF_MOD("du2", 722, R8A7796_CLK_S2D1), diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c -index 92a4772..7b0c8c7 100644 +index 581a7a9..a042f9f 100644 --- a/drivers/clk/renesas/r8a77965-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c -@@ -179,6 +179,9 @@ enum clk_ids { - DEF_MOD("ehci1", 702, R8A77965_CLK_S3D4), - DEF_MOD("ehci0", 703, R8A77965_CLK_S3D4), - DEF_MOD("hsusb", 704, R8A77965_CLK_S3D4), -+ DEF_MOD("cmm3", 708, R8A77965_CLK_S2D1), -+ DEF_MOD("cmm1", 710, R8A77965_CLK_S2D1), -+ DEF_MOD("cmm0", 711, R8A77965_CLK_S2D1), - DEF_MOD("csi20", 714, R8A77965_CLK_CSI0), - DEF_MOD("csi40", 716, R8A77965_CLK_CSI0), - DEF_MOD("du3", 721, R8A77965_CLK_S2D1), +@@ -180,6 +180,9 @@ enum clk_ids { + DEF_MOD("ehci1", 702, R8A77965_CLK_S3D2), + DEF_MOD("ehci0", 703, R8A77965_CLK_S3D2), + DEF_MOD("hsusb", 704, R8A77965_CLK_S3D2), ++ DEF_MOD("cmm3", 708, R8A77965_CLK_S2D1), ++ DEF_MOD("cmm1", 710, R8A77965_CLK_S2D1), ++ DEF_MOD("cmm0", 711, R8A77965_CLK_S2D1), + DEF_MOD("csi20", 714, R8A77965_CLK_CSI0), + DEF_MOD("csi40", 716, R8A77965_CLK_CSI0), + DEF_MOD("du3", 721, R8A77965_CLK_S2D1), diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c -index 3b35524..1222edc 100644 +index 6814c85..5d0c8b6 100644 --- a/drivers/clk/renesas/r8a77990-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c -@@ -179,6 +179,8 @@ enum clk_ids { - DEF_MOD("vspi0", 631, R8A77990_CLK_S0D1), - DEF_MOD("ehci0", 703, R8A77990_CLK_S3D4), - DEF_MOD("hsusb", 704, R8A77990_CLK_S3D4), -+ DEF_MOD("cmm1", 710, R8A77990_CLK_S0D1), -+ DEF_MOD("cmm0", 711, R8A77990_CLK_S0D1), +@@ -178,6 +178,8 @@ enum clk_ids { + + DEF_MOD("ehci0", 703, R8A77990_CLK_S3D2), + DEF_MOD("hsusb", 704, R8A77990_CLK_S3D2), ++ DEF_MOD("cmm1", 710, R8A77990_CLK_S1D1), ++ DEF_MOD("cmm0", 711, R8A77990_CLK_S1D1), DEF_MOD("csi40", 716, R8A77990_CLK_CSI0), - DEF_MOD("du1", 723, R8A77990_CLK_S2D1), - DEF_MOD("du0", 724, R8A77990_CLK_S2D1), + DEF_MOD("du1", 723, R8A77990_CLK_S1D1), + DEF_MOD("du0", 724, R8A77990_CLK_S1D1), diff --git a/drivers/gpu/drm/rcar-du/Makefile b/drivers/gpu/drm/rcar-du/Makefile -index 0cf5c11..9082be8 100644 +index 3e58ed9..1fd15a8 100644 --- a/drivers/gpu/drm/rcar-du/Makefile +++ b/drivers/gpu/drm/rcar-du/Makefile -@@ -7,6 +7,8 @@ rcar-du-drm-y := rcar_du_crtc.o \ - rcar_du_lvdscon.o \ +@@ -6,6 +6,8 @@ rcar-du-drm-y := rcar_du_crtc.o \ + rcar_du_kms.o \ rcar_du_plane.o +rcar-du-drm-y += rcar_du_cmm.o + - rcar-du-drm-$(CONFIG_DRM_RCAR_LVDS) += rcar_du_lvdsenc.o - - rcar-du-drm-$(CONFIG_DRM_RCAR_VSP) += rcar_du_vsp.o + rcar-du-drm-$(CONFIG_DRM_RCAR_LVDS) += rcar_du_of.o \ + rcar_du_of_lvds_r8a7790.dtb.o \ + rcar_du_of_lvds_r8a7791.dtb.o \ diff --git a/drivers/gpu/drm/rcar-du/rcar_du_cmm.c b/drivers/gpu/drm/rcar-du/rcar_du_cmm.c new file mode 100644 -index 0000000..4856277 +index 0000000..ae4717c --- /dev/null +++ b/drivers/gpu/drm/rcar-du/rcar_du_cmm.c -@@ -0,0 +1,1770 @@ +@@ -0,0 +1,1758 @@ +/*************************************************************************/ /* + * DU CMM + * @@ -522,8 +509,9 @@ index 0000000..4856277 + +/* #define DEBUG_PROCE_TIME 1 */ + ++#define CMM_CLU_SAMPLES 17 +#define CMM_LUT_NUM 256 -+#define CMM_CLU_NUM (17 * 17 * 17) ++#define CMM_CLU_NUM (CMM_CLU_SAMPLES * CMM_CLU_SAMPLES * CMM_CLU_SAMPLES) +#define CMM_HGO_NUM 64 + +enum { @@ -565,16 +553,15 @@ index 0000000..4856277 + +struct cmm_reg_save { +#ifdef CONFIG_PM_SLEEP -+ wait_queue_head_t wait; -+ + u32 *lut_table; + u32 *clu_table; +#endif /* CONFIG_PM_SLEEP */ ++ wait_queue_head_t wait; + + u32 cm2_ctl0; /* CM2_CTL0 */ -+ u32 hgo_offset; /* CMM_HGO_OFFSET */ -+ u32 hgo_size; /* CMM_HGO_SIZE */ -+ u32 hgo_mode; /* CMM_HGO_MODE */ ++ u32 hgo_offset; /* CM2_HGO_OFFSET */ ++ u32 hgo_size; /* CM2_HGO_SIZE */ ++ u32 hgo_mode; /* CM2_HGO_MODE */ +}; + +struct rcar_du_cmm { @@ -646,11 +633,11 @@ index 0000000..4856277 +{ + int r, g, b; + -+ r = index % 17; -+ index /= 17; -+ g = index % 17; -+ index /= 17; -+ b = index % 17; ++ r = index % CMM_CLU_SAMPLES; ++ index /= CMM_CLU_SAMPLES; ++ g = index % CMM_CLU_SAMPLES; ++ index /= CMM_CLU_SAMPLES; ++ b = index % CMM_CLU_SAMPLES; + + r = (r << 20); + if (r > (255 << 16)) @@ -736,27 +723,27 @@ index 0000000..4856277 + mutex_unlock(&cmm_event_lock); + + cm2_ctl0 = du_cmm->reg_save.cm2_ctl0; -+ cm2_ctl0 &= ~(CMM_CTL0_TM1_MASK | CMM_CTL0_TM0_MASK | -+ CMM_CTL0_YC | CMM_CTL0_DBUF | CMM_CTL0_CLUDB); ++ cm2_ctl0 &= ~(CM2_CTL0_TM1_MASK | CM2_CTL0_TM0_MASK | ++ CM2_CTL0_YC | CM2_CTL0_DBUF | CM2_CTL0_CLUDB); + + switch (config->csc) { + case CSC_CONVERT_NONE: + break; + + case CSC_CONVERT_BT601_YCbCr240: -+ cm2_ctl0 |= (CMM_CTL0_TM_BT601_YC240 | CMM_CTL0_YC); ++ cm2_ctl0 |= (CM2_CTL0_TM_BT601_YC240 | CM2_CTL0_YC); + break; + + case CSC_CONVERT_BT601_YCbCr255: -+ cm2_ctl0 |= (CMM_CTL0_TM_BT601_YC255 | CMM_CTL0_YC); ++ cm2_ctl0 |= (CM2_CTL0_TM_BT601_YC255 | CM2_CTL0_YC); + break; + + case CSC_CONVERT_BT709_RGB255: -+ cm2_ctl0 |= (CMM_CTL0_TM_BT709_RG255 | CMM_CTL0_YC); ++ cm2_ctl0 |= (CM2_CTL0_TM_BT709_RG255 | CM2_CTL0_YC); + break; + + case CSC_CONVERT_BT709_RGB235: -+ cm2_ctl0 |= (CMM_CTL0_TM_BT709_RG235 | CMM_CTL0_YC); ++ cm2_ctl0 |= (CM2_CTL0_TM_BT709_RG235 | CM2_CTL0_YC); + break; + + default: @@ -768,7 +755,7 @@ index 0000000..4856277 + case LUT_DOUBLE_BUFFER_AUTO: + case LUT_DOUBLE_BUFFER_A: + case LUT_DOUBLE_BUFFER_B: -+ cm2_ctl0 |= CMM_CTL0_DBUF; ++ cm2_ctl0 |= CM2_CTL0_DBUF; + break; + + default: @@ -785,7 +772,7 @@ index 0000000..4856277 + case CLU_DOUBLE_BUFFER_AUTO: + case CLU_DOUBLE_BUFFER_A: + case CLU_DOUBLE_BUFFER_B: -+ cm2_ctl0 |= CMM_CTL0_CLUDB; ++ cm2_ctl0 |= CM2_CTL0_CLUDB; + break; + + default: @@ -975,7 +962,7 @@ index 0000000..4856277 + (mode->vdisplay < (hgo->y_offset + hgo->height))) + return -EINVAL; + -+ if ((hgo->mode & ~CMM_HGO_MODE_MASK) || ++ if ((hgo->mode & ~CM2_HGO_MODE_MASK) || + ((hgo->mode & (0x3 << 0)) == (0x3 << 0)) || + ((hgo->mode & (0x3 << 2)) == (0x3 << 2))) + return -EINVAL; @@ -985,7 +972,7 @@ index 0000000..4856277 + hists = 0; + break; + case HGO_CTRL_BEFORE_LUT: -+ hists = CMM_CTL0_HISTS; ++ hists = CM2_CTL0_HISTS; + break; + default: + return -EINVAL; @@ -993,23 +980,23 @@ index 0000000..4856277 + + mutex_lock(&du_cmm->lock); + -+ rcar_du_cmm_write(du_cmm, CMM_HGO_OFFSET, ++ rcar_du_cmm_write(du_cmm, CM2_HGO_OFFSET, + (hgo->x_offset << 16) | (hgo->y_offset << 0)); -+ rcar_du_cmm_write(du_cmm, CMM_HGO_SIZE, ++ rcar_du_cmm_write(du_cmm, CM2_HGO_SIZE, + (hgo->width << 16) | (hgo->height << 0)); -+ rcar_du_cmm_write(du_cmm, CMM_HGO_MODE, hgo->mode); -+ rcar_du_cmm_write(du_cmm, CMM_HGO_LB_TH, 0); -+ rcar_du_cmm_write(du_cmm, CMM_HGO_LB0_H, 0); -+ rcar_du_cmm_write(du_cmm, CMM_HGO_LB0_V, 0); -+ rcar_du_cmm_write(du_cmm, CMM_HGO_LB1_H, 0); -+ rcar_du_cmm_write(du_cmm, CMM_HGO_LB1_V, 0); -+ rcar_du_cmm_write(du_cmm, CMM_HGO_LB2_H, 0); -+ rcar_du_cmm_write(du_cmm, CMM_HGO_LB2_V, 0); -+ rcar_du_cmm_write(du_cmm, CMM_HGO_LB3_H, 0); -+ rcar_du_cmm_write(du_cmm, CMM_HGO_LB3_V, 0); ++ rcar_du_cmm_write(du_cmm, CM2_HGO_MODE, hgo->mode); ++ rcar_du_cmm_write(du_cmm, CM2_HGO_LB_TH, 0); ++ rcar_du_cmm_write(du_cmm, CM2_HGO_LB0_H, 0); ++ rcar_du_cmm_write(du_cmm, CM2_HGO_LB0_V, 0); ++ rcar_du_cmm_write(du_cmm, CM2_HGO_LB1_H, 0); ++ rcar_du_cmm_write(du_cmm, CM2_HGO_LB1_V, 0); ++ rcar_du_cmm_write(du_cmm, CM2_HGO_LB2_H, 0); ++ rcar_du_cmm_write(du_cmm, CM2_HGO_LB2_V, 0); ++ rcar_du_cmm_write(du_cmm, CM2_HGO_LB3_H, 0); ++ rcar_du_cmm_write(du_cmm, CM2_HGO_LB3_V, 0); + + cm2_ctl0 = du_cmm->reg_save.cm2_ctl0; -+ cm2_ctl0 &= ~CMM_CTL0_HISTS; ++ cm2_ctl0 &= ~CM2_CTL0_HISTS; + cm2_ctl0 |= hists; + + rcar_du_cmm_write(du_cmm, CM2_CTL0, cm2_ctl0); @@ -1276,8 +1263,8 @@ index 0000000..4856277 + if (!on) { + du_cmm->active = false; + -+ rcar_du_cmm_write(du_cmm, CMM_LUT_CTRL, 0x00000000); -+ rcar_du_cmm_write(du_cmm, CMM_CLU_CTRL, 0x00000000); ++ rcar_du_cmm_write(du_cmm, CM2_LUT_CTRL, 0x00000000); ++ rcar_du_cmm_write(du_cmm, CM2_CLU_CTRL, 0x00000000); + + du_cmm_clk(du_cmm, false); + @@ -1309,23 +1296,23 @@ index 0000000..4856277 + du_cmm->reg_save.hgo_size = (w << 16) | h; + + if (mode->flags & DRM_MODE_FLAG_PVSYNC) -+ du_cmm->reg_save.cm2_ctl0 |= CMM_CTL0_VPOL; ++ du_cmm->reg_save.cm2_ctl0 |= CM2_CTL0_VPOL; + else -+ du_cmm->reg_save.cm2_ctl0 &= ~CMM_CTL0_VPOL; ++ du_cmm->reg_save.cm2_ctl0 &= ~CM2_CTL0_VPOL; + + rcar_du_cmm_write(du_cmm, CM2_CTL0, du_cmm->reg_save.cm2_ctl0); -+ rcar_du_cmm_write(du_cmm, CMM_HGO_OFFSET, du_cmm->reg_save.hgo_offset); -+ rcar_du_cmm_write(du_cmm, CMM_HGO_SIZE, du_cmm->reg_save.hgo_size); -+ rcar_du_cmm_write(du_cmm, CMM_HGO_MODE, du_cmm->reg_save.hgo_mode); -+ rcar_du_cmm_write(du_cmm, CMM_HGO_LB_TH, 0); -+ rcar_du_cmm_write(du_cmm, CMM_HGO_LB0_H, 0); -+ rcar_du_cmm_write(du_cmm, CMM_HGO_LB0_V, 0); -+ rcar_du_cmm_write(du_cmm, CMM_HGO_LB1_H, 0); -+ rcar_du_cmm_write(du_cmm, CMM_HGO_LB1_V, 0); -+ rcar_du_cmm_write(du_cmm, CMM_HGO_LB2_H, 0); -+ rcar_du_cmm_write(du_cmm, CMM_HGO_LB2_V, 0); -+ rcar_du_cmm_write(du_cmm, CMM_HGO_LB3_H, 0); -+ rcar_du_cmm_write(du_cmm, CMM_HGO_LB3_V, 0); ++ rcar_du_cmm_write(du_cmm, CM2_HGO_OFFSET, du_cmm->reg_save.hgo_offset); ++ rcar_du_cmm_write(du_cmm, CM2_HGO_SIZE, du_cmm->reg_save.hgo_size); ++ rcar_du_cmm_write(du_cmm, CM2_HGO_MODE, du_cmm->reg_save.hgo_mode); ++ rcar_du_cmm_write(du_cmm, CM2_HGO_LB_TH, 0); ++ rcar_du_cmm_write(du_cmm, CM2_HGO_LB0_H, 0); ++ rcar_du_cmm_write(du_cmm, CM2_HGO_LB0_V, 0); ++ rcar_du_cmm_write(du_cmm, CM2_HGO_LB1_H, 0); ++ rcar_du_cmm_write(du_cmm, CM2_HGO_LB1_V, 0); ++ rcar_du_cmm_write(du_cmm, CM2_HGO_LB2_H, 0); ++ rcar_du_cmm_write(du_cmm, CM2_HGO_LB2_V, 0); ++ rcar_du_cmm_write(du_cmm, CM2_HGO_LB3_H, 0); ++ rcar_du_cmm_write(du_cmm, CM2_HGO_LB3_V, 0); + + /* init color table */ + for (i = 0; i < CMM_LUT_NUM; i++) { @@ -1334,19 +1321,19 @@ index 0000000..4856277 + #else + table_data = ((i << 16) | (i << 8) | (i << 0)); + #endif /* CONFIG_PM_SLEEP */ -+ rcar_du_cmm_write(du_cmm, CMM_LUT_TBLA(i), table_data); ++ rcar_du_cmm_write(du_cmm, CM2_LUT_TBL_A(i), table_data); + + if (du_cmm->dbuf) -+ rcar_du_cmm_write(du_cmm, CMM_LUT_TBLB(i), ++ rcar_du_cmm_write(du_cmm, CM2_LUT_TBL2_B(i), + table_data); + } + -+ rcar_du_cmm_write(du_cmm, CMM_CLU_CTRL, -+ CMM_CLU_CTRL_AAI | CMM_CLU_CTRL_MVS); ++ rcar_du_cmm_write(du_cmm, CM2_CLU_CTRL, ++ CM2_CLU_CTRL_AAI | CM2_CLU_CTRL_MVS); + -+ rcar_du_cmm_write(du_cmm, CMM_CLU_ADDR, 0); ++ rcar_du_cmm_write(du_cmm, CM2_CLU_ADDR, 0); + if (du_cmm->clu_dbuf) -+ rcar_du_cmm_write(du_cmm, CMM_CLU_ADDR2, 0); ++ rcar_du_cmm_write(du_cmm, CM2_CLU_ADDR2, 0); + + for (i = 0; i < CMM_CLU_NUM; i++) { + #ifdef CONFIG_PM_SLEEP @@ -1354,18 +1341,18 @@ index 0000000..4856277 + #else + table_data = index_to_clu_data(i); + #endif /* CONFIG_PM_SLEEP */ -+ rcar_du_cmm_write(du_cmm, CMM_CLU_DATA, table_data); ++ rcar_du_cmm_write(du_cmm, CM2_CLU_DATA, table_data); + + if (du_cmm->dbuf) -+ rcar_du_cmm_write(du_cmm, CMM_CLU_DATA2, ++ rcar_du_cmm_write(du_cmm, CM2_CLU_DATA2, + table_data); + } + +init_done: + /* enable color table */ -+ rcar_du_cmm_write(du_cmm, CMM_LUT_CTRL, CMM_LUT_CTRL_EN); -+ rcar_du_cmm_write(du_cmm, CMM_CLU_CTRL, CMM_CLU_CTRL_AAI | -+ CMM_CLU_CTRL_MVS | CMM_CLU_CTRL_EN); ++ rcar_du_cmm_write(du_cmm, CM2_LUT_CTRL, CM2_LUT_CTRL_EN); ++ rcar_du_cmm_write(du_cmm, CM2_CLU_CTRL, CM2_CLU_CTRL_AAI | ++ CM2_CLU_CTRL_MVS | CM2_CLU_CTRL_EN); + + du_cmm->active = true; +end: @@ -1529,12 +1516,12 @@ index 0000000..4856277 + int i; + u32 src, dst; + -+ if (rcar_du_cmm_read(du_cmm, CM2_CTL1) & CMM_CTL1_BFS) { -+ dst = CMM_LUT_TBLA(0); -+ src = CMM_LUT_TBLB(0); ++ if (rcar_du_cmm_read(du_cmm, CM2_CTL1) & CM2_CTL1_BFS) { ++ dst = CM2_LUT_TBL_A(0); ++ src = CM2_LUT_TBL2_B(0); + } else { -+ dst = CMM_LUT_TBLB(0); -+ src = CMM_LUT_TBLA(0); ++ dst = CM2_LUT_TBL2_B(0); ++ src = CM2_LUT_TBL_A(0); + } + + for (i = 0; i < CMM_LUT_NUM; i++) { @@ -1563,18 +1550,18 @@ index 0000000..4856277 + /* set LUT */ + switch (du_cmm->lut.buf_mode) { + case LUT_DOUBLE_BUFFER_A: -+ lut_base = CMM_LUT_TBLA(0); ++ lut_base = CM2_LUT_TBL_A(0); + break; + + case LUT_DOUBLE_BUFFER_AUTO: -+ if (rcar_du_cmm_read(du_cmm, CM2_CTL1) & CMM_CTL1_BFS) { -+ lut_base = CMM_LUT_TBLA(0); ++ if (rcar_du_cmm_read(du_cmm, CM2_CTL1) & CM2_CTL1_BFS) { ++ lut_base = CM2_LUT_TBL_A(0); + break; + } -+ lut_base = CMM_LUT_TBLB(0); ++ lut_base = CM2_LUT_TBL2_B(0); + break; + case LUT_DOUBLE_BUFFER_B: -+ lut_base = CMM_LUT_TBLB(0); ++ lut_base = CM2_LUT_TBL2_B(0); + break; + + default: @@ -1631,22 +1618,22 @@ index 0000000..4856277 + int i, j, k; + u32 src_addr, src_data, dst_addr, dst_data; + -+ if (rcar_du_cmm_read(du_cmm, CM2_CTL1) & CMM_CTL1_BFS) { -+ dst_addr = CMM_CLU_ADDR; -+ dst_data = CMM_CLU_DATA; -+ src_addr = CMM_CLU_ADDR2; -+ src_data = CMM_CLU_DATA2; ++ if (rcar_du_cmm_read(du_cmm, CM2_CTL1) & CM2_CTL1_BFS) { ++ dst_addr = CM2_CLU_ADDR; ++ dst_data = CM2_CLU_DATA; ++ src_addr = CM2_CLU_ADDR2; ++ src_data = CM2_CLU_DATA2; + } else { -+ dst_addr = CMM_CLU_ADDR2; -+ dst_data = CMM_CLU_DATA2; -+ src_addr = CMM_CLU_ADDR; -+ src_data = CMM_CLU_DATA; ++ dst_addr = CM2_CLU_ADDR2; ++ dst_data = CM2_CLU_DATA2; ++ src_addr = CM2_CLU_ADDR; ++ src_data = CM2_CLU_DATA; + } + + rcar_du_cmm_write(du_cmm, dst_addr, 0); -+ for (i = 0; i < 17; i++) { -+ for (j = 0; j < 17; j++) { -+ for (k = 0; k < 17; k++) { ++ for (i = 0; i < CMM_CLU_SAMPLES; i++) { ++ for (j = 0; j < CMM_CLU_SAMPLES; j++) { ++ for (k = 0; k < CMM_CLU_SAMPLES; k++) { + rcar_du_cmm_write(du_cmm, src_addr, + (k << 16) | (j << 8) | + (i << 0)); @@ -1677,22 +1664,22 @@ index 0000000..4856277 + /* set CLU */ + switch (du_cmm->clu.buf_mode) { + case CLU_DOUBLE_BUFFER_A: -+ addr_reg = CMM_CLU_ADDR; -+ data_reg = CMM_CLU_DATA; ++ addr_reg = CM2_CLU_ADDR; ++ data_reg = CM2_CLU_DATA; + break; + + case CLU_DOUBLE_BUFFER_AUTO: -+ if (rcar_du_cmm_read(du_cmm, CM2_CTL1) & CMM_CTL1_BFS) { -+ addr_reg = CMM_CLU_ADDR; -+ data_reg = CMM_CLU_DATA; ++ if (rcar_du_cmm_read(du_cmm, CM2_CTL1) & CM2_CTL1_BFS) { ++ addr_reg = CM2_CLU_ADDR; ++ data_reg = CM2_CLU_DATA; + break; + } -+ addr_reg = CMM_CLU_ADDR2; -+ data_reg = CMM_CLU_DATA2; ++ addr_reg = CM2_CLU_ADDR2; ++ data_reg = CM2_CLU_DATA2; + break; + case CLU_DOUBLE_BUFFER_B: -+ addr_reg = CMM_CLU_ADDR2; -+ data_reg = CMM_CLU_DATA2; ++ addr_reg = CM2_CLU_ADDR2; ++ data_reg = CM2_CLU_DATA2; + break; + + default: @@ -1737,9 +1724,9 @@ index 0000000..4856277 +{ + int i, j; + const u32 histo_offset[3] = { -+ CMM_HGO_R_HISTO(0), -+ CMM_HGO_G_HISTO(0), -+ CMM_HGO_B_HISTO(0), ++ CM2_HGO_R_HISTO(0), ++ CM2_HGO_G_HISTO(0), ++ CM2_HGO_B_HISTO(0), + }; + void *vaddr; + @@ -1762,7 +1749,7 @@ index 0000000..4856277 + event_done(stat->p2); + +hgo_reset: -+ rcar_du_cmm_write(du_cmm, CMM_HGO_REGRST, CMM_HGO_REGRST_RCLEA); ++ rcar_du_cmm_write(du_cmm, CM2_HGO_REGRST, CM2_HGO_REGRST_RCLEA); + + return 0; +} @@ -1848,9 +1835,7 @@ index 0000000..4856277 + hgo_time = (long)diff_timevals(&start_time, &end_time); +#endif + -+#ifdef CONFIG_PM_SLEEP + wake_up_interruptible(&du_cmm->reg_save.wait); -+#endif /* CONFIG_PM_SLEEP */ + +#ifdef DEBUG_PROCE_TIME + { @@ -1922,18 +1907,18 @@ index 0000000..4856277 + /* table save */ + for (i = 0; i < CMM_LUT_NUM; i++) { + du_cmm->reg_save.lut_table[i] = -+ rcar_du_cmm_read(du_cmm, CMM_LUT_TBLA(i)); ++ rcar_du_cmm_read(du_cmm, CM2_LUT_TBL_A(i)); + } + + index = 0; -+ for (i = 0; i < 17; i++) { -+ for (j = 0; j < 17; j++) { -+ for (k = 0; k < 17; k++) { -+ rcar_du_cmm_write(du_cmm, CMM_CLU_ADDR, ++ for (i = 0; i < CMM_CLU_SAMPLES; i++) { ++ for (j = 0; j < CMM_CLU_SAMPLES; j++) { ++ for (k = 0; k < CMM_CLU_SAMPLES; k++) { ++ rcar_du_cmm_write(du_cmm, CM2_CLU_ADDR, + (k << 16) | (j << 8) | + (i << 0)); + du_cmm->reg_save.clu_table[index++] = -+ rcar_du_cmm_read(du_cmm, CMM_CLU_DATA); ++ rcar_du_cmm_read(du_cmm, CM2_CLU_DATA); + } + } + } @@ -1966,7 +1951,7 @@ index 0000000..4856277 + if (unlikely(!fpriv)) + return -ENOMEM; + -+ fpriv->done_list = kcalloc(rcdu->info->num_crtcs, ++ fpriv->done_list = kcalloc(rcdu->num_crtcs, + sizeof(*fpriv->done_list), + GFP_KERNEL); + if (unlikely(!fpriv->done_list)) { @@ -1977,7 +1962,7 @@ index 0000000..4856277 + init_waitqueue_head(&fpriv->event_wait); + INIT_LIST_HEAD(&fpriv->list); + INIT_LIST_HEAD(&fpriv->active_list); -+ for (i = 0; i < rcdu->info->num_crtcs; i++) ++ for (i = 0; i < rcdu->num_crtcs; i++) + INIT_LIST_HEAD(&fpriv->done_list[i]); + + file_priv->driver_priv = fpriv; @@ -2039,42 +2024,30 @@ index 0000000..4856277 + if (ret == 0) + dev_err(rcdu->dev, "rcar-du cmm close : timeout\n"); + -+ for (i = 0; i < CMM_LUT_NUM; i++) -+ du_cmm->reg_save.lut_table[i] = (i << 16) | -+ (i << 8) | -+ (i << 0); -+ -+ for (i = 0; i < CMM_CLU_NUM; i++) { -+ du_cmm->reg_save.clu_table[i] = -+ index_to_clu_data(i); -+ } -+ + for (i = 0; i < CMM_LUT_NUM; i++) { -+#ifdef CONFIG_PM_SLEEP -+ table_data = du_cmm->reg_save.lut_table[i]; -+#else + table_data = ((i << 16) | (i << 8) | (i << 0)); ++#ifdef CONFIG_PM_SLEEP ++ du_cmm->reg_save.lut_table[i] = table_data; +#endif /* CONFIG_PM_SLEEP */ -+ rcar_du_cmm_write(du_cmm, CMM_LUT_TBLA(i), ++ rcar_du_cmm_write(du_cmm, CM2_LUT_TBL_A(i), + table_data); + if (du_cmm->dbuf) { + rcar_du_cmm_write(du_cmm, -+ CMM_LUT_TBLB(i), ++ CM2_LUT_TBL2_B(i), + table_data); + } + } + + for (i = 0; i < CMM_CLU_NUM; i++) { -+#ifdef CONFIG_PM_SLEEP -+ table_data = du_cmm->reg_save.clu_table[i]; -+#else + table_data = index_to_clu_data(i); ++#ifdef CONFIG_PM_SLEEP ++ du_cmm->reg_save.clu_table[i] = table_data; +#endif /* CONFIG_PM_SLEEP */ -+ rcar_du_cmm_write(du_cmm, CMM_CLU_DATA, ++ rcar_du_cmm_write(du_cmm, CM2_CLU_DATA, + table_data); + + if (du_cmm->dbuf) { -+ rcar_du_cmm_write(du_cmm, CMM_CLU_DATA2, ++ rcar_du_cmm_write(du_cmm, CM2_CLU_DATA2, + table_data); + } + } @@ -2086,7 +2059,9 @@ index 0000000..4856277 +{ + struct rcar_du_cmm *du_cmm; + int ret; ++#ifdef CONFIG_PM_SLEEP + int i; ++#endif + struct rcar_du_device *rcdu = rcrtc->group->dev; + char name[64]; + struct resource *mem; @@ -2133,23 +2108,23 @@ index 0000000..4856277 + du_cmm->dbuf = rcar_du_has(rcdu, RCAR_DU_FEATURE_CMM_LUT_DBUF); + if (du_cmm->dbuf) { + du_cmm->lut.buf_mode = LUT_DOUBLE_BUFFER_AUTO; -+ du_cmm->reg_save.cm2_ctl0 |= CMM_CTL0_DBUF; ++ du_cmm->reg_save.cm2_ctl0 |= CM2_CTL0_DBUF; + } else { + dev_err(rcdu->dev, "single buffer is not supported.\n"); + du_cmm->dbuf = true; + du_cmm->lut.buf_mode = LUT_DOUBLE_BUFFER_AUTO; -+ du_cmm->reg_save.cm2_ctl0 |= CMM_CTL0_DBUF; ++ du_cmm->reg_save.cm2_ctl0 |= CM2_CTL0_DBUF; + } + + du_cmm->clu_dbuf = rcar_du_has(rcdu, RCAR_DU_FEATURE_CMM_CLU_DBUF); + if (du_cmm->clu_dbuf) { + du_cmm->clu.buf_mode = CLU_DOUBLE_BUFFER_AUTO; -+ du_cmm->reg_save.cm2_ctl0 |= CMM_CTL0_CLUDB; ++ du_cmm->reg_save.cm2_ctl0 |= CM2_CTL0_CLUDB; + } else { + dev_err(rcdu->dev, "single buffer is not supported.\n"); + du_cmm->clu_dbuf = true; + du_cmm->clu.buf_mode = CLU_DOUBLE_BUFFER_AUTO; -+ du_cmm->reg_save.cm2_ctl0 |= CMM_CTL0_CLUDB; ++ du_cmm->reg_save.cm2_ctl0 |= CM2_CTL0_CLUDB; + } + +#ifdef CONFIG_PM_SLEEP @@ -2171,8 +2146,8 @@ index 0000000..4856277 + for (i = 0; i < CMM_CLU_NUM; i++) + du_cmm->reg_save.clu_table[i] = index_to_clu_data(i); + -+ init_waitqueue_head(&du_cmm->reg_save.wait); +#endif /* CONFIG_PM_SLEEP */ ++ init_waitqueue_head(&du_cmm->reg_save.wait); + if (soc_device_match(rcar_du_cmm_r8a7795_es1)) + du_cmm->soc_support = false; + else @@ -2215,10 +2190,10 @@ index 0000000..4856277 + return ret; +} diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c -index 6eae2b4..3e8d9eb 100644 +index 9b2558b..58809f3 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c -@@ -280,6 +280,19 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc) +@@ -294,6 +294,19 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc) rcar_du_crtc_write(rcrtc, HDSR, mode->htotal - mode->hsync_start - 19); rcar_du_crtc_write(rcrtc, HDER, mode->htotal - mode->hsync_start + mode->hdisplay - 19); @@ -2238,27 +2213,29 @@ index 6eae2b4..3e8d9eb 100644 rcar_du_crtc_write(rcrtc, HSWR, mode->hsync_end - mode->hsync_start - 1); rcar_du_crtc_write(rcrtc, HCR, mode->htotal - 1); -@@ -524,6 +537,9 @@ static void rcar_du_crtc_start(struct rcar_du_crtc *rcrtc) - rcar_du_lvdsenc_enable(rcdu->lvds[rcrtc->index], crtc, true); +@@ -600,6 +613,10 @@ static void rcar_du_crtc_start(struct rcar_du_crtc *rcrtc) + DSYSR_TVM_MASTER); rcar_du_group_start_stop(rcrtc->group, true); + -+ if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_CMM)) ++ if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_CMM) && ++ !rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_R8A7799X)) + rcar_du_cmm_start_stop(rcrtc, true); } static void rcar_du_crtc_disable_planes(struct rcar_du_crtc *rcrtc) -@@ -560,6 +576,9 @@ static void rcar_du_crtc_stop(struct rcar_du_crtc *rcrtc) - struct drm_crtc *crtc = &rcrtc->crtc; +@@ -636,6 +653,10 @@ static void rcar_du_crtc_stop(struct rcar_du_crtc *rcrtc) struct rcar_du_device *rcdu = rcrtc->group->dev; + struct drm_crtc *crtc = &rcrtc->crtc; -+ if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_CMM)) ++ if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_CMM) && ++ !rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_R8A7799X)) + rcar_du_cmm_start_stop(rcrtc, false); + /* * Disable all planes and wait for the change to take effect. This is * required as the plane enable registers are updated on vblank, and no -@@ -779,6 +798,9 @@ static irqreturn_t rcar_du_crtc_irq(int irq, void *arg) +@@ -1002,6 +1023,9 @@ static irqreturn_t rcar_du_crtc_irq(int irq, void *arg) rcar_du_crtc_finish_page_flip(rcrtc); } @@ -2268,7 +2245,7 @@ index 6eae2b4..3e8d9eb 100644 ret = IRQ_HANDLED; } -@@ -899,5 +921,7 @@ int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int index) +@@ -1120,5 +1144,7 @@ int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int swindex, return ret; } @@ -2277,19 +2254,18 @@ index 6eae2b4..3e8d9eb 100644 return 0; } diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.h b/drivers/gpu/drm/rcar-du/rcar_du_crtc.h -index e131e9f..65f45f4 100644 +index e3a48f9..ad8759e 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.h +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.h -@@ -69,6 +69,8 @@ struct rcar_du_crtc { +@@ -68,6 +68,7 @@ struct rcar_du_crtc { + struct rcar_du_group *group; + struct rcar_du_vsp *vsp; unsigned int vsp_pipe; - int lvds_ch; - bool extal_use; -+ + void *cmm_handle; }; #define to_rcar_crtc(c) container_of(c, struct rcar_du_crtc, crtc) -@@ -92,4 +94,34 @@ void rcar_du_crtc_route_output(struct drm_crtc *crtc, +@@ -105,4 +106,34 @@ void rcar_du_crtc_route_output(struct drm_crtc *crtc, enum rcar_du_output output); void rcar_du_crtc_finish_page_flip(struct rcar_du_crtc *rcrtc); @@ -2325,64 +2301,58 @@ index e131e9f..65f45f4 100644 + #endif /* __RCAR_DU_CRTC_H__ */ diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c -index a98e83c..50a9ad3 100644 +index b3ffa6f0..c9c44f2 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c -@@ -93,7 +93,8 @@ - static const struct rcar_du_device_info rcar_du_r8a7791_info = { - .gen = 2, - .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK -- | RCAR_DU_FEATURE_EXT_CTRL_REGS, -+ | RCAR_DU_FEATURE_EXT_CTRL_REGS -+ | RCAR_DU_FEATURE_CMM, - .num_crtcs = 2, - .routes = { - /* -@@ -157,7 +158,9 @@ - .gen = 3, - .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK +@@ -204,7 +204,10 @@ | RCAR_DU_FEATURE_EXT_CTRL_REGS -- | RCAR_DU_FEATURE_VSP1_SOURCE, -+ | RCAR_DU_FEATURE_VSP1_SOURCE -+ | RCAR_DU_FEATURE_CMM | RCAR_DU_FEATURE_CMM_LUT_DBUF + | RCAR_DU_FEATURE_VSP1_SOURCE + | RCAR_DU_FEATURE_R8A7795_REGS +- | RCAR_DU_FEATURE_TVM_SYNC, ++ | RCAR_DU_FEATURE_TVM_SYNC ++ | RCAR_DU_FEATURE_CMM ++ | RCAR_DU_FEATURE_CMM_LUT_DBUF + | RCAR_DU_FEATURE_CMM_CLU_DBUF, - .num_crtcs = 4, + .channels_mask = BIT(3) | BIT(2) | BIT(1) | BIT(0), .routes = { /* -@@ -189,7 +192,9 @@ - .gen = 3, - .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK +@@ -238,7 +241,10 @@ | RCAR_DU_FEATURE_EXT_CTRL_REGS -- | RCAR_DU_FEATURE_VSP1_SOURCE, -+ | RCAR_DU_FEATURE_VSP1_SOURCE -+ | RCAR_DU_FEATURE_CMM | RCAR_DU_FEATURE_CMM_LUT_DBUF + | RCAR_DU_FEATURE_VSP1_SOURCE + | RCAR_DU_FEATURE_R8A7796_REGS +- | RCAR_DU_FEATURE_TVM_SYNC, ++ | RCAR_DU_FEATURE_TVM_SYNC ++ | RCAR_DU_FEATURE_CMM ++ | RCAR_DU_FEATURE_CMM_LUT_DBUF + | RCAR_DU_FEATURE_CMM_CLU_DBUF, - .num_crtcs = 3, + .channels_mask = BIT(2) | BIT(1) | BIT(0), .routes = { /* -@@ -218,7 +223,9 @@ - .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK +@@ -268,7 +274,10 @@ | RCAR_DU_FEATURE_EXT_CTRL_REGS | RCAR_DU_FEATURE_VSP1_SOURCE -- | RCAR_DU_FEATURE_R8A77965_REGS, -+ | RCAR_DU_FEATURE_R8A77965_REGS -+ | RCAR_DU_FEATURE_CMM | RCAR_DU_FEATURE_CMM_LUT_DBUF + | RCAR_DU_FEATURE_R8A77965_REGS +- | RCAR_DU_FEATURE_TVM_SYNC, ++ | RCAR_DU_FEATURE_TVM_SYNC ++ | RCAR_DU_FEATURE_CMM ++ | RCAR_DU_FEATURE_CMM_LUT_DBUF + | RCAR_DU_FEATURE_CMM_CLU_DBUF, - .num_crtcs = 3, + .channels_mask = BIT(3) | BIT(1) | BIT(0), .routes = { - /* R8A77965 has one RGB output, one LVDS output and one -@@ -275,7 +282,9 @@ + /* +@@ -318,7 +327,10 @@ + .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK | RCAR_DU_FEATURE_EXT_CTRL_REGS | RCAR_DU_FEATURE_VSP1_SOURCE - | RCAR_DU_FEATURE_R8A77990_REGS -- | RCAR_DU_FEATURE_LVDS_PLL, -+ | RCAR_DU_FEATURE_LVDS_PLL -+ | RCAR_DU_FEATURE_CMM | RCAR_DU_FEATURE_CMM_LUT_DBUF +- | RCAR_DU_FEATURE_R8A7799X, ++ | RCAR_DU_FEATURE_R8A7799X ++ | RCAR_DU_FEATURE_CMM ++ | RCAR_DU_FEATURE_CMM_LUT_DBUF + | RCAR_DU_FEATURE_CMM_CLU_DBUF, - .num_crtcs = 2, + .channels_mask = BIT(1) | BIT(0), .routes = { - /* R8A77990 has two LVDS output and one RGB output. -@@ -329,6 +338,26 @@ static void rcar_du_lastclose(struct drm_device *dev) + /* +@@ -378,6 +390,26 @@ static void rcar_du_lastclose(struct drm_device *dev) DRM_UNLOCKED | DRM_CONTROL_ALLOW), DRM_IOCTL_DEF_DRV(RCAR_DU_SCRSHOT, rcar_du_vsp_write_back, DRM_UNLOCKED | DRM_CONTROL_ALLOW), @@ -2409,7 +2379,7 @@ index a98e83c..50a9ad3 100644 }; DEFINE_DRM_GEM_CMA_FOPS(rcar_du_fops); -@@ -336,6 +365,8 @@ static void rcar_du_lastclose(struct drm_device *dev) +@@ -385,6 +417,8 @@ static void rcar_du_lastclose(struct drm_device *dev) static struct drm_driver rcar_du_driver = { .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME | DRIVER_ATOMIC, @@ -2418,7 +2388,7 @@ index a98e83c..50a9ad3 100644 .lastclose = rcar_du_lastclose, .gem_free_object_unlocked = drm_gem_cma_free_object, .gem_vm_ops = &drm_gem_cma_vm_ops, -@@ -371,6 +402,12 @@ static int rcar_du_pm_shutdown(struct device *dev) +@@ -420,6 +454,12 @@ static int rcar_du_pm_shutdown(struct device *dev) #if IS_ENABLED(CONFIG_DRM_RCAR_DW_HDMI) struct drm_encoder *encoder; #endif @@ -2431,7 +2401,7 @@ index a98e83c..50a9ad3 100644 drm_kms_helper_poll_disable(rcdu->ddev); drm_fbdev_cma_set_suspend_unlocked(rcdu->fbdev, true); -@@ -418,6 +455,12 @@ static int rcar_du_pm_resume(struct device *dev) +@@ -467,6 +507,12 @@ static int rcar_du_pm_resume(struct device *dev) struct rcar_du_device *rcdu = dev_get_drvdata(dev); #if IS_ENABLED(CONFIG_DRM_RCAR_DW_HDMI) struct drm_encoder *encoder; @@ -2445,33 +2415,28 @@ index a98e83c..50a9ad3 100644 list_for_each_entry(encoder, &rcdu->ddev->mode_config.encoder_list, diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.h b/drivers/gpu/drm/rcar-du/rcar_du_drv.h -index bb3fb3d..4cf35f8 100644 +index 504a188..2598d4d 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.h +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.h -@@ -36,8 +36,16 @@ - #define RCAR_DU_FEATURE_LVDS_PLL (1 << 5) /* Use PLL in LVDS */ - #define RCAR_DU_FEATURE_R8A77990_REGS (1 << 6) /* Use R8A77990 registers */ +@@ -38,6 +38,13 @@ + #define RCAR_DU_FEATURE_TVM_SYNC (1 << 8) /* Has TV switch/sync modes */ + #define RCAR_DU_FEATURE_R8A7799X (1 << 9) /* Use R8A7799X */ --#define RCAR_DU_QUIRK_ALIGN_128B (1 << 0) /* Align pitches to 128 bytes */ --#define RCAR_DU_QUIRK_LVDS_LANES (1 << 1) /* LVDS lanes 1 and 3 inverted */ +/* Has DEF7R register & CMM */ +#define RCAR_DU_FEATURE_CMM BIT(10) +/* Has CMM LUT Double buffer */ +#define RCAR_DU_FEATURE_CMM_LUT_DBUF BIT(11) +/* Has CMM CLU Double buffer */ +#define RCAR_DU_FEATURE_CMM_CLU_DBUF BIT(12) -+/* Align pitches to 128 bytes */ -+#define RCAR_DU_QUIRK_ALIGN_128B BIT(0) -+/* LVDS lanes 1 and 3 inverted */ -+#define RCAR_DU_QUIRK_LVDS_LANES BIT(1) ++ + #define RCAR_DU_QUIRK_ALIGN_128B (1 << 0) /* Align pitches to 128 bytes */ /* - * struct rcar_du_output_routing - Output routing specification diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c b/drivers/gpu/drm/rcar-du/rcar_du_group.c -index df407f4..321abb4 100644 +index 9309df5..f119dbe 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_group.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c -@@ -147,6 +147,11 @@ static void rcar_du_group_setup(struct rcar_du_group *rgrp) +@@ -234,6 +234,11 @@ static void rcar_du_group_setup(struct rcar_du_group *rgrp) if (rcdu->info->gen >= 3) rcar_du_group_write(rgrp, DEFR10, DEFR10_CODE | DEFR10_DEFE10); @@ -2484,7 +2449,7 @@ index df407f4..321abb4 100644 * Use DS1PR and DS2PR to configure planes priorities and connects the * superposition 0 to DU0 pins. DU1 pins will be configured dynamically. diff --git a/drivers/gpu/drm/rcar-du/rcar_du_regs.h b/drivers/gpu/drm/rcar-du/rcar_du_regs.h -index 89d3024..e5aae46 100644 +index 1b1390e..4178db2 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_regs.h +++ b/drivers/gpu/drm/rcar-du/rcar_du_regs.h @@ -200,6 +200,11 @@ @@ -2499,7 +2464,7 @@ index 89d3024..e5aae46 100644 /* ----------------------------------------------------------------------------- * R8A7790-only Control Registers */ -@@ -553,4 +558,91 @@ +@@ -553,4 +558,89 @@ #define GCBCR 0x11098 #define BCBCR 0x1109c @@ -2507,90 +2472,140 @@ index 89d3024..e5aae46 100644 + * DU Color Management Module Registers + */ + -+#define CMM_LUT_CTRL 0x0000 -+#define CMM_LUT_CTRL_EN BIT(0) -+ -+#define CMM_CLU_CTRL 0x0100 -+#define CMM_CLU_CTRL_EN BIT(0) -+#define CMM_CLU_CTRL_MVS BIT(24) -+#define CMM_CLU_CTRL_AAI BIT(28) -+ -+#define CMM_CTL0 0x0180 -+#define CM2_CTL0 CMM_CTL0 -+#define CMM_CTL0_CLUDB BIT(24) -+#define CMM_CTL0_HISTS BIT(20) -+#define CMM_CTL0_TM1_MASK (3 << 16) -+#define CMM_CTL0_TM1_BT601_YC240 (0 << 16) -+#define CMM_CTL0_TM1_BT601_YC255 BIT(16) -+#define CMM_CTL0_TM1_BT709_RG255 (2 << 16) -+#define CMM_CTL0_TM1_BT709_RG235 (3 << 16) -+#define CMM_CTL0_TM0_MASK (3 << 12) -+#define CMM_CTL0_TM0_BT601_YC240 (0 << 12) -+#define CMM_CTL0_TM0_BT601_YC255 BIT(12) -+#define CMM_CTL0_TM0_BT709_RG255 (2 << 12) -+#define CMM_CTL0_TM0_BT709_RG235 (3 << 12) -+#define CMM_CTL0_TM_BT601_YC240 (CMM_CTL0_TM1_BT601_YC240 |\ -+ CMM_CTL0_TM0_BT601_YC240) -+#define CMM_CTL0_TM_BT601_YC255 (CMM_CTL0_TM1_BT601_YC255 |\ -+ CMM_CTL0_TM0_BT601_YC255) -+#define CMM_CTL0_TM_BT709_RG255 (CMM_CTL0_TM1_BT709_RG255 |\ -+ CMM_CTL0_TM0_BT709_RG255) -+#define CMM_CTL0_TM_BT709_RG235 (CMM_CTL0_TM1_BT709_RG235 |\ -+ CMM_CTL0_TM0_BT709_RG235) -+#define CMM_CTL0_YC BIT(8) -+#define CMM_CTL0_VPOL BIT(4) -+#define CMM_CTL0_DBUF BIT(0) -+ -+#define CMM_CTL1 0x0184 -+#define CM2_CTL1 CMM_CTL1 -+#define CMM_CTL1_BFS BIT(0) -+ -+#define CMM_CTL2 0x0188 -+#define CMM_HGO_OFFSET 0x0200 -+#define CMM_HGO_SIZE 0x0204 -+#define CMM_HGO_MODE 0x0208 -+#define CMM_HGO_MODE_MASK (0xFF) -+#define CMM_HGO_MODE_MAXRGB BIT(7) -+#define CMM_HGO_MODE_OFSB_R BIT(6) -+#define CMM_HGO_MODE_OFSB_G BIT(5) -+#define CMM_HGO_MODE_OFSB_B BIT(4) -+#define CMM_HGO_MODE_HRATIO_NO_SKIPP (0 << 2) -+#define CMM_HGO_MODE_HRATIO_HALF_SKIPP BIT(2) -+#define CMM_HGO_MODE_HRATIO_QUARTER_SKIPP (2 << 2) -+#define CMM_HGO_MODE_VRATIO_NO_SKIPP (0 << 0) -+#define CMM_HGO_MODE_VRATIO_HALF_SKIPP BIT(0) -+#define CMM_HGO_MODE_VRATIO_QUARTER_SKIPP (2 << 0) -+#define CMM_HGO_LB_TH 0x020C -+#define CMM_HGO_LB0_H 0x0210 -+#define CMM_HGO_LB0_V 0x0214 -+#define CMM_HGO_LB1_H 0x0218 -+#define CMM_HGO_LB1_V 0x021C -+#define CMM_HGO_LB2_H 0x0220 -+#define CMM_HGO_LB2_V 0x0224 -+#define CMM_HGO_LB3_H 0x0228 -+#define CMM_HGO_LB3_V 0x022C -+#define CMM_HGO_R_HISTO(n) (0x0230 + ((n) * 4)) -+#define CMM_HGO_R_MAXMIN 0x0330 -+#define CMM_HGO_R_SUM 0x0334 -+#define CMM_HGO_R_LB_DET 0x0338 -+#define CMM_HGO_G_HISTO(n) (0x0340 + ((n) * 4)) -+#define CMM_HGO_G_MAXMIN 0x0440 -+#define CMM_HGO_G_SUM 0x0444 -+#define CMM_HGO_G_LB_DET 0x0448 -+#define CMM_HGO_B_HISTO(n) (0x0450 + ((n) * 4)) -+#define CMM_HGO_B_MAXMIN 0x0550 -+#define CMM_HGO_B_SUM 0x0554 -+#define CMM_HGO_B_LB_DET 0x0558 -+#define CMM_HGO_REGRST 0x05FC -+#define CMM_HGO_REGRST_RCLEA BIT(0) -+#define CMM_LUT_TBLA(n) (0x0600 + ((n) * 4)) -+#define CMM_CLU_ADDR 0x0A00 -+#define CMM_CLU_DATA 0x0A04 -+#define CMM_LUT_TBLB(n) (0x0B00 + ((n) * 4)) -+#define CMM_CLU_ADDR2 0x0F00 -+#define CMM_CLU_DATA2 0x0F04 ++#define CM2_LUT_CTRL 0x0000 ++#define CM2_LUT_CTRL_EN BIT(0) ++ ++#define CM2_CLU_CTRL 0x0100 ++#define CM2_CLU_CTRL_EN BIT(0) ++#define CM2_CLU_CTRL_MVS BIT(24) ++#define CM2_CLU_CTRL_AAI BIT(28) ++ ++#define CM2_CTL0 0x0180 ++#define CM2_CTL0_CLUDB BIT(24) ++#define CM2_CTL0_HISTS BIT(20) ++#define CM2_CTL0_TM1_MASK (3 << 16) ++#define CM2_CTL0_TM1_BT601_YC240 (0 << 16) ++#define CM2_CTL0_TM1_BT601_YC255 BIT(16) ++#define CM2_CTL0_TM1_BT709_RG255 (2 << 16) ++#define CM2_CTL0_TM1_BT709_RG235 (3 << 16) ++#define CM2_CTL0_TM0_MASK (3 << 12) ++#define CM2_CTL0_TM0_BT601_YC240 (0 << 12) ++#define CM2_CTL0_TM0_BT601_YC255 BIT(12) ++#define CM2_CTL0_TM0_BT709_RG255 (2 << 12) ++#define CM2_CTL0_TM0_BT709_RG235 (3 << 12) ++#define CM2_CTL0_TM_BT601_YC240 (CM2_CTL0_TM1_BT601_YC240 |\ ++ CM2_CTL0_TM0_BT601_YC240) ++#define CM2_CTL0_TM_BT601_YC255 (CM2_CTL0_TM1_BT601_YC255 |\ ++ CM2_CTL0_TM0_BT601_YC255) ++#define CM2_CTL0_TM_BT709_RG255 (CM2_CTL0_TM1_BT709_RG255 |\ ++ CM2_CTL0_TM0_BT709_RG255) ++#define CM2_CTL0_TM_BT709_RG235 (CM2_CTL0_TM1_BT709_RG235 |\ ++ CM2_CTL0_TM0_BT709_RG235) ++#define CM2_CTL0_YC BIT(8) ++#define CM2_CTL0_VPOL BIT(4) ++#define CM2_CTL0_DBUF BIT(0) ++ ++#define CM2_CTL1 0x0184 ++#define CM2_CTL1_BFS BIT(0) ++ ++#define CM2_CTL2 0x0188 ++#define CM2_HGO_OFFSET 0x0200 ++#define CM2_HGO_SIZE 0x0204 ++#define CM2_HGO_MODE 0x0208 ++#define CM2_HGO_MODE_MASK (0xFF) ++#define CM2_HGO_MODE_MAXRGB BIT(7) ++#define CM2_HGO_MODE_OFSB_R BIT(6) ++#define CM2_HGO_MODE_OFSB_G BIT(5) ++#define CM2_HGO_MODE_OFSB_B BIT(4) ++#define CM2_HGO_MODE_HRATIO_NO_SKIPP (0 << 2) ++#define CM2_HGO_MODE_HRATIO_HALF_SKIPP BIT(2) ++#define CM2_HGO_MODE_HRATIO_QUARTER_SKIPP (2 << 2) ++#define CM2_HGO_MODE_VRATIO_NO_SKIPP (0 << 0) ++#define CM2_HGO_MODE_VRATIO_HALF_SKIPP BIT(0) ++#define CM2_HGO_MODE_VRATIO_QUARTER_SKIPP (2 << 0) ++#define CM2_HGO_LB_TH 0x020C ++#define CM2_HGO_LB0_H 0x0210 ++#define CM2_HGO_LB0_V 0x0214 ++#define CM2_HGO_LB1_H 0x0218 ++#define CM2_HGO_LB1_V 0x021C ++#define CM2_HGO_LB2_H 0x0220 ++#define CM2_HGO_LB2_V 0x0224 ++#define CM2_HGO_LB3_H 0x0228 ++#define CM2_HGO_LB3_V 0x022C ++#define CM2_HGO_R_HISTO(n) (0x0230 + ((n) * 4)) ++#define CM2_HGO_R_MAXMIN 0x0330 ++#define CM2_HGO_R_SUM 0x0334 ++#define CM2_HGO_R_LB_DET 0x0338 ++#define CM2_HGO_G_HISTO(n) (0x0340 + ((n) * 4)) ++#define CM2_HGO_G_MAXMIN 0x0440 ++#define CM2_HGO_G_SUM 0x0444 ++#define CM2_HGO_G_LB_DET 0x0448 ++#define CM2_HGO_B_HISTO(n) (0x0450 + ((n) * 4)) ++#define CM2_HGO_B_MAXMIN 0x0550 ++#define CM2_HGO_B_SUM 0x0554 ++#define CM2_HGO_B_LB_DET 0x0558 ++#define CM2_HGO_REGRST 0x05FC ++#define CM2_HGO_REGRST_RCLEA BIT(0) ++#define CM2_LUT_TBL_A(n) (0x0600 + ((n) * 4)) ++#define CM2_CLU_ADDR 0x0A00 ++#define CM2_CLU_DATA 0x0A04 ++#define CM2_LUT_TBL2_B(n) (0x0B00 + ((n) * 4)) ++#define CM2_CLU_ADDR2 0x0F00 ++#define CM2_CLU_DATA2 0x0F04 + #endif /* __RCAR_DU_REGS_H__ */ +diff --git a/drivers/gpu/drm/rcar-du/rcar_lvds.c b/drivers/gpu/drm/rcar-du/rcar_lvds.c +index 58a611f..12b9191 100644 +--- a/drivers/gpu/drm/rcar-du/rcar_lvds.c ++++ b/drivers/gpu/drm/rcar-du/rcar_lvds.c +@@ -25,6 +25,8 @@ + #include + + #include "rcar_lvds_regs.h" ++#include "rcar_du_crtc.h" ++#include "rcar_du_drv.h" + + struct rcar_lvds; + +@@ -453,6 +455,7 @@ static void rcar_lvds_enable(struct drm_bridge *bridge) + * do we get a state pointer? + */ + struct drm_crtc *crtc = lvds->bridge.encoder->crtc; ++ struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc); + u32 lvdhcr; + u32 lvdcr0; + int ret; +@@ -549,6 +552,10 @@ static void rcar_lvds_enable(struct drm_bridge *bridge) + rcar_lvds_write(lvds, LVDCR0, lvdcr0); + + dual_link: ++ if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_CMM) && ++ (lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)) ++ rcar_du_cmm_start_stop(rcrtc, true); ++ + if (lvds->panel) { + drm_panel_prepare(lvds->panel); + drm_panel_enable(lvds->panel); +@@ -560,6 +567,8 @@ static void rcar_lvds_enable(struct drm_bridge *bridge) + static void __rcar_lvds_disable(struct drm_bridge *bridge) + { + struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge); ++ struct drm_crtc *crtc = lvds->bridge.encoder->crtc; ++ struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc); + u32 lvdcr0 = 0; + + WARN_ON(!lvds->enabled); +@@ -569,6 +578,10 @@ static void __rcar_lvds_disable(struct drm_bridge *bridge) + drm_panel_unprepare(lvds->panel); + } + ++ if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_CMM) && ++ (lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)) ++ rcar_du_cmm_start_stop(rcrtc, false); ++ + if (lvds->info->quirks & RCAR_LVDS_QUIRK_DUAL_LINK && + lvds->link_mode == RCAR_LVDS_DUAL) { + struct rcar_lvds *lvds_pair; diff --git a/include/uapi/drm/rcar_du_drm.h b/include/uapi/drm/rcar_du_drm.h index 712b729..1f29aca 100644 --- a/include/uapi/drm/rcar_du_drm.h diff --git a/meta-rcar-gen3/recipes-kernel/linux/linux-renesas_4.14.bbappend b/meta-rcar-gen3/recipes-kernel/linux/linux-renesas_4.14.bbappend index 2d30e6d..825831d 100644 --- a/meta-rcar-gen3/recipes-kernel/linux/linux-renesas_4.14.bbappend +++ b/meta-rcar-gen3/recipes-kernel/linux/linux-renesas_4.14.bbappend @@ -1,3 +1,4 @@ -SRC_URI_append_salvator-x += " \ +SRC_URI += " \ file://0001-drm-rcar-du-Add-DU-CMM-support.patch \ " + diff --git a/rcar_du_drm.h b/rcar_du_drm.h index 893ef00..4b06198 100644 --- a/rcar_du_drm.h +++ b/rcar_du_drm.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2017 Renesas Electronics Corporation + * Copyright (c) 2016-2018 Renesas Electronics Corporation * Released under the MIT license * http://opensource.org/licenses/mit-license.php */ @@ -7,13 +7,14 @@ #ifndef __RCAR_DU_DRM_H__ #define __RCAR_DU_DRM_H__ +/* DRM_RCAR_DU_CMM_SET_LUT, DU-CMM set LUT */ /* DRM_RCAR_DU_CMM_SET_CLU: DU-CMM set CLU */ /* DRM_RCAR_DU_CMM_GET_HGO: DU-CMM get histogram */ struct rcar_du_cmm_table { unsigned int crtc_id; unsigned int buff; /* set DRM_RCAR_DU_CMM_ALLOC handle */ unsigned int buff_len; - unsigned long user_data; + uint64_t user_data; }; /* DRM_RCAR_DU_CMM_SET_HGO: DU-CMM set HGO */ @@ -31,15 +32,16 @@ struct rcar_du_cmm_hgo_config { struct rcar_du_cmm_event { unsigned int crtc_id; unsigned int event; - unsigned long callback_data; + uint64_t callback_data; }; /* DRM_RCAR_DU_CMM_CONFIG: DU-CMM set config */ struct rcar_du_cmm_config { unsigned int crtc_id; - int csc; - int lut_buf; - int clu_buf; + unsigned int csc; + unsigned int lut_buf; + unsigned int clu_buf; + bool authority; }; /* DRM_RCAR_DU_CMM_ALLOC: DU-CMM alloc cma buffer */ @@ -48,7 +50,7 @@ struct rcar_du_cmm_buf { size_t size; /* in */ uint64_t mmap_offset; /* out */ uint64_t phy_addr; /* out */ - uint32_t handle; /* out */ + unsigned int handle; /* out */ }; /* DRM_RCAR_DU_CMM_WAIT_EVENT: DU-CMM done event */ @@ -81,12 +83,10 @@ struct rcar_du_cmm_buf { #define LUT_DOUBLE_BUFFER_AUTO 0 #define LUT_DOUBLE_BUFFER_A 1 #define LUT_DOUBLE_BUFFER_B 2 -#define LUT_SINGLE_BUFFER 3 #define CLU_DOUBLE_BUFFER_AUTO 0 #define CLU_DOUBLE_BUFFER_A 1 #define CLU_DOUBLE_BUFFER_B 2 -#define CLU_SINGLE_BUFFER 3 /* rcar-du + vspd specific ioctls */ /* DU-CMM ioctl */