From 31da1bafdfb30e856ede06fdd5181002c90a97c6 Mon Sep 17 00:00:00 2001 From: Alasdair Date: Mon, 11 Dec 2023 16:10:08 +0000 Subject: [PATCH] Rename and add Arm v9.4 config --- configs/aarch64_macos.toml | 199 -------------- configs/{aarch64.toml => armv8p5.toml} | 0 ...arch64_mmu_on.toml => armv8p5_mmu_on.toml} | 0 configs/armv9_macos_mmu_on.toml | 253 ------------------ configs/{armv9.toml => armv9p3.toml} | 0 ...{armv9_mmu_on.toml => armv9p3_mmu_on.toml} | 0 configs/{armv9_macos.toml => armv9p4.toml} | 175 +++++++----- 7 files changed, 113 insertions(+), 514 deletions(-) delete mode 100644 configs/aarch64_macos.toml rename configs/{aarch64.toml => armv8p5.toml} (100%) rename configs/{aarch64_mmu_on.toml => armv8p5_mmu_on.toml} (100%) delete mode 100644 configs/armv9_macos_mmu_on.toml rename configs/{armv9.toml => armv9p3.toml} (100%) rename configs/{armv9_mmu_on.toml => armv9p3_mmu_on.toml} (100%) rename configs/{armv9_macos.toml => armv9p4.toml} (50%) diff --git a/configs/aarch64_macos.toml b/configs/aarch64_macos.toml deleted file mode 100644 index f61aefe6..00000000 --- a/configs/aarch64_macos.toml +++ /dev/null @@ -1,199 +0,0 @@ -# This is a config file for the Sail generated from ARM-ASL - -pc = "_PC" - -translation_function = "AArch64_TranslateAddress" - -# The assembler is used for assembling the code in litmus tests. We -# assume it takes arguments like GNU as. -assembler = "as --target=aarch64-unknown-linux-gnu" -objdump = "/opt/homebrew/opt/llvm/bin/llvm-objdump" -linker = "/opt/homebrew/opt/llvm/bin/ld.lld" - -in_program_order = ["sail_barrier"] - -[mmu] -page_table_base = "0x300000" -page_size = "4096" -s2_page_table_base = "0x200000" -s2_page_size = "4096" - -# This section contains the base address for loading the code for each -# thread in a litmus test, and the stride which is the distance -# between each thread in bytes. The overall range for thread memory is -# the half-open range [base,top)" -[threads] -base = "0x400000" -top = "0x500000" -stride = "0x1000" - -# If we want to give symbolic addresses concrete values, then we start -# with a base address and increment by stride for each new symbolic -# address. -[symbolic_addrs] -base = "0x600000" -top = "0x700000" -stride = "0x10" - -[registers] -ignore = [ - "_PC", - "__PC_changed", - "SEE", - "__unconditional", - "__trickbox_enabled", - "__v81_implemented", - "__v82_implemented", - "__v83_implemented", - "__v84_implemented", - "__v85_implemented" -] - -# These registers are set before any symbolic execution occurs -[registers.defaults] -"__isla_vector_gpr" = false -"__isla_continue_on_see" = true -"__monomorphize_reads" = false -"__monomorphize_writes" = false -"VBAR_EL1" = "0x0000000000000000" -"VBAR_EL2" = "0x0000000000000000" -# Causes CNTCV to be incremented every cycle if bit 0 is 1 -"CNTCR" = "0x00000001" -# SSAdvance? -"MDSCR_EL1" = "0x00000000" -"InGuardedPage" = false -"__highest_el_aarch32" = false -"__currentInstrLength" = 4 -"_PendingPhysicalSE" = false -"__CNTControlBase" = "0x0000000000000" -"HCR_EL2" = "0x0000000000000000" -"TCR_EL1" = "0x0000000000000000" -"TCR_EL2" = "0x0000000000000000" -"TCR_EL3" = "0x00000000" -"TLBHits" = 0 -"TLBMisses" = 0 -"CFG_RMR_AA64" = "0b1" -"CFG_RVBAR" = "0x0000000010300000" -"CFG_ID_AA64PFR0_EL1_MPAM" = "0x1" -"CFG_ID_AA64PFR0_EL1_EL3" = "0x1" -"CFG_ID_AA64PFR0_EL1_EL2" = "0x1" -"CFG_ID_AA64PFR0_EL1_EL1" = "0x1" -"CFG_ID_AA64PFR0_EL1_EL0" = "0x1" -# Need to investigate BTI extension. Guard pages cause problems with -# memory accesses. -"__v81_implemented" = true -"__v82_implemented" = false -"__v83_implemented" = false -"__v84_implemented" = false -"__v85_implemented" = false -"__unpred_tsize_aborts" = true -# Trickbox has various features for debugging spec and running tests -"__trickbox_enabled" = false -"__tlb_enabled" = false -"__syncAbortOnTTWNonCache" = true -"__syncAbortOnTTWCache" = true -"__syncAbortOnSoWrite" = true -"__syncAbortOnSoRead" = true -"__syncAbortOnReadNormNonCache" = true -"__syncAbortOnReadNormCache" = true -"__syncAbortOnPrefetch" = true -"__syncAbortOnDeviceRead" = true -"__support_52bit_pa" = true -"__mte_implemented" = false -"__mpam_has_hcr" = true -"__vmid16_implemented" = true -"__pan_implemented" = true -"__fp16_implemented" = true -"__dot_product_implemented" = true -"__crc32_implemented" = true -"__aa32_hpd_implemented" = true -"__crypto_aes_implemented" = 2 -"__crypto_sha256_implemented" = true -"__crypto_sha1_implemented" = true -"__syncAbortOnWriteNormNonCache" = false -"__syncAbortOnWriteNormCache" = false -"__syncAbortOnDeviceWrite" = false -"__mpam_implemented" = false -"__crypto_sm4_implemented" = false -"__crypto_sm3_implemented" = false -"__crypto_sha512_implemented" = false -"__crypto_sha3_implemented" = false -"_GTEExtObsAccess" = "[0x0000; 256]" -"_GTEExtObsAddress" = "[0x0000000000000000; 256]" -"_GTEExtObsData" = "[0x0000000000000000; 256]" -"_GTEExtObsResult" = "[0x0000000000000000; 256]" -"_GTE_PPU_SizeEn" = "[0x00000000; 6]" -"_GTE_PPU_Address" = "[0x0000000000000000; 6]" -"_GTE_PPU_Access" = "[0x00000000; 6]" - -# These registers are set during symbolic execution by the special builtin "reset_registers" -[registers.reset] -# Bit 1 being unset allows unaligned accesses -# Bit 26 being set allows cache-maintenance ops in EL0 -"SCTLR_EL1" = "0x0000000004000000" - -# A map from register names that may appear in litmus files to Sail -# register names -[registers.renames] -"X0" = "R0" -"X1" = "R1" -"X2" = "R2" -"X3" = "R3" -"X4" = "R4" -"X5" = "R5" -"X6" = "R6" -"X7" = "R7" -"X8" = "R8" -"X9" = "R9" -"X10" = "R10" -"X11" = "R11" -"X12" = "R12" -"X13" = "R13" -"X14" = "R14" -"X15" = "R15" -"X16" = "R16" -"X17" = "R17" -"X18" = "R18" -"X19" = "R19" -"X20" = "R20" -"X21" = "R21" -"X22" = "R22" -"X23" = "R23" -"X24" = "R24" -"X25" = "R25" -"X26" = "R26" -"X27" = "R27" -"X28" = "R28" -"X29" = "R29" -"X30" = "R30" -"W0" = "R0" -"W1" = "R1" -"W2" = "R2" -"W3" = "R3" -"W4" = "R4" -"W5" = "R5" -"W6" = "R6" -"W7" = "R7" -"W8" = "R8" -"W9" = "R9" -"W10" = "R10" -"W11" = "R11" -"W12" = "R12" -"W13" = "R13" -"W14" = "R14" -"W15" = "R15" -"W16" = "R16" -"W17" = "R17" -"W18" = "R18" -"W19" = "R19" -"W20" = "R20" -"W21" = "R21" -"W22" = "R22" -"W23" = "R23" -"W24" = "R24" -"W25" = "R25" -"W26" = "R26" -"W27" = "R27" -"W28" = "R28" -"W29" = "R29" -"W30" = "R30" diff --git a/configs/aarch64.toml b/configs/armv8p5.toml similarity index 100% rename from configs/aarch64.toml rename to configs/armv8p5.toml diff --git a/configs/aarch64_mmu_on.toml b/configs/armv8p5_mmu_on.toml similarity index 100% rename from configs/aarch64_mmu_on.toml rename to configs/armv8p5_mmu_on.toml diff --git a/configs/armv9_macos_mmu_on.toml b/configs/armv9_macos_mmu_on.toml deleted file mode 100644 index 64c4ce08..00000000 --- a/configs/armv9_macos_mmu_on.toml +++ /dev/null @@ -1,253 +0,0 @@ -# This is a config file for the Sail generated from ARM-ASL - -pc = "_PC" - -translation_function = "AArch64_TranslateAddress" - -# The assembler is used for assembling the code in litmus tests. We -# assume it takes arguments like GNU as. -assembler = "as --target=aarch64-unknown-linux-gnu" -objdump = "/opt/homebrew/opt/llvm/bin/llvm-objdump" -linker = "/opt/homebrew/opt/llvm/bin/ld.lld" - -in_program_order = ["sail_barrier"] - -# litmus variables have type uint32_t by default -default_sizeof = 4 - -[mmu] -page_table_base = "0x300000" -page_size = "4096" -s2_page_table_base = "0x200000" -s2_page_size = "4096" - -default_setup = """ -let PAGE(x) = x[48 .. 12]; -let PAGEOFF(x) = x[11 .. 0]; -""" - -# This section contains the base address for loading the code for each -# thread in a litmus test, and the stride which is the distance -# between each thread in bytes. The overall range for thread memory is -# the half-open range [base,top)" -[threads] -base = "0x400000" -top = "0x500000" -stride = "0x1000" - -# If we want to give symbolic addresses concrete values, then we start -# with a base address and increment by stride for each new symbolic -# address. -[symbolic_addrs] -base = "0x600000" -top = "0x700000" -stride = "0x10" - -[registers] -ignore = [ - "_PC", - "SEE", - "__trickbox_enabled", - "__v81_implemented", - "__v82_implemented", - "__v83_implemented", - "__v84_implemented", - "__v85_implemented" -] - -relaxed = [ - "TTBR0_EL1", - "TTBR0_EL2", - "TTBR0_EL3", - "TTBR1_EL1", - "TTBR1_EL2", - "VTTBR_EL2" -] - -[registers.defaults] -"__isla_vector_gpr" = false -#"__isla_continue_on_see" = true -"__monomorphize_reads" = true -"__monomorphize_writes" = false -"VBAR_EL1" = "0x0000000000000000" -"VBAR_EL2" = "0x0000000000000000" -# Causes CNTCV to be incremented every cycle if bit 0 is 1 -"CNTCR" = "0x00000001" -# SSAdvance? -"MDSCR_EL1" = "0x0000000000000000" -"InGuardedPage" = false -"__highest_el_aarch32" = false -"__CNTControlBase" = "0x0000000000000" -"__supported_pa_size" = 52 -"__supported_va_size" = 52 -"__max_implemented_smeveclen" = 512 -"SCTLR_EL3" = "0x0000000000000000" -"SMCR_EL3" = "0x0000000000000000" -"ZCR_EL3" = "0x0000000000000000" -"CPTR_EL3" = "0x0000000000000000" -"CNTP_CTL_EL0" = "0x0000000000000000" -"CNTV_CTL_EL0" = "0x0000000000000000" -"CNTHP_CTL_EL2" = "0x0000000000000000" -"CNTHV_CTL_EL2" = "0x0000000000000000" -"CNTHPS_CTL_EL2" = "0x0000000000000000" -"CNTHVS_CTL_EL2" = "0x0000000000000000" -"CNTPS_CTL_EL1" = "0x0000000000000000" -"CNTHCTL_EL2" = "0x0000000000000000" -"CNTKCTL_EL1" = "0x0000000000000000" -"MPAMIDR_EL1" = "0x0000000000000000" -"CFG_RMR_AA64" = "0b1" -"CFG_RVBAR" = "0x0000000010300000" -"CFG_ID_AA64PFR0_EL1_MPAM" = "0x1" -"CFG_ID_AA64PFR0_EL1_EL3" = "0x1" -"CFG_ID_AA64PFR0_EL1_EL2" = "0x1" -"CFG_ID_AA64PFR0_EL1_EL1" = "0x1" -"CFG_ID_AA64PFR0_EL1_EL0" = "0x1" -# Need to investigate BTI extension. Guard pages cause problems with -# memory accesses. -"__v81_implemented" = true -"__v82_implemented" = false -"__v83_implemented" = false -"__v84_implemented" = false -"__v85_implemented" = false -"__unpred_tsize_aborts" = true -# Trickbox has various features for debugging spec and running tests -"__trickbox_enabled" = false -"__tlb_enabled" = false -"__syncAbortOnTTWNonCache" = true -"__syncAbortOnTTWCache" = true -"__syncAbortOnSoWrite" = true -"__syncAbortOnSoRead" = true -"__syncAbortOnReadNormNonCache" = true -"__syncAbortOnReadNormCache" = true -"__syncAbortOnPrefetch" = true -"__syncAbortOnDeviceRead" = true -"__mte_implemented" = "0b0000" -"__brbev1p1_implemented" = false -"__rme_implemented" = false -"__brbe_implemented" = false -"__empam_implemented" = false -"__pac_frac_implemented" = false -"__pacqarma3_implemented" = false -"__has_sme" = false -"__mpam_has_hcr" = true -"__mpam_has_altsp" = true -"__vmid16_implemented" = true -"__pan_implemented" = true -"__fp16_implemented" = true -"__dot_product_implemented" = true -"__crc32_implemented" = true -"__aa32_hpd_implemented" = true -"__crypto_aes_implemented" = 2 -"__crypto_sha256_implemented" = true -"__crypto_sha1_implemented" = true -"__syncAbortOnWriteNormNonCache" = false -"__syncAbortOnWriteNormCache" = false -"__syncAbortOnDeviceWrite" = false -"__mpam_implemented" = false -"__crypto_sm4_implemented" = false -"__crypto_sm3_implemented" = false -"__crypto_sha512_implemented" = false -"__crypto_sha3_implemented" = false -"__feat_ls64_v" = true -"__feat_ls64_accdata" = true - -"SCTLR_EL1" = "0x0000000004800005" -"SCTLR_EL2" = "0x0000000000000005" -"HCR_EL2" = "0x0000000000000003" -#"HCR_EL2" = "0x0000000400000001" E2H -"SCR_EL3" = "0x0000000000040101" -"VTCR_EL2" = "0x0000000000050090" -"VTTBR_EL2" = "0x0000000000200000" -"TCR_EL1" = "0x0000000080000010" -"TCR_EL2" = "0x0000000080000010" -"TCR_EL3" = "0x0000000000000010" -"TTBR0_EL1" = "0x0000000000300000" -"TTBR0_EL2" = "0x0000000000300000" - -# These registers are set during symbolic execution by the special builtin "reset_registers" -[registers.reset] -# Bit 0 enables the MMU -# Bit 1 being unset allows unaligned accesses -# Bit 2 allows cacheable mappings -# Bit 26 being set allows cache-maintenance ops in EL0 -"SCTLR_EL1" = "0x0000000004800005" -"SCTLR_EL2" = "0x0000000000000005" -"HCR_EL2" = "0x0000000000000003" -#"HCR_EL2" = "0x0000000400000001" E2H -"SCR_EL3" = "0x0000000000040101" -"VTCR_EL2" = "0x0000000000050090" -"VTTBR_EL2" = "0x0000000000200000" -"TCR_EL1" = "0x0000000080000010" -"TCR_EL2" = "0x0000000080000010" -"TCR_EL3" = "0x0000000000000010" -"TTBR0_EL1" = "0x0000000000300000" -"TTBR0_EL2" = "0x0000000000300000" -"PSTATE.PAN" = "0b0" -"PSTATE.SP" = "0b0" -"CNTCR" = "0x00000000" - -# A map from register names that may appear in litmus files to Sail -# register names -[registers.renames] -"X0" = "R0" -"X1" = "R1" -"X2" = "R2" -"X3" = "R3" -"X4" = "R4" -"X5" = "R5" -"X6" = "R6" -"X7" = "R7" -"X8" = "R8" -"X9" = "R9" -"X10" = "R10" -"X11" = "R11" -"X12" = "R12" -"X13" = "R13" -"X14" = "R14" -"X15" = "R15" -"X16" = "R16" -"X17" = "R17" -"X18" = "R18" -"X19" = "R19" -"X20" = "R20" -"X21" = "R21" -"X22" = "R22" -"X23" = "R23" -"X24" = "R24" -"X25" = "R25" -"X26" = "R26" -"X27" = "R27" -"X28" = "R28" -"X29" = "R29" -"X30" = "R30" -"W0" = "R0" -"W1" = "R1" -"W2" = "R2" -"W3" = "R3" -"W4" = "R4" -"W5" = "R5" -"W6" = "R6" -"W7" = "R7" -"W8" = "R8" -"W9" = "R9" -"W10" = "R10" -"W11" = "R11" -"W12" = "R12" -"W13" = "R13" -"W14" = "R14" -"W15" = "R15" -"W16" = "R16" -"W17" = "R17" -"W18" = "R18" -"W19" = "R19" -"W20" = "R20" -"W21" = "R21" -"W22" = "R22" -"W23" = "R23" -"W24" = "R24" -"W25" = "R25" -"W26" = "R26" -"W27" = "R27" -"W28" = "R28" -"W29" = "R29" -"W30" = "R30" \ No newline at end of file diff --git a/configs/armv9.toml b/configs/armv9p3.toml similarity index 100% rename from configs/armv9.toml rename to configs/armv9p3.toml diff --git a/configs/armv9_mmu_on.toml b/configs/armv9p3_mmu_on.toml similarity index 100% rename from configs/armv9_mmu_on.toml rename to configs/armv9p3_mmu_on.toml diff --git a/configs/armv9_macos.toml b/configs/armv9p4.toml similarity index 50% rename from configs/armv9_macos.toml rename to configs/armv9p4.toml index e879fd62..0f19152d 100644 --- a/configs/armv9_macos.toml +++ b/configs/armv9p4.toml @@ -4,16 +4,28 @@ pc = "_PC" translation_function = "AArch64_TranslateAddress" +in_program_order = ["sail_barrier", "sail_cache_op", "sail_take_exception", "sail_return_exception", "sail_tlbi"] + +# litmus variables have type uint32_t by default +default_sizeof = 4 + # The assembler is used for assembling the code in litmus tests. We # assume it takes arguments like GNU as. +[[toolchain]] +name = "macos-aarch64" +os = "macos" +arch = "aarch64" assembler = "as --target=aarch64-unknown-linux-gnu" objdump = "/opt/homebrew/opt/llvm/bin/llvm-objdump" +nm = "/opt/homebrew/opt/llvm/bin/llvm-nm" linker = "/opt/homebrew/opt/llvm/bin/ld.lld" -in_program_order = ["sail_barrier"] - -# litmus variables have type uint32_t by default -default_sizeof = 4 +[[toolchain]] +name = "default" +assembler = "aarch64-linux-gnu-as -march=armv8.1-a" +objdump = "aarch64-linux-gnu-objdump" +nm = "aarch64-linux-gnu-nm" +linker = "aarch64-linux-gnu-ld" [mmu] page_table_base = "0x300000" @@ -43,11 +55,20 @@ ignore = [ "_PC", "SEE", "__trickbox_enabled", - "__v81_implemented", - "__v82_implemented", - "__v83_implemented", - "__v84_implemented", - "__v85_implemented" + "v8Ap1_IMPLEMENTED", + "v8Ap2_IMPLEMENTED", + "v8Ap3_IMPLEMENTED", + "v8Ap4_IMPLEMENTED", + "v8Ap5_IMPLEMENTED", + "v8Ap6_IMPLEMENTED", + "v8Ap7_IMPLEMENTED", + "v8Ap8_IMPLEMENTED", + "v8Ap9_IMPLEMENTED", + "v9Ap0_IMPLEMENTED", + "v9Ap1_IMPLEMENTED", + "v9Ap2_IMPLEMENTED", + "v9Ap3_IMPLEMENTED", + "v9Ap4_IMPLEMENTED", ] # These registers are set before any symbolic execution occurs @@ -59,48 +80,59 @@ ignore = [ "VBAR_EL1" = "0x0000000000000000" "VBAR_EL2" = "0x0000000000000000" # Causes CNTCV to be incremented every cycle if bit 0 is 1 -"CNTCR" = "0x00000001" +"CNTCR" = "{ bits = 0x00000001 }" # SSAdvance? -"MDSCR_EL1" = "0x0000000000000000" +"MDSCR_EL1" = "{ bits = 0x0000000000000000 }" "InGuardedPage" = false "__highest_el_aarch32" = false -"__CNTControlBase" = "0x0000000000000" +"__CNTControlBase" = "0x00000000000000" "__supported_pa_size" = 52 "__supported_va_size" = 52 "__max_implemented_smeveclen" = 512 -"HCR_EL2" = "0x0000000000000000" -"TCR_EL1" = "0x0000000000000000" -"TCR_EL2" = "0x0000000000000000" -"TCR_EL3" = "0x0000000000000000" -"SCR_EL3" = "0x0000000000000000" -"SCTLR_EL3" = "0x0000000000000000" -"SMCR_EL3" = "0x0000000000000000" -"ZCR_EL3" = "0x0000000000000000" -"CPTR_EL3" = "0x0000000000000000" -"CNTP_CTL_EL0" = "0x0000000000000000" -"CNTV_CTL_EL0" = "0x0000000000000000" -"CNTHP_CTL_EL2" = "0x0000000000000000" -"CNTHV_CTL_EL2" = "0x0000000000000000" -"CNTHPS_CTL_EL2" = "0x0000000000000000" -"CNTHVS_CTL_EL2" = "0x0000000000000000" -"CNTPS_CTL_EL1" = "0x0000000000000000" -"CNTHCTL_EL2" = "0x0000000000000000" -"CNTKCTL_EL1" = "0x0000000000000000" -"MPAMIDR_EL1" = "0x0000000000000000" +# HCR_EL2.RW +"HCR_EL2" = "{ bits = 0x0000000080000000 }" +"TCR_EL1" = "{ bits = 0x0000000000000000 }" +"TCR_EL2" = "{ bits = 0x0000000000000000 }" +"TCR_EL3" = "{ bits = 0x0000000000000000 }" +# SCR_EL3.{RW,NS} +"SCR_EL3" = "{ bits = 0x0000000000000401 }" +"SCTLR_EL3" = "{ bits = 0x0000000000000000 }" +"SMCR_EL3" = "{ bits = 0x0000000000000000 }" +"ZCR_EL3" = "{ bits = 0x0000000000000000 }" +"CPTR_EL3" = "{ bits = 0x0000000000000000 }" +"CNTP_CTL_EL0" = "{ bits = 0x0000000000000000 }" +"CNTV_CTL_EL0" = "{ bits = 0x0000000000000000 }" +"CNTHP_CTL_EL2" = "{ bits = 0x0000000000000000 }" +"CNTHV_CTL_EL2" = "{ bits = 0x0000000000000000 }" +"CNTHPS_CTL_EL2" = "{ bits = 0x0000000000000000 }" +"CNTHVS_CTL_EL2" = "{ bits = 0x0000000000000000 }" +"CNTPS_CTL_EL1" = "{ bits = 0x0000000000000000 }" +"CNTHCTL_EL2" = "{ bits = 0x0000000000000000 }" +"CNTKCTL_EL1" = "{ bits = 0x0000000000000000 }" +"MPAMIDR_EL1" = "{ bits = 0x0000000000000000 }" +"GPCCR_EL3" = "{ bits = 0x0000000000000000 }" "CFG_RMR_AA64" = "0b1" "CFG_RVBAR" = "0x0000000010300000" -"CFG_ID_AA64PFR0_EL1_MPAM" = "0x1" "CFG_ID_AA64PFR0_EL1_EL3" = "0x1" "CFG_ID_AA64PFR0_EL1_EL2" = "0x1" "CFG_ID_AA64PFR0_EL1_EL1" = "0x1" "CFG_ID_AA64PFR0_EL1_EL0" = "0x1" # Need to investigate BTI extension. Guard pages cause problems with # memory accesses. -"__v81_implemented" = true -"__v82_implemented" = false -"__v83_implemented" = false -"__v84_implemented" = false -"__v85_implemented" = false +"v8Ap1_IMPLEMENTED" = true +"v8Ap2_IMPLEMENTED" = false +"v8Ap3_IMPLEMENTED" = false +"v8Ap4_IMPLEMENTED" = false +"v8Ap5_IMPLEMENTED" = false +"v8Ap6_IMPLEMENTED" = false +"v8Ap7_IMPLEMENTED" = false +"v8Ap8_IMPLEMENTED" = false +"v8Ap9_IMPLEMENTED" = false +"v9Ap0_IMPLEMENTED" = false +"v9Ap1_IMPLEMENTED" = false +"v9Ap2_IMPLEMENTED" = false +"v9Ap3_IMPLEMENTED" = false +"v9Ap4_IMPLEMENTED" = false "__unpred_tsize_aborts" = true # Trickbox has various features for debugging spec and running tests "__trickbox_enabled" = false @@ -114,41 +146,60 @@ ignore = [ "__syncAbortOnPrefetch" = true "__syncAbortOnDeviceRead" = true "__mte_implemented" = "0b0000" -"__brbev1p1_implemented" = false -"__rme_implemented" = false -"__brbe_implemented" = false -"__empam_implemented" = false -"__pac_frac_implemented" = false -"__pacqarma3_implemented" = false -"__has_sme" = false +"FEAT_BRBEv1p1_IMPLEMENTED" = false +"FEAT_RME_IMPLEMENTED" = false +"FEAT_BRBE_IMPLEMENTED" = false +"__empam_force_ns_implemented" = false +"__empam_sdeflt_implemented" = false +"__empam_tidr_implemented" = false +"FEAT_CONSTPACFIELD_IMPLEMENTED" = false +"FEAT_PACQARMA3_IMPLEMENTED" = false +"FEAT_SME_IMPLEMENTED" = false "__mpam_has_hcr" = true "__mpam_has_altsp" = true -"__vmid16_implemented" = true -"__pan_implemented" = true -"__fp16_implemented" = true -"__dot_product_implemented" = true -"__crc32_implemented" = true -"__aa32_hpd_implemented" = true -"__crypto_aes_implemented" = 2 -"__crypto_sha256_implemented" = true -"__crypto_sha1_implemented" = true +#"__vmid16_implemented" = true +"FEAT_PAN_IMPLEMENTED" = true +"FEAT_FP16_IMPLEMENTED" = true +"FEAT_DotProd_IMPLEMENTED" = true +"FEAT_CRC32_IMPLEMENTED" = true +"FEAT_AA32HPD_IMPLEMENTED" = true +"FEAT_AES_IMPLEMENTED" = true +"FEAT_PMULL_IMPLEMENTED" = true +"FEAT_SHA256_IMPLEMENTED" = true +"FEAT_SHA1_IMPLEMENTED" = true "__syncAbortOnWriteNormNonCache" = false "__syncAbortOnWriteNormCache" = false "__syncAbortOnDeviceWrite" = false -"__mpam_implemented" = false -"__crypto_sm4_implemented" = false -"__crypto_sm3_implemented" = false -"__crypto_sha512_implemented" = false -"__crypto_sha3_implemented" = false -"__feat_ls64_v" = true -"__feat_ls64_accdata" = true +"FEAT_MPAM_IMPLEMENTED" = false +"FEAT_SM4_IMPLEMENTED" = false +"FEAT_SM3_IMPLEMENTED" = false +"FEAT_SHA512_IMPLEMENTED" = false +"FEAT_SHA3_IMPLEMENTED" = false +"FEAT_LS64_V_IMPLEMENTED" = true +"FEAT_LS64_ACCDATA_IMPLEMENTED" = true + +# Avoid some extra complication +"FEAT_TME_IMPLEMENTED" = false +# As an alternative to the below, you could abstract the SPEBranch and +# BRBEBranch functions. +"FEAT_SPE_IMPLEMENTED" = false +"FEAT_SPEv1p1_IMPLEMENTED" = false +"FEAT_SPEv1p2_IMPLEMENTED" = false +"FEAT_SPEv1p3_IMPLEMENTED" = false +"FEAT_SPEv1p4_IMPLEMENTED" = false +"FEAT_PMUv3_IMPLEMENTED" = false + +"SPESampleInFlight" = false + +"__g1_activity_monitor_implemented" = "0x0000" +"__g1_activity_monitor_offset_implemented" = "0x0000" # These registers are set during symbolic execution by the special builtin "reset_registers" [registers.reset] # Bit 1 being unset allows unaligned accesses # Bit 26 being set allows cache-maintenance ops in EL0 -"SCTLR_EL1" = "0x0000000004000000" -"CNTCR" = "0x00000000" +"SCTLR_EL1" = "{ bits = 0x0000000004000000 }" +"CNTCR" = "{ bits = 0x00000000 }" # A map from register names that may appear in litmus files to Sail # register names