Gate Validation incorrectly rejects supported SYC gate

[senecameeks]

Description of the issue

Gate validation improperly rejects SYC gate. When running internally and bypassing validation e.g remote_sampler = qe.CirqServerSampler(connector.grpc_client, "SYC01_10A_BLACK", "current", "iswap7_lower", use_json_serialization=True) I'm able to get back a result. Likely a logical mismatch is occuring in cirq-google/cirq_google/devices/grid_device.py

How to reproduce the issue

import time
import cirq
import cirq_google
from cirq_google.engine import get_engine
from cirq_google.engine.qcs_notebook import authenticate_user

authenticate_user()
engine = get_engine("cirq-tutorial")
engine.enable_streaming = False

id = 'SYC01_10A_BLACK'
processor = engine.get_processor(id)
sampler = processor.get_sampler(run_name="current", device_config_name="iswap7_lower")
duration = 600
elapsed_time = 0
# For "iswap7_lower", using cz, or sqrt_iswap.on, sqrt_iswap_like.on cause system errors
# for an iswap grid use SYC cirq_google.ops.SYC
# iswap_like = syc
qubit1 = cirq.GridQubit(8,4)
qubit2 = cirq.GridQubit(8,5)
circuit = cirq.Circuit(cirq_google.ops.SYC(qubit1, qubit2), cirq.measure(qubit1))


result = sampler.run_batch([circuit]*50)
print(result)

Outputs 
Job projects/cirq-tutorial/programs/prog-1DH5XNLJORTEK3Y4241029-101250/jobs/job-6HYWYUV7J2CH17UT241029-101250 on processor projects/cirq-tutorial/processors/SYC01_10A_BLACK failed. INVALID_PROGRAM: Operation cirq.FSimGate(theta=1.5707963705062866, phi=0.5235987901687622)(q(8, 4), q(8, 5)) contains a gate which is not supported.

[senecameeks]

I think the problem might be that SYC is not represented here in the default gatesets supported by Quantum Engine: https://github.com/qh-lab/pyle/blob/5640ffb2297f685239b3d6897f49028f3b82f058/src/pyle/quantum_engine/gatesets.py#L30

[BichengYing]

yes, you find the right spot! CC: @verult since he taught me about this file. I can create a simple PR to fix it

[BichengYing]

wait, there is no such serialization representation of SYC gate.

Cirq/cirq-google/cirq_google/api/v2/program.proto

Lines 197 to 220 in 2975d10

	message Operation {
	// Which gate this operation corresponds to.
	// Populated pre-v2.5+.
	Gate gate = 1 [deprecated = true];
	// Each gate should populate one possible gate message
	// depending on the type desired. Only populated in v2.5+.
	oneof gate_value {
	XPowGate xpowgate = 7;
	YPowGate ypowgate = 8;
	ZPowGate zpowgate = 9;
	PhasedXPowGate phasedxpowgate = 10;
	PhasedXZGate phasedxzgate = 11;
	CZPowGate czpowgate = 12;
	FSimGate fsimgate = 13;
	ISwapPowGate iswappowgate = 14;
	MeasurementGate measurementgate = 15;
	WaitGate waitgate = 16;
	InternalGate internalgate = 17;
	CouplerPulseGate couplerpulsegate = 18;
	IdentityGate identitygate = 19;
	HPowGate hpowgate = 20;
	SingleQubitCliffordGate singlequbitcliffordgate = 21;
	}

So it is not possible to support it quickly, unfortunately. @senecameeks Can you add serialization and deserialization logic for SYC gate?

[github-actions]

This issue is stale because it has been open 30 days with no activity. Remove stale label or comment or this will be closed in 30 days

[NoureldinYosri]

cirq-sync: SYC serialization is not implemented directly since it can be converted to an FSimGate which is supported

[eliottrosenberg]

@NoureldinYosri it also fails for the corresponding fSim gate. See this colab.

[wcourtney]

It looks like the failure of FSim gate validation is because they apparently require the FSimViaModelTag. This was added by @BichengYing in #6527.

I verified that including the tag passes validation, including when applied to the SYC gate (colab).

Example:

cirq_google.SYC(q1,q2).with_tags(cirq_google.FSimViaModelTag())

However, once the circuit is past validation and sent to the backends there are further issues that we should track on our internal repo.

@eliottrosenberg - is there additional work you'd like done on the client-side regarding validation here?

[eliottrosenberg]

@wcourtney with that tag, it would get translated to an arbitrary-angle fSim gate (i.e. a different gate internally), which is not what we want.