From f64b0c698d7ed0a8cb4ddf3bacd797d5b6abb5a2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Kr=C3=B3l?= Date: Sun, 19 Jun 2016 22:25:28 +0200 Subject: [PATCH 01/12] amd/pi/hudson: force to use SD in 2.0 mode --- src/southbridge/amd/pi/hudson/sd.c | 28 +++++++++++++++------------- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/src/southbridge/amd/pi/hudson/sd.c b/src/southbridge/amd/pi/hudson/sd.c index 03b097a0c53..1b755c54d7b 100644 --- a/src/southbridge/amd/pi/hudson/sd.c +++ b/src/southbridge/amd/pi/hudson/sd.c @@ -31,27 +31,29 @@ static void sd_init(struct device *dev) stepping = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xFC); - struct southbridge_amd_pi_hudson_config *sd_chip = - (struct southbridge_amd_pi_hudson_config *)(dev->chip_info); +// Force to use SD host in 2.0 mode for APU2 +// struct southbridge_amd_pi_hudson_config *sd_chip = +// (struct southbridge_amd_pi_hudson_config *)(dev->chip_info); - if (sd_chip->sd_mode == 3) { /* SD 3.0 mode */ - pci_write_config32(dev, 0xA4, 0x31FEC8B2); - pci_write_config32(dev, 0xA8, 0x00002503); - pci_write_config32(dev, 0xB0, 0x02180C19); - pci_write_config32(dev, 0xD0, 0x0000078B); - } - else { /* SD 2.0 mode */ +// if (sd_chip->sd_mode == 3) { /* SD 3.0 mode */ +// pci_write_config32(dev, 0xA4, 0x31FEC8B2); +// pci_write_config32(dev, 0xA8, 0x00002503); +// pci_write_config32(dev, 0xB0, 0x02180C19); +// pci_write_config32(dev, 0xD0, 0x0000078B); +// } +// else { /* SD 2.0 mode */ if ((stepping & 0x0000000F) == 0) { /* Stepping A0 */ pci_write_config32(dev, 0xA4, 0x31DE32B2); pci_write_config32(dev, 0xB0, 0x01180C19); pci_write_config32(dev, 0xD0, 0x0000058B); } else { /* Stepping >= A1 */ - pci_write_config32(dev, 0xA4, 0x31FE3FB2); - pci_write_config32(dev, 0xB0, 0x01180C19); - pci_write_config32(dev, 0xD0, 0x0000078B); + pci_write_config32(dev, 0xA4, 0x01003200); + pci_write_config32(dev, 0xA8, 0x00000070); + pci_write_config32(dev, 0xB0, 0x01000000); + pci_write_config32(dev, 0xD0, 0x0000048B); } - } +// } } static struct device_operations sd_ops = { From d1dacb2e489a94578a2371643a8006912bf24a15 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Kr=C3=B3l?= Date: Mon, 27 Jun 2016 02:02:20 +0200 Subject: [PATCH 02/12] southbridge/amd/pi/hudson: set SDHC A8 register for SD 2.0 mode --- src/southbridge/amd/pi/hudson/sd.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/southbridge/amd/pi/hudson/sd.c b/src/southbridge/amd/pi/hudson/sd.c index 1b755c54d7b..47dd69ce306 100644 --- a/src/southbridge/amd/pi/hudson/sd.c +++ b/src/southbridge/amd/pi/hudson/sd.c @@ -48,10 +48,10 @@ static void sd_init(struct device *dev) pci_write_config32(dev, 0xD0, 0x0000058B); } else { /* Stepping >= A1 */ - pci_write_config32(dev, 0xA4, 0x01003200); + pci_write_config32(dev, 0xA4, 0x31FE3FB2); pci_write_config32(dev, 0xA8, 0x00000070); - pci_write_config32(dev, 0xB0, 0x01000000); - pci_write_config32(dev, 0xD0, 0x0000048B); + pci_write_config32(dev, 0xB0, 0x01180C19); + pci_write_config32(dev, 0xD0, 0x0000078B); } // } } From f56021de5f4458274577932c0a2792aa64fad9cc Mon Sep 17 00:00:00 2001 From: Maciej Pijanowski Date: Mon, 4 Jul 2016 14:55:59 +0200 Subject: [PATCH 03/12] config: SeaBIOS update --- configs/pcengines.apu2.20160304.config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/pcengines.apu2.20160304.config b/configs/pcengines.apu2.20160304.config index 64394d22cb0..27261dbfb80 100644 --- a/configs/pcengines.apu2.20160304.config +++ b/configs/pcengines.apu2.20160304.config @@ -391,7 +391,7 @@ CONFIG_PAYLOAD_SEABIOS=y CONFIG_SEABIOS_ELTAN=y CONFIG_SEABIOS_STABLE=y # CONFIG_SEABIOS_MASTER is not set -CONFIG_ELTAN_SEABIOS_TAG="dc06fd2a7057e9a2f748cf6a9f8fb8d41a95097c" +CONFIG_ELTAN_SEABIOS_TAG="ac6d3e213a3867bd586b62924b8255d57333e078" # CONFIG_SEABIOS_SERIAL_CONSOLE is not set # CONFIG_SKIP_PXE_LOAD is not set # CONFIG_SEABIOS_THREAD_OPTIONROMS is not set From 1d16c69a2312f4ad0442fe96e17205e55bdc40ac Mon Sep 17 00:00:00 2001 From: Maciej Pijanowski Date: Mon, 4 Jul 2016 15:07:03 +0200 Subject: [PATCH 04/12] src/southbridge/amd/pi/hudson: disable 64-mode bits in A4 register Bit 28 (64-bit support) from A4 set to 0. Bits 4 (64-bit MSI) and 3 (64-bit PCI addr) from B0 set to 0. --- src/southbridge/amd/pi/hudson/sd.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/southbridge/amd/pi/hudson/sd.c b/src/southbridge/amd/pi/hudson/sd.c index 47dd69ce306..2e1ec940e58 100644 --- a/src/southbridge/amd/pi/hudson/sd.c +++ b/src/southbridge/amd/pi/hudson/sd.c @@ -43,14 +43,14 @@ static void sd_init(struct device *dev) // } // else { /* SD 2.0 mode */ if ((stepping & 0x0000000F) == 0) { /* Stepping A0 */ - pci_write_config32(dev, 0xA4, 0x31DE32B2); - pci_write_config32(dev, 0xB0, 0x01180C19); + pci_write_config32(dev, 0xA4, 0x21DE32B2); + pci_write_config32(dev, 0xB0, 0x01180C01); pci_write_config32(dev, 0xD0, 0x0000058B); } else { /* Stepping >= A1 */ - pci_write_config32(dev, 0xA4, 0x31FE3FB2); + pci_write_config32(dev, 0xA4, 0x21FE32B2); pci_write_config32(dev, 0xA8, 0x00000070); - pci_write_config32(dev, 0xB0, 0x01180C19); + pci_write_config32(dev, 0xB0, 0x01180C01); pci_write_config32(dev, 0xD0, 0x0000078B); } // } From 45dad4407ec73b914e4e5342e5ccf8bdb2e9a23a Mon Sep 17 00:00:00 2001 From: Maciej Pijanowski Date: Tue, 5 Jul 2016 16:32:39 +0200 Subject: [PATCH 05/12] config, payloads/external/SeaBIOS/Makefile.inc: reduce log level --- configs/pcengines.apu2.20160304.config | 6 +++--- payloads/external/SeaBIOS/Makefile.inc | 2 ++ 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/configs/pcengines.apu2.20160304.config b/configs/pcengines.apu2.20160304.config index 27261dbfb80..853b7127697 100644 --- a/configs/pcengines.apu2.20160304.config +++ b/configs/pcengines.apu2.20160304.config @@ -330,11 +330,11 @@ CONFIG_CONSOLE_PRERAM_BUFFER_SIZE=0x0 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL=3 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=1 # CONFIG_NO_POST is not set # CONFIG_CMOS_POST is not set # CONFIG_CONSOLE_POST is not set diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index 1a5a07f54f4..0b265ad1e24 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -70,6 +70,8 @@ ifeq ($(CONFIG_SEABIOS_VGA_COREBOOT),y) echo "CONFIG_BUILD_VGABIOS=y" >> seabios/.config endif + echo "CONFIG_DEBUG_LEVEL=0" >> seabios/.config + ifeq ($(CONFIG_SEABIOS_SERIAL_CONSOLE),y) echo "CONFIG_SEABIOS_SERIAL_CONSOLE=y" >> seabios/.config echo "CONFIG_DEBUG_LEVEL=0" >> seabios/.config From a55b50fabdbc3d07f978748a621723ca14860250 Mon Sep 17 00:00:00 2001 From: Maciej Pijanowski Date: Tue, 5 Jul 2016 16:36:10 +0200 Subject: [PATCH 06/12] src/mainboard/pcengines/apu2/mainboard.c: change data written to etc/screen-and-debug from 1 to 0 --- src/mainboard/pcengines/apu2/mainboard.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c index 3ec0b489487..fef52a54a6e 100644 --- a/src/mainboard/pcengines/apu2/mainboard.c +++ b/src/mainboard/pcengines/apu2/mainboard.c @@ -249,7 +249,7 @@ static void mainboard_final(void *chip_info) { // // The console should be disabled // - unsigned char data = 1; + unsigned char data = 0; // // Indicated to SeaBIOS it should display console output itself From 25d72f228f70d2ce86bfcd37ca45163918b3c07b Mon Sep 17 00:00:00 2001 From: Maciej Pijanowski Date: Wed, 6 Jul 2016 13:04:47 +0200 Subject: [PATCH 07/12] src/mainboard/pcengines/apu2: add iPXE to sortbootorder menu --- src/mainboard/pcengines/apu2/bootorder_def | 1 + src/mainboard/pcengines/apu2/bootorder_map | 1 + 2 files changed, 2 insertions(+) diff --git a/src/mainboard/pcengines/apu2/bootorder_def b/src/mainboard/pcengines/apu2/bootorder_def index 2eaf1e5f7fb..45f0252d3f4 100644 --- a/src/mainboard/pcengines/apu2/bootorder_def +++ b/src/mainboard/pcengines/apu2/bootorder_def @@ -5,4 +5,5 @@ /pci@i0cf8/*@14,7 /pci@i0cf8/*@11/drive@0/disk@0 /pci@i0cf8/*@11/drive@1/disk@0 +/rom@genroms/pxe.rom diff --git a/src/mainboard/pcengines/apu2/bootorder_map b/src/mainboard/pcengines/apu2/bootorder_map index 2ed91cb0671..cea2ca5ab1a 100644 --- a/src/mainboard/pcengines/apu2/bootorder_map +++ b/src/mainboard/pcengines/apu2/bootorder_map @@ -5,4 +5,5 @@ d USB 2 HS e SDCARD f mSATA g SATA +h iPXE From 263f2d25421f52a85537ac55bee09e0213f23ef6 Mon Sep 17 00:00:00 2001 From: Maciej Pijanowski Date: Thu, 7 Jul 2016 12:15:32 +0200 Subject: [PATCH 08/12] src/mainboard/pcengines/apu2/bootorder: add usb enable entry into bootorder --- src/mainboard/pcengines/apu2/bootorder | Bin 4096 -> 4096 bytes 1 file changed, 0 insertions(+), 0 deletions(-) diff --git a/src/mainboard/pcengines/apu2/bootorder b/src/mainboard/pcengines/apu2/bootorder index 8744ceb615b723276094f2d30a0b8edb4dbd7904..baca2e9e63220c33d6013e27a11431a1dd57a6ee 100644 GIT binary patch delta 22 ecmZorXi%8&n5DEhDRtxh$9$8|@S8C4asdEsG6 Date: Wed, 13 Jul 2016 14:47:17 +0200 Subject: [PATCH 09/12] pcengines/apu2: remove empty lines in bootorder files --- src/mainboard/pcengines/apu2/bootorder_def | 1 - src/mainboard/pcengines/apu2/bootorder_map | 1 - 2 files changed, 2 deletions(-) diff --git a/src/mainboard/pcengines/apu2/bootorder_def b/src/mainboard/pcengines/apu2/bootorder_def index 45f0252d3f4..4753635881e 100644 --- a/src/mainboard/pcengines/apu2/bootorder_def +++ b/src/mainboard/pcengines/apu2/bootorder_def @@ -6,4 +6,3 @@ /pci@i0cf8/*@11/drive@0/disk@0 /pci@i0cf8/*@11/drive@1/disk@0 /rom@genroms/pxe.rom - diff --git a/src/mainboard/pcengines/apu2/bootorder_map b/src/mainboard/pcengines/apu2/bootorder_map index cea2ca5ab1a..41239066dbd 100644 --- a/src/mainboard/pcengines/apu2/bootorder_map +++ b/src/mainboard/pcengines/apu2/bootorder_map @@ -6,4 +6,3 @@ e SDCARD f mSATA g SATA h iPXE - From e82ab107f0062be51e83be240029965106322c91 Mon Sep 17 00:00:00 2001 From: Maciej Pijanowski Date: Wed, 13 Jul 2016 09:42:38 +0200 Subject: [PATCH 10/12] pcengines/apu2/mainboard.c: restore PC Engines, DRAM, ECC logs --- src/mainboard/pcengines/apu2/mainboard.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c index fef52a54a6e..3d89aff6190 100644 --- a/src/mainboard/pcengines/apu2/mainboard.c +++ b/src/mainboard/pcengines/apu2/mainboard.c @@ -46,6 +46,8 @@ #include #include +static bool check_console(void); + /********************************************** * enable the dedicated function in mainboard. **********************************************/ @@ -54,10 +56,14 @@ static void mainboard_enable(device_t dev) { struct device *sio_dev; + bool scon = check_console(); setup_bsp_ramtop(); u32 TOM1 = bsp_topmem() / (1024 *1024); // Tom1 in Mbyte u32 TOM2 = ( bsp_topmem2() / (1024 *1024)) - 4 * 1024; // Tom2 in Mbyte - printk(BIOS_ERR, "%d MB", TOM1+TOM2); + if (scon) { + printk(BIOS_ALERT, CONFIG_MAINBOARD_PART_NUMBER "\n"); + printk(BIOS_ALERT, "%d MB", TOM1+TOM2); + } u8 spd_buffer[SPD_SIZE]; int index = 0; @@ -66,13 +72,15 @@ static void mainboard_enable(device_t dev) if ( ReadFchGpio(APU2_SPD_STRAP0_GPIO) ) index |= BIT0; if ( ReadFchGpio(APU2_SPD_STRAP1_GPIO) ) index |= BIT1; - + printk(BIOS_SPEW, "Reading SPD index %d to get ECC info \n", index); if (read_spd_from_cbfs(spd_buffer, index) < 0) spd_buffer[3]=3; // Indicate no ECC - if ( spd_buffer[3] == 8 ) printk(BIOS_ERR, " ECC"); - printk(BIOS_ERR, " DRAM\n\n"); + if (scon) { + if ( spd_buffer[3] == 8 ) printk(BIOS_ALERT, " ECC"); + printk(BIOS_ALERT, " DRAM\n\n"); + } // // Enable the RTC output From e4a557281138177567a0e239966ee7d8117a7002 Mon Sep 17 00:00:00 2001 From: Maciej Pijanowski Date: Wed, 13 Jul 2016 10:41:48 +0200 Subject: [PATCH 11/12] pcengines/apu2/boot-menu-message: N for one-time pxe boot --- src/mainboard/pcengines/apu2/boot-menu-message | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/pcengines/apu2/boot-menu-message b/src/mainboard/pcengines/apu2/boot-menu-message index 55dae9a9280..2b61487904a 100644 --- a/src/mainboard/pcengines/apu2/boot-menu-message +++ b/src/mainboard/pcengines/apu2/boot-menu-message @@ -1 +1 @@ -PCengines Press F10 key now for boot menu: +Press F10 key now for boot menu, N for PXE boot From 6e700a6384bbe843439b9784d6347f6f63d67943 Mon Sep 17 00:00:00 2001 From: Maciej Pijanowski Date: Tue, 19 Jul 2016 12:11:40 +0200 Subject: [PATCH 12/12] pcengines/apu2/bootorder_map: merge all USB entries --- src/mainboard/pcengines/apu2/bootorder_map | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/mainboard/pcengines/apu2/bootorder_map b/src/mainboard/pcengines/apu2/bootorder_map index 41239066dbd..5ca4c0f0830 100644 --- a/src/mainboard/pcengines/apu2/bootorder_map +++ b/src/mainboard/pcengines/apu2/bootorder_map @@ -1,8 +1,8 @@ -a USB 1 SS -b USB 2 SS -c USB 1 HS -d USB 2 HS -e SDCARD -f mSATA -g SATA -h iPXE +a USB 1 / USB 2 SS and HS +a USB 1 / USB 2 SS and HS +a USB 1 / USB 2 SS and HS +a USB 1 / USB 2 SS and HS +b SDCARD +c mSATA +d SATA +e iPXE