OpenVAF Crash while Compiling Verilog-A File

[MAFTY22]

nn_verilog_a_l0_2_l1_2_l2_2.va.txt

openvaf-crash-1712820826.log

Issue Description:
OpenVAF encountered a crash while attempting to compile the Verilog-A file nn_verilog_a_l0_2_l1_2_l2_2.va. The error message received was:
OpenVAF encountered a problem and has crashed!
A log file has been generated at "/tmp/openvaf-crash-1712820826.log".
To help us fix the problem, please open an issue at https://github.com/pascalkuthe/OpenVAF/ or send an email to [email protected] and attach the log file.
If possible please also attach the source file that OpenVAF was compiling.

Steps to Reproduce:
Attempt to compile the Verilog-A file nn_verilog_a_l0_2_l1_2_l2_2.va using OpenVAF.
Observe the crash and error message mentioned above.

Expected Behavior:
OpenVAF should be able to compile the Verilog-A file without encountering a crash.

Additional Information:
Attached log file: openvaf-crash-1712820826.log
Source file being compiled: nn_verilog_a_l0_2_l1_2_l2_2.va
Please investigate this issue and provide guidance on resolving the crash. Let me know if any further information is needed. Thank you!

[dwarning]

Declaring one ore more of your real variables as parameter will help. It is a known bug - see #103