Verilog-A features unavailable in OpenVAF

[mikewu99]

I am in the process of using OpenVAF to port some mixed electrical and non-electrical models into ngspice. I have already discovered that I need to convert my non-electrical disciplines into electrical disciplines to "fool" OpenVAF to compile. I also discovered that arrayed ports are not supported (which makes sense since SPICE does not support arrayed ports).

OpenVAF apparently does not support arrays internal to a module either, nor does it support genvars. Is this correct? This makes it difficult to code some complex models since generate loops need to be unwound and arrays expanded into a bunch of individual variables.

Is there a comprehensive list of what Verilog-A constructs OpenVAF suports? I only found two things mentioned in the online documentation.