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Index: CMakeLists.txt
===================================================================
--- CMakeLists.txt (revision 272794)
+++ CMakeLists.txt (working copy)
@@ -42,6 +42,7 @@
rtl/tsan_report.cc
rtl/tsan_rtl.cc
rtl/tsan_rtl_mutex.cc
+ rtl/tsan_relaxed.cc
rtl/tsan_rtl_proc.cc
rtl/tsan_rtl_report.cc
rtl/tsan_rtl_thread.cc
@@ -84,6 +85,7 @@
rtl/tsan_mutex.h
rtl/tsan_mutexset.h
rtl/tsan_platform.h
+ rtl/tsan_relaxed.h
rtl/tsan_report.h
rtl/tsan_rtl.h
rtl/tsan_stack_trace.h
Index: rtl/tsan_clock.cc
===================================================================
--- rtl/tsan_clock.cc (revision 272794)
+++ rtl/tsan_clock.cc (working copy)
@@ -158,14 +158,14 @@
}
}
-void ThreadClock::release(ClockCache *c, SyncClock *dst) const {
+void ThreadClock::release(ClockCache *c, VClockCache *vc, SyncClock *dst) const {
DCHECK_LE(nclk_, kMaxTid);
DCHECK_LE(dst->size_, kMaxTid);
- if (dst->size_ == 0) {
+ if (dst->size_ == 0) { // TODO used by locks, not yet compatible with VVC.
// ReleaseStore will correctly set release_store_tid_,
// which can be important for future operations.
- ReleaseStore(c, dst);
+ ReleaseStore(c, vc, dst);
return;
}
@@ -212,11 +212,17 @@
dst->elem(tid_).reused = reused_;
}
-void ThreadClock::ReleaseStore(ClockCache *c, SyncClock *dst) const {
+void ThreadClock::ReleaseStore(ClockCache *c, VClockCache *vc, SyncClock *dst) const {
DCHECK_LE(nclk_, kMaxTid);
DCHECK_LE(dst->size_, kMaxTid);
CPP_STAT_INC(StatClockStore);
+ // If vvc is in use, must reset then release.
+ if (dst->vvc_in_use_) {
+ CPP_STAT_INC(StatCollapseVVC);
+ dst->Reset(c, vc);
+ }
+
// Check if we need to resize dst.
if (dst->size_ < nclk_)
dst->Resize(c, nclk_);
@@ -253,10 +259,10 @@
dst->elem(tid_).reused = reused_;
}
-void ThreadClock::acq_rel(ClockCache *c, SyncClock *dst) {
+void ThreadClock::acq_rel(ClockCache *c, VClockCache *vc, SyncClock *dst) {
CPP_STAT_INC(StatClockAcquireRelease);
acquire(c, dst);
- ReleaseStore(c, dst);
+ ReleaseStore(c, vc, dst);
}
// Updates only single element related to the current thread in dst->clk_.
@@ -371,7 +377,9 @@
, release_store_reused_()
, tab_()
, tab_idx_()
- , size_() {
+ , size_()
+ , vclock_()
+ , vvc_in_use_() {
for (uptr i = 0; i < kDirtyTids; i++)
dirty_tids_[i] = kInvalidTid;
}
@@ -383,7 +391,50 @@
CHECK_EQ(tab_idx_, 0);
}
-void SyncClock::Reset(ClockCache *c) {
+void SyncClock::CopyClock(ClockCache *c, VClockCache *vc, SyncClock *dst) const {
+ // Must copy to empty clock.
+ //CHECK_EQ(dst->size_, 0);
+ //CHECK_EQ(dst->tab_, 0);
+ //CHECK_EQ(dst->tab_idx_, 0);
+ dst->Reset(c, vc);
+
+ if (size_ == 0)
+ return;
+ dst->Resize(c, size_);
+
+ // Copy raw data, this is duplicated, needs cleaning.
+ if (dst->size_ <= ClockBlock::kClockCount) {
+ internal_memcpy(dst->tab_, tab_, sizeof(*dst->tab_));
+ } else {
+ for (unsigned idx = 0; idx < dst->size_; idx += ClockBlock::kClockCount) {
+ u32 tab_idx = tab_->table[idx / ClockBlock::kClockCount];
+ ClockBlock *cb = ctx->clock_alloc.Map(tab_idx);
+ tab_idx = dst->tab_->table[idx / ClockBlock::kClockCount];
+ ClockBlock *cb_new = ctx->clock_alloc.Map(tab_idx);
+ internal_memcpy(cb_new->clock, cb->clock, sizeof(*cb->clock));
+ }
+ }
+}
+
+void SyncClock::JoinClock(ClockCache *c, SyncClock *src) {
+ if (src->size_ > size_)
+ Resize(c, src->size_);
+
+ for (uptr i = 0; i < src->size_; i++) {
+ ClockElem &ce = elem(i);
+ ClockElem &src_ce = src->elem(i);
+ ce.epoch = max(ce.epoch, src_ce.epoch);
+ ce.reused = 0;
+ }
+
+ // Not really sure what this does but w/e we'll go with it.
+ for (unsigned i = 0; i < kDirtyTids; i++)
+ dirty_tids_[i] = kInvalidTid;
+ release_store_tid_ = kInvalidTid;
+ release_store_reused_ = 0;
+}
+
+void SyncClock::Reset(ClockCache *c, VClockCache *vc) {
if (size_ == 0) {
// nothing
} else if (size_ <= ClockBlock::kClockCount) {
@@ -402,6 +453,25 @@
release_store_reused_ = 0;
for (uptr i = 0; i < kDirtyTids; i++)
dirty_tids_[i] = kInvalidTid;
+
+ // For the VVC
+ if (vvc_in_use_) {
+ for (unsigned idx = 0; idx < VClockBlock::kNumElems; ++idx) {
+ if (vclock_->sizes_[idx] == 0)
+ continue;
+ if (vclock_->sizes_[idx] <= ClockBlock::kClockCount) {
+ ctx->clock_alloc.Free(c, vclock_->clocks_[idx]);
+ } else {
+ ClockBlock *cb = ctx->clock_alloc.Map(vclock_->clocks_[idx]);
+ for (uptr i = 0; i < vclock_->sizes_[idx]; i += ClockBlock::kClockCount)
+ ctx->clock_alloc.Free(c, cb->table[i / ClockBlock::kClockCount]);
+ ctx->clock_alloc.Free(c, vclock_->clocks_[idx]);
+ }
+ vclock_->sizes_[idx] = 0;
+ }
+ ctx->vclock_alloc.Free(vc, vclock_idx_);
+ vvc_in_use_ = false;
+ }
}
ClockElem &SyncClock::elem(unsigned tid) const {
@@ -424,4 +494,167 @@
release_store_tid_, release_store_reused_,
dirty_tids_[0], dirty_tids_[1]);
}
+
+void ThreadClock::NonReleaseStore(ClockCache *c, VClockCache *vc,
+ SyncClock *dst, SyncClock *Frel_clock) const {
+ // No VVC, block if relaxed write is from non-releasing thread.
+ if (!dst->vvc_in_use_) {
+ if (dst->release_store_tid_ != tid_)
+ dst->Reset(c, vc);
+ return;
+ }
+ CPP_STAT_INC(StatCollapseVVC);
+
+ // Try and find VC in VVC for this thread.
+ unsigned idx;
+ for (idx = 0; idx < dst->vclock_->last_free_idx_; ++idx) {
+ if (dst->vclock_->tids_[idx] == tid_)
+ break;
+ }
+
+ // If no VC, block all RS and return.
+ if (idx == dst->vclock_->last_free_idx_) {
+ dst->Reset(c, vc);
+ return;
+ }
+
+ // If VC found, save this RS and block all others.
+ u32 tab_idx = dst->vclock_->clocks_[idx];
+ u32 size = dst->vclock_->sizes_[idx];
+ dst->vclock_->clocks_[idx] = 0;
+ dst->vclock_->sizes_[idx] = 0;
+ dst->Reset(c, vc);
+ dst->tab_idx_ = tab_idx;
+ dst->size_ = size;
+ dst->tab_ = ctx->clock_alloc.Map(tab_idx);
+ dst->release_store_tid_ = tid_;
+}
+
+void ThreadClock::NonReleaseStore2(ClockCache *c, VClockCache *vc, SyncClock *dst, SyncClock *Frel_clock) const {
+ CHECK(dst->release_store_tid_ == tid_ || dst->size_ == 0);
+ if (Frel_clock->size_ != 0 &&
+ (dst->size_ == 0 || (dst->get(tid_) < Frel_clock->get(tid_)))) {
+ Frel_clock->CopyClock(c, vc, dst);
+ dst->release_store_tid_ = tid_;
+ }
+}
+
+void ThreadClock::RMW(ClockCache *c, VClockCache *vc, SyncClock *dst,
+ bool is_acquire, bool is_release,
+ SyncClock *Facq_clock, SyncClock *Frel_clock) {
+ // acquire is simple, just the same as non RMW.
+ if (is_acquire)
+ acquire(c, dst);
+ else
+ Facq_clock->JoinClock(c, dst);
+
+ // If not release, and no fences. All RSs will continue.
+ if (!is_release && Frel_clock->size_ == 0)
+ return;
+
+ // Check for simple case, where there is no current RS or there is one with
+ // the same tid.
+ if (!dst->vvc_in_use_ && (dst->size_ == 0 || dst->release_store_tid_ == tid_)) {
+ if (is_release)
+ release(c, vc, dst);
+ else
+ NonReleaseStore2(c, vc, dst, Frel_clock);
+ return;
+ }
+
+ // In the case of a relaxed RMW, the VVC does not need to change, because:
+ // - If the thread then does a release store, the VVC is not used, as a
+ // normal release to the VC is appropriate.
+ // - If the thread then does a relaxed store, we have:
+ // - The fence occurred before the last release, so Frel < Ct, and so
+ // joining Frel onto the VC won't change anything, leaving it correct.
+ // - The fence occurred after the last release, so setting the VC to Frel as
+ // normal is correct.
+ //
+ // At this point, we have established that there will now be multiple (h)rs.
+ // If the VVC is still not being used, release_tid must be set to a bogus
+ // value so the thread that did the first release knows to clear the VC.
+ if (!is_release) {
+ dst->JoinClock(c, Frel_clock);
+ dst->release_store_tid_ = -1;
+ return;
+ }
+
+ // Not so simple case where vcc is not in use, but need to migrate to it.
+ if (!dst->vvc_in_use_) {
+ CPP_STAT_INC(StatInitVVC);
+ dst->vclock_idx_ = ctx->vclock_alloc.Alloc(vc);
+ dst->vclock_ = ctx->vclock_alloc.Map(dst->vclock_idx_);
+ dst->vclock_->tids_[0] = dst->release_store_tid_;
+ dst->vclock_->clocks_[0] = dst->tab_idx_;
+ dst->vclock_->sizes_[0] = dst->size_;
+ ClockBlock *old_tab = dst->tab_;
+ // Allocate new tabs for SyncVar clock and allocate space equal to old size.
+ uptr nclk = dst->size_;
+ dst->size_ = 0;
+ dst->tab_ = 0;
+ dst->tab_idx_ = 0;
+ dst->Resize(c, nclk);
+ // Set new clock to moved clock, merge will happen later.
+ if (dst->size_ <= ClockBlock::kClockCount) {
+ internal_memcpy(dst->tab_, old_tab, sizeof(*dst->tab_));
+ } else {
+ for (unsigned idx = 0; idx < dst->size_; idx += ClockBlock::kClockCount) {
+ u32 tab_idx = old_tab->table[idx / ClockBlock::kClockCount];
+ ClockBlock *cb = ctx->clock_alloc.Map(tab_idx);
+ tab_idx = dst->tab_->table[idx / ClockBlock::kClockCount];
+ ClockBlock *cb_new = ctx->clock_alloc.Map(tab_idx);
+ internal_memcpy(cb_new->clock, cb->clock, sizeof(*cb->clock));
+ }
+ }
+ dst->vvc_in_use_ = true;
+ dst->vclock_->last_free_idx_ = 1;
+ }
+
+ // vvc is in use and may need to add thread clock to vvc, but before, merge
+ // with the main clock.
+ release(c, vc, dst);
+
+ // Remove existing entry if it exists (easier to do but more expensive).
+ // Create new entry.
+ unsigned idx;
+ for (idx = 0; idx < dst->vclock_->last_free_idx_; ++idx) {
+ if (dst->vclock_->tids_[idx] == tid_)
+ break;
+ }
+ if (idx == VClockBlock::kNumElems) {
+ Printf("Too many VCs for RMW.");
+ Die();
+ }
+ if (idx != dst->vclock_->last_free_idx_) {
+ CPP_STAT_INC(StatModifyVVC);
+ if (dst->vclock_->sizes_[idx] <= ClockBlock::kClockCount) {
+ ctx->clock_alloc.Free(c, dst->vclock_->clocks_[idx]);
+ } else {
+ ClockBlock *cb = ctx->clock_alloc.Map(dst->vclock_->clocks_[idx]);
+ for (uptr i = 0; i < dst->vclock_->sizes_[idx]; i += ClockBlock::kClockCount)
+ ctx->clock_alloc.Free(c, cb->table[i / ClockBlock::kClockCount]);
+ ctx->clock_alloc.Free(c, dst->vclock_->clocks_[idx]);
+ }
+ } else {
+ CPP_STAT_INC(StatAddToVVC);
+ ++dst->vclock_->last_free_idx_;
+ }
+ SyncClock tmp;
+ ReleaseStore(c, vc, &tmp);
+ dst->vclock_->tids_[idx] = tmp.release_store_tid_;
+ dst->vclock_->clocks_[idx] = tmp.tab_idx_;
+ dst->vclock_->sizes_[idx] = tmp.size_;
+ tmp.size_ = 0;
+ tmp.Reset(c, vc);
+}
+
+void ThreadClock::FenceRelease(ClockCache *c, VClockCache *vc, SyncClock *dst) {
+ release(c, vc, dst);
+}
+
+void ThreadClock::FenceAcquire(ClockCache *c, VClockCache *vc, SyncClock *src) {
+ acquire(c, src);
+}
+
} // namespace __tsan
Index: rtl/tsan_clock.h
===================================================================
--- rtl/tsan_clock.h (revision 272794)
+++ rtl/tsan_clock.h (working copy)
@@ -40,12 +40,44 @@
typedef DenseSlabAlloc<ClockBlock, 1<<16, 1<<10> ClockAlloc;
typedef DenseSlabAllocCache ClockCache;
+// Vector of Vector Clocks for the RMW release sequence tracking.
+// When a new thread performs a RMW with release, add mapping from tid -> VC and
+// release the thread's clock to it.
+// When there is a non-RMW of any kind, collapse VVC to just the VC of the
+// performing thread, or empty everything.
+//
+// Associativity and mem management is difficult, so handle everything linearly
+// for now.
+//
+// ThreadClock will handle it, so the SyncClock will have the VVC inside it.
+struct VClockBlock {
+ static const int kNumElems = 80; // Limit VVC to 10 for now.
+
+ VClockBlock() {}
+ ~VClockBlock() {}
+
+ u32 clocks_[kNumElems];
+ unsigned tids_[kNumElems];
+ u32 sizes_[kNumElems];
+ unsigned last_free_idx_;
+};
+
+typedef DenseSlabAlloc<VClockBlock, 1<<16, 1<<10> VClockAlloc;
+typedef DenseSlabAllocCache VClockCache;
+
// The clock that lives in sync variables (mutexes, atomics, etc).
+// TODO: Shallow version for just the tab, allowing us to save space.
+// (no VVC, just a tab).
class SyncClock {
public:
SyncClock();
~SyncClock();
+ // Copies the current state of the clock into dest. Ignores the VVC.
+ void CopyClock(ClockCache *c, VClockCache *vc, SyncClock *dst) const;
+ // Joins the clock in src with this, becoming the piecewise maximum.
+ void JoinClock(ClockCache *c, SyncClock *src);
+
uptr size() const {
return size_;
}
@@ -55,7 +87,7 @@
}
void Resize(ClockCache *c, uptr nclk);
- void Reset(ClockCache *c);
+ void Reset(ClockCache *c, VClockCache *vc);
void DebugDump(int(*printf)(const char *s, ...));
@@ -74,6 +106,11 @@
u32 tab_idx_;
u32 size_;
+ // For RMWs. if multiple RSs are created, use the VCC.
+ VClockBlock *vclock_;
+ u32 vclock_idx_;
+ bool vvc_in_use_;
+
ClockElem &elem(unsigned tid) const;
};
@@ -105,10 +142,17 @@
}
void acquire(ClockCache *c, const SyncClock *src);
- void release(ClockCache *c, SyncClock *dst) const;
- void acq_rel(ClockCache *c, SyncClock *dst);
- void ReleaseStore(ClockCache *c, SyncClock *dst) const;
+ void release(ClockCache *c, VClockCache *vc, SyncClock *dst) const;
+ void acq_rel(ClockCache *c, VClockCache *vc, SyncClock *dst);
+ void ReleaseStore(ClockCache *c, VClockCache *vc, SyncClock *dst) const;
+ // Extras for RS support, we let thread clock code handle it.
+ void NonReleaseStore(ClockCache *c, VClockCache *vc, SyncClock *dst, SyncClock *Frel_clock) const;
+ void NonReleaseStore2(ClockCache *c, VClockCache *vc, SyncClock *dst, SyncClock *Frel_clock) const; // Merge with 1.
+ void RMW(ClockCache *c, VClockCache *vc, SyncClock *dst, bool is_acquire, bool is_release, SyncClock *Facq_clock, SyncClock *Frel_clock);
+ void FenceRelease(ClockCache *c, VClockCache *vc, SyncClock *dst);
+ void FenceAcquire(ClockCache *c, VClockCache *vc, SyncClock *src);
+
void DebugReset();
void DebugDump(int(*printf)(const char *s, ...));
Index: rtl/tsan_defs.h
===================================================================
--- rtl/tsan_defs.h (revision 272794)
+++ rtl/tsan_defs.h (working copy)
@@ -25,7 +25,7 @@
#endif
#ifndef TSAN_COLLECT_STATS
-# define TSAN_COLLECT_STATS 0
+# define TSAN_COLLECT_STATS 0//1
#endif
#ifndef TSAN_CONTAINS_UBSAN
Index: rtl/tsan_interceptors.cc
===================================================================
--- rtl/tsan_interceptors.cc (revision 272794)
+++ rtl/tsan_interceptors.cc (working copy)
@@ -887,6 +887,8 @@
Processor *proc = ProcCreate();
ProcWire(proc, thr);
ThreadStart(thr, tid, GetTid());
+ //atomic_store(&p->tid, 0, memory_order_release);
+ //ThreadStart(thr, tid, GetTid());
atomic_store(&p->tid, 0, memory_order_release);
}
void *res = callback(param);
Index: rtl/tsan_interface.h
===================================================================
--- rtl/tsan_interface.h (revision 272794)
+++ rtl/tsan_interface.h (working copy)
@@ -72,6 +72,9 @@
SANITIZER_INTERFACE_ATTRIBUTE void __tsan_func_entry(void *call_pc);
SANITIZER_INTERFACE_ATTRIBUTE void __tsan_func_exit();
+SANITIZER_INTERFACE_ATTRIBUTE void __tsan_debug_start();
+SANITIZER_INTERFACE_ATTRIBUTE void __tsan_debug_end();
+
SANITIZER_INTERFACE_ATTRIBUTE
void __tsan_read_range(void *addr, unsigned long size); // NOLINT
SANITIZER_INTERFACE_ATTRIBUTE
Index: rtl/tsan_interface_atomic.cc
===================================================================
--- rtl/tsan_interface_atomic.cc (revision 272794)
+++ rtl/tsan_interface_atomic.cc (working copy)
@@ -25,6 +25,7 @@
#include "tsan_flags.h"
#include "tsan_interface.h"
#include "tsan_rtl.h"
+//#include "tsan_relaxed.h"
using namespace __tsan; // NOLINT
@@ -51,9 +52,9 @@
|| mo == mo_acq_rel || mo == mo_seq_cst;
}
-static bool IsAcqRelOrder(morder mo) {
- return mo == mo_acq_rel || mo == mo_seq_cst;
-}
+//static bool IsAcqRelOrder(morder mo) {
+// return mo == mo_acq_rel || mo == mo_seq_cst;
+//}
template<typename T> T func_xchg(volatile T *v, T op) {
T res = __sync_lock_test_and_set(v, op);
@@ -223,18 +224,40 @@
static T AtomicLoad(ThreadState *thr, uptr pc, const volatile T *a,
morder mo) {
CHECK(IsLoadOrder(mo));
+ // Could potentially get the lock in read mode if relaxed load.
+ SyncVar *s = ctx->metamap.GetOrCreateAndLock(thr, pc, (uptr)a, true);
+ // Must acquire the SC lock for whole duration, before accessing buffer.
+ if (mo == mo_seq_cst) {
+ ctx->Smtx.Lock();
+ SCRead(thr, pc);
+ }
+ // Check the store buffer.
+ u64 bits;
+ SyncClock *clock;
+ bool buffered =
+ s->store_buffer.FetchStore(thr, &bits, &clock, mo == mo_seq_cst, false);
+ // Get appropriate values depending on if we read from the buffer.
+ T val;
+ if (!buffered) {
+ val = NoTsanAtomicLoad(a, mo);
+ clock = &s->clock;
+ } else {
+ internal_memcpy(&val, &bits, sizeof(T));
+ }
// This fast-path is critical for performance.
// Assume the access is atomic.
if (!IsAcquireOrder(mo)) {
+ NonAcquireLoadImpl(thr, pc, clock);
+ s->mtx.Unlock();
MemoryReadAtomic(thr, pc, (uptr)a, SizeLog<T>());
- return NoTsanAtomicLoad(a, mo);
+ return val;
}
- SyncVar *s = ctx->metamap.GetOrCreateAndLock(thr, pc, (uptr)a, false);
- AcquireImpl(thr, pc, &s->clock);
- T v = NoTsanAtomicLoad(a, mo);
- s->mtx.ReadUnlock();
+ AcquireImpl(thr, pc, clock);
+ if (mo == mo_seq_cst)
+ ctx->Smtx.Unlock();
+ s->mtx.Unlock();
MemoryReadAtomic(thr, pc, (uptr)a, SizeLog<T>());
- return v;
+ return val;
}
template<typename T>
@@ -254,21 +277,36 @@
morder mo) {
CHECK(IsStoreOrder(mo));
MemoryWriteAtomic(thr, pc, (uptr)a, SizeLog<T>());
+ // Start of critical section
+ __sync_synchronize();
+ SyncVar *s = ctx->metamap.GetOrCreateAndLock(thr, pc, (uptr)a, true);
+ // Increment epoch here, even if relaxed, to enforce CoWR.
+ // Can't increment epoch w/o writing to the trace as well.
+ thr->fast_state.IncrementEpoch();
+ TraceAddEvent(thr, thr->fast_state, EventTypeMop, 0);
+ // Acquire SC lock here for the whole function?
+ if (mo == mo_seq_cst) {
+ ctx->Smtx.Lock();
+ SCWrite(thr, pc);
+ }
+ // Cache the current state of the location in the store buffer.
+ T val = NoTsanAtomicLoad(a, mo);
+ u64 bits = 0;
+ internal_memcpy(&bits, &val, sizeof(T));
+ s->store_buffer.BufferStore(
+ thr, bits, &s->clock, mo == mo_seq_cst, IsReleaseOrder(mo));
// This fast-path is critical for performance.
// Assume the access is atomic.
- // Strictly saying even relaxed store cuts off release sequence,
- // so must reset the clock.
if (!IsReleaseOrder(mo)) {
+ NonReleaseStoreImpl(thr, pc, &s->clock);
NoTsanAtomicStore(a, v, mo);
+ s->mtx.Unlock();
return;
}
- __sync_synchronize();
- SyncVar *s = ctx->metamap.GetOrCreateAndLock(thr, pc, (uptr)a, true);
- thr->fast_state.IncrementEpoch();
- // Can't increment epoch w/o writing to the trace as well.
- TraceAddEvent(thr, thr->fast_state, EventTypeMop, 0);
- ReleaseImpl(thr, pc, &s->clock);
+ ReleaseStoreImpl(thr, pc, &s->clock);
NoTsanAtomicStore(a, v, mo);
+ if (mo == mo_seq_cst)
+ ctx->Smtx.Unlock();
s->mtx.Unlock();
}
@@ -275,22 +313,31 @@
template<typename T, T (*F)(volatile T *v, T op)>
static T AtomicRMW(ThreadState *thr, uptr pc, volatile T *a, T v, morder mo) {
MemoryWriteAtomic(thr, pc, (uptr)a, SizeLog<T>());
- SyncVar *s = 0;
- if (mo != mo_relaxed) {
- s = ctx->metamap.GetOrCreateAndLock(thr, pc, (uptr)a, true);
- thr->fast_state.IncrementEpoch();
- // Can't increment epoch w/o writing to the trace as well.
- TraceAddEvent(thr, thr->fast_state, EventTypeMop, 0);
- if (IsAcqRelOrder(mo))
- AcquireReleaseImpl(thr, pc, &s->clock);
- else if (IsReleaseOrder(mo))
- ReleaseImpl(thr, pc, &s->clock);
- else if (IsAcquireOrder(mo))
- AcquireImpl(thr, pc, &s->clock);
+ // Start of critical section
+ __sync_synchronize();
+ SyncVar *s = ctx->metamap.GetOrCreateAndLock(thr, pc, (uptr)a, true);
+ // Increment epoch here, even if relaxed, to enforce CoWR.
+ // Can't increment epoch w/o writing to the trace as well.
+ thr->fast_state.IncrementEpoch();
+ TraceAddEvent(thr, thr->fast_state, EventTypeMop, 0);
+ // Treat as SC read and write.
+ if (mo == mo_seq_cst) {
+ ctx->Smtx.Lock();
+ SCRead(thr, pc);
+ SCWrite(thr, pc);
}
+ // RMW will always put the thread's pos in mo to the end. Done by BufferStore.
+ // Identical to AtomicStore.
+ T val = NoTsanAtomicLoad(a, mo);
+ u64 bits = 0;
+ internal_memcpy(&bits, &val, sizeof(T));
+ s->store_buffer.BufferStore(
+ thr, bits, &s->clock, mo == mo_seq_cst, IsReleaseOrder(mo));
+ RMWImpl(thr, pc, &s->clock, IsAcquireOrder(mo), IsReleaseOrder(mo));
v = F(a, v);
- if (s)
- s->mtx.Unlock();
+ if (mo == mo_seq_cst)
+ ctx->Smtx.Unlock();
+ s->mtx.Unlock();
return v;
}
@@ -394,7 +441,7 @@
return c;
}
-template<typename T>
+/*template<typename T>
static bool AtomicCAS(ThreadState *thr, uptr pc,
volatile T *a, T *c, T v, morder mo, morder fmo) {
(void)fmo; // Unused because llvm does not pass it yet.
@@ -425,6 +472,56 @@
return true;
*c = pr;
return false;
+}*/
+
+template<typename T>
+static bool AtomicCAS(ThreadState *thr, uptr pc,
+ volatile T *a, T *c, T v, morder mo, morder fmo) {
+ MemoryWriteAtomic(thr, pc, (uptr)a, SizeLog<T>());
+ // Start of critical section
+ __sync_synchronize();
+ SyncVar *s = ctx->metamap.GetOrCreateAndLock(thr, pc, (uptr)a, true);
+ // Increment epoch here, even if relaxed, to enforce CoWR.
+ // Can't increment epoch w/o writing to the trace as well.
+ thr->fast_state.IncrementEpoch();
+ TraceAddEvent(thr, thr->fast_state, EventTypeMop, 0);
+ // If the success order is SC, must acquire the lock in case we succeed.
+ if (mo == mo_seq_cst) {
+ ctx->Smtx.Lock();
+ }
+ // Prepare the previous value in case the CAS succeeds.
+ T val = func_cas(a, *c, v);
+ bool success = val == *c;
+ if (success) {
+ if (mo == mo_seq_cst) {
+ SCRead(thr, pc);
+ SCWrite(thr, pc);
+ }
+ // Store previous value only if successful.
+ u64 bits = 0;
+ internal_memcpy(&bits, &val, sizeof(T));
+ s->store_buffer.BufferStore(
+ thr, bits, &s->clock, mo == mo_seq_cst, IsReleaseOrder(mo));
+ // Don't bother if relaxed, unless some stats need updating.
+ if (mo != mo_relaxed) {
+ // Relaxed RMW should not affect the RS states.
+ RMWImpl(thr, pc, &s->clock, IsAcquireOrder(mo), IsReleaseOrder(mo));
+ }
+ } else {
+ if (fmo == mo_seq_cst) {
+ SCRead(thr, pc);
+ }
+ // Nothing is stored, but the mo pos of this thread moves to the end.
+ s->store_buffer.AdvanceToEnd(thr);
+ *c = val;
+ if (IsAcquireOrder(fmo)) {
+ AcquireImpl(thr, pc, &s->clock);
+ }
+ }
+ if (mo == mo_seq_cst)
+ ctx->Smtx.Unlock();
+ s->mtx.Unlock();
+ return success;
}
template<typename T>
@@ -440,8 +537,26 @@
}
static void AtomicFence(ThreadState *thr, uptr pc, morder mo) {
- // FIXME(dvyukov): not implemented.
__sync_synchronize();
+ if (mo == mo_relaxed) {
+ return;
+ }
+ // Increment epoch to know when the fence occurred in the thread.
+ // Can't increment epoch w/o writing to the trace as well.
+ thr->fast_state.IncrementEpoch();
+ TraceAddEvent(thr, thr->fast_state, EventTypeMop, 0); // Not really a mem op.
+ // Needed for CoRR in the store buffer.
+ if (IsReleaseOrder(mo))
+ thr->last_release = thr->fast_state.epoch();
+ // SC fence
+ if (mo == mo_seq_cst) {
+ ctx->Smtx.Lock();
+ SCFence(thr, pc);
+ }
+ // Acquire and release, let the VC code handle it.
+ FenceImpl(thr, pc, IsLoadOrder(mo), IsReleaseOrder(mo));
+ if (mo == mo_seq_cst)
+ ctx->Smtx.Unlock();
}
#endif
@@ -457,7 +572,7 @@
ThreadState *const thr = cur_thread(); \
if (thr->ignore_interceptors) \
return NoTsanAtomic##func(__VA_ARGS__); \
- AtomicStatInc(thr, sizeof(*a), mo, StatAtomic##func); \
+ AtomicStatInc(thr, sizeof(*a), mo, StatAtomic##func, (StatType)(StatAtomic##func##Relaxed + mo)); \
ScopedAtomic sa(thr, callpc, a, mo, __func__); \
return Atomic##func(thr, pc, __VA_ARGS__); \
/**/
@@ -473,12 +588,15 @@
~ScopedAtomic() {
ProcessPendingSignals(thr_);
FuncExit(thr_);
+ // Scheduling strategy here!
+ //internal_sched_yield(); // random
+ // End scheduling strategy
}
private:
ThreadState *thr_;
};
-static void AtomicStatInc(ThreadState *thr, uptr size, morder mo, StatType t) {
+static void AtomicStatInc(ThreadState *thr, uptr size, morder mo, StatType t, StatType tmo) {
StatInc(thr, StatAtomic);
StatInc(thr, t);
StatInc(thr, size == 1 ? StatAtomic1
@@ -492,6 +610,7 @@
: mo == mo_release ? StatAtomicRelease
: mo == mo_acq_rel ? StatAtomicAcq_Rel
: StatAtomicSeq_Cst);
+ StatInc(thr, tmo);
}
extern "C" {
Index: rtl/tsan_interface_inl.h
===================================================================
--- rtl/tsan_interface_inl.h (revision 272794)
+++ rtl/tsan_interface_inl.h (working copy)
@@ -108,6 +108,14 @@
FuncExit(cur_thread());
}
+void __tsan_debug_start() {
+ cur_thread()->in_debug = true;
+}
+
+void __tsan_debug_end() {
+ cur_thread()->in_debug = false;
+}
+
void __tsan_read_range(void *addr, uptr size) {
MemoryAccessRange(cur_thread(), CALLERPC, (uptr)addr, size, false);
}
Index: rtl/tsan_mutex.cc
===================================================================
--- rtl/tsan_mutex.cc (revision 272794)
+++ rtl/tsan_mutex.cc (working copy)
@@ -44,6 +44,7 @@
/*12 MutexTypeFired*/ {MutexTypeLeaf},
/*13 MutexTypeRacy*/ {MutexTypeLeaf},
/*14 MutexTypeGlobalProc*/ {},
+ /*15 MutexTypeSC*/ {},
};
static bool CanLockAdj[MutexTypeCount][MutexTypeCount];
Index: rtl/tsan_mutex.h
===================================================================
--- rtl/tsan_mutex.h (revision 272794)
+++ rtl/tsan_mutex.h (working copy)
@@ -35,6 +35,7 @@
MutexTypeFired,
MutexTypeRacy,
MutexTypeGlobalProc,
+ MutexTypeSC,
// This must be the last.
MutexTypeCount
Index: rtl/tsan_platform.h
===================================================================
--- rtl/tsan_platform.h (revision 272794)
+++ rtl/tsan_platform.h (working copy)
@@ -244,9 +244,31 @@
static const uptr kVdsoBeg = 0x7800000000000000ull;
};
+//<<<<<<< .mine
+// Fits all user memory into the shadow memory space.
+//
+// Module and stack memory is 7e80 0000 0000 - 7fff ffff ffff
+// 7e80 0000 0000 - 7eff ffff ffff maps to 0200 0000 0000 - 03ff ffff ffff
+// 7f00 0000 0000 - 7fff ffff ffff maps to 0400 0000 0000 - 07ff ffff ffff
+//
+// Static memory is 0000 0000 1000 - 0100 0000 0000
+// which maps to 0800 0000 4000 - 0bff ffff ffff
+//
+// Heap memory is 7d00 0000 0000 - 7dff ffff ffff
+// which maps to 0c00 0000 0000 - 0fff ffff ffff
+//
+// Shadow memory region 0800 0000 0000 - 0800 0000 3fff is unused.
+//ALWAYS_INLINE
+//uptr MemToShadow(uptr x) {
+// DCHECK(IsAppMem(x));
+// return (((x) & ~(kAppMemMsk | (kShadowCell - 1)))
+// ^ kAppMemXor) * kShadowCnt;
+//}
+//=======
// Indicates the runtime will define the memory regions at runtime.
#define TSAN_RUNTIME_VMA 1
#endif
+//>>>>>>> .r272794
#elif defined(SANITIZER_GO) && !SANITIZER_WINDOWS
Index: rtl/tsan_relaxed.cc
===================================================================
--- rtl/tsan_relaxed.cc (revision 0)
+++ rtl/tsan_relaxed.cc (working copy)
@@ -0,0 +1,341 @@
+// TODO Do not commit load when a release has happened until the load reads later
+// in mo.
+// TODO Put latest store in buffer instead of treating it specially.
+
+#include "tsan_relaxed.h"
+
+#include "tsan_clock.h"
+#include "tsan_rtl.h"
+#include "sanitizer_common/sanitizer_placement_new.h"
+
+namespace __tsan {
+
+// Fetch the value in the tsc register (x86).
+// Can be used as a random value (for the lower bits).
+static inline u64 rdtsc() {
+ u64 ret;
+ asm volatile ("rdtsc; " // read of tsc
+ "shl $32,%%rdx; " // shift higher 32 bits stored in rdx up
+ "or %%rdx,%%rax" // and or onto rax
+ : "=a"(ret) // output to tsc
+ :
+ : "%rcx", "%rdx", "memory"); // rcx and rdx are clobbered
+ // memory to prevent reordering
+ return ret;
+}
+
+StoreBuffer::StoreBuffer() {
+ Reset(0);
+}
+
+void StoreBuffer::Reset(Processor *proc) {
+ last_pos_ = 0;
+ size_ = 0;
+ prev_tid_ = 0;
+ prev_is_sc_access_ = false;
+ prev_epoch_ = 0;
+ //internal_memset(pos_, 0, sizeof(*pos_));
+ //internal_memset(loads_, 0, sizeof(*loads_));
+ internal_memset(pos_, 0, sizeof(pos_));
+ internal_memset(loads_, 0, sizeof(loads_));
+ if (proc == 0) {
+ CHECK_EQ(stores_, 0);
+ CHECK_EQ(stores_back_, 0);
+ CHECK_EQ(prev_loads_, 0);
+ return;
+ }
+ StoreElem *current = stores_;
+ while (current != 0) {
+ LoadElem *load = current->loads_;
+ while (load != 0) {
+ LoadElem *next = load->next_;
+ ctx->load_alloc.Free(&proc->load_cache, load->id_);
+ load = next;
+ }
+ StoreElem *next = current->next_;
+ current->clock_.Reset(&proc->clock_cache, 0);
+ ctx->store_alloc.Free(&proc->store_cache, current->id_);
+ current = next;
+ }
+ stores_ = 0;
+ stores_back_ = 0;
+ LoadElem *load = prev_loads_;
+ while (load != 0) {
+ LoadElem *next = load->next_;
+ ctx->load_alloc.Free(&proc->load_cache, load->id_);
+ load = next;
+ }
+ prev_loads_ = 0;
+}
+
+void StoreBuffer::RemoveLoadFromList(LoadElem *load) {
+ if (load->next_ != 0)
+ load->next_->prev_ = load->prev_;
+ if (load->prev_ != 0) {
+ load->prev_->next_ = load->next_;
+ } else {
+ if (load->store_ != 0) {
+ load->store_->loads_ = load->next_;
+ } else {
+ prev_loads_ = load->next_;
+ }
+ }
+}
+
+void StoreBuffer::AddLoadToList(LoadElem *load, StoreElem *store) {
+ load->store_ = store;
+ load->prev_ = 0;
+ if (store != 0) {
+ load->next_ = store->loads_;
+ store->loads_ = load;
+ } else {
+ load->next_ = prev_loads_;
+ prev_loads_ = load;
+ }
+ if (load->next_ != 0)
+ load->next_->prev_ = load;
+}
+
+void StoreBuffer::BufferStore(ThreadState *thr, u64 bits, SyncClock *clock,
+ bool is_sc_access, bool is_release) {
+ StoreElem *elem = 0;
+ if (!stores_) {
+ StatInc(thr, StatUniqueStore);
+ }
+ // Cap the buffer size, otherwise it will grow very large.
+ if (stores_ && last_pos_ - stores_->pos_ > kBuffMaxSize) {
+ // Remove elem from the front, free clock and loads.
+ StatInc(thr, StatStoreElemFall);
+ elem = stores_;
+ stores_ = stores_->next_;
+ if (stores_ != 0)
+ stores_->prev_ = 0;
+ for (LoadElem *load = elem->loads_; load != 0;) {
+ StatInc(thr, StatLoadElemFall);
+ if (loads_[load->tid_] == load)
+ loads_[load->tid_] = 0;
+ LoadElem *next = load->next_;
+ ctx->load_alloc.Free(&thr->proc()->load_cache, load->id_);
+ load = next;
+ }
+ elem->clock_.Reset(&thr->proc()->clock_cache, 0);
+ } else {
+ // Otherwise, allocate new elem.
+ StatInc(thr, StatStoreElemCreate);
+ u32 id = ctx->store_alloc.Alloc(&thr->proc()->store_cache);
+ elem = ctx->store_alloc.Map(id);
+ elem->id_ = id;
+ }
+
+ // Set up the StoreElem for the previous store.
+ elem->pos_ = ++last_pos_;
+ elem->epoch_ = prev_epoch_;
+ clock->CopyClock(
+ &thr->proc()->clock_cache, &thr->proc()->vclock_cache, &elem->clock_);
+ elem->tid_ = prev_tid_;
+ elem->is_sc_access_ = prev_is_sc_access_;
+ elem->value_ = bits;
+ elem->loads_ = prev_loads_;
+ for (LoadElem *load = prev_loads_; load != 0; load = load->next_)
+ load->store_ = elem;
+ if (stores_ == 0) {
+ stores_ = elem;
+ elem->prev_ = 0;
+ } else {
+ stores_back_->next_ = elem;
+ elem->prev_ = stores_back_;
+ }
+ stores_back_ = elem;
+ elem->next_ = 0;
+ // Threads pos in mo is now the front. This assumes the thread is about to
+ // perform a store.
+ pos_[thr->tid] = last_pos_ + 1;
+ // Store this thread's info for the next buffer store.
+ prev_epoch_ = thr->fast_state.epoch();
+ prev_is_sc_access_ = is_sc_access;
+ prev_tid_ = thr->tid;
+ prev_loads_ = 0;
+
+ // For SC stores, very inefficient, but no better solution right now.
+ // Mark every store that happens before this as SC, when fetch store is called
+ // for SC read, it will skip over these.
+ if (is_sc_access)
+ for (StoreElem *current = stores_back_; current != 0; current = current->prev_) {