TangNano4K/20K support

[Krasnomakov]

          Not as-is since at least the constraints would need to be changed as this is for the Tang Nano 9K. But most of them should be pretty straight forward to port.

For example is there a specific one you were looking at ? I can maybe help walk you through the changes required

Originally posted by @lushaylabs in #3 (comment)

        Have issues with 9k and 20k boards 
        
        For 20K rates mismatch
        

        For 9K can't find pins e.g. it can't find pin45 sys_clk
        
        Starting PnR with NextPnR
Series:GW1N-9C Device:GW1NR-9C Package:QFN88P Speed:C6/I5
ERROR: Pin 45 not found (pin# style)

[lushaylabs]

Hi, can you share the .cst file you are using, as I don't think there is a pin 45, if you are referring to the main clk then it should be set to pin 52 on the tang nano 9k and to pin 4 on the tang nano 20k as those are the pads connected to the internal clock.