Bus logic operations

[renau]

In several of our key benchmarks (BOOM, Rocket...), we have a high percentage of cells using buses.

I mean, we do xor or and for a bus not a single bit wire. Checking BOOM, over 10% of the gates
are for buses, since they are multibit, if I flatten the number of gates more than doubles. We could "flatten" the wire to use mockturle bit representation, but it is an unnecessary overhead. Also, different bits can have slightly different (but equally good) results break symmetry.

Do you have anything on the plan to handle buses? (notice, this is not the same as nary functions that you have)