From 69b8bccd76bd7c2c95784cfc04b3d7d7598918b0 Mon Sep 17 00:00:00 2001 From: Travis Geiselbrecht Date: Sun, 16 Jun 2024 22:16:33 -0700 Subject: [PATCH] [riscv] switch stimecmp/stimecmph registers to using the raw integer format Though using the named nmemonics is a generally better idea it has the unforunate property of not working on older compilers. In this case, these new registers are for the Sstic extension, which is new enough that even reasonably recent compilers as GCC 12.1 doesn't understand it. Fixes issue #410 --- arch/riscv/include/arch/riscv.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/arch/riscv.h b/arch/riscv/include/arch/riscv.h index 21c05dec3..e1e1f0c2e 100644 --- a/arch/riscv/include/arch/riscv.h +++ b/arch/riscv/include/arch/riscv.h @@ -38,6 +38,8 @@ #define RISCV_CSR_TIMEH (0xc81) #define RISCV_CSR_INSRETH (0xc82) +// CSRs that exist in both machine and supervisor mode. Synthesize the appropriate +// one based on prefixing the name with either m or s. #define RISCV_CSR_XSTATUS __CONCAT(RISCV_MODE_PREFIX, status) #define RISCV_CSR_XIE __CONCAT(RISCV_MODE_PREFIX, ie) #define RISCV_CSR_XTVEC __CONCAT(RISCV_MODE_PREFIX, tvec) @@ -59,8 +61,8 @@ #if RISCV_S_MODE // Supervisor-mode only CSRs #define RISCV_CSR_SATP satp // sstc feature -#define RISCV_CSR_STIMECMP stimecmp -#define RISCV_CSR_STIMECMPH stimecmph +#define RISCV_CSR_STIMECMP (0x14d) +#define RISCV_CSR_STIMECMPH (0x15d) #endif #define RISCV_CSR_XSTATUS_IE (1ul << (RISCV_XMODE_OFFSET + 0))