From f713e45fc97200feb84c24c42baa665dddc78c62 Mon Sep 17 00:00:00 2001 From: Martin Schoeberl Date: Thu, 25 Jul 2024 13:51:45 +0200 Subject: [PATCH] Fix some Chisel 6 warnings --- src/main/scala/leros/InstrMem.scala | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/main/scala/leros/InstrMem.scala b/src/main/scala/leros/InstrMem.scala index 2edf9a9..f4bacad 100644 --- a/src/main/scala/leros/InstrMem.scala +++ b/src/main/scala/leros/InstrMem.scala @@ -1,6 +1,7 @@ package leros import chisel3._ +import chisel3.util._ import leros.util.Assembler @@ -21,5 +22,6 @@ class InstrMem(memAddrWidth: Int, prog: String) extends Module { val progMem = VecInit(code.toIndexedSeq.map(_.asUInt(16.W))) val memReg = RegInit(0.U(memAddrWidth.W)) memReg := io.addr - io.instr := progMem(memReg) + val index = log2Ceil(code.length) + io.instr := progMem(memReg(index - 1, 0)) }