From 36e974ef2bb5381b5d192ca86f6b151dc9de7bb6 Mon Sep 17 00:00:00 2001 From: YannLocatelli Date: Thu, 14 May 2020 19:39:15 +0200 Subject: [PATCH] Test - Sensors (#5) Test all sensors on the board. --- LKExp-mbed-sensors/.mbed | 4 + LKExp-mbed-sensors/.mbedignore | 24 + LKExp-mbed-sensors/README.md | 40 + .../lib/mbed-ST_lib/Device/GyroSensor.h | 126 + .../lib/mbed-ST_lib/Device/HumiditySensor.h | 72 + .../lib/mbed-ST_lib/Device/MagneticSensor.h | 89 + .../lib/mbed-ST_lib/Device/MotionSensor.h | 126 + .../lib/mbed-ST_lib/Device/TempSensor.h | 91 + .../lib/mbed-ST_lib/Drivers/Component.h | 81 + .../Drivers/HTS221/HTS221Sensor.cpp | 296 + .../mbed-ST_lib/Drivers/HTS221/HTS221Sensor.h | 145 + .../Drivers/HTS221/HTS221_driver.c | 1056 ++ .../Drivers/HTS221/HTS221_driver.h | 507 + .../Drivers/LSM303AGR/LSM303AGRAccSensor.cpp | 648 ++ .../Drivers/LSM303AGR/LSM303AGRAccSensor.h | 167 + .../Drivers/LSM303AGR/LSM303AGRMagSensor.cpp | 352 + .../Drivers/LSM303AGR/LSM303AGRMagSensor.h | 145 + .../Drivers/LSM303AGR/LSM303AGR_acc_driver.c | 3950 +++++++ .../Drivers/LSM303AGR/LSM303AGR_acc_driver.h | 1608 +++ .../Drivers/LSM303AGR/LSM303AGR_mag_driver.c | 1639 +++ .../Drivers/LSM303AGR/LSM303AGR_mag_driver.h | 766 ++ .../Drivers/LSM6DSOX/LSM6DSOXSensor.cpp | 2667 +++++ .../Drivers/LSM6DSOX/LSM6DSOXSensor.h | 319 + .../Drivers/LSM6DSOX/lsm6dsox_reg.c | 9520 +++++++++++++++++ .../Drivers/LSM6DSOX/lsm6dsox_reg.h | 2935 +++++ .../lib/mbed-ST_lib/Interface/DevI2C.h | 122 + LKExp-mbed-sensors/lib/mbed-os.lib | 1 + LKExp-mbed-sensors/mbed_app.json | 8 + LKExp-mbed-sensors/src/board.cpp | 25 + LKExp-mbed-sensors/src/board.h | 26 + LKExp-mbed-sensors/src/main.cpp | 9 + 31 files changed, 27564 insertions(+) create mode 100644 LKExp-mbed-sensors/.mbed create mode 100644 LKExp-mbed-sensors/.mbedignore create mode 100644 LKExp-mbed-sensors/README.md create mode 100644 LKExp-mbed-sensors/lib/mbed-ST_lib/Device/GyroSensor.h create mode 100644 LKExp-mbed-sensors/lib/mbed-ST_lib/Device/HumiditySensor.h create mode 100644 LKExp-mbed-sensors/lib/mbed-ST_lib/Device/MagneticSensor.h create mode 100644 LKExp-mbed-sensors/lib/mbed-ST_lib/Device/MotionSensor.h create mode 100644 LKExp-mbed-sensors/lib/mbed-ST_lib/Device/TempSensor.h create mode 100644 LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/Component.h create mode 100644 LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/HTS221/HTS221Sensor.cpp create mode 100644 LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/HTS221/HTS221Sensor.h create mode 100644 LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/HTS221/HTS221_driver.c create mode 100644 LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/HTS221/HTS221_driver.h create mode 100644 LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/LSM303AGR/LSM303AGRAccSensor.cpp create mode 100644 LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/LSM303AGR/LSM303AGRAccSensor.h create mode 100644 LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/LSM303AGR/LSM303AGRMagSensor.cpp create mode 100644 LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/LSM303AGR/LSM303AGRMagSensor.h create mode 100644 LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/LSM303AGR/LSM303AGR_acc_driver.c create mode 100644 LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/LSM303AGR/LSM303AGR_acc_driver.h create mode 100644 LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/LSM303AGR/LSM303AGR_mag_driver.c create mode 100644 LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/LSM303AGR/LSM303AGR_mag_driver.h create mode 100644 LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/LSM6DSOX/LSM6DSOXSensor.cpp create mode 100644 LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/LSM6DSOX/LSM6DSOXSensor.h create mode 100644 LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/LSM6DSOX/lsm6dsox_reg.c create mode 100644 LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/LSM6DSOX/lsm6dsox_reg.h create mode 100644 LKExp-mbed-sensors/lib/mbed-ST_lib/Interface/DevI2C.h create mode 100644 LKExp-mbed-sensors/lib/mbed-os.lib create mode 100644 LKExp-mbed-sensors/mbed_app.json create mode 100644 LKExp-mbed-sensors/src/board.cpp create mode 100644 LKExp-mbed-sensors/src/board.h create mode 100644 LKExp-mbed-sensors/src/main.cpp diff --git a/LKExp-mbed-sensors/.mbed b/LKExp-mbed-sensors/.mbed new file mode 100644 index 0000000..2f2e881 --- /dev/null +++ b/LKExp-mbed-sensors/.mbed @@ -0,0 +1,4 @@ +MBED_OS_DIR=./lib/mbed-os +TARGET=disco_f769ni +TOOLCHAIN=GCC_ARM +ROOT=. diff --git a/LKExp-mbed-sensors/.mbedignore b/LKExp-mbed-sensors/.mbedignore new file mode 100644 index 0000000..2e82c8b --- /dev/null +++ b/LKExp-mbed-sensors/.mbedignore @@ -0,0 +1,24 @@ +### Ignored directories to speed up compilation time + +test/** +# lib/mbed-os/components/** +lib/mbed-os/features/cellular/** +lib/mbed-os/features/cryptocell/** +lib/mbed-os/features/deprecated_warnings/** + +lib/mbed-os/features/FEATURE_BLE/** +lib/mbed-os/features/FEATURE_BOOTLOADER/** + +lib/mbed-os/features/lorawan/** +lib/mbed-os/features/lwipstack/** + +lib/mbed-os/features/nanostack/** +lib/mbed-os/features/netsocket/** +lib/mbed-os/features/nfc/** +lib/mbed-os/features/unsupported/** + +### Needed directories + +# lib/mbed-os/features/device_key/** +# lib/mbed-os/features/frameworks/** +# lib/mbed-os/features/mbedtls/** diff --git a/LKExp-mbed-sensors/README.md b/LKExp-mbed-sensors/README.md new file mode 100644 index 0000000..5dd0da8 --- /dev/null +++ b/LKExp-mbed-sensors/README.md @@ -0,0 +1,40 @@ +# LKExp-mbed-sensors + +## Goal + +Clean example to use relevant sensors & test differents drivers + +Requested in [issue #4](https://github.com/leka/LekaOS_Explorations/issues/4) + +## Ressources + +[LKExp-mbed-X\_NUCLEO\_IKS01A2](https://github.com/leka/LekaOS_Explorations/tree/master/LKExp-mbed-x-nucleo-iks01a2) + +LSM6DSOX: + +* mbed by ST : [Link](https://os.mbed.com/teams/ST/code/LSM6DSOX/) (commit [`f27ce43dee4f`](https://os.mbed.com/teams/ST/code/LSM6DSOX/#f27ce43dee4f)) +* github by ST : [Link](https://github.com/STMicroelectronics/STMems_Standard_C_drivers/tree/master/lsm6dsox_STdC) +* github by stm32duino : [Link](https://github.com/stm32duino/LSM6DSOX) + +LSM303AGR (only magnetic sensor) + +* mbed by ST : [Link](https://os.mbed.com/teams/ST/code/LSM303AGR/) (commit [`6c7e83ae885e`](https://os.mbed.com/teams/ST/code/LSM303AGR/#6c7e83ae885e)) +* github by ST : [Link](https://github.com/STMicroelectronics/STMems_Standard_C_drivers/tree/master/lsm303agr_STdC) +* github by stm32duino : [Link](https://github.com/stm32duino/LSM303AGR) + +HTS221 + +* mbed by ST : [Link](https://os.mbed.com/teams/ST/code/HTS221/) (commit [`ccf7f36492ae`](https://os.mbed.com/teams/ST/code/HTS221/#ccf7f36492ae)) +* github by ST : [Link](https://github.com/STMicroelectronics/STMems_Standard_C_drivers/tree/master/hts221_STdC) +* github by stm32duino : [Link](https://github.com/stm32duino/HTS221) + +## Construction + +* Board set to [BSP\_DISCO\_F769NI](https://os.mbed.com/teams/ST/code/BSP_DISCO_F769NI/) (mbed) but can be changed to any ST board on mbed with Arduino shield connector. +* `DevI2C.h` come from [X\_NUCLEO\_COMMON](https://os.mbed.com/teams/ST/code/X_NUCLEO_COMMON/), it adapts i2c of mbed to i2c to manage i2c devices proposed by ST. +* `Component.h`, `GyroSensor.h`, `HumiditySensor.h`, `MagneticSensor.h`, `MotionSensor.h` and `TempSensor.h` come from [ST\_INTERFACES](https://os.mbed.com/teams/ST/code/ST_INTERFACES/) are abstract classes to build specific drivers. + +## Execution + +* Plug X\_NUCLEO\_IKS01A2 and STEVAL\_MKI197V1 on Arduino conenctors +* If an error occurs, LED1 turns on (after flash) diff --git a/LKExp-mbed-sensors/lib/mbed-ST_lib/Device/GyroSensor.h b/LKExp-mbed-sensors/lib/mbed-ST_lib/Device/GyroSensor.h new file mode 100644 index 0000000..ff2e7d8 --- /dev/null +++ b/LKExp-mbed-sensors/lib/mbed-ST_lib/Device/GyroSensor.h @@ -0,0 +1,126 @@ +/** + ****************************************************************************** + * @file GyroSensor.h + * @author AST / EST + * @version V0.0.1 + * @date 13-April-2015 + * @brief This file contains the abstract class describing in general + * the interfaces of a gyroscope + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + +/* Define to prevent from recursive inclusion --------------------------------*/ + +#ifndef __GYRO_SENSOR_CLASS_H +#define __GYRO_SENSOR_CLASS_H + + +/* Includes ------------------------------------------------------------------*/ + +#include + + +/* Classes ------------------------------------------------------------------*/ + +/** + * An abstract class for a Gyroscope + */ +class GyroSensor : public Component { +public: + + /** + * @brief Get current gyroscope angular rate X/Y/Z-axes values + * in standard data units [mdps] + * @param[out] p_data Pointer to where to store angular rates to. + * p_data must point to an array of (at least) three elements, where: + * p_data[0] corresponds to X-axis, + * p_data[1] corresponds to Y-axis, and + * p_data[2] corresponds to Z-axis. + * @return 0 in case of success, an error code otherwise + */ + virtual int get_g_axes(int32_t *p_data) = 0; + + /** + * @brief Get current gyroscope raw data X/Y/Z-axes values + * in device sepcific LSB units + * @param[out] p_data Pointer to where to store gyroscope raw data to. + * p_data must point to an array of (at least) three elements, where: + * p_data[0] corresponds to X-axis, + * p_data[1] corresponds to Y-axis, and + * p_data[2] corresponds to Z-axis. + * @return 0 in case of success, an error code otherwise + */ + virtual int get_g_axes_raw(int16_t *p_data) = 0; + + /** + * @brief Get gyroscope's current sensitivity [mdps/LSB] + * @param[out] pf_data Pointer to where the gyroscope's sensitivity is stored to + * @return 0 in case of success, an error code otherwise + */ + virtual int get_g_sensitivity(float *pf_data) = 0; + + /** + * @brief Get gyroscope's current output data rate [Hz] + * @param[out] pf_data Pointer to where the gyroscope output data rate is stored to + * @return 0 in case of success, an error code otherwise + */ + virtual int get_g_odr(float *pf_data) = 0; + + /** + * @brief Set gyroscope's output data rate + * @param[in] odr New value for gyroscope's output data rate in [Hz] + * @return 0 in case of success, an error code otherwise + */ + virtual int set_g_odr(float odr) = 0; + + /** + * @brief Get gyroscope's full scale value + * i.e.\ min/max measurable value [dps] + * @param[out] pf_data Pointer to where the gyroscope full scale value is stored to + * @return 0 in case of success, an error code otherwise + */ + virtual int get_g_fs(float *pf_data) = 0; + + /** + * @brief Set gyroscope's full scale value + * i.e.\ min/max measurable value + * @param[in] fs New full scale value for gyroscope in [dps] + * @return 0 in case of success, an error code otherwise + */ + virtual int set_g_fs(float fs) = 0; + + /** + * @brief Destructor. + */ + virtual ~GyroSensor() {}; +}; + +#endif /* __GYRO_SENSOR_CLASS_H */ diff --git a/LKExp-mbed-sensors/lib/mbed-ST_lib/Device/HumiditySensor.h b/LKExp-mbed-sensors/lib/mbed-ST_lib/Device/HumiditySensor.h new file mode 100644 index 0000000..248b06b --- /dev/null +++ b/LKExp-mbed-sensors/lib/mbed-ST_lib/Device/HumiditySensor.h @@ -0,0 +1,72 @@ +/** + ****************************************************************************** + * @file HumiditySensor.h + * @author AST / EST + * @version V0.0.1 + * @date 13-April-2015 + * @brief This file contains the abstract class describing in general + * the interfaces of a humidity sensor + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + +/* Define to prevent from recursive inclusion --------------------------------*/ + +#ifndef __HUMIDITY_SENSOR_CLASS_H +#define __HUMIDITY_SENSOR_CLASS_H + + +/* Includes ------------------------------------------------------------------*/ + +#include + + +/* Classes ------------------------------------------------------------------*/ + +/** + * An abstract class for Humidity sensors + */ +class HumiditySensor : public Component { +public: + + /** + * @brief Get current humidity [%] + * @param[out] pf_data Pointer to where to store humidity to + * @return 0 in case of success, an error code otherwise + */ + virtual int get_humidity(float *pf_data) = 0; + + /** + * @brief Destructor. + */ + virtual ~HumiditySensor() {}; +}; + +#endif /* __HUMIDITY_SENSOR_CLASS_H */ diff --git a/LKExp-mbed-sensors/lib/mbed-ST_lib/Device/MagneticSensor.h b/LKExp-mbed-sensors/lib/mbed-ST_lib/Device/MagneticSensor.h new file mode 100644 index 0000000..ee9afdf --- /dev/null +++ b/LKExp-mbed-sensors/lib/mbed-ST_lib/Device/MagneticSensor.h @@ -0,0 +1,89 @@ +/** + ****************************************************************************** + * @file MagneticSensor.h + * @author AST / EST + * @version V0.0.1 + * @date 13-April-2015 + * @brief This file contains the abstract class describing in general + * the interfaces of a magnetometer + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + +/* Define to prevent from recursive inclusion --------------------------------*/ + +#ifndef __MAGNETIC_SENSOR_CLASS_H +#define __MAGNETIC_SENSOR_CLASS_H + + +/* Includes ------------------------------------------------------------------*/ + +#include + + +/* Classes ------------------------------------------------------------------*/ + +/** + * An abstract class for a magnetometer + */ +class MagneticSensor : public Component { +public: + + /** + * @brief Get current magnetometer magnetic X/Y/Z-axes values + * in standard data units [mgauss] + * @param[out] p_data Pointer to where to store magnetic values to. + * p_data must point to an array of (at least) three elements, where: + * p_data[0] corresponds to X-axis, + * p_data[1] corresponds to Y-axis, and + * p_data[2] corresponds to Z-axis. + * @return 0 in case of success, an error code otherwise + */ + virtual int get_m_axes(int32_t *p_data) = 0; + + /** + * @brief Get current magnetometer raw data X/Y/Z-axes values + * in device sepcific LSB units + * @param[out] p_data Pointer to where to store magnetometer raw data to. + * p_data must point to an array of (at least) three elements, where: + * p_data[0] corresponds to X-axis, + * p_data[1] corresponds to Y-axis, and + * p_data[2] corresponds to Z-axis. + * @return 0 in case of success, an error code otherwise + */ + virtual int get_m_axes_raw(int16_t *p_data) = 0; + + /** + * @brief Destructor. + */ + virtual ~MagneticSensor() {}; +}; + +#endif /* __MAGNETIC_SENSOR_CLASS_H */ diff --git a/LKExp-mbed-sensors/lib/mbed-ST_lib/Device/MotionSensor.h b/LKExp-mbed-sensors/lib/mbed-ST_lib/Device/MotionSensor.h new file mode 100644 index 0000000..729cb28 --- /dev/null +++ b/LKExp-mbed-sensors/lib/mbed-ST_lib/Device/MotionSensor.h @@ -0,0 +1,126 @@ +/** + ****************************************************************************** + * @file MotionSensor.h + * @author AST / EST + * @version V0.0.1 + * @date 13-April-2015 + * @brief This file contains the abstract class describing in general + * the interfaces of an accelerometer + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + +/* Define to prevent from recursive inclusion --------------------------------*/ + +#ifndef __MOTION_SENSOR_CLASS_H +#define __MOTION_SENSOR_CLASS_H + + +/* Includes ------------------------------------------------------------------*/ + +#include + + +/* Classes ------------------------------------------------------------------*/ + +/** + * An abstract class for an Accelerometer + */ +class MotionSensor : public Component { +public: + + /** + * @brief Get current accelerometer linear acceleration X/Y/Z-axes values + * in standard data units [mg] + * @param[out] p_data Pointer to where to store linear accelerations to. + * p_data must point to an array of (at least) three elements, where: + * p_data[0] corresponds to X-axis, + * p_data[1] corresponds to Y-axis, and + * p_data[2] corresponds to Z-axis. + * @return 0 in case of success, an error code otherwise + */ + virtual int get_x_axes(int32_t *p_data) = 0; + + /** + * @brief Get current accelerometer raw data X/Y/Z-axes values + * in device sepcific LSB units + * @param[out] p_data Pointer to where to store accelerometer raw data to. + * p_data must point to an array of (at least) three elements, where: + * p_data[0] corresponds to X-axis, + * p_data[1] corresponds to Y-axis, and + * p_data[2] corresponds to Z-axis. + * @return 0 in case of success, an error code otherwise + */ + virtual int get_x_axes_raw(int16_t *p_data) = 0; + + /** + * @brief Get accelerometer's current sensitivity [mg/LSB] + * @param[out] pf_data Pointer to where the accelerometer's sensitivity is stored to + * @return 0 in case of success, an error code otherwise + */ + virtual int get_x_sensitivity(float *pf_data) = 0; + + /** + * @brief Get accelerometer's current output data rate [Hz] + * @param[out] pf_data Pointer to where the accelerometer output data rate is stored to + * @return 0 in case of success, an error code otherwise + */ + virtual int get_x_odr(float *pf_data) = 0; + + /** + * @brief Set accelerometer's output data rate + * @param[in] odr New value for accelerometer's output data rate in [Hz] + * @return 0 in case of success, an error code otherwise + */ + virtual int set_x_odr(float odr) = 0; + + /** + * @brief Get accelerometer's full scale value + * i.e.\ min/max measurable value [g] + * @param[out] pf_data Pointer to where the accelerometer full scale value is stored to + * @return 0 in case of success, an error code otherwise + */ + virtual int get_x_fs(float *pf_data) = 0; + + /** + * @brief Set accelerometer's full scale value + * i.e.\ min/max measurable value + * @param[in] fs New full scale value for accelerometer in [g] + * @return 0 in case of success, an error code otherwise + */ + virtual int set_x_fs(float fs) = 0; + + /** + * @brief Destructor. + */ + virtual ~MotionSensor() {}; +}; + +#endif /* __MOTION_SENSOR_CLASS_H */ diff --git a/LKExp-mbed-sensors/lib/mbed-ST_lib/Device/TempSensor.h b/LKExp-mbed-sensors/lib/mbed-ST_lib/Device/TempSensor.h new file mode 100644 index 0000000..bbc216f --- /dev/null +++ b/LKExp-mbed-sensors/lib/mbed-ST_lib/Device/TempSensor.h @@ -0,0 +1,91 @@ +/** + ****************************************************************************** + * @file TempSensor.h + * @author AST / EST + * @version V0.0.1 + * @date 13-April-2015 + * @brief This file contains the abstract class describing in general + * the interfaces of a temperature sensor + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + +/* Define to prevent from recursive inclusion --------------------------------*/ + +#ifndef __TEMP_SENSOR_CLASS_H +#define __TEMP_SENSOR_CLASS_H + + +/* Includes ------------------------------------------------------------------*/ + +#include + + +/* Classes ------------------------------------------------------------------*/ + +/** + * An abstract class for Temperature sensors + */ +class TempSensor : public Component { +public: + + /** + * @brief Get current temperature in degrees Celsius [°C] + * @param[out] pf_data Pointer to where to store temperature to + * @return 0 in case of success, an error code otherwise + */ + virtual int get_temperature(float *pf_data) = 0; + + /** + * @brief Get current temperature in degrees Fahrenheit [°F] + * @param[out] pf_data Pointer to where to store temperature to + * @return 0 in case of success, an error code otherwise + */ + virtual int get_fahrenheit(float *pf_data) { + float celsius; + int ret; + + ret = get_temperature(&celsius); + if (ret) { + return ret; + } + + *pf_data = ((celsius * 1.8f) + 32.0f); + + return 0; + } + + /** + * @brief Destructor. + */ + virtual ~TempSensor() {}; +}; + +#endif /* __TEMP_SENSOR_CLASS_H */ diff --git a/LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/Component.h b/LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/Component.h new file mode 100644 index 0000000..d4b340e --- /dev/null +++ b/LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/Component.h @@ -0,0 +1,81 @@ +/** + ****************************************************************************** + * @file Component.h + * @author AST + * @version V1.0.0 + * @date April 13th, 2015 + * @brief This file contains the abstract class describing the interface of a + * generic component. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + +/* Define to prevent recursive inclusion -------------------------------------*/ + +#ifndef __COMPONENT_CLASS_H +#define __COMPONENT_CLASS_H + + +/* Includes ------------------------------------------------------------------*/ + +#include + + +/* Classes ------------------------------------------------------------------*/ + +/** + * An abstract class for Generic components. + */ +class Component { +public: + + /** + * @brief Initializing the component. + * @param[in] init pointer to device specific initalization structure. + * @retval "0" in case of success, an error code otherwise. + */ + virtual int init(void *init) = 0; + + /** + * @brief Getting the ID of the component. + * @param[out] id pointer to an allocated variable to store the ID into. + * @retval "0" in case of success, an error code otherwise. + */ + virtual int read_id(uint8_t *id) = 0; + + /** + * @brief Destructor. + */ + virtual ~Component() {}; +}; + +#endif /* __COMPONENT_CLASS_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/HTS221/HTS221Sensor.cpp b/LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/HTS221/HTS221Sensor.cpp new file mode 100644 index 0000000..094111c --- /dev/null +++ b/LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/HTS221/HTS221Sensor.cpp @@ -0,0 +1,296 @@ +/** + ****************************************************************************** + * @file HTS221Sensor.cpp + * @author CLab + * @version V1.0.0 + * @date 5 August 2016 + * @brief Implementation of an HTS221 Humidity and Temperature sensor. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + +/* Includes ------------------------------------------------------------------*/ + + +#include "HTS221Sensor.h" + + +/* Class Implementation ------------------------------------------------------*/ + +HTS221Sensor::HTS221Sensor(SPI *spi, PinName cs_pin, PinName drdy_pin) : + _dev_spi(spi), _cs_pin(cs_pin), _drdy_pin(drdy_pin) // SPI3W ONLY +{ + assert(spi); + _dev_i2c = NULL; +}; + +/** Constructor + * @param i2c object of an helper class which handles the I2C peripheral + * @param address the address of the component's instance + */ +HTS221Sensor::HTS221Sensor(DevI2C *i2c, uint8_t address, PinName drdy_pin) : + _dev_i2c(i2c), _address(address), _cs_pin(NC), _drdy_pin(drdy_pin) +{ + assert(i2c); + _dev_spi = NULL; +}; + +/** + * @brief Initializing the component. + * @param[in] init pointer to device specific initalization structure. + * @retval "0" in case of success, an error code otherwise. + */ +int HTS221Sensor::init(void *init) +{ + /* Power down the device */ + if (HTS221_DeActivate((void *)this) == HTS221_ERROR) { + return 1; + } + + /* Enable BDU */ + if (HTS221_Set_BduMode((void *)this, HTS221_ENABLE) == HTS221_ERROR) { + return 1; + } + + if (set_odr(1.0f) == 1) { + return 1; + } + + return 0; +} + +/** + * @brief Enable HTS221 + * @retval 0 in case of success, an error code otherwise + */ +int HTS221Sensor::enable(void) +{ + /* Power up the device */ + if (HTS221_Activate((void *)this) == HTS221_ERROR) { + return 1; + } + + return 0; +} + +/** + * @brief Disable HTS221 + * @retval 0 in case of success, an error code otherwise + */ +int HTS221Sensor::disable(void) +{ + /* Power up the device */ + if (HTS221_DeActivate((void *)this) == HTS221_ERROR) { + return 1; + } + + return 0; +} + +/** + * @brief Read ID address of HTS221 + * @param id the pointer where the ID of the device is stored + * @retval 0 in case of success, an error code otherwise + */ +int HTS221Sensor::read_id(uint8_t *id) +{ + if (!id) { + return 1; + } + + /* Read WHO AM I register */ + if (HTS221_Get_DeviceID((void *)this, id) == HTS221_ERROR) { + return 1; + } + + return 0; +} + +/** + * @brief Reboot memory content of HTS221 + * @param None + * @retval 0 in case of success, an error code otherwise + */ +int HTS221Sensor::reset(void) +{ + uint8_t tmpreg; + + /* Read CTRL_REG2 register */ + if (read_reg(HTS221_CTRL_REG2, &tmpreg) != 0) { + return 1; + } + + /* Enable or Disable the reboot memory */ + tmpreg |= (0x01 << HTS221_BOOT_BIT); + + /* Write value to MEMS CTRL_REG2 regsister */ + if (write_reg(HTS221_CTRL_REG2, tmpreg) != 0) { + return 1; + } + + return 0; +} + +/** + * @brief Read HTS221 output register, and calculate the humidity + * @param pfData the pointer to data output + * @retval 0 in case of success, an error code otherwise + */ +int HTS221Sensor::get_humidity(float *pfData) +{ + uint16_t uint16data = 0; + + /* Read data from HTS221. */ + if (HTS221_Get_Humidity((void *)this, &uint16data) == HTS221_ERROR) { + return 1; + } + + *pfData = (float)uint16data / 10.0f; + + return 0; +} + +/** + * @brief Read HTS221 output register, and calculate the temperature + * @param pfData the pointer to data output + * @retval 0 in case of success, an error code otherwise + */ +int HTS221Sensor::get_temperature(float *pfData) +{ + int16_t int16data = 0; + + /* Read data from HTS221. */ + if (HTS221_Get_Temperature((void *)this, &int16data) == HTS221_ERROR) { + return 1; + } + + *pfData = (float)int16data / 10.0f; + + return 0; +} + +/** + * @brief Read HTS221 output register, and calculate the humidity + * @param odr the pointer to the output data rate + * @retval 0 in case of success, an error code otherwise + */ +int HTS221Sensor::get_odr(float *odr) +{ + HTS221_Odr_et odr_low_level; + + if (HTS221_Get_Odr((void *)this, &odr_low_level) == HTS221_ERROR) { + return 1; + } + + switch (odr_low_level) { + case HTS221_ODR_ONE_SHOT: + *odr = 0.0f; + break; + case HTS221_ODR_1HZ : + *odr = 1.0f; + break; + case HTS221_ODR_7HZ : + *odr = 7.0f; + break; + case HTS221_ODR_12_5HZ : + *odr = 12.5f; + break; + default : + *odr = -1.0f; + return 1; + } + + return 0; +} + +/** + * @brief Set ODR + * @param odr the output data rate to be set + * @retval 0 in case of success, an error code otherwise + */ +int HTS221Sensor::set_odr(float odr) +{ + HTS221_Odr_et new_odr; + + new_odr = (odr <= 1.0f) ? HTS221_ODR_1HZ + : (odr <= 7.0f) ? HTS221_ODR_7HZ + : HTS221_ODR_12_5HZ; + + if (HTS221_Set_Odr((void *)this, new_odr) == HTS221_ERROR) { + return 1; + } + + return 0; +} + + +/** + * @brief Read the data from register + * @param reg register address + * @param data register data + * @retval 0 in case of success + * @retval 1 in case of failure + */ +int HTS221Sensor::read_reg(uint8_t reg, uint8_t *data) +{ + + if (HTS221_read_reg((void *)this, reg, 1, data) == HTS221_ERROR) { + return 1; + } + + return 0; +} + +/** + * @brief Write the data to register + * @param reg register address + * @param data register data + * @retval 0 in case of success + * @retval 1 in case of failure + */ +int HTS221Sensor::write_reg(uint8_t reg, uint8_t data) +{ + + if (HTS221_write_reg((void *)this, reg, 1, &data) == HTS221_ERROR) { + return 1; + } + + return 0; +} + +uint8_t HTS221_io_write(void *handle, uint8_t WriteAddr, uint8_t *pBuffer, uint16_t nBytesToWrite) +{ + return ((HTS221Sensor *)handle)->io_write(pBuffer, WriteAddr, nBytesToWrite); +} + +uint8_t HTS221_io_read(void *handle, uint8_t ReadAddr, uint8_t *pBuffer, uint16_t nBytesToRead) +{ + return ((HTS221Sensor *)handle)->io_read(pBuffer, ReadAddr, nBytesToRead); +} diff --git a/LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/HTS221/HTS221Sensor.h b/LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/HTS221/HTS221Sensor.h new file mode 100644 index 0000000..6986427 --- /dev/null +++ b/LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/HTS221/HTS221Sensor.h @@ -0,0 +1,145 @@ +/** + ****************************************************************************** + * @file HTS221Sensor.h + * @author CLab + * @version V1.0.0 + * @date 5 August 2016 + * @brief Abstract class of an HTS221 Humidity and Temperature sensor. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + +/* Prevent recursive inclusion -----------------------------------------------*/ + +#ifndef __HTS221Sensor_H__ +#define __HTS221Sensor_H__ + + +/* Includes ------------------------------------------------------------------*/ + +#include "DevI2C.h" +#include +#include "HTS221_driver.h" +#include "HumiditySensor.h" +#include "TempSensor.h" +#include + +/* Class Declaration ---------------------------------------------------------*/ + +/** + * Abstract class of an HTS221 Humidity and Temperature sensor. + */ +class HTS221Sensor : public HumiditySensor, public TempSensor { +public: + HTS221Sensor(SPI *spi, PinName cs_pin = NC, PinName drdy_pin = NC); // SPI3W ONLY + HTS221Sensor(DevI2C *i2c, uint8_t address = HTS221_I2C_ADDRESS, PinName drdy_pin = NC); + virtual int init(void *init); + virtual int read_id(uint8_t *id); + virtual int get_humidity(float *pfData); + virtual int get_temperature(float *pfData); + int enable(void); + int disable(void); + int reset(void); + int get_odr(float *odr); + int set_odr(float odr); + int read_reg(uint8_t reg, uint8_t *data); + int write_reg(uint8_t reg, uint8_t data); + /** + * @brief Utility function to read data. + * @param pBuffer: pointer to data to be read. + * @param RegisterAddr: specifies internal address register to be read. + * @param NumByteToRead: number of bytes to be read. + * @retval 0 if ok, an error code otherwise. + */ + uint8_t io_read(uint8_t *pBuffer, uint8_t RegisterAddr, uint16_t NumByteToRead) + { + if (_dev_spi) { + /* Write Reg Address */ + _dev_spi->lock(); + _cs_pin = 0; + /* Write RD Reg Address with RD bit*/ + uint8_t TxByte = RegisterAddr | 0x80; + _dev_spi->write((char *)&TxByte, 1, (char *)pBuffer, (int) NumByteToRead); + _cs_pin = 1; + _dev_spi->unlock(); + return 0; + } + if (_dev_i2c) { + return (uint8_t) _dev_i2c->i2c_read(pBuffer, _address, RegisterAddr, NumByteToRead); + } + return 1; + } + + /** + * @brief Utility function to write data. + * @param pBuffer: pointer to data to be written. + * @param RegisterAddr: specifies internal address register to be written. + * @param NumByteToWrite: number of bytes to write. + * @retval 0 if ok, an error code otherwise. + */ + uint8_t io_write(uint8_t *pBuffer, uint8_t RegisterAddr, uint16_t NumByteToWrite) + { + if (_dev_spi) { + _dev_spi->lock(); + _cs_pin = 0; + _dev_spi->write(RegisterAddr); + _dev_spi->write((char *)pBuffer, (int) NumByteToWrite, NULL, 0); + _cs_pin = 1; + _dev_spi->unlock(); + return 0; + } + if (_dev_i2c) { + return (uint8_t) _dev_i2c->i2c_write(pBuffer, _address, RegisterAddr, NumByteToWrite); + } + return 1; + } + +private: + + /* Helper classes. */ + DevI2C *_dev_i2c; + SPI *_dev_spi; + + /* Configuration */ + uint8_t _address; + DigitalOut _cs_pin; + InterruptIn _drdy_pin; +}; + +#ifdef __cplusplus +extern "C" { +#endif +uint8_t HTS221_io_write(void *handle, uint8_t WriteAddr, uint8_t *pBuffer, uint16_t nBytesToWrite); +uint8_t HTS221_io_read(void *handle, uint8_t ReadAddr, uint8_t *pBuffer, uint16_t nBytesToRead); +#ifdef __cplusplus +} +#endif + +#endif diff --git a/LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/HTS221/HTS221_driver.c b/LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/HTS221/HTS221_driver.c new file mode 100644 index 0000000..ba7d99f --- /dev/null +++ b/LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/HTS221/HTS221_driver.c @@ -0,0 +1,1056 @@ +/** + ****************************************************************************** + * @file HTS221_driver.c + * @author HESA Application Team + * @version V1.1 + * @date 10-August-2016 + * @brief HTS221 driver file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "HTS221_driver.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef USE_FULL_ASSERT_HTS221 +#include +#endif + + +/** @addtogroup Environmental_Sensor +* @{ +*/ + +/** @defgroup HTS221_DRIVER +* @brief HTS221 DRIVER +* @{ +*/ + +/** @defgroup HTS221_Imported_Function_Prototypes +* @{ +*/ + +extern uint8_t HTS221_io_write(void *handle, uint8_t WriteAddr, uint8_t *pBuffer, uint16_t nBytesToWrite); +extern uint8_t HTS221_io_read(void *handle, uint8_t ReadAddr, uint8_t *pBuffer, uint16_t nBytesToRead); + +/** +* @} +*/ + +/** @defgroup HTS221_Private_Function_Prototypes +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup HTS221_Private_Functions +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup HTS221_Public_Functions +* @{ +*/ + +/******************************************************************************* +* Function Name : HTS221_read_reg +* Description : Generic Reading function. It must be fullfilled with either +* : I2C or SPI reading functions +* Input : Register Address +* Output : Data Read +* Return : None +*******************************************************************************/ +HTS221_Error_et HTS221_read_reg(void *handle, uint8_t RegAddr, uint16_t NumByteToRead, uint8_t *Data) +{ + + if (NumByteToRead > 1) { + RegAddr |= 0x80; + } + + if (HTS221_io_read(handle, RegAddr, Data, NumByteToRead)) { + return HTS221_ERROR; + } else { + return HTS221_OK; + } +} + +/******************************************************************************* +* Function Name : HTS221_write_reg +* Description : Generic Writing function. It must be fullfilled with either +* : I2C or SPI writing function +* Input : Register Address, Data to be written +* Output : None +* Return : None +*******************************************************************************/ +HTS221_Error_et HTS221_write_reg(void *handle, uint8_t RegAddr, uint16_t NumByteToWrite, uint8_t *Data) +{ + + if (NumByteToWrite > 1) { + RegAddr |= 0x80; + } + + if (HTS221_io_write(handle, RegAddr, Data, NumByteToWrite)) { + return HTS221_ERROR; + } else { + return HTS221_OK; + } +} + +/** +* @brief Get the version of this driver. +* @param pxVersion pointer to a HTS221_DriverVersion_st structure that contains the version information. +* This parameter is a pointer to @ref HTS221_DriverVersion_st. +* @retval Error code [HTS221_OK, HTS221_ERROR]. +*/ +HTS221_Error_et HTS221_Get_DriverVersion(HTS221_DriverVersion_st *version) +{ + version->Major = HTS221_DRIVER_VERSION_MAJOR; + version->Minor = HTS221_DRIVER_VERSION_MINOR; + version->Point = HTS221_DRIVER_VERSION_POINT; + + return HTS221_OK; +} + +/** +* @brief Get device type ID. +* @param *handle Device handle. +* @param deviceid pointer to the returned device type ID. +* @retval Error code [HTS221_OK, HTS221_ERROR]. +*/ +HTS221_Error_et HTS221_Get_DeviceID(void *handle, uint8_t *deviceid) +{ + if (HTS221_read_reg(handle, HTS221_WHO_AM_I_REG, 1, deviceid)) { + return HTS221_ERROR; + } + + return HTS221_OK; +} + +/** +* @brief Initializes the HTS221 with the specified parameters in HTS221_Init_st struct. +* @param *handle Device handle. +* @param pxInit pointer to a HTS221_Init_st structure that contains the configuration. +* This parameter is a pointer to @ref HTS221_Init_st. +* @retval Error code [HTS221_OK, HTS221_ERROR]. +*/ +HTS221_Error_et HTS221_Set_InitConfig(void *handle, HTS221_Init_st *pxInit) +{ + uint8_t buffer[3]; + + HTS221_assert_param(IS_HTS221_AVGH(pxInit->avg_h)); + HTS221_assert_param(IS_HTS221_AVGT(pxInit->avg_t)); + HTS221_assert_param(IS_HTS221_ODR(pxInit->odr)); + HTS221_assert_param(IS_HTS221_State(pxInit->bdu_status)); + HTS221_assert_param(IS_HTS221_State(pxInit->heater_status)); + + HTS221_assert_param(IS_HTS221_DrdyLevelType(pxInit->irq_level)); + HTS221_assert_param(IS_HTS221_OutputType(pxInit->irq_output_type)); + HTS221_assert_param(IS_HTS221_State(pxInit->irq_enable)); + + if (HTS221_read_reg(handle, HTS221_AV_CONF_REG, 1, buffer)) { + return HTS221_ERROR; + } + + buffer[0] &= ~(HTS221_AVGH_MASK | HTS221_AVGT_MASK); + buffer[0] |= (uint8_t)pxInit->avg_h; + buffer[0] |= (uint8_t)pxInit->avg_t; + + if (HTS221_write_reg(handle, HTS221_AV_CONF_REG, 1, buffer)) { + return HTS221_ERROR; + } + + if (HTS221_read_reg(handle, HTS221_CTRL_REG1, 3, buffer)) { + return HTS221_ERROR; + } + + buffer[0] &= ~(HTS221_BDU_MASK | HTS221_ODR_MASK); + buffer[0] |= (uint8_t)pxInit->odr; + buffer[0] |= ((uint8_t)pxInit->bdu_status) << HTS221_BDU_BIT; + + buffer[1] &= ~HTS221_HEATHER_BIT; + buffer[1] |= ((uint8_t)pxInit->heater_status) << HTS221_HEATHER_BIT; + + buffer[2] &= ~(HTS221_DRDY_H_L_MASK | HTS221_PP_OD_MASK | HTS221_DRDY_MASK); + buffer[2] |= ((uint8_t)pxInit->irq_level) << HTS221_DRDY_H_L_BIT; + buffer[2] |= (uint8_t)pxInit->irq_output_type; + buffer[2] |= ((uint8_t)pxInit->irq_enable) << HTS221_DRDY_BIT; + + if (HTS221_write_reg(handle, HTS221_CTRL_REG1, 3, buffer)) { + return HTS221_ERROR; + } + + return HTS221_OK; +} + +/** +* @brief Returns a HTS221_Init_st struct with the actual configuration. +* @param *handle Device handle. +* @param pxInit pointer to a HTS221_Init_st structure. +* This parameter is a pointer to @ref HTS221_Init_st. +* @retval Error code [HTS221_OK, HTS221_ERROR]. +*/ +HTS221_Error_et HTS221_Get_InitConfig(void *handle, HTS221_Init_st *pxInit) +{ + uint8_t buffer[3]; + + if (HTS221_read_reg(handle, HTS221_AV_CONF_REG, 1, buffer)) { + return HTS221_ERROR; + } + + pxInit->avg_h = (HTS221_Avgh_et)(buffer[0] & HTS221_AVGH_MASK); + pxInit->avg_t = (HTS221_Avgt_et)(buffer[0] & HTS221_AVGT_MASK); + + if (HTS221_read_reg(handle, HTS221_CTRL_REG1, 3, buffer)) { + return HTS221_ERROR; + } + + pxInit->odr = (HTS221_Odr_et)(buffer[0] & HTS221_ODR_MASK); + pxInit->bdu_status = (HTS221_State_et)((buffer[0] & HTS221_BDU_MASK) >> HTS221_BDU_BIT); + pxInit->heater_status = (HTS221_State_et)((buffer[1] & HTS221_HEATHER_MASK) >> HTS221_HEATHER_BIT); + + pxInit->irq_level = (HTS221_DrdyLevel_et)(buffer[2] & HTS221_DRDY_H_L_MASK); + pxInit->irq_output_type = (HTS221_OutputType_et)(buffer[2] & HTS221_PP_OD_MASK); + pxInit->irq_enable = (HTS221_State_et)((buffer[2] & HTS221_DRDY_MASK) >> HTS221_DRDY_BIT); + + return HTS221_OK; +} + +/** +* @brief De initialization function for HTS221. +* This function put the HTS221 in power down, make a memory boot and clear the data output flags. +* @param *handle Device handle. +* @retval Error code [HTS221_OK, HTS221_ERROR]. +*/ +HTS221_Error_et HTS221_DeInit(void *handle) +{ + uint8_t buffer[4]; + + if (HTS221_read_reg(handle, HTS221_CTRL_REG1, 2, buffer)) { + return HTS221_ERROR; + } + + /* HTS221 in power down */ + buffer[0] |= 0x01 << HTS221_PD_BIT; + + /* Make HTS221 boot */ + buffer[1] |= 0x01 << HTS221_BOOT_BIT; + + if (HTS221_write_reg(handle, HTS221_CTRL_REG1, 2, buffer)) { + return HTS221_ERROR; + } + + /* Dump of data output */ + if (HTS221_read_reg(handle, HTS221_HR_OUT_L_REG, 4, buffer)) { + return HTS221_ERROR; + } + + return HTS221_OK; +} + +/** +* @brief Read HTS221 output registers, and calculate humidity and temperature. +* @param *handle Device handle. +* @param humidity pointer to the returned humidity value that must be divided by 10 to get the value in [%]. +* @param temperature pointer to the returned temperature value that must be divided by 10 to get the value in ['C]. +* @retval Error code [HTS221_OK, HTS221_ERROR]. +*/ +HTS221_Error_et HTS221_Get_Measurement(void *handle, uint16_t *humidity, int16_t *temperature) +{ + if (HTS221_Get_Temperature(handle, temperature) == HTS221_ERROR) { + return HTS221_ERROR; + } + if (HTS221_Get_Humidity(handle, humidity) == HTS221_ERROR) { + return HTS221_ERROR; + } + + return HTS221_OK; +} + +/** +* @brief Read HTS221 output registers. Humidity and temperature. +* @param *handle Device handle. +* @param humidity pointer to the returned humidity raw value. +* @param temperature pointer to the returned temperature raw value. +* @retval Error code [HTS221_OK, HTS221_ERROR]. +*/ +HTS221_Error_et HTS221_Get_RawMeasurement(void *handle, int16_t *humidity, int16_t *temperature) +{ + uint8_t buffer[4]; + + if (HTS221_read_reg(handle, HTS221_HR_OUT_L_REG, 4, buffer)) { + return HTS221_ERROR; + } + + *humidity = (int16_t)((((uint16_t)buffer[1]) << 8) | (uint16_t)buffer[0]); + *temperature = (int16_t)((((uint16_t)buffer[3]) << 8) | (uint16_t)buffer[2]); + + return HTS221_OK; +} + +/** +* @brief Read HTS221 Humidity output registers, and calculate humidity. +* @param *handle Device handle. +* @param Pointer to the returned humidity value that must be divided by 10 to get the value in [%]. +* @retval Error code [HTS221_OK, HTS221_ERROR]. +*/ +HTS221_Error_et HTS221_Get_Humidity(void *handle, uint16_t *value) +{ + int16_t H0_T0_out, H1_T0_out, H_T_out; + int16_t H0_rh, H1_rh; + uint8_t buffer[2]; + float tmp_f; + + if (HTS221_read_reg(handle, HTS221_H0_RH_X2, 2, buffer)) { + return HTS221_ERROR; + } + H0_rh = buffer[0] >> 1; + H1_rh = buffer[1] >> 1; + + if (HTS221_read_reg(handle, HTS221_H0_T0_OUT_L, 2, buffer)) { + return HTS221_ERROR; + } + H0_T0_out = (((uint16_t)buffer[1]) << 8) | (uint16_t)buffer[0]; + + if (HTS221_read_reg(handle, HTS221_H1_T0_OUT_L, 2, buffer)) { + return HTS221_ERROR; + } + H1_T0_out = (((uint16_t)buffer[1]) << 8) | (uint16_t)buffer[0]; + + if (HTS221_read_reg(handle, HTS221_HR_OUT_L_REG, 2, buffer)) { + return HTS221_ERROR; + } + H_T_out = (((uint16_t)buffer[1]) << 8) | (uint16_t)buffer[0]; + + tmp_f = (float)(H_T_out - H0_T0_out) * (float)(H1_rh - H0_rh) / (float)(H1_T0_out - H0_T0_out) + H0_rh; + tmp_f *= 10.0f; + + *value = (tmp_f > 1000.0f) ? 1000 + : (tmp_f < 0.0f) ? 0 + : (uint16_t)tmp_f; + + return HTS221_OK; +} + +/** +* @brief Read HTS221 humidity output registers. +* @param *handle Device handle. +* @param Pointer to the returned humidity raw value. +* @retval Error code [HTS221_OK, HTS221_ERROR]. +*/ +HTS221_Error_et HTS221_Get_HumidityRaw(void *handle, int16_t *value) +{ + uint8_t buffer[2]; + + if (HTS221_read_reg(handle, HTS221_HR_OUT_L_REG, 2, buffer)) { + return HTS221_ERROR; + } + + *value = (int16_t)((((uint16_t)buffer[1]) << 8) | (uint16_t)buffer[0]); + + return HTS221_OK; +} + +/** +* @brief Read HTS221 temperature output registers, and calculate temperature. +* @param *handle Device handle. +* @param Pointer to the returned temperature value that must be divided by 10 to get the value in ['C]. +* @retval Error code [HTS221_OK, HTS221_ERROR]. +*/ +HTS221_Error_et HTS221_Get_Temperature(void *handle, int16_t *value) +{ + int16_t T0_out, T1_out, T_out, T0_degC_x8_u16, T1_degC_x8_u16; + int16_t T0_degC, T1_degC; + uint8_t buffer[4], tmp; + float tmp_f; + + if (HTS221_read_reg(handle, HTS221_T0_DEGC_X8, 2, buffer)) { + return HTS221_ERROR; + } + if (HTS221_read_reg(handle, HTS221_T0_T1_DEGC_H2, 1, &tmp)) { + return HTS221_ERROR; + } + + T0_degC_x8_u16 = (((uint16_t)(tmp & 0x03)) << 8) | ((uint16_t)buffer[0]); + T1_degC_x8_u16 = (((uint16_t)(tmp & 0x0C)) << 6) | ((uint16_t)buffer[1]); + T0_degC = T0_degC_x8_u16 >> 3; + T1_degC = T1_degC_x8_u16 >> 3; + + if (HTS221_read_reg(handle, HTS221_T0_OUT_L, 4, buffer)) { + return HTS221_ERROR; + } + + T0_out = (((uint16_t)buffer[1]) << 8) | (uint16_t)buffer[0]; + T1_out = (((uint16_t)buffer[3]) << 8) | (uint16_t)buffer[2]; + + if (HTS221_read_reg(handle, HTS221_TEMP_OUT_L_REG, 2, buffer)) { + return HTS221_ERROR; + } + + T_out = (((uint16_t)buffer[1]) << 8) | (uint16_t)buffer[0]; + + tmp_f = (float)(T_out - T0_out) * (float)(T1_degC - T0_degC) / (float)(T1_out - T0_out) + T0_degC; + tmp_f *= 10.0f; + + *value = (int16_t)tmp_f; + + return HTS221_OK; +} + +/** +* @brief Read HTS221 temperature output registers. +* @param *handle Device handle. +* @param Pointer to the returned temperature raw value. +* @retval Error code [HTS221_OK, HTS221_ERROR]. +*/ +HTS221_Error_et HTS221_Get_TemperatureRaw(void *handle, int16_t *value) +{ + uint8_t buffer[2]; + + if (HTS221_read_reg(handle, HTS221_TEMP_OUT_L_REG, 2, buffer)) { + return HTS221_ERROR; + } + + *value = (int16_t)((((uint16_t)buffer[1]) << 8) | (uint16_t)buffer[0]); + + return HTS221_OK; +} + +/** +* @brief Get the availability of new data for humidity and temperature. +* @param *handle Device handle. +* @param humidity pointer to the returned humidity data status [HTS221_SET/HTS221_RESET]. +* @param temperature pointer to the returned temperature data status [HTS221_SET/HTS221_RESET]. +* This parameter is a pointer to @ref HTS221_BitStatus_et. +* @retval Error code [HTS221_OK, HTS221_ERROR]. +*/ +HTS221_Error_et HTS221_Get_DataStatus(void *handle, HTS221_BitStatus_et *humidity, HTS221_BitStatus_et *temperature) +{ + uint8_t tmp; + + if (HTS221_read_reg(handle, HTS221_STATUS_REG, 1, &tmp)) { + return HTS221_ERROR; + } + + *humidity = (HTS221_BitStatus_et)((tmp & HTS221_HDA_MASK) >> HTS221_H_DA_BIT); + *temperature = (HTS221_BitStatus_et)(tmp & HTS221_TDA_MASK); + + return HTS221_OK; +} + +/** +* @brief Exit from power down mode. +* @param *handle Device handle. +* @param void. +* @retval Error code [HTS221_OK, HTS221_ERROR]. +*/ +HTS221_Error_et HTS221_Activate(void *handle) +{ + uint8_t tmp; + + if (HTS221_read_reg(handle, HTS221_CTRL_REG1, 1, &tmp)) { + return HTS221_ERROR; + } + + tmp |= HTS221_PD_MASK; + + if (HTS221_write_reg(handle, HTS221_CTRL_REG1, 1, &tmp)) { + return HTS221_ERROR; + } + + return HTS221_OK; +} + +/** +* @brief Put the sensor in power down mode. +* @param *handle Device handle. +* @retval Error code [HTS221_OK, HTS221_ERROR]. +*/ +HTS221_Error_et HTS221_DeActivate(void *handle) +{ + uint8_t tmp; + + if (HTS221_read_reg(handle, HTS221_CTRL_REG1, 1, &tmp)) { + return HTS221_ERROR; + } + + tmp &= ~HTS221_PD_MASK; + + if (HTS221_write_reg(handle, HTS221_CTRL_REG1, 1, &tmp)) { + return HTS221_ERROR; + } + + return HTS221_OK; +} + + + +/** +* @brief Check if the single measurement has completed. +* @param *handle Device handle. +* @param tmp is set to 1, when the measure is completed +* @retval Status [HTS221_ERROR, HTS221_OK] +*/ +HTS221_Error_et HTS221_IsMeasurementCompleted(void *handle, HTS221_BitStatus_et *Is_Measurement_Completed) +{ + uint8_t tmp; + + if (HTS221_read_reg(handle, HTS221_STATUS_REG, 1, &tmp)) { + return HTS221_ERROR; + } + + if ((tmp & (uint8_t)(HTS221_HDA_MASK | HTS221_TDA_MASK)) == (uint8_t)(HTS221_HDA_MASK | HTS221_TDA_MASK)) { + *Is_Measurement_Completed = HTS221_SET; + } else { + *Is_Measurement_Completed = HTS221_RESET; + } + + return HTS221_OK; +} + + +/** +* @brief Set_ humidity and temperature average mode. +* @param *handle Device handle. +* @param avgh is the average mode for humidity, this parameter is @ref HTS221_Avgh_et. +* @param avgt is the average mode for temperature, this parameter is @ref HTS221_Avgt_et. +* @retval Error code [HTS221_OK, HTS221_ERROR]. +*/ +HTS221_Error_et HTS221_Set_AvgHT(void *handle, HTS221_Avgh_et avgh, HTS221_Avgt_et avgt) +{ + uint8_t tmp; + + HTS221_assert_param(IS_HTS221_AVGH(avgh)); + HTS221_assert_param(IS_HTS221_AVGT(avgt)); + + if (HTS221_read_reg(handle, HTS221_AV_CONF_REG, 1, &tmp)) { + return HTS221_ERROR; + } + + tmp &= ~(HTS221_AVGH_MASK | HTS221_AVGT_MASK); + tmp |= (uint8_t)avgh; + tmp |= (uint8_t)avgt; + + if (HTS221_write_reg(handle, HTS221_AV_CONF_REG, 1, &tmp)) { + return HTS221_ERROR; + } + + return HTS221_OK; +} + +/** +* @brief Set humidity average mode. +* @param *handle Device handle. +* @param avgh is the average mode for humidity, this parameter is @ref HTS221_Avgh_et. +* @retval Error code [HTS221_OK, HTS221_ERROR]. +*/ +HTS221_Error_et HTS221_Set_AvgH(void *handle, HTS221_Avgh_et avgh) +{ + uint8_t tmp; + + HTS221_assert_param(IS_HTS221_AVGH(avgh)); + + if (HTS221_read_reg(handle, HTS221_AV_CONF_REG, 1, &tmp)) { + return HTS221_ERROR; + } + + tmp &= ~HTS221_AVGH_MASK; + tmp |= (uint8_t)avgh; + + if (HTS221_write_reg(handle, HTS221_AV_CONF_REG, 1, &tmp)) { + return HTS221_ERROR; + } + + return HTS221_OK; +} + +/** +* @brief Set temperature average mode. +* @param *handle Device handle. +* @param avgt is the average mode for temperature, this parameter is @ref HTS221_Avgt_et. +* @retval Error code [HTS221_OK, HTS221_ERROR]. +*/ +HTS221_Error_et HTS221_Set_AvgT(void *handle, HTS221_Avgt_et avgt) +{ + uint8_t tmp; + + HTS221_assert_param(IS_HTS221_AVGT(avgt)); + + if (HTS221_read_reg(handle, HTS221_AV_CONF_REG, 1, &tmp)) { + return HTS221_ERROR; + } + + tmp &= ~HTS221_AVGT_MASK; + tmp |= (uint8_t)avgt; + + if (HTS221_write_reg(handle, HTS221_AV_CONF_REG, 1, &tmp)) { + return HTS221_ERROR; + } + + return HTS221_OK; +} + +/** +* @brief Get humidity and temperature average mode. +* @param *handle Device handle. +* @param avgh pointer to the returned value with the humidity average mode. +* @param avgt pointer to the returned value with the temperature average mode. +* @retval Error code [HTS221_OK, HTS221_ERROR]. +*/ +HTS221_Error_et HTS221_Get_AvgHT(void *handle, HTS221_Avgh_et *avgh, HTS221_Avgt_et *avgt) +{ + uint8_t tmp; + + if (HTS221_read_reg(handle, HTS221_AV_CONF_REG, 1, &tmp)) { + return HTS221_ERROR; + } + + *avgh = (HTS221_Avgh_et)(tmp & HTS221_AVGH_MASK); + *avgt = (HTS221_Avgt_et)(tmp & HTS221_AVGT_MASK); + + return HTS221_OK; +} + +/** +* @brief Set block data update mode. +* @param *handle Device handle. +* @param status can be HTS221_ENABLE: enable the block data update, output data registers are updated once both MSB and LSB are read. +* @param status can be HTS221_DISABLE: output data registers are continuously updated. +* This parameter is a @ref HTS221_BitStatus_et. +* @retval Error code [HTS221_OK, HTS221_ERROR]. +*/ +HTS221_Error_et HTS221_Set_BduMode(void *handle, HTS221_State_et status) +{ + uint8_t tmp; + + HTS221_assert_param(IS_HTS221_State(status)); + + if (HTS221_read_reg(handle, HTS221_CTRL_REG1, 1, &tmp)) { + return HTS221_ERROR; + } + + tmp &= ~HTS221_BDU_MASK; + tmp |= ((uint8_t)status) << HTS221_BDU_BIT; + + if (HTS221_write_reg(handle, HTS221_CTRL_REG1, 1, &tmp)) { + return HTS221_ERROR; + } + + return HTS221_OK; +} + +/** +* @brief Get block data update mode. +* @param *handle Device handle. +* @param Pointer to the returned value with block data update mode status. +* @retval Error code [HTS221_OK, HTS221_ERROR]. +*/ +HTS221_Error_et HTS221_Get_BduMode(void *handle, HTS221_State_et *status) +{ + uint8_t tmp; + + if (HTS221_read_reg(handle, HTS221_CTRL_REG1, 1, &tmp)) { + return HTS221_ERROR; + } + + *status = (HTS221_State_et)((tmp & HTS221_BDU_MASK) >> HTS221_BDU_BIT); + + return HTS221_OK; +} + +/** +* @brief Enter or exit from power down mode. +* @param *handle Device handle. +* @param status can be HTS221_SET: HTS221 in power down mode. +* @param status can be HTS221_REET: HTS221 in active mode. +* This parameter is a @ref HTS221_BitStatus_et. +* @retval Error code [HTS221_OK, HTS221_ERROR]. +*/ +HTS221_Error_et HTS221_Set_PowerDownMode(void *handle, HTS221_BitStatus_et status) +{ + uint8_t tmp; + + HTS221_assert_param(IS_HTS221_BitStatus(status)); + + if (HTS221_read_reg(handle, HTS221_CTRL_REG1, 1, &tmp)) { + return HTS221_ERROR; + } + + tmp &= ~HTS221_PD_MASK; + tmp |= ((uint8_t)status) << HTS221_PD_BIT; + + if (HTS221_write_reg(handle, HTS221_CTRL_REG1, 1, &tmp)) { + return HTS221_ERROR; + } + + return HTS221_OK; +} + +/** +* @brief Get if HTS221 is in active mode or in power down mode. +* @param *handle Device handle. +* @param Pointer to the returned value with HTS221 status. +* @retval Error code [HTS221_OK, HTS221_ERROR]. +*/ +HTS221_Error_et HTS221_Get_PowerDownMode(void *handle, HTS221_BitStatus_et *status) +{ + uint8_t tmp; + + if (HTS221_read_reg(handle, HTS221_CTRL_REG1, 1, &tmp)) { + return HTS221_ERROR; + } + + *status = (HTS221_BitStatus_et)((tmp & HTS221_PD_MASK) >> HTS221_PD_BIT); + + return HTS221_OK; +} + +/** +* @brief Set the output data rate mode. +* @param *handle Device handle. +* @param odr is the output data rate mode. +* This parameter is a @ref HTS221_Odr_et. +* @retval Error code [HTS221_OK, HTS221_ERROR]. +*/ +HTS221_Error_et HTS221_Set_Odr(void *handle, HTS221_Odr_et odr) +{ + uint8_t tmp; + + HTS221_assert_param(IS_HTS221_ODR(odr)); + + if (HTS221_read_reg(handle, HTS221_CTRL_REG1, 1, &tmp)) { + return HTS221_ERROR; + } + + tmp &= ~HTS221_ODR_MASK; + tmp |= (uint8_t)odr; + + if (HTS221_write_reg(handle, HTS221_CTRL_REG1, 1, &tmp)) { + return HTS221_ERROR; + } + + return HTS221_OK; +} + +/** +* @brief Get the output data rate mode. +* @param *handle Device handle. +* @param Pointer to the returned value with output data rate mode. +* @retval Error code [HTS221_OK, HTS221_ERROR]. +*/ +HTS221_Error_et HTS221_Get_Odr(void *handle, HTS221_Odr_et *odr) +{ + uint8_t tmp; + + if (HTS221_read_reg(handle, HTS221_CTRL_REG1, 1, &tmp)) { + return HTS221_ERROR; + } + + tmp &= HTS221_ODR_MASK; + *odr = (HTS221_Odr_et)tmp; + + return HTS221_OK; +} + +/** +* @brief Reboot Memory Content. +* @param *handle Device handle. +* @retval Error code [HTS221_OK, HTS221_ERROR]. +*/ +HTS221_Error_et HTS221_MemoryBoot(void *handle) +{ + uint8_t tmp; + + if (HTS221_read_reg(handle, HTS221_CTRL_REG2, 1, &tmp)) { + return HTS221_ERROR; + } + + tmp |= HTS221_BOOT_MASK; + + if (HTS221_write_reg(handle, HTS221_CTRL_REG2, 1, &tmp)) { + return HTS221_ERROR; + } + + return HTS221_OK; +} + +/** +* @brief Configure the internal heater. +* @param *handle Device handle. +* @param The status of the internal heater [HTS221_ENABLE/HTS221_DISABLE]. +* This parameter is a @ref HTS221_State_et. +* @retval Error code [HTS221_OK, HTS221_ERROR] +*/ +HTS221_Error_et HTS221_Set_HeaterState(void *handle, HTS221_State_et status) +{ + uint8_t tmp; + + HTS221_assert_param(IS_HTS221_State(status)); + + if (HTS221_read_reg(handle, HTS221_CTRL_REG2, 1, &tmp)) { + return HTS221_ERROR; + } + + tmp &= ~HTS221_HEATHER_MASK; + tmp |= ((uint8_t)status) << HTS221_HEATHER_BIT; + + if (HTS221_write_reg(handle, HTS221_CTRL_REG2, 1, &tmp)) { + return HTS221_ERROR; + } + + return HTS221_OK; +} + +/** +* @brief Get the internal heater. +* @param *handle Device handle. +* @param Pointer to the returned status of the internal heater [HTS221_ENABLE/HTS221_DISABLE]. +* @retval Error code [HTS221_OK, HTS221_ERROR]. +*/ +HTS221_Error_et HTS221_Get_HeaterState(void *handle, HTS221_State_et *status) +{ + uint8_t tmp; + + if (HTS221_read_reg(handle, HTS221_CTRL_REG2, 1, &tmp)) { + return HTS221_ERROR; + } + + *status = (HTS221_State_et)((tmp & HTS221_HEATHER_MASK) >> HTS221_HEATHER_BIT); + + return HTS221_OK; +} + +/** +* @brief Set ONE_SHOT bit to start a new conversion (ODR mode has to be 00). +* Once the measurement is done, ONE_SHOT bit is self-cleared. +* @param *handle Device handle. +* @retval Error code [HTS221_OK, HTS221_ERROR]. +*/ +HTS221_Error_et HTS221_StartOneShotMeasurement(void *handle) +{ + uint8_t tmp; + + if (HTS221_read_reg(handle, HTS221_CTRL_REG2, 1, &tmp)) { + return HTS221_ERROR; + } + + tmp |= HTS221_ONE_SHOT_MASK; + + if (HTS221_write_reg(handle, HTS221_CTRL_REG2, 1, &tmp)) { + return HTS221_ERROR; + } + + return HTS221_OK; + +} + +/** +* @brief Set level configuration of the interrupt pin DRDY. +* @param *handle Device handle. +* @param status can be HTS221_LOW_LVL: active level is LOW. +* @param status can be HTS221_HIGH_LVL: active level is HIGH. +* This parameter is a @ref HTS221_State_et. +* @retval Error code [HTS221_OK, HTS221_ERROR]. +*/ +HTS221_Error_et HTS221_Set_IrqActiveLevel(void *handle, HTS221_DrdyLevel_et value) +{ + uint8_t tmp; + + HTS221_assert_param(IS_HTS221_DrdyLevelType(value)); + + if (HTS221_read_reg(handle, HTS221_CTRL_REG3, 1, &tmp)) { + return HTS221_ERROR; + } + + tmp &= ~HTS221_DRDY_H_L_MASK; + tmp |= (uint8_t)value; + + if (HTS221_write_reg(handle, HTS221_CTRL_REG3, 1, &tmp)) { + return HTS221_ERROR; + } + + return HTS221_OK; +} + +/** +* @brief Get level configuration of the interrupt pin DRDY. +* @param *handle Device handle. +* @param Pointer to the returned status of the level configuration [HTS221_ENABLE/HTS221_DISABLE]. +* @retval Error code [HTS221_OK, HTS221_ERROR]. +*/ +HTS221_Error_et HTS221_Get_IrqActiveLevel(void *handle, HTS221_DrdyLevel_et *value) +{ + uint8_t tmp; + + if (HTS221_read_reg(handle, HTS221_CTRL_REG3, 1, &tmp)) { + return HTS221_ERROR; + } + + *value = (HTS221_DrdyLevel_et)(tmp & HTS221_DRDY_H_L_MASK); + + return HTS221_OK; +} + +/** +* @brief Set Push-pull/open drain configuration for the interrupt pin DRDY. +* @param *handle Device handle. +* @param value is the output type configuration. +* This parameter is a @ref HTS221_OutputType_et. +* @retval Error code [HTS221_OK, HTS221_ERROR]. +*/ +HTS221_Error_et HTS221_Set_IrqOutputType(void *handle, HTS221_OutputType_et value) +{ + uint8_t tmp; + + HTS221_assert_param(IS_HTS221_OutputType(value)); + + if (HTS221_read_reg(handle, HTS221_CTRL_REG3, 1, &tmp)) { + return HTS221_ERROR; + } + + tmp &= ~HTS221_PP_OD_MASK; + tmp |= (uint8_t)value; + + if (HTS221_write_reg(handle, HTS221_CTRL_REG3, 1, &tmp)) { + return HTS221_ERROR; + } + + return HTS221_OK; +} + +/** +* @brief Get the configuration for the interrupt pin DRDY. +* @param *handle Device handle. +* @param Pointer to the returned value with output type configuration. +* @retval Error code [HTS221_OK, HTS221_ERROR]. +*/ +HTS221_Error_et HTS221_Get_IrqOutputType(void *handle, HTS221_OutputType_et *value) +{ + uint8_t tmp; + + if (HTS221_read_reg(handle, HTS221_CTRL_REG3, 1, &tmp)) { + return HTS221_ERROR; + } + + *value = (HTS221_OutputType_et)(tmp & HTS221_PP_OD_MASK); + + return HTS221_OK; +} + +/** +* @brief Enable/disable the interrupt mode. +* @param *handle Device handle. +* @param status is the enable/disable for the interrupt mode. +* This parameter is a @ref HTS221_State_et. +* @retval Error code [HTS221_OK, HTS221_ERROR]. +*/ +HTS221_Error_et HTS221_Set_IrqEnable(void *handle, HTS221_State_et status) +{ + uint8_t tmp; + + HTS221_assert_param(IS_HTS221_State(status)); + + if (HTS221_read_reg(handle, HTS221_CTRL_REG3, 1, &tmp)) { + return HTS221_ERROR; + } + + tmp &= ~HTS221_DRDY_MASK; + tmp |= ((uint8_t)status) << HTS221_DRDY_BIT; + + if (HTS221_write_reg(handle, HTS221_CTRL_REG3, 1, &tmp)) { + return HTS221_ERROR; + } + + return HTS221_OK; +} + +/** +* @brief Get the interrupt mode. +* @param *handle Device handle. +* @param Pointer to the returned status of the interrupt mode configuration [HTS221_ENABLE/HTS221_DISABLE]. +* @retval Error code [HTS221_OK, HTS221_ERROR]. +*/ +HTS221_Error_et HTS221_Get_IrqEnable(void *handle, HTS221_State_et *status) +{ + uint8_t tmp; + + if (HTS221_read_reg(handle, HTS221_CTRL_REG3, 1, &tmp)) { + return HTS221_ERROR; + } + + *status = (HTS221_State_et)((tmp & HTS221_DRDY_MASK) >> HTS221_DRDY_BIT); + + return HTS221_OK; +} + + +#ifdef USE_FULL_ASSERT_HTS221 +/** +* @brief Reports the name of the source file and the source line number +* where the assert_param error has occurred. +* @param file: pointer to the source file name +* @param line: assert_param error line source number +* @retval : None +*/ +void HTS221_assert_failed(uint8_t *file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number */ + printf("Wrong parameters value: file %s on line %d\r\n", file, (int)line); + + /* Infinite loop */ + while (1) { + } +} +#endif + +#ifdef __cplusplus +} +#endif + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/******************* (C) COPYRIGHT 2013 STMicroelectronics *****END OF FILE****/ diff --git a/LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/HTS221/HTS221_driver.h b/LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/HTS221/HTS221_driver.h new file mode 100644 index 0000000..4cb1e28 --- /dev/null +++ b/LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/HTS221/HTS221_driver.h @@ -0,0 +1,507 @@ +/** + ****************************************************************************** + * @file HTS221_driver.h + * @author HESA Application Team + * @version V1.1 + * @date 10-August-2016 + * @brief HTS221 driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __HTS221_DRIVER__H +#define __HTS221_DRIVER__H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Uncomment the line below to expanse the "assert_param" macro in the drivers code */ +#define USE_FULL_ASSERT_HTS221 + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT_HTS221 + +/** +* @brief The assert_param macro is used for function's parameters check. +* @param expr: If expr is false, it calls assert_failed function which reports +* the name of the source file and the source line number of the call +* that failed. If expr is true, it returns no value. +* @retval None +*/ +#define HTS221_assert_param(expr) ((expr) ? (void)0 : HTS221_assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ +void HTS221_assert_failed(uint8_t *file, uint32_t line); +#else +#define HTS221_assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT_HTS221 */ + +/** @addtogroup Environmental_Sensor +* @{ +*/ + +/** @addtogroup HTS221_DRIVER +* @{ +*/ + +/* Exported Types -------------------------------------------------------------*/ +/** @defgroup HTS221_Exported_Types +* @{ +*/ + + +/** +* @brief Error code type. +*/ +typedef enum {HTS221_OK = (uint8_t)0, HTS221_ERROR = !HTS221_OK} HTS221_Error_et; + +/** +* @brief State type. +*/ +typedef enum {HTS221_DISABLE = (uint8_t)0, HTS221_ENABLE = !HTS221_DISABLE} HTS221_State_et; +#define IS_HTS221_State(MODE) ((MODE == HTS221_ENABLE) || (MODE == HTS221_DISABLE)) + +/** +* @brief Bit status type. +*/ +typedef enum {HTS221_RESET = (uint8_t)0, HTS221_SET = !HTS221_RESET} HTS221_BitStatus_et; +#define IS_HTS221_BitStatus(MODE) ((MODE == HTS221_RESET) || (MODE == HTS221_SET)) + +/** +* @brief Humidity average. +*/ +typedef enum { + HTS221_AVGH_4 = (uint8_t)0x00, /*!< Internal average on 4 samples */ + HTS221_AVGH_8 = (uint8_t)0x01, /*!< Internal average on 8 samples */ + HTS221_AVGH_16 = (uint8_t)0x02, /*!< Internal average on 16 samples */ + HTS221_AVGH_32 = (uint8_t)0x03, /*!< Internal average on 32 samples */ + HTS221_AVGH_64 = (uint8_t)0x04, /*!< Internal average on 64 samples */ + HTS221_AVGH_128 = (uint8_t)0x05, /*!< Internal average on 128 samples */ + HTS221_AVGH_256 = (uint8_t)0x06, /*!< Internal average on 256 samples */ + HTS221_AVGH_512 = (uint8_t)0x07 /*!< Internal average on 512 samples */ +} HTS221_Avgh_et; +#define IS_HTS221_AVGH(AVGH) ((AVGH == HTS221_AVGH_4) || (AVGH == HTS221_AVGH_8) || \ + (AVGH == HTS221_AVGH_16) || (AVGH == HTS221_AVGH_32) || \ + (AVGH == HTS221_AVGH_64) || (AVGH == HTS221_AVGH_128) || \ + (AVGH == HTS221_AVGH_256) || (AVGH == HTS221_AVGH_512)) + +/** +* @brief Temperature average. +*/ +typedef enum { + HTS221_AVGT_2 = (uint8_t)0x00, /*!< Internal average on 2 samples */ + HTS221_AVGT_4 = (uint8_t)0x08, /*!< Internal average on 4 samples */ + HTS221_AVGT_8 = (uint8_t)0x10, /*!< Internal average on 8 samples */ + HTS221_AVGT_16 = (uint8_t)0x18, /*!< Internal average on 16 samples */ + HTS221_AVGT_32 = (uint8_t)0x20, /*!< Internal average on 32 samples */ + HTS221_AVGT_64 = (uint8_t)0x28, /*!< Internal average on 64 samples */ + HTS221_AVGT_128 = (uint8_t)0x30, /*!< Internal average on 128 samples */ + HTS221_AVGT_256 = (uint8_t)0x38 /*!< Internal average on 256 samples */ +} HTS221_Avgt_et; +#define IS_HTS221_AVGT(AVGT) ((AVGT == HTS221_AVGT_2) || (AVGT == HTS221_AVGT_4) || \ + (AVGT == HTS221_AVGT_8) || (AVGT == HTS221_AVGT_16) || \ + (AVGT == HTS221_AVGT_32) || (AVGT == HTS221_AVGT_64) || \ + (AVGT == HTS221_AVGT_128) || (AVGT == HTS221_AVGT_256)) + +/** +* @brief Output data rate configuration. +*/ +typedef enum { + HTS221_ODR_ONE_SHOT = (uint8_t)0x00, /*!< Output Data Rate: one shot */ + HTS221_ODR_1HZ = (uint8_t)0x01, /*!< Output Data Rate: 1Hz */ + HTS221_ODR_7HZ = (uint8_t)0x02, /*!< Output Data Rate: 7Hz */ + HTS221_ODR_12_5HZ = (uint8_t)0x03, /*!< Output Data Rate: 12.5Hz */ +} HTS221_Odr_et; +#define IS_HTS221_ODR(ODR) ((ODR == HTS221_ODR_ONE_SHOT) || (ODR == HTS221_ODR_1HZ) || \ + (ODR == HTS221_ODR_7HZ) || (ODR == HTS221_ODR_12_5HZ)) + + +/** +* @brief Push-pull/Open Drain selection on DRDY pin. +*/ +typedef enum { + HTS221_PUSHPULL = (uint8_t)0x00, /*!< DRDY pin in push pull */ + HTS221_OPENDRAIN = (uint8_t)0x40 /*!< DRDY pin in open drain */ +} HTS221_OutputType_et; +#define IS_HTS221_OutputType(MODE) ((MODE == HTS221_PUSHPULL) || (MODE == HTS221_OPENDRAIN)) + +/** +* @brief Active level of DRDY pin. +*/ +typedef enum { + HTS221_HIGH_LVL = (uint8_t)0x00, /*!< HIGH state level for DRDY pin */ + HTS221_LOW_LVL = (uint8_t)0x80 /*!< LOW state level for DRDY pin */ +} HTS221_DrdyLevel_et; +#define IS_HTS221_DrdyLevelType(MODE) ((MODE == HTS221_HIGH_LVL) || (MODE == HTS221_LOW_LVL)) + +/** +* @brief Driver Version Info structure definition. +*/ +typedef struct { + uint8_t Major; + uint8_t Minor; + uint8_t Point; +} HTS221_DriverVersion_st; + + +/** +* @brief HTS221 Init structure definition. +*/ +typedef struct { + HTS221_Avgh_et avg_h; /*!< Humidity average */ + HTS221_Avgt_et avg_t; /*!< Temperature average */ + HTS221_Odr_et odr; /*!< Output data rate */ + HTS221_State_et bdu_status; /*!< HTS221_ENABLE/HTS221_DISABLE the block data update */ + HTS221_State_et heater_status; /*!< HTS221_ENABLE/HTS221_DISABLE the internal heater */ + + HTS221_DrdyLevel_et irq_level; /*!< HTS221_HIGH_LVL/HTS221_LOW_LVL the level for DRDY pin */ + HTS221_OutputType_et irq_output_type; /*!< Output configuration for DRDY pin */ + HTS221_State_et irq_enable; /*!< HTS221_ENABLE/HTS221_DISABLE interrupt on DRDY pin */ +} HTS221_Init_st; + +/** +* @} +*/ + + +/* Exported Constants ---------------------------------------------------------*/ +/** @defgroup HTS221_Exported_Constants +* @{ +*/ + +/** +* @brief Bitfield positioning. +*/ +#define HTS221_BIT(x) ((uint8_t)x) + +/** +* @brief I2C address. +*/ +#define HTS221_I2C_ADDRESS (uint8_t)0xBE + +/** +* @brief Driver version. +*/ +#define HTS221_DRIVER_VERSION_MAJOR (uint8_t)1 +#define HTS221_DRIVER_VERSION_MINOR (uint8_t)1 +#define HTS221_DRIVER_VERSION_POINT (uint8_t)0 + +/** +* @addtogroup HTS221_Registers +* @{ +*/ + + +/** +* @brief Device Identification register. +* \code +* Read +* Default value: 0xBC +* 7:0 This read-only register contains the device identifier for HTS221. +* \endcode +*/ +#define HTS221_WHO_AM_I_REG (uint8_t)0x0F + +/** +* @brief Device Identification value. +*/ +#define HTS221_WHO_AM_I_VAL (uint8_t)0xBC + + +/** +* @brief Humidity and temperature average mode register. +* \code +* Read/write +* Default value: 0x1B +* 7:6 Reserved. +* 5:3 AVGT2-AVGT1-AVGT0: Select the temperature internal average. +* +* AVGT2 | AVGT1 | AVGT0 | Nr. Internal Average +* ---------------------------------------------------- +* 0 | 0 | 0 | 2 +* 0 | 0 | 1 | 4 +* 0 | 1 | 0 | 8 +* 0 | 1 | 1 | 16 +* 1 | 0 | 0 | 32 +* 1 | 0 | 1 | 64 +* 1 | 1 | 0 | 128 +* 1 | 1 | 1 | 256 +* +* 2:0 AVGH2-AVGH1-AVGH0: Select humidity internal average. +* AVGH2 | AVGH1 | AVGH0 | Nr. Internal Average +* ------------------------------------------------------ +* 0 | 0 | 0 | 4 +* 0 | 0 | 1 | 8 +* 0 | 1 | 0 | 16 +* 0 | 1 | 1 | 32 +* 1 | 0 | 0 | 64 +* 1 | 0 | 1 | 128 +* 1 | 1 | 0 | 256 +* 1 | 1 | 1 | 512 +* +* \endcode +*/ +#define HTS221_AV_CONF_REG (uint8_t)0x10 + +#define HTS221_AVGT_BIT HTS221_BIT(3) +#define HTS221_AVGH_BIT HTS221_BIT(0) + +#define HTS221_AVGH_MASK (uint8_t)0x07 +#define HTS221_AVGT_MASK (uint8_t)0x38 + +/** +* @brief Control register 1. +* \code +* Read/write +* Default value: 0x00 +* 7 PD: power down control. 0 - power down mode; 1 - active mode. +* 6:3 Reserved. +* 2 BDU: block data update. 0 - continuous update; 1 - output registers not updated until MSB and LSB reading. +* 1:0 ODR1, ODR0: output data rate selection. +* +* ODR1 | ODR0 | Humidity output data-rate(Hz) | Pressure output data-rate(Hz) +* ---------------------------------------------------------------------------------- +* 0 | 0 | one shot | one shot +* 0 | 1 | 1 | 1 +* 1 | 0 | 7 | 7 +* 1 | 1 | 12.5 | 12.5 +* +* \endcode +*/ +#define HTS221_CTRL_REG1 (uint8_t)0x20 + +#define HTS221_PD_BIT HTS221_BIT(7) +#define HTS221_BDU_BIT HTS221_BIT(2) +#define HTS221_ODR_BIT HTS221_BIT(0) + +#define HTS221_PD_MASK (uint8_t)0x80 +#define HTS221_BDU_MASK (uint8_t)0x04 +#define HTS221_ODR_MASK (uint8_t)0x03 + +/** +* @brief Control register 2. +* \code +* Read/write +* Default value: 0x00 +* 7 BOOT: Reboot memory content. 0: normal mode; 1: reboot memory content. Self-cleared upon completation. +* 6:2 Reserved. +* 1 HEATHER: 0: heater enable; 1: heater disable. +* 0 ONE_SHOT: 0: waiting for start of conversion; 1: start for a new dataset. Self-cleared upon completation. +* \endcode +*/ +#define HTS221_CTRL_REG2 (uint8_t)0x21 + +#define HTS221_BOOT_BIT HTS221_BIT(7) +#define HTS221_HEATHER_BIT HTS221_BIT(1) +#define HTS221_ONESHOT_BIT HTS221_BIT(0) + +#define HTS221_BOOT_MASK (uint8_t)0x80 +#define HTS221_HEATHER_MASK (uint8_t)0x02 +#define HTS221_ONE_SHOT_MASK (uint8_t)0x01 + +/** +* @brief Control register 3. +* \code +* Read/write +* Default value: 0x00 +* 7 DRDY_H_L: Interrupt edge. 0: active high, 1: active low. +* 6 PP_OD: Push-Pull/OpenDrain selection on interrupt pads. 0: push-pull; 1: open drain. +* 5:3 Reserved. +* 2 DRDY: interrupt config. 0: disable, 1: enable. +* \endcode +*/ +#define HTS221_CTRL_REG3 (uint8_t)0x22 + +#define HTS221_DRDY_H_L_BIT HTS221_BIT(7) +#define HTS221_PP_OD_BIT HTS221_BIT(6) +#define HTS221_DRDY_BIT HTS221_BIT(2) + +#define HTS221_DRDY_H_L_MASK (uint8_t)0x80 +#define HTS221_PP_OD_MASK (uint8_t)0x40 +#define HTS221_DRDY_MASK (uint8_t)0x04 + +/** +* @brief Status register. +* \code +* Read +* Default value: 0x00 +* 7:2 Reserved. +* 1 H_DA: Humidity data available. 0: new data for humidity is not yet available; 1: new data for humidity is available. +* 0 T_DA: Temperature data available. 0: new data for temperature is not yet available; 1: new data for temperature is available. +* \endcode +*/ +#define HTS221_STATUS_REG (uint8_t)0x27 + +#define HTS221_H_DA_BIT HTS221_BIT(1) +#define HTS221_T_DA_BIT HTS221_BIT(0) + +#define HTS221_HDA_MASK (uint8_t)0x02 +#define HTS221_TDA_MASK (uint8_t)0x01 + +/** +* @brief Humidity data (LSB). +* \code +* Read +* Default value: 0x00. +* HOUT7 - HOUT0: Humidity data LSB (2's complement). +* \endcode +*/ +#define HTS221_HR_OUT_L_REG (uint8_t)0x28 + +/** +* @brief Humidity data (MSB). +* \code +* Read +* Default value: 0x00. +* HOUT15 - HOUT8: Humidity data MSB (2's complement). +* \endcode +*/ +#define HTS221_HR_OUT_H_REG (uint8_t)0x29 + + +/** +* @brief Temperature data (LSB). +* \code +* Read +* Default value: 0x00. +* TOUT7 - TOUT0: temperature data LSB. +* \endcode +*/ +#define HTS221_TEMP_OUT_L_REG (uint8_t)0x2A + +/** +* @brief Temperature data (MSB). +* \code +* Read +* Default value: 0x00. +* TOUT15 - TOUT8: temperature data MSB. +* \endcode +*/ +#define HTS221_TEMP_OUT_H_REG (uint8_t)0x2B + +/** +* @brief Calibration registers. +* \code +* Read +* \endcode +*/ +#define HTS221_H0_RH_X2 (uint8_t)0x30 +#define HTS221_H1_RH_X2 (uint8_t)0x31 +#define HTS221_T0_DEGC_X8 (uint8_t)0x32 +#define HTS221_T1_DEGC_X8 (uint8_t)0x33 +#define HTS221_T0_T1_DEGC_H2 (uint8_t)0x35 +#define HTS221_H0_T0_OUT_L (uint8_t)0x36 +#define HTS221_H0_T0_OUT_H (uint8_t)0x37 +#define HTS221_H1_T0_OUT_L (uint8_t)0x3A +#define HTS221_H1_T0_OUT_H (uint8_t)0x3B +#define HTS221_T0_OUT_L (uint8_t)0x3C +#define HTS221_T0_OUT_H (uint8_t)0x3D +#define HTS221_T1_OUT_L (uint8_t)0x3E +#define HTS221_T1_OUT_H (uint8_t)0x3F + + +/** +* @} +*/ + + +/** +* @} +*/ + + +/* Exported Functions -------------------------------------------------------------*/ +/** @defgroup HTS221_Exported_Functions +* @{ +*/ + +HTS221_Error_et HTS221_read_reg(void *handle, uint8_t RegAddr, uint16_t NumByteToRead, uint8_t *Data); +HTS221_Error_et HTS221_write_reg(void *handle, uint8_t RegAddr, uint16_t NumByteToWrite, uint8_t *Data); + +HTS221_Error_et HTS221_Get_DriverVersion(HTS221_DriverVersion_st *version); +HTS221_Error_et HTS221_Get_DeviceID(void *handle, uint8_t *deviceid); + +HTS221_Error_et HTS221_Set_InitConfig(void *handle, HTS221_Init_st *pxInit); +HTS221_Error_et HTS221_Get_InitConfig(void *handle, HTS221_Init_st *pxInit); +HTS221_Error_et HTS221_DeInit(void *handle); +HTS221_Error_et HTS221_IsMeasurementCompleted(void *handle, HTS221_BitStatus_et *Is_Measurement_Completed); + +HTS221_Error_et HTS221_Get_Measurement(void *handle, uint16_t *humidity, int16_t *temperature); +HTS221_Error_et HTS221_Get_RawMeasurement(void *handle, int16_t *humidity, int16_t *temperature); +HTS221_Error_et HTS221_Get_Humidity(void *handle, uint16_t *value); +HTS221_Error_et HTS221_Get_HumidityRaw(void *handle, int16_t *value); +HTS221_Error_et HTS221_Get_TemperatureRaw(void *handle, int16_t *value); +HTS221_Error_et HTS221_Get_Temperature(void *handle, int16_t *value); +HTS221_Error_et HTS221_Get_DataStatus(void *handle, HTS221_BitStatus_et *humidity, HTS221_BitStatus_et *temperature); +HTS221_Error_et HTS221_Activate(void *handle); +HTS221_Error_et HTS221_DeActivate(void *handle); + +HTS221_Error_et HTS221_Set_AvgHT(void *handle, HTS221_Avgh_et avgh, HTS221_Avgt_et avgt); +HTS221_Error_et HTS221_Set_AvgH(void *handle, HTS221_Avgh_et avgh); +HTS221_Error_et HTS221_Set_AvgT(void *handle, HTS221_Avgt_et avgt); +HTS221_Error_et HTS221_Get_AvgHT(void *handle, HTS221_Avgh_et *avgh, HTS221_Avgt_et *avgt); +HTS221_Error_et HTS221_Set_BduMode(void *handle, HTS221_State_et status); +HTS221_Error_et HTS221_Get_BduMode(void *handle, HTS221_State_et *status); +HTS221_Error_et HTS221_Set_PowerDownMode(void *handle, HTS221_BitStatus_et status); +HTS221_Error_et HTS221_Get_PowerDownMode(void *handle, HTS221_BitStatus_et *status); +HTS221_Error_et HTS221_Set_Odr(void *handle, HTS221_Odr_et odr); +HTS221_Error_et HTS221_Get_Odr(void *handle, HTS221_Odr_et *odr); +HTS221_Error_et HTS221_MemoryBoot(void *handle); +HTS221_Error_et HTS221_Set_HeaterState(void *handle, HTS221_State_et status); +HTS221_Error_et HTS221_Get_HeaterState(void *handle, HTS221_State_et *status); +HTS221_Error_et HTS221_StartOneShotMeasurement(void *handle); +HTS221_Error_et HTS221_Set_IrqActiveLevel(void *handle, HTS221_DrdyLevel_et status); +HTS221_Error_et HTS221_Get_IrqActiveLevel(void *handle, HTS221_DrdyLevel_et *status); +HTS221_Error_et HTS221_Set_IrqOutputType(void *handle, HTS221_OutputType_et value); +HTS221_Error_et HTS221_Get_IrqOutputType(void *handle, HTS221_OutputType_et *value); +HTS221_Error_et HTS221_Set_IrqEnable(void *handle, HTS221_State_et status); +HTS221_Error_et HTS221_Get_IrqEnable(void *handle, HTS221_State_et *status); + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __HTS221_DRIVER__H */ + +/******************* (C) COPYRIGHT 2013 STMicroelectronics *****END OF FILE****/ diff --git a/LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/LSM303AGR/LSM303AGRAccSensor.cpp b/LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/LSM303AGR/LSM303AGRAccSensor.cpp new file mode 100644 index 0000000..1025352 --- /dev/null +++ b/LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/LSM303AGR/LSM303AGRAccSensor.cpp @@ -0,0 +1,648 @@ +/** + ****************************************************************************** + * @file LSM303AGRAccSensor.cpp + * @author CLab + * @version V1.0.0 + * @date 5 August 2016 + * @brief Implementation an LSM303AGR accelerometer sensor. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + +/* Includes ------------------------------------------------------------------*/ + +#include "LSM303AGRAccSensor.h" + + +/* Class Implementation ------------------------------------------------------*/ + +LSM303AGRAccSensor::LSM303AGRAccSensor(SPI *spi, PinName cs_pin, PinName int1_pin, PinName int2_pin) : + _dev_spi(spi), _cs_pin(cs_pin), _int1_pin(int1_pin), _int2_pin(int2_pin) // SPI3W ONLY +{ + assert (spi); + if (cs_pin == NC) + { + printf ("ERROR LSM303AGRAccSensor CS MUST NOT BE NC\n\r"); + _dev_spi = NULL; + _dev_i2c=NULL; + return; + } + _cs_pin = 0; // enable SPI3W disable I2C + _dev_i2c=NULL; + + LSM303AGR_ACC_W_SPI_mode((void *)this, LSM303AGR_ACC_SIM_3_WIRES); +} + + +/** Constructor + * @param i2c object of an helper class which handles the I2C peripheral + * @param address the address of the component's instance + */ +LSM303AGRAccSensor::LSM303AGRAccSensor(DevI2C *i2c, uint8_t address, PinName int1_pin, PinName int2_pin) : + _dev_i2c(i2c), _address(address), _cs_pin(NC), _int1_pin(int1_pin), _int2_pin(int2_pin) +{ + assert (i2c); + _dev_spi = NULL; +}; + +/** + * @brief Initializing the component. + * @param[in] init pointer to device specific initalization structure. + * @retval "0" in case of success, an error code otherwise. + */ +int LSM303AGRAccSensor::init(void *init) +{ + /* Enable BDU */ + if ( LSM303AGR_ACC_W_BlockDataUpdate( (void *)this, LSM303AGR_ACC_BDU_ENABLED ) == MEMS_ERROR ) + { + return 1; + } + + /* FIFO mode selection */ + if ( LSM303AGR_ACC_W_FifoMode( (void *)this, LSM303AGR_ACC_FM_BYPASS ) == MEMS_ERROR ) + { + return 1; + } + + /* Output data rate selection - power down. */ + if ( LSM303AGR_ACC_W_ODR( (void *)this, LSM303AGR_ACC_ODR_DO_PWR_DOWN ) == MEMS_ERROR ) + { + return 1; + } + + /* Full scale selection. */ + if ( set_x_fs( 2.0f ) == 1 ) + { + return 1; + } + + /* Enable axes. */ + if ( LSM303AGR_ACC_W_XEN( (void *)this, LSM303AGR_ACC_XEN_ENABLED ) == MEMS_ERROR ) + { + return 1; + } + + if ( LSM303AGR_ACC_W_YEN ( (void *)this, LSM303AGR_ACC_YEN_ENABLED ) == MEMS_ERROR ) + { + return 1; + } + + if ( LSM303AGR_ACC_W_ZEN ( (void *)this, LSM303AGR_ACC_ZEN_ENABLED ) == MEMS_ERROR ) + { + return 1; + } + + /* Select default output data rate. */ + _last_odr = 100.0f; + + _is_enabled = 0; + + return 0; +} + +/** + * @brief Enable LSM303AGR Accelerator + * @retval 0 in case of success, an error code otherwise + */ +int LSM303AGRAccSensor::enable(void) +{ + /* Check if the component is already enabled */ + if ( _is_enabled == 1 ) + { + return 0; + } + + /* Output data rate selection. */ + if ( set_x_odr_when_enabled( _last_odr ) == 1 ) + { + return 1; + } + + _is_enabled = 1; + + return 0; +} + +/** + * @brief Disable LSM303AGR Accelerator + * @retval 0 in case of success, an error code otherwise + */ +int LSM303AGRAccSensor::disable(void) +{ + /* Check if the component is already disabled */ + if ( _is_enabled == 0 ) + { + return 0; + } + + /* Store actual output data rate. */ + if ( get_x_odr( &_last_odr ) == 1 ) + { + return 1; + } + + /* Output data rate selection - power down. */ + if ( LSM303AGR_ACC_W_ODR( (void *)this, LSM303AGR_ACC_ODR_DO_PWR_DOWN ) == MEMS_ERROR ) + { + return 1; + } + + _is_enabled = 0; + + return 0; +} + +/** + * @brief Read ID of LSM303AGR Accelerometer + * @param p_id the pointer where the ID of the device is stored + * @retval 0 in case of success, an error code otherwise + */ +int LSM303AGRAccSensor::read_id(uint8_t *id) +{ + if(!id) + { + return 1; + } + + /* Read WHO AM I register */ + if ( LSM303AGR_ACC_R_WHO_AM_I( (void *)this, id ) == MEMS_ERROR ) + { + return 1; + } + + return 0; +} + +/** + * @brief Read data from LSM303AGR Accelerometer + * @param pData the pointer where the accelerometer data are stored + * @retval 0 in case of success, an error code otherwise + */ +int LSM303AGRAccSensor::get_x_axes(int32_t *pData) +{ + int data[3]; + + /* Read data from LSM303AGR. */ + if ( !LSM303AGR_ACC_Get_Acceleration((void *)this, data) ) + { + return 1; + } + + /* Calculate the data. */ + pData[0] = (int32_t)data[0]; + pData[1] = (int32_t)data[1]; + pData[2] = (int32_t)data[2]; + + return 0; +} + +/** + * @brief Read Accelerometer Sensitivity + * @param pfData the pointer where the accelerometer sensitivity is stored + * @retval 0 in case of success, an error code otherwise + */ +int LSM303AGRAccSensor::get_x_sensitivity(float *pfData) +{ + LSM303AGR_ACC_LPEN_t lp_value; + LSM303AGR_ACC_HR_t hr_value; + + /* Read low power flag */ + if( LSM303AGR_ACC_R_LOWPWR_EN( (void *)this, &lp_value ) == MEMS_ERROR ) + { + return 1; + } + + /* Read high performance flag */ + if( LSM303AGR_ACC_R_HiRes( (void *)this, &hr_value ) == MEMS_ERROR ) + { + return 1; + } + + if( lp_value == LSM303AGR_ACC_LPEN_DISABLED && hr_value == LSM303AGR_ACC_HR_DISABLED ) + { + /* Normal Mode */ + return get_x_sensitivity_normal_mode( pfData ); + } else if ( lp_value == LSM303AGR_ACC_LPEN_ENABLED && hr_value == LSM303AGR_ACC_HR_DISABLED ) + { + /* Low Power Mode */ + return get_x_sensitivity_lp_mode( pfData ); + } else if ( lp_value == LSM303AGR_ACC_LPEN_DISABLED && hr_value == LSM303AGR_ACC_HR_ENABLED ) + { + /* High Resolution Mode */ + return get_x_sensitivity_hr_mode( pfData ); + } else + { + /* Not allowed */ + return 1; + } +} + +/** + * @brief Read Accelerometer Sensitivity in Normal Mode + * @param sensitivity the pointer where the accelerometer sensitivity is stored + * @retval 0 in case of success, an error code otherwise + */ +int LSM303AGRAccSensor::get_x_sensitivity_normal_mode( float *sensitivity ) +{ + LSM303AGR_ACC_FS_t fullScale; + + /* Read actual full scale selection from sensor. */ + if ( LSM303AGR_ACC_R_FullScale( (void *)this, &fullScale ) == MEMS_ERROR ) + { + return 1; + } + + /* Store the sensitivity based on actual full scale. */ + switch( fullScale ) + { + case LSM303AGR_ACC_FS_2G: + *sensitivity = ( float )LSM303AGR_ACC_SENSITIVITY_FOR_FS_2G_NORMAL_MODE; + break; + case LSM303AGR_ACC_FS_4G: + *sensitivity = ( float )LSM303AGR_ACC_SENSITIVITY_FOR_FS_4G_NORMAL_MODE; + break; + case LSM303AGR_ACC_FS_8G: + *sensitivity = ( float )LSM303AGR_ACC_SENSITIVITY_FOR_FS_8G_NORMAL_MODE; + break; + case LSM303AGR_ACC_FS_16G: + *sensitivity = ( float )LSM303AGR_ACC_SENSITIVITY_FOR_FS_16G_NORMAL_MODE; + break; + default: + *sensitivity = -1.0f; + return 1; + } + + return 0; +} + +/** + * @brief Read Accelerometer Sensitivity in LP Mode + * @param sensitivity the pointer where the accelerometer sensitivity is stored + * @retval 0 in case of success, an error code otherwise + */ +int LSM303AGRAccSensor::get_x_sensitivity_lp_mode( float *sensitivity ) +{ + LSM303AGR_ACC_FS_t fullScale; + + /* Read actual full scale selection from sensor. */ + if ( LSM303AGR_ACC_R_FullScale( (void *)this, &fullScale ) == MEMS_ERROR ) + { + return 1; + } + + /* Store the sensitivity based on actual full scale. */ + switch( fullScale ) + { + case LSM303AGR_ACC_FS_2G: + *sensitivity = ( float )LSM303AGR_ACC_SENSITIVITY_FOR_FS_2G_LOW_POWER_MODE; + break; + case LSM303AGR_ACC_FS_4G: + *sensitivity = ( float )LSM303AGR_ACC_SENSITIVITY_FOR_FS_4G_LOW_POWER_MODE; + break; + case LSM303AGR_ACC_FS_8G: + *sensitivity = ( float )LSM303AGR_ACC_SENSITIVITY_FOR_FS_8G_LOW_POWER_MODE; + break; + case LSM303AGR_ACC_FS_16G: + *sensitivity = ( float )LSM303AGR_ACC_SENSITIVITY_FOR_FS_16G_LOW_POWER_MODE; + break; + default: + *sensitivity = -1.0f; + return 1; + } + + return 0; +} + +/** + * @brief Read Accelerometer Sensitivity in HR Mode + * @param sensitivity the pointer where the accelerometer sensitivity is stored + * @retval 0 in case of success, an error code otherwise + */ +int LSM303AGRAccSensor::get_x_sensitivity_hr_mode( float *sensitivity ) +{ + LSM303AGR_ACC_FS_t fullScale; + + /* Read actual full scale selection from sensor. */ + if ( LSM303AGR_ACC_R_FullScale( (void *)this, &fullScale ) == MEMS_ERROR ) + { + return 1; + } + + /* Store the sensitivity based on actual full scale. */ + switch( fullScale ) + { + case LSM303AGR_ACC_FS_2G: + *sensitivity = ( float )LSM303AGR_ACC_SENSITIVITY_FOR_FS_2G_HIGH_RESOLUTION_MODE; + break; + case LSM303AGR_ACC_FS_4G: + *sensitivity = ( float )LSM303AGR_ACC_SENSITIVITY_FOR_FS_4G_HIGH_RESOLUTION_MODE; + break; + case LSM303AGR_ACC_FS_8G: + *sensitivity = ( float )LSM303AGR_ACC_SENSITIVITY_FOR_FS_8G_HIGH_RESOLUTION_MODE; + break; + case LSM303AGR_ACC_FS_16G: + *sensitivity = ( float )LSM303AGR_ACC_SENSITIVITY_FOR_FS_16G_HIGH_RESOLUTION_MODE; + break; + default: + *sensitivity = -1.0f; + return 1; + } + + return 0; +} + +/** + * @brief Read raw data from LSM303AGR Accelerometer + * @param pData the pointer where the accelerometer raw data are stored + * @retval 0 in case of success, an error code otherwise + */ +int LSM303AGRAccSensor::get_x_axes_raw(int16_t *pData) +{ + uint8_t regValue[6] = {0, 0, 0, 0, 0, 0}; + u8_t shift = 0; + LSM303AGR_ACC_LPEN_t lp; + LSM303AGR_ACC_HR_t hr; + + /* Determine which operational mode the acc is set */ + if(!LSM303AGR_ACC_R_HiRes( (void *)this, &hr )) { + return 1; + } + + if(!LSM303AGR_ACC_R_LOWPWR_EN( (void *)this, &lp )) { + return 1; + } + + if (lp == LSM303AGR_ACC_LPEN_ENABLED && hr == LSM303AGR_ACC_HR_DISABLED) { + /* op mode is LP 8-bit */ + shift = 8; + } else if (lp == LSM303AGR_ACC_LPEN_DISABLED && hr == LSM303AGR_ACC_HR_DISABLED) { + /* op mode is Normal 10-bit */ + shift = 6; + } else if (lp == LSM303AGR_ACC_LPEN_DISABLED && hr == LSM303AGR_ACC_HR_ENABLED) { + /* op mode is HR 12-bit */ + shift = 4; + } else { + return 1; + } + + /* Read output registers from LSM303AGR_ACC_GYRO_OUTX_L_XL to LSM303AGR_ACC_GYRO_OUTZ_H_XL. */ + if (!LSM303AGR_ACC_Get_Raw_Acceleration( (void *)this, ( uint8_t* )regValue )) + { + return 1; + } + + /* Format the data. */ + pData[0] = ( ( ( ( ( int16_t )regValue[1] ) << 8 ) + ( int16_t )regValue[0] ) >> shift ); + pData[1] = ( ( ( ( ( int16_t )regValue[3] ) << 8 ) + ( int16_t )regValue[2] ) >> shift ); + pData[2] = ( ( ( ( ( int16_t )regValue[5] ) << 8 ) + ( int16_t )regValue[4] ) >> shift ); + + return 0; +} + +/** + * @brief Read LSM303AGR Accelerometer output data rate + * @param odr the pointer to the output data rate + * @retval 0 in case of success, an error code otherwise + */ +int LSM303AGRAccSensor::get_x_odr(float* odr) +{ + LSM303AGR_ACC_ODR_t odr_low_level; + + if ( LSM303AGR_ACC_R_ODR( (void *)this, &odr_low_level ) == MEMS_ERROR ) + { + return 1; + } + + switch( odr_low_level ) + { + case LSM303AGR_ACC_ODR_DO_PWR_DOWN: + *odr = 0.0f; + break; + case LSM303AGR_ACC_ODR_DO_1Hz: + *odr = 1.0f; + break; + case LSM303AGR_ACC_ODR_DO_10Hz: + *odr = 10.0f; + break; + case LSM303AGR_ACC_ODR_DO_25Hz: + *odr = 25.0f; + break; + case LSM303AGR_ACC_ODR_DO_50Hz: + *odr = 50.0f; + break; + case LSM303AGR_ACC_ODR_DO_100Hz: + *odr = 100.0f; + break; + case LSM303AGR_ACC_ODR_DO_200Hz: + *odr = 200.0f; + break; + case LSM303AGR_ACC_ODR_DO_400Hz: + *odr = 400.0f; + break; + default: + *odr = -1.0f; + return 1; + } + + return 0; +} + +/** + * @brief Set ODR + * @param odr the output data rate to be set + * @retval 0 in case of success, an error code otherwise + */ +int LSM303AGRAccSensor::set_x_odr(float odr) +{ + if(_is_enabled == 1) + { + if(set_x_odr_when_enabled(odr) == 1) + { + return 1; + } + } + else + { + if(set_x_odr_when_disabled(odr) == 1) + { + return 1; + } + } + + return 0; +} + +/** + * @brief Set ODR when enabled + * @param odr the output data rate to be set + * @retval 0 in case of success, an error code otherwise + */ +int LSM303AGRAccSensor::set_x_odr_when_enabled(float odr) +{ + LSM303AGR_ACC_ODR_t new_odr; + + new_odr = ( odr <= 1.0f ) ? LSM303AGR_ACC_ODR_DO_1Hz + : ( odr <= 10.0f ) ? LSM303AGR_ACC_ODR_DO_10Hz + : ( odr <= 25.0f ) ? LSM303AGR_ACC_ODR_DO_25Hz + : ( odr <= 50.0f ) ? LSM303AGR_ACC_ODR_DO_50Hz + : ( odr <= 100.0f ) ? LSM303AGR_ACC_ODR_DO_100Hz + : ( odr <= 200.0f ) ? LSM303AGR_ACC_ODR_DO_200Hz + : LSM303AGR_ACC_ODR_DO_400Hz; + + if ( LSM303AGR_ACC_W_ODR( (void *)this, new_odr ) == MEMS_ERROR ) + { + return 1; + } + + return 0; +} + +/** + * @brief Set ODR when disabled + * @param odr the output data rate to be set + * @retval 0 in case of success, an error code otherwise + */ +int LSM303AGRAccSensor::set_x_odr_when_disabled(float odr) +{ + _last_odr = ( odr <= 1.0f ) ? 1.0f + : ( odr <= 10.0f ) ? 10.0f + : ( odr <= 25.0f ) ? 25.0f + : ( odr <= 50.0f ) ? 50.0f + : ( odr <= 100.0f ) ? 100.0f + : ( odr <= 200.0f ) ? 200.0f + : 400.0f; + + return 0; +} + + +/** + * @brief Read LSM303AGR Accelerometer full scale + * @param fullScale the pointer to the full scale + * @retval 0 in case of success, an error code otherwise + */ +int LSM303AGRAccSensor::get_x_fs(float* fullScale) +{ + LSM303AGR_ACC_FS_t fs_low_level; + + if ( LSM303AGR_ACC_R_FullScale( (void *)this, &fs_low_level ) == MEMS_ERROR ) + { + return 1; + } + + switch( fs_low_level ) + { + case LSM303AGR_ACC_FS_2G: + *fullScale = 2.0f; + break; + case LSM303AGR_ACC_FS_4G: + *fullScale = 4.0f; + break; + case LSM303AGR_ACC_FS_8G: + *fullScale = 8.0f; + break; + case LSM303AGR_ACC_FS_16G: + *fullScale = 16.0f; + break; + default: + *fullScale = -1.0f; + return 1; + } + + return 0; +} + +/** + * @brief Set full scale + * @param fullScale the full scale to be set + * @retval 0 in case of success, an error code otherwise + */ +int LSM303AGRAccSensor::set_x_fs(float fullScale) +{ + LSM303AGR_ACC_FS_t new_fs; + + new_fs = ( fullScale <= 2.0f ) ? LSM303AGR_ACC_FS_2G + : ( fullScale <= 4.0f ) ? LSM303AGR_ACC_FS_4G + : ( fullScale <= 8.0f ) ? LSM303AGR_ACC_FS_8G + : LSM303AGR_ACC_FS_16G; + + if ( LSM303AGR_ACC_W_FullScale( (void *)this, new_fs ) == MEMS_ERROR ) + { + return 1; + } + + return 0; +} + +/** + * @brief Read accelerometer data from register + * @param reg register address + * @param data register data + * @retval 0 in case of success + * @retval 1 in case of failure + */ +int LSM303AGRAccSensor::read_reg( uint8_t reg, uint8_t *data ) +{ + + if ( LSM303AGR_ACC_read_reg( (void *)this, reg, data ) == MEMS_ERROR ) + { + return 1; + } + + return 0; +} + +/** + * @brief Write accelerometer data to register + * @param reg register address + * @param data register data + * @retval 0 in case of success + * @retval 1 in case of failure + */ +int LSM303AGRAccSensor::write_reg( uint8_t reg, uint8_t data ) +{ + + if ( LSM303AGR_ACC_write_reg( (void *)this, reg, data ) == MEMS_ERROR ) + { + return 1; + } + + return 0; +} + +uint8_t LSM303AGR_ACC_io_write( void *handle, uint8_t WriteAddr, uint8_t *pBuffer, uint16_t nBytesToWrite ) +{ + return ((LSM303AGRAccSensor *)handle)->io_write(pBuffer, WriteAddr, nBytesToWrite); +} + +uint8_t LSM303AGR_ACC_io_read( void *handle, uint8_t ReadAddr, uint8_t *pBuffer, uint16_t nBytesToRead ) +{ + return ((LSM303AGRAccSensor *)handle)->io_read(pBuffer, ReadAddr, nBytesToRead); +} diff --git a/LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/LSM303AGR/LSM303AGRAccSensor.h b/LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/LSM303AGR/LSM303AGRAccSensor.h new file mode 100644 index 0000000..b2959ca --- /dev/null +++ b/LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/LSM303AGR/LSM303AGRAccSensor.h @@ -0,0 +1,167 @@ +/** + ****************************************************************************** + * @file LSM303AGRAccSensor.h + * @author CLab + * @version V1.0.0 + * @date 5 August 2016 + * @brief Abstract Class of an LSM303AGR accelerometer sensor. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + +/* Prevent recursive inclusion -----------------------------------------------*/ + +#ifndef __LSM303AGRAccSensor_H__ +#define __LSM303AGRAccSensor_H__ + + +/* Includes ------------------------------------------------------------------*/ + +#include "DevI2C.h" +#include "LSM303AGR_acc_driver.h" +#include "MotionSensor.h" +#include + +/* Defines -------------------------------------------------------------------*/ +#define LSM303AGR_ACC_SENSITIVITY_FOR_FS_2G_NORMAL_MODE 3.900f /**< Sensitivity value for 2 g full scale and normal mode [mg/LSB] */ +#define LSM303AGR_ACC_SENSITIVITY_FOR_FS_2G_HIGH_RESOLUTION_MODE 0.980f /**< Sensitivity value for 2 g full scale and high resolution mode [mg/LSB] */ +#define LSM303AGR_ACC_SENSITIVITY_FOR_FS_2G_LOW_POWER_MODE 15.630f /**< Sensitivity value for 2 g full scale and low power mode [mg/LSB] */ +#define LSM303AGR_ACC_SENSITIVITY_FOR_FS_4G_NORMAL_MODE 7.820f /**< Sensitivity value for 4 g full scale and normal mode [mg/LSB] */ +#define LSM303AGR_ACC_SENSITIVITY_FOR_FS_4G_HIGH_RESOLUTION_MODE 1.950f /**< Sensitivity value for 4 g full scale and high resolution mode [mg/LSB] */ +#define LSM303AGR_ACC_SENSITIVITY_FOR_FS_4G_LOW_POWER_MODE 31.260f /**< Sensitivity value for 4 g full scale and low power mode [mg/LSB] */ +#define LSM303AGR_ACC_SENSITIVITY_FOR_FS_8G_NORMAL_MODE 15.630f /**< Sensitivity value for 8 g full scale and normal mode [mg/LSB] */ +#define LSM303AGR_ACC_SENSITIVITY_FOR_FS_8G_HIGH_RESOLUTION_MODE 3.900f /**< Sensitivity value for 8 g full scale and high resolution mode [mg/LSB] */ +#define LSM303AGR_ACC_SENSITIVITY_FOR_FS_8G_LOW_POWER_MODE 62.520f /**< Sensitivity value for 8 g full scale and low power mode [mg/LSB] */ +#define LSM303AGR_ACC_SENSITIVITY_FOR_FS_16G_NORMAL_MODE 46.900f /**< Sensitivity value for 16 g full scale and normal mode [mg/LSB] */ +#define LSM303AGR_ACC_SENSITIVITY_FOR_FS_16G_HIGH_RESOLUTION_MODE 11.720f /**< Sensitivity value for 16 g full scale and high resolution mode [mg/LSB] */ +#define LSM303AGR_ACC_SENSITIVITY_FOR_FS_16G_LOW_POWER_MODE 187.580f /**< Sensitivity value for 16 g full scale and low power mode [mg/LSB] */ + +/* Class Declaration ---------------------------------------------------------*/ + +/** + * Abstract class of an LSM303AGR Inertial Measurement Unit (IMU) 6 axes + * sensor. + */ +class LSM303AGRAccSensor : public MotionSensor +{ + public: + LSM303AGRAccSensor(SPI *spi, PinName cs_pin, PinName int1_pin=NC, PinName int2_pin=NC); // SPI3W ONLY + LSM303AGRAccSensor(DevI2C *i2c, uint8_t address=LSM303AGR_ACC_I2C_ADDRESS, PinName int1_pin=NC, PinName int2_pin=NC); + virtual int init(void *init); + virtual int read_id(uint8_t *id); + virtual int get_x_axes(int32_t *pData); + virtual int get_x_axes_raw(int16_t *pData); + virtual int get_x_sensitivity(float *pfData); + virtual int get_x_odr(float *odr); + virtual int set_x_odr(float odr); + virtual int get_x_fs(float *fullScale); + virtual int set_x_fs(float fullScale); + int enable(void); + int disable(void); + int read_reg(uint8_t reg, uint8_t *data); + int write_reg(uint8_t reg, uint8_t data); + + /** + * @brief Utility function to read data. + * @param pBuffer: pointer to data to be read. + * @param RegisterAddr: specifies internal address register to be read. + * @param NumByteToRead: number of bytes to be read. + * @retval 0 if ok, an error code otherwise. + */ + uint8_t io_read(uint8_t* pBuffer, uint8_t RegisterAddr, uint16_t NumByteToRead) + { + if (_dev_spi) { + /* Write Reg Address */ + _dev_spi->lock(); + _cs_pin = 0; + /* Write RD Reg Address with RD bit*/ + uint8_t TxByte = RegisterAddr | 0x80; + _dev_spi->write((char *)&TxByte, 1, (char *)pBuffer, (int) NumByteToRead); + _cs_pin = 1; + _dev_spi->unlock(); + return 0; + } + if (_dev_i2c) return (uint8_t) _dev_i2c->i2c_read(pBuffer, _address, RegisterAddr, NumByteToRead); + return 1; + } + + /** + * @brief Utility function to write data. + * @param pBuffer: pointer to data to be written. + * @param RegisterAddr: specifies internal address register to be written. + * @param NumByteToWrite: number of bytes to write. + * @retval 0 if ok, an error code otherwise. + */ + uint8_t io_write(uint8_t* pBuffer, uint8_t RegisterAddr, uint16_t NumByteToWrite) + { + if (_dev_spi) { + _dev_spi->lock(); + _cs_pin = 0; + _dev_spi->write(RegisterAddr); + _dev_spi->write((char *)pBuffer, (int) NumByteToWrite, NULL, 0); + _cs_pin = 1; + _dev_spi->unlock(); + return 0; + } + if (_dev_i2c) return (uint8_t)_dev_i2c->i2c_write(pBuffer, _address, RegisterAddr, NumByteToWrite); + return 1; + } + + private: + int set_x_odr_when_enabled(float odr); + int set_x_odr_when_disabled(float odr); + int get_x_sensitivity_normal_mode(float *sensitivity ); + int get_x_sensitivity_lp_mode(float *sensitivity ); + int get_x_sensitivity_hr_mode(float *sensitivity ); + + /* Helper classes. */ + DevI2C *_dev_i2c; + SPI *_dev_spi; + + /* Configuration */ + uint8_t _address; + DigitalOut _cs_pin; + InterruptIn _int1_pin; + InterruptIn _int2_pin; + + uint8_t _is_enabled; + float _last_odr; +}; + +#ifdef __cplusplus + extern "C" { +#endif +uint8_t LSM303AGR_ACC_io_write( void *handle, uint8_t WriteAddr, uint8_t *pBuffer, uint16_t nBytesToWrite ); +uint8_t LSM303AGR_ACC_io_read( void *handle, uint8_t ReadAddr, uint8_t *pBuffer, uint16_t nBytesToRead ); +#ifdef __cplusplus + } +#endif + +#endif diff --git a/LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/LSM303AGR/LSM303AGRMagSensor.cpp b/LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/LSM303AGR/LSM303AGRMagSensor.cpp new file mode 100644 index 0000000..d64d092 --- /dev/null +++ b/LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/LSM303AGR/LSM303AGRMagSensor.cpp @@ -0,0 +1,352 @@ +/** + ****************************************************************************** + * @file LSM303AGRMagSensor.cpp + * @author CLab + * @version V1.0.0 + * @date 5 August 2016 + * @brief Implementation an LSM303AGR magnetometer sensor. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + +/* Includes ------------------------------------------------------------------*/ + +#include "LSM303AGRMagSensor.h" + + +/* Class Implementation ------------------------------------------------------*/ +LSM303AGRMagSensor::LSM303AGRMagSensor(SPI *spi, PinName cs_pin, PinName intmag_pin) : + _dev_spi(spi), _cs_pin(cs_pin), _intmag_pin(intmag_pin) // SPI3W ONLY +{ + assert (spi); + if (cs_pin == NC) + { + printf ("ERROR LSM303AGRMagSensor CS MUST NOT BE NC\n\r"); + _dev_spi = NULL; + _dev_i2c=NULL; + return; + } + _cs_pin = 0; // enable SPI3W disable I2C + _dev_i2c=NULL; + + LSM303AGR_ACC_W_SPI_mode((void *)this, LSM303AGR_ACC_SIM_3_WIRES); +} +/** Constructor + * @param i2c object of an helper class which handles the I2C peripheral + * @param address the address of the component's instance + */ +LSM303AGRMagSensor::LSM303AGRMagSensor(DevI2C *i2c, uint8_t address, PinName intmag_pin) : + _dev_i2c(i2c), _address(address), _cs_pin(NC), _intmag_pin(intmag_pin) +{ + assert (i2c); + _dev_spi = NULL; +} + +/** + * @brief Initializing the component. + * @param[in] init pointer to device specific initalization structure. + * @retval "0" in case of success, an error code otherwise. + */ +int LSM303AGRMagSensor::init(void *init) +{ + /* Operating mode selection - power down */ + if ( LSM303AGR_MAG_W_MD( (void *)this, LSM303AGR_MAG_MD_IDLE1_MODE ) == MEMS_ERROR ) + { + return 1; + } + + /* Enable BDU */ + if ( LSM303AGR_MAG_W_BDU( (void *)this, LSM303AGR_MAG_BDU_ENABLED ) == MEMS_ERROR ) + { + return 1; + } + + if ( set_m_odr( 100.0f ) == 1 ) + { + return 1; + } + + if ( set_m_fs( 50.0f ) == 1 ) + { + return 1; + } + + if ( LSM303AGR_MAG_W_ST( (void *)this, LSM303AGR_MAG_ST_DISABLED ) == MEMS_ERROR ) + { + return 1; + } + + return 0; +} + +/** + * @brief Enable LSM303AGR magnetometer + * @retval 0 in case of success, an error code otherwise + */ +int LSM303AGRMagSensor::enable(void) +{ + /* Operating mode selection */ + if ( LSM303AGR_MAG_W_MD( (void *)this, LSM303AGR_MAG_MD_CONTINUOS_MODE ) == MEMS_ERROR ) + { + return 1; + } + + return 0; +} + +/** + * @brief Disable LSM303AGR magnetometer + * @retval 0 in case of success, an error code otherwise + */ +int LSM303AGRMagSensor::disable(void) +{ + /* Operating mode selection - power down */ + if ( LSM303AGR_MAG_W_MD( (void *)this, LSM303AGR_MAG_MD_IDLE1_MODE ) == MEMS_ERROR ) + { + return 1; + } + + return 0; +} + +/** + * @brief Read ID of LSM303AGR Magnetometer + * @param p_id the pointer where the ID of the device is stored + * @retval 0 in case of success, an error code otherwise + */ +int LSM303AGRMagSensor::read_id(uint8_t *id) +{ + if(!id) + { + return 1; + } + + /* Read WHO AM I register */ + if ( LSM303AGR_MAG_R_WHO_AM_I( (void *)this, id ) == MEMS_ERROR ) + { + return 1; + } + + return 0; +} + +/** + * @brief Read data from LSM303AGR Magnetometer + * @param pData the pointer where the magnetometer data are stored + * @retval 0 in case of success, an error code otherwise + */ +int LSM303AGRMagSensor::get_m_axes(int32_t *pData) +{ + int16_t pDataRaw[3]; + float sensitivity = 0; + + /* Read raw data from LSM303AGR output register. */ + if ( get_m_axes_raw( pDataRaw ) == 1 ) + { + return 1; + } + + /* Get LSM303AGR actual sensitivity. */ + if ( get_m_sensitivity( &sensitivity ) == 1 ) + { + return 1; + } + + /* Calculate the data. */ + pData[0] = ( int32_t )( pDataRaw[0] * sensitivity ); + pData[1] = ( int32_t )( pDataRaw[1] * sensitivity ); + pData[2] = ( int32_t )( pDataRaw[2] * sensitivity ); + + return 0; +} + +/** + * @brief Read Magnetometer Sensitivity + * @param pfData the pointer where the magnetometer sensitivity is stored + * @retval 0 in case of success, an error code otherwise + */ +int LSM303AGRMagSensor::get_m_sensitivity(float *pfData) +{ + *pfData = 1.5f; + + return 0; +} + +/** + * @brief Read raw data from LSM303AGR Magnetometer + * @param pData the pointer where the magnetomer raw data are stored + * @retval 0 in case of success, an error code otherwise + */ +int LSM303AGRMagSensor::get_m_axes_raw(int16_t *pData) +{ + uint8_t regValue[6] = {0, 0, 0, 0, 0, 0}; + int16_t *regValueInt16; + + /* Read output registers from LSM303AGR_MAG_OUTX_L to LSM303AGR_MAG_OUTZ_H. */ + if ( LSM303AGR_MAG_Get_Raw_Magnetic( (void *)this, regValue ) == MEMS_ERROR ) + { + return 1; + } + + regValueInt16 = (int16_t *)regValue; + + /* Format the data. */ + pData[0] = regValueInt16[0]; + pData[1] = regValueInt16[1]; + pData[2] = regValueInt16[2]; + + return 0; +} + +/** + * @brief Read LSM303AGR Magnetometer output data rate + * @param odr the pointer to the output data rate + * @retval 0 in case of success, an error code otherwise + */ +int LSM303AGRMagSensor::get_m_odr(float* odr) +{ + LSM303AGR_MAG_ODR_t odr_low_level; + + if ( LSM303AGR_MAG_R_ODR( (void *)this, &odr_low_level ) == MEMS_ERROR ) + { + return 1; + } + + switch( odr_low_level ) + { + case LSM303AGR_MAG_ODR_10Hz: + *odr = 10.000f; + break; + case LSM303AGR_MAG_ODR_20Hz: + *odr = 20.000f; + break; + case LSM303AGR_MAG_ODR_50Hz: + *odr = 50.000f; + break; + case LSM303AGR_MAG_ODR_100Hz: + *odr = 100.000f; + break; + default: + *odr = -1.000f; + return 1; + } + return 0; +} + +/** + * @brief Set ODR + * @param odr the output data rate to be set + * @retval 0 in case of success, an error code otherwise + */ +int LSM303AGRMagSensor::set_m_odr(float odr) +{ + LSM303AGR_MAG_ODR_t new_odr; + + new_odr = ( odr <= 10.000f ) ? LSM303AGR_MAG_ODR_10Hz + : ( odr <= 20.000f ) ? LSM303AGR_MAG_ODR_20Hz + : ( odr <= 50.000f ) ? LSM303AGR_MAG_ODR_50Hz + : LSM303AGR_MAG_ODR_100Hz; + + if ( LSM303AGR_MAG_W_ODR( (void *)this, new_odr ) == MEMS_ERROR ) + { + return 1; + } + + return 0; +} + + +/** + * @brief Read LSM303AGR Magnetometer full scale + * @param fullScale the pointer to the output data rate + * @retval 0 in case of success, an error code otherwise + */ +int LSM303AGRMagSensor::get_m_fs(float* fullScale) +{ + *fullScale = 50.0f; + + return 0; +} + +/** + * @brief Set full scale + * @param fullScale the full scale to be set + * @retval 0 in case of success, an error code otherwise + */ +int LSM303AGRMagSensor::set_m_fs(float fullScale) +{ + return 0; +} + + +/** + * @brief Read magnetometer data from register + * @param reg register address + * @param data register data + * @retval 0 in case of success + * @retval 1 in case of failure + */ +int LSM303AGRMagSensor::read_reg( uint8_t reg, uint8_t *data ) +{ + if ( LSM303AGR_MAG_read_reg( (void *)this, reg, data ) == MEMS_ERROR ) + { + return 1; + } + + return 0; +} + + +/** + * @brief Write magnetometer data to register + * @param reg register address + * @param data register data + * @retval 0 in case of success + * @retval 1 in case of failure + */ +int LSM303AGRMagSensor::write_reg( uint8_t reg, uint8_t data ) +{ + if ( LSM303AGR_MAG_write_reg( (void *)this, reg, data ) == MEMS_ERROR ) + { + return 1; + } + + return 0; +} + +uint8_t LSM303AGR_MAG_io_write( void *handle, uint8_t WriteAddr, uint8_t *pBuffer, uint16_t nBytesToWrite ) +{ + return ((LSM303AGRMagSensor *)handle)->io_write(pBuffer, WriteAddr, nBytesToWrite); +} + +uint8_t LSM303AGR_MAG_io_read( void *handle, uint8_t ReadAddr, uint8_t *pBuffer, uint16_t nBytesToRead ) +{ + return ((LSM303AGRMagSensor *)handle)->io_read(pBuffer, ReadAddr, nBytesToRead); +} diff --git a/LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/LSM303AGR/LSM303AGRMagSensor.h b/LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/LSM303AGR/LSM303AGRMagSensor.h new file mode 100644 index 0000000..e35fbaa --- /dev/null +++ b/LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/LSM303AGR/LSM303AGRMagSensor.h @@ -0,0 +1,145 @@ +/** + ****************************************************************************** + * @file LSM303AGRMagSensor.h + * @author CLab + * @version V1.0.0 + * @date 5 August 2016 + * @brief Abstract Class of an LSM303AGR magnetometer sensor. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + +/* Prevent recursive inclusion -----------------------------------------------*/ + +#ifndef __LSM303AGRMagSensor_H__ +#define __LSM303AGRMagSensor_H__ + + +/* Includes ------------------------------------------------------------------*/ + +#include "DevI2C.h" +#include "LSM303AGR_mag_driver.h" +#include "LSM303AGR_acc_driver.h" +#include "MagneticSensor.h" +#include + +/* Class Declaration ---------------------------------------------------------*/ + +/** + * Abstract class of an LSM303AGR Inertial Measurement Unit (IMU) 6 axes + * sensor. + */ +class LSM303AGRMagSensor : public MagneticSensor +{ + public: + LSM303AGRMagSensor(SPI *spi, PinName cs_pin, PinName intmag_pin=NC); // SPI3W ONLY + LSM303AGRMagSensor(DevI2C *i2c, uint8_t address=LSM303AGR_MAG_I2C_ADDRESS, PinName intmag_pin=NC); + virtual int init(void *init); + virtual int read_id(uint8_t *id); + virtual int get_m_axes(int32_t *pData); + virtual int get_m_axes_raw(int16_t *pData); + int enable(void); + int disable(void); + int get_m_sensitivity(float *pfData); + int get_m_odr(float *odr); + int set_m_odr(float odr); + int get_m_fs(float *fullScale); + int set_m_fs(float fullScale); + int read_reg(uint8_t reg, uint8_t *data); + int write_reg(uint8_t reg, uint8_t data); + + /** + * @brief Utility function to read data. + * @param pBuffer: pointer to data to be read. + * @param RegisterAddr: specifies internal address register to be read. + * @param NumByteToRead: number of bytes to be read. + * @retval 0 if ok, an error code otherwise. + */ + uint8_t io_read(uint8_t* pBuffer, uint8_t RegisterAddr, uint16_t NumByteToRead) + { + if (_dev_spi) { + /* Write Reg Address */ + _dev_spi->lock(); + _cs_pin = 0; + /* Write RD Reg Address with RD bit*/ + uint8_t TxByte = RegisterAddr | 0x80; + _dev_spi->write((char *)&TxByte, 1, (char *)pBuffer, (int) NumByteToRead); + _cs_pin = 1; + _dev_spi->unlock(); + return 0; + } + if (_dev_i2c) return (uint8_t) _dev_i2c->i2c_read(pBuffer, _address, RegisterAddr, NumByteToRead); + return 1; + } + + /** + * @brief Utility function to write data. + * @param pBuffer: pointer to data to be written. + * @param RegisterAddr: specifies internal address register to be written. + * @param NumByteToWrite: number of bytes to write. + * @retval 0 if ok, an error code otherwise. + */ + uint8_t io_write(uint8_t* pBuffer, uint8_t RegisterAddr, uint16_t NumByteToWrite) + { + if (_dev_spi) { + _dev_spi->lock(); + _cs_pin = 0; + _dev_spi->write(RegisterAddr); + _dev_spi->write((char *)pBuffer, (int) NumByteToWrite, NULL, 0); + _cs_pin = 1; + _dev_spi->unlock(); + return 0; + } + if (_dev_i2c) return (uint8_t) _dev_i2c->i2c_write(pBuffer, _address, RegisterAddr, NumByteToWrite); + return 1; + } + + private: + + /* Helper classes. */ + DevI2C *_dev_i2c; + SPI *_dev_spi; + + /* Configuration */ + uint8_t _address; + DigitalOut _cs_pin; + InterruptIn _intmag_pin; +}; + +#ifdef __cplusplus + extern "C" { +#endif +uint8_t LSM303AGR_MAG_io_write( void *handle, uint8_t WriteAddr, uint8_t *pBuffer, uint16_t nBytesToWrite ); +uint8_t LSM303AGR_MAG_io_read( void *handle, uint8_t ReadAddr, uint8_t *pBuffer, uint16_t nBytesToRead ); +#ifdef __cplusplus + } +#endif + +#endif diff --git a/LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/LSM303AGR/LSM303AGR_acc_driver.c b/LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/LSM303AGR/LSM303AGR_acc_driver.c new file mode 100644 index 0000000..35d72fe --- /dev/null +++ b/LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/LSM303AGR/LSM303AGR_acc_driver.c @@ -0,0 +1,3950 @@ +/** + ****************************************************************************** + * @file LSM303AGR_acc_driver.c + * @author MEMS Application Team + * @version V1.1 + * @date 24-February-2016 + * @brief LSM303AGR Accelerometer driver file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "LSM303AGR_acc_driver.h" + +/* Imported function prototypes ----------------------------------------------*/ +extern uint8_t LSM303AGR_ACC_io_write(void *handle, uint8_t WriteAddr, uint8_t *pBuffer, uint16_t nBytesToWrite); +extern uint8_t LSM303AGR_ACC_io_read(void *handle, uint8_t ReadAddr, uint8_t *pBuffer, uint16_t nBytesToRead); + +/* Private typedef -----------------------------------------------------------*/ + +/* Private define ------------------------------------------------------------*/ + +/* Private macro -------------------------------------------------------------*/ + +/* Private variables ---------------------------------------------------------*/ + +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_read_reg +* Description : Generic Reading function. It must be fullfilled with either +* : I2C or SPI reading functions +* Input : Register Address +* Output : Data REad +* Return : None +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_read_reg(void *handle, u8_t Reg, u8_t* Data) +{ + + if (LSM303AGR_ACC_io_read(handle, Reg, Data, 1)) + { + return MEMS_ERROR; + } + else + { + return MEMS_SUCCESS; + } +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_write_reg +* Description : Generic Writing function. It must be fullfilled with either +* : I2C or SPI writing function +* Input : Register Address, Data to be written +* Output : None +* Return : None +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_write_reg(void *handle, u8_t Reg, u8_t Data) +{ + + if (LSM303AGR_ACC_io_write(handle, Reg, &Data, 1)) + { + return MEMS_ERROR; + } + else + { + return MEMS_SUCCESS; + } +} + +/******************************************************************************* +* Function Name : SwapHighLowByte +* Description : Swap High/low byte in multiple byte values +* It works with minimum 2 byte for every dimension. +* Example x,y,z with 2 byte for every dimension +* +* Input : bufferToSwap -> buffer to swap +* numberOfByte -> the buffer length in byte +* dimension -> number of dimension +* +* Output : bufferToSwap -> buffer swapped +* Return : None +*******************************************************************************/ +void LSM303AGR_ACC_SwapHighLowByte(u8_t *bufferToSwap, u8_t numberOfByte, u8_t dimension) +{ + + u8_t numberOfByteForDimension, i, j; + u8_t tempValue[10]; + + numberOfByteForDimension=numberOfByte/dimension; + + for (i=0; i> LSM303AGR_ACC_IC_POSITION; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_WHO_AM_I +* Description : Read WHO_AM_I +* Input : Pointer to u8_t +* Output : Status of WHO_AM_I +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_WHO_AM_I(void *handle, u8_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_WHO_AM_I_REG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_WHO_AM_I_MASK; //coerce + *value = *value >> LSM303AGR_ACC_WHO_AM_I_POSITION; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_TEMP_EN_bits +* Description : Write TEMP_EN +* Input : LSM303AGR_ACC_TEMP_EN_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_TEMP_EN_bits(void *handle, LSM303AGR_ACC_TEMP_EN_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_TEMP_CFG_REG, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_TEMP_EN_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_TEMP_CFG_REG, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_TEMP_EN_bits +* Description : Read TEMP_EN +* Input : Pointer to LSM303AGR_ACC_TEMP_EN_t +* Output : Status of TEMP_EN see LSM303AGR_ACC_TEMP_EN_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_TEMP_EN_bits(void *handle, LSM303AGR_ACC_TEMP_EN_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_TEMP_CFG_REG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_TEMP_EN_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_ADC_PD +* Description : Write ADC_PD +* Input : LSM303AGR_ACC_ADC_PD_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_ADC_PD(void *handle, LSM303AGR_ACC_ADC_PD_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_TEMP_CFG_REG, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_ADC_PD_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_TEMP_CFG_REG, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_ADC_PD +* Description : Read ADC_PD +* Input : Pointer to LSM303AGR_ACC_ADC_PD_t +* Output : Status of ADC_PD see LSM303AGR_ACC_ADC_PD_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_ADC_PD(void *handle, LSM303AGR_ACC_ADC_PD_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_TEMP_CFG_REG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_ADC_PD_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_XEN +* Description : Write XEN +* Input : LSM303AGR_ACC_XEN_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_XEN(void *handle, LSM303AGR_ACC_XEN_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG1, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_XEN_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_CTRL_REG1, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_XEN +* Description : Read XEN +* Input : Pointer to LSM303AGR_ACC_XEN_t +* Output : Status of XEN see LSM303AGR_ACC_XEN_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_XEN(void *handle, LSM303AGR_ACC_XEN_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG1, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_XEN_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_YEN +* Description : Write YEN +* Input : LSM303AGR_ACC_YEN_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_YEN(void *handle, LSM303AGR_ACC_YEN_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG1, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_YEN_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_CTRL_REG1, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_YEN +* Description : Read YEN +* Input : Pointer to LSM303AGR_ACC_YEN_t +* Output : Status of YEN see LSM303AGR_ACC_YEN_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_YEN(void *handle, LSM303AGR_ACC_YEN_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG1, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_YEN_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_ZEN +* Description : Write ZEN +* Input : LSM303AGR_ACC_ZEN_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_ZEN(void *handle, LSM303AGR_ACC_ZEN_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG1, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_ZEN_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_CTRL_REG1, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_ZEN +* Description : Read ZEN +* Input : Pointer to LSM303AGR_ACC_ZEN_t +* Output : Status of ZEN see LSM303AGR_ACC_ZEN_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_ZEN(void *handle, LSM303AGR_ACC_ZEN_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG1, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_ZEN_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_LOWPWR_EN +* Description : Write LPEN +* Input : LSM303AGR_ACC_LPEN_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_LOWPWR_EN(void *handle, LSM303AGR_ACC_LPEN_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG1, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_LPEN_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_CTRL_REG1, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_LOWPWR_EN +* Description : Read LPEN +* Input : Pointer to LSM303AGR_ACC_LPEN_t +* Output : Status of LPEN see LSM303AGR_ACC_LPEN_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_LOWPWR_EN(void *handle, LSM303AGR_ACC_LPEN_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG1, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_LPEN_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_ODR +* Description : Write ODR +* Input : LSM303AGR_ACC_ODR_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_ODR(void *handle, LSM303AGR_ACC_ODR_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG1, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_ODR_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_CTRL_REG1, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_ODR +* Description : Read ODR +* Input : Pointer to LSM303AGR_ACC_ODR_t +* Output : Status of ODR see LSM303AGR_ACC_ODR_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_ODR(void *handle, LSM303AGR_ACC_ODR_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG1, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_ODR_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_hpf_aoi_en_int1 +* Description : Write HPIS1 +* Input : LSM303AGR_ACC_HPIS1_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_hpf_aoi_en_int1(void *handle, LSM303AGR_ACC_HPIS1_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG2, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_HPIS1_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_CTRL_REG2, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_hpf_aoi_en_int1 +* Description : Read HPIS1 +* Input : Pointer to LSM303AGR_ACC_HPIS1_t +* Output : Status of HPIS1 see LSM303AGR_ACC_HPIS1_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_hpf_aoi_en_int1(void *handle, LSM303AGR_ACC_HPIS1_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG2, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_HPIS1_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_hpf_aoi_en_int2 +* Description : Write HPIS2 +* Input : LSM303AGR_ACC_HPIS2_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_hpf_aoi_en_int2(void *handle, LSM303AGR_ACC_HPIS2_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG2, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_HPIS2_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_CTRL_REG2, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_hpf_aoi_en_int2 +* Description : Read HPIS2 +* Input : Pointer to LSM303AGR_ACC_HPIS2_t +* Output : Status of HPIS2 see LSM303AGR_ACC_HPIS2_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_hpf_aoi_en_int2(void *handle, LSM303AGR_ACC_HPIS2_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG2, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_HPIS2_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_hpf_click_en +* Description : Write HPCLICK +* Input : LSM303AGR_ACC_HPCLICK_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_hpf_click_en(void *handle, LSM303AGR_ACC_HPCLICK_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG2, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_HPCLICK_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_CTRL_REG2, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_hpf_click_en +* Description : Read HPCLICK +* Input : Pointer to LSM303AGR_ACC_HPCLICK_t +* Output : Status of HPCLICK see LSM303AGR_ACC_HPCLICK_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_hpf_click_en(void *handle, LSM303AGR_ACC_HPCLICK_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG2, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_HPCLICK_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_Data_Filter +* Description : Write FDS +* Input : LSM303AGR_ACC_FDS_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_Data_Filter(void *handle, LSM303AGR_ACC_FDS_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG2, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_FDS_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_CTRL_REG2, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_Data_Filter +* Description : Read FDS +* Input : Pointer to LSM303AGR_ACC_FDS_t +* Output : Status of FDS see LSM303AGR_ACC_FDS_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_Data_Filter(void *handle, LSM303AGR_ACC_FDS_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG2, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_FDS_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_hpf_cutoff_freq +* Description : Write HPCF +* Input : LSM303AGR_ACC_HPCF_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_hpf_cutoff_freq(void *handle, LSM303AGR_ACC_HPCF_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG2, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_HPCF_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_CTRL_REG2, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_hpf_cutoff_freq +* Description : Read HPCF +* Input : Pointer to LSM303AGR_ACC_HPCF_t +* Output : Status of HPCF see LSM303AGR_ACC_HPCF_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_hpf_cutoff_freq(void *handle, LSM303AGR_ACC_HPCF_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG2, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_HPCF_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_hpf_mode +* Description : Write HPM +* Input : LSM303AGR_ACC_HPM_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_hpf_mode(void *handle, LSM303AGR_ACC_HPM_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG2, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_HPM_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_CTRL_REG2, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_hpf_mode +* Description : Read HPM +* Input : Pointer to LSM303AGR_ACC_HPM_t +* Output : Status of HPM see LSM303AGR_ACC_HPM_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_hpf_mode(void *handle, LSM303AGR_ACC_HPM_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG2, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_HPM_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_FIFO_Overrun_on_INT1 +* Description : Write I1_OVERRUN +* Input : LSM303AGR_ACC_I1_OVERRUN_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_FIFO_Overrun_on_INT1(void *handle, LSM303AGR_ACC_I1_OVERRUN_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG3, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_I1_OVERRUN_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_CTRL_REG3, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_FIFO_Overrun_on_INT1 +* Description : Read I1_OVERRUN +* Input : Pointer to LSM303AGR_ACC_I1_OVERRUN_t +* Output : Status of I1_OVERRUN see LSM303AGR_ACC_I1_OVERRUN_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_FIFO_Overrun_on_INT1(void *handle, LSM303AGR_ACC_I1_OVERRUN_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG3, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_I1_OVERRUN_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_FIFO_Watermark_on_INT1 +* Description : Write I1_WTM +* Input : LSM303AGR_ACC_I1_WTM_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_FIFO_Watermark_on_INT1(void *handle, LSM303AGR_ACC_I1_WTM_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG3, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_I1_WTM_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_CTRL_REG3, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_FIFO_Watermark_on_INT1 +* Description : Read I1_WTM +* Input : Pointer to LSM303AGR_ACC_I1_WTM_t +* Output : Status of I1_WTM see LSM303AGR_ACC_I1_WTM_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_FIFO_Watermark_on_INT1(void *handle, LSM303AGR_ACC_I1_WTM_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG3, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_I1_WTM_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_FIFO_DRDY2_on_INT1 +* Description : Write I1_DRDY2 +* Input : LSM303AGR_ACC_I1_DRDY2_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_FIFO_DRDY2_on_INT1(void *handle, LSM303AGR_ACC_I1_DRDY2_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG3, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_I1_DRDY2_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_CTRL_REG3, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_FIFO_DRDY2_on_INT1 +* Description : Read I1_DRDY2 +* Input : Pointer to LSM303AGR_ACC_I1_DRDY2_t +* Output : Status of I1_DRDY2 see LSM303AGR_ACC_I1_DRDY2_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_FIFO_DRDY2_on_INT1(void *handle, LSM303AGR_ACC_I1_DRDY2_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG3, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_I1_DRDY2_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_FIFO_DRDY1_on_INT1 +* Description : Write I1_DRDY1 +* Input : LSM303AGR_ACC_I1_DRDY1_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_FIFO_DRDY1_on_INT1(void *handle, LSM303AGR_ACC_I1_DRDY1_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG3, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_I1_DRDY1_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_CTRL_REG3, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_FIFO_DRDY1_on_INT1 +* Description : Read I1_DRDY1 +* Input : Pointer to LSM303AGR_ACC_I1_DRDY1_t +* Output : Status of I1_DRDY1 see LSM303AGR_ACC_I1_DRDY1_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_FIFO_DRDY1_on_INT1(void *handle, LSM303AGR_ACC_I1_DRDY1_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG3, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_I1_DRDY1_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_FIFO_AOL2_on_INT1 +* Description : Write I1_AOI2 +* Input : LSM303AGR_ACC_I1_AOI2_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_FIFO_AOL2_on_INT1(void *handle, LSM303AGR_ACC_I1_AOI2_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG3, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_I1_AOI2_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_CTRL_REG3, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_FIFO_AOL2_on_INT1 +* Description : Read I1_AOI2 +* Input : Pointer to LSM303AGR_ACC_I1_AOI2_t +* Output : Status of I1_AOI2 see LSM303AGR_ACC_I1_AOI2_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_FIFO_AOL2_on_INT1(void *handle, LSM303AGR_ACC_I1_AOI2_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG3, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_I1_AOI2_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_FIFO_AOL1_on_INT1 +* Description : Write I1_AOI1 +* Input : LSM303AGR_ACC_I1_AOI1_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_FIFO_AOL1_on_INT1(void *handle, LSM303AGR_ACC_I1_AOI1_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG3, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_I1_AOI1_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_CTRL_REG3, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_FIFO_AOL1_on_INT1 +* Description : Read I1_AOI1 +* Input : Pointer to LSM303AGR_ACC_I1_AOI1_t +* Output : Status of I1_AOI1 see LSM303AGR_ACC_I1_AOI1_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_FIFO_AOL1_on_INT1(void *handle, LSM303AGR_ACC_I1_AOI1_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG3, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_I1_AOI1_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_FIFO_Click_on_INT1 +* Description : Write I1_CLICK +* Input : LSM303AGR_ACC_I1_CLICK_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_FIFO_Click_on_INT1(void *handle, LSM303AGR_ACC_I1_CLICK_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG3, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_I1_CLICK_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_CTRL_REG3, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_FIFO_Click_on_INT1 +* Description : Read I1_CLICK +* Input : Pointer to LSM303AGR_ACC_I1_CLICK_t +* Output : Status of I1_CLICK see LSM303AGR_ACC_I1_CLICK_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_FIFO_Click_on_INT1(void *handle, LSM303AGR_ACC_I1_CLICK_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG3, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_I1_CLICK_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_SPI_mode +* Description : Write SIM +* Input : LSM303AGR_ACC_SIM_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_SPI_mode(void *handle, LSM303AGR_ACC_SIM_t newValue) +{ + u8_t value=0; + +// if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG4, &value) ) +// return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_SIM_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_CTRL_REG4, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_SPI_mode +* Description : Read SIM +* Input : Pointer to LSM303AGR_ACC_SIM_t +* Output : Status of SIM see LSM303AGR_ACC_SIM_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_SPI_mode(void *handle, LSM303AGR_ACC_SIM_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG4, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_SIM_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_SelfTest +* Description : Write ST +* Input : LSM303AGR_ACC_ST_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_SelfTest(void *handle, LSM303AGR_ACC_ST_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG4, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_ST_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_CTRL_REG4, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_SelfTest +* Description : Read ST +* Input : Pointer to LSM303AGR_ACC_ST_t +* Output : Status of ST see LSM303AGR_ACC_ST_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_SelfTest(void *handle, LSM303AGR_ACC_ST_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG4, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_ST_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_HiRes +* Description : Write HR +* Input : LSM303AGR_ACC_HR_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_HiRes(void *handle, LSM303AGR_ACC_HR_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG4, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_HR_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_CTRL_REG4, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_HiRes +* Description : Read HR +* Input : Pointer to LSM303AGR_ACC_HR_t +* Output : Status of HR see LSM303AGR_ACC_HR_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_HiRes(void *handle, LSM303AGR_ACC_HR_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG4, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_HR_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_FullScale +* Description : Write FS +* Input : LSM303AGR_ACC_FS_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_FullScale(void *handle, LSM303AGR_ACC_FS_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG4, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_FS_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_CTRL_REG4, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_FullScale +* Description : Read FS +* Input : Pointer to LSM303AGR_ACC_FS_t +* Output : Status of FS see LSM303AGR_ACC_FS_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_FullScale(void *handle, LSM303AGR_ACC_FS_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG4, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_FS_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_LittleBigEndian +* Description : Write BLE +* Input : LSM303AGR_ACC_BLE_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_LittleBigEndian(void *handle, LSM303AGR_ACC_BLE_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG4, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_BLE_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_CTRL_REG4, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_LittleBigEndian +* Description : Read BLE +* Input : Pointer to LSM303AGR_ACC_BLE_t +* Output : Status of BLE see LSM303AGR_ACC_BLE_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_LittleBigEndian(void *handle, LSM303AGR_ACC_BLE_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG4, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_BLE_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_BlockDataUpdate +* Description : Write BDU +* Input : LSM303AGR_ACC_BDU_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_BlockDataUpdate(void *handle, LSM303AGR_ACC_BDU_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG4, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_BDU_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_CTRL_REG4, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_BlockDataUpdate +* Description : Read BDU +* Input : Pointer to LSM303AGR_ACC_BDU_t +* Output : Status of BDU see LSM303AGR_ACC_BDU_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_BlockDataUpdate(void *handle, LSM303AGR_ACC_BDU_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG4, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_BDU_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_4D_on_INT2 +* Description : Write D4D_INT2 +* Input : LSM303AGR_ACC_D4D_INT2_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_4D_on_INT2(void *handle, LSM303AGR_ACC_D4D_INT2_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG5, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_D4D_INT2_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_CTRL_REG5, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_4D_on_INT2 +* Description : Read D4D_INT2 +* Input : Pointer to LSM303AGR_ACC_D4D_INT2_t +* Output : Status of D4D_INT2 see LSM303AGR_ACC_D4D_INT2_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_4D_on_INT2(void *handle, LSM303AGR_ACC_D4D_INT2_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG5, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_D4D_INT2_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_LatchInterrupt_on_INT2 +* Description : Write LIR_INT2 +* Input : LSM303AGR_ACC_LIR_INT2_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_LatchInterrupt_on_INT2(void *handle, LSM303AGR_ACC_LIR_INT2_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG5, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_LIR_INT2_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_CTRL_REG5, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_LatchInterrupt_on_INT2 +* Description : Read LIR_INT2 +* Input : Pointer to LSM303AGR_ACC_LIR_INT2_t +* Output : Status of LIR_INT2 see LSM303AGR_ACC_LIR_INT2_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_LatchInterrupt_on_INT2(void *handle, LSM303AGR_ACC_LIR_INT2_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG5, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_LIR_INT2_MASK; //mask + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_4D_on_INT1 +* Description : Write D4D_INT1 +* Input : LSM303AGR_ACC_D4D_INT1_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_4D_on_INT1(void *handle, LSM303AGR_ACC_D4D_INT1_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG5, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_D4D_INT1_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_CTRL_REG5, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_4D_on_INT1 +* Description : Read D4D_INT1 +* Input : Pointer to LSM303AGR_ACC_D4D_INT1_t +* Output : Status of D4D_INT1 see LSM303AGR_ACC_D4D_INT1_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_4D_on_INT1(void *handle, LSM303AGR_ACC_D4D_INT1_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG5, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_D4D_INT1_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_LatchInterrupt_on_INT1 +* Description : Write LIR_INT1 +* Input : LSM303AGR_ACC_LIR_INT1_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_LatchInterrupt_on_INT1(void *handle, LSM303AGR_ACC_LIR_INT1_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG5, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_LIR_INT1_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_CTRL_REG5, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_LatchInterrupt_on_INT1 +* Description : Read LIR_INT1 +* Input : Pointer to LSM303AGR_ACC_LIR_INT1_t +* Output : Status of LIR_INT1 see LSM303AGR_ACC_LIR_INT1_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_LatchInterrupt_on_INT1(void *handle, LSM303AGR_ACC_LIR_INT1_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG5, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_LIR_INT1_MASK; //mask + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_FIFO_EN +* Description : Write FIFO_EN +* Input : LSM303AGR_ACC_FIFO_EN_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_FIFO_EN(void *handle, LSM303AGR_ACC_FIFO_EN_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG5, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_FIFO_EN_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_CTRL_REG5, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_FIFO_EN +* Description : Read FIFO_EN +* Input : Pointer to LSM303AGR_ACC_FIFO_EN_t +* Output : Status of FIFO_EN see LSM303AGR_ACC_FIFO_EN_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_FIFO_EN(void *handle, LSM303AGR_ACC_FIFO_EN_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG5, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_FIFO_EN_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_RebootMemory +* Description : Write BOOT +* Input : LSM303AGR_ACC_BOOT_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_RebootMemory(void *handle, LSM303AGR_ACC_BOOT_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG5, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_BOOT_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_CTRL_REG5, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_RebootMemory +* Description : Read BOOT +* Input : Pointer to LSM303AGR_ACC_BOOT_t +* Output : Status of BOOT see LSM303AGR_ACC_BOOT_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_RebootMemory(void *handle, LSM303AGR_ACC_BOOT_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG5, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_BOOT_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_IntActive +* Description : Write H_LACTIVE +* Input : LSM303AGR_ACC_H_LACTIVE_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_IntActive(void *handle, LSM303AGR_ACC_H_LACTIVE_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG6, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_H_LACTIVE_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_CTRL_REG6, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_IntActive +* Description : Read H_LACTIVE +* Input : Pointer to LSM303AGR_ACC_H_LACTIVE_t +* Output : Status of H_LACTIVE see LSM303AGR_ACC_H_LACTIVE_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_IntActive(void *handle, LSM303AGR_ACC_H_LACTIVE_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG6, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_H_LACTIVE_MASK; //mask + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_P2_ACT +* Description : Write P2_ACT +* Input : LSM303AGR_ACC_P2_ACT_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_P2_ACT(void *handle, LSM303AGR_ACC_P2_ACT_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG6, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_P2_ACT_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_CTRL_REG6, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_P2_ACT +* Description : Read P2_ACT +* Input : Pointer to LSM303AGR_ACC_P2_ACT_t +* Output : Status of P2_ACT see LSM303AGR_ACC_P2_ACT_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_P2_ACT(void *handle, LSM303AGR_ACC_P2_ACT_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG6, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_P2_ACT_MASK; //mask + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_Boot_on_INT2 +* Description : Write BOOT_I1 +* Input : LSM303AGR_ACC_BOOT_I1_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_Boot_on_INT2(void *handle, LSM303AGR_ACC_BOOT_I1_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG6, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_BOOT_I1_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_CTRL_REG6, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_Boot_on_INT2 +* Description : Read BOOT_I1 +* Input : Pointer to LSM303AGR_ACC_BOOT_I1_t +* Output : Status of BOOT_I1 see LSM303AGR_ACC_BOOT_I1_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_Boot_on_INT2(void *handle, LSM303AGR_ACC_BOOT_I1_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG6, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_BOOT_I1_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_I2_on_INT2 +* Description : Write I2_INT2 +* Input : LSM303AGR_ACC_I2_INT2_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_I2_on_INT2(void *handle, LSM303AGR_ACC_I2_INT2_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG6, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_I2_INT2_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_CTRL_REG6, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_I2_on_INT2 +* Description : Read I2_INT2 +* Input : Pointer to LSM303AGR_ACC_I2_INT2_t +* Output : Status of I2_INT2 see LSM303AGR_ACC_I2_INT2_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_I2_on_INT2(void *handle, LSM303AGR_ACC_I2_INT2_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG6, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_I2_INT2_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_I2_on_INT1 +* Description : Write I2_INT1 +* Input : LSM303AGR_ACC_I2_INT1_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_I2_on_INT1(void *handle, LSM303AGR_ACC_I2_INT1_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG6, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_I2_INT1_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_CTRL_REG6, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_I2_on_INT1 +* Description : Read I2_INT1 +* Input : Pointer to LSM303AGR_ACC_I2_INT1_t +* Output : Status of I2_INT1 see LSM303AGR_ACC_I2_INT1_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_I2_on_INT1(void *handle, LSM303AGR_ACC_I2_INT1_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG6, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_I2_INT1_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_Click_on_INT2 +* Description : Write I2_CLICKEN +* Input : LSM303AGR_ACC_I2_CLICKEN_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_Click_on_INT2(void *handle, LSM303AGR_ACC_I2_CLICKEN_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG6, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_I2_CLICKEN_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_CTRL_REG6, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_Click_on_INT2 +* Description : Read I2_CLICKEN +* Input : Pointer to LSM303AGR_ACC_I2_CLICKEN_t +* Output : Status of I2_CLICKEN see LSM303AGR_ACC_I2_CLICKEN_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_Click_on_INT2(void *handle, LSM303AGR_ACC_I2_CLICKEN_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CTRL_REG6, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_I2_CLICKEN_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_ReferenceVal +* Description : Write REF +* Input : u8_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_ReferenceVal(void *handle, u8_t newValue) +{ + u8_t value; + + newValue = newValue << LSM303AGR_ACC_REF_POSITION; //mask + newValue &= LSM303AGR_ACC_REF_MASK; //coerce + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_REFERENCE, &value) ) + return MEMS_ERROR; + + value &= (u8_t)~LSM303AGR_ACC_REF_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_REFERENCE, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_ReferenceVal +* Description : Read REF +* Input : Pointer to u8_t +* Output : Status of REF +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_ReferenceVal(void *handle, u8_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_REFERENCE, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_REF_MASK; //coerce + *value = *value >> LSM303AGR_ACC_REF_POSITION; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_XDataAvail +* Description : Read XDA +* Input : Pointer to LSM303AGR_ACC_XDA_t +* Output : Status of XDA see LSM303AGR_ACC_XDA_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_XDataAvail(void *handle, LSM303AGR_ACC_XDA_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_STATUS_REG2, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_XDA_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_YDataAvail +* Description : Read YDA +* Input : Pointer to LSM303AGR_ACC_YDA_t +* Output : Status of YDA see LSM303AGR_ACC_YDA_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_YDataAvail(void *handle, LSM303AGR_ACC_YDA_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_STATUS_REG2, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_YDA_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_ZDataAvail +* Description : Read ZDA +* Input : Pointer to LSM303AGR_ACC_ZDA_t +* Output : Status of ZDA see LSM303AGR_ACC_ZDA_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_ZDataAvail(void *handle, LSM303AGR_ACC_ZDA_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_STATUS_REG2, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_ZDA_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_XYZDataAvail +* Description : Read ZYXDA +* Input : Pointer to LSM303AGR_ACC_ZYXDA_t +* Output : Status of ZYXDA see LSM303AGR_ACC_ZYXDA_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_XYZDataAvail(void *handle, LSM303AGR_ACC_ZYXDA_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_STATUS_REG2, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_ZYXDA_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_XDataOverrun +* Description : Read XOR +* Input : Pointer to LSM303AGR_ACC_XOR_t +* Output : Status of XOR see LSM303AGR_ACC_XOR_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_XDataOverrun(void *handle, LSM303AGR_ACC_XOR_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_STATUS_REG2, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_XOR_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_YDataOverrun +* Description : Read YOR +* Input : Pointer to LSM303AGR_ACC_YOR_t +* Output : Status of YOR see LSM303AGR_ACC_YOR_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_YDataOverrun(void *handle, LSM303AGR_ACC_YOR_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_STATUS_REG2, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_YOR_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_ZDataOverrun +* Description : Read ZOR +* Input : Pointer to LSM303AGR_ACC_ZOR_t +* Output : Status of ZOR see LSM303AGR_ACC_ZOR_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_ZDataOverrun(void *handle, LSM303AGR_ACC_ZOR_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_STATUS_REG2, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_ZOR_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_XYZDataOverrun +* Description : Read ZYXOR +* Input : Pointer to LSM303AGR_ACC_ZYXOR_t +* Output : Status of ZYXOR see LSM303AGR_ACC_ZYXOR_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_XYZDataOverrun(void *handle, LSM303AGR_ACC_ZYXOR_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_STATUS_REG2, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_ZYXOR_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_FifoThreshold +* Description : Write FTH +* Input : u8_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_FifoThreshold(void *handle, u8_t newValue) +{ + u8_t value; + + newValue = newValue << LSM303AGR_ACC_FTH_POSITION; //mask + newValue &= LSM303AGR_ACC_FTH_MASK; //coerce + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_FIFO_CTRL_REG, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_FTH_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_FIFO_CTRL_REG, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_FifoThreshold +* Description : Read FTH +* Input : Pointer to u8_t +* Output : Status of FTH +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_FifoThreshold(void *handle, u8_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_FIFO_CTRL_REG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_FTH_MASK; //coerce + *value = *value >> LSM303AGR_ACC_FTH_POSITION; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_TriggerSel +* Description : Write TR +* Input : LSM303AGR_ACC_TR_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_TriggerSel(void *handle, LSM303AGR_ACC_TR_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_FIFO_CTRL_REG, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_TR_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_FIFO_CTRL_REG, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_TriggerSel +* Description : Read TR +* Input : Pointer to LSM303AGR_ACC_TR_t +* Output : Status of TR see LSM303AGR_ACC_TR_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_TriggerSel(void *handle, LSM303AGR_ACC_TR_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_FIFO_CTRL_REG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_TR_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_FifoMode +* Description : Write FM +* Input : LSM303AGR_ACC_FM_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_FifoMode(void *handle, LSM303AGR_ACC_FM_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_FIFO_CTRL_REG, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_FM_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_FIFO_CTRL_REG, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_FifoMode +* Description : Read FM +* Input : Pointer to LSM303AGR_ACC_FM_t +* Output : Status of FM see LSM303AGR_ACC_FM_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_FifoMode(void *handle, LSM303AGR_ACC_FM_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_FIFO_CTRL_REG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_FM_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_FifoSamplesAvail +* Description : Read FSS +* Input : Pointer to u8_t +* Output : Status of FSS +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_FifoSamplesAvail(void *handle, u8_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_FIFO_SRC_REG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_FSS_MASK; //coerce + *value = *value >> LSM303AGR_ACC_FSS_POSITION; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_FifoEmpty +* Description : Read EMPTY +* Input : Pointer to LSM303AGR_ACC_EMPTY_t +* Output : Status of EMPTY see LSM303AGR_ACC_EMPTY_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_FifoEmpty(void *handle, LSM303AGR_ACC_EMPTY_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_FIFO_SRC_REG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_EMPTY_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_FifoOverrun +* Description : Read OVRN_FIFO +* Input : Pointer to LSM303AGR_ACC_OVRN_FIFO_t +* Output : Status of OVRN_FIFO see LSM303AGR_ACC_OVRN_FIFO_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_FifoOverrun(void *handle, LSM303AGR_ACC_OVRN_FIFO_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_FIFO_SRC_REG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_OVRN_FIFO_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_WatermarkLevel +* Description : Read WTM +* Input : Pointer to LSM303AGR_ACC_WTM_t +* Output : Status of WTM see LSM303AGR_ACC_WTM_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_WatermarkLevel(void *handle, LSM303AGR_ACC_WTM_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_FIFO_SRC_REG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_WTM_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_Int1EnXLo +* Description : Write XLIE +* Input : LSM303AGR_ACC_XLIE_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_Int1EnXLo(void *handle, LSM303AGR_ACC_XLIE_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT1_CFG, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_XLIE_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_INT1_CFG, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_Int1EnXLo +* Description : Read XLIE +* Input : Pointer to LSM303AGR_ACC_XLIE_t +* Output : Status of XLIE see LSM303AGR_ACC_XLIE_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_Int1EnXLo(void *handle, LSM303AGR_ACC_XLIE_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT1_CFG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_XLIE_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_Int1EnXHi +* Description : Write XHIE +* Input : LSM303AGR_ACC_XHIE_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_Int1EnXHi(void *handle, LSM303AGR_ACC_XHIE_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT1_CFG, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_XHIE_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_INT1_CFG, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_Int1EnXHi +* Description : Read XHIE +* Input : Pointer to LSM303AGR_ACC_XHIE_t +* Output : Status of XHIE see LSM303AGR_ACC_XHIE_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_Int1EnXHi(void *handle, LSM303AGR_ACC_XHIE_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT1_CFG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_XHIE_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_Int1EnYLo +* Description : Write YLIE +* Input : LSM303AGR_ACC_YLIE_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_Int1EnYLo(void *handle, LSM303AGR_ACC_YLIE_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT1_CFG, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_YLIE_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_INT1_CFG, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_Int1EnYLo +* Description : Read YLIE +* Input : Pointer to LSM303AGR_ACC_YLIE_t +* Output : Status of YLIE see LSM303AGR_ACC_YLIE_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_Int1EnYLo(void *handle, LSM303AGR_ACC_YLIE_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT1_CFG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_YLIE_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_Int1EnYHi +* Description : Write YHIE +* Input : LSM303AGR_ACC_YHIE_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_Int1EnYHi(void *handle, LSM303AGR_ACC_YHIE_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT1_CFG, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_YHIE_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_INT1_CFG, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_Int1EnYHi +* Description : Read YHIE +* Input : Pointer to LSM303AGR_ACC_YHIE_t +* Output : Status of YHIE see LSM303AGR_ACC_YHIE_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_Int1EnYHi(void *handle, LSM303AGR_ACC_YHIE_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT1_CFG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_YHIE_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_Int1EnZLo +* Description : Write ZLIE +* Input : LSM303AGR_ACC_ZLIE_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_Int1EnZLo(void *handle, LSM303AGR_ACC_ZLIE_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT1_CFG, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_ZLIE_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_INT1_CFG, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_Int1EnZLo +* Description : Read ZLIE +* Input : Pointer to LSM303AGR_ACC_ZLIE_t +* Output : Status of ZLIE see LSM303AGR_ACC_ZLIE_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_Int1EnZLo(void *handle, LSM303AGR_ACC_ZLIE_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT1_CFG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_ZLIE_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_Int1EnZHi +* Description : Write ZHIE +* Input : LSM303AGR_ACC_ZHIE_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_Int1EnZHi(void *handle, LSM303AGR_ACC_ZHIE_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT1_CFG, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_ZHIE_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_INT1_CFG, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_Int1EnZHi +* Description : Read ZHIE +* Input : Pointer to LSM303AGR_ACC_ZHIE_t +* Output : Status of ZHIE see LSM303AGR_ACC_ZHIE_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_Int1EnZHi(void *handle, LSM303AGR_ACC_ZHIE_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT1_CFG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_ZHIE_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_Int1_6D +* Description : Write 6D +* Input : LSM303AGR_ACC_6D_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_Int1_6D(void *handle, LSM303AGR_ACC_6D_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT1_CFG, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_6D_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_INT1_CFG, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_Int1_6D +* Description : Read 6D +* Input : Pointer to LSM303AGR_ACC_6D_t +* Output : Status of 6D see LSM303AGR_ACC_6D_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_Int1_6D(void *handle, LSM303AGR_ACC_6D_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT1_CFG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_6D_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_Int1_AOI +* Description : Write AOI +* Input : LSM303AGR_ACC_AOI_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_Int1_AOI(void *handle, LSM303AGR_ACC_AOI_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT1_CFG, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_AOI_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_INT1_CFG, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_Int1_AOI +* Description : Read AOI +* Input : Pointer to LSM303AGR_ACC_AOI_t +* Output : Status of AOI see LSM303AGR_ACC_AOI_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_Int1_AOI(void *handle, LSM303AGR_ACC_AOI_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT1_CFG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_AOI_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_Int2EnXLo +* Description : Write XLIE +* Input : LSM303AGR_ACC_XLIE_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_Int2EnXLo(void *handle, LSM303AGR_ACC_XLIE_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT2_CFG, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_XLIE_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_INT2_CFG, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_Int2EnXLo +* Description : Read XLIE +* Input : Pointer to LSM303AGR_ACC_XLIE_t +* Output : Status of XLIE see LSM303AGR_ACC_XLIE_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_Int2EnXLo(void *handle, LSM303AGR_ACC_XLIE_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT2_CFG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_XLIE_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_Int2EnXHi +* Description : Write XHIE +* Input : LSM303AGR_ACC_XHIE_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_Int2EnXHi(void *handle, LSM303AGR_ACC_XHIE_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT2_CFG, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_XHIE_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_INT2_CFG, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_Int2EnXHi +* Description : Read XHIE +* Input : Pointer to LSM303AGR_ACC_XHIE_t +* Output : Status of XHIE see LSM303AGR_ACC_XHIE_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_Int2EnXHi(void *handle, LSM303AGR_ACC_XHIE_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT2_CFG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_XHIE_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_Int2EnYLo +* Description : Write YLIE +* Input : LSM303AGR_ACC_YLIE_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_Int2EnYLo(void *handle, LSM303AGR_ACC_YLIE_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT2_CFG, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_YLIE_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_INT2_CFG, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_Int2EnYLo +* Description : Read YLIE +* Input : Pointer to LSM303AGR_ACC_YLIE_t +* Output : Status of YLIE see LSM303AGR_ACC_YLIE_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_Int2EnYLo(void *handle, LSM303AGR_ACC_YLIE_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT2_CFG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_YLIE_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_Int2EnYHi +* Description : Write YHIE +* Input : LSM303AGR_ACC_YHIE_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_Int2EnYHi(void *handle, LSM303AGR_ACC_YHIE_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT2_CFG, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_YHIE_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_INT2_CFG, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_Int2EnYHi +* Description : Read YHIE +* Input : Pointer to LSM303AGR_ACC_YHIE_t +* Output : Status of YHIE see LSM303AGR_ACC_YHIE_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_Int2EnYHi(void *handle, LSM303AGR_ACC_YHIE_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT2_CFG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_YHIE_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_Int2EnZLo +* Description : Write ZLIE +* Input : LSM303AGR_ACC_ZLIE_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_Int2EnZLo(void *handle, LSM303AGR_ACC_ZLIE_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT2_CFG, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_ZLIE_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_INT2_CFG, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_Int2EnZLo +* Description : Read ZLIE +* Input : Pointer to LSM303AGR_ACC_ZLIE_t +* Output : Status of ZLIE see LSM303AGR_ACC_ZLIE_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_Int2EnZLo(void *handle, LSM303AGR_ACC_ZLIE_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT2_CFG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_ZLIE_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_Int2EnZHi +* Description : Write ZHIE +* Input : LSM303AGR_ACC_ZHIE_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_Int2EnZHi(void *handle, LSM303AGR_ACC_ZHIE_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT2_CFG, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_ZHIE_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_INT2_CFG, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_Int2EnZHi +* Description : Read ZHIE +* Input : Pointer to LSM303AGR_ACC_ZHIE_t +* Output : Status of ZHIE see LSM303AGR_ACC_ZHIE_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_Int2EnZHi(void *handle, LSM303AGR_ACC_ZHIE_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT2_CFG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_ZHIE_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_Int2_6D +* Description : Write 6D +* Input : LSM303AGR_ACC_6D_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_Int2_6D(void *handle, LSM303AGR_ACC_6D_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT2_CFG, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_6D_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_INT2_CFG, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_Int2_6D +* Description : Read 6D +* Input : Pointer to LSM303AGR_ACC_6D_t +* Output : Status of 6D see LSM303AGR_ACC_6D_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_Int2_6D(void *handle, LSM303AGR_ACC_6D_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT2_CFG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_6D_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_Int2_AOI +* Description : Write AOI +* Input : LSM303AGR_ACC_AOI_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_Int2_AOI(void *handle, LSM303AGR_ACC_AOI_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT2_CFG, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_AOI_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_INT2_CFG, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_Int2_AOI +* Description : Read AOI +* Input : Pointer to LSM303AGR_ACC_AOI_t +* Output : Status of AOI see LSM303AGR_ACC_AOI_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_Int2_AOI(void *handle, LSM303AGR_ACC_AOI_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT2_CFG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_AOI_MASK; //mask + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_Int1_Xlo +* Description : Read XL +* Input : Pointer to LSM303AGR_ACC_XL_t +* Output : Status of XL see LSM303AGR_ACC_XL_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_Int1_Xlo(void *handle, LSM303AGR_ACC_XL_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT1_SOURCE, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_XL_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_Int1_XHi +* Description : Read XH +* Input : Pointer to LSM303AGR_ACC_XH_t +* Output : Status of XH see LSM303AGR_ACC_XH_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_Int1_XHi(void *handle, LSM303AGR_ACC_XH_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT1_SOURCE, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_XH_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_Int1_YLo +* Description : Read YL +* Input : Pointer to LSM303AGR_ACC_YL_t +* Output : Status of YL see LSM303AGR_ACC_YL_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_Int1_YLo(void *handle, LSM303AGR_ACC_YL_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT1_SOURCE, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_YL_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_Int1_YHi +* Description : Read YH +* Input : Pointer to LSM303AGR_ACC_YH_t +* Output : Status of YH see LSM303AGR_ACC_YH_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_Int1_YHi(void *handle, LSM303AGR_ACC_YH_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT1_SOURCE, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_YH_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_Int1_Zlo +* Description : Read ZL +* Input : Pointer to LSM303AGR_ACC_ZL_t +* Output : Status of ZL see LSM303AGR_ACC_ZL_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_Int1_Zlo(void *handle, LSM303AGR_ACC_ZL_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT1_SOURCE, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_ZL_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_Int1_ZHi +* Description : Read ZH +* Input : Pointer to LSM303AGR_ACC_ZH_t +* Output : Status of ZH see LSM303AGR_ACC_ZH_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_Int1_ZHi(void *handle, LSM303AGR_ACC_ZH_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT1_SOURCE, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_ZH_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_Int1_IA +* Description : Read IA +* Input : Pointer to LSM303AGR_ACC_IA_t +* Output : Status of IA see LSM303AGR_ACC_IA_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_Int1_IA(void *handle, LSM303AGR_ACC_IA_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT1_SOURCE, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_IA_MASK; //mask + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_Int2_Xlo +* Description : Read XL +* Input : Pointer to LSM303AGR_ACC_XL_t +* Output : Status of XL see LSM303AGR_ACC_XL_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_Int2_Xlo(void *handle, LSM303AGR_ACC_XL_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT2_SOURCE, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_XL_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_Int2_XHi +* Description : Read XH +* Input : Pointer to LSM303AGR_ACC_XH_t +* Output : Status of XH see LSM303AGR_ACC_XH_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_Int2_XHi(void *handle, LSM303AGR_ACC_XH_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT2_SOURCE, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_XH_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_Int2_YLo +* Description : Read YL +* Input : Pointer to LSM303AGR_ACC_YL_t +* Output : Status of YL see LSM303AGR_ACC_YL_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_Int2_YLo(void *handle, LSM303AGR_ACC_YL_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT2_SOURCE, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_YL_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_Int2_YHi +* Description : Read YH +* Input : Pointer to LSM303AGR_ACC_YH_t +* Output : Status of YH see LSM303AGR_ACC_YH_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_Int2_YHi(void *handle, LSM303AGR_ACC_YH_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT2_SOURCE, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_YH_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_Int2_Zlo +* Description : Read ZL +* Input : Pointer to LSM303AGR_ACC_ZL_t +* Output : Status of ZL see LSM303AGR_ACC_ZL_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_Int2_Zlo(void *handle, LSM303AGR_ACC_ZL_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT2_SOURCE, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_ZL_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_Int2_ZHi +* Description : Read ZH +* Input : Pointer to LSM303AGR_ACC_ZH_t +* Output : Status of ZH see LSM303AGR_ACC_ZH_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_Int2_ZHi(void *handle, LSM303AGR_ACC_ZH_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT2_SOURCE, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_ZH_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_Int2_IA +* Description : Read IA +* Input : Pointer to LSM303AGR_ACC_IA_t +* Output : Status of IA see LSM303AGR_ACC_IA_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_Int2_IA(void *handle, LSM303AGR_ACC_IA_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT2_SOURCE, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_IA_MASK; //mask + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_Int1_Threshold +* Description : Write THS +* Input : u8_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_Int1_Threshold(void *handle, u8_t newValue) +{ + u8_t value; + + newValue = newValue << LSM303AGR_ACC_THS_POSITION; //mask + newValue &= LSM303AGR_ACC_THS_MASK; //coerce + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT1_THS, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_THS_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_INT1_THS, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_Int1_Threshold +* Description : Read THS +* Input : Pointer to u8_t +* Output : Status of THS +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_Int1_Threshold(void *handle, u8_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT1_THS, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_THS_MASK; //coerce + *value = *value >> LSM303AGR_ACC_THS_POSITION; //mask + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_Int2_Threshold +* Description : Write THS +* Input : u8_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_Int2_Threshold(void *handle, u8_t newValue) +{ + u8_t value; + + newValue = newValue << LSM303AGR_ACC_THS_POSITION; //mask + newValue &= LSM303AGR_ACC_THS_MASK; //coerce + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT2_THS, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_THS_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_INT2_THS, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_Int2_Threshold +* Description : Read THS +* Input : Pointer to u8_t +* Output : Status of THS +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_Int2_Threshold(void *handle, u8_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT2_THS, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_THS_MASK; //coerce + *value = *value >> LSM303AGR_ACC_THS_POSITION; //mask + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_Int1_Duration +* Description : Write D +* Input : u8_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_Int1_Duration(void *handle, u8_t newValue) +{ + u8_t value; + + newValue = newValue << LSM303AGR_ACC_D_POSITION; //mask + newValue &= LSM303AGR_ACC_D_MASK; //coerce + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT1_DURATION, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_D_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_INT1_DURATION, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_Int1_Duration +* Description : Read D +* Input : Pointer to u8_t +* Output : Status of D +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_Int1_Duration(void *handle, u8_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT1_DURATION, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_D_MASK; //coerce + *value = *value >> LSM303AGR_ACC_D_POSITION; //mask + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_Int2_Duration +* Description : Write D +* Input : u8_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_Int2_Duration(void *handle, u8_t newValue) +{ + u8_t value; + + newValue = newValue << LSM303AGR_ACC_D_POSITION; //mask + newValue &= LSM303AGR_ACC_D_MASK; //coerce + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT2_DURATION, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_D_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_INT2_DURATION, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_Int2_Duration +* Description : Read D +* Input : Pointer to u8_t +* Output : Status of D +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_Int2_Duration(void *handle, u8_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_INT2_DURATION, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_D_MASK; //coerce + *value = *value >> LSM303AGR_ACC_D_POSITION; //mask + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_XSingle +* Description : Write XS +* Input : LSM303AGR_ACC_XS_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_XSingle(void *handle, LSM303AGR_ACC_XS_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CLICK_CFG, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_XS_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_CLICK_CFG, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_XSingle +* Description : Read XS +* Input : Pointer to LSM303AGR_ACC_XS_t +* Output : Status of XS see LSM303AGR_ACC_XS_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_XSingle(void *handle, LSM303AGR_ACC_XS_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CLICK_CFG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_XS_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_XDouble +* Description : Write XD +* Input : LSM303AGR_ACC_XD_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_XDouble(void *handle, LSM303AGR_ACC_XD_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CLICK_CFG, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_XD_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_CLICK_CFG, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_XDouble +* Description : Read XD +* Input : Pointer to LSM303AGR_ACC_XD_t +* Output : Status of XD see LSM303AGR_ACC_XD_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_XDouble(void *handle, LSM303AGR_ACC_XD_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CLICK_CFG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_XD_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_YSingle +* Description : Write YS +* Input : LSM303AGR_ACC_YS_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_YSingle(void *handle, LSM303AGR_ACC_YS_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CLICK_CFG, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_YS_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_CLICK_CFG, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_YSingle +* Description : Read YS +* Input : Pointer to LSM303AGR_ACC_YS_t +* Output : Status of YS see LSM303AGR_ACC_YS_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_YSingle(void *handle, LSM303AGR_ACC_YS_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CLICK_CFG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_YS_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_YDouble +* Description : Write YD +* Input : LSM303AGR_ACC_YD_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_YDouble(void *handle, LSM303AGR_ACC_YD_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CLICK_CFG, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_YD_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_CLICK_CFG, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_YDouble +* Description : Read YD +* Input : Pointer to LSM303AGR_ACC_YD_t +* Output : Status of YD see LSM303AGR_ACC_YD_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_YDouble(void *handle, LSM303AGR_ACC_YD_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CLICK_CFG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_YD_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_ZSingle +* Description : Write ZS +* Input : LSM303AGR_ACC_ZS_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_ZSingle(void *handle, LSM303AGR_ACC_ZS_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CLICK_CFG, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_ZS_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_CLICK_CFG, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_ZSingle +* Description : Read ZS +* Input : Pointer to LSM303AGR_ACC_ZS_t +* Output : Status of ZS see LSM303AGR_ACC_ZS_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_ZSingle(void *handle, LSM303AGR_ACC_ZS_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CLICK_CFG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_ZS_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_ZDouble +* Description : Write ZD +* Input : LSM303AGR_ACC_ZD_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_ZDouble(void *handle, LSM303AGR_ACC_ZD_t newValue) +{ + u8_t value; + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CLICK_CFG, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_ZD_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_CLICK_CFG, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_ZDouble +* Description : Read ZD +* Input : Pointer to LSM303AGR_ACC_ZD_t +* Output : Status of ZD see LSM303AGR_ACC_ZD_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_ZDouble(void *handle, LSM303AGR_ACC_ZD_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CLICK_CFG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_ZD_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_ClickX +* Description : Read X +* Input : Pointer to LSM303AGR_ACC_X_t +* Output : Status of X see LSM303AGR_ACC_X_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_ClickX(void *handle, LSM303AGR_ACC_X_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CLICK_SRC, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_X_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_ClickY +* Description : Read Y +* Input : Pointer to LSM303AGR_ACC_Y_t +* Output : Status of Y see LSM303AGR_ACC_Y_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_ClickY(void *handle, LSM303AGR_ACC_Y_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CLICK_SRC, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_Y_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_ClickZ +* Description : Read Z +* Input : Pointer to LSM303AGR_ACC_Z_t +* Output : Status of Z see LSM303AGR_ACC_Z_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_ClickZ(void *handle, LSM303AGR_ACC_Z_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CLICK_SRC, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_Z_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_ClickSign +* Description : Read SIGN +* Input : Pointer to LSM303AGR_ACC_SIGN_t +* Output : Status of SIGN see LSM303AGR_ACC_SIGN_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_ClickSign(void *handle, LSM303AGR_ACC_SIGN_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CLICK_SRC, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_SIGN_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_SingleCLICK +* Description : Read SCLICK +* Input : Pointer to LSM303AGR_ACC_SCLICK_t +* Output : Status of SCLICK see LSM303AGR_ACC_SCLICK_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_SingleCLICK(void *handle, LSM303AGR_ACC_SCLICK_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CLICK_SRC, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_SCLICK_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_DoubleCLICK +* Description : Read DCLICK +* Input : Pointer to LSM303AGR_ACC_DCLICK_t +* Output : Status of DCLICK see LSM303AGR_ACC_DCLICK_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_DoubleCLICK(void *handle, LSM303AGR_ACC_DCLICK_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CLICK_SRC, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_DCLICK_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_IA +* Description : Read IA +* Input : Pointer to LSM303AGR_ACC_IA_t +* Output : Status of IA see LSM303AGR_ACC_IA_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_CLICK_IA(void *handle, LSM303AGR_ACC_CLICK_IA_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CLICK_SRC, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_IA_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_ClickThreshold +* Description : Write THS +* Input : u8_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_ClickThreshold(void *handle, u8_t newValue) +{ + u8_t value; + + newValue = newValue << LSM303AGR_ACC_THS_POSITION; //mask + newValue &= LSM303AGR_ACC_THS_MASK; //coerce + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CLICK_THS, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_THS_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_CLICK_THS, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_ClickThreshold +* Description : Read THS +* Input : Pointer to u8_t +* Output : Status of THS +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_ClickThreshold(void *handle, u8_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_CLICK_THS, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_THS_MASK; //coerce + *value = *value >> LSM303AGR_ACC_THS_POSITION; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_ClickTimeLimit +* Description : Write TLI +* Input : u8_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_ClickTimeLimit(void *handle, u8_t newValue) +{ + u8_t value; + + newValue = newValue << LSM303AGR_ACC_TLI_POSITION; //mask + newValue &= LSM303AGR_ACC_TLI_MASK; //coerce + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_TIME_LIMIT, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_ACC_TLI_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_TIME_LIMIT, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_ClickTimeLimit +* Description : Read TLI +* Input : Pointer to u8_t +* Output : Status of TLI +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_ClickTimeLimit(void *handle, u8_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_TIME_LIMIT, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_TLI_MASK; //coerce + *value = *value >> LSM303AGR_ACC_TLI_POSITION; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_ClickTimeLatency +* Description : Write TLA +* Input : u8_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_ClickTimeLatency(void *handle, u8_t newValue) +{ + u8_t value; + + newValue = newValue << LSM303AGR_ACC_TLA_POSITION; //mask + newValue &= LSM303AGR_ACC_TLA_MASK; //coerce + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_TIME_LATENCY, &value) ) + return MEMS_ERROR; + + value &= (u8_t)~LSM303AGR_ACC_TLA_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_TIME_LATENCY, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_ClickTimeLatency +* Description : Read TLA +* Input : Pointer to u8_t +* Output : Status of TLA +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_ClickTimeLatency(void *handle, u8_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_TIME_LATENCY, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_TLA_MASK; //coerce + *value = *value >> LSM303AGR_ACC_TLA_POSITION; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_ACC_W_ClickTimeWindow +* Description : Write TW +* Input : u8_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_W_ClickTimeWindow(void *handle, u8_t newValue) +{ + u8_t value; + + newValue = newValue << LSM303AGR_ACC_TW_POSITION; //mask + newValue &= LSM303AGR_ACC_TW_MASK; //coerce + + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_TIME_WINDOW, &value) ) + return MEMS_ERROR; + + value &= (u8_t)~LSM303AGR_ACC_TW_MASK; + value |= newValue; + + if( !LSM303AGR_ACC_write_reg(handle, LSM303AGR_ACC_TIME_WINDOW, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_ACC_R_ClickTimeWindow +* Description : Read TW +* Input : Pointer to u8_t +* Output : Status of TW +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_ACC_R_ClickTimeWindow(void *handle, u8_t *value) +{ + if( !LSM303AGR_ACC_read_reg(handle, LSM303AGR_ACC_TIME_WINDOW, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_ACC_TW_MASK; //coerce + *value = *value >> LSM303AGR_ACC_TW_POSITION; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : mems_status_t LSM303AGR_ACC_Get_Voltage_ADC(u8_t *buff) +* Description : Read Voltage_ADC output register +* Input : pointer to [u8_t] +* Output : Voltage_ADC buffer u8_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_Get_Voltage_ADC(void *handle, u8_t *buff) +{ + u8_t i, j, k; + u8_t numberOfByteForDimension; + + numberOfByteForDimension=6/3; + + k=0; + for (i=0; i<3;i++ ) + { + for (j=0; j> shift) * LSM303AGR_ACC_Sensitivity_List[op_mode][fs_mode] + 500) / 1000; + buff[1] = ((raw_data_tmp.i16bit[1] >> shift) * LSM303AGR_ACC_Sensitivity_List[op_mode][fs_mode] + 500) / 1000; + buff[2] = ((raw_data_tmp.i16bit[2] >> shift) * LSM303AGR_ACC_Sensitivity_List[op_mode][fs_mode] + 500) / 1000; + + return MEMS_SUCCESS; +} diff --git a/LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/LSM303AGR/LSM303AGR_acc_driver.h b/LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/LSM303AGR/LSM303AGR_acc_driver.h new file mode 100644 index 0000000..42b213a --- /dev/null +++ b/LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/LSM303AGR/LSM303AGR_acc_driver.h @@ -0,0 +1,1608 @@ +/** + ****************************************************************************** + * @file LSM303AGR_acc_driver.h + * @author MEMS Application Team + * @version V1.1 + * @date 24-February-2016 + * @brief LSM303AGR Accelerometer header driver file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __LSM303AGR_ACC_DRIVER__H +#define __LSM303AGR_ACC_DRIVER__H + +/* Includes ------------------------------------------------------------------*/ +#include + +/* Exported types ------------------------------------------------------------*/ + +#ifdef __cplusplus +extern "C" { +#endif + +//these could change accordingly with the architecture + +#ifndef __ARCHDEP__TYPES +#define __ARCHDEP__TYPES + +typedef unsigned char u8_t; +typedef unsigned short int u16_t; +typedef unsigned int u32_t; +typedef int i32_t; +typedef short int i16_t; +typedef signed char i8_t; + +#endif /*__ARCHDEP__TYPES*/ + +/* Exported common structure --------------------------------------------------------*/ + +#ifndef __SHARED__TYPES +#define __SHARED__TYPES + +typedef union{ + i16_t i16bit[3]; + u8_t u8bit[6]; +} Type3Axis16bit_U; + +typedef union{ + i16_t i16bit; + u8_t u8bit[2]; +} Type1Axis16bit_U; + +typedef union{ + i32_t i32bit; + u8_t u8bit[4]; +} Type1Axis32bit_U; + +typedef enum { + MEMS_SUCCESS = 0x01, + MEMS_ERROR = 0x00 +} mems_status_t; + +#endif /*__SHARED__TYPES*/ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ + +/************** I2C Address *****************/ + +#define LSM303AGR_ACC_I2C_ADDRESS 0x32 + +/************** Who am I *******************/ + +#define LSM303AGR_ACC_WHO_AM_I 0x33 + +/* Private Function Prototype -------------------------------------------------------*/ + +void LSM303AGR_ACC_SwapHighLowByte(u8_t *bufferToSwap, u8_t numberOfByte, u8_t dimension); + +/* Public Function Prototypes ------------------------------------------------*/ + +mems_status_t LSM303AGR_ACC_read_reg( void *handle, u8_t Reg, u8_t* Data ); +mems_status_t LSM303AGR_ACC_write_reg( void *handle, u8_t Reg, u8_t Data ); + + +/************** Device Register *******************/ +#define LSM303AGR_ACC_STATUS_REG_AUX 0X07 +#define LSM303AGR_ACC_OUT_ADC1_L 0X08 +#define LSM303AGR_ACC_OUT_ADC1_H 0X09 +#define LSM303AGR_ACC_OUT_ADC2_L 0X0A +#define LSM303AGR_ACC_OUT_ADC2_H 0X0B +#define LSM303AGR_ACC_OUT_ADC3_L 0X0C +#define LSM303AGR_ACC_OUT_ADC3_H 0X0D +#define LSM303AGR_ACC_INT_COUNTER_REG 0X0E +#define LSM303AGR_ACC_WHO_AM_I_REG 0X0F +#define LSM303AGR_ACC_TEMP_CFG_REG 0X1F +#define LSM303AGR_ACC_CTRL_REG1 0X20 +#define LSM303AGR_ACC_CTRL_REG2 0X21 +#define LSM303AGR_ACC_CTRL_REG3 0X22 +#define LSM303AGR_ACC_CTRL_REG4 0X23 +#define LSM303AGR_ACC_CTRL_REG5 0X24 +#define LSM303AGR_ACC_CTRL_REG6 0X25 +#define LSM303AGR_ACC_REFERENCE 0X26 +#define LSM303AGR_ACC_STATUS_REG2 0X27 +#define LSM303AGR_ACC_OUT_X_L 0X28 +#define LSM303AGR_ACC_OUT_X_H 0X29 +#define LSM303AGR_ACC_OUT_Y_L 0X2A +#define LSM303AGR_ACC_OUT_Y_H 0X2B +#define LSM303AGR_ACC_OUT_Z_L 0X2C +#define LSM303AGR_ACC_OUT_Z_H 0X2D +#define LSM303AGR_ACC_FIFO_CTRL_REG 0X2E +#define LSM303AGR_ACC_FIFO_SRC_REG 0X2F +#define LSM303AGR_ACC_INT1_CFG 0X30 +#define LSM303AGR_ACC_INT1_SOURCE 0X31 +#define LSM303AGR_ACC_INT1_THS 0X32 +#define LSM303AGR_ACC_INT1_DURATION 0X33 +#define LSM303AGR_ACC_INT2_CFG 0X34 +#define LSM303AGR_ACC_INT2_SOURCE 0X35 +#define LSM303AGR_ACC_INT2_THS 0X36 +#define LSM303AGR_ACC_INT2_DURATION 0X37 +#define LSM303AGR_ACC_CLICK_CFG 0X38 +#define LSM303AGR_ACC_CLICK_SRC 0X39 +#define LSM303AGR_ACC_CLICK_THS 0X3A +#define LSM303AGR_ACC_TIME_LIMIT 0X3B +#define LSM303AGR_ACC_TIME_LATENCY 0X3C +#define LSM303AGR_ACC_TIME_WINDOW 0X3D + +/******************************************************************************* +* Register : STATUS_REG_AUX +* Address : 0X07 +* Bit Group Name: 1DA +* Permission : RO +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_1DA_NOT_AVAILABLE =0x00, + LSM303AGR_ACC_1DA_AVAILABLE =0x01, +} LSM303AGR_ACC_1DA_t; + +#define LSM303AGR_ACC_1DA_MASK 0x01 +mems_status_t LSM303AGR_ACC_R_x_data_avail(void *handle, LSM303AGR_ACC_1DA_t *value); + +/******************************************************************************* +* Register : STATUS_REG_AUX +* Address : 0X07 +* Bit Group Name: 2DA_ +* Permission : RO +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_2DA__NOT_AVAILABLE =0x00, + LSM303AGR_ACC_2DA__AVAILABLE =0x02, +} LSM303AGR_ACC_2DA__t; + +#define LSM303AGR_ACC_2DA__MASK 0x02 +mems_status_t LSM303AGR_ACC_R_y_data_avail(void *handle, LSM303AGR_ACC_2DA__t *value); + +/******************************************************************************* +* Register : STATUS_REG_AUX +* Address : 0X07 +* Bit Group Name: 3DA_ +* Permission : RO +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_3DA__NOT_AVAILABLE =0x00, + LSM303AGR_ACC_3DA__AVAILABLE =0x04, +} LSM303AGR_ACC_3DA__t; + +#define LSM303AGR_ACC_3DA__MASK 0x04 +mems_status_t LSM303AGR_ACC_R_z_data_avail(void *handle, LSM303AGR_ACC_3DA__t *value); + +/******************************************************************************* +* Register : STATUS_REG_AUX +* Address : 0X07 +* Bit Group Name: 321DA_ +* Permission : RO +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_321DA__NOT_AVAILABLE =0x00, + LSM303AGR_ACC_321DA__AVAILABLE =0x08, +} LSM303AGR_ACC_321DA__t; + +#define LSM303AGR_ACC_321DA__MASK 0x08 +mems_status_t LSM303AGR_ACC_R_xyz_data_avail(void *handle, LSM303AGR_ACC_321DA__t *value); + +/******************************************************************************* +* Register : STATUS_REG_AUX +* Address : 0X07 +* Bit Group Name: 1OR_ +* Permission : RO +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_1OR__NO_OVERRUN =0x00, + LSM303AGR_ACC_1OR__OVERRUN =0x10, +} LSM303AGR_ACC_1OR__t; + +#define LSM303AGR_ACC_1OR__MASK 0x10 +mems_status_t LSM303AGR_ACC_R_DataXOverrun(void *handle, LSM303AGR_ACC_1OR__t *value); + +/******************************************************************************* +* Register : STATUS_REG_AUX +* Address : 0X07 +* Bit Group Name: 2OR_ +* Permission : RO +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_2OR__NO_OVERRUN =0x00, + LSM303AGR_ACC_2OR__OVERRUN =0x20, +} LSM303AGR_ACC_2OR__t; + +#define LSM303AGR_ACC_2OR__MASK 0x20 +mems_status_t LSM303AGR_ACC_R_DataYOverrun(void *handle, LSM303AGR_ACC_2OR__t *value); + +/******************************************************************************* +* Register : STATUS_REG_AUX +* Address : 0X07 +* Bit Group Name: 3OR_ +* Permission : RO +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_3OR__NO_OVERRUN =0x00, + LSM303AGR_ACC_3OR__OVERRUN =0x40, +} LSM303AGR_ACC_3OR__t; + +#define LSM303AGR_ACC_3OR__MASK 0x40 +mems_status_t LSM303AGR_ACC_R_DataZOverrun(void *handle, LSM303AGR_ACC_3OR__t *value); + +/******************************************************************************* +* Register : STATUS_REG_AUX +* Address : 0X07 +* Bit Group Name: 321OR_ +* Permission : RO +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_321OR__NO_OVERRUN =0x00, + LSM303AGR_ACC_321OR__OVERRUN =0x80, +} LSM303AGR_ACC_321OR__t; + +#define LSM303AGR_ACC_321OR__MASK 0x80 +mems_status_t LSM303AGR_ACC_R_DataXYZOverrun(void *handle, LSM303AGR_ACC_321OR__t *value); + +/******************************************************************************* +* Register : INT_COUNTER_REG +* Address : 0X0E +* Bit Group Name: IC +* Permission : RO +*******************************************************************************/ +#define LSM303AGR_ACC_IC_MASK 0xFF +#define LSM303AGR_ACC_IC_POSITION 0 +mems_status_t LSM303AGR_ACC_R_int_counter(void *handle, u8_t *value); + +/******************************************************************************* +* Register : WHO_AM_I +* Address : 0X0F +* Bit Group Name: WHO_AM_I +* Permission : RO +*******************************************************************************/ +#define LSM303AGR_ACC_WHO_AM_I_MASK 0xFF +#define LSM303AGR_ACC_WHO_AM_I_POSITION 0 +mems_status_t LSM303AGR_ACC_R_WHO_AM_I(void *handle, u8_t *value); + +/******************************************************************************* +* Register : TEMP_CFG_REG +* Address : 0X1F +* Bit Group Name: TEMP_EN +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_TEMP_EN_DISABLED =0x00, + LSM303AGR_ACC_TEMP_EN_ENABLED =0x40, +} LSM303AGR_ACC_TEMP_EN_t; + +#define LSM303AGR_ACC_TEMP_EN_MASK 0x40 +mems_status_t LSM303AGR_ACC_W_TEMP_EN_bits(void *handle, LSM303AGR_ACC_TEMP_EN_t newValue); +mems_status_t LSM303AGR_ACC_R_TEMP_EN_bits(void *handle, LSM303AGR_ACC_TEMP_EN_t *value); + +/******************************************************************************* +* Register : TEMP_CFG_REG +* Address : 0X1F +* Bit Group Name: ADC_PD +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_ADC_PD_DISABLED =0x00, + LSM303AGR_ACC_ADC_PD_ENABLED =0x80, +} LSM303AGR_ACC_ADC_PD_t; + +#define LSM303AGR_ACC_ADC_PD_MASK 0x80 +mems_status_t LSM303AGR_ACC_W_ADC_PD(void *handle, LSM303AGR_ACC_ADC_PD_t newValue); +mems_status_t LSM303AGR_ACC_R_ADC_PD(void *handle, LSM303AGR_ACC_ADC_PD_t *value); + +/******************************************************************************* +* Register : CTRL_REG1 +* Address : 0X20 +* Bit Group Name: XEN +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_XEN_DISABLED =0x00, + LSM303AGR_ACC_XEN_ENABLED =0x01, +} LSM303AGR_ACC_XEN_t; + +#define LSM303AGR_ACC_XEN_MASK 0x01 +mems_status_t LSM303AGR_ACC_W_XEN(void *handle, LSM303AGR_ACC_XEN_t newValue); +mems_status_t LSM303AGR_ACC_R_XEN(void *handle, LSM303AGR_ACC_XEN_t *value); + +/******************************************************************************* +* Register : CTRL_REG1 +* Address : 0X20 +* Bit Group Name: YEN +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_YEN_DISABLED =0x00, + LSM303AGR_ACC_YEN_ENABLED =0x02, +} LSM303AGR_ACC_YEN_t; + +#define LSM303AGR_ACC_YEN_MASK 0x02 +mems_status_t LSM303AGR_ACC_W_YEN(void *handle, LSM303AGR_ACC_YEN_t newValue); +mems_status_t LSM303AGR_ACC_R_YEN(void *handle, LSM303AGR_ACC_YEN_t *value); + +/******************************************************************************* +* Register : CTRL_REG1 +* Address : 0X20 +* Bit Group Name: ZEN +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_ZEN_DISABLED =0x00, + LSM303AGR_ACC_ZEN_ENABLED =0x04, +} LSM303AGR_ACC_ZEN_t; + +#define LSM303AGR_ACC_ZEN_MASK 0x04 +mems_status_t LSM303AGR_ACC_W_ZEN(void *handle, LSM303AGR_ACC_ZEN_t newValue); +mems_status_t LSM303AGR_ACC_R_ZEN(void *handle, LSM303AGR_ACC_ZEN_t *value); + +/******************************************************************************* +* Register : CTRL_REG1 +* Address : 0X20 +* Bit Group Name: LPEN +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_LPEN_DISABLED =0x00, + LSM303AGR_ACC_LPEN_ENABLED =0x08, +} LSM303AGR_ACC_LPEN_t; + +#define LSM303AGR_ACC_LPEN_MASK 0x08 +mems_status_t LSM303AGR_ACC_W_LOWPWR_EN(void *handle, LSM303AGR_ACC_LPEN_t newValue); +mems_status_t LSM303AGR_ACC_R_LOWPWR_EN(void *handle, LSM303AGR_ACC_LPEN_t *value); + +/******************************************************************************* +* Register : CTRL_REG1 +* Address : 0X20 +* Bit Group Name: ODR +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_ODR_DO_PWR_DOWN =0x00, + LSM303AGR_ACC_ODR_DO_1Hz =0x10, + LSM303AGR_ACC_ODR_DO_10Hz =0x20, + LSM303AGR_ACC_ODR_DO_25Hz =0x30, + LSM303AGR_ACC_ODR_DO_50Hz =0x40, + LSM303AGR_ACC_ODR_DO_100Hz =0x50, + LSM303AGR_ACC_ODR_DO_200Hz =0x60, + LSM303AGR_ACC_ODR_DO_400Hz =0x70, + LSM303AGR_ACC_ODR_DO_1_6KHz =0x80, + LSM303AGR_ACC_ODR_DO_1_25KHz =0x90, +} LSM303AGR_ACC_ODR_t; + +#define LSM303AGR_ACC_ODR_MASK 0xF0 +mems_status_t LSM303AGR_ACC_W_ODR(void *handle, LSM303AGR_ACC_ODR_t newValue); +mems_status_t LSM303AGR_ACC_R_ODR(void *handle, LSM303AGR_ACC_ODR_t *value); + +/******************************************************************************* +* Register : CTRL_REG2 +* Address : 0X21 +* Bit Group Name: HPIS1 +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_HPIS1_DISABLED =0x00, + LSM303AGR_ACC_HPIS1_ENABLED =0x01, +} LSM303AGR_ACC_HPIS1_t; + +#define LSM303AGR_ACC_HPIS1_MASK 0x01 +mems_status_t LSM303AGR_ACC_W_hpf_aoi_en_int1(void *handle, LSM303AGR_ACC_HPIS1_t newValue); +mems_status_t LSM303AGR_ACC_R_hpf_aoi_en_int1(void *handle, LSM303AGR_ACC_HPIS1_t *value); + +/******************************************************************************* +* Register : CTRL_REG2 +* Address : 0X21 +* Bit Group Name: HPIS2 +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_HPIS2_DISABLED =0x00, + LSM303AGR_ACC_HPIS2_ENABLED =0x02, +} LSM303AGR_ACC_HPIS2_t; + +#define LSM303AGR_ACC_HPIS2_MASK 0x02 +mems_status_t LSM303AGR_ACC_W_hpf_aoi_en_int2(void *handle, LSM303AGR_ACC_HPIS2_t newValue); +mems_status_t LSM303AGR_ACC_R_hpf_aoi_en_int2(void *handle, LSM303AGR_ACC_HPIS2_t *value); + +/******************************************************************************* +* Register : CTRL_REG2 +* Address : 0X21 +* Bit Group Name: HPCLICK +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_HPCLICK_DISABLED =0x00, + LSM303AGR_ACC_HPCLICK_ENABLED =0x04, +} LSM303AGR_ACC_HPCLICK_t; + +#define LSM303AGR_ACC_HPCLICK_MASK 0x04 +mems_status_t LSM303AGR_ACC_W_hpf_click_en(void *handle, LSM303AGR_ACC_HPCLICK_t newValue); +mems_status_t LSM303AGR_ACC_R_hpf_click_en(void *handle, LSM303AGR_ACC_HPCLICK_t *value); + +/******************************************************************************* +* Register : CTRL_REG2 +* Address : 0X21 +* Bit Group Name: FDS +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_FDS_BYPASSED =0x00, + LSM303AGR_ACC_FDS_ENABLED =0x08, +} LSM303AGR_ACC_FDS_t; + +#define LSM303AGR_ACC_FDS_MASK 0x08 +mems_status_t LSM303AGR_ACC_W_Data_Filter(void *handle, LSM303AGR_ACC_FDS_t newValue); +mems_status_t LSM303AGR_ACC_R_Data_Filter(void *handle, LSM303AGR_ACC_FDS_t *value); + +/******************************************************************************* +* Register : CTRL_REG2 +* Address : 0X21 +* Bit Group Name: HPCF +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_HPCF_00 =0x00, + LSM303AGR_ACC_HPCF_01 =0x10, + LSM303AGR_ACC_HPCF_10 =0x20, + LSM303AGR_ACC_HPCF_11 =0x30, +} LSM303AGR_ACC_HPCF_t; + +#define LSM303AGR_ACC_HPCF_MASK 0x30 +mems_status_t LSM303AGR_ACC_W_hpf_cutoff_freq(void *handle, LSM303AGR_ACC_HPCF_t newValue); +mems_status_t LSM303AGR_ACC_R_hpf_cutoff_freq(void *handle, LSM303AGR_ACC_HPCF_t *value); + +/******************************************************************************* +* Register : CTRL_REG2 +* Address : 0X21 +* Bit Group Name: HPM +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_HPM_NORMAL =0x00, + LSM303AGR_ACC_HPM_REFERENCE_SIGNAL =0x40, + LSM303AGR_ACC_HPM_NORMAL_2 =0x80, + LSM303AGR_ACC_HPM_AUTORST_ON_INT =0xC0, +} LSM303AGR_ACC_HPM_t; + +#define LSM303AGR_ACC_HPM_MASK 0xC0 +mems_status_t LSM303AGR_ACC_W_hpf_mode(void *handle, LSM303AGR_ACC_HPM_t newValue); +mems_status_t LSM303AGR_ACC_R_hpf_mode(void *handle, LSM303AGR_ACC_HPM_t *value); + +/******************************************************************************* +* Register : CTRL_REG3 +* Address : 0X22 +* Bit Group Name: I1_OVERRUN +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_I1_OVERRUN_DISABLED =0x00, + LSM303AGR_ACC_I1_OVERRUN_ENABLED =0x02, +} LSM303AGR_ACC_I1_OVERRUN_t; + +#define LSM303AGR_ACC_I1_OVERRUN_MASK 0x02 +mems_status_t LSM303AGR_ACC_W_FIFO_Overrun_on_INT1(void *handle, LSM303AGR_ACC_I1_OVERRUN_t newValue); +mems_status_t LSM303AGR_ACC_R_FIFO_Overrun_on_INT1(void *handle, LSM303AGR_ACC_I1_OVERRUN_t *value); + +/******************************************************************************* +* Register : CTRL_REG3 +* Address : 0X22 +* Bit Group Name: I1_WTM +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_I1_WTM_DISABLED =0x00, + LSM303AGR_ACC_I1_WTM_ENABLED =0x04, +} LSM303AGR_ACC_I1_WTM_t; + +#define LSM303AGR_ACC_I1_WTM_MASK 0x04 +mems_status_t LSM303AGR_ACC_W_FIFO_Watermark_on_INT1(void *handle, LSM303AGR_ACC_I1_WTM_t newValue); +mems_status_t LSM303AGR_ACC_R_FIFO_Watermark_on_INT1(void *handle, LSM303AGR_ACC_I1_WTM_t *value); + +/******************************************************************************* +* Register : CTRL_REG3 +* Address : 0X22 +* Bit Group Name: I1_DRDY2 +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_I1_DRDY2_DISABLED =0x00, + LSM303AGR_ACC_I1_DRDY2_ENABLED =0x08, +} LSM303AGR_ACC_I1_DRDY2_t; + +#define LSM303AGR_ACC_I1_DRDY2_MASK 0x08 +mems_status_t LSM303AGR_ACC_W_FIFO_DRDY2_on_INT1(void *handle, LSM303AGR_ACC_I1_DRDY2_t newValue); +mems_status_t LSM303AGR_ACC_R_FIFO_DRDY2_on_INT1(void *handle, LSM303AGR_ACC_I1_DRDY2_t *value); + +/******************************************************************************* +* Register : CTRL_REG3 +* Address : 0X22 +* Bit Group Name: I1_DRDY1 +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_I1_DRDY1_DISABLED =0x00, + LSM303AGR_ACC_I1_DRDY1_ENABLED =0x10, +} LSM303AGR_ACC_I1_DRDY1_t; + +#define LSM303AGR_ACC_I1_DRDY1_MASK 0x10 +mems_status_t LSM303AGR_ACC_W_FIFO_DRDY1_on_INT1(void *handle, LSM303AGR_ACC_I1_DRDY1_t newValue); +mems_status_t LSM303AGR_ACC_R_FIFO_DRDY1_on_INT1(void *handle, LSM303AGR_ACC_I1_DRDY1_t *value); + +/******************************************************************************* +* Register : CTRL_REG3 +* Address : 0X22 +* Bit Group Name: I1_AOI2 +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_I1_AOI2_DISABLED =0x00, + LSM303AGR_ACC_I1_AOI2_ENABLED =0x20, +} LSM303AGR_ACC_I1_AOI2_t; + +#define LSM303AGR_ACC_I1_AOI2_MASK 0x20 +mems_status_t LSM303AGR_ACC_W_FIFO_AOL2_on_INT1(void *handle, LSM303AGR_ACC_I1_AOI2_t newValue); +mems_status_t LSM303AGR_ACC_R_FIFO_AOL2_on_INT1(void *handle, LSM303AGR_ACC_I1_AOI2_t *value); + +/******************************************************************************* +* Register : CTRL_REG3 +* Address : 0X22 +* Bit Group Name: I1_AOI1 +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_I1_AOI1_DISABLED =0x00, + LSM303AGR_ACC_I1_AOI1_ENABLED =0x40, +} LSM303AGR_ACC_I1_AOI1_t; + +#define LSM303AGR_ACC_I1_AOI1_MASK 0x40 +mems_status_t LSM303AGR_ACC_W_FIFO_AOL1_on_INT1(void *handle, LSM303AGR_ACC_I1_AOI1_t newValue); +mems_status_t LSM303AGR_ACC_R_FIFO_AOL1_on_INT1(void *handle, LSM303AGR_ACC_I1_AOI1_t *value); + +/******************************************************************************* +* Register : CTRL_REG3 +* Address : 0X22 +* Bit Group Name: I1_CLICK +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_I1_CLICK_DISABLED =0x00, + LSM303AGR_ACC_I1_CLICK_ENABLED =0x80, +} LSM303AGR_ACC_I1_CLICK_t; + +#define LSM303AGR_ACC_I1_CLICK_MASK 0x80 +mems_status_t LSM303AGR_ACC_W_FIFO_Click_on_INT1(void *handle, LSM303AGR_ACC_I1_CLICK_t newValue); +mems_status_t LSM303AGR_ACC_R_FIFO_Click_on_INT1(void *handle, LSM303AGR_ACC_I1_CLICK_t *value); + +/******************************************************************************* +* Register : CTRL_REG4 +* Address : 0X23 +* Bit Group Name: SIM +* Permission : RW +*******************************************************************************/ +typedef enum { +// LSM303AGR_ACC_SIM_4_WIRES =0x00, // FIXME not allowed by the component + LSM303AGR_ACC_SIM_3_WIRES =0x01 +} LSM303AGR_ACC_SIM_t; + +#define LSM303AGR_ACC_SIM_MASK 0x01 +mems_status_t LSM303AGR_ACC_W_SPI_mode(void *handle, LSM303AGR_ACC_SIM_t newValue); +mems_status_t LSM303AGR_ACC_R_SPI_mode(void *handle, LSM303AGR_ACC_SIM_t *value); + +/******************************************************************************* +* Register : CTRL_REG4 +* Address : 0X23 +* Bit Group Name: ST +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_ST_DISABLED =0x00, + LSM303AGR_ACC_ST_SELF_TEST_0 =0x02, + LSM303AGR_ACC_ST_SELF_TEST_1 =0x04, + LSM303AGR_ACC_ST_NOT_APPLICABLE =0x06, +} LSM303AGR_ACC_ST_t; + +#define LSM303AGR_ACC_ST_MASK 0x06 +mems_status_t LSM303AGR_ACC_W_SelfTest(void *handle, LSM303AGR_ACC_ST_t newValue); +mems_status_t LSM303AGR_ACC_R_SelfTest(void *handle, LSM303AGR_ACC_ST_t *value); + +/******************************************************************************* +* Register : CTRL_REG4 +* Address : 0X23 +* Bit Group Name: HR +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_HR_DISABLED =0x00, + LSM303AGR_ACC_HR_ENABLED =0x08, +} LSM303AGR_ACC_HR_t; + +#define LSM303AGR_ACC_HR_MASK 0x08 +mems_status_t LSM303AGR_ACC_W_HiRes(void *handle, LSM303AGR_ACC_HR_t newValue); +mems_status_t LSM303AGR_ACC_R_HiRes(void *handle, LSM303AGR_ACC_HR_t *value); + +/******************************************************************************* +* Register : CTRL_REG4 +* Address : 0X23 +* Bit Group Name: FS +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_FS_2G =0x00, + LSM303AGR_ACC_FS_4G =0x10, + LSM303AGR_ACC_FS_8G =0x20, + LSM303AGR_ACC_FS_16G =0x30, +} LSM303AGR_ACC_FS_t; + +#define LSM303AGR_ACC_FS_MASK 0x30 +mems_status_t LSM303AGR_ACC_W_FullScale(void *handle, LSM303AGR_ACC_FS_t newValue); +mems_status_t LSM303AGR_ACC_R_FullScale(void *handle, LSM303AGR_ACC_FS_t *value); + +/******************************************************************************* +* Register : CTRL_REG4 +* Address : 0X23 +* Bit Group Name: BLE +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_BLE_LITTLE_ENDIAN =0x00, + LSM303AGR_ACC_BLE_BIG_ENDIAN =0x40, +} LSM303AGR_ACC_BLE_t; + +#define LSM303AGR_ACC_BLE_MASK 0x40 +mems_status_t LSM303AGR_ACC_W_LittleBigEndian(void *handle, LSM303AGR_ACC_BLE_t newValue); +mems_status_t LSM303AGR_ACC_R_LittleBigEndian(void *handle, LSM303AGR_ACC_BLE_t *value); + +/******************************************************************************* +* Register : CTRL_REG4 +* Address : 0X23 +* Bit Group Name: BDU +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_BDU_DISABLED =0x00, + LSM303AGR_ACC_BDU_ENABLED =0x80, +} LSM303AGR_ACC_BDU_t; + +#define LSM303AGR_ACC_BDU_MASK 0x80 +mems_status_t LSM303AGR_ACC_W_BlockDataUpdate(void *handle, LSM303AGR_ACC_BDU_t newValue); +mems_status_t LSM303AGR_ACC_R_BlockDataUpdate(void *handle, LSM303AGR_ACC_BDU_t *value); + +/******************************************************************************* +* Register : CTRL_REG5 +* Address : 0X24 +* Bit Group Name: D4D_INT2 +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_D4D_INT2_DISABLED =0x00, + LSM303AGR_ACC_D4D_INT2_ENABLED =0x01, +} LSM303AGR_ACC_D4D_INT2_t; + +#define LSM303AGR_ACC_D4D_INT2_MASK 0x01 +mems_status_t LSM303AGR_ACC_W_4D_on_INT2(void *handle, LSM303AGR_ACC_D4D_INT2_t newValue); +mems_status_t LSM303AGR_ACC_R_4D_on_INT2(void *handle, LSM303AGR_ACC_D4D_INT2_t *value); + +/******************************************************************************* +* Register : CTRL_REG5 +* Address : 0X24 +* Bit Group Name: LIR_INT2 +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_LIR_INT2_DISABLED =0x00, + LSM303AGR_ACC_LIR_INT2_ENABLED =0x02, +} LSM303AGR_ACC_LIR_INT2_t; + +#define LSM303AGR_ACC_LIR_INT2_MASK 0x02 +mems_status_t LSM303AGR_ACC_W_LatchInterrupt_on_INT2(void *handle, LSM303AGR_ACC_LIR_INT2_t newValue); +mems_status_t LSM303AGR_ACC_R_LatchInterrupt_on_INT2(void *handle, LSM303AGR_ACC_LIR_INT2_t *value); + +/******************************************************************************* +* Register : CTRL_REG5 +* Address : 0X24 +* Bit Group Name: D4D_INT1 +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_D4D_INT1_DISABLED =0x00, + LSM303AGR_ACC_D4D_INT1_ENABLED =0x04, +} LSM303AGR_ACC_D4D_INT1_t; + +#define LSM303AGR_ACC_D4D_INT1_MASK 0x04 +mems_status_t LSM303AGR_ACC_W_4D_on_INT1(void *handle, LSM303AGR_ACC_D4D_INT1_t newValue); +mems_status_t LSM303AGR_ACC_R_4D_on_INT1(void *handle, LSM303AGR_ACC_D4D_INT1_t *value); + +/******************************************************************************* +* Register : CTRL_REG5 +* Address : 0X24 +* Bit Group Name: LIR_INT1 +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_LIR_INT1_DISABLED =0x00, + LSM303AGR_ACC_LIR_INT1_ENABLED =0x08, +} LSM303AGR_ACC_LIR_INT1_t; + +#define LSM303AGR_ACC_LIR_INT1_MASK 0x08 +mems_status_t LSM303AGR_ACC_W_LatchInterrupt_on_INT1(void *handle, LSM303AGR_ACC_LIR_INT1_t newValue); +mems_status_t LSM303AGR_ACC_R_LatchInterrupt_on_INT1(void *handle, LSM303AGR_ACC_LIR_INT1_t *value); + +/******************************************************************************* +* Register : CTRL_REG5 +* Address : 0X24 +* Bit Group Name: FIFO_EN +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_FIFO_EN_DISABLED =0x00, + LSM303AGR_ACC_FIFO_EN_ENABLED =0x40, +} LSM303AGR_ACC_FIFO_EN_t; + +#define LSM303AGR_ACC_FIFO_EN_MASK 0x40 +mems_status_t LSM303AGR_ACC_W_FIFO_EN(void *handle, LSM303AGR_ACC_FIFO_EN_t newValue); +mems_status_t LSM303AGR_ACC_R_FIFO_EN(void *handle, LSM303AGR_ACC_FIFO_EN_t *value); + +/******************************************************************************* +* Register : CTRL_REG5 +* Address : 0X24 +* Bit Group Name: BOOT +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_BOOT_NORMAL_MODE =0x00, + LSM303AGR_ACC_BOOT_REBOOT =0x80, +} LSM303AGR_ACC_BOOT_t; + +#define LSM303AGR_ACC_BOOT_MASK 0x80 +mems_status_t LSM303AGR_ACC_W_RebootMemory(void *handle, LSM303AGR_ACC_BOOT_t newValue); +mems_status_t LSM303AGR_ACC_R_RebootMemory(void *handle, LSM303AGR_ACC_BOOT_t *value); + +/******************************************************************************* +* Register : CTRL_REG6 +* Address : 0X25 +* Bit Group Name: H_LACTIVE +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_H_LACTIVE_ACTIVE_HI =0x00, + LSM303AGR_ACC_H_LACTIVE_ACTIVE_LO =0x02, +} LSM303AGR_ACC_H_LACTIVE_t; + +#define LSM303AGR_ACC_H_LACTIVE_MASK 0x02 +mems_status_t LSM303AGR_ACC_W_IntActive(void *handle, LSM303AGR_ACC_H_LACTIVE_t newValue); +mems_status_t LSM303AGR_ACC_R_IntActive(void *handle, LSM303AGR_ACC_H_LACTIVE_t *value); + +/******************************************************************************* +* Register : CTRL_REG6 +* Address : 0X25 +* Bit Group Name: P2_ACT +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_P2_ACT_DISABLED =0x00, + LSM303AGR_ACC_P2_ACT_ENABLED =0x08, +} LSM303AGR_ACC_P2_ACT_t; + +#define LSM303AGR_ACC_P2_ACT_MASK 0x08 +mems_status_t LSM303AGR_ACC_W_P2_ACT(void *handle, LSM303AGR_ACC_P2_ACT_t newValue); +mems_status_t LSM303AGR_ACC_R_P2_ACT(void *handle, LSM303AGR_ACC_P2_ACT_t *value); + +/******************************************************************************* +* Register : CTRL_REG6 +* Address : 0X25 +* Bit Group Name: BOOT_I1 +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_BOOT_I1_DISABLED =0x00, + LSM303AGR_ACC_BOOT_I1_ENABLED =0x10, +} LSM303AGR_ACC_BOOT_I1_t; + +#define LSM303AGR_ACC_BOOT_I1_MASK 0x10 +mems_status_t LSM303AGR_ACC_W_Boot_on_INT2(void *handle, LSM303AGR_ACC_BOOT_I1_t newValue); +mems_status_t LSM303AGR_ACC_R_Boot_on_INT2(void *handle, LSM303AGR_ACC_BOOT_I1_t *value); + +/******************************************************************************* +* Register : CTRL_REG6 +* Address : 0X25 +* Bit Group Name: I2_INT2 +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_I2_INT2_DISABLED =0x00, + LSM303AGR_ACC_I2_INT2_ENABLED =0x20, +} LSM303AGR_ACC_I2_INT2_t; + +#define LSM303AGR_ACC_I2_INT2_MASK 0x20 +mems_status_t LSM303AGR_ACC_W_I2_on_INT2(void *handle, LSM303AGR_ACC_I2_INT2_t newValue); +mems_status_t LSM303AGR_ACC_R_I2_on_INT2(void *handle, LSM303AGR_ACC_I2_INT2_t *value); + +/******************************************************************************* +* Register : CTRL_REG6 +* Address : 0X25 +* Bit Group Name: I2_INT1 +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_I2_INT1_DISABLED =0x00, + LSM303AGR_ACC_I2_INT1_ENABLED =0x40, +} LSM303AGR_ACC_I2_INT1_t; + +#define LSM303AGR_ACC_I2_INT1_MASK 0x40 +mems_status_t LSM303AGR_ACC_W_I2_on_INT1(void *handle, LSM303AGR_ACC_I2_INT1_t newValue); +mems_status_t LSM303AGR_ACC_R_I2_on_INT1(void *handle, LSM303AGR_ACC_I2_INT1_t *value); + +/******************************************************************************* +* Register : CTRL_REG6 +* Address : 0X25 +* Bit Group Name: I2_CLICKEN +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_I2_CLICKEN_DISABLED =0x00, + LSM303AGR_ACC_I2_CLICKEN_ENABLED =0x80, +} LSM303AGR_ACC_I2_CLICKEN_t; + +#define LSM303AGR_ACC_I2_CLICKEN_MASK 0x80 +mems_status_t LSM303AGR_ACC_W_Click_on_INT2(void *handle, LSM303AGR_ACC_I2_CLICKEN_t newValue); +mems_status_t LSM303AGR_ACC_R_Click_on_INT2(void *handle, LSM303AGR_ACC_I2_CLICKEN_t *value); + +/******************************************************************************* +* Register : REFERENCE +* Address : 0X26 +* Bit Group Name: REF +* Permission : RW +*******************************************************************************/ +#define LSM303AGR_ACC_REF_MASK 0xFF +#define LSM303AGR_ACC_REF_POSITION 0 +mems_status_t LSM303AGR_ACC_W_ReferenceVal(void *handle, u8_t newValue); +mems_status_t LSM303AGR_ACC_R_ReferenceVal(void *handle, u8_t *value); + +/******************************************************************************* +* Register : STATUS_REG2 +* Address : 0X27 +* Bit Group Name: XDA +* Permission : RO +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_XDA_NOT_AVAILABLE =0x00, + LSM303AGR_ACC_XDA_AVAILABLE =0x01, +} LSM303AGR_ACC_XDA_t; + +#define LSM303AGR_ACC_XDA_MASK 0x01 +mems_status_t LSM303AGR_ACC_R_XDataAvail(void *handle, LSM303AGR_ACC_XDA_t *value); + +/******************************************************************************* +* Register : STATUS_REG2 +* Address : 0X27 +* Bit Group Name: YDA +* Permission : RO +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_YDA_NOT_AVAILABLE =0x00, + LSM303AGR_ACC_YDA_AVAILABLE =0x02, +} LSM303AGR_ACC_YDA_t; + +#define LSM303AGR_ACC_YDA_MASK 0x02 +mems_status_t LSM303AGR_ACC_R_YDataAvail(void *handle, LSM303AGR_ACC_YDA_t *value); + +/******************************************************************************* +* Register : STATUS_REG2 +* Address : 0X27 +* Bit Group Name: ZDA +* Permission : RO +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_ZDA_NOT_AVAILABLE =0x00, + LSM303AGR_ACC_ZDA_AVAILABLE =0x04, +} LSM303AGR_ACC_ZDA_t; + +#define LSM303AGR_ACC_ZDA_MASK 0x04 +mems_status_t LSM303AGR_ACC_R_ZDataAvail(void *handle, LSM303AGR_ACC_ZDA_t *value); + +/******************************************************************************* +* Register : STATUS_REG2 +* Address : 0X27 +* Bit Group Name: ZYXDA +* Permission : RO +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_ZYXDA_NOT_AVAILABLE =0x00, + LSM303AGR_ACC_ZYXDA_AVAILABLE =0x08, +} LSM303AGR_ACC_ZYXDA_t; + +#define LSM303AGR_ACC_ZYXDA_MASK 0x08 +mems_status_t LSM303AGR_ACC_R_XYZDataAvail(void *handle, LSM303AGR_ACC_ZYXDA_t *value); + +/******************************************************************************* +* Register : STATUS_REG2 +* Address : 0X27 +* Bit Group Name: XOR +* Permission : RO +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_XOR_NO_OVERRUN =0x00, + LSM303AGR_ACC_XOR_OVERRUN =0x10, +} LSM303AGR_ACC_XOR_t; + +#define LSM303AGR_ACC_XOR_MASK 0x10 +mems_status_t LSM303AGR_ACC_R_XDataOverrun(void *handle, LSM303AGR_ACC_XOR_t *value); + +/******************************************************************************* +* Register : STATUS_REG2 +* Address : 0X27 +* Bit Group Name: YOR +* Permission : RO +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_YOR_NO_OVERRUN =0x00, + LSM303AGR_ACC_YOR_OVERRUN =0x20, +} LSM303AGR_ACC_YOR_t; + +#define LSM303AGR_ACC_YOR_MASK 0x20 +mems_status_t LSM303AGR_ACC_R_YDataOverrun(void *handle, LSM303AGR_ACC_YOR_t *value); + +/******************************************************************************* +* Register : STATUS_REG2 +* Address : 0X27 +* Bit Group Name: ZOR +* Permission : RO +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_ZOR_NO_OVERRUN =0x00, + LSM303AGR_ACC_ZOR_OVERRUN =0x40, +} LSM303AGR_ACC_ZOR_t; + +#define LSM303AGR_ACC_ZOR_MASK 0x40 +mems_status_t LSM303AGR_ACC_R_ZDataOverrun(void *handle, LSM303AGR_ACC_ZOR_t *value); + +/******************************************************************************* +* Register : STATUS_REG2 +* Address : 0X27 +* Bit Group Name: ZYXOR +* Permission : RO +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_ZYXOR_NO_OVERRUN =0x00, + LSM303AGR_ACC_ZYXOR_OVERRUN =0x80, +} LSM303AGR_ACC_ZYXOR_t; + +#define LSM303AGR_ACC_ZYXOR_MASK 0x80 +mems_status_t LSM303AGR_ACC_R_XYZDataOverrun(void *handle, LSM303AGR_ACC_ZYXOR_t *value); + +/******************************************************************************* +* Register : FIFO_CTRL_REG +* Address : 0X2E +* Bit Group Name: FTH +* Permission : RW +*******************************************************************************/ +#define LSM303AGR_ACC_FTH_MASK 0x1F +#define LSM303AGR_ACC_FTH_POSITION 0 +mems_status_t LSM303AGR_ACC_W_FifoThreshold(void *handle, u8_t newValue); +mems_status_t LSM303AGR_ACC_R_FifoThreshold(void *handle, u8_t *value); + +/******************************************************************************* +* Register : FIFO_CTRL_REG +* Address : 0X2E +* Bit Group Name: TR +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_TR_TRIGGER_ON_INT1 =0x00, + LSM303AGR_ACC_TR_TRIGGER_ON_INT2 =0x20, +} LSM303AGR_ACC_TR_t; + +#define LSM303AGR_ACC_TR_MASK 0x20 +mems_status_t LSM303AGR_ACC_W_TriggerSel(void *handle, LSM303AGR_ACC_TR_t newValue); +mems_status_t LSM303AGR_ACC_R_TriggerSel(void *handle, LSM303AGR_ACC_TR_t *value); + +/******************************************************************************* +* Register : FIFO_CTRL_REG +* Address : 0X2E +* Bit Group Name: FM +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_FM_BYPASS =0x00, + LSM303AGR_ACC_FM_FIFO =0x40, + LSM303AGR_ACC_FM_STREAM =0x80, + LSM303AGR_ACC_FM_TRIGGER =0xC0, +} LSM303AGR_ACC_FM_t; + +#define LSM303AGR_ACC_FM_MASK 0xC0 +mems_status_t LSM303AGR_ACC_W_FifoMode(void *handle, LSM303AGR_ACC_FM_t newValue); +mems_status_t LSM303AGR_ACC_R_FifoMode(void *handle, LSM303AGR_ACC_FM_t *value); + +/******************************************************************************* +* Register : FIFO_SRC_REG +* Address : 0X2F +* Bit Group Name: FSS +* Permission : RO +*******************************************************************************/ +#define LSM303AGR_ACC_FSS_MASK 0x1F +#define LSM303AGR_ACC_FSS_POSITION 0 +mems_status_t LSM303AGR_ACC_R_FifoSamplesAvail(void *handle, u8_t *value); + +/******************************************************************************* +* Register : FIFO_SRC_REG +* Address : 0X2F +* Bit Group Name: EMPTY +* Permission : RO +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_EMPTY_NOT_EMPTY =0x00, + LSM303AGR_ACC_EMPTY_EMPTY =0x20, +} LSM303AGR_ACC_EMPTY_t; + +#define LSM303AGR_ACC_EMPTY_MASK 0x20 +mems_status_t LSM303AGR_ACC_R_FifoEmpty(void *handle, LSM303AGR_ACC_EMPTY_t *value); + +/******************************************************************************* +* Register : FIFO_SRC_REG +* Address : 0X2F +* Bit Group Name: OVRN_FIFO +* Permission : RO +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_OVRN_FIFO_NO_OVERRUN =0x00, + LSM303AGR_ACC_OVRN_FIFO_OVERRUN =0x40, +} LSM303AGR_ACC_OVRN_FIFO_t; + +#define LSM303AGR_ACC_OVRN_FIFO_MASK 0x40 +mems_status_t LSM303AGR_ACC_R_FifoOverrun(void *handle, LSM303AGR_ACC_OVRN_FIFO_t *value); + +/******************************************************************************* +* Register : FIFO_SRC_REG +* Address : 0X2F +* Bit Group Name: WTM +* Permission : RO +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_WTM_NORMAL =0x00, + LSM303AGR_ACC_WTM_OVERFLOW =0x80, +} LSM303AGR_ACC_WTM_t; + +#define LSM303AGR_ACC_WTM_MASK 0x80 +mems_status_t LSM303AGR_ACC_R_WatermarkLevel(void *handle, LSM303AGR_ACC_WTM_t *value); + +/******************************************************************************* +* Register : INT1_CFG/INT2_CFG +* Address : 0X30/0x34 +* Bit Group Name: XLIE +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_XLIE_DISABLED =0x00, + LSM303AGR_ACC_XLIE_ENABLED =0x01, +} LSM303AGR_ACC_XLIE_t; + +#define LSM303AGR_ACC_XLIE_MASK 0x01 +mems_status_t LSM303AGR_ACC_W_Int1EnXLo(void *handle, LSM303AGR_ACC_XLIE_t newValue); +mems_status_t LSM303AGR_ACC_R_Int1EnXLo(void *handle, LSM303AGR_ACC_XLIE_t *value); +mems_status_t LSM303AGR_ACC_W_Int2EnXLo(void *handle, LSM303AGR_ACC_XLIE_t newValue); +mems_status_t LSM303AGR_ACC_R_Int2EnXLo(void *handle, LSM303AGR_ACC_XLIE_t *value); + +/******************************************************************************* +* Register : INT1_CFG/INT2_CFG +* Address : 0X30/0x34 +* Bit Group Name: XHIE +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_XHIE_DISABLED =0x00, + LSM303AGR_ACC_XHIE_ENABLED =0x02, +} LSM303AGR_ACC_XHIE_t; + +#define LSM303AGR_ACC_XHIE_MASK 0x02 +mems_status_t LSM303AGR_ACC_W_Int1EnXHi(void *handle, LSM303AGR_ACC_XHIE_t newValue); +mems_status_t LSM303AGR_ACC_R_Int1EnXHi(void *handle, LSM303AGR_ACC_XHIE_t *value); +mems_status_t LSM303AGR_ACC_W_Int2EnXHi(void *handle, LSM303AGR_ACC_XHIE_t newValue); +mems_status_t LSM303AGR_ACC_R_Int2EnXHi(void *handle, LSM303AGR_ACC_XHIE_t *value); + +/******************************************************************************* +* Register : INT1_CFG/INT2_CFG +* Address : 0X30/0x34 +* Bit Group Name: YLIE +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_YLIE_DISABLED =0x00, + LSM303AGR_ACC_YLIE_ENABLED =0x04, +} LSM303AGR_ACC_YLIE_t; + +#define LSM303AGR_ACC_YLIE_MASK 0x04 +mems_status_t LSM303AGR_ACC_W_Int1EnYLo(void *handle, LSM303AGR_ACC_YLIE_t newValue); +mems_status_t LSM303AGR_ACC_R_Int1EnYLo(void *handle, LSM303AGR_ACC_YLIE_t *value); +mems_status_t LSM303AGR_ACC_W_Int2EnYLo(void *handle, LSM303AGR_ACC_YLIE_t newValue); +mems_status_t LSM303AGR_ACC_R_Int2EnYLo(void *handle, LSM303AGR_ACC_YLIE_t *value); + +/******************************************************************************* +* Register : INT1_CFG/INT2_CFG +* Address : 0X30/0x34 +* Bit Group Name: YHIE +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_YHIE_DISABLED =0x00, + LSM303AGR_ACC_YHIE_ENABLED =0x08, +} LSM303AGR_ACC_YHIE_t; + +#define LSM303AGR_ACC_YHIE_MASK 0x08 +mems_status_t LSM303AGR_ACC_W_Int1EnYHi(void *handle, LSM303AGR_ACC_YHIE_t newValue); +mems_status_t LSM303AGR_ACC_R_Int1EnYHi(void *handle, LSM303AGR_ACC_YHIE_t *value); +mems_status_t LSM303AGR_ACC_W_Int2EnYHi(void *handle, LSM303AGR_ACC_YHIE_t newValue); +mems_status_t LSM303AGR_ACC_R_Int2EnYHi(void *handle, LSM303AGR_ACC_YHIE_t *value); + +/******************************************************************************* +* Register : INT1_CFG/INT2_CFG +* Address : 0X30/0x34 +* Bit Group Name: ZLIE +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_ZLIE_DISABLED =0x00, + LSM303AGR_ACC_ZLIE_ENABLED =0x10, +} LSM303AGR_ACC_ZLIE_t; + +#define LSM303AGR_ACC_ZLIE_MASK 0x10 +mems_status_t LSM303AGR_ACC_W_Int1EnZLo(void *handle, LSM303AGR_ACC_ZLIE_t newValue); +mems_status_t LSM303AGR_ACC_R_Int1EnZLo(void *handle, LSM303AGR_ACC_ZLIE_t *value); +mems_status_t LSM303AGR_ACC_W_Int2EnZLo(void *handle, LSM303AGR_ACC_ZLIE_t newValue); +mems_status_t LSM303AGR_ACC_R_Int2EnZLo(void *handle, LSM303AGR_ACC_ZLIE_t *value); + +/******************************************************************************* +* Register : INT1_CFG/INT2_CFG +* Address : 0X30/0x34 +* Bit Group Name: ZHIE +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_ZHIE_DISABLED =0x00, + LSM303AGR_ACC_ZHIE_ENABLED =0x20, +} LSM303AGR_ACC_ZHIE_t; + +#define LSM303AGR_ACC_ZHIE_MASK 0x20 +mems_status_t LSM303AGR_ACC_W_Int1EnZHi(void *handle, LSM303AGR_ACC_ZHIE_t newValue); +mems_status_t LSM303AGR_ACC_R_Int1EnZHi(void *handle, LSM303AGR_ACC_ZHIE_t *value); +mems_status_t LSM303AGR_ACC_W_Int2EnZHi(void *handle, LSM303AGR_ACC_ZHIE_t newValue); +mems_status_t LSM303AGR_ACC_R_Int2EnZHi(void *handle, LSM303AGR_ACC_ZHIE_t *value); + +/******************************************************************************* +* Register : INT1_CFG/INT2_CFG +* Address : 0X30/0x34 +* Bit Group Name: 6D +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_6D_DISABLED =0x00, + LSM303AGR_ACC_6D_ENABLED =0x40, +} LSM303AGR_ACC_6D_t; + +#define LSM303AGR_ACC_6D_MASK 0x40 +mems_status_t LSM303AGR_ACC_W_Int1_6D(void *handle, LSM303AGR_ACC_6D_t newValue); +mems_status_t LSM303AGR_ACC_R_Int1_6D(void *handle, LSM303AGR_ACC_6D_t *value); +mems_status_t LSM303AGR_ACC_W_Int2_6D(void *handle, LSM303AGR_ACC_6D_t newValue); +mems_status_t LSM303AGR_ACC_R_Int2_6D(void *handle, LSM303AGR_ACC_6D_t *value); + +/******************************************************************************* +* Register : INT1_CFG/INT2_CFG +* Address : 0X30/0x34 +* Bit Group Name: AOI +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_AOI_OR =0x00, + LSM303AGR_ACC_AOI_AND =0x80, +} LSM303AGR_ACC_AOI_t; + +#define LSM303AGR_ACC_AOI_MASK 0x80 +mems_status_t LSM303AGR_ACC_W_Int1_AOI(void *handle, LSM303AGR_ACC_AOI_t newValue); +mems_status_t LSM303AGR_ACC_R_Int1_AOI(void *handle, LSM303AGR_ACC_AOI_t *value); +mems_status_t LSM303AGR_ACC_W_Int2_AOI(void *handle, LSM303AGR_ACC_AOI_t newValue); +mems_status_t LSM303AGR_ACC_R_Int2_AOI(void *handle, LSM303AGR_ACC_AOI_t *value); + +/******************************************************************************* +* Register : INT1_SOURCE/INT2_SOURCE +* Address : 0X31/0x35 +* Bit Group Name: XL +* Permission : RO +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_XL_DOWN =0x00, + LSM303AGR_ACC_XL_UP =0x01, +} LSM303AGR_ACC_XL_t; + +#define LSM303AGR_ACC_XL_MASK 0x01 +mems_status_t LSM303AGR_ACC_R_Int1_Xlo(void *handle, LSM303AGR_ACC_XL_t *value); +mems_status_t LSM303AGR_ACC_R_Int2_Xlo(void *handle, LSM303AGR_ACC_XL_t *value); + +/******************************************************************************* +* Register : INT1_SOURCE/INT2_SOURCE +* Address : 0X31/0x35 +* Bit Group Name: XH +* Permission : RO +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_XH_DOWN =0x00, + LSM303AGR_ACC_XH_UP =0x02, +} LSM303AGR_ACC_XH_t; + +#define LSM303AGR_ACC_XH_MASK 0x02 +mems_status_t LSM303AGR_ACC_R_Int1_XHi(void *handle, LSM303AGR_ACC_XH_t *value); +mems_status_t LSM303AGR_ACC_R_Int2_XHi(void *handle, LSM303AGR_ACC_XH_t *value); + +/******************************************************************************* +* Register : INT1_SOURCE/INT2_SOURCE +* Address : 0X31/0x35 +* Bit Group Name: YL +* Permission : RO +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_YL_DOWN =0x00, + LSM303AGR_ACC_YL_UP =0x04, +} LSM303AGR_ACC_YL_t; + +#define LSM303AGR_ACC_YL_MASK 0x04 +mems_status_t LSM303AGR_ACC_R_Int1_YLo(void *handle, LSM303AGR_ACC_YL_t *value); +mems_status_t LSM303AGR_ACC_R_Int2_YLo(void *handle, LSM303AGR_ACC_YL_t *value); + +/******************************************************************************* +* Register : INT1_SOURCE/INT2_SOURCE +* Address : 0X31/0x35 +* Bit Group Name: YH +* Permission : RO +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_YH_DOWN =0x00, + LSM303AGR_ACC_YH_UP =0x08, +} LSM303AGR_ACC_YH_t; + +#define LSM303AGR_ACC_YH_MASK 0x08 +mems_status_t LSM303AGR_ACC_R_Int1_YHi(void *handle, LSM303AGR_ACC_YH_t *value); +mems_status_t LSM303AGR_ACC_R_Int2_YHi(void *handle, LSM303AGR_ACC_YH_t *value); + +/******************************************************************************* +* Register : INT1_SOURCE/INT2_SOURCE +* Address : 0X31/0x35 +* Bit Group Name: ZL +* Permission : RO +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_ZL_DOWN =0x00, + LSM303AGR_ACC_ZL_UP =0x10, +} LSM303AGR_ACC_ZL_t; + +#define LSM303AGR_ACC_ZL_MASK 0x10 +mems_status_t LSM303AGR_ACC_R_Int1_Zlo(void *handle, LSM303AGR_ACC_ZL_t *value); +mems_status_t LSM303AGR_ACC_R_Int2_Zlo(void *handle, LSM303AGR_ACC_ZL_t *value); + +/******************************************************************************* +* Register : INT1_SOURCE/INT2_SOURCE +* Address : 0X31/0x35 +* Bit Group Name: ZH +* Permission : RO +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_ZH_DOWN =0x00, + LSM303AGR_ACC_ZH_UP =0x20, +} LSM303AGR_ACC_ZH_t; + +#define LSM303AGR_ACC_ZH_MASK 0x20 +mems_status_t LSM303AGR_ACC_R_Int1_ZHi(void *handle, LSM303AGR_ACC_ZH_t *value); +mems_status_t LSM303AGR_ACC_R_Int2_ZHi(void *handle, LSM303AGR_ACC_ZH_t *value); + +/******************************************************************************* +* Register : INT1_SOURCE/INT2_SOURCE +* Address : 0X31/0x35 +* Bit Group Name: IA +* Permission : RO +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_IA_DOWN =0x00, + LSM303AGR_ACC_IA_UP =0x40, +} LSM303AGR_ACC_IA_t; + +#define LSM303AGR_ACC_IA_MASK 0x40 +mems_status_t LSM303AGR_ACC_R_Int1_IA(void *handle, LSM303AGR_ACC_IA_t *value); +mems_status_t LSM303AGR_ACC_R_Int2_IA(void *handle, LSM303AGR_ACC_IA_t *value); + +/******************************************************************************* +* Register : INT1_THS/INT2_THS +* Address : 0X32/0x36 +* Bit Group Name: THS +* Permission : RW +*******************************************************************************/ +#define LSM303AGR_ACC_THS_MASK 0x7F +#define LSM303AGR_ACC_THS_POSITION 0 +mems_status_t LSM303AGR_ACC_W_Int1_Threshold(void *handle, u8_t newValue); +mems_status_t LSM303AGR_ACC_R_Int1_Threshold(void *handle, u8_t *value); +mems_status_t LSM303AGR_ACC_W_Int2_Threshold(void *handle, u8_t newValue); +mems_status_t LSM303AGR_ACC_R_Int2_Threshold(void *handle, u8_t *value); + +/******************************************************************************* +* Register : INT1_DURATION/INT2_DURATION +* Address : 0X33/0x37 +* Bit Group Name: D +* Permission : RW +*******************************************************************************/ +#define LSM303AGR_ACC_D_MASK 0x7F +#define LSM303AGR_ACC_D_POSITION 0 +mems_status_t LSM303AGR_ACC_W_Int1_Duration(void *handle, u8_t newValue); +mems_status_t LSM303AGR_ACC_R_Int1_Duration(void *handle, u8_t *value); +mems_status_t LSM303AGR_ACC_W_Int2_Duration(void *handle, u8_t newValue); +mems_status_t LSM303AGR_ACC_R_Int2_Duration(void *handle, u8_t *value); + +/******************************************************************************* +* Register : CLICK_CFG +* Address : 0X38 +* Bit Group Name: XS +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_XS_DISABLED =0x00, + LSM303AGR_ACC_XS_ENABLED =0x01, +} LSM303AGR_ACC_XS_t; + +#define LSM303AGR_ACC_XS_MASK 0x01 +mems_status_t LSM303AGR_ACC_W_XSingle(void *handle, LSM303AGR_ACC_XS_t newValue); +mems_status_t LSM303AGR_ACC_R_XSingle(void *handle, LSM303AGR_ACC_XS_t *value); + +/******************************************************************************* +* Register : CLICK_CFG +* Address : 0X38 +* Bit Group Name: XD +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_XD_DISABLED =0x00, + LSM303AGR_ACC_XD_ENABLED =0x02, +} LSM303AGR_ACC_XD_t; + +#define LSM303AGR_ACC_XD_MASK 0x02 +mems_status_t LSM303AGR_ACC_W_XDouble(void *handle, LSM303AGR_ACC_XD_t newValue); +mems_status_t LSM303AGR_ACC_R_XDouble(void *handle, LSM303AGR_ACC_XD_t *value); + +/******************************************************************************* +* Register : CLICK_CFG +* Address : 0X38 +* Bit Group Name: YS +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_YS_DISABLED =0x00, + LSM303AGR_ACC_YS_ENABLED =0x04, +} LSM303AGR_ACC_YS_t; + +#define LSM303AGR_ACC_YS_MASK 0x04 +mems_status_t LSM303AGR_ACC_W_YSingle(void *handle, LSM303AGR_ACC_YS_t newValue); +mems_status_t LSM303AGR_ACC_R_YSingle(void *handle, LSM303AGR_ACC_YS_t *value); + +/******************************************************************************* +* Register : CLICK_CFG +* Address : 0X38 +* Bit Group Name: YD +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_YD_DISABLED =0x00, + LSM303AGR_ACC_YD_ENABLED =0x08, +} LSM303AGR_ACC_YD_t; + +#define LSM303AGR_ACC_YD_MASK 0x08 +mems_status_t LSM303AGR_ACC_W_YDouble(void *handle, LSM303AGR_ACC_YD_t newValue); +mems_status_t LSM303AGR_ACC_R_YDouble(void *handle, LSM303AGR_ACC_YD_t *value); + +/******************************************************************************* +* Register : CLICK_CFG +* Address : 0X38 +* Bit Group Name: ZS +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_ZS_DISABLED =0x00, + LSM303AGR_ACC_ZS_ENABLED =0x10, +} LSM303AGR_ACC_ZS_t; + +#define LSM303AGR_ACC_ZS_MASK 0x10 +mems_status_t LSM303AGR_ACC_W_ZSingle(void *handle, LSM303AGR_ACC_ZS_t newValue); +mems_status_t LSM303AGR_ACC_R_ZSingle(void *handle, LSM303AGR_ACC_ZS_t *value); + +/******************************************************************************* +* Register : CLICK_CFG +* Address : 0X38 +* Bit Group Name: ZD +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_ZD_DISABLED =0x00, + LSM303AGR_ACC_ZD_ENABLED =0x20, +} LSM303AGR_ACC_ZD_t; + +#define LSM303AGR_ACC_ZD_MASK 0x20 +mems_status_t LSM303AGR_ACC_W_ZDouble(void *handle, LSM303AGR_ACC_ZD_t newValue); +mems_status_t LSM303AGR_ACC_R_ZDouble(void *handle, LSM303AGR_ACC_ZD_t *value); + +/******************************************************************************* +* Register : CLICK_SRC +* Address : 0X39 +* Bit Group Name: X +* Permission : RO +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_X_DOWN =0x00, + LSM303AGR_ACC_X_UP =0x01, +} LSM303AGR_ACC_X_t; + +#define LSM303AGR_ACC_X_MASK 0x01 +mems_status_t LSM303AGR_ACC_R_ClickX(void *handle, LSM303AGR_ACC_X_t *value); + +/******************************************************************************* +* Register : CLICK_SRC +* Address : 0X39 +* Bit Group Name: Y +* Permission : RO +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_Y_DOWN =0x00, + LSM303AGR_ACC_Y_UP =0x02, +} LSM303AGR_ACC_Y_t; + +#define LSM303AGR_ACC_Y_MASK 0x02 +mems_status_t LSM303AGR_ACC_R_ClickY(void *handle, LSM303AGR_ACC_Y_t *value); + +/******************************************************************************* +* Register : CLICK_SRC +* Address : 0X39 +* Bit Group Name: Z +* Permission : RO +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_Z_DOWN =0x00, + LSM303AGR_ACC_Z_UP =0x04, +} LSM303AGR_ACC_Z_t; + +#define LSM303AGR_ACC_Z_MASK 0x04 +mems_status_t LSM303AGR_ACC_R_ClickZ(void *handle, LSM303AGR_ACC_Z_t *value); + +/******************************************************************************* +* Register : CLICK_SRC +* Address : 0X39 +* Bit Group Name: SIGN +* Permission : RO +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_SIGN_POSITIVE =0x00, + LSM303AGR_ACC_SIGN_NEGATIVE =0x08, +} LSM303AGR_ACC_SIGN_t; + +#define LSM303AGR_ACC_SIGN_MASK 0x08 +mems_status_t LSM303AGR_ACC_R_ClickSign(void *handle, LSM303AGR_ACC_SIGN_t *value); + +/******************************************************************************* +* Register : CLICK_SRC +* Address : 0X39 +* Bit Group Name: SCLICK +* Permission : RO +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_SCLICK_DISABLED =0x00, + LSM303AGR_ACC_SCLICK_ENABLED =0x10, +} LSM303AGR_ACC_SCLICK_t; + +#define LSM303AGR_ACC_SCLICK_MASK 0x10 +mems_status_t LSM303AGR_ACC_R_SingleCLICK(void *handle, LSM303AGR_ACC_SCLICK_t *value); + +/******************************************************************************* +* Register : CLICK_SRC +* Address : 0X39 +* Bit Group Name: DCLICK +* Permission : RO +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_DCLICK_DISABLED =0x00, + LSM303AGR_ACC_DCLICK_ENABLED =0x20, +} LSM303AGR_ACC_DCLICK_t; + +#define LSM303AGR_ACC_DCLICK_MASK 0x20 +mems_status_t LSM303AGR_ACC_R_DoubleCLICK(void *handle, LSM303AGR_ACC_DCLICK_t *value); + +/******************************************************************************* +* Register : CLICK_SRC +* Address : 0X39 +* Bit Group Name: IA +* Permission : RO +*******************************************************************************/ +typedef enum { + LSM303AGR_ACC_CLICK_IA_DOWN =0x00, + LSM303AGR_ACC_CLICK_IA_UP =0x40, +} LSM303AGR_ACC_CLICK_IA_t; + +#define LSM303AGR_ACC_IA_MASK 0x40 +mems_status_t LSM303AGR_ACC_R_CLICK_IA(void *handle, LSM303AGR_ACC_CLICK_IA_t *value); + +/******************************************************************************* +* Register : CLICK_THS +* Address : 0X3A +* Bit Group Name: THS +* Permission : RW +*******************************************************************************/ +#define LSM303AGR_ACC_THS_MASK 0x7F +#define LSM303AGR_ACC_THS_POSITION 0 +mems_status_t LSM303AGR_ACC_W_ClickThreshold(void *handle, u8_t newValue); +mems_status_t LSM303AGR_ACC_R_ClickThreshold(void *handle, u8_t *value); + +/******************************************************************************* +* Register : TIME_LIMIT +* Address : 0X3B +* Bit Group Name: TLI +* Permission : RW +*******************************************************************************/ +#define LSM303AGR_ACC_TLI_MASK 0x7F +#define LSM303AGR_ACC_TLI_POSITION 0 +mems_status_t LSM303AGR_ACC_W_ClickTimeLimit(void *handle, u8_t newValue); +mems_status_t LSM303AGR_ACC_R_ClickTimeLimit(void *handle, u8_t *value); + +/******************************************************************************* +* Register : TIME_LATENCY +* Address : 0X3C +* Bit Group Name: TLA +* Permission : RW +*******************************************************************************/ +#define LSM303AGR_ACC_TLA_MASK 0xFF +#define LSM303AGR_ACC_TLA_POSITION 0 +mems_status_t LSM303AGR_ACC_W_ClickTimeLatency(void *handle, u8_t newValue); +mems_status_t LSM303AGR_ACC_R_ClickTimeLatency(void *handle, u8_t *value); + +/******************************************************************************* +* Register : TIME_WINDOW +* Address : 0X3D +* Bit Group Name: TW +* Permission : RW +*******************************************************************************/ +#define LSM303AGR_ACC_TW_MASK 0xFF +#define LSM303AGR_ACC_TW_POSITION 0 +mems_status_t LSM303AGR_ACC_W_ClickTimeWindow(void *handle, u8_t newValue); +mems_status_t LSM303AGR_ACC_R_ClickTimeWindow(void *handle, u8_t *value); +/******************************************************************************* +* Register : - +* Output Type : Voltage_ADC +* Permission : RO +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_Get_Voltage_ADC(void *handle, u8_t *buff); +/******************************************************************************* +* Register : - +* Output Type : Acceleration +* Permission : RO +*******************************************************************************/ +mems_status_t LSM303AGR_ACC_Get_Raw_Acceleration(void *handle, u8_t *buff); +mems_status_t LSM303AGR_ACC_Get_Acceleration(void *handle, int *buff); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/LSM303AGR/LSM303AGR_mag_driver.c b/LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/LSM303AGR/LSM303AGR_mag_driver.c new file mode 100644 index 0000000..9fbdd84 --- /dev/null +++ b/LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/LSM303AGR/LSM303AGR_mag_driver.c @@ -0,0 +1,1639 @@ +/** + ******************************************************************************* + * @file LSM303AGR_mag_driver.c + * @author MEMS Application Team + * @version V1.1 + * @date 25-February-2016 + * @brief LSM303AGR Magnetometer driver file + ******************************************************************************* + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "LSM303AGR_mag_driver.h" + +/* Imported function prototypes ----------------------------------------------*/ +extern uint8_t LSM303AGR_MAG_io_write(void *handle, uint8_t WriteAddr, uint8_t *pBuffer, uint16_t nBytesToWrite); +extern uint8_t LSM303AGR_MAG_io_read(void *handle, uint8_t ReadAddr, uint8_t *pBuffer, uint16_t nBytesToRead); + +/* Private typedef -----------------------------------------------------------*/ + +/* Private define ------------------------------------------------------------*/ + +/* Private macro -------------------------------------------------------------*/ + +/* Private variables ---------------------------------------------------------*/ + +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : LSM303AGR_MAG_read_reg +* Description : Generic Reading function. It must be fullfilled with either +* : I2C or SPI reading functions +* Input : Register Address +* Output : Data REad +* Return : None +*******************************************************************************/ +mems_status_t LSM303AGR_MAG_read_reg( void *handle, u8_t Reg, u8_t* Data ) +{ + + if (LSM303AGR_MAG_io_read(handle, Reg, Data, 1)) + { + return MEMS_ERROR; + } + else + { + return MEMS_SUCCESS; + } +} + +/******************************************************************************* +* Function Name : LSM303AGR_MAG_write_reg +* Description : Generic Writing function. It must be fullfilled with either +* : I2C or SPI writing function +* Input : Register Address, Data to be written +* Output : None +* Return : None +*******************************************************************************/ +mems_status_t LSM303AGR_MAG_write_reg( void *handle, u8_t Reg, u8_t Data ) +{ + + if (LSM303AGR_MAG_io_write(handle, Reg, &Data, 1)) + { + return MEMS_ERROR; + } + else + { + return MEMS_SUCCESS; + } +} + +/******************************************************************************* +* Function Name : SwapHighLowByte +* Description : Swap High/low byte in multiple byte values +* It works with minimum 2 byte for every dimension. +* Example x,y,z with 2 byte for every dimension +* +* Input : bufferToSwap -> buffer to swap +* numberOfByte -> the buffer length in byte +* dimension -> number of dimension +* +* Output : bufferToSwap -> buffer swapped +* Return : None +*******************************************************************************/ +void LSM303AGR_MAG_SwapHighLowByte(u8_t *bufferToSwap, u8_t numberOfByte, u8_t dimension) +{ + + u8_t numberOfByteForDimension, i, j; + u8_t tempValue[10]; + + numberOfByteForDimension=numberOfByte/dimension; + + for (i=0; i> LSM303AGR_MAG_OFF_X_L_POSITION; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_MAG_W_OFF_X_H +* Description : Write OFF_X_H +* Input : u8_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_MAG_W_OFF_X_H(void *handle, u8_t newValue) +{ + u8_t value; + + newValue = newValue << LSM303AGR_MAG_OFF_X_H_POSITION; //mask + newValue &= LSM303AGR_MAG_OFF_X_H_MASK; //coerce + + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_OFFSET_X_REG_H, &value) ) + return MEMS_ERROR; + + value &= (u8_t)~LSM303AGR_MAG_OFF_X_H_MASK; + value |= newValue; + + if( !LSM303AGR_MAG_write_reg(handle, LSM303AGR_MAG_OFFSET_X_REG_H, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_MAG_R_OFF_X_H +* Description : Read OFF_X_H +* Input : Pointer to u8_t +* Output : Status of OFF_X_H +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_MAG_R_OFF_X_H(void *handle, u8_t *value) +{ + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_OFFSET_X_REG_H, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_MAG_OFF_X_H_MASK; //coerce + *value = *value >> LSM303AGR_MAG_OFF_X_H_POSITION; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_MAG_W_OFF_Y_L +* Description : Write OFF_Y_L +* Input : u8_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_MAG_W_OFF_Y_L(void *handle, u8_t newValue) +{ + u8_t value; + + newValue = newValue << LSM303AGR_MAG_OFF_Y_L_POSITION; //mask + newValue &= LSM303AGR_MAG_OFF_Y_L_MASK; //coerce + + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_OFFSET_Y_REG_L, &value) ) + return MEMS_ERROR; + + value &= (u8_t)~LSM303AGR_MAG_OFF_Y_L_MASK; + value |= newValue; + + if( !LSM303AGR_MAG_write_reg(handle, LSM303AGR_MAG_OFFSET_Y_REG_L, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_MAG_R_OFF_Y_L +* Description : Read OFF_Y_L +* Input : Pointer to u8_t +* Output : Status of OFF_Y_L +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_MAG_R_OFF_Y_L(void *handle, u8_t *value) +{ + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_OFFSET_Y_REG_L, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_MAG_OFF_Y_L_MASK; //coerce + *value = *value >> LSM303AGR_MAG_OFF_Y_L_POSITION; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_MAG_W_OFF_Y_H +* Description : Write OFF_Y_H +* Input : u8_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_MAG_W_OFF_Y_H(void *handle, u8_t newValue) +{ + u8_t value; + + newValue = newValue << LSM303AGR_MAG_OFF_Y_H_POSITION; //mask + newValue &= LSM303AGR_MAG_OFF_Y_H_MASK; //coerce + + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_OFFSET_Y_REG_H, &value) ) + return MEMS_ERROR; + + value &= (u8_t)~LSM303AGR_MAG_OFF_Y_H_MASK; + value |= newValue; + + if( !LSM303AGR_MAG_write_reg(handle, LSM303AGR_MAG_OFFSET_Y_REG_H, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_MAG_R_OFF_Y_H +* Description : Read OFF_Y_H +* Input : Pointer to u8_t +* Output : Status of OFF_Y_H +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_MAG_R_OFF_Y_H(void *handle, u8_t *value) +{ + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_OFFSET_Y_REG_H, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_MAG_OFF_Y_H_MASK; //coerce + *value = *value >> LSM303AGR_MAG_OFF_Y_H_POSITION; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_MAG_W_OFF_Z_L +* Description : Write OFF_Z_L +* Input : u8_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_MAG_W_OFF_Z_L(void *handle, u8_t newValue) +{ + u8_t value; + + newValue = newValue << LSM303AGR_MAG_OFF_Z_L_POSITION; //mask + newValue &= LSM303AGR_MAG_OFF_Z_L_MASK; //coerce + + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_OFFSET_Z_REG_L, &value) ) + return MEMS_ERROR; + + value &= (u8_t)~LSM303AGR_MAG_OFF_Z_L_MASK; + value |= newValue; + + if( !LSM303AGR_MAG_write_reg(handle, LSM303AGR_MAG_OFFSET_Z_REG_L, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_MAG_R_OFF_Z_L +* Description : Read OFF_Z_L +* Input : Pointer to u8_t +* Output : Status of OFF_Z_L +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_MAG_R_OFF_Z_L(void *handle, u8_t *value) +{ + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_OFFSET_Z_REG_L, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_MAG_OFF_Z_L_MASK; //coerce + *value = *value >> LSM303AGR_MAG_OFF_Z_L_POSITION; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_MAG_W_OFF_Z_H +* Description : Write OFF_Z_H +* Input : u8_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_MAG_W_OFF_Z_H(void *handle, u8_t newValue) +{ + u8_t value; + + newValue = newValue << LSM303AGR_MAG_OFF_Z_H_POSITION; //mask + newValue &= LSM303AGR_MAG_OFF_Z_H_MASK; //coerce + + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_OFFSET_Z_REG_H, &value) ) + return MEMS_ERROR; + + value &= (u8_t)~LSM303AGR_MAG_OFF_Z_H_MASK; + value |= newValue; + + if( !LSM303AGR_MAG_write_reg(handle, LSM303AGR_MAG_OFFSET_Z_REG_H, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* + * Set/Get the Magnetic offsets +*******************************************************************************/ +mems_status_t LSM303AGR_MAG_Get_MagOff(void *handle, u16_t *magx_off, u16_t *magy_off, u16_t *magz_off) +{ + u8_t reg_l, reg_h; + + /* read mag_x_off */ + //LSM303AGR_MAG_R_OFF_X_L(®_l); + //LSM303AGR_MAG_R_OFF_X_H(®_h); + LSM303AGR_MAG_R_OFF_X_L(handle, ®_l); + LSM303AGR_MAG_R_OFF_X_H(handle, ®_h); + *magx_off = ((reg_h << 8) & 0xff00) | reg_l; + + /* read mag_y_off */ + //LSM303AGR_MAG_R_OFF_Y_L(®_l); + //LSM303AGR_MAG_R_OFF_Y_H(®_h); + LSM303AGR_MAG_R_OFF_Y_L(handle, ®_l); + LSM303AGR_MAG_R_OFF_Y_H(handle, ®_h); + *magy_off = ((reg_h << 8) & 0xff00) | reg_l; + + /* read mag_z_off */ + //LSM303AGR_MAG_R_OFF_Z_L(®_l); + //LSM303AGR_MAG_R_OFF_Z_H(®_h); + LSM303AGR_MAG_R_OFF_Z_L(handle, ®_l); + LSM303AGR_MAG_R_OFF_Z_H(handle, ®_h); + *magz_off = ((reg_h << 8) & 0xff00) | reg_l; + + return MEMS_SUCCESS; +} + +mems_status_t LSM303AGR_MAG_Set_MagOff(void *handle, u16_t magx_off, u16_t magy_off, u16_t magz_off) +{ + /* write mag_x_off */ + //LSM303AGR_MAG_W_OFF_X_L(magx_off & 0xff); + //LSM303AGR_MAG_W_OFF_X_H((magx_off >> 8) & 0xff); + LSM303AGR_MAG_W_OFF_X_L(handle, magx_off & 0xff); + LSM303AGR_MAG_W_OFF_X_H(handle, (magx_off >> 8) & 0xff); + + /* write mag_y_off */ + //LSM303AGR_MAG_W_OFF_Y_L(magy_off & 0xff); + //LSM303AGR_MAG_W_OFF_Y_H((magy_off >> 8) & 0xff); + LSM303AGR_MAG_W_OFF_Y_L(handle, magy_off & 0xff); + LSM303AGR_MAG_W_OFF_Y_H(handle, (magy_off >> 8) & 0xff); + + /* write mag_z_off */ + //LSM303AGR_MAG_W_OFF_Z_L(magz_off & 0xff); + //LSM303AGR_MAG_W_OFF_Z_H((magz_off >> 8) & 0xff); + LSM303AGR_MAG_W_OFF_Z_L(handle, magz_off & 0xff); + LSM303AGR_MAG_W_OFF_Z_H(handle, (magz_off >> 8) & 0xff); + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_MAG_R_OFF_Z_H +* Description : Read OFF_Z_H +* Input : Pointer to u8_t +* Output : Status of OFF_Z_H +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_MAG_R_OFF_Z_H(void *handle, u8_t *value) +{ + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_OFFSET_Z_REG_H, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_MAG_OFF_Z_H_MASK; //coerce + *value = *value >> LSM303AGR_MAG_OFF_Z_H_POSITION; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_MAG_R_WHO_AM_I +* Description : Read WHO_AM_I +* Input : Pointer to u8_t +* Output : Status of WHO_AM_I +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_MAG_R_WHO_AM_I(void *handle, u8_t *value) +{ + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_WHO_AM_I_REG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_MAG_WHO_AM_I_MASK; //coerce + *value = *value >> LSM303AGR_MAG_WHO_AM_I_POSITION; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_MAG_W_MD +* Description : Write MD +* Input : LSM303AGR_MAG_MD_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_MAG_W_MD(void *handle, LSM303AGR_MAG_MD_t newValue) +{ + u8_t value; + + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_CFG_REG_A, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_MAG_MD_MASK; + value |= newValue; + + if( !LSM303AGR_MAG_write_reg(handle, LSM303AGR_MAG_CFG_REG_A, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_MAG_R_MD +* Description : Read MD +* Input : Pointer to LSM303AGR_MAG_MD_t +* Output : Status of MD see LSM303AGR_MAG_MD_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_MAG_R_MD(void *handle, LSM303AGR_MAG_MD_t *value) +{ + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_CFG_REG_A, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_MAG_MD_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_MAG_W_ODR +* Description : Write ODR +* Input : LSM303AGR_MAG_ODR_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_MAG_W_ODR(void *handle, LSM303AGR_MAG_ODR_t newValue) +{ + u8_t value; + + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_CFG_REG_A, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_MAG_ODR_MASK; + value |= newValue; + + if( !LSM303AGR_MAG_write_reg(handle, LSM303AGR_MAG_CFG_REG_A, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_MAG_R_ODR +* Description : Read ODR +* Input : Pointer to LSM303AGR_MAG_ODR_t +* Output : Status of ODR see LSM303AGR_MAG_ODR_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_MAG_R_ODR(void *handle, LSM303AGR_MAG_ODR_t *value) +{ + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_CFG_REG_A, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_MAG_ODR_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_MAG_W_LP +* Description : Write LP +* Input : LSM303AGR_MAG_LP_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_MAG_W_LP(void *handle, LSM303AGR_MAG_LP_t newValue) +{ + u8_t value; + + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_CFG_REG_A, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_MAG_LP_MASK; + value |= newValue; + + if( !LSM303AGR_MAG_write_reg(handle, LSM303AGR_MAG_CFG_REG_A, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_MAG_R_LP +* Description : Read LP +* Input : Pointer to LSM303AGR_MAG_LP_t +* Output : Status of LP see LSM303AGR_MAG_LP_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_MAG_R_LP(void *handle, LSM303AGR_MAG_LP_t *value) +{ + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_CFG_REG_A, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_MAG_LP_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_MAG_W_SOFT_RST +* Description : Write SOFT_RST +* Input : LSM303AGR_MAG_SOFT_RST_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_MAG_W_SOFT_RST(void *handle, LSM303AGR_MAG_SOFT_RST_t newValue) +{ + u8_t value; + + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_CFG_REG_A, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_MAG_SOFT_RST_MASK; + value |= newValue; + + if( !LSM303AGR_MAG_write_reg(handle, LSM303AGR_MAG_CFG_REG_A, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_MAG_R_SOFT_RST +* Description : Read SOFT_RST +* Input : Pointer to LSM303AGR_MAG_SOFT_RST_t +* Output : Status of SOFT_RST see LSM303AGR_MAG_SOFT_RST_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_MAG_R_SOFT_RST(void *handle, LSM303AGR_MAG_SOFT_RST_t *value) +{ + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_CFG_REG_A, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_MAG_SOFT_RST_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_MAG_W_LPF +* Description : Write LPF +* Input : LSM303AGR_MAG_LPF_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_MAG_W_LPF(void *handle, LSM303AGR_MAG_LPF_t newValue) +{ + u8_t value; + + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_CFG_REG_B, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_MAG_LPF_MASK; + value |= newValue; + + if( !LSM303AGR_MAG_write_reg(handle, LSM303AGR_MAG_CFG_REG_B, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_MAG_R_LPF +* Description : Read LPF +* Input : Pointer to LSM303AGR_MAG_LPF_t +* Output : Status of LPF see LSM303AGR_MAG_LPF_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_MAG_R_LPF(void *handle, LSM303AGR_MAG_LPF_t *value) +{ + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_CFG_REG_B, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_MAG_LPF_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_MAG_W_OFF_CANC +* Description : Write OFF_CANC +* Input : LSM303AGR_MAG_OFF_CANC_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_MAG_W_OFF_CANC(void *handle, LSM303AGR_MAG_OFF_CANC_t newValue) +{ + u8_t value; + + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_CFG_REG_B, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_MAG_OFF_CANC_MASK; + value |= newValue; + + if( !LSM303AGR_MAG_write_reg(handle, LSM303AGR_MAG_CFG_REG_B, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_MAG_R_OFF_CANC +* Description : Read OFF_CANC +* Input : Pointer to LSM303AGR_MAG_OFF_CANC_t +* Output : Status of OFF_CANC see LSM303AGR_MAG_OFF_CANC_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_MAG_R_OFF_CANC(void *handle, LSM303AGR_MAG_OFF_CANC_t *value) +{ + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_CFG_REG_B, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_MAG_OFF_CANC_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_MAG_W_SET_FREQ +* Description : Write SET_FREQ +* Input : LSM303AGR_MAG_SET_FREQ_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_MAG_W_SET_FREQ(void *handle, LSM303AGR_MAG_SET_FREQ_t newValue) +{ + u8_t value; + + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_CFG_REG_B, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_MAG_SET_FREQ_MASK; + value |= newValue; + + if( !LSM303AGR_MAG_write_reg(handle, LSM303AGR_MAG_CFG_REG_B, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_MAG_R_SET_FREQ +* Description : Read SET_FREQ +* Input : Pointer to LSM303AGR_MAG_SET_FREQ_t +* Output : Status of SET_FREQ see LSM303AGR_MAG_SET_FREQ_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_MAG_R_SET_FREQ(void *handle, LSM303AGR_MAG_SET_FREQ_t *value) +{ + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_CFG_REG_B, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_MAG_SET_FREQ_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_MAG_W_INT_ON_DATAOFF +* Description : Write INT_ON_DATAOFF +* Input : LSM303AGR_MAG_INT_ON_DATAOFF_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_MAG_W_INT_ON_DATAOFF(void *handle, LSM303AGR_MAG_INT_ON_DATAOFF_t newValue) +{ + u8_t value; + + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_CFG_REG_B, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_MAG_INT_ON_DATAOFF_MASK; + value |= newValue; + + if( !LSM303AGR_MAG_write_reg(handle, LSM303AGR_MAG_CFG_REG_B, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_MAG_R_INT_ON_DATAOFF +* Description : Read INT_ON_DATAOFF +* Input : Pointer to LSM303AGR_MAG_INT_ON_DATAOFF_t +* Output : Status of INT_ON_DATAOFF see LSM303AGR_MAG_INT_ON_DATAOFF_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_MAG_R_INT_ON_DATAOFF(void *handle, LSM303AGR_MAG_INT_ON_DATAOFF_t *value) +{ + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_CFG_REG_B, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_MAG_INT_ON_DATAOFF_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_MAG_W_INT_MAG +* Description : Write INT_MAG +* Input : LSM303AGR_MAG_INT_MAG_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_MAG_W_INT_MAG(void *handle, LSM303AGR_MAG_INT_MAG_t newValue) +{ + u8_t value; + + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_CFG_REG_C, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_MAG_INT_MAG_MASK; + value |= newValue; + + if( !LSM303AGR_MAG_write_reg(handle, LSM303AGR_MAG_CFG_REG_C, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_MAG_R_INT_MAG +* Description : Read INT_MAG +* Input : Pointer to LSM303AGR_MAG_INT_MAG_t +* Output : Status of INT_MAG see LSM303AGR_MAG_INT_MAG_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_MAG_R_INT_MAG(void *handle, LSM303AGR_MAG_INT_MAG_t *value) +{ + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_CFG_REG_C, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_MAG_INT_MAG_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_MAG_W_ST +* Description : Write ST +* Input : LSM303AGR_MAG_ST_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_MAG_W_ST(void *handle, LSM303AGR_MAG_ST_t newValue) +{ + u8_t value; + + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_CFG_REG_C, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_MAG_ST_MASK; + value |= newValue; + + if( !LSM303AGR_MAG_write_reg(handle, LSM303AGR_MAG_CFG_REG_C, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_MAG_R_ST +* Description : Read ST +* Input : Pointer to LSM303AGR_MAG_ST_t +* Output : Status of ST see LSM303AGR_MAG_ST_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_MAG_R_ST(void *handle, LSM303AGR_MAG_ST_t *value) +{ + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_CFG_REG_C, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_MAG_ST_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_MAG_W_BLE +* Description : Write BLE +* Input : LSM303AGR_MAG_BLE_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_MAG_W_BLE(void *handle, LSM303AGR_MAG_BLE_t newValue) +{ + u8_t value; + + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_CFG_REG_C, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_MAG_BLE_MASK; + value |= newValue; + + if( !LSM303AGR_MAG_write_reg(handle, LSM303AGR_MAG_CFG_REG_C, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_MAG_R_BLE +* Description : Read BLE +* Input : Pointer to LSM303AGR_MAG_BLE_t +* Output : Status of BLE see LSM303AGR_MAG_BLE_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_MAG_R_BLE(void *handle, LSM303AGR_MAG_BLE_t *value) +{ + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_CFG_REG_C, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_MAG_BLE_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_MAG_W_BDU +* Description : Write BDU +* Input : LSM303AGR_MAG_BDU_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_MAG_W_BDU(void *handle, LSM303AGR_MAG_BDU_t newValue) +{ + u8_t value; + + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_CFG_REG_C, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_MAG_BDU_MASK; + value |= newValue; + + if( !LSM303AGR_MAG_write_reg(handle, LSM303AGR_MAG_CFG_REG_C, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_MAG_R_BDU +* Description : Read BDU +* Input : Pointer to LSM303AGR_MAG_BDU_t +* Output : Status of BDU see LSM303AGR_MAG_BDU_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_MAG_R_BDU(void *handle, LSM303AGR_MAG_BDU_t *value) +{ + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_CFG_REG_C, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_MAG_BDU_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_MAG_W_I2C_DIS +* Description : Write I2C_DIS +* Input : LSM303AGR_MAG_I2C_DIS_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_MAG_W_I2C_DIS(void *handle, LSM303AGR_MAG_I2C_DIS_t newValue) +{ + u8_t value; + + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_CFG_REG_C, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_MAG_I2C_DIS_MASK; + value |= newValue; + + if( !LSM303AGR_MAG_write_reg(handle, LSM303AGR_MAG_CFG_REG_C, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_MAG_R_I2C_DIS +* Description : Read I2C_DIS +* Input : Pointer to LSM303AGR_MAG_I2C_DIS_t +* Output : Status of I2C_DIS see LSM303AGR_MAG_I2C_DIS_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_MAG_R_I2C_DIS(void *handle, LSM303AGR_MAG_I2C_DIS_t *value) +{ + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_CFG_REG_C, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_MAG_I2C_DIS_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_MAG_W_INT_MAG_PIN +* Description : Write INT_MAG_PIN +* Input : LSM303AGR_MAG_INT_MAG_PIN_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_MAG_W_INT_MAG_PIN(void *handle, LSM303AGR_MAG_INT_MAG_PIN_t newValue) +{ + u8_t value; + + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_CFG_REG_C, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_MAG_INT_MAG_PIN_MASK; + value |= newValue; + + if( !LSM303AGR_MAG_write_reg(handle, LSM303AGR_MAG_CFG_REG_C, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_MAG_R_INT_MAG_PIN +* Description : Read INT_MAG_PIN +* Input : Pointer to LSM303AGR_MAG_INT_MAG_PIN_t +* Output : Status of INT_MAG_PIN see LSM303AGR_MAG_INT_MAG_PIN_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_MAG_R_INT_MAG_PIN(void *handle, LSM303AGR_MAG_INT_MAG_PIN_t *value) +{ + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_CFG_REG_C, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_MAG_INT_MAG_PIN_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_MAG_W_IEN +* Description : Write IEN +* Input : LSM303AGR_MAG_IEN_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_MAG_W_IEN(void *handle, LSM303AGR_MAG_IEN_t newValue) +{ + u8_t value; + + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_INT_CTRL_REG, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_MAG_IEN_MASK; + value |= newValue; + + if( !LSM303AGR_MAG_write_reg(handle, LSM303AGR_MAG_INT_CTRL_REG, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_MAG_R_IEN +* Description : Read IEN +* Input : Pointer to LSM303AGR_MAG_IEN_t +* Output : Status of IEN see LSM303AGR_MAG_IEN_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_MAG_R_IEN(void *handle, LSM303AGR_MAG_IEN_t *value) +{ + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_INT_CTRL_REG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_MAG_IEN_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_MAG_W_IEL +* Description : Write IEL +* Input : LSM303AGR_MAG_IEL_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_MAG_W_IEL(void *handle, LSM303AGR_MAG_IEL_t newValue) +{ + u8_t value; + + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_INT_CTRL_REG, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_MAG_IEL_MASK; + value |= newValue; + + if( !LSM303AGR_MAG_write_reg(handle, LSM303AGR_MAG_INT_CTRL_REG, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_MAG_R_IEL +* Description : Read IEL +* Input : Pointer to LSM303AGR_MAG_IEL_t +* Output : Status of IEL see LSM303AGR_MAG_IEL_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_MAG_R_IEL(void *handle, LSM303AGR_MAG_IEL_t *value) +{ + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_INT_CTRL_REG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_MAG_IEL_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_MAG_W_IEA +* Description : Write IEA +* Input : LSM303AGR_MAG_IEA_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_MAG_W_IEA(void *handle, LSM303AGR_MAG_IEA_t newValue) +{ + u8_t value; + + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_INT_CTRL_REG, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_MAG_IEA_MASK; + value |= newValue; + + if( !LSM303AGR_MAG_write_reg(handle, LSM303AGR_MAG_INT_CTRL_REG, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_MAG_R_IEA +* Description : Read IEA +* Input : Pointer to LSM303AGR_MAG_IEA_t +* Output : Status of IEA see LSM303AGR_MAG_IEA_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_MAG_R_IEA(void *handle, LSM303AGR_MAG_IEA_t *value) +{ + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_INT_CTRL_REG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_MAG_IEA_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_MAG_W_ZIEN +* Description : Write ZIEN +* Input : LSM303AGR_MAG_ZIEN_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_MAG_W_ZIEN(void *handle, LSM303AGR_MAG_ZIEN_t newValue) +{ + u8_t value; + + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_INT_CTRL_REG, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_MAG_ZIEN_MASK; + value |= newValue; + + if( !LSM303AGR_MAG_write_reg(handle, LSM303AGR_MAG_INT_CTRL_REG, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_MAG_R_ZIEN +* Description : Read ZIEN +* Input : Pointer to LSM303AGR_MAG_ZIEN_t +* Output : Status of ZIEN see LSM303AGR_MAG_ZIEN_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_MAG_R_ZIEN(void *handle, LSM303AGR_MAG_ZIEN_t *value) +{ + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_INT_CTRL_REG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_MAG_ZIEN_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_MAG_W_YIEN +* Description : Write YIEN +* Input : LSM303AGR_MAG_YIEN_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_MAG_W_YIEN(void *handle, LSM303AGR_MAG_YIEN_t newValue) +{ + u8_t value; + + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_INT_CTRL_REG, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_MAG_YIEN_MASK; + value |= newValue; + + if( !LSM303AGR_MAG_write_reg(handle, LSM303AGR_MAG_INT_CTRL_REG, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_MAG_R_YIEN +* Description : Read YIEN +* Input : Pointer to LSM303AGR_MAG_YIEN_t +* Output : Status of YIEN see LSM303AGR_MAG_YIEN_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_MAG_R_YIEN(void *handle, LSM303AGR_MAG_YIEN_t *value) +{ + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_INT_CTRL_REG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_MAG_YIEN_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_MAG_W_XIEN +* Description : Write XIEN +* Input : LSM303AGR_MAG_XIEN_t +* Output : None +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_MAG_W_XIEN(void *handle, LSM303AGR_MAG_XIEN_t newValue) +{ + u8_t value; + + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_INT_CTRL_REG, &value) ) + return MEMS_ERROR; + + value &= ~LSM303AGR_MAG_XIEN_MASK; + value |= newValue; + + if( !LSM303AGR_MAG_write_reg(handle, LSM303AGR_MAG_INT_CTRL_REG, value) ) + return MEMS_ERROR; + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_MAG_R_XIEN +* Description : Read XIEN +* Input : Pointer to LSM303AGR_MAG_XIEN_t +* Output : Status of XIEN see LSM303AGR_MAG_XIEN_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_MAG_R_XIEN(void *handle, LSM303AGR_MAG_XIEN_t *value) +{ + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_INT_CTRL_REG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_MAG_XIEN_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_MAG_R_INT +* Description : Read INT +* Input : Pointer to LSM303AGR_MAG_INT_t +* Output : Status of INT see LSM303AGR_MAG_INT_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_MAG_R_INT(void *handle, LSM303AGR_MAG_INT_t *value) +{ + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_INT_SOURCE_REG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_MAG_INT_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_MAG_R_MROI +* Description : Read MROI +* Input : Pointer to LSM303AGR_MAG_MROI_t +* Output : Status of MROI see LSM303AGR_MAG_MROI_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_MAG_R_MROI(void *handle, LSM303AGR_MAG_MROI_t *value) +{ + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_INT_SOURCE_REG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_MAG_MROI_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_MAG_R_N_TH_S_Z +* Description : Read N_TH_S_Z +* Input : Pointer to LSM303AGR_MAG_N_TH_S_Z_t +* Output : Status of N_TH_S_Z see LSM303AGR_MAG_N_TH_S_Z_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_MAG_R_N_TH_S_Z(void *handle, LSM303AGR_MAG_N_TH_S_Z_t *value) +{ + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_INT_SOURCE_REG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_MAG_N_TH_S_Z_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_MAG_R_N_TH_S_Y +* Description : Read N_TH_S_Y +* Input : Pointer to LSM303AGR_MAG_N_TH_S_Y_t +* Output : Status of N_TH_S_Y see LSM303AGR_MAG_N_TH_S_Y_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_MAG_R_N_TH_S_Y(void *handle, LSM303AGR_MAG_N_TH_S_Y_t *value) +{ + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_INT_SOURCE_REG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_MAG_N_TH_S_Y_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_MAG_R_N_TH_S_X +* Description : Read N_TH_S_X +* Input : Pointer to LSM303AGR_MAG_N_TH_S_X_t +* Output : Status of N_TH_S_X see LSM303AGR_MAG_N_TH_S_X_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_MAG_R_N_TH_S_X(void *handle, LSM303AGR_MAG_N_TH_S_X_t *value) +{ + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_INT_SOURCE_REG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_MAG_N_TH_S_X_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_MAG_R_P_TH_S_Z +* Description : Read P_TH_S_Z +* Input : Pointer to LSM303AGR_MAG_P_TH_S_Z_t +* Output : Status of P_TH_S_Z see LSM303AGR_MAG_P_TH_S_Z_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_MAG_R_P_TH_S_Z(void *handle, LSM303AGR_MAG_P_TH_S_Z_t *value) +{ + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_INT_SOURCE_REG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_MAG_P_TH_S_Z_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_MAG_R_P_TH_S_Y +* Description : Read P_TH_S_Y +* Input : Pointer to LSM303AGR_MAG_P_TH_S_Y_t +* Output : Status of P_TH_S_Y see LSM303AGR_MAG_P_TH_S_Y_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_MAG_R_P_TH_S_Y(void *handle, LSM303AGR_MAG_P_TH_S_Y_t *value) +{ + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_INT_SOURCE_REG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_MAG_P_TH_S_Y_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_MAG_R_P_TH_S_X +* Description : Read P_TH_S_X +* Input : Pointer to LSM303AGR_MAG_P_TH_S_X_t +* Output : Status of P_TH_S_X see LSM303AGR_MAG_P_TH_S_X_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_MAG_R_P_TH_S_X(void *handle, LSM303AGR_MAG_P_TH_S_X_t *value) +{ + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_INT_SOURCE_REG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_MAG_P_TH_S_X_MASK; //mask + + return MEMS_SUCCESS; +} + +/******************************************************************************* +* Function Name : LSM303AGR_MAG_R_XDA +* Description : Read XDA +* Input : Pointer to LSM303AGR_MAG_XDA_t +* Output : Status of XDA see LSM303AGR_MAG_XDA_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_MAG_R_XDA(void *handle, LSM303AGR_MAG_XDA_t *value) +{ + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_STATUS_REG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_MAG_XDA_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_MAG_R_YDA +* Description : Read YDA +* Input : Pointer to LSM303AGR_MAG_YDA_t +* Output : Status of YDA see LSM303AGR_MAG_YDA_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_MAG_R_YDA(void *handle, LSM303AGR_MAG_YDA_t *value) +{ + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_STATUS_REG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_MAG_YDA_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_MAG_R_ZDA +* Description : Read ZDA +* Input : Pointer to LSM303AGR_MAG_ZDA_t +* Output : Status of ZDA see LSM303AGR_MAG_ZDA_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_MAG_R_ZDA(void *handle, LSM303AGR_MAG_ZDA_t *value) +{ + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_STATUS_REG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_MAG_ZDA_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_MAG_R_ZYXDA +* Description : Read ZYXDA +* Input : Pointer to LSM303AGR_MAG_ZYXDA_t +* Output : Status of ZYXDA see LSM303AGR_MAG_ZYXDA_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_MAG_R_ZYXDA(void *handle, LSM303AGR_MAG_ZYXDA_t *value) +{ + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_STATUS_REG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_MAG_ZYXDA_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_MAG_R_XOR +* Description : Read XOR +* Input : Pointer to LSM303AGR_MAG_XOR_t +* Output : Status of XOR see LSM303AGR_MAG_XOR_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_MAG_R_XOR(void *handle, LSM303AGR_MAG_XOR_t *value) +{ + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_STATUS_REG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_MAG_XOR_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_MAG_R_YOR +* Description : Read YOR +* Input : Pointer to LSM303AGR_MAG_YOR_t +* Output : Status of YOR see LSM303AGR_MAG_YOR_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_MAG_R_YOR(void *handle, LSM303AGR_MAG_YOR_t *value) +{ + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_STATUS_REG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_MAG_YOR_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_MAG_R_ZOR +* Description : Read ZOR +* Input : Pointer to LSM303AGR_MAG_ZOR_t +* Output : Status of ZOR see LSM303AGR_MAG_ZOR_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_MAG_R_ZOR(void *handle, LSM303AGR_MAG_ZOR_t *value) +{ + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_STATUS_REG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_MAG_ZOR_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : LSM303AGR_MAG_R_ZYXOR +* Description : Read ZYXOR +* Input : Pointer to LSM303AGR_MAG_ZYXOR_t +* Output : Status of ZYXOR see LSM303AGR_MAG_ZYXOR_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ + +mems_status_t LSM303AGR_MAG_R_ZYXOR(void *handle, LSM303AGR_MAG_ZYXOR_t *value) +{ + if( !LSM303AGR_MAG_read_reg(handle, LSM303AGR_MAG_STATUS_REG, (u8_t *)value) ) + return MEMS_ERROR; + + *value &= LSM303AGR_MAG_ZYXOR_MASK; //mask + + return MEMS_SUCCESS; +} +/******************************************************************************* +* Function Name : mems_status_t LSM303AGR_MAG_Get_Raw_Magnetic(u8_t *buff) +* Description : Read Magnetic output register +* Input : pointer to [u8_t] +* Output : Magnetic buffer u8_t +* Return : Status [MEMS_ERROR, MEMS_SUCCESS] +*******************************************************************************/ +mems_status_t LSM303AGR_MAG_Get_Raw_Magnetic(void *handle, u8_t *buff) +{ + u8_t i, j, k; + u8_t numberOfByteForDimension; + + numberOfByteForDimension=6/3; + + k=0; + for (i=0; i<3;i++ ) + { + for (j=0; j
© COPYRIGHT(c) 2016 STMicroelectronics
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __LSM303AGR_MAG_DRIVER__H +#define __LSM303AGR_MAG_DRIVER__H + +/* Includes ------------------------------------------------------------------*/ +#include + +/* Exported types ------------------------------------------------------------*/ + +#ifdef __cplusplus +extern "C" { +#endif + +//these could change accordingly with the architecture + +#ifndef __ARCHDEP__TYPES +#define __ARCHDEP__TYPES + +typedef unsigned char u8_t; +typedef unsigned short int u16_t; +typedef unsigned int u32_t; +typedef int i32_t; +typedef short int i16_t; +typedef signed char i8_t; + +#endif /*__ARCHDEP__TYPES*/ + +/* Exported common structure --------------------------------------------------------*/ + +#ifndef __SHARED__TYPES +#define __SHARED__TYPES + +typedef union{ + i16_t i16bit[3]; + u8_t u8bit[6]; +} Type3Axis16bit_U; + +typedef union{ + i16_t i16bit; + u8_t u8bit[2]; +} Type1Axis16bit_U; + +typedef union{ + i32_t i32bit; + u8_t u8bit[4]; +} Type1Axis32bit_U; + +typedef enum { + MEMS_SUCCESS = 0x01, + MEMS_ERROR = 0x00 +} mems_status_t; + +#endif /*__SHARED__TYPES*/ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ + +/************** I2C Address *****************/ + +#define LSM303AGR_MAG_I2C_ADDRESS 0x3C + +/************** Who am I *******************/ + +#define LSM303AGR_MAG_WHO_AM_I 0x40 + +/* Private Function Prototype -------------------------------------------------------*/ + +void LSM303AGR_MAG_SwapHighLowByte(u8_t *bufferToSwap, u8_t numberOfByte, u8_t dimension); + +/* Public Function Prototypes -------------------------------------------------------*/ + +mems_status_t LSM303AGR_MAG_read_reg( void *handle, u8_t Reg, u8_t* Data ); +mems_status_t LSM303AGR_MAG_write_reg( void *handle, u8_t Reg, u8_t Data ); + + +/************** Device Register *******************/ +#define LSM303AGR_MAG_OFFSET_X_REG_L 0X45 +#define LSM303AGR_MAG_OFFSET_X_REG_H 0X46 +#define LSM303AGR_MAG_OFFSET_Y_REG_L 0X47 +#define LSM303AGR_MAG_OFFSET_Y_REG_H 0X48 +#define LSM303AGR_MAG_OFFSET_Z_REG_L 0X49 +#define LSM303AGR_MAG_OFFSET_Z_REG_H 0X4A +#define LSM303AGR_MAG_WHO_AM_I_REG 0X4F +#define LSM303AGR_MAG_CFG_REG_A 0X60 +#define LSM303AGR_MAG_CFG_REG_B 0X61 +#define LSM303AGR_MAG_CFG_REG_C 0X62 +#define LSM303AGR_MAG_INT_CTRL_REG 0X63 +#define LSM303AGR_MAG_INT_SOURCE_REG 0X64 +#define LSM303AGR_MAG_INT_THS_L_REG 0X65 +#define LSM303AGR_MAG_INT_THS_H_REG 0X66 +#define LSM303AGR_MAG_STATUS_REG 0X67 +#define LSM303AGR_MAG_OUTX_L_REG 0X68 +#define LSM303AGR_MAG_OUTX_H_REG 0X69 +#define LSM303AGR_MAG_OUTY_L_REG 0X6A +#define LSM303AGR_MAG_OUTY_H_REG 0X6B +#define LSM303AGR_MAG_OUTZ_L_REG 0X6C +#define LSM303AGR_MAG_OUTZ_H_REG 0X6D + +/******************************************************************************* +* Register : OFFSET_X_REG_L +* Address : 0X45 +* Bit Group Name: OFF_X_L +* Permission : RW +*******************************************************************************/ +#define LSM303AGR_MAG_OFF_X_L_MASK 0xFF +#define LSM303AGR_MAG_OFF_X_L_POSITION 0 +mems_status_t LSM303AGR_MAG_W_OFF_X_L(void *handle, u8_t newValue); +mems_status_t LSM303AGR_MAG_R_OFF_X_L(void *handle, u8_t *value); + +/******************************************************************************* +* Register : OFFSET_X_REG_H +* Address : 0X46 +* Bit Group Name: OFF_X_H +* Permission : RW +*******************************************************************************/ +#define LSM303AGR_MAG_OFF_X_H_MASK 0xFF +#define LSM303AGR_MAG_OFF_X_H_POSITION 0 +mems_status_t LSM303AGR_MAG_W_OFF_X_H(void *handle, u8_t newValue); +mems_status_t LSM303AGR_MAG_R_OFF_X_H(void *handle, u8_t *value); + +/******************************************************************************* +* Register : OFFSET_Y_REG_L +* Address : 0X47 +* Bit Group Name: OFF_Y_L +* Permission : RW +*******************************************************************************/ +#define LSM303AGR_MAG_OFF_Y_L_MASK 0xFF +#define LSM303AGR_MAG_OFF_Y_L_POSITION 0 +mems_status_t LSM303AGR_MAG_W_OFF_Y_L(void *handle, u8_t newValue); +mems_status_t LSM303AGR_MAG_R_OFF_Y_L(void *handle, u8_t *value); + +/******************************************************************************* +* Register : OFFSET_Y_REG_H +* Address : 0X48 +* Bit Group Name: OFF_Y_H +* Permission : RW +*******************************************************************************/ +#define LSM303AGR_MAG_OFF_Y_H_MASK 0xFF +#define LSM303AGR_MAG_OFF_Y_H_POSITION 0 +mems_status_t LSM303AGR_MAG_W_OFF_Y_H(void *handle, u8_t newValue); +mems_status_t LSM303AGR_MAG_R_OFF_Y_H(void *handle, u8_t *value); + +/******************************************************************************* +* Register : OFFSET_Z_REG_L +* Address : 0X49 +* Bit Group Name: OFF_Z_L +* Permission : RW +*******************************************************************************/ +#define LSM303AGR_MAG_OFF_Z_L_MASK 0xFF +#define LSM303AGR_MAG_OFF_Z_L_POSITION 0 +mems_status_t LSM303AGR_MAG_W_OFF_Z_L(void *handle, u8_t newValue); +mems_status_t LSM303AGR_MAG_R_OFF_Z_L(void *handle, u8_t *value); + +/******************************************************************************* +* Register : OFFSET_Z_REG_H +* Address : 0X4A +* Bit Group Name: OFF_Z_H +* Permission : RW +*******************************************************************************/ +#define LSM303AGR_MAG_OFF_Z_H_MASK 0xFF +#define LSM303AGR_MAG_OFF_Z_H_POSITION 0 +mems_status_t LSM303AGR_MAG_W_OFF_Z_H(void *handle, u8_t newValue); +mems_status_t LSM303AGR_MAG_R_OFF_Z_H(void *handle, u8_t *value); + +/******************************************************************************* + * Set/Get the Magnetic offsets +*******************************************************************************/ +mems_status_t LSM303AGR_MAG_Get_MagOff(void *handle, u16_t *magx_off, u16_t *magy_off, u16_t *magz_off); +mems_status_t LSM303AGR_MAG_Set_MagOff(void *handle, u16_t magx_off, u16_t magy_off, u16_t magz_off); + +/******************************************************************************* +* Register : WHO_AM_I_REG +* Address : 0X4F +* Bit Group Name: WHO_AM_I +* Permission : RO +*******************************************************************************/ +#define LSM303AGR_MAG_WHO_AM_I_MASK 0xFF +#define LSM303AGR_MAG_WHO_AM_I_POSITION 0 +mems_status_t LSM303AGR_MAG_R_WHO_AM_I(void *handle, u8_t *value); + +/******************************************************************************* +* Register : CFG_REG_A +* Address : 0X60 +* Bit Group Name: MD +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_MAG_MD_CONTINUOS_MODE =0x00, + LSM303AGR_MAG_MD_SINGLE_MODE =0x01, + LSM303AGR_MAG_MD_IDLE1_MODE =0x02, + LSM303AGR_MAG_MD_IDLE2_MODE =0x03, +} LSM303AGR_MAG_MD_t; + +#define LSM303AGR_MAG_MD_MASK 0x03 +mems_status_t LSM303AGR_MAG_W_MD(void *handle, LSM303AGR_MAG_MD_t newValue); +mems_status_t LSM303AGR_MAG_R_MD(void *handle, LSM303AGR_MAG_MD_t *value); + +/******************************************************************************* +* Register : CFG_REG_A +* Address : 0X60 +* Bit Group Name: ODR +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_MAG_ODR_10Hz =0x00, + LSM303AGR_MAG_ODR_20Hz =0x04, + LSM303AGR_MAG_ODR_50Hz =0x08, + LSM303AGR_MAG_ODR_100Hz =0x0C, +} LSM303AGR_MAG_ODR_t; + +#define LSM303AGR_MAG_ODR_MASK 0x0C +mems_status_t LSM303AGR_MAG_W_ODR(void *handle, LSM303AGR_MAG_ODR_t newValue); +mems_status_t LSM303AGR_MAG_R_ODR(void *handle, LSM303AGR_MAG_ODR_t *value); + +/******************************************************************************* +* Register : CFG_REG_A +* Address : 0X60 +* Bit Group Name: LP +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_MAG_HR_MODE =0x00, + LSM303AGR_MAG_LP_MODE =0x10, +} LSM303AGR_MAG_LP_t; + +#define LSM303AGR_MAG_LP_MASK 0x10 +mems_status_t LSM303AGR_MAG_W_LP(void *handle, LSM303AGR_MAG_LP_t newValue); +mems_status_t LSM303AGR_MAG_R_LP(void *handle, LSM303AGR_MAG_LP_t *value); + +/******************************************************************************* +* Register : CFG_REG_A +* Address : 0X60 +* Bit Group Name: SOFT_RST +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_MAG_SOFT_RST_DISABLED =0x00, + LSM303AGR_MAG_SOFT_RST_ENABLED =0x20, +} LSM303AGR_MAG_SOFT_RST_t; + +#define LSM303AGR_MAG_SOFT_RST_MASK 0x20 +mems_status_t LSM303AGR_MAG_W_SOFT_RST(void *handle, LSM303AGR_MAG_SOFT_RST_t newValue); +mems_status_t LSM303AGR_MAG_R_SOFT_RST(void *handle, LSM303AGR_MAG_SOFT_RST_t *value); + +/******************************************************************************* +* Register : CFG_REG_B +* Address : 0X61 +* Bit Group Name: LPF +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_MAG_LPF_DISABLED =0x00, + LSM303AGR_MAG_LPF_ENABLED =0x01, +} LSM303AGR_MAG_LPF_t; + +#define LSM303AGR_MAG_LPF_MASK 0x01 +mems_status_t LSM303AGR_MAG_W_LPF(void *handle, LSM303AGR_MAG_LPF_t newValue); +mems_status_t LSM303AGR_MAG_R_LPF(void *handle, LSM303AGR_MAG_LPF_t *value); + +/******************************************************************************* +* Register : CFG_REG_B +* Address : 0X61 +* Bit Group Name: OFF_CANC +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_MAG_OFF_CANC_DISABLED =0x00, + LSM303AGR_MAG_OFF_CANC_ENABLED =0x02, +} LSM303AGR_MAG_OFF_CANC_t; + +#define LSM303AGR_MAG_OFF_CANC_MASK 0x02 +mems_status_t LSM303AGR_MAG_W_OFF_CANC(void *handle, LSM303AGR_MAG_OFF_CANC_t newValue); +mems_status_t LSM303AGR_MAG_R_OFF_CANC(void *handle, LSM303AGR_MAG_OFF_CANC_t *value); + +/******************************************************************************* +* Register : CFG_REG_B +* Address : 0X61 +* Bit Group Name: SET_FREQ +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_MAG_SET_FREQ_CONTINUOS =0x00, + LSM303AGR_MAG_SET_FREQ_SINGLE =0x04, +} LSM303AGR_MAG_SET_FREQ_t; + +#define LSM303AGR_MAG_SET_FREQ_MASK 0x04 +mems_status_t LSM303AGR_MAG_W_SET_FREQ(void *handle, LSM303AGR_MAG_SET_FREQ_t newValue); +mems_status_t LSM303AGR_MAG_R_SET_FREQ(void *handle, LSM303AGR_MAG_SET_FREQ_t *value); + +/******************************************************************************* +* Register : CFG_REG_B +* Address : 0X61 +* Bit Group Name: INT_ON_DATAOFF +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_MAG_INT_ON_DATAOFF_DISABLED =0x00, + LSM303AGR_MAG_INT_ON_DATAOFF_ENABLED =0x08, +} LSM303AGR_MAG_INT_ON_DATAOFF_t; + +#define LSM303AGR_MAG_INT_ON_DATAOFF_MASK 0x08 +mems_status_t LSM303AGR_MAG_W_INT_ON_DATAOFF(void *handle, LSM303AGR_MAG_INT_ON_DATAOFF_t newValue); +mems_status_t LSM303AGR_MAG_R_INT_ON_DATAOFF(void *handle, LSM303AGR_MAG_INT_ON_DATAOFF_t *value); + +/******************************************************************************* +* Register : CFG_REG_C +* Address : 0X62 +* Bit Group Name: INT_MAG +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_MAG_INT_MAG_DISABLED =0x00, + LSM303AGR_MAG_INT_MAG_ENABLED =0x01, +} LSM303AGR_MAG_INT_MAG_t; + +#define LSM303AGR_MAG_INT_MAG_MASK 0x01 +mems_status_t LSM303AGR_MAG_W_INT_MAG(void *handle, LSM303AGR_MAG_INT_MAG_t newValue); +mems_status_t LSM303AGR_MAG_R_INT_MAG(void *handle, LSM303AGR_MAG_INT_MAG_t *value); + +/******************************************************************************* +* Register : CFG_REG_C +* Address : 0X62 +* Bit Group Name: ST +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_MAG_ST_DISABLED =0x00, + LSM303AGR_MAG_ST_ENABLED =0x02, +} LSM303AGR_MAG_ST_t; + +#define LSM303AGR_MAG_ST_MASK 0x02 +mems_status_t LSM303AGR_MAG_W_ST(void *handle, LSM303AGR_MAG_ST_t newValue); +mems_status_t LSM303AGR_MAG_R_ST(void *handle, LSM303AGR_MAG_ST_t *value); + +/******************************************************************************* +* Register : CFG_REG_C +* Address : 0X62 +* Bit Group Name: BLE +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_MAG_BLE_DISABLED =0x00, + LSM303AGR_MAG_BLE_ENABLED =0x08, +} LSM303AGR_MAG_BLE_t; + +#define LSM303AGR_MAG_BLE_MASK 0x08 +mems_status_t LSM303AGR_MAG_W_BLE(void *handle, LSM303AGR_MAG_BLE_t newValue); +mems_status_t LSM303AGR_MAG_R_BLE(void *handle, LSM303AGR_MAG_BLE_t *value); + +/******************************************************************************* +* Register : CFG_REG_C +* Address : 0X62 +* Bit Group Name: BDU +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_MAG_BDU_DISABLED =0x00, + LSM303AGR_MAG_BDU_ENABLED =0x10, +} LSM303AGR_MAG_BDU_t; + +#define LSM303AGR_MAG_BDU_MASK 0x10 +mems_status_t LSM303AGR_MAG_W_BDU(void *handle, LSM303AGR_MAG_BDU_t newValue); +mems_status_t LSM303AGR_MAG_R_BDU(void *handle, LSM303AGR_MAG_BDU_t *value); + +/******************************************************************************* +* Register : CFG_REG_C +* Address : 0X62 +* Bit Group Name: I2C_DIS +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_MAG_I2C_ENABLED =0x00, + LSM303AGR_MAG_I2C_DISABLED =0x20, +} LSM303AGR_MAG_I2C_DIS_t; + +#define LSM303AGR_MAG_I2C_DIS_MASK 0x20 +mems_status_t LSM303AGR_MAG_W_I2C_DIS(void *handle, LSM303AGR_MAG_I2C_DIS_t newValue); +mems_status_t LSM303AGR_MAG_R_I2C_DIS(void *handle, LSM303AGR_MAG_I2C_DIS_t *value); + +/******************************************************************************* +* Register : CFG_REG_C +* Address : 0X62 +* Bit Group Name: INT_MAG_PIN +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_MAG_INT_MAG_PIN_DISABLED =0x00, + LSM303AGR_MAG_INT_MAG_PIN_ENABLED =0x40, +} LSM303AGR_MAG_INT_MAG_PIN_t; + +#define LSM303AGR_MAG_INT_MAG_PIN_MASK 0x40 +mems_status_t LSM303AGR_MAG_W_INT_MAG_PIN(void *handle, LSM303AGR_MAG_INT_MAG_PIN_t newValue); +mems_status_t LSM303AGR_MAG_R_INT_MAG_PIN(void *handle, LSM303AGR_MAG_INT_MAG_PIN_t *value); + +/******************************************************************************* +* Register : INT_CTRL_REG +* Address : 0X63 +* Bit Group Name: IEN +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_MAG_IEN_DISABLED =0x00, + LSM303AGR_MAG_IEN_ENABLED =0x01, +} LSM303AGR_MAG_IEN_t; + +#define LSM303AGR_MAG_IEN_MASK 0x01 +mems_status_t LSM303AGR_MAG_W_IEN(void *handle, LSM303AGR_MAG_IEN_t newValue); +mems_status_t LSM303AGR_MAG_R_IEN(void *handle, LSM303AGR_MAG_IEN_t *value); + +/******************************************************************************* +* Register : INT_CTRL_REG +* Address : 0X63 +* Bit Group Name: IEL +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_MAG_IEL_PULSED =0x00, + LSM303AGR_MAG_IEL_LATCHED =0x02, +} LSM303AGR_MAG_IEL_t; + +#define LSM303AGR_MAG_IEL_MASK 0x02 +mems_status_t LSM303AGR_MAG_W_IEL(void *handle, LSM303AGR_MAG_IEL_t newValue); +mems_status_t LSM303AGR_MAG_R_IEL(void *handle, LSM303AGR_MAG_IEL_t *value); + +/******************************************************************************* +* Register : INT_CTRL_REG +* Address : 0X63 +* Bit Group Name: IEA +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_MAG_IEA_ACTIVE_LO =0x00, + LSM303AGR_MAG_IEA_ACTIVE_HI =0x04, +} LSM303AGR_MAG_IEA_t; + +#define LSM303AGR_MAG_IEA_MASK 0x04 +mems_status_t LSM303AGR_MAG_W_IEA(void *handle, LSM303AGR_MAG_IEA_t newValue); +mems_status_t LSM303AGR_MAG_R_IEA(void *handle, LSM303AGR_MAG_IEA_t *value); + +/******************************************************************************* +* Register : INT_CTRL_REG +* Address : 0X63 +* Bit Group Name: ZIEN +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_MAG_ZIEN_DISABLED =0x00, + LSM303AGR_MAG_ZIEN_ENABLED =0x20, +} LSM303AGR_MAG_ZIEN_t; + +#define LSM303AGR_MAG_ZIEN_MASK 0x20 +mems_status_t LSM303AGR_MAG_W_ZIEN(void *handle, LSM303AGR_MAG_ZIEN_t newValue); +mems_status_t LSM303AGR_MAG_R_ZIEN(void *handle, LSM303AGR_MAG_ZIEN_t *value); + +/******************************************************************************* +* Register : INT_CTRL_REG +* Address : 0X63 +* Bit Group Name: YIEN +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_MAG_YIEN_DISABLED =0x00, + LSM303AGR_MAG_YIEN_ENABLED =0x40, +} LSM303AGR_MAG_YIEN_t; + +#define LSM303AGR_MAG_YIEN_MASK 0x40 +mems_status_t LSM303AGR_MAG_W_YIEN(void *handle, LSM303AGR_MAG_YIEN_t newValue); +mems_status_t LSM303AGR_MAG_R_YIEN(void *handle, LSM303AGR_MAG_YIEN_t *value); + +/******************************************************************************* +* Register : INT_CTRL_REG +* Address : 0X63 +* Bit Group Name: XIEN +* Permission : RW +*******************************************************************************/ +typedef enum { + LSM303AGR_MAG_XIEN_DISABLED =0x00, + LSM303AGR_MAG_XIEN_ENABLED =0x80, +} LSM303AGR_MAG_XIEN_t; + +#define LSM303AGR_MAG_XIEN_MASK 0x80 +mems_status_t LSM303AGR_MAG_W_XIEN(void *handle, LSM303AGR_MAG_XIEN_t newValue); +mems_status_t LSM303AGR_MAG_R_XIEN(void *handle, LSM303AGR_MAG_XIEN_t *value); + +/******************************************************************************* +* Register : INT_SOURCE_REG +* Address : 0X64 +* Bit Group Name: INT +* Permission : RO +*******************************************************************************/ +typedef enum { + LSM303AGR_MAG_INT_EV_OFF =0x00, + LSM303AGR_MAG_INT_EV_ON =0x01, +} LSM303AGR_MAG_INT_t; + +#define LSM303AGR_MAG_INT_MASK 0x01 +mems_status_t LSM303AGR_MAG_R_INT(void *handle, LSM303AGR_MAG_INT_t *value); + +/******************************************************************************* +* Register : INT_SOURCE_REG +* Address : 0X64 +* Bit Group Name: MROI +* Permission : RO +*******************************************************************************/ +typedef enum { + LSM303AGR_MAG_MROI_EV_OFF =0x00, + LSM303AGR_MAG_MROI_EV_ON =0x02, +} LSM303AGR_MAG_MROI_t; + +#define LSM303AGR_MAG_MROI_MASK 0x02 +mems_status_t LSM303AGR_MAG_R_MROI(void *handle, LSM303AGR_MAG_MROI_t *value); + +/******************************************************************************* +* Register : INT_SOURCE_REG +* Address : 0X64 +* Bit Group Name: N_TH_S_Z +* Permission : RO +*******************************************************************************/ +typedef enum { + LSM303AGR_MAG_N_TH_S_Z_EV_OFF =0x00, + LSM303AGR_MAG_N_TH_S_Z_EV_ON =0x04, +} LSM303AGR_MAG_N_TH_S_Z_t; + +#define LSM303AGR_MAG_N_TH_S_Z_MASK 0x04 +mems_status_t LSM303AGR_MAG_R_N_TH_S_Z(void *handle, LSM303AGR_MAG_N_TH_S_Z_t *value); + +/******************************************************************************* +* Register : INT_SOURCE_REG +* Address : 0X64 +* Bit Group Name: N_TH_S_Y +* Permission : RO +*******************************************************************************/ +typedef enum { + LSM303AGR_MAG_N_TH_S_Y_EV_OFF =0x00, + LSM303AGR_MAG_N_TH_S_Y_EV_ON =0x08, +} LSM303AGR_MAG_N_TH_S_Y_t; + +#define LSM303AGR_MAG_N_TH_S_Y_MASK 0x08 +mems_status_t LSM303AGR_MAG_R_N_TH_S_Y(void *handle, LSM303AGR_MAG_N_TH_S_Y_t *value); + +/******************************************************************************* +* Register : INT_SOURCE_REG +* Address : 0X64 +* Bit Group Name: N_TH_S_X +* Permission : RO +*******************************************************************************/ +typedef enum { + LSM303AGR_MAG_N_TH_S_X_EV_OFF =0x00, + LSM303AGR_MAG_N_TH_S_X_EV_ON =0x10, +} LSM303AGR_MAG_N_TH_S_X_t; + +#define LSM303AGR_MAG_N_TH_S_X_MASK 0x10 +mems_status_t LSM303AGR_MAG_R_N_TH_S_X(void *handle, LSM303AGR_MAG_N_TH_S_X_t *value); + +/******************************************************************************* +* Register : INT_SOURCE_REG +* Address : 0X64 +* Bit Group Name: P_TH_S_Z +* Permission : RO +*******************************************************************************/ +typedef enum { + LSM303AGR_MAG_P_TH_S_Z_EV_OFF =0x00, + LSM303AGR_MAG_P_TH_S_Z_EV_ON =0x20, +} LSM303AGR_MAG_P_TH_S_Z_t; + +#define LSM303AGR_MAG_P_TH_S_Z_MASK 0x20 +mems_status_t LSM303AGR_MAG_R_P_TH_S_Z(void *handle, LSM303AGR_MAG_P_TH_S_Z_t *value); + +/******************************************************************************* +* Register : INT_SOURCE_REG +* Address : 0X64 +* Bit Group Name: P_TH_S_Y +* Permission : RO +*******************************************************************************/ +typedef enum { + LSM303AGR_MAG_P_TH_S_Y_EV_OFF =0x00, + LSM303AGR_MAG_P_TH_S_Y_EV_ON =0x40, +} LSM303AGR_MAG_P_TH_S_Y_t; + +#define LSM303AGR_MAG_P_TH_S_Y_MASK 0x40 +mems_status_t LSM303AGR_MAG_R_P_TH_S_Y(void *handle, LSM303AGR_MAG_P_TH_S_Y_t *value); + +/******************************************************************************* +* Register : INT_SOURCE_REG +* Address : 0X64 +* Bit Group Name: P_TH_S_X +* Permission : RO +*******************************************************************************/ +typedef enum { + LSM303AGR_MAG_P_TH_S_X_EV_OFF =0x00, + LSM303AGR_MAG_P_TH_S_X_EV_ON =0x80, +} LSM303AGR_MAG_P_TH_S_X_t; + +#define LSM303AGR_MAG_P_TH_S_X_MASK 0x80 +mems_status_t LSM303AGR_MAG_R_P_TH_S_X(void *handle, LSM303AGR_MAG_P_TH_S_X_t *value); + +/******************************************************************************* +* Register : STATUS_REG +* Address : 0X67 +* Bit Group Name: XDA +* Permission : RO +*******************************************************************************/ +typedef enum { + LSM303AGR_MAG_XDA_EV_OFF =0x00, + LSM303AGR_MAG_XDA_EV_ON =0x01, +} LSM303AGR_MAG_XDA_t; + +#define LSM303AGR_MAG_XDA_MASK 0x01 +mems_status_t LSM303AGR_MAG_R_XDA(void *handle, LSM303AGR_MAG_XDA_t *value); + +/******************************************************************************* +* Register : STATUS_REG +* Address : 0X67 +* Bit Group Name: YDA +* Permission : RO +*******************************************************************************/ +typedef enum { + LSM303AGR_MAG_YDA_EV_OFF =0x00, + LSM303AGR_MAG_YDA_EV_ON =0x02, +} LSM303AGR_MAG_YDA_t; + +#define LSM303AGR_MAG_YDA_MASK 0x02 +mems_status_t LSM303AGR_MAG_R_YDA(void *handle, LSM303AGR_MAG_YDA_t *value); + +/******************************************************************************* +* Register : STATUS_REG +* Address : 0X67 +* Bit Group Name: ZDA +* Permission : RO +*******************************************************************************/ +typedef enum { + LSM303AGR_MAG_ZDA_EV_OFF =0x00, + LSM303AGR_MAG_ZDA_EV_ON =0x04, +} LSM303AGR_MAG_ZDA_t; + +#define LSM303AGR_MAG_ZDA_MASK 0x04 +mems_status_t LSM303AGR_MAG_R_ZDA(void *handle, LSM303AGR_MAG_ZDA_t *value); + +/******************************************************************************* +* Register : STATUS_REG +* Address : 0X67 +* Bit Group Name: ZYXDA +* Permission : RO +*******************************************************************************/ +typedef enum { + LSM303AGR_MAG_ZYXDA_EV_OFF =0x00, + LSM303AGR_MAG_ZYXDA_EV_ON =0x08, +} LSM303AGR_MAG_ZYXDA_t; + +#define LSM303AGR_MAG_ZYXDA_MASK 0x08 +mems_status_t LSM303AGR_MAG_R_ZYXDA(void *handle, LSM303AGR_MAG_ZYXDA_t *value); + +/******************************************************************************* +* Register : STATUS_REG +* Address : 0X67 +* Bit Group Name: XOR +* Permission : RO +*******************************************************************************/ +typedef enum { + LSM303AGR_MAG_XOR_EV_OFF =0x00, + LSM303AGR_MAG_XOR_EV_ON =0x10, +} LSM303AGR_MAG_XOR_t; + +#define LSM303AGR_MAG_XOR_MASK 0x10 +mems_status_t LSM303AGR_MAG_R_XOR(void *handle, LSM303AGR_MAG_XOR_t *value); + +/******************************************************************************* +* Register : STATUS_REG +* Address : 0X67 +* Bit Group Name: YOR +* Permission : RO +*******************************************************************************/ +typedef enum { + LSM303AGR_MAG_YOR_EV_OFF =0x00, + LSM303AGR_MAG_YOR_EV_ON =0x20, +} LSM303AGR_MAG_YOR_t; + +#define LSM303AGR_MAG_YOR_MASK 0x20 +mems_status_t LSM303AGR_MAG_R_YOR(void *handle, LSM303AGR_MAG_YOR_t *value); + +/******************************************************************************* +* Register : STATUS_REG +* Address : 0X67 +* Bit Group Name: ZOR +* Permission : RO +*******************************************************************************/ +typedef enum { + LSM303AGR_MAG_ZOR_EV_OFF =0x00, + LSM303AGR_MAG_ZOR_EV_ON =0x40, +} LSM303AGR_MAG_ZOR_t; + +#define LSM303AGR_MAG_ZOR_MASK 0x40 +mems_status_t LSM303AGR_MAG_R_ZOR(void *handle, LSM303AGR_MAG_ZOR_t *value); + +/******************************************************************************* +* Register : STATUS_REG +* Address : 0X67 +* Bit Group Name: ZYXOR +* Permission : RO +*******************************************************************************/ +typedef enum { + LSM303AGR_MAG_ZYXOR_EV_OFF =0x00, + LSM303AGR_MAG_ZYXOR_EV_ON =0x80, +} LSM303AGR_MAG_ZYXOR_t; + +#define LSM303AGR_MAG_ZYXOR_MASK 0x80 +mems_status_t LSM303AGR_MAG_R_ZYXOR(void *handle, LSM303AGR_MAG_ZYXOR_t *value); +/******************************************************************************* +* Register : - +* Output Type : Magnetic +* Permission : ro +*******************************************************************************/ +mems_status_t LSM303AGR_MAG_Get_Raw_Magnetic(void *handle, u8_t *buff); +mems_status_t LSM303AGR_MAG_Get_Magnetic(void *handle, int *buff); + +/******************************************************************************* +* Register : - +* Output Type : IntThreshld +* Permission : rw +*******************************************************************************/ +mems_status_t LSM303AGR_MAG_Get_IntThreshld(void *handle, u8_t *buff); +mems_status_t LSM303AGR_MAG_Set_IntThreshld(void *handle, u8_t *buff); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/LSM6DSOX/LSM6DSOXSensor.cpp b/LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/LSM6DSOX/LSM6DSOXSensor.cpp new file mode 100644 index 0000000..9733400 --- /dev/null +++ b/LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/LSM6DSOX/LSM6DSOXSensor.cpp @@ -0,0 +1,2667 @@ +/** + ****************************************************************************** + * @file LSM6DSOXSensor.cpp + * @author SRA + * @version V1.0.0 + * @date February 2019 + * @brief Implementation of an LSM6DSOX Inertial Measurement Unit (IMU) 6 axes + * sensor. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + +/* Includes ------------------------------------------------------------------*/ + +#include "LSM6DSOXSensor.h" + + +/* Class Implementation ------------------------------------------------------*/ + +/** Constructor + * @param spi object of an helper class which handles the SPI peripheral + * @param cs_pin the chip select pin + * @param int1_pin the interrupt 1 pin + * @param int2_pin the interrupt 2 pin + * @param spi_type the SPI type + */ +LSM6DSOXSensor::LSM6DSOXSensor(SPI *spi, PinName cs_pin, PinName int1_pin, PinName int2_pin, SPI_type_t spi_type) : _dev_spi(spi), _cs_pin(cs_pin), _int1_irq(int1_pin), _int2_irq(int2_pin), _spi_type(spi_type) +{ + assert (spi); + if (cs_pin == NC) + { + printf ("ERROR LSM6DSOX CS MUST NOT BE NC\n\r"); + _dev_spi = NULL; + _dev_i2c = NULL; + return; + } + + _reg_ctx.write_reg = LSM6DSOX_io_write; + _reg_ctx.read_reg = LSM6DSOX_io_read; + _reg_ctx.handle = (void *)this; + _cs_pin = 1; + _dev_i2c = NULL; + _address = 0; + + if (_spi_type == SPI3W) + { + /* Enable SPI 3-Wires on the component */ + uint8_t data = 0x0C; + lsm6dsox_write_reg(&_reg_ctx, LSM6DSOX_CTRL3_C, &data, 1); + } +} + + +/** Constructor + * @param i2c object of an helper class which handles the I2C peripheral + * @param address the address of the component's instance + * @param int1_pin the interrupt 1 pin + * @param int2_pin the interrupt 2 pin + */ +LSM6DSOXSensor::LSM6DSOXSensor(DevI2C *i2c, uint8_t address, PinName int1_pin, PinName int2_pin) : _dev_i2c(i2c), _address(address), _cs_pin(NC), _int1_irq(int1_pin), _int2_irq(int2_pin) +{ + assert (i2c); + _dev_spi = NULL; + _reg_ctx.write_reg = LSM6DSOX_io_write; + _reg_ctx.read_reg = LSM6DSOX_io_read; + _reg_ctx.handle = (void *)this; +} + +/** + * @brief Initializing the component + * @param init pointer to device specific initalization structure + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::init(void *init) +{ + /* Enable register address automatically incremented during a multiple byte + access with a serial interface. */ + if (lsm6dsox_auto_increment_set(&_reg_ctx, PROPERTY_ENABLE) != 0) + { + return 1; + } + + /* Enable BDU */ + if (lsm6dsox_block_data_update_set(&_reg_ctx, PROPERTY_ENABLE) != 0) + { + return 1; + } + + /* FIFO mode selection */ + if (lsm6dsox_fifo_mode_set(&_reg_ctx, LSM6DSOX_BYPASS_MODE) != 0) + { + return 1; + } + + /* Output data rate selection - power down. */ + if (lsm6dsox_xl_data_rate_set(&_reg_ctx, LSM6DSOX_XL_ODR_OFF) != 0) + { + return 1; + } + + /* Full scale selection. */ + if (lsm6dsox_xl_full_scale_set(&_reg_ctx, LSM6DSOX_2g) != 0) + { + return 1; + } + + /* Output data rate selection - power down. */ + if (lsm6dsox_gy_data_rate_set(&_reg_ctx, LSM6DSOX_GY_ODR_OFF) != 0) + { + return 1; + } + + /* Full scale selection. */ + if (lsm6dsox_gy_full_scale_set(&_reg_ctx, LSM6DSOX_2000dps) != 0) + { + return 1; + } + + /* Select default output data rate. */ + _x_last_odr = LSM6DSOX_XL_ODR_104Hz; + + /* Select default output data rate. */ + _g_last_odr = LSM6DSOX_GY_ODR_104Hz; + + _x_is_enabled = 0; + + _g_is_enabled = 0; + + return 0; +} + +/** + * @brief Read component ID + * @param id the WHO_AM_I value + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::read_id(uint8_t *id) +{ + if (lsm6dsox_device_id_get(&_reg_ctx, id) != 0) + { + return 1; + } + + return 0; +} + +/** + * @brief Enable the LSM6DSOX accelerometer sensor + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::enable_x() +{ + /* Check if the component is already enabled */ + if (_x_is_enabled == 1U) + { + return 0; + } + + /* Output data rate selection. */ + if (lsm6dsox_xl_data_rate_set(&_reg_ctx, _x_last_odr) != 0) + { + return 1; + } + + _x_is_enabled = 1; + + return 0; +} + +/** + * @brief Disable the LSM6DSOX accelerometer sensor + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::disable_x() +{ + /* Check if the component is already disabled */ + if (_x_is_enabled == 0U) + { + return 0; + } + + /* Get current output data rate. */ + if (lsm6dsox_xl_data_rate_get(&_reg_ctx, &_x_last_odr) != 0) + { + return 1; + } + + /* Output data rate selection - power down. */ + if (lsm6dsox_xl_data_rate_set(&_reg_ctx, LSM6DSOX_XL_ODR_OFF) != 0) + { + return 1; + } + + _x_is_enabled = 0; + + return 0; +} + +/** + * @brief Get the LSM6DSOX accelerometer sensor sensitivity + * @param sensitivity pointer where the sensitivity is written + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::get_x_sensitivity(float *sensitivity) +{ + int ret = 0; + lsm6dsox_fs_xl_t full_scale; + + /* Read actual full scale selection from sensor. */ + if (lsm6dsox_xl_full_scale_get(&_reg_ctx, &full_scale) != 0) + { + return 1; + } + + /* Store the sensitivity based on actual full scale. */ + switch (full_scale) + { + case LSM6DSOX_2g: + *sensitivity = LSM6DSOX_ACC_SENSITIVITY_FS_2G; + break; + + case LSM6DSOX_4g: + *sensitivity = LSM6DSOX_ACC_SENSITIVITY_FS_4G; + break; + + case LSM6DSOX_8g: + *sensitivity = LSM6DSOX_ACC_SENSITIVITY_FS_8G; + break; + + case LSM6DSOX_16g: + *sensitivity = LSM6DSOX_ACC_SENSITIVITY_FS_16G; + break; + + default: + ret = 1; + break; + } + + return ret; +} + +/** + * @brief Get the LSM6DSOX accelerometer sensor output data rate + * @param odr pointer where the output data rate is written + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::get_x_odr(float *odr) +{ + int ret = 0; + lsm6dsox_odr_xl_t odr_low_level; + + /* Get current output data rate. */ + if (lsm6dsox_xl_data_rate_get(&_reg_ctx, &odr_low_level) != 0) + { + return 1; + } + + switch (odr_low_level) + { + case LSM6DSOX_XL_ODR_OFF: + *odr = 0.0f; + break; + + case LSM6DSOX_XL_ODR_6Hz5: + *odr = 6.5f; + break; + + case LSM6DSOX_XL_ODR_12Hz5: + *odr = 12.5f; + break; + + case LSM6DSOX_XL_ODR_26Hz: + *odr = 26.0f; + break; + + case LSM6DSOX_XL_ODR_52Hz: + *odr = 52.0f; + break; + + case LSM6DSOX_XL_ODR_104Hz: + *odr = 104.0f; + break; + + case LSM6DSOX_XL_ODR_208Hz: + *odr = 208.0f; + break; + + case LSM6DSOX_XL_ODR_417Hz: + *odr = 417.0f; + break; + + case LSM6DSOX_XL_ODR_833Hz: + *odr = 833.0f; + break; + + case LSM6DSOX_XL_ODR_1667Hz: + *odr = 1667.0f; + break; + + case LSM6DSOX_XL_ODR_3333Hz: + *odr = 3333.0f; + break; + + case LSM6DSOX_XL_ODR_6667Hz: + *odr = 6667.0f; + break; + + default: + ret = 1; + break; + } + + return ret; +} + +/** + * @brief Set the LSM6DSOX accelerometer sensor output data rate + * @param odr the output data rate value to be set + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::set_x_odr(float odr) +{ + /* Check if the component is enabled */ + if (_x_is_enabled == 1U) + { + return set_x_odr_when_enabled(odr); + } + else + { + return set_x_odr_when_disabled(odr); + } +} + +/** + * @brief Set the LSM6DSOX accelerometer sensor output data rate when enabled + * @param odr the functional output data rate to be set + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::set_x_odr_when_enabled(float odr) +{ + lsm6dsox_odr_xl_t new_odr; + + new_odr = (odr <= 12.5f) ? LSM6DSOX_XL_ODR_12Hz5 + : (odr <= 26.0f) ? LSM6DSOX_XL_ODR_26Hz + : (odr <= 52.0f) ? LSM6DSOX_XL_ODR_52Hz + : (odr <= 104.0f) ? LSM6DSOX_XL_ODR_104Hz + : (odr <= 208.0f) ? LSM6DSOX_XL_ODR_208Hz + : (odr <= 417.0f) ? LSM6DSOX_XL_ODR_417Hz + : (odr <= 833.0f) ? LSM6DSOX_XL_ODR_833Hz + : (odr <= 1667.0f) ? LSM6DSOX_XL_ODR_1667Hz + : (odr <= 3333.0f) ? LSM6DSOX_XL_ODR_3333Hz + : LSM6DSOX_XL_ODR_6667Hz; + + /* Output data rate selection. */ + if (lsm6dsox_xl_data_rate_set(&_reg_ctx, new_odr) != 0) + { + return 1; + } + + return 0; +} + +/** + * @brief Set the LSM6DSOX accelerometer sensor output data rate when disabled + * @param odr the functional output data rate to be set + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::set_x_odr_when_disabled(float odr) +{ + _x_last_odr = (odr <= 12.5f) ? LSM6DSOX_XL_ODR_12Hz5 + : (odr <= 26.0f) ? LSM6DSOX_XL_ODR_26Hz + : (odr <= 52.0f) ? LSM6DSOX_XL_ODR_52Hz + : (odr <= 104.0f) ? LSM6DSOX_XL_ODR_104Hz + : (odr <= 208.0f) ? LSM6DSOX_XL_ODR_208Hz + : (odr <= 417.0f) ? LSM6DSOX_XL_ODR_417Hz + : (odr <= 833.0f) ? LSM6DSOX_XL_ODR_833Hz + : (odr <= 1667.0f) ? LSM6DSOX_XL_ODR_1667Hz + : (odr <= 3333.0f) ? LSM6DSOX_XL_ODR_3333Hz + : LSM6DSOX_XL_ODR_6667Hz; + + return 0; +} + + +/** + * @brief Get the LSM6DSOX accelerometer sensor full scale + * @param full_scale pointer where the full scale is written + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::get_x_fs(float *full_scale) +{ + int ret = 0; + lsm6dsox_fs_xl_t fs_low_level; + + /* Read actual full scale selection from sensor. */ + if (lsm6dsox_xl_full_scale_get(&_reg_ctx, &fs_low_level) != 0) + { + return 1; + } + + switch (fs_low_level) + { + case LSM6DSOX_2g: + *full_scale = 2.0f; + break; + + case LSM6DSOX_4g: + *full_scale = 4.0f; + break; + + case LSM6DSOX_8g: + *full_scale = 8.0f; + break; + + case LSM6DSOX_16g: + *full_scale = 16.0f; + break; + + default: + ret = 1; + break; + } + + return ret; +} + +/** + * @brief Set the LSM6DSOX accelerometer sensor full scale + * @param full_scale the functional full scale to be set + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::set_x_fs(float full_scale) +{ + lsm6dsox_fs_xl_t new_fs; + + /* Seems like MISRA C-2012 rule 14.3a violation but only from single file statical analysis point of view because + the parameter passed to the function is not known at the moment of analysis */ + new_fs = (full_scale <= 2.0f) ? LSM6DSOX_2g + : (full_scale <= 4.0f) ? LSM6DSOX_4g + : (full_scale <= 8.0f) ? LSM6DSOX_8g + : LSM6DSOX_16g; + + if (lsm6dsox_xl_full_scale_set(&_reg_ctx, new_fs) != 0) + { + return 1; + } + + return 0; +} + +/** + * @brief Get the LSM6DSOX accelerometer sensor raw axes + * @param value pointer where the raw values of the axes are written + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::get_x_axes_raw(int16_t *value) +{ + axis3bit16_t data_raw; + + /* Read raw data values. */ + if (lsm6dsox_acceleration_raw_get(&_reg_ctx, data_raw.u8bit) != 0) + { + return 1; + } + + /* Format the data. */ + value[0] = data_raw.i16bit[0]; + value[1] = data_raw.i16bit[1]; + value[2] = data_raw.i16bit[2]; + + return 0; +} + + +/** + * @brief Get the LSM6DSOX accelerometer sensor axes + * @param acceleration pointer where the values of the axes are written + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::get_x_axes(int32_t *acceleration) +{ + axis3bit16_t data_raw; + float sensitivity = 0.0f; + + /* Read raw data values. */ + if (lsm6dsox_acceleration_raw_get(&_reg_ctx, data_raw.u8bit) != 0) + { + return 1; + } + + /* Get LSM6DSOX actual sensitivity. */ + if (get_x_sensitivity(&sensitivity) != 0) + { + return 1; + } + + /* Calculate the data. */ + acceleration[0] = (int32_t)((float)((float)data_raw.i16bit[0] * sensitivity)); + acceleration[1] = (int32_t)((float)((float)data_raw.i16bit[1] * sensitivity)); + acceleration[2] = (int32_t)((float)((float)data_raw.i16bit[2] * sensitivity)); + + return 0; +} + + +/** + * @brief Enable the LSM6DSOX gyroscope sensor + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::enable_g() +{ + /* Check if the component is already enabled */ + if (_g_is_enabled == 1U) + { + return 0; + } + + /* Output data rate selection. */ + if (lsm6dsox_gy_data_rate_set(&_reg_ctx, _g_last_odr) != 0) + { + return 1; + } + + _g_is_enabled = 1; + + return 0; +} + + +/** + * @brief Disable the LSM6DSOX gyroscope sensor + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::disable_g() +{ + /* Check if the component is already disabled */ + if (_g_is_enabled == 0U) + { + return 0; + } + + /* Get current output data rate. */ + if (lsm6dsox_gy_data_rate_get(&_reg_ctx, &_g_last_odr) != 0) + { + return 1; + } + + /* Output data rate selection - power down. */ + if (lsm6dsox_gy_data_rate_set(&_reg_ctx, LSM6DSOX_GY_ODR_OFF) != 0) + { + return 1; + } + + _g_is_enabled = 0; + + return 0; +} + +/** + * @brief Get the LSM6DSOX gyroscope sensor sensitivity + * @param sensitivity pointer where the sensitivity is written + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::get_g_sensitivity(float *sensitivity) +{ + int ret = 0; + lsm6dsox_fs_g_t full_scale; + + /* Read actual full scale selection from sensor. */ + if (lsm6dsox_gy_full_scale_get(&_reg_ctx, &full_scale) != 0) + { + return 1; + } + + /* Store the sensitivity based on actual full scale. */ + switch (full_scale) + { + case LSM6DSOX_125dps: + *sensitivity = LSM6DSOX_GYRO_SENSITIVITY_FS_125DPS; + break; + + case LSM6DSOX_250dps: + *sensitivity = LSM6DSOX_GYRO_SENSITIVITY_FS_250DPS; + break; + + case LSM6DSOX_500dps: + *sensitivity = LSM6DSOX_GYRO_SENSITIVITY_FS_500DPS; + break; + + case LSM6DSOX_1000dps: + *sensitivity = LSM6DSOX_GYRO_SENSITIVITY_FS_1000DPS; + break; + + case LSM6DSOX_2000dps: + *sensitivity = LSM6DSOX_GYRO_SENSITIVITY_FS_2000DPS; + break; + + default: + ret = 1; + break; + } + + return ret; +} + +/** + * @brief Get the LSM6DSOX gyroscope sensor output data rate + * @param odr pointer where the output data rate is written + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::get_g_odr(float *odr) +{ + int ret = 0; + lsm6dsox_odr_g_t odr_low_level; + + /* Get current output data rate. */ + if (lsm6dsox_gy_data_rate_get(&_reg_ctx, &odr_low_level) != 0) + { + return 1; + } + + switch (odr_low_level) + { + case LSM6DSOX_GY_ODR_OFF: + *odr = 0.0f; + break; + + case LSM6DSOX_GY_ODR_12Hz5: + *odr = 12.5f; + break; + + case LSM6DSOX_GY_ODR_26Hz: + *odr = 26.0f; + break; + + case LSM6DSOX_GY_ODR_52Hz: + *odr = 52.0f; + break; + + case LSM6DSOX_GY_ODR_104Hz: + *odr = 104.0f; + break; + + case LSM6DSOX_GY_ODR_208Hz: + *odr = 208.0f; + break; + + case LSM6DSOX_GY_ODR_417Hz: + *odr = 417.0f; + break; + + case LSM6DSOX_GY_ODR_833Hz: + *odr = 833.0f; + break; + + case LSM6DSOX_GY_ODR_1667Hz: + *odr = 1667.0f; + break; + + case LSM6DSOX_GY_ODR_3333Hz: + *odr = 3333.0f; + break; + + case LSM6DSOX_GY_ODR_6667Hz: + *odr = 6667.0f; + break; + + default: + ret = 1; + break; + } + + return ret; +} + +/** + * @brief Set the LSM6DSOX gyroscope sensor output data rate + * @param odr the output data rate value to be set + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::set_g_odr(float odr) +{ + /* Check if the component is enabled */ + if (_g_is_enabled == 1U) + { + return set_g_odr_when_enabled(odr); + } + else + { + return set_g_odr_when_disabled(odr); + } +} + +/** + * @brief Set the LSM6DSOX gyroscope sensor output data rate when enabled + * @param odr the functional output data rate to be set + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::set_g_odr_when_enabled(float odr) +{ + lsm6dsox_odr_g_t new_odr; + + new_odr = (odr <= 12.5f) ? LSM6DSOX_GY_ODR_12Hz5 + : (odr <= 26.0f) ? LSM6DSOX_GY_ODR_26Hz + : (odr <= 52.0f) ? LSM6DSOX_GY_ODR_52Hz + : (odr <= 104.0f) ? LSM6DSOX_GY_ODR_104Hz + : (odr <= 208.0f) ? LSM6DSOX_GY_ODR_208Hz + : (odr <= 417.0f) ? LSM6DSOX_GY_ODR_417Hz + : (odr <= 833.0f) ? LSM6DSOX_GY_ODR_833Hz + : (odr <= 1667.0f) ? LSM6DSOX_GY_ODR_1667Hz + : (odr <= 3333.0f) ? LSM6DSOX_GY_ODR_3333Hz + : LSM6DSOX_GY_ODR_6667Hz; + + /* Output data rate selection. */ + if (lsm6dsox_gy_data_rate_set(&_reg_ctx, new_odr) != 0) + { + return 1; + } + + return 0; +} + +/** + * @brief Set the LSM6DSOX gyroscope sensor output data rate when disabled + * @param odr the functional output data rate to be set + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::set_g_odr_when_disabled(float odr) +{ + _g_last_odr = (odr <= 12.5f) ? LSM6DSOX_GY_ODR_12Hz5 + : (odr <= 26.0f) ? LSM6DSOX_GY_ODR_26Hz + : (odr <= 52.0f) ? LSM6DSOX_GY_ODR_52Hz + : (odr <= 104.0f) ? LSM6DSOX_GY_ODR_104Hz + : (odr <= 208.0f) ? LSM6DSOX_GY_ODR_208Hz + : (odr <= 417.0f) ? LSM6DSOX_GY_ODR_417Hz + : (odr <= 833.0f) ? LSM6DSOX_GY_ODR_833Hz + : (odr <= 1667.0f) ? LSM6DSOX_GY_ODR_1667Hz + : (odr <= 3333.0f) ? LSM6DSOX_GY_ODR_3333Hz + : LSM6DSOX_GY_ODR_6667Hz; + + return 0; +} + + +/** + * @brief Get the LSM6DSOX gyroscope sensor full scale + * @param full_scale pointer where the full scale is written + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::get_g_fs(float *full_scale) +{ + int ret = 0; + lsm6dsox_fs_g_t fs_low_level; + + /* Read actual full scale selection from sensor. */ + if (lsm6dsox_gy_full_scale_get(&_reg_ctx, &fs_low_level) != 0) + { + return 1; + } + + switch (fs_low_level) + { + case LSM6DSOX_125dps: + *full_scale = 125.0f; + break; + + case LSM6DSOX_250dps: + *full_scale = 250.0f; + break; + + case LSM6DSOX_500dps: + *full_scale = 500.0f; + break; + + case LSM6DSOX_1000dps: + *full_scale = 1000.0f; + break; + + case LSM6DSOX_2000dps: + *full_scale = 2000.0f; + break; + + default: + ret = 1; + break; + } + + return ret; +} + +/** + * @brief Set the LSM6DSOX gyroscope sensor full scale + * @param full_scale the functional full scale to be set + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::set_g_fs(float full_scale) +{ + lsm6dsox_fs_g_t new_fs; + + new_fs = (full_scale <= 125.0f) ? LSM6DSOX_125dps + : (full_scale <= 250.0f) ? LSM6DSOX_250dps + : (full_scale <= 500.0f) ? LSM6DSOX_500dps + : (full_scale <= 1000.0f) ? LSM6DSOX_1000dps + : LSM6DSOX_2000dps; + + if (lsm6dsox_gy_full_scale_set(&_reg_ctx, new_fs) != 0) + { + return 1; + } + + return 0; +} + +/** + * @brief Get the LSM6DSOX gyroscope sensor raw axes + * @param value pointer where the raw values of the axes are written + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::get_g_axes_raw(int16_t *value) +{ + axis3bit16_t data_raw; + + /* Read raw data values. */ + if (lsm6dsox_angular_rate_raw_get(&_reg_ctx, data_raw.u8bit) != 0) + { + return 1; + } + + /* Format the data. */ + value[0] = data_raw.i16bit[0]; + value[1] = data_raw.i16bit[1]; + value[2] = data_raw.i16bit[2]; + + return 0; +} + + +/** + * @brief Get the LSM6DSOX gyroscope sensor axes + * @param angular_rate pointer where the values of the axes are written + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::get_g_axes(int32_t *angular_rate) +{ + axis3bit16_t data_raw; + float sensitivity; + + /* Read raw data values. */ + if (lsm6dsox_angular_rate_raw_get(&_reg_ctx, data_raw.u8bit) != 0) + { + return 1; + } + + /* Get LSM6DSOX actual sensitivity. */ + if (get_g_sensitivity(&sensitivity) != 0) + { + return 1; + } + + /* Calculate the data. */ + angular_rate[0] = (int32_t)((float)((float)data_raw.i16bit[0] * sensitivity)); + angular_rate[1] = (int32_t)((float)((float)data_raw.i16bit[1] * sensitivity)); + angular_rate[2] = (int32_t)((float)((float)data_raw.i16bit[2] * sensitivity)); + + return 0; +} + + +/** + * @brief Get the LSM6DSOX register value + * @param reg address to be read + * @param data pointer where the value is written + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::read_reg(uint8_t reg, uint8_t *data) +{ + if (lsm6dsox_read_reg(&_reg_ctx, reg, data, 1) != 0) + { + return 1; + } + + return 0; +} + + +/** + * @brief Set the LSM6DSOX register value + * @param reg address to be written + * @param data value to be written + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::write_reg(uint8_t reg, uint8_t data) +{ + if (lsm6dsox_write_reg(&_reg_ctx, reg, &data, 1) != 0) + { + return 1; + } + + return 0; +} + +/** + * @brief Set the interrupt latch + * @param status value to be written + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::set_interrupt_latch(uint8_t status) +{ + if (status > 1U) + { + return 1; + } + + if (lsm6dsox_int_notification_set(&_reg_ctx, (lsm6dsox_lir_t)status) != 0) + { + return 1; + } + + return 0; +} + +/** + * @brief Enable free fall detection + * @param int_pin interrupt pin line to be used + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::enable_free_fall_detection(LSM6DSOX_Interrupt_Pin_t int_pin) +{ + int ret = 0; + lsm6dsox_pin_int1_route_t val1; + lsm6dsox_pin_int2_route_t val2; + + /* Output Data Rate selection */ + if (set_x_odr(416.0f) != 0) + { + return 1; + } + + /* Full scale selection */ + if (set_x_fs(2.0f) != 0) + { + return 1; + } + + /* FF_DUR setting */ + if (lsm6dsox_ff_dur_set(&_reg_ctx, 0x06) != 0) + { + return 1; + } + + /* WAKE_DUR setting */ + if (lsm6dsox_wkup_dur_set(&_reg_ctx, 0x00) != 0) + { + return 1; + } + + /* SLEEP_DUR setting */ + if (lsm6dsox_act_sleep_dur_set(&_reg_ctx, 0x00) != 0) + { + return 1; + } + + /* FF_THS setting */ + if (lsm6dsox_ff_threshold_set(&_reg_ctx, LSM6DSOX_FF_TSH_312mg) != 0) + { + return 1; + } + + /* Enable free fall event on either INT1 or INT2 pin */ + switch (int_pin) + { + case LSM6DSOX_INT1_PIN: + if (lsm6dsox_pin_int1_route_get(&_reg_ctx, &val1) != 0) + { + return 1; + } + + val1.md1_cfg.int1_ff = PROPERTY_ENABLE; + + if (lsm6dsox_pin_int1_route_set(&_reg_ctx, &val1) != 0) + { + return 1; + } + break; + + case LSM6DSOX_INT2_PIN: + if (lsm6dsox_pin_int2_route_get(&_reg_ctx, &val2) != 0) + { + return 1; + } + + val2.md2_cfg.int2_ff = PROPERTY_ENABLE; + + if (lsm6dsox_pin_int2_route_set(&_reg_ctx, &val2) != 0) + { + return 1; + } + break; + + default: + ret = 1; + break; + } + + return ret; +} + +/** + * @brief Disable free fall detection + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::disable_free_fall_detection() +{ + lsm6dsox_pin_int1_route_t val1; + lsm6dsox_pin_int2_route_t val2; + + /* Disable free fall event on both INT1 and INT2 pins */ + if (lsm6dsox_pin_int1_route_get(&_reg_ctx, &val1) != 0) + { + return 1; + } + + val1.md1_cfg.int1_ff = PROPERTY_DISABLE; + + if (lsm6dsox_pin_int1_route_set(&_reg_ctx, &val1) != 0) + { + return 1; + } + + if (lsm6dsox_pin_int2_route_get(&_reg_ctx, &val2) != 0) + { + return 1; + } + + val2.md2_cfg.int2_ff = PROPERTY_DISABLE; + + if (lsm6dsox_pin_int2_route_set(&_reg_ctx, &val2) != 0) + { + return 1; + } + + /* FF_DUR setting */ + if (lsm6dsox_ff_dur_set(&_reg_ctx, 0x00) != 0) + { + return 1; + } + + /* FF_THS setting */ + if (lsm6dsox_ff_threshold_set(&_reg_ctx, LSM6DSOX_FF_TSH_156mg) != 0) + { + return 1; + } + + return 0; +} + +/** + * @brief Set free fall threshold + * @param thr free fall detection threshold + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::set_free_fall_threshold(uint8_t thr) +{ + if (lsm6dsox_ff_threshold_set(&_reg_ctx, (lsm6dsox_ff_ths_t)thr) != 0) + { + return 1; + } + + return 0; +} + + +/** + * @brief Set free fall duration + * @param dur free fall detection duration + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::set_free_fall_duration(uint8_t dur) +{ + if (lsm6dsox_ff_dur_set(&_reg_ctx, dur) != 0) + { + return 1; + } + + return 0; +} + + +/** + * @brief Enable pedometer + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::enable_pedometer() +{ + lsm6dsox_pin_int1_route_t val; + + /* Output Data Rate selection */ + if (set_x_odr(26.0f) != 0) + { + return 1; + } + + /* Full scale selection */ + if (set_x_fs(2.0f) != 0) + { + return 1; + } + + /* Enable pedometer algorithm. */ + if (lsm6dsox_pedo_sens_set(&_reg_ctx, LSM6DSOX_PEDO_BASE_MODE) != 0) + { + return 1; + } + + /* Enable step detector on INT1 pin */ + if (lsm6dsox_pin_int1_route_get(&_reg_ctx, &val) != 0) + { + return 1; + } + + val.emb_func_int1.int1_step_detector = PROPERTY_ENABLE; + + if (lsm6dsox_pin_int1_route_set(&_reg_ctx, &val) != 0) + { + return 1; + } + + return 0; +} + +/** + * @brief Disable pedometer + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::disable_pedometer() +{ + lsm6dsox_pin_int1_route_t val1; + + /* Disable step detector on INT1 pin */ + if (lsm6dsox_pin_int1_route_get(&_reg_ctx, &val1) != 0) + { + return 1; + } + + val1.emb_func_int1.int1_step_detector = PROPERTY_DISABLE; + + if (lsm6dsox_pin_int1_route_set(&_reg_ctx, &val1) != 0) + { + return 1; + } + + /* Disable pedometer algorithm. */ + if (lsm6dsox_pedo_sens_set(&_reg_ctx, LSM6DSOX_PEDO_DISABLE) != 0) + { + return 1; + } + + return 0; +} + +/** + * @brief Get step count + * @param step_count step counter + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::get_step_counter(uint16_t *step_count) +{ + if (lsm6dsox_number_of_steps_get(&_reg_ctx, (uint8_t *)step_count) != 0) + { + return 1; + } + + return 0; +} + +/** + * @brief Enable step counter reset + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::reset_step_counter() +{ + if (lsm6dsox_steps_reset(&_reg_ctx) != 0) + { + return 1; + } + + return 0; +} + +/** + * @brief Enable tilt detection + * @param int_pin interrupt pin line to be used + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::enable_tilt_detection(LSM6DSOX_Interrupt_Pin_t int_pin) +{ + int ret = 0; + lsm6dsox_pin_int1_route_t val1; + lsm6dsox_pin_int2_route_t val2; + + /* Output Data Rate selection */ + if (set_x_odr(26.0f) != 0) + { + return 1; + } + + /* Full scale selection */ + if (set_x_fs(2.0f) != 0) + { + return 1; + } + + /* Enable tilt calculation. */ + if (lsm6dsox_tilt_sens_set(&_reg_ctx, PROPERTY_ENABLE) != 0) + { + return 1; + } + + /* Enable tilt event on either INT1 or INT2 pin */ + switch (int_pin) + { + case LSM6DSOX_INT1_PIN: + if (lsm6dsox_pin_int1_route_get(&_reg_ctx, &val1) != 0) + { + return 1; + } + + val1.emb_func_int1.int1_tilt = PROPERTY_ENABLE; + + if (lsm6dsox_pin_int1_route_set(&_reg_ctx, &val1) != 0) + { + return 1; + } + break; + + case LSM6DSOX_INT2_PIN: + if (lsm6dsox_pin_int2_route_get(&_reg_ctx, &val2) != 0) + { + return 1; + } + + val2.emb_func_int2.int2_tilt = PROPERTY_ENABLE; + + if (lsm6dsox_pin_int2_route_set(&_reg_ctx, &val2) != 0) + { + return 1; + } + break; + + default: + ret = 1; + break; + } + + return ret; +} + +/** + * @brief Disable tilt detection + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::disable_tilt_detection() +{ + lsm6dsox_pin_int1_route_t val1; + lsm6dsox_pin_int2_route_t val2; + + /* Disable tilt event on both INT1 and INT2 pins */ + if (lsm6dsox_pin_int1_route_get(&_reg_ctx, &val1) != 0) + { + return 1; + } + + val1.emb_func_int1.int1_tilt = PROPERTY_DISABLE; + + if (lsm6dsox_pin_int1_route_set(&_reg_ctx, &val1) != 0) + { + return 1; + } + + if (lsm6dsox_pin_int2_route_get(&_reg_ctx, &val2) != 0) + { + return 1; + } + + val2.emb_func_int2.int2_tilt = PROPERTY_DISABLE; + + if (lsm6dsox_pin_int2_route_set(&_reg_ctx, &val2) != 0) + { + return 1; + } + + /* Disable tilt calculation. */ + if (lsm6dsox_tilt_sens_set(&_reg_ctx, PROPERTY_DISABLE) != 0) + { + return 1; + } + + return 0; +} + +/** + * @brief Enable wake up detection + * @param int_pin interrupt pin line to be used + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::enable_wake_up_detection(LSM6DSOX_Interrupt_Pin_t int_pin) +{ + int ret = 0; + lsm6dsox_pin_int1_route_t val1; + lsm6dsox_pin_int2_route_t val2; + + /* Output Data Rate selection */ + if (set_x_odr(416.0f) != 0) + { + return 1; + } + + /* Full scale selection */ + if (set_x_fs(2.0f) != 0) + { + return 1; + } + + /* WAKE_DUR setting */ + if (lsm6dsox_wkup_dur_set(&_reg_ctx, 0x00) != 0) + { + return 1; + } + + /* Set wake up threshold. */ + if (lsm6dsox_wkup_threshold_set(&_reg_ctx, 0x02) != 0) + { + return 1; + } + + /* Enable wake up event on either INT1 or INT2 pin */ + switch (int_pin) + { + case LSM6DSOX_INT1_PIN: + if (lsm6dsox_pin_int1_route_get(&_reg_ctx, &val1) != 0) + { + return 1; + } + + val1.md1_cfg.int1_wu = PROPERTY_ENABLE; + + if (lsm6dsox_pin_int1_route_set(&_reg_ctx, &val1) != 0) + { + return 1; + } + break; + + case LSM6DSOX_INT2_PIN: + if (lsm6dsox_pin_int2_route_get(&_reg_ctx, &val2) != 0) + { + return 1; + } + + val2.md2_cfg.int2_wu = PROPERTY_ENABLE; + + if (lsm6dsox_pin_int2_route_set(&_reg_ctx, &val2) != 0) + { + return 1; + } + break; + + default: + ret = 1; + break; + } + + return ret; +} + + +/** + * @brief Disable wake up detection + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::disable_wake_up_detection() +{ + lsm6dsox_pin_int1_route_t val1; + lsm6dsox_pin_int2_route_t val2; + + /* Disable wake up event on both INT1 and INT2 pins */ + if (lsm6dsox_pin_int1_route_get(&_reg_ctx, &val1) != 0) + { + return 1; + } + + val1.md1_cfg.int1_wu = PROPERTY_DISABLE; + + if (lsm6dsox_pin_int1_route_set(&_reg_ctx, &val1) != 0) + { + return 1; + } + + if (lsm6dsox_pin_int2_route_get(&_reg_ctx, &val2) != 0) + { + return 1; + } + + val2.md2_cfg.int2_wu = PROPERTY_DISABLE; + + if (lsm6dsox_pin_int2_route_set(&_reg_ctx, &val2) != 0) + { + return 1; + } + + /* Reset wake up threshold. */ + if (lsm6dsox_wkup_threshold_set(&_reg_ctx, 0x00) != 0) + { + return 1; + } + + /* WAKE_DUR setting */ + if (lsm6dsox_wkup_dur_set(&_reg_ctx, 0x00) != 0) + { + return 1; + } + + return 0; +} + +/** + * @brief Set wake up threshold + * @param thr wake up detection threshold + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::set_wake_up_threshold(uint8_t thr) +{ + /* Set wake up threshold. */ + if (lsm6dsox_wkup_threshold_set(&_reg_ctx, thr) != 0) + { + return 1; + } + + return 0; +} + +/** + * @brief Set wake up duration + * @param dur wake up detection duration + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::set_wake_up_duration(uint8_t dur) +{ + /* Set wake up duration. */ + if (lsm6dsox_wkup_dur_set(&_reg_ctx, dur) != 0) + { + return 1; + } + + return 0; +} + +/** + * @brief Enable single tap detection + * @param int_pin interrupt pin line to be used + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::enable_single_tap_detection(LSM6DSOX_Interrupt_Pin_t int_pin) +{ + int ret = 0; + lsm6dsox_pin_int1_route_t val1; + lsm6dsox_pin_int2_route_t val2; + + /* Output Data Rate selection */ + if (set_x_odr(416.0f) != 0) + { + return 1; + } + + /* Full scale selection */ + if (set_x_fs(2.0f) != 0) + { + return 1; + } + + /* Enable X direction in tap recognition. */ + if (lsm6dsox_tap_detection_on_x_set(&_reg_ctx, PROPERTY_ENABLE) != 0) + { + return 1; + } + + /* Enable Y direction in tap recognition. */ + if (lsm6dsox_tap_detection_on_y_set(&_reg_ctx, PROPERTY_ENABLE) != 0) + { + return 1; + } + + /* Enable Z direction in tap recognition. */ + if (lsm6dsox_tap_detection_on_z_set(&_reg_ctx, PROPERTY_ENABLE) != 0) + { + return 1; + } + + /* Set tap threshold. */ + if (lsm6dsox_tap_threshold_x_set(&_reg_ctx, 0x08) != 0) + { + return 1; + } + + /* Set tap shock time window. */ + if (lsm6dsox_tap_shock_set(&_reg_ctx, 0x02) != 0) + { + return 1; + } + + /* Set tap quiet time window. */ + if (lsm6dsox_tap_quiet_set(&_reg_ctx, 0x01) != 0) + { + return 1; + } + + /* _NOTE_: Tap duration time window - don't care for single tap. */ + + /* _NOTE_: Single/Double Tap event - don't care of this flag for single tap. */ + + /* Enable single tap event on either INT1 or INT2 pin */ + switch (int_pin) + { + case LSM6DSOX_INT1_PIN: + if (lsm6dsox_pin_int1_route_get(&_reg_ctx, &val1) != 0) + { + return 1; + } + + val1.md1_cfg.int1_single_tap = PROPERTY_ENABLE; + + if (lsm6dsox_pin_int1_route_set(&_reg_ctx, &val1) != 0) + { + return 1; + } + break; + + case LSM6DSOX_INT2_PIN: + if (lsm6dsox_pin_int2_route_get(&_reg_ctx, &val2) != 0) + { + return 1; + } + + val2.md2_cfg.int2_single_tap = PROPERTY_ENABLE; + + if (lsm6dsox_pin_int2_route_set(&_reg_ctx, &val2) != 0) + { + return 1; + } + break; + + default: + ret = 1; + break; + } + + return ret; +} + +/** + * @brief Disable single tap detection + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::disable_single_tap_detection() +{ + lsm6dsox_pin_int1_route_t val1; + lsm6dsox_pin_int2_route_t val2; + + /* Disable single tap event on both INT1 and INT2 pins */ + if (lsm6dsox_pin_int1_route_get(&_reg_ctx, &val1) != 0) + { + return 1; + } + + val1.md1_cfg.int1_single_tap = PROPERTY_DISABLE; + + if (lsm6dsox_pin_int1_route_set(&_reg_ctx, &val1) != 0) + { + return 1; + } + + if (lsm6dsox_pin_int2_route_get(&_reg_ctx, &val2) != 0) + { + return 1; + } + + val2.md2_cfg.int2_single_tap = PROPERTY_DISABLE; + + if (lsm6dsox_pin_int2_route_set(&_reg_ctx, &val2) != 0) + { + return 1; + } + + /* Reset tap quiet time window. */ + if (lsm6dsox_tap_quiet_set(&_reg_ctx, 0x00) != 0) + { + return 1; + } + + /* Reset tap shock time window. */ + if (lsm6dsox_tap_shock_set(&_reg_ctx, 0x00) != 0) + { + return 1; + } + + /* Reset tap threshold. */ + if (lsm6dsox_tap_threshold_x_set(&_reg_ctx, 0x00) != 0) + { + return 1; + } + + /* Disable Z direction in tap recognition. */ + if (lsm6dsox_tap_detection_on_z_set(&_reg_ctx, PROPERTY_DISABLE) != 0) + { + return 1; + } + + /* Disable Y direction in tap recognition. */ + if (lsm6dsox_tap_detection_on_y_set(&_reg_ctx, PROPERTY_DISABLE) != 0) + { + return 1; + } + + /* Disable X direction in tap recognition. */ + if (lsm6dsox_tap_detection_on_x_set(&_reg_ctx, PROPERTY_DISABLE) != 0) + { + return 1; + } + + return 0; +} + +/** + * @brief Enable double tap detection + * @param int_pin interrupt pin line to be used + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::enable_double_tap_detection(LSM6DSOX_Interrupt_Pin_t int_pin) +{ + int ret = 0; + lsm6dsox_pin_int1_route_t val1; + lsm6dsox_pin_int2_route_t val2; + + /* Output Data Rate selection */ + if (set_x_odr(416.0f) != 0) + { + return 1; + } + + /* Full scale selection */ + if (set_x_fs(2.0f) != 0) + { + return 1; + } + + /* Enable X direction in tap recognition. */ + if (lsm6dsox_tap_detection_on_x_set(&_reg_ctx, PROPERTY_ENABLE) != 0) + { + return 1; + } + + /* Enable Y direction in tap recognition. */ + if (lsm6dsox_tap_detection_on_y_set(&_reg_ctx, PROPERTY_ENABLE) != 0) + { + return 1; + } + + /* Enable Z direction in tap recognition. */ + if (lsm6dsox_tap_detection_on_z_set(&_reg_ctx, PROPERTY_ENABLE) != 0) + { + return 1; + } + + /* Set tap threshold. */ + if (lsm6dsox_tap_threshold_x_set(&_reg_ctx, 0x08) != 0) + { + return 1; + } + + /* Set tap shock time window. */ + if (lsm6dsox_tap_shock_set(&_reg_ctx, 0x03) != 0) + { + return 1; + } + + /* Set tap quiet time window. */ + if (lsm6dsox_tap_quiet_set(&_reg_ctx, 0x03) != 0) + { + return 1; + } + + /* Set tap duration time window. */ + if (lsm6dsox_tap_dur_set(&_reg_ctx, 0x08) != 0) + { + return 1; + } + + /* Single and double tap enabled. */ + if (lsm6dsox_tap_mode_set(&_reg_ctx, LSM6DSOX_BOTH_SINGLE_DOUBLE) != 0) + { + return 1; + } + + /* Enable double tap event on either INT1 or INT2 pin */ + switch (int_pin) + { + case LSM6DSOX_INT1_PIN: + if (lsm6dsox_pin_int1_route_get(&_reg_ctx, &val1) != 0) + { + return 1; + } + + val1.md1_cfg.int1_double_tap = PROPERTY_ENABLE; + + if (lsm6dsox_pin_int1_route_set(&_reg_ctx, &val1) != 0) + { + return 1; + } + break; + + case LSM6DSOX_INT2_PIN: + if (lsm6dsox_pin_int2_route_get(&_reg_ctx, &val2) != 0) + { + return 1; + } + + val2.md2_cfg.int2_double_tap = PROPERTY_ENABLE; + + if (lsm6dsox_pin_int2_route_set(&_reg_ctx, &val2) != 0) + { + return 1; + } + break; + + default: + ret = 1; + break; + } + + return ret; +} + +/** + * @brief Disable double tap detection + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::disable_double_tap_detection() +{ + lsm6dsox_pin_int1_route_t val1; + lsm6dsox_pin_int2_route_t val2; + + /* Disable double tap event on both INT1 and INT2 pins */ + if (lsm6dsox_pin_int1_route_get(&_reg_ctx, &val1) != 0) + { + return 1; + } + + val1.md1_cfg.int1_double_tap = PROPERTY_DISABLE; + + if (lsm6dsox_pin_int1_route_set(&_reg_ctx, &val1) != 0) + { + return 1; + } + + if (lsm6dsox_pin_int2_route_get(&_reg_ctx, &val2) != 0) + { + return 1; + } + + val2.md2_cfg.int2_double_tap = PROPERTY_DISABLE; + + if (lsm6dsox_pin_int2_route_set(&_reg_ctx, &val2) != 0) + { + return 1; + } + + /* Only single tap enabled. */ + if (lsm6dsox_tap_mode_set(&_reg_ctx, LSM6DSOX_ONLY_SINGLE) != 0) + { + return 1; + } + + /* Reset tap duration time window. */ + if (lsm6dsox_tap_dur_set(&_reg_ctx, 0x00) != 0) + { + return 1; + } + + /* Reset tap quiet time window. */ + if (lsm6dsox_tap_quiet_set(&_reg_ctx, 0x00) != 0) + { + return 1; + } + + /* Reset tap shock time window. */ + if (lsm6dsox_tap_shock_set(&_reg_ctx, 0x00) != 0) + { + return 1; + } + + /* Reset tap threshold. */ + if (lsm6dsox_tap_threshold_x_set(&_reg_ctx, 0x00) != 0) + { + return 1; + } + + /* Disable Z direction in tap recognition. */ + if (lsm6dsox_tap_detection_on_z_set(&_reg_ctx, PROPERTY_DISABLE) != 0) + { + return 1; + } + + /* Disable Y direction in tap recognition. */ + if (lsm6dsox_tap_detection_on_y_set(&_reg_ctx, PROPERTY_DISABLE) != 0) + { + return 1; + } + + /* Disable X direction in tap recognition. */ + if (lsm6dsox_tap_detection_on_x_set(&_reg_ctx, PROPERTY_DISABLE) != 0) + { + return 1; + } + + return 0; +} + +/** + * @brief Set tap threshold + * @param thr tap threshold + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::set_tap_threshold(uint8_t thr) +{ + /* Set tap threshold. */ + if (lsm6dsox_tap_threshold_x_set(&_reg_ctx, thr) != 0) + { + return 1; + } + + return 0; +} + +/** + * @brief Set tap shock time + * @param time tap shock time + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::set_tap_shock_time(uint8_t time) +{ + /* Set tap shock time window. */ + if (lsm6dsox_tap_shock_set(&_reg_ctx, time) != 0) + { + return 1; + } + + return 0; +} + +/** + * @brief Set tap quiet time + * @param time tap quiet time + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::set_tap_quiet_time(uint8_t time) +{ + /* Set tap quiet time window. */ + if (lsm6dsox_tap_quiet_set(&_reg_ctx, time) != 0) + { + return 1; + } + + return 0; +} + +/** + * @brief Set tap duration time + * @param time tap duration time + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::set_tap_duration_time(uint8_t time) +{ + /* Set tap duration time window. */ + if (lsm6dsox_tap_dur_set(&_reg_ctx, time) != 0) + { + return 1; + } + + return 0; +} + +/** + * @brief Enable 6D orientation detection + * @param int_pin interrupt pin line to be used + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::enable_6d_orientation(LSM6DSOX_Interrupt_Pin_t int_pin) +{ + int ret = 0; + lsm6dsox_pin_int1_route_t val1; + lsm6dsox_pin_int2_route_t val2; + + /* Output Data Rate selection */ + if (set_x_odr(416.0f) != 0) + { + return 1; + } + + /* Full scale selection */ + if (set_x_fs(2.0f) != 0) + { + return 1; + } + + /* 6D orientation enabled. */ + if (lsm6dsox_6d_threshold_set(&_reg_ctx, LSM6DSOX_DEG_60) != 0) + { + return 1; + } + + /* Enable 6D orientation event on either INT1 or INT2 pin */ + switch (int_pin) + { + case LSM6DSOX_INT1_PIN: + if (lsm6dsox_pin_int1_route_get(&_reg_ctx, &val1) != 0) + { + return 1; + } + + val1.md1_cfg.int1_6d = PROPERTY_ENABLE; + + if (lsm6dsox_pin_int1_route_set(&_reg_ctx, &val1) != 0) + { + return 1; + } + break; + + case LSM6DSOX_INT2_PIN: + if (lsm6dsox_pin_int2_route_get(&_reg_ctx, &val2) != 0) + { + return 1; + } + + val2.md2_cfg.int2_6d = PROPERTY_ENABLE; + + if (lsm6dsox_pin_int2_route_set(&_reg_ctx, &val2) != 0) + { + return 1; + } + break; + + default: + ret = 1; + break; + } + + return ret; +} + +/** + * @brief Disable 6D orientation detection + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::disable_6d_orientation() +{ + lsm6dsox_pin_int1_route_t val1; + lsm6dsox_pin_int2_route_t val2; + + /* Disable 6D orientation event on both INT1 and INT2 pins */ + if (lsm6dsox_pin_int1_route_get(&_reg_ctx, &val1) != 0) + { + return 1; + } + + val1.md1_cfg.int1_6d = PROPERTY_DISABLE; + + if (lsm6dsox_pin_int1_route_set(&_reg_ctx, &val1) != 0) + { + return 1; + } + + if (lsm6dsox_pin_int2_route_get(&_reg_ctx, &val2) != 0) + { + return 1; + } + + val2.md2_cfg.int2_6d = PROPERTY_DISABLE; + + if (lsm6dsox_pin_int2_route_set(&_reg_ctx, &val2) != 0) + { + return 1; + } + + /* Reset 6D orientation. */ + if (lsm6dsox_6d_threshold_set(&_reg_ctx, LSM6DSOX_DEG_80) != 0) + { + return 1; + } + + return 0; +} + +/** + * @brief Set 6D orientation threshold + * @param thr 6D Orientation detection threshold + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::set_6d_orientation_threshold(uint8_t thr) +{ + if (lsm6dsox_6d_threshold_set(&_reg_ctx, (lsm6dsox_sixd_ths_t)thr) != 0) + { + return 1; + } + + return 0; +} + +/** + * @brief Get the status of XLow orientation + * @param xl the status of XLow orientation + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::get_6d_orientation_xl(uint8_t *xl) +{ + lsm6dsox_d6d_src_t data; + + if (lsm6dsox_read_reg(&_reg_ctx, LSM6DSOX_D6D_SRC, (uint8_t *)&data, 1) != 0) + { + return 1; + } + + *xl = data.xl; + + return 0; +} + +/** + * @brief Get the status of XHigh orientation + * @param xh the status of XHigh orientation + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::get_6d_orientation_xh(uint8_t *xh) +{ + lsm6dsox_d6d_src_t data; + + if (lsm6dsox_read_reg(&_reg_ctx, LSM6DSOX_D6D_SRC, (uint8_t *)&data, 1) != 0) + { + return 1; + } + + *xh = data.xh; + + return 0; +} + +/** + * @brief Get the status of YLow orientation + * @param yl the status of YLow orientation + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::get_6d_orientation_yl(uint8_t *yl) +{ + lsm6dsox_d6d_src_t data; + + if (lsm6dsox_read_reg(&_reg_ctx, LSM6DSOX_D6D_SRC, (uint8_t *)&data, 1) != 0) + { + return 1; + } + + *yl = data.yl; + + return 0; +} + +/** + * @brief Get the status of YHigh orientation + * @param yh the status of YHigh orientation + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::get_6d_orientation_yh(uint8_t *yh) +{ + lsm6dsox_d6d_src_t data; + + if (lsm6dsox_read_reg(&_reg_ctx, LSM6DSOX_D6D_SRC, (uint8_t *)&data, 1) != 0) + { + return 1; + } + + *yh = data.yh; + + return 0; +} + +/** + * @brief Get the status of ZLow orientation + * @param zl the status of ZLow orientation + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::get_6d_orientation_zl(uint8_t *zl) +{ + lsm6dsox_d6d_src_t data; + + if (lsm6dsox_read_reg(&_reg_ctx, LSM6DSOX_D6D_SRC, (uint8_t *)&data, 1) != 0) + { + return 1; + } + + *zl = data.zl; + + return 0; +} + +/** + * @brief Get the status of ZHigh orientation + * @param zh the status of ZHigh orientation + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::get_6d_orientation_zh(uint8_t *zh) +{ + lsm6dsox_d6d_src_t data; + + if (lsm6dsox_read_reg(&_reg_ctx, LSM6DSOX_D6D_SRC, (uint8_t *)&data, 1) != 0) + { + return 1; + } + + *zh = data.zh; + + return 0; +} + +/** + * @brief Get the LSM6DSOX ACC data ready bit value + * @param status the status of data ready bit + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::get_x_drdy_status(uint8_t *status) +{ + if (lsm6dsox_xl_flag_data_ready_get(&_reg_ctx, status) != 0) + { + return 1; + } + + return 0; +} + +/** + * @brief Get the status of all hardware events + * @param status the status of all hardware events + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::get_event_status(LSM6DSOX_Event_Status_t *status) +{ + uint8_t tilt_ia = 0U; + lsm6dsox_wake_up_src_t wake_up_src; + lsm6dsox_tap_src_t tap_src; + lsm6dsox_d6d_src_t d6d_src; + lsm6dsox_emb_func_src_t func_src; + lsm6dsox_md1_cfg_t md1_cfg; + lsm6dsox_md2_cfg_t md2_cfg; + lsm6dsox_emb_func_int1_t int1_ctrl; + lsm6dsox_emb_func_int2_t int2_ctrl; + + (void)memset((void *)status, 0x0, sizeof(LSM6DSOX_Event_Status_t)); + + if (lsm6dsox_read_reg(&_reg_ctx, LSM6DSOX_WAKE_UP_SRC, (uint8_t *)&wake_up_src, 1) != 0) + { + return 1; + } + + if (lsm6dsox_read_reg(&_reg_ctx, LSM6DSOX_TAP_SRC, (uint8_t *)&tap_src, 1) != 0) + { + return 1; + } + + if (lsm6dsox_read_reg(&_reg_ctx, LSM6DSOX_D6D_SRC, (uint8_t *)&d6d_src, 1) != 0) + { + return 1; + } + + if (lsm6dsox_mem_bank_set(&_reg_ctx, LSM6DSOX_EMBEDDED_FUNC_BANK) != 0) + { + return 1; + } + + if (lsm6dsox_read_reg(&_reg_ctx, LSM6DSOX_EMB_FUNC_SRC, (uint8_t *)&func_src, 1) != 0) + { + return 1; + } + + if (lsm6dsox_read_reg(&_reg_ctx, LSM6DSOX_EMB_FUNC_INT1, (uint8_t *)&int1_ctrl, 1) != 0) + { + return 1; + } + + if (lsm6dsox_read_reg(&_reg_ctx, LSM6DSOX_EMB_FUNC_INT2, (uint8_t *)&int2_ctrl, 1) != 0) + { + return 1; + } + + if (lsm6dsox_mem_bank_set(&_reg_ctx, LSM6DSOX_USER_BANK) != 0) + { + return 1; + } + + if (lsm6dsox_read_reg(&_reg_ctx, LSM6DSOX_MD1_CFG, (uint8_t *)&md1_cfg, 1) != 0) + { + return 1; + } + + if (lsm6dsox_read_reg(&_reg_ctx, LSM6DSOX_MD2_CFG, (uint8_t *)&md2_cfg, 1) != 0) + { + return 1; + } + + if (lsm6dsox_tilt_flag_data_ready_get(&_reg_ctx, &tilt_ia) != 0) + { + return 1; + } + + if ((md1_cfg.int1_ff == 1U) || (md2_cfg.int2_ff == 1U)) + { + if (wake_up_src.ff_ia == 1U) + { + status->FreeFallStatus = 1; + } + } + + if ((md1_cfg.int1_wu == 1U) || (md2_cfg.int2_wu == 1U)) + { + if (wake_up_src.wu_ia == 1U) + { + status->WakeUpStatus = 1; + } + } + + if ((md1_cfg.int1_single_tap == 1U) || (md2_cfg.int2_single_tap == 1U)) + { + if (tap_src.single_tap == 1U) + { + status->TapStatus = 1; + } + } + + if ((md1_cfg.int1_double_tap == 1U) || (md2_cfg.int2_double_tap == 1U)) + { + if (tap_src.double_tap == 1U) + { + status->DoubleTapStatus = 1; + } + } + + if ((md1_cfg.int1_6d == 1U) || (md2_cfg.int2_6d == 1U)) + { + if (d6d_src.d6d_ia == 1U) + { + status->D6DOrientationStatus = 1; + } + } + + if (int1_ctrl.int1_step_detector == 1U) + { + if (func_src.step_detected == 1U) + { + status->StepStatus = 1; + } + } + + if ((int1_ctrl.int1_tilt == 1U) || (int2_ctrl.int2_tilt == 1U)) + { + if (tilt_ia == 1U) + { + status->TiltStatus = 1; + } + } + + return 0; +} + +/** + * @brief Set self test + * @param val the value of st_xl in reg CTRL5_C + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::set_x_self_test(uint8_t val) +{ + lsm6dsox_st_xl_t reg; + + reg = (val == 0U) ? LSM6DSOX_XL_ST_DISABLE + : (val == 1U) ? LSM6DSOX_XL_ST_POSITIVE + : (val == 2U) ? LSM6DSOX_XL_ST_NEGATIVE + : LSM6DSOX_XL_ST_DISABLE; + + if (lsm6dsox_xl_self_test_set(&_reg_ctx, reg) != 0) + { + return 1; + } + + return 0; +} + +/** + * @brief Get the LSM6DSOX GYRO data ready bit value + * @param status the status of data ready bit + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::get_g_drdy_status(uint8_t *status) +{ + if (lsm6dsox_gy_flag_data_ready_get(&_reg_ctx, status) != 0) + { + return 1; + } + + return 0; +} + +/** + * @brief Set self test + * @param val the value of st_xl in reg CTRL5_C + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::set_g_self_test(uint8_t val) +{ + lsm6dsox_st_g_t reg; + + reg = (val == 0U) ? LSM6DSOX_GY_ST_DISABLE + : (val == 1U) ? LSM6DSOX_GY_ST_POSITIVE + : (val == 2U) ? LSM6DSOX_GY_ST_NEGATIVE + : LSM6DSOX_GY_ST_DISABLE; + + + if (lsm6dsox_gy_self_test_set(&_reg_ctx, reg) != 0) + { + return 1; + } + + return 0; +} + +/** + * @brief Get the LSM6DSOX FIFO number of samples + * @param num_samples number of samples + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::get_fifo_num_samples(uint16_t *num_samples) +{ + if (lsm6dsox_fifo_data_level_get(&_reg_ctx, num_samples) != 0) + { + return 1; + } + + return 0; +} + +/** + * @brief Get the LSM6DSOX FIFO full status + * @param status FIFO full status + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::get_fifo_full_status(uint8_t *status) +{ + lsm6dsox_reg_t reg; + + if (lsm6dsox_read_reg(&_reg_ctx, LSM6DSOX_FIFO_STATUS2, ®.byte, 1) != 0) + { + return 1; + } + + *status = reg.fifo_status2.fifo_full_ia; + + return 0; +} + +/** + * @brief Set the LSM6DSOX FIFO full interrupt on INT1 pin + * @param status FIFO full interrupt on INT1 pin status + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::set_fifo_int1_fifo_full(uint8_t status) +{ + lsm6dsox_reg_t reg; + + if (lsm6dsox_read_reg(&_reg_ctx, LSM6DSOX_INT1_CTRL, ®.byte, 1) != 0) + { + return 1; + } + + reg.int1_ctrl.int1_fifo_full = status; + + if (lsm6dsox_write_reg(&_reg_ctx, LSM6DSOX_INT1_CTRL, ®.byte, 1) != 0) + { + return 1; + } + + return 0; +} + +/** + * @brief Set the LSM6DSOX FIFO watermark level + * @param watermark FIFO watermark level + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::set_fifo_watermark_level(uint16_t watermark) +{ + if (lsm6dsox_fifo_watermark_set(&_reg_ctx, watermark) != 0) + { + return 1; + } + + return 0; +} + +/** + * @brief Set the LSM6DSOX FIFO stop on watermark + * @param status FIFO stop on watermark status + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::set_fifo_stop_on_fth(uint8_t status) +{ + if (lsm6dsox_fifo_stop_on_wtm_set(&_reg_ctx, status) != 0) + { + return 1; + } + + return 0; +} + +/** + * @brief Set the LSM6DSOX FIFO mode + * @param mode FIFO mode + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::set_fifo_mode(uint8_t mode) +{ + int ret = 0; + + /* Verify that the passed parameter contains one of the valid values. */ + switch ((lsm6dsox_fifo_mode_t)mode) + { + case LSM6DSOX_BYPASS_MODE: + case LSM6DSOX_FIFO_MODE: + case LSM6DSOX_STREAM_TO_FIFO_MODE: + case LSM6DSOX_BYPASS_TO_STREAM_MODE: + case LSM6DSOX_STREAM_MODE: + break; + + default: + ret = 1; + break; + } + + if (ret == 1) + { + return ret; + } + + if (lsm6dsox_fifo_mode_set(&_reg_ctx, (lsm6dsox_fifo_mode_t)mode) != 0) + { + return 1; + } + + return ret; +} + +/** + * @brief Get the LSM6DSOX FIFO tag + * @param tag FIFO tag + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::get_fifo_tag(uint8_t *tag) +{ + lsm6dsox_fifo_tag_t tag_local; + + if (lsm6dsox_fifo_sensor_tag_get(&_reg_ctx, &tag_local) != 0) + { + return 1; + } + + *tag = (uint8_t)tag_local; + + return 0; +} + +/** + * @brief Get the LSM6DSOX FIFO raw data + * @param data FIFO raw data array [6] + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::get_fifo_data(uint8_t *data) +{ + if (lsm6dsox_read_reg(&_reg_ctx, LSM6DSOX_FIFO_DATA_OUT_X_L, data, 6) != 0) + { + return 1; + } + + return 0; +} + +/** + * @brief Get the LSM6DSOX FIFO accelero single sample (16-bit data per 3 axes) and calculate acceleration [mg] + * @param acceleration FIFO accelero axes [mg] + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::get_fifo_x_axes(int32_t *acceleration) +{ + uint8_t data[6]; + int16_t data_raw[3]; + float sensitivity = 0.0f; + float acceleration_float[3]; + + if (get_fifo_data(data) != 0) + { + return 1; + } + + data_raw[0] = ((int16_t)data[1] << 8) | data[0]; + data_raw[1] = ((int16_t)data[3] << 8) | data[2]; + data_raw[2] = ((int16_t)data[5] << 8) | data[4]; + + if (get_x_sensitivity(&sensitivity) != 0) + { + return 1; + } + + acceleration_float[0] = (float)data_raw[0] * sensitivity; + acceleration_float[1] = (float)data_raw[1] * sensitivity; + acceleration_float[2] = (float)data_raw[2] * sensitivity; + + acceleration[0] = (int32_t)acceleration_float[0]; + acceleration[1] = (int32_t)acceleration_float[1]; + acceleration[2] = (int32_t)acceleration_float[2]; + + return 0; +} + +/** + * @brief Set the LSM6DSOX FIFO accelero BDR value + * @param bdr FIFO accelero BDR value + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::set_fifo_x_bdr(float bdr) +{ + lsm6dsox_bdr_xl_t new_bdr; + + new_bdr = (bdr <= 0.0f) ? LSM6DSOX_XL_NOT_BATCHED + : (bdr <= 12.5f) ? LSM6DSOX_XL_BATCHED_AT_12Hz5 + : (bdr <= 26.0f) ? LSM6DSOX_XL_BATCHED_AT_26Hz + : (bdr <= 52.0f) ? LSM6DSOX_XL_BATCHED_AT_52Hz + : (bdr <= 104.0f) ? LSM6DSOX_XL_BATCHED_AT_104Hz + : (bdr <= 208.0f) ? LSM6DSOX_XL_BATCHED_AT_208Hz + : (bdr <= 416.0f) ? LSM6DSOX_XL_BATCHED_AT_417Hz + : (bdr <= 833.0f) ? LSM6DSOX_XL_BATCHED_AT_833Hz + : (bdr <= 1660.0f) ? LSM6DSOX_XL_BATCHED_AT_1667Hz + : (bdr <= 3330.0f) ? LSM6DSOX_XL_BATCHED_AT_3333Hz + : LSM6DSOX_XL_BATCHED_AT_6667Hz; + + if (lsm6dsox_fifo_xl_batch_set(&_reg_ctx, new_bdr) != 0) + { + return 1; + } + + return 0; +} + +/** + * @brief Get the LSM6DSOX FIFO gyro single sample (16-bit data per 3 axes) and calculate angular velocity [mDPS] + * @param angular_velocity FIFO gyro axes [mDPS] + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::get_fifo_g_axes(int32_t *angular_velocity) +{ + uint8_t data[6]; + int16_t data_raw[3]; + float sensitivity = 0.0f; + float angular_velocity_float[3]; + + if (get_fifo_data(data) != 0) + { + return 1; + } + + data_raw[0] = ((int16_t)data[1] << 8) | data[0]; + data_raw[1] = ((int16_t)data[3] << 8) | data[2]; + data_raw[2] = ((int16_t)data[5] << 8) | data[4]; + + if (get_g_sensitivity(&sensitivity) != 0) + { + return 1; + } + + angular_velocity_float[0] = (float)data_raw[0] * sensitivity; + angular_velocity_float[1] = (float)data_raw[1] * sensitivity; + angular_velocity_float[2] = (float)data_raw[2] * sensitivity; + + angular_velocity[0] = (int32_t)angular_velocity_float[0]; + angular_velocity[1] = (int32_t)angular_velocity_float[1]; + angular_velocity[2] = (int32_t)angular_velocity_float[2]; + + return 0; +} + +/** + * @brief Set the LSM6DSOX FIFO gyro BDR value + * @param bdr FIFO gyro BDR value + * @retval 0 in case of success, an error code otherwise + */ +int LSM6DSOXSensor::set_fifo_g_bdr(float bdr) +{ + lsm6dsox_bdr_gy_t new_bdr; + + new_bdr = (bdr <= 0.0f) ? LSM6DSOX_GY_NOT_BATCHED + : (bdr <= 12.5f) ? LSM6DSOX_GY_BATCHED_AT_12Hz5 + : (bdr <= 26.0f) ? LSM6DSOX_GY_BATCHED_AT_26Hz + : (bdr <= 52.0f) ? LSM6DSOX_GY_BATCHED_AT_52Hz + : (bdr <= 104.0f) ? LSM6DSOX_GY_BATCHED_AT_104Hz + : (bdr <= 208.0f) ? LSM6DSOX_GY_BATCHED_AT_208Hz + : (bdr <= 416.0f) ? LSM6DSOX_GY_BATCHED_AT_417Hz + : (bdr <= 833.0f) ? LSM6DSOX_GY_BATCHED_AT_833Hz + : (bdr <= 1660.0f) ? LSM6DSOX_GY_BATCHED_AT_1667Hz + : (bdr <= 3330.0f) ? LSM6DSOX_GY_BATCHED_AT_3333Hz + : LSM6DSOX_GY_BATCHED_AT_6667Hz; + + if (lsm6dsox_fifo_gy_batch_set(&_reg_ctx, new_bdr) != 0) + { + return 1; + } + + return 0; +} + + + +int32_t LSM6DSOX_io_write(void *handle, uint8_t WriteAddr, uint8_t *pBuffer, uint16_t nBytesToWrite) +{ + return ((LSM6DSOXSensor *)handle)->io_write(pBuffer, WriteAddr, nBytesToWrite); +} + +int32_t LSM6DSOX_io_read(void *handle, uint8_t ReadAddr, uint8_t *pBuffer, uint16_t nBytesToRead) +{ + return ((LSM6DSOXSensor *)handle)->io_read(pBuffer, ReadAddr, nBytesToRead); +} diff --git a/LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/LSM6DSOX/LSM6DSOXSensor.h b/LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/LSM6DSOX/LSM6DSOXSensor.h new file mode 100644 index 0000000..754e463 --- /dev/null +++ b/LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/LSM6DSOX/LSM6DSOXSensor.h @@ -0,0 +1,319 @@ +/** + ****************************************************************************** + * @file LSM6DSOXSensor.h + * @author SRA + * @version V1.0.0 + * @date February 2019 + * @brief Abstract Class of an LSM6DSOX Inertial Measurement Unit (IMU) 6 axes + * sensor. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + +/* Prevent recursive inclusion -----------------------------------------------*/ + +#ifndef __LSM6DSOXSensor_H__ +#define __LSM6DSOXSensor_H__ + + +/* Includes ------------------------------------------------------------------*/ +#include "DevI2C.h" +#include "lsm6dsox_reg.h" +#include "MotionSensor.h" +#include "GyroSensor.h" +#include + +/* Defines -------------------------------------------------------------------*/ + +#define LSM6DSOX_ACC_SENSITIVITY_FS_2G 0.061f +#define LSM6DSOX_ACC_SENSITIVITY_FS_4G 0.122f +#define LSM6DSOX_ACC_SENSITIVITY_FS_8G 0.244f +#define LSM6DSOX_ACC_SENSITIVITY_FS_16G 0.488f + +#define LSM6DSOX_GYRO_SENSITIVITY_FS_125DPS 4.375f +#define LSM6DSOX_GYRO_SENSITIVITY_FS_250DPS 8.750f +#define LSM6DSOX_GYRO_SENSITIVITY_FS_500DPS 17.500f +#define LSM6DSOX_GYRO_SENSITIVITY_FS_1000DPS 35.000f +#define LSM6DSOX_GYRO_SENSITIVITY_FS_2000DPS 70.000f + + +/* Typedefs ------------------------------------------------------------------*/ + +typedef enum +{ + LSM6DSOX_INT1_PIN, + LSM6DSOX_INT2_PIN, +} LSM6DSOX_Interrupt_Pin_t; + +typedef struct +{ + unsigned int FreeFallStatus : 1; + unsigned int TapStatus : 1; + unsigned int DoubleTapStatus : 1; + unsigned int WakeUpStatus : 1; + unsigned int StepStatus : 1; + unsigned int TiltStatus : 1; + unsigned int D6DOrientationStatus : 1; + unsigned int SleepStatus : 1; +} LSM6DSOX_Event_Status_t; + + +/* Class Declaration ---------------------------------------------------------*/ + +/** + * Abstract class of an LSM6DSOX Inertial Measurement Unit (IMU) 6 axes + * sensor. + */ +class LSM6DSOXSensor : public MotionSensor, public GyroSensor +{ + public: + enum SPI_type_t {SPI3W, SPI4W}; + LSM6DSOXSensor(SPI *spi, PinName cs_pin, PinName int1_pin=NC, PinName int2_pin=NC, SPI_type_t spi_type=SPI4W); + LSM6DSOXSensor(DevI2C *i2c, uint8_t address=LSM6DSOX_I2C_ADD_H, PinName int1_pin=NC, PinName int2_pin=NC); + virtual int init(void *init); + virtual int read_id(uint8_t *id); + virtual int get_x_axes(int32_t *acceleration); + virtual int get_g_axes(int32_t *angular_rate); + virtual int get_x_sensitivity(float *sensitivity); + virtual int get_g_sensitivity(float *sensitivity); + virtual int get_x_axes_raw(int16_t *value); + virtual int get_g_axes_raw(int16_t *value); + virtual int get_x_odr(float *odr); + virtual int get_g_odr(float *odr); + virtual int set_x_odr(float odr); + virtual int set_g_odr(float odr); + virtual int get_x_fs(float *full_scale); + virtual int get_g_fs(float *full_scale); + virtual int set_x_fs(float full_scale); + virtual int set_g_fs(float full_scale); + int enable_x(void); + int enable_g(void); + int disable_x(void); + int disable_g(void); + int enable_free_fall_detection(LSM6DSOX_Interrupt_Pin_t pin = LSM6DSOX_INT1_PIN); + int disable_free_fall_detection(void); + int set_free_fall_threshold(uint8_t thr); + int set_free_fall_duration(uint8_t dur); + int enable_pedometer(void); + int disable_pedometer(void); + int get_step_counter(uint16_t *step_count); + int reset_step_counter(void); + int enable_tilt_detection(LSM6DSOX_Interrupt_Pin_t pin = LSM6DSOX_INT1_PIN); + int disable_tilt_detection(void); + int enable_wake_up_detection(LSM6DSOX_Interrupt_Pin_t pin = LSM6DSOX_INT2_PIN); + int disable_wake_up_detection(void); + int set_wake_up_threshold(uint8_t thr); + int set_wake_up_duration(uint8_t dur); + int enable_single_tap_detection(LSM6DSOX_Interrupt_Pin_t pin = LSM6DSOX_INT1_PIN); + int disable_single_tap_detection(void); + int enable_double_tap_detection(LSM6DSOX_Interrupt_Pin_t pin = LSM6DSOX_INT1_PIN); + int disable_double_tap_detection(void); + int set_tap_threshold(uint8_t thr); + int set_tap_shock_time(uint8_t time); + int set_tap_quiet_time(uint8_t time); + int set_tap_duration_time(uint8_t time); + int enable_6d_orientation(LSM6DSOX_Interrupt_Pin_t pin = LSM6DSOX_INT1_PIN); + int disable_6d_orientation(void); + int set_6d_orientation_threshold(uint8_t thr); + int get_6d_orientation_xl(uint8_t *xl); + int get_6d_orientation_xh(uint8_t *xh); + int get_6d_orientation_yl(uint8_t *yl); + int get_6d_orientation_yh(uint8_t *yh); + int get_6d_orientation_zl(uint8_t *zl); + int get_6d_orientation_zh(uint8_t *zh); + int get_event_status(LSM6DSOX_Event_Status_t *status); + int read_reg(uint8_t reg, uint8_t *data); + int write_reg(uint8_t reg, uint8_t data); + int set_interrupt_latch(uint8_t status); + int get_x_drdy_status(uint8_t *status); + int set_x_self_test(uint8_t status); + int get_g_drdy_status(uint8_t *status); + int set_g_self_test(uint8_t status); + int get_fifo_num_samples(uint16_t *num_samples); + int get_fifo_full_status(uint8_t *status); + int set_fifo_int1_fifo_full(uint8_t status); + int set_fifo_watermark_level(uint16_t watermark); + int set_fifo_stop_on_fth(uint8_t status); + int set_fifo_mode(uint8_t mode); + int get_fifo_tag(uint8_t *tag); + int get_fifo_data(uint8_t *data); + int get_fifo_x_axes(int32_t *acceleration); + int set_fifo_x_bdr(float bdr); + int get_fifo_g_axes(int32_t *angular_velocity); + int set_fifo_g_bdr(float bdr); + + /** + * @brief Attaching an interrupt handler to the INT1 interrupt. + * @param fptr An interrupt handler. + * @retval None. + */ + void attach_int1_irq(void (*fptr)(void)) + { + _int1_irq.rise(fptr); + } + + /** + * @brief Enabling the INT1 interrupt handling. + * @param None. + * @retval None. + */ + void enable_int1_irq(void) + { + _int1_irq.enable_irq(); + } + + /** + * @brief Disabling the INT1 interrupt handling. + * @param None. + * @retval None. + */ + void disable_int1_irq(void) + { + _int1_irq.disable_irq(); + } + + /** + * @brief Attaching an interrupt handler to the INT2 interrupt. + * @param fptr An interrupt handler. + * @retval None. + */ + void attach_int2_irq(void (*fptr)(void)) + { + _int2_irq.rise(fptr); + } + + /** + * @brief Enabling the INT2 interrupt handling. + * @param None. + * @retval None. + */ + void enable_int2_irq(void) + { + _int2_irq.enable_irq(); + } + + /** + * @brief Disabling the INT2 interrupt handling. + * @param None. + * @retval None. + */ + void disable_int2_irq(void) + { + _int2_irq.disable_irq(); + } + + /** + * @brief Utility function to read data. + * @param pBuffer: pointer to data to be read. + * @param RegisterAddr: specifies internal address register to be read. + * @param NumByteToRead: number of bytes to be read. + * @retval 0 if ok, an error code otherwise. + */ + uint8_t io_read(uint8_t* pBuffer, uint8_t RegisterAddr, uint16_t NumByteToRead) + { + if (_dev_spi) { + /* Write Reg Address */ + _dev_spi->lock(); + _cs_pin = 0; + if (_spi_type == SPI4W) { + _dev_spi->write(RegisterAddr | 0x80); + for (int i=0; iwrite(0x00); + } + } else if (_spi_type == SPI3W){ + /* Write RD Reg Address with RD bit*/ + uint8_t TxByte = RegisterAddr | 0x80; + _dev_spi->write((char *)&TxByte, 1, (char *)pBuffer, (int) NumByteToRead); + } + _cs_pin = 1; + _dev_spi->unlock(); + return 0; + } + if (_dev_i2c) return (uint8_t) _dev_i2c->i2c_read(pBuffer, _address, RegisterAddr, NumByteToRead); + return 1; + } + + /** + * @brief Utility function to write data. + * @param pBuffer: pointer to data to be written. + * @param RegisterAddr: specifies internal address register to be written. + * @param NumByteToWrite: number of bytes to write. + * @retval 0 if ok, an error code otherwise. + */ + uint8_t io_write(uint8_t* pBuffer, uint8_t RegisterAddr, uint16_t NumByteToWrite) + { + if (_dev_spi) { + _dev_spi->lock(); + _cs_pin = 0; + _dev_spi->write(RegisterAddr); + _dev_spi->write((char *)pBuffer, (int) NumByteToWrite, NULL, 0); + _cs_pin = 1; + _dev_spi->unlock(); + return 0; + } + if (_dev_i2c) return (uint8_t) _dev_i2c->i2c_write(pBuffer, _address, RegisterAddr, NumByteToWrite); + return 1; + } + + private: + int set_x_odr_when_enabled(float odr); + int set_g_odr_when_enabled(float odr); + int set_x_odr_when_disabled(float odr); + int set_g_odr_when_disabled(float odr); + + /* Helper classes. */ + DevI2C *_dev_i2c; + SPI *_dev_spi; + + /* Configuration */ + uint8_t _address; + DigitalOut _cs_pin; + InterruptIn _int1_irq; + InterruptIn _int2_irq; + SPI_type_t _spi_type; + + uint8_t _x_is_enabled; + lsm6dsox_odr_xl_t _x_last_odr; + uint8_t _g_is_enabled; + lsm6dsox_odr_g_t _g_last_odr; + + lsm6dsox_ctx_t _reg_ctx; +}; + +#ifdef __cplusplus + extern "C" { +#endif +int32_t LSM6DSOX_io_write( void *handle, uint8_t WriteAddr, uint8_t *pBuffer, uint16_t nBytesToWrite ); +int32_t LSM6DSOX_io_read( void *handle, uint8_t ReadAddr, uint8_t *pBuffer, uint16_t nBytesToRead ); +#ifdef __cplusplus + } +#endif + +#endif diff --git a/LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/LSM6DSOX/lsm6dsox_reg.c b/LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/LSM6DSOX/lsm6dsox_reg.c new file mode 100644 index 0000000..853f9e8 --- /dev/null +++ b/LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/LSM6DSOX/lsm6dsox_reg.c @@ -0,0 +1,9520 @@ +/* + ****************************************************************************** + * @file lsm6dsox_reg.c + * @author Sensor Solutions Software Team + * @brief LSM6DSOX driver file + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +#include "lsm6dsox_reg.h" + +/** + * @defgroup LSM6DSOX + * @brief This file provides a set of functions needed to drive the + * lsm6dsox enhanced inertial module. + * @{ + * +*/ + +/** + * @defgroup LSM6DSOX_Interfaces_Functions + * @brief This section provide a set of functions used to read and + * write a generic register of the device. + * MANDATORY: return 0 -> no Error. + * @{ + * + */ + +/** + * @brief Read generic device register + * + * @param ctx read / write interface definitions(ptr) + * @param reg register to read + * @param data pointer to buffer that store the data read(ptr) + * @param len number of consecutive register to read + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsox_read_reg(lsm6dsox_ctx_t* ctx, uint8_t reg, uint8_t* data, + uint16_t len) +{ + int32_t ret; + ret = ctx->read_reg(ctx->handle, reg, data, len); + return ret; +} + +/** + * @brief Write generic device register + * + * @param ctx read / write interface definitions(ptr) + * @param reg register to write + * @param data pointer to data to write in register reg(ptr) + * @param len number of consecutive register to write + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsox_write_reg(lsm6dsox_ctx_t* ctx, uint8_t reg, uint8_t* data, + uint16_t len) +{ + int32_t ret; + ret = ctx->write_reg(ctx->handle, reg, data, len); + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DSOX_Sensitivity + * @brief These functions convert raw-data into engineering units. + * @{ + * + */ +float_t lsm6dsox_from_fs2_to_mg(int16_t lsb) +{ + return ((float_t)lsb) * 0.061f; +} + +float_t lsm6dsox_from_fs4_to_mg(int16_t lsb) +{ + return ((float_t)lsb) * 0.122f; +} + +float_t lsm6dsox_from_fs8_to_mg(int16_t lsb) +{ + return ((float_t)lsb) * 0.244f; +} + +float_t lsm6dsox_from_fs16_to_mg(int16_t lsb) +{ + return ((float_t)lsb) *0.488f; +} + +float_t lsm6dsox_from_fs125_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) *4.375f; +} + +float_t lsm6dsox_from_fs500_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) *17.50f; +} + +float_t lsm6dsox_from_fs250_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) *8.750f; +} + +float_t lsm6dsox_from_fs1000_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) *35.0f; +} + +float_t lsm6dsox_from_fs2000_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) *70.0f; +} + +float_t lsm6dsox_from_lsb_to_celsius(int16_t lsb) +{ + return (((float_t)lsb / 256.0f) + 25.0f); +} + +float_t lsm6dsox_from_lsb_to_nsec(int16_t lsb) +{ + return ((float_t)lsb * 25000.0f); +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DSOX_Data_Generation + * @brief This section groups all the functions concerning + * data generation. + * + */ + +/** + * @brief Accelerometer full-scale selection.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of fs_xl in reg CTRL1_XL + * + */ +int32_t lsm6dsox_xl_full_scale_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_fs_xl_t val) +{ + lsm6dsox_ctrl1_xl_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t*)®, 1); + if (ret == 0) { + reg.fs_xl = (uint8_t) val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Accelerometer full-scale selection.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of fs_xl in reg CTRL1_XL + * + */ +int32_t lsm6dsox_xl_full_scale_get(lsm6dsox_ctx_t *ctx, lsm6dsox_fs_xl_t *val) +{ + lsm6dsox_ctrl1_xl_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t*)®, 1); + switch (reg.fs_xl) { + case LSM6DSOX_2g: + *val = LSM6DSOX_2g; + break; + case LSM6DSOX_16g: + *val = LSM6DSOX_16g; + break; + case LSM6DSOX_4g: + *val = LSM6DSOX_4g; + break; + case LSM6DSOX_8g: + *val = LSM6DSOX_8g; + break; + default: + *val = LSM6DSOX_2g; + break; + } + + return ret; +} + +/** + * @brief Accelerometer UI data rate selection.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of odr_xl in reg CTRL1_XL + * + */ +int32_t lsm6dsox_xl_data_rate_set(lsm6dsox_ctx_t *ctx, lsm6dsox_odr_xl_t val) +{ + lsm6dsox_ctrl1_xl_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t*)®, 1); + if (ret == 0) { + reg.odr_xl = (uint8_t) val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Accelerometer UI data rate selection.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of odr_xl in reg CTRL1_XL + * + */ +int32_t lsm6dsox_xl_data_rate_get(lsm6dsox_ctx_t *ctx, lsm6dsox_odr_xl_t *val) +{ + lsm6dsox_ctrl1_xl_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t*)®, 1); + + switch (reg.odr_xl) { + case LSM6DSOX_XL_ODR_OFF: + *val = LSM6DSOX_XL_ODR_OFF; + break; + case LSM6DSOX_XL_ODR_12Hz5: + *val = LSM6DSOX_XL_ODR_12Hz5; + break; + case LSM6DSOX_XL_ODR_26Hz: + *val = LSM6DSOX_XL_ODR_26Hz; + break; + case LSM6DSOX_XL_ODR_52Hz: + *val = LSM6DSOX_XL_ODR_52Hz; + break; + case LSM6DSOX_XL_ODR_104Hz: + *val = LSM6DSOX_XL_ODR_104Hz; + break; + case LSM6DSOX_XL_ODR_208Hz: + *val = LSM6DSOX_XL_ODR_208Hz; + break; + case LSM6DSOX_XL_ODR_417Hz: + *val = LSM6DSOX_XL_ODR_417Hz; + break; + case LSM6DSOX_XL_ODR_833Hz: + *val = LSM6DSOX_XL_ODR_833Hz; + break; + case LSM6DSOX_XL_ODR_1667Hz: + *val = LSM6DSOX_XL_ODR_1667Hz; + break; + case LSM6DSOX_XL_ODR_3333Hz: + *val = LSM6DSOX_XL_ODR_3333Hz; + break; + case LSM6DSOX_XL_ODR_6667Hz: + *val = LSM6DSOX_XL_ODR_6667Hz; + break; + case LSM6DSOX_XL_ODR_6Hz5: + *val = LSM6DSOX_XL_ODR_6Hz5; + break; + default: + *val = LSM6DSOX_XL_ODR_OFF; + break; + } + return ret; +} + +/** + * @brief Gyroscope UI chain full-scale selection.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of fs_g in reg CTRL2_G + * + */ +int32_t lsm6dsox_gy_full_scale_set(lsm6dsox_ctx_t *ctx, lsm6dsox_fs_g_t val) +{ + lsm6dsox_ctrl2_g_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL2_G, (uint8_t*)®, 1); + if (ret == 0) { + reg.fs_g = (uint8_t) val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL2_G, (uint8_t*)®, 1); + } + + return ret; +} + +/** + * @brief Gyroscope UI chain full-scale selection.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of fs_g in reg CTRL2_G + * + */ +int32_t lsm6dsox_gy_full_scale_get(lsm6dsox_ctx_t *ctx, lsm6dsox_fs_g_t *val) +{ + lsm6dsox_ctrl2_g_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL2_G, (uint8_t*)®, 1); + switch (reg.fs_g) { + case LSM6DSOX_250dps: + *val = LSM6DSOX_250dps; + break; + case LSM6DSOX_125dps: + *val = LSM6DSOX_125dps; + break; + case LSM6DSOX_500dps: + *val = LSM6DSOX_500dps; + break; + case LSM6DSOX_1000dps: + *val = LSM6DSOX_1000dps; + break; + case LSM6DSOX_2000dps: + *val = LSM6DSOX_2000dps; + break; + default: + *val = LSM6DSOX_250dps; + break; + } + + return ret; +} + +/** + * @brief Gyroscope UI data rate selection.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of odr_g in reg CTRL2_G + * + */ +int32_t lsm6dsox_gy_data_rate_set(lsm6dsox_ctx_t *ctx, lsm6dsox_odr_g_t val) +{ + lsm6dsox_ctrl2_g_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL2_G, (uint8_t*)®, 1); + if (ret == 0) { + reg.odr_g = (uint8_t) val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL2_G, (uint8_t*)®, 1); + } + + return ret; +} + +/** + * @brief Gyroscope UI data rate selection.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of odr_g in reg CTRL2_G + * + */ +int32_t lsm6dsox_gy_data_rate_get(lsm6dsox_ctx_t *ctx, lsm6dsox_odr_g_t *val) +{ + lsm6dsox_ctrl2_g_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL2_G, (uint8_t*)®, 1); + switch (reg.odr_g) { + case LSM6DSOX_GY_ODR_OFF: + *val = LSM6DSOX_GY_ODR_OFF; + break; + case LSM6DSOX_GY_ODR_12Hz5: + *val = LSM6DSOX_GY_ODR_12Hz5; + break; + case LSM6DSOX_GY_ODR_26Hz: + *val = LSM6DSOX_GY_ODR_26Hz; + break; + case LSM6DSOX_GY_ODR_52Hz: + *val = LSM6DSOX_GY_ODR_52Hz; + break; + case LSM6DSOX_GY_ODR_104Hz: + *val = LSM6DSOX_GY_ODR_104Hz; + break; + case LSM6DSOX_GY_ODR_208Hz: + *val = LSM6DSOX_GY_ODR_208Hz; + break; + case LSM6DSOX_GY_ODR_417Hz: + *val = LSM6DSOX_GY_ODR_417Hz; + break; + case LSM6DSOX_GY_ODR_833Hz: + *val = LSM6DSOX_GY_ODR_833Hz; + break; + case LSM6DSOX_GY_ODR_1667Hz: + *val = LSM6DSOX_GY_ODR_1667Hz; + break; + case LSM6DSOX_GY_ODR_3333Hz: + *val = LSM6DSOX_GY_ODR_3333Hz; + break; + case LSM6DSOX_GY_ODR_6667Hz: + *val = LSM6DSOX_GY_ODR_6667Hz; + break; + default: + *val = LSM6DSOX_GY_ODR_OFF; + break; + } + return ret; +} + +/** + * @brief Block data update.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of bdu in reg CTRL3_C + * + */ +int32_t lsm6dsox_block_data_update_set(lsm6dsox_ctx_t *ctx, uint8_t val) +{ + lsm6dsox_ctrl3_c_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1); + if (ret == 0) { + reg.bdu = val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Block data update.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of bdu in reg CTRL3_C + * + */ +int32_t lsm6dsox_block_data_update_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_ctrl3_c_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1); + *val = reg.bdu; + + return ret; +} + +/** + * @brief Weight of XL user offset bits of registers X_OFS_USR (73h), + * Y_OFS_USR (74h), Z_OFS_USR (75h).[set] + * + * @param ctx read / write interface definitions + * @param val change the values of usr_off_w in reg CTRL6_C + * + */ +int32_t lsm6dsox_xl_offset_weight_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_usr_off_w_t val) +{ + lsm6dsox_ctrl6_c_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*)®, 1); + if (ret == 0) { + reg.usr_off_w = (uint8_t)val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Weight of XL user offset bits of registers X_OFS_USR (73h), + * Y_OFS_USR (74h), Z_OFS_USR (75h).[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of usr_off_w in reg CTRL6_C + * + */ +int32_t lsm6dsox_xl_offset_weight_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_usr_off_w_t *val) +{ + lsm6dsox_ctrl6_c_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*)®, 1); + + switch (reg.usr_off_w) { + case LSM6DSOX_LSb_1mg: + *val = LSM6DSOX_LSb_1mg; + break; + case LSM6DSOX_LSb_16mg: + *val = LSM6DSOX_LSb_16mg; + break; + default: + *val = LSM6DSOX_LSb_1mg; + break; + } + return ret; +} + +/** + * @brief Accelerometer power mode.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of xl_hm_mode in + * reg CTRL6_C + * + */ +int32_t lsm6dsox_xl_power_mode_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_xl_hm_mode_t val) +{ + lsm6dsox_ctrl5_c_t ctrl5_c; + lsm6dsox_ctrl6_c_t ctrl6_c; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*) &ctrl5_c, 1); + if (ret == 0) { + ctrl5_c.xl_ulp_en = ((uint8_t)val & 0x02U) >> 1; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*) &ctrl5_c, 1); + } + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*) &ctrl6_c, 1); + } + if (ret == 0) { + ctrl6_c.xl_hm_mode = (uint8_t)val & 0x01U; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*) &ctrl6_c, 1); + } + return ret; +} + +/** + * @brief Accelerometer power mode.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of xl_hm_mode in reg CTRL6_C + * + */ +int32_t lsm6dsox_xl_power_mode_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_xl_hm_mode_t *val) +{ + lsm6dsox_ctrl5_c_t ctrl5_c; + lsm6dsox_ctrl6_c_t ctrl6_c; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*) &ctrl5_c, 1); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*) &ctrl6_c, 1); + switch ( (ctrl5_c.xl_ulp_en << 1) | ctrl6_c.xl_hm_mode) { + case LSM6DSOX_HIGH_PERFORMANCE_MD: + *val = LSM6DSOX_HIGH_PERFORMANCE_MD; + break; + case LSM6DSOX_LOW_NORMAL_POWER_MD: + *val = LSM6DSOX_LOW_NORMAL_POWER_MD; + break; + case LSM6DSOX_ULTRA_LOW_POWER_MD: + *val = LSM6DSOX_ULTRA_LOW_POWER_MD; + break; + default: + *val = LSM6DSOX_HIGH_PERFORMANCE_MD; + break; + } + } + return ret; +} + +/** + * @brief Operating mode for gyroscope.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of g_hm_mode in reg CTRL7_G + * + */ +int32_t lsm6dsox_gy_power_mode_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_g_hm_mode_t val) +{ + lsm6dsox_ctrl7_g_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)®, 1); + if (ret == 0) { + reg.g_hm_mode = (uint8_t)val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Operating mode for gyroscope.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of g_hm_mode in reg CTRL7_G + * + */ +int32_t lsm6dsox_gy_power_mode_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_g_hm_mode_t *val) +{ + lsm6dsox_ctrl7_g_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)®, 1); + switch (reg.g_hm_mode) { + case LSM6DSOX_GY_HIGH_PERFORMANCE: + *val = LSM6DSOX_GY_HIGH_PERFORMANCE; + break; + case LSM6DSOX_GY_NORMAL: + *val = LSM6DSOX_GY_NORMAL; + break; + default: + *val = LSM6DSOX_GY_HIGH_PERFORMANCE; + break; + } + return ret; +} + +/** + * @brief Read all the interrupt flag of the device.[get] + * + * @param ctx read / write interface definitions + * @param val registers ALL_INT_SRC; WAKE_UP_SRC; + * TAP_SRC; D6D_SRC; STATUS_REG; + * EMB_FUNC_STATUS; FSM_STATUS_A/B + * + */ +int32_t lsm6dsox_all_sources_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_all_sources_t *val) +{ + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_ALL_INT_SRC, + (uint8_t*)&val->all_int_src, 1); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_SRC, + (uint8_t*)&val->wake_up_src, 1); + } + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_SRC, + (uint8_t*)&val->tap_src, 1); + } + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_D6D_SRC, + (uint8_t*)&val->d6d_src, 1); + } + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_STATUS_REG, + (uint8_t*)&val->status_reg, 1); + } + if (ret == 0) { + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); + } + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_STATUS, + (uint8_t*)&val->emb_func_status, 1); + } + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_STATUS_A, + (uint8_t*)&val->fsm_status_a, 1); + } + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_STATUS_B, + (uint8_t*)&val->fsm_status_b, 1); + } + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MLC_STATUS, + (uint8_t*)&val->mlc_status, 1); + } + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + + return ret; +} + +/** + * @brief The STATUS_REG register is read by the primary interface.[get] + * + * @param ctx read / write interface definitions + * @param val register STATUS_REG + * + */ +int32_t lsm6dsox_status_reg_get(lsm6dsox_ctx_t *ctx, lsm6dsox_status_reg_t *val) +{ + int32_t ret; + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_STATUS_REG, (uint8_t*) val, 1); + return ret; +} + +/** + * @brief Accelerometer new data available.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of xlda in reg STATUS_REG + * + */ +int32_t lsm6dsox_xl_flag_data_ready_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_status_reg_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_STATUS_REG, (uint8_t*)®, 1); + *val = reg.xlda; + + return ret; +} + +/** + * @brief Gyroscope new data available.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of gda in reg STATUS_REG + * + */ +int32_t lsm6dsox_gy_flag_data_ready_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_status_reg_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_STATUS_REG, (uint8_t*)®, 1); + *val = reg.gda; + + return ret; +} + +/** + * @brief Temperature new data available.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of tda in reg STATUS_REG + * + */ +int32_t lsm6dsox_temp_flag_data_ready_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_status_reg_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_STATUS_REG, (uint8_t*)®, 1); + *val = reg.tda; + + return ret; +} + +/** + * @brief Accelerometer X-axis user offset correction expressed in + * two’s complement, weight depends on USR_OFF_W in CTRL6_C (15h). + * The value must be in the range [-127 127].[set] + * + * @param ctx read / write interface definitions + * @param buff buffer that contains data to write + * + */ +int32_t lsm6dsox_xl_usr_offset_x_set(lsm6dsox_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_X_OFS_USR, buff, 1); + return ret; +} + +/** + * @brief Accelerometer X-axis user offset correction expressed in two’s + * complement, weight depends on USR_OFF_W in CTRL6_C (15h). + * The value must be in the range [-127 127].[get] + * + * @param ctx read / write interface definitions + * @param buff buffer that stores data read + * + */ +int32_t lsm6dsox_xl_usr_offset_x_get(lsm6dsox_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_X_OFS_USR, buff, 1); + return ret; +} + +/** + * @brief Accelerometer Y-axis user offset correction expressed in two’s + * complement, weight depends on USR_OFF_W in CTRL6_C (15h). + * The value must be in the range [-127 127].[set] + * + * @param ctx read / write interface definitions + * @param buff buffer that contains data to write + * + */ +int32_t lsm6dsox_xl_usr_offset_y_set(lsm6dsox_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_Y_OFS_USR, buff, 1); + return ret; +} + +/** + * @brief Accelerometer Y-axis user offset correction expressed in two’s + * complement, weight depends on USR_OFF_W in CTRL6_C (15h). + * The value must be in the range [-127 127].[get] + * + * @param ctx read / write interface definitions + * @param buff buffer that stores data read + * + */ +int32_t lsm6dsox_xl_usr_offset_y_get(lsm6dsox_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_Y_OFS_USR, buff, 1); + return ret; +} + +/** + * @brief Accelerometer Z-axis user offset correction expressed in two’s + * complement, weight depends on USR_OFF_W in CTRL6_C (15h). + * The value must be in the range [-127 127].[set] + * + * @param ctx read / write interface definitions + * @param buff buffer that contains data to write + * + */ +int32_t lsm6dsox_xl_usr_offset_z_set(lsm6dsox_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_Z_OFS_USR, buff, 1); + return ret; +} + +/** + * @brief Accelerometer Z-axis user offset correction expressed in two’s + * complement, weight depends on USR_OFF_W in CTRL6_C (15h). + * The value must be in the range [-127 127].[get] + * + * @param ctx read / write interface definitions + * @param buff buffer that stores data read + * + */ +int32_t lsm6dsox_xl_usr_offset_z_get(lsm6dsox_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_Z_OFS_USR, buff, 1); + return ret; +} + +/** + * @brief Enables user offset on out.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of usr_off_on_out in reg CTRL7_G + * + */ +int32_t lsm6dsox_xl_usr_offset_set(lsm6dsox_ctx_t *ctx, uint8_t val) +{ + lsm6dsox_ctrl7_g_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)®, 1); + if (ret == 0) { + reg.usr_off_on_out = val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief User offset on out flag.[get] + * + * @param ctx read / write interface definitions + * @param val values of usr_off_on_out in reg CTRL7_G + * + */ +int32_t lsm6dsox_xl_usr_offset_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_ctrl7_g_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)®, 1); + *val = reg.usr_off_on_out; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DSOX_Timestamp + * @brief This section groups all the functions that manage the + * timestamp generation. + * @{ + * + */ + +/** + * @brief Enables timestamp counter.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of timestamp_en in reg CTRL10_C + * + */ +int32_t lsm6dsox_timestamp_set(lsm6dsox_ctx_t *ctx, uint8_t val) +{ + lsm6dsox_ctrl10_c_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL10_C, (uint8_t*)®, 1); + if (ret == 0) { + reg.timestamp_en = val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL10_C, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Enables timestamp counter.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of timestamp_en in reg CTRL10_C + * + */ +int32_t lsm6dsox_timestamp_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_ctrl10_c_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL10_C, (uint8_t*)®, 1); + *val = reg.timestamp_en; + + return ret; +} + +/** + * @brief Timestamp first data output register (r). + * The value is expressed as a 32-bit word and the bit + * resolution is 25 μs.[get] + * + * @param ctx read / write interface definitions + * @param buff buffer that stores data read + * + */ +int32_t lsm6dsox_timestamp_raw_get(lsm6dsox_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TIMESTAMP0, buff, 4); + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DSOX_Data output + * @brief This section groups all the data output functions. + * @{ + * + */ + +/** + * @brief Circular burst-mode (rounding) read of the output + * registers.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of rounding in reg CTRL5_C + * + */ +int32_t lsm6dsox_rounding_mode_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_rounding_t val) +{ + lsm6dsox_ctrl5_c_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)®, 1); + if (ret == 0) { + reg.rounding = (uint8_t)val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Gyroscope UI chain full-scale selection.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of rounding in reg CTRL5_C + * + */ +int32_t lsm6dsox_rounding_mode_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_rounding_t *val) +{ + lsm6dsox_ctrl5_c_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)®, 1); + switch (reg.rounding) { + case LSM6DSOX_NO_ROUND: + *val = LSM6DSOX_NO_ROUND; + break; + case LSM6DSOX_ROUND_XL: + *val = LSM6DSOX_ROUND_XL; + break; + case LSM6DSOX_ROUND_GY: + *val = LSM6DSOX_ROUND_GY; + break; + case LSM6DSOX_ROUND_GY_XL: + *val = LSM6DSOX_ROUND_GY_XL; + break; + default: + *val = LSM6DSOX_NO_ROUND; + break; + } + return ret; +} + +/** + * @brief rounding_on_status: [set] Source register rounding function in + * ALL_INT_SRC (1Ah), WAKE_UP_SRC(1Bh), + * TAP_SRC (1Ch), D6D_SRC (1Dh), + * STATUS_REG (1Eh) and + * EMB_FUNC_STATUS_MAINPAGE(35h), + * FSM_STATUS_A_MAINPAGE (36h), + * FSM_STATUS_B_MAINPAGE (37h), + * MLC_STATUS_MAINPAGE (38h), + * STATUS_MASTER_MAINPAGE (39h), + * FIFO_STATUS1 (3Ah), FIFO_STATUS2(3Bh). + * + * @param ctx read / write interface definitions + * @param lsm6dsox_rounding_status_t: change the values of rounding_status + * in reg CTRL7_G + * + */ +int32_t lsm6dsox_rounding_on_status_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_rounding_status_t val) +{ + lsm6dsox_ctrl5_c_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)®, 1); + if (ret == 0) { + reg.rounding_status = (uint8_t)val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)®, 1); + } + + return ret; +} + +/** + * @brief rounding_on_status: [get] Source register rounding function in + * ALL_INT_SRC (1Ah), WAKE_UP_SRC(1Bh), + * TAP_SRC (1Ch), D6D_SRC (1Dh), + * STATUS_REG (1Eh) and + * EMB_FUNC_STATUS_MAINPAGE(35h), + * FSM_STATUS_A_MAINPAGE (36h), + * FSM_STATUS_B_MAINPAGE (37h), + * MLC_STATUS_MAINPAGE (38h), + * STATUS_MASTER_MAINPAGE (39h), + * FIFO_STATUS1 (3Ah), FIFO_STATUS2(3Bh). + * + * @param ctx read / write interface definitions + * @param lsm6dsox_rounding_status_t: Get the values of rounding_status + * in reg CTRL7_G + * + */ +int32_t lsm6dsox_rounding_on_status_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_rounding_status_t *val) +{ + lsm6dsox_ctrl5_c_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)®, 1); + switch (reg.rounding_status) { + case LSM6DSOX_STAT_RND_DISABLE: + *val = LSM6DSOX_STAT_RND_DISABLE; + break; + case LSM6DSOX_STAT_RND_ENABLE: + *val = LSM6DSOX_STAT_RND_ENABLE; + break; + default: + *val = LSM6DSOX_STAT_RND_DISABLE; + break; + } + return ret; +} + +/** + * @brief Temperature data output register (r). + * L and H registers together express a 16-bit word in two’s + * complement.[get] + * + * @param ctx read / write interface definitions + * @param buff buffer that stores data read + * + */ +int32_t lsm6dsox_temperature_raw_get(lsm6dsox_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_OUT_TEMP_L, buff, 2); + return ret; +} + +/** + * @brief Angular rate sensor. The value is expressed as a 16-bit + * word in two’s complement.[get] + * + * @param ctx read / write interface definitions + * @param buff buffer that stores data read + * + */ +int32_t lsm6dsox_angular_rate_raw_get(lsm6dsox_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_OUTX_L_G, buff, 6); + return ret; +} + +/** + * @brief Linear acceleration output register. + * The value is expressed as a 16-bit word in two’s complement.[get] + * + * @param ctx read / write interface definitions + * @param buff buffer that stores data read + * + */ +int32_t lsm6dsox_acceleration_raw_get(lsm6dsox_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_OUTX_L_A, buff, 6); + return ret; +} + +/** + * @brief FIFO data output [get] + * + * @param ctx read / write interface definitions + * @param buff buffer that stores data read + * + */ +int32_t lsm6dsox_fifo_out_raw_get(lsm6dsox_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_DATA_OUT_X_L, buff, 6); + return ret; +} + +/** + * @brief ois_angular_rate_raw: [get] OIS angular rate sensor. + * The value is expressed as a + * 16-bit word in two’s complement. + * + * @param ctx read / write interface definitions + * @param uint8_t * : buffer that stores data read + * + */ +int32_t lsm6dsox_ois_angular_rate_raw_get(lsm6dsox_ctx_t *ctx, uint8_t *buff) +{ + return lsm6dsox_read_reg(ctx, LSM6DSOX_UI_OUTX_L_G_OIS, buff, 6); +} + +/** + * @brief ois_acceleration_raw: [get] OIS Linear acceleration output register. + * The value is expressed as a + * 16-bit word in two’s complement. + * + * @param ctx read / write interface definitions + * @param uint8_t * : buffer that stores data read + * + */ +int32_t lsm6dsox_ois_acceleration_raw_get(lsm6dsox_ctx_t *ctx, uint8_t *buff) +{ + return lsm6dsox_read_reg(ctx, LSM6DSOX_UI_OUTX_L_A_OIS, buff, 6); +} + +/** + * @brief aux_temperature_raw: [get] Temperature from auxiliary + * interface. + * The value is expressed as a + * 16-bit word in two’s complement. + * + * @param ctx read / write interface definitions + * @param uint8_t * : buffer that stores data read + * + */ +int32_t lsm6dsox_aux_temperature_raw_get(lsm6dsox_ctx_t *ctx, uint8_t *buff) +{ + return lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_OUT_TEMP_L, buff, 2); +} + +/** + * @brief aux_ois_angular_rate_raw: [get] OIS angular rate sensor from + * auxiliary interface. + * The value is expressed as a + * 16-bit word in two’s complement. + * + * @param ctx read / write interface definitions + * @param uint8_t * : buffer that stores data read + * + */ +int32_t lsm6dsox_aux_ois_angular_rate_raw_get(lsm6dsox_ctx_t *ctx, uint8_t *buff) +{ + return lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_OUTX_L_G_OIS, buff, 6); +} + +/** + * @brief aux_ois_acceleration_raw: [get] OIS linear acceleration output + * register from auxiliary interface. + * The value is expressed as a + * 16-bit word in two’s complement. + * + * @param ctx read / write interface definitions + * @param uint8_t * : buffer that stores data read + * + */ +int32_t lsm6dsox_aux_ois_acceleration_raw_get(lsm6dsox_ctx_t *ctx, uint8_t *buff) +{ + return lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_OUTX_L_A_OIS, buff, 6); +} + +/** + * @brief Step counter output register.[get] + * + * @param ctx read / write interface definitions + * @param buff buffer that stores data read + * + */ +int32_t lsm6dsox_number_of_steps_get(lsm6dsox_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_STEP_COUNTER_L, buff, 2); + } + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + return ret; +} + +/** + * @brief Reset step counter register.[get] + * + * @param ctx read / write interface definitions + * + */ +int32_t lsm6dsox_steps_reset(lsm6dsox_ctx_t *ctx) +{ + lsm6dsox_emb_func_src_t reg; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_SRC, (uint8_t*)®, 1); + } + if (ret == 0) { + reg.pedo_rst_step = PROPERTY_ENABLE; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_SRC, (uint8_t*)®, 1); + } + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + return ret; +} + +/** + * @brief prgsens_out: [get] Output value of all MLCx decision trees. + * + * @param ctx_t *ctx: read / write interface definitions + * @param uint8_t * : buffer that stores data read + * + */ +int32_t lsm6dsox_mlc_out_get(lsm6dsox_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MLC0_SRC, buff, 8); + } + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DSOX_common + * @brief This section groups common usefull functions. + * @{ + * + */ + +/** + * @brief Difference in percentage of the effective ODR(and timestamp rate) + * with respect to the typical. + * Step: 0.15%. 8-bit format, 2's complement.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of freq_fine in reg + * INTERNAL_FREQ_FINE + * + */ +int32_t lsm6dsox_odr_cal_reg_set(lsm6dsox_ctx_t *ctx, uint8_t val) +{ + lsm6dsox_internal_freq_fine_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INTERNAL_FREQ_FINE, (uint8_t*)®, 1); + if (ret == 0) { + reg.freq_fine = val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_INTERNAL_FREQ_FINE, + (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Difference in percentage of the effective ODR(and timestamp rate) + * with respect to the typical. + * Step: 0.15%. 8-bit format, 2's complement.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of freq_fine in reg INTERNAL_FREQ_FINE + * + */ +int32_t lsm6dsox_odr_cal_reg_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_internal_freq_fine_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INTERNAL_FREQ_FINE, (uint8_t*)®, 1); + *val = reg.freq_fine; + + return ret; +} + + +/** + * @brief Enable access to the embedded functions/sensor + * hub configuration registers.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of reg_access in + * reg FUNC_CFG_ACCESS + * + */ +int32_t lsm6dsox_mem_bank_set(lsm6dsox_ctx_t *ctx, lsm6dsox_reg_access_t val) +{ + lsm6dsox_func_cfg_access_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS, (uint8_t*)®, 1); + if (ret == 0) { + reg.reg_access = (uint8_t)val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Enable access to the embedded functions/sensor + * hub configuration registers.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of reg_access in + * reg FUNC_CFG_ACCESS + * + */ +int32_t lsm6dsox_mem_bank_get(lsm6dsox_ctx_t *ctx, lsm6dsox_reg_access_t *val) +{ + lsm6dsox_func_cfg_access_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS, (uint8_t*)®, 1); + switch (reg.reg_access) { + case LSM6DSOX_USER_BANK: + *val = LSM6DSOX_USER_BANK; + break; + case LSM6DSOX_SENSOR_HUB_BANK: + *val = LSM6DSOX_SENSOR_HUB_BANK; + break; + case LSM6DSOX_EMBEDDED_FUNC_BANK: + *val = LSM6DSOX_EMBEDDED_FUNC_BANK; + break; + default: + *val = LSM6DSOX_USER_BANK; + break; + } + return ret; +} + +/** + * @brief Write a line(byte) in a page.[set] + * + * @param ctx read / write interface definitions + * @param uint8_t address: page line address + * @param val value to write + * + */ +int32_t lsm6dsox_ln_pg_write_byte(lsm6dsox_ctx_t *ctx, uint16_t address, + uint8_t *val) +{ + lsm6dsox_page_rw_t page_rw; + lsm6dsox_page_sel_t page_sel; + lsm6dsox_page_address_t page_address; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); + + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1); + } + if (ret == 0) { + page_rw.page_rw = 0x02; /* page_write enable */ + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1); + } + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t*) &page_sel, 1); + } + + if (ret == 0) { + page_sel.page_sel = ((uint8_t)(address >> 8) & 0x0FU); + page_sel.not_used_01 = 1; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t*) &page_sel, 1); + } + if (ret == 0) { + page_address.page_addr = (uint8_t)address & 0xFFU; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_ADDRESS, + (uint8_t*)&page_address, 1); + } + if (ret == 0) { + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_VALUE, val, 1); + } + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1); + } + if (ret == 0) { + page_rw.page_rw = 0x00; /* page_write disable */ + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1); + } + if (ret == 0) { + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + return ret; +} + +/** + * @brief Write buffer in a page.[set] + * + * @param ctx read / write interface definitions + * @param uint8_t address: page line address + * @param uint8_t *buf: buffer to write + * @param uint8_t len: buffer len + * + */ +int32_t lsm6dsox_ln_pg_write(lsm6dsox_ctx_t *ctx, uint16_t address, + uint8_t *buf, uint8_t len) +{ + lsm6dsox_page_rw_t page_rw; + lsm6dsox_page_sel_t page_sel; + lsm6dsox_page_address_t page_address; + int32_t ret; + uint8_t msb, lsb; + uint8_t i ; + + msb = ((uint8_t)(address >> 8) & 0x0FU); + lsb = (uint8_t)address & 0xFFU; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); + if (ret == 0) { + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1); + } + if (ret == 0) { + page_rw.page_rw = 0x02; /* page_write enable*/ + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1); + } + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t*) &page_sel, 1); + } + if (ret == 0) { + page_sel.page_sel = msb; + page_sel.not_used_01 = 1; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t*) &page_sel, 1); + } + if (ret == 0) { + page_address.page_addr = lsb; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_ADDRESS, + (uint8_t*)&page_address, 1); + } + + if (ret == 0) { + + for (i = 0; ( (i < len) && (ret == 0) ); i++) + { + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_VALUE, &buf[i], 1); + + /* Check if page wrap */ + if ( (lsb == 0x00U) && (ret == 0) ) { + lsb++; + msb++; + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t*)&page_sel, 1); + if (ret == 0) { + page_sel.page_sel = msb; + page_sel.not_used_01 = 1; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_SEL, + (uint8_t*)&page_sel, 1); + } + } + } + page_sel.page_sel = 0; + page_sel.not_used_01 = 1; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t*) &page_sel, 1); + } + if (ret == 0) { + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1); + } + if (ret == 0) { + page_rw.page_rw = 0x00; /* page_write disable */ + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1); + } + + if (ret == 0) { + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + return ret; +} + +/** + * @brief Read a line(byte) in a page.[get] + * + * @param ctx read / write interface definitions + * @param uint8_t address: page line address + * @param val read value + * + */ +int32_t lsm6dsox_ln_pg_read_byte(lsm6dsox_ctx_t *ctx, uint16_t address, + uint8_t *val) +{ + lsm6dsox_page_rw_t page_rw; + lsm6dsox_page_sel_t page_sel; + lsm6dsox_page_address_t page_address; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); + if (ret == 0) { + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1); + } + if (ret == 0) { + page_rw.page_rw = 0x01; /* page_read enable*/ + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1); + } + if (ret == 0) { + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t*) &page_sel, 1); + } + if (ret == 0) { + page_sel.page_sel = ((uint8_t)(address >> 8) & 0x0FU); + page_sel.not_used_01 = 1; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t*) &page_sel, 1); + } + if (ret == 0) { + page_address.page_addr = (uint8_t)address & 0x00FFU; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_ADDRESS, + (uint8_t*)&page_address, 1); + } + if (ret == 0) { + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_VALUE, val, 2); + } + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1); + } + if (ret == 0) { + page_rw.page_rw = 0x00; /* page_read disable */ + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1); + } + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + + return ret; +} + +/** + * @brief Data-ready pulsed / letched mode.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of + * dataready_pulsed in + * reg COUNTER_BDR_REG1 + * + */ +int32_t lsm6dsox_data_ready_mode_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_dataready_pulsed_t val) +{ + lsm6dsox_counter_bdr_reg1_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, (uint8_t*)®, 1); + if (ret == 0) { + reg.dataready_pulsed = (uint8_t)val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Data-ready pulsed / letched mode.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of + * dataready_pulsed in + * reg COUNTER_BDR_REG1 + * + */ +int32_t lsm6dsox_data_ready_mode_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_dataready_pulsed_t *val) +{ + lsm6dsox_counter_bdr_reg1_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, (uint8_t*)®, 1); + switch (reg.dataready_pulsed) { + case LSM6DSOX_DRDY_LATCHED: + *val = LSM6DSOX_DRDY_LATCHED; + break; + case LSM6DSOX_DRDY_PULSED: + *val = LSM6DSOX_DRDY_PULSED; + break; + default: + *val = LSM6DSOX_DRDY_LATCHED; + break; + } + return ret; +} + +/** + * @brief Device "Who am I".[get] + * + * @param ctx read / write interface definitions + * @param buff buffer that stores data read + * + */ +int32_t lsm6dsox_device_id_get(lsm6dsox_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WHO_AM_I, buff, 1); + return ret; +} + +/** + * @brief Software reset. Restore the default values + * in user registers[set] + * + * @param ctx read / write interface definitions + * @param val change the values of sw_reset in reg CTRL3_C + * + */ +int32_t lsm6dsox_reset_set(lsm6dsox_ctx_t *ctx, uint8_t val) +{ + lsm6dsox_ctrl3_c_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1); + if (ret == 0) { + reg.sw_reset = val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1); + } + + return ret; +} + +/** + * @brief Software reset. Restore the default values in user registers.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of sw_reset in reg CTRL3_C + * + */ +int32_t lsm6dsox_reset_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_ctrl3_c_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1); + *val = reg.sw_reset; + + return ret; +} + +/** + * @brief Register address automatically incremented during a multiple byte + * access with a serial interface.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of if_inc in reg CTRL3_C + * + */ +int32_t lsm6dsox_auto_increment_set(lsm6dsox_ctx_t *ctx, uint8_t val) +{ + lsm6dsox_ctrl3_c_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1); + if (ret == 0) { + reg.if_inc = val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Register address automatically incremented during a multiple byte + * access with a serial interface.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of if_inc in reg CTRL3_C + * + */ +int32_t lsm6dsox_auto_increment_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_ctrl3_c_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1); + *val = reg.if_inc; + + return ret; +} + +/** + * @brief Reboot memory content. Reload the calibration parameters.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of boot in reg CTRL3_C + * + */ +int32_t lsm6dsox_boot_set(lsm6dsox_ctx_t *ctx, uint8_t val) +{ + lsm6dsox_ctrl3_c_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1); + if (ret == 0) { + reg.boot = val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Reboot memory content. Reload the calibration parameters.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of boot in reg CTRL3_C + * + */ +int32_t lsm6dsox_boot_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_ctrl3_c_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1); + *val = reg.boot; + + return ret; +} + +/** + * @brief Linear acceleration sensor self-test enable.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of st_xl in reg CTRL5_C + * + */ +int32_t lsm6dsox_xl_self_test_set(lsm6dsox_ctx_t *ctx, lsm6dsox_st_xl_t val) +{ + lsm6dsox_ctrl5_c_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)®, 1); + if (ret == 0) { + reg.st_xl = (uint8_t)val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Linear acceleration sensor self-test enable.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of st_xl in reg CTRL5_C + * + */ +int32_t lsm6dsox_xl_self_test_get(lsm6dsox_ctx_t *ctx, lsm6dsox_st_xl_t *val) +{ + lsm6dsox_ctrl5_c_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)®, 1); + switch (reg.st_xl) { + case LSM6DSOX_XL_ST_DISABLE: + *val = LSM6DSOX_XL_ST_DISABLE; + break; + case LSM6DSOX_XL_ST_POSITIVE: + *val = LSM6DSOX_XL_ST_POSITIVE; + break; + case LSM6DSOX_XL_ST_NEGATIVE: + *val = LSM6DSOX_XL_ST_NEGATIVE; + break; + default: + *val = LSM6DSOX_XL_ST_DISABLE; + break; + } + return ret; +} + +/** + * @brief Angular rate sensor self-test enable.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of st_g in reg CTRL5_C + * + */ +int32_t lsm6dsox_gy_self_test_set(lsm6dsox_ctx_t *ctx, lsm6dsox_st_g_t val) +{ + lsm6dsox_ctrl5_c_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)®, 1); + if (ret == 0) { + reg.st_g = (uint8_t)val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Angular rate sensor self-test enable.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of st_g in reg CTRL5_C + * + */ +int32_t lsm6dsox_gy_self_test_get(lsm6dsox_ctx_t *ctx, lsm6dsox_st_g_t *val) +{ + lsm6dsox_ctrl5_c_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t*)®, 1); + switch (reg.st_g) { + case LSM6DSOX_GY_ST_DISABLE: + *val = LSM6DSOX_GY_ST_DISABLE; + break; + case LSM6DSOX_GY_ST_POSITIVE: + *val = LSM6DSOX_GY_ST_POSITIVE; + break; + case LSM6DSOX_GY_ST_NEGATIVE: + *val = LSM6DSOX_GY_ST_NEGATIVE; + break; + default: + *val = LSM6DSOX_GY_ST_DISABLE; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DSOX_filters + * @brief This section group all the functions concerning the + * filters configuration + * @{ + * + */ + +/** + * @brief Accelerometer output from LPF2 filtering stage selection.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of lpf2_xl_en in reg CTRL1_XL + * + */ +int32_t lsm6dsox_xl_filter_lp2_set(lsm6dsox_ctx_t *ctx, uint8_t val) +{ + lsm6dsox_ctrl1_xl_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t*)®, 1); + if (ret == 0) { + reg.lpf2_xl_en = val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Accelerometer output from LPF2 filtering stage selection.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of lpf2_xl_en in reg CTRL1_XL + * + */ +int32_t lsm6dsox_xl_filter_lp2_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_ctrl1_xl_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t*)®, 1); + *val = reg.lpf2_xl_en; + + return ret; +} + +/** + * @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled; + * the bandwidth can be selected through FTYPE [2:0] + * in CTRL6_C (15h).[set] + * + * @param ctx read / write interface definitions + * @param val change the values of lpf1_sel_g in reg CTRL4_C + * + */ +int32_t lsm6dsox_gy_filter_lp1_set(lsm6dsox_ctx_t *ctx, uint8_t val) +{ + lsm6dsox_ctrl4_c_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)®, 1); + if (ret == 0) { + reg.lpf1_sel_g = val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled; + * the bandwidth can be selected through FTYPE [2:0] + * in CTRL6_C (15h).[get] + * + * @param ctx read / write interface definitions + * @param val change the values of lpf1_sel_g in reg CTRL4_C + * + */ +int32_t lsm6dsox_gy_filter_lp1_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_ctrl4_c_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)®, 1); + *val = reg.lpf1_sel_g; + + return ret; +} + +/** + * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends + * (XL and Gyro independently masked).[set] + * + * @param ctx read / write interface definitions + * @param val change the values of drdy_mask in reg CTRL4_C + * + */ +int32_t lsm6dsox_filter_settling_mask_set(lsm6dsox_ctx_t *ctx, uint8_t val) +{ + lsm6dsox_ctrl4_c_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)®, 1); + if (ret == 0) { + reg.drdy_mask = val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends + * (XL and Gyro independently masked).[get] + * + * @param ctx read / write interface definitions + * @param val change the values of drdy_mask in reg CTRL4_C + * + */ +int32_t lsm6dsox_filter_settling_mask_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_ctrl4_c_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)®, 1); + *val = reg.drdy_mask; + + return ret; +} + +/** + * @brief Gyroscope lp1 bandwidth.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of ftype in reg CTRL6_C + * + */ +int32_t lsm6dsox_gy_lp1_bandwidth_set(lsm6dsox_ctx_t *ctx, lsm6dsox_ftype_t val) +{ + lsm6dsox_ctrl6_c_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*)®, 1); + if (ret == 0) { + reg.ftype = (uint8_t)val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Gyroscope lp1 bandwidth.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of ftype in reg CTRL6_C + * + */ +int32_t lsm6dsox_gy_lp1_bandwidth_get(lsm6dsox_ctx_t *ctx, lsm6dsox_ftype_t *val) +{ + lsm6dsox_ctrl6_c_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*)®, 1); + switch (reg.ftype) { + case LSM6DSOX_ULTRA_LIGHT: + *val = LSM6DSOX_ULTRA_LIGHT; + break; + case LSM6DSOX_VERY_LIGHT: + *val = LSM6DSOX_VERY_LIGHT; + break; + case LSM6DSOX_LIGHT: + *val = LSM6DSOX_LIGHT; + break; + case LSM6DSOX_MEDIUM: + *val = LSM6DSOX_MEDIUM; + break; + case LSM6DSOX_STRONG: + *val = LSM6DSOX_STRONG; + break; + case LSM6DSOX_VERY_STRONG: + *val = LSM6DSOX_VERY_STRONG; + break; + case LSM6DSOX_AGGRESSIVE: + *val = LSM6DSOX_AGGRESSIVE; + break; + case LSM6DSOX_XTREME: + *val = LSM6DSOX_XTREME; + break; + default: + *val = LSM6DSOX_ULTRA_LIGHT; + break; + } + return ret; +} + +/** + * @brief Low pass filter 2 on 6D function selection.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of low_pass_on_6d in reg CTRL8_XL + * + */ +int32_t lsm6dsox_xl_lp2_on_6d_set(lsm6dsox_ctx_t *ctx, uint8_t val) +{ + lsm6dsox_ctrl8_xl_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)®, 1); + if (ret == 0) { + reg.low_pass_on_6d = val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Low pass filter 2 on 6D function selection.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of low_pass_on_6d in reg CTRL8_XL + * + */ +int32_t lsm6dsox_xl_lp2_on_6d_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_ctrl8_xl_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)®, 1); + *val = reg.low_pass_on_6d; + + return ret; +} + +/** + * @brief Accelerometer slope filter / high-pass filter selection + * on output.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of hp_slope_xl_en + * in reg CTRL8_XL + * + */ +int32_t lsm6dsox_xl_hp_path_on_out_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_hp_slope_xl_en_t val) +{ + lsm6dsox_ctrl8_xl_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)®, 1); + if (ret == 0) { + reg.hp_slope_xl_en = ((uint8_t)val & 0x10U) >> 4; + reg.hp_ref_mode_xl = ((uint8_t)val & 0x20U) >> 5; + reg.hpcf_xl = (uint8_t)val & 0x07U; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Accelerometer slope filter / high-pass filter selection + * on output.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of hp_slope_xl_en + * in reg CTRL8_XL + * + */ +int32_t lsm6dsox_xl_hp_path_on_out_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_hp_slope_xl_en_t *val) +{ + lsm6dsox_ctrl8_xl_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)®, 1); + switch ((reg.hp_ref_mode_xl << 5) | (reg.hp_slope_xl_en << 4) | + reg.hpcf_xl) { + case LSM6DSOX_HP_PATH_DISABLE_ON_OUT: + *val = LSM6DSOX_HP_PATH_DISABLE_ON_OUT; + break; + case LSM6DSOX_SLOPE_ODR_DIV_4: + *val = LSM6DSOX_SLOPE_ODR_DIV_4; + break; + case LSM6DSOX_HP_ODR_DIV_10: + *val = LSM6DSOX_HP_ODR_DIV_10; + break; + case LSM6DSOX_HP_ODR_DIV_20: + *val = LSM6DSOX_HP_ODR_DIV_20; + break; + case LSM6DSOX_HP_ODR_DIV_45: + *val = LSM6DSOX_HP_ODR_DIV_45; + break; + case LSM6DSOX_HP_ODR_DIV_100: + *val = LSM6DSOX_HP_ODR_DIV_100; + break; + case LSM6DSOX_HP_ODR_DIV_200: + *val = LSM6DSOX_HP_ODR_DIV_200; + break; + case LSM6DSOX_HP_ODR_DIV_400: + *val = LSM6DSOX_HP_ODR_DIV_400; + break; + case LSM6DSOX_HP_ODR_DIV_800: + *val = LSM6DSOX_HP_ODR_DIV_800; + break; + case LSM6DSOX_HP_REF_MD_ODR_DIV_10: + *val = LSM6DSOX_HP_REF_MD_ODR_DIV_10; + break; + case LSM6DSOX_HP_REF_MD_ODR_DIV_20: + *val = LSM6DSOX_HP_REF_MD_ODR_DIV_20; + break; + case LSM6DSOX_HP_REF_MD_ODR_DIV_45: + *val = LSM6DSOX_HP_REF_MD_ODR_DIV_45; + break; + case LSM6DSOX_HP_REF_MD_ODR_DIV_100: + *val = LSM6DSOX_HP_REF_MD_ODR_DIV_100; + break; + case LSM6DSOX_HP_REF_MD_ODR_DIV_200: + *val = LSM6DSOX_HP_REF_MD_ODR_DIV_200; + break; + case LSM6DSOX_HP_REF_MD_ODR_DIV_400: + *val = LSM6DSOX_HP_REF_MD_ODR_DIV_400; + break; + case LSM6DSOX_HP_REF_MD_ODR_DIV_800: + *val = LSM6DSOX_HP_REF_MD_ODR_DIV_800; + break; + case LSM6DSOX_LP_ODR_DIV_10: + *val = LSM6DSOX_LP_ODR_DIV_10; + break; + case LSM6DSOX_LP_ODR_DIV_20: + *val = LSM6DSOX_LP_ODR_DIV_20; + break; + case LSM6DSOX_LP_ODR_DIV_45: + *val = LSM6DSOX_LP_ODR_DIV_45; + break; + case LSM6DSOX_LP_ODR_DIV_100: + *val = LSM6DSOX_LP_ODR_DIV_100; + break; + case LSM6DSOX_LP_ODR_DIV_200: + *val = LSM6DSOX_LP_ODR_DIV_200; + break; + case LSM6DSOX_LP_ODR_DIV_400: + *val = LSM6DSOX_LP_ODR_DIV_400; + break; + case LSM6DSOX_LP_ODR_DIV_800: + *val = LSM6DSOX_LP_ODR_DIV_800; + break; + default: + *val = LSM6DSOX_HP_PATH_DISABLE_ON_OUT; + break; + } + + return ret; +} + +/** + * @brief Enables accelerometer LPF2 and HPF fast-settling mode. + * The filter sets the second samples after writing this bit. + * Active only during device exit from power-down mode.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of fastsettl_mode_xl in + * reg CTRL8_XL + * + */ +int32_t lsm6dsox_xl_fast_settling_set(lsm6dsox_ctx_t *ctx, uint8_t val) +{ + lsm6dsox_ctrl8_xl_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)®, 1); + if (ret == 0) { + reg.fastsettl_mode_xl = val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Enables accelerometer LPF2 and HPF fast-settling mode. + * The filter sets the second samples after writing this bit. + * Active only during device exit from power-down mode.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of fastsettl_mode_xl in reg CTRL8_XL + * + */ +int32_t lsm6dsox_xl_fast_settling_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_ctrl8_xl_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)®, 1); + *val = reg.fastsettl_mode_xl; + + return ret; +} + +/** + * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity + * functions.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of slope_fds in reg TAP_CFG0 + * + */ +int32_t lsm6dsox_xl_hp_path_internal_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_slope_fds_t val) +{ + lsm6dsox_tap_cfg0_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)®, 1); + if (ret == 0) { + reg.slope_fds = (uint8_t)val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity + * functions.[get] + * + * @param ctx read / write interface definitions + * @param val Change the values of slope_fds in reg TAP_CFG0 + * + */ +int32_t lsm6dsox_xl_hp_path_internal_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_slope_fds_t *val) +{ + lsm6dsox_tap_cfg0_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)®, 1); + switch (reg.slope_fds) { + case LSM6DSOX_USE_SLOPE: + *val = LSM6DSOX_USE_SLOPE; + break; + case LSM6DSOX_USE_HPF: + *val = LSM6DSOX_USE_HPF; + break; + default: + *val = LSM6DSOX_USE_SLOPE; + break; + } + return ret; +} + +/** + * @brief Enables gyroscope digital high-pass filter. The filter is + * enabled only if the gyro is in HP mode.[set] + * + * @param ctx read / write interface definitions + * @param val Get the values of hp_en_g and hp_en_g + * in reg CTRL7_G + * + */ +int32_t lsm6dsox_gy_hp_path_internal_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_hpm_g_t val) +{ + lsm6dsox_ctrl7_g_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)®, 1); + if (ret == 0) { + reg.hp_en_g = ((uint8_t)val & 0x80U) >> 7; + reg.hpm_g = (uint8_t)val & 0x03U; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Enables gyroscope digital high-pass filter. The filter is + * enabled only if the gyro is in HP mode.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of hp_en_g and hp_en_g + * in reg CTRL7_G + * + */ +int32_t lsm6dsox_gy_hp_path_internal_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_hpm_g_t *val) +{ + lsm6dsox_ctrl7_g_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)®, 1); + switch ((reg.hp_en_g << 7) + reg.hpm_g) { + case LSM6DSOX_HP_FILTER_NONE: + *val = LSM6DSOX_HP_FILTER_NONE; + break; + case LSM6DSOX_HP_FILTER_16mHz: + *val = LSM6DSOX_HP_FILTER_16mHz; + break; + case LSM6DSOX_HP_FILTER_65mHz: + *val = LSM6DSOX_HP_FILTER_65mHz; + break; + case LSM6DSOX_HP_FILTER_260mHz: + *val = LSM6DSOX_HP_FILTER_260mHz; + break; + case LSM6DSOX_HP_FILTER_1Hz04: + *val = LSM6DSOX_HP_FILTER_1Hz04; + break; + default: + *val = LSM6DSOX_HP_FILTER_NONE; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DSOX_ Auxiliary_interface + * @brief This section groups all the functions concerning + * auxiliary interface. + * @{ + * + */ + +/** + * @brief OIS data reading from Auxiliary / Main SPI.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of spi2_read_en in reg UI_INT_OIS + * + */ +int32_t lsm6dsox_ois_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_spi2_read_en_t val) +{ + lsm6dsox_func_cfg_access_t func_cfg_access; + lsm6dsox_ui_int_ois_t ui_int_ois; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*)&ui_int_ois, 1); + if (ret == 0) { + ui_int_ois.spi2_read_en = ((uint8_t)val & 0x01U); + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_INT_OIS, + (uint8_t*)&ui_int_ois, 1); + } + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS, + (uint8_t*)&func_cfg_access, 1); + } + if (ret == 0) { + func_cfg_access.ois_ctrl_from_ui = ( ((uint8_t)val & 0x02U) >> 1 ); + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS, + (uint8_t*)&func_cfg_access, 1); + } + return ret; +} + +/** + * @brief aux_ois_data: [get] OIS data reading from Auxiliary / Main SPI + * + * @param ctx read / write interface definitions + * @param val Get the values of spi2_read_en + * in reg UI_INT_OIS + * + */ +int32_t lsm6dsox_ois_mode_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_spi2_read_en_t *val) +{ + lsm6dsox_func_cfg_access_t func_cfg_access; + lsm6dsox_ui_int_ois_t ui_int_ois; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*)&ui_int_ois, 1); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS, + (uint8_t*)&func_cfg_access, 1); + } + switch ((func_cfg_access.ois_ctrl_from_ui << 1) + ui_int_ois.spi2_read_en) { + case LSM6DSOX_OIS_CTRL_AUX_DATA_UI: + *val = LSM6DSOX_OIS_CTRL_AUX_DATA_UI; + break; + case LSM6DSOX_OIS_CTRL_AUX_DATA_UI_AUX: + *val = LSM6DSOX_OIS_CTRL_AUX_DATA_UI_AUX; + break; + case LSM6DSOX_OIS_CTRL_UI_AUX_DATA_UI: + *val = LSM6DSOX_OIS_CTRL_UI_AUX_DATA_UI; + break; + case LSM6DSOX_OIS_CTRL_UI_AUX_DATA_UI_AUX: + *val = LSM6DSOX_OIS_CTRL_UI_AUX_DATA_UI_AUX; + break; + default: + *val = LSM6DSOX_OIS_CTRL_AUX_DATA_UI; + break; + } + return ret; +} + +/** + * @brief aOn auxiliary interface connect/disconnect SDO and OCS + * internal pull-up.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of ois_pu_dis in + * reg PIN_CTRL + * + */ +int32_t lsm6dsox_aux_sdo_ocs_mode_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_ois_pu_dis_t val) +{ + lsm6dsox_pin_ctrl_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t*)®, 1); + if (ret == 0) { + reg.ois_pu_dis = (uint8_t)val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief On auxiliary interface connect/disconnect SDO and OCS + * internal pull-up.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of ois_pu_dis in reg PIN_CTRL + * + */ +int32_t lsm6dsox_aux_sdo_ocs_mode_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_ois_pu_dis_t *val) +{ + lsm6dsox_pin_ctrl_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t*)®, 1); + switch (reg.ois_pu_dis) { + case LSM6DSOX_AUX_PULL_UP_DISC: + *val = LSM6DSOX_AUX_PULL_UP_DISC; + break; + case LSM6DSOX_AUX_PULL_UP_CONNECT: + *val = LSM6DSOX_AUX_PULL_UP_CONNECT; + break; + default: + *val = LSM6DSOX_AUX_PULL_UP_DISC; + break; + } + return ret; +} + +/** + * @brief OIS chain on aux interface power on mode.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of ois_on in reg CTRL7_G + * + */ +int32_t lsm6dsox_aux_pw_on_ctrl_set(lsm6dsox_ctx_t *ctx, lsm6dsox_ois_on_t val) +{ + lsm6dsox_ctrl7_g_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)®, 1); + if (ret == 0) { + reg.ois_on_en = (uint8_t)val & 0x01U; + reg.ois_on = (uint8_t)val & 0x01U; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief aux_pw_on_ctrl: [get] OIS chain on aux interface power on mode + * + * @param ctx read / write interface definitions + * @param val Get the values of ois_on in reg CTRL7_G + * + */ +int32_t lsm6dsox_aux_pw_on_ctrl_get(lsm6dsox_ctx_t *ctx, lsm6dsox_ois_on_t *val) +{ + lsm6dsox_ctrl7_g_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t*)®, 1); + switch (reg.ois_on) { + case LSM6DSOX_AUX_ON: + *val = LSM6DSOX_AUX_ON; + break; + case LSM6DSOX_AUX_ON_BY_AUX_INTERFACE: + *val = LSM6DSOX_AUX_ON_BY_AUX_INTERFACE; + break; + default: + *val = LSM6DSOX_AUX_ON; + break; + } + + return ret; +} + +/** + * @brief Accelerometer full-scale management between UI chain and + * OIS chain. When XL UI is on, the full scale is the same + * between UI/OIS and is chosen by the UI CTRL registers; + * when XL UI is in PD, the OIS can choose the FS. + * Full scales are independent between the UI/OIS chain + * but both bound to 8 g.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of xl_fs_mode in + * reg CTRL8_XL + * + */ +int32_t lsm6dsox_aux_xl_fs_mode_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_xl_fs_mode_t val) +{ + lsm6dsox_ctrl8_xl_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)®, 1); + if (ret == 0) { + reg.xl_fs_mode = (uint8_t)val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Accelerometer full-scale management between UI chain and + * OIS chain. When XL UI is on, the full scale is the same + * between UI/OIS and is chosen by the UI CTRL registers; + * when XL UI is in PD, the OIS can choose the FS. + * Full scales are independent between the UI/OIS chain + * but both bound to 8 g.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of xl_fs_mode in reg CTRL8_XL + * + */ +int32_t lsm6dsox_aux_xl_fs_mode_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_xl_fs_mode_t *val) +{ + lsm6dsox_ctrl8_xl_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t*)®, 1); + switch (reg.xl_fs_mode) { + case LSM6DSOX_USE_SAME_XL_FS: + *val = LSM6DSOX_USE_SAME_XL_FS; + break; + case LSM6DSOX_USE_DIFFERENT_XL_FS: + *val = LSM6DSOX_USE_DIFFERENT_XL_FS; + break; + default: + *val = LSM6DSOX_USE_SAME_XL_FS; + break; + } + + return ret; +} + +/** + * @brief The STATUS_SPIAux register is read by the auxiliary SPI.[get] + * + * @param ctx read / write interface definitions + * @param val Get registers STATUS_SPIAUX + * + */ +int32_t lsm6dsox_aux_status_reg_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_spi2_status_reg_ois_t *val) +{ + int32_t ret; + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_STATUS_REG_OIS, (uint8_t*) val, 1); + return ret; +} + +/** + * @brief aux_xl_flag_data_ready: [get] AUX accelerometer data available + * + * @param ctx read / write interface definitions + * @param val change the values of xlda in reg STATUS_SPIAUX + * + */ +int32_t lsm6dsox_aux_xl_flag_data_ready_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_spi2_status_reg_ois_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_STATUS_REG_OIS, (uint8_t*)®, 1); + *val = reg.xlda; + + return ret; +} + +/** + * @brief aux_gy_flag_data_ready: [get] AUX gyroscope data available. + * + * @param ctx read / write interface definitions + * @param val change the values of gda in reg STATUS_SPIAUX + * + */ +int32_t lsm6dsox_aux_gy_flag_data_ready_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_spi2_status_reg_ois_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_STATUS_REG_OIS, (uint8_t*)®, 1); + *val = reg.gda; + + return ret; +} + +/** + * @brief High when the gyroscope output is in the settling phase.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of gyro_settling in reg STATUS_SPIAUX + * + */ +int32_t lsm6dsox_aux_gy_flag_settling_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_spi2_status_reg_ois_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_STATUS_REG_OIS, (uint8_t*)®, 1); + *val = reg.gyro_settling; + + return ret; +} + +/** + * @brief Indicates polarity of DEN signal on OIS chain.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of den_lh_ois in + * reg INT_OIS + * + */ +int32_t lsm6dsox_aux_den_polarity_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_den_lh_ois_t val) +{ + lsm6dsox_ui_int_ois_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*)®, 1); + if (ret == 0) { + reg.den_lh_ois = (uint8_t)val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Indicates polarity of DEN signal on OIS chain.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of den_lh_ois in reg INT_OIS + * + */ +int32_t lsm6dsox_aux_den_polarity_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_den_lh_ois_t *val) +{ + lsm6dsox_ui_int_ois_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*)®, 1); + switch (reg.den_lh_ois) { + case LSM6DSOX_AUX_DEN_ACTIVE_LOW: + *val = LSM6DSOX_AUX_DEN_ACTIVE_LOW; + break; + case LSM6DSOX_AUX_DEN_ACTIVE_HIGH: + *val = LSM6DSOX_AUX_DEN_ACTIVE_HIGH; + break; + default: + *val = LSM6DSOX_AUX_DEN_ACTIVE_LOW; + break; + } + return ret; +} + +/** + * @brief Configure DEN mode on the OIS chain.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of lvl2_ois in reg INT_OIS + * + */ +int32_t lsm6dsox_aux_den_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_lvl2_ois_t val) +{ + lsm6dsox_ui_ctrl1_ois_t ctrl1_ois; + lsm6dsox_ui_int_ois_t int_ois; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*) &int_ois, 1); + if (ret == 0) { + int_ois.lvl2_ois = (uint8_t)val & 0x01U; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*) &int_ois, 1); + } + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*) &ctrl1_ois, 1); + } + if (ret == 0) { + ctrl1_ois.lvl1_ois = ((uint8_t)val & 0x02U) >> 1; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*) &ctrl1_ois, 1); + } + return ret; +} + +/** + * @brief Configure DEN mode on the OIS chain.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of lvl2_ois in reg INT_OIS + * + */ +int32_t lsm6dsox_aux_den_mode_get(lsm6dsox_ctx_t *ctx, lsm6dsox_lvl2_ois_t *val) +{ + lsm6dsox_ui_ctrl1_ois_t ctrl1_ois; + lsm6dsox_ui_int_ois_t int_ois; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*) &int_ois, 1); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*) &ctrl1_ois, 1); + switch ((ctrl1_ois.lvl1_ois << 1) + int_ois.lvl2_ois) { + case LSM6DSOX_AUX_DEN_DISABLE: + *val = LSM6DSOX_AUX_DEN_DISABLE; + break; + case LSM6DSOX_AUX_DEN_LEVEL_LATCH: + *val = LSM6DSOX_AUX_DEN_LEVEL_LATCH; + break; + case LSM6DSOX_AUX_DEN_LEVEL_TRIG: + *val = LSM6DSOX_AUX_DEN_LEVEL_TRIG; + break; + default: + *val = LSM6DSOX_AUX_DEN_DISABLE; + break; + } + } + return ret; +} + +/** + * @brief Enables/Disable OIS chain DRDY on INT2 pin. + * This setting has priority over all other INT2 settings.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of int2_drdy_ois in reg INT_OIS + * + */ +int32_t lsm6dsox_aux_drdy_on_int2_set(lsm6dsox_ctx_t *ctx, uint8_t val) +{ + lsm6dsox_ui_int_ois_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*)®, 1); + if (ret == 0) { + reg.int2_drdy_ois = val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Enables/Disable OIS chain DRDY on INT2 pin. + * This setting has priority over all other INT2 settings.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of int2_drdy_ois in reg INT_OIS + * + */ +int32_t lsm6dsox_aux_drdy_on_int2_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_ui_int_ois_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t*)®, 1); + *val = reg.int2_drdy_ois; + + return ret; +} + +/** + * @brief Enables OIS chain data processing for gyro in Mode 3 and Mode 4 + * (mode4_en = 1) and accelerometer data in and Mode 4 (mode4_en = 1). + * When the OIS chain is enabled, the OIS outputs are available + * through the SPI2 in registers OUTX_L_G (22h) through + * OUTZ_H_G (27h) and STATUS_REG (1Eh) / STATUS_SPIAux, and + * LPF1 is dedicated to this chain.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of ois_en_spi2 in + * reg CTRL1_OIS + * + */ +int32_t lsm6dsox_aux_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_ois_en_spi2_t val) +{ + lsm6dsox_ui_ctrl1_ois_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*)®, 1); + if (ret == 0) { + reg.ois_en_spi2 = (uint8_t)val & 0x01U; + reg.mode4_en = ((uint8_t)val & 0x02U) >> 1; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Enables OIS chain data processing for gyro in Mode 3 and Mode 4 + * (mode4_en = 1) and accelerometer data in and Mode 4 (mode4_en = 1). + * When the OIS chain is enabled, the OIS outputs are available + * through the SPI2 in registers OUTX_L_G (22h) through + * OUTZ_H_G (27h) and STATUS_REG (1Eh) / STATUS_SPIAux, and + * LPF1 is dedicated to this chain.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of ois_en_spi2 in + * reg CTRL1_OIS + * + */ +int32_t lsm6dsox_aux_mode_get(lsm6dsox_ctx_t *ctx, lsm6dsox_ois_en_spi2_t *val) +{ + lsm6dsox_ui_ctrl1_ois_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*)®, 1); + switch ((reg.mode4_en << 1) | reg.ois_en_spi2) { + case LSM6DSOX_AUX_DISABLE: + *val = LSM6DSOX_AUX_DISABLE; + break; + case LSM6DSOX_MODE_3_GY: + *val = LSM6DSOX_MODE_3_GY; + break; + case LSM6DSOX_MODE_4_GY_XL: + *val = LSM6DSOX_MODE_4_GY_XL; + break; + default: + *val = LSM6DSOX_AUX_DISABLE; + break; + } + return ret; +} + +/** + * @brief Selects gyroscope OIS chain full-scale.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of fs_g_ois in reg CTRL1_OIS + * + */ +int32_t lsm6dsox_aux_gy_full_scale_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_fs_g_ois_t val) +{ + lsm6dsox_ui_ctrl1_ois_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*)®, 1); + if (ret == 0) { + reg.fs_g_ois = (uint8_t)val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Selects gyroscope OIS chain full-scale.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of fs_g_ois in reg CTRL1_OIS + * + */ +int32_t lsm6dsox_aux_gy_full_scale_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_fs_g_ois_t *val) +{ + lsm6dsox_ui_ctrl1_ois_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*)®, 1); + switch (reg.fs_g_ois) { + case LSM6DSOX_250dps_AUX: + *val = LSM6DSOX_250dps_AUX; + break; + case LSM6DSOX_125dps_AUX: + *val = LSM6DSOX_125dps_AUX; + break; + case LSM6DSOX_500dps_AUX: + *val = LSM6DSOX_500dps_AUX; + break; + case LSM6DSOX_1000dps_AUX: + *val = LSM6DSOX_1000dps_AUX; + break; + case LSM6DSOX_2000dps_AUX: + *val = LSM6DSOX_2000dps_AUX; + break; + default: + *val = LSM6DSOX_250dps_AUX; + break; + } + return ret; +} + +/** + * @brief SPI2 3- or 4-wire interface.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of sim_ois in reg CTRL1_OIS + * + */ +int32_t lsm6dsox_aux_spi_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_sim_ois_t val) +{ + lsm6dsox_ui_ctrl1_ois_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*)®, 1); + if (ret == 0) { + reg.sim_ois = (uint8_t)val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief SPI2 3- or 4-wire interface.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of sim_ois in reg CTRL1_OIS + * + */ +int32_t lsm6dsox_aux_spi_mode_get(lsm6dsox_ctx_t *ctx, lsm6dsox_sim_ois_t *val) +{ + lsm6dsox_ui_ctrl1_ois_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t*)®, 1); + switch (reg.sim_ois) { + case LSM6DSOX_AUX_SPI_4_WIRE: + *val = LSM6DSOX_AUX_SPI_4_WIRE; + break; + case LSM6DSOX_AUX_SPI_3_WIRE: + *val = LSM6DSOX_AUX_SPI_3_WIRE; + break; + default: + *val = LSM6DSOX_AUX_SPI_4_WIRE; + break; + } + return ret; +} + +/** + * @brief Selects gyroscope digital LPF1 filter bandwidth.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of ftype_ois in + * reg CTRL2_OIS + * + */ +int32_t lsm6dsox_aux_gy_lp1_bandwidth_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_ftype_ois_t val) +{ + lsm6dsox_ui_ctrl2_ois_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL2_OIS, (uint8_t*)®, 1); + if (ret == 0) { + reg.ftype_ois = (uint8_t)val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL2_OIS, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Selects gyroscope digital LPF1 filter bandwidth.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of ftype_ois in reg CTRL2_OIS + * + */ +int32_t lsm6dsox_aux_gy_lp1_bandwidth_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_ftype_ois_t *val) +{ + lsm6dsox_ui_ctrl2_ois_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL2_OIS, (uint8_t*)®, 1); + switch (reg.ftype_ois) { + case LSM6DSOX_351Hz39: + *val = LSM6DSOX_351Hz39; + break; + case LSM6DSOX_236Hz63: + *val = LSM6DSOX_236Hz63; + break; + case LSM6DSOX_172Hz70: + *val = LSM6DSOX_172Hz70; + break; + case LSM6DSOX_937Hz91: + *val = LSM6DSOX_937Hz91; + break; + default: + *val = LSM6DSOX_351Hz39; + break; + } + return ret; +} + +/** + * @brief Selects gyroscope OIS chain digital high-pass filter cutoff.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of hpm_ois in reg CTRL2_OIS + * + */ +int32_t lsm6dsox_aux_gy_hp_bandwidth_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_hpm_ois_t val) +{ + lsm6dsox_ui_ctrl2_ois_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL2_OIS, (uint8_t*)®, 1); + if (ret == 0) { + reg.hpm_ois = (uint8_t)val & 0x03U; + reg.hp_en_ois = ((uint8_t)val & 0x10U) >> 4; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL2_OIS, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Selects gyroscope OIS chain digital high-pass filter cutoff.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of hpm_ois in reg CTRL2_OIS + * + */ +int32_t lsm6dsox_aux_gy_hp_bandwidth_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_hpm_ois_t *val) +{ + lsm6dsox_ui_ctrl2_ois_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL2_OIS, (uint8_t*)®, 1); + switch ((reg.hp_en_ois << 4) | reg.hpm_ois) { + case LSM6DSOX_AUX_HP_DISABLE: + *val = LSM6DSOX_AUX_HP_DISABLE; + break; + case LSM6DSOX_AUX_HP_Hz016: + *val = LSM6DSOX_AUX_HP_Hz016; + break; + case LSM6DSOX_AUX_HP_Hz065: + *val = LSM6DSOX_AUX_HP_Hz065; + break; + case LSM6DSOX_AUX_HP_Hz260: + *val = LSM6DSOX_AUX_HP_Hz260; + break; + case LSM6DSOX_AUX_HP_1Hz040: + *val = LSM6DSOX_AUX_HP_1Hz040; + break; + default: + *val = LSM6DSOX_AUX_HP_DISABLE; + break; + } + return ret; +} + +/** + * @brief Enable / Disables OIS chain clamp. + * Enable: All OIS chain outputs = 8000h + * during self-test; Disable: OIS chain self-test + * outputs dependent from the aux gyro full + * scale selected.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of st_ois_clampdis in + * reg CTRL3_OIS + * + */ +int32_t lsm6dsox_aux_gy_clamp_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_st_ois_clampdis_t val) +{ + lsm6dsox_ui_ctrl3_ois_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t*)®, 1); + if (ret == 0) { + reg.st_ois_clampdis = (uint8_t)val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Enable / Disables OIS chain clamp. + * Enable: All OIS chain outputs = 8000h + * during self-test; Disable: OIS chain self-test + * outputs dependent from the aux gyro full + * scale selected.[set] + * + * @param ctx read / write interface definitions + * @param val Get the values of st_ois_clampdis in + * reg CTRL3_OIS + * + */ +int32_t lsm6dsox_aux_gy_clamp_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_st_ois_clampdis_t *val) +{ + lsm6dsox_ui_ctrl3_ois_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t*)®, 1); + switch (reg.st_ois_clampdis) { + case LSM6DSOX_ENABLE_CLAMP: + *val = LSM6DSOX_ENABLE_CLAMP; + break; + case LSM6DSOX_DISABLE_CLAMP: + *val = LSM6DSOX_DISABLE_CLAMP; + break; + default: + *val = LSM6DSOX_ENABLE_CLAMP; + break; + } + return ret; +} + +/** + * @brief Selects accelerometer OIS channel bandwidth.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of + * filter_xl_conf_ois in reg CTRL3_OIS + * + */ +int32_t lsm6dsox_aux_xl_bandwidth_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_filter_xl_conf_ois_t val) +{ + lsm6dsox_ui_ctrl3_ois_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t*)®, 1); + if (ret == 0) { + reg.filter_xl_conf_ois = (uint8_t)val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Selects accelerometer OIS channel bandwidth.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of + * filter_xl_conf_ois in reg CTRL3_OIS + * + */ +int32_t lsm6dsox_aux_xl_bandwidth_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_filter_xl_conf_ois_t *val) +{ + lsm6dsox_ui_ctrl3_ois_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t*)®, 1); + + switch (reg.filter_xl_conf_ois) { + case LSM6DSOX_289Hz: + *val = LSM6DSOX_289Hz; + break; + case LSM6DSOX_258Hz: + *val = LSM6DSOX_258Hz; + break; + case LSM6DSOX_120Hz: + *val = LSM6DSOX_120Hz; + break; + case LSM6DSOX_65Hz2: + *val = LSM6DSOX_65Hz2; + break; + case LSM6DSOX_33Hz2: + *val = LSM6DSOX_33Hz2; + break; + case LSM6DSOX_16Hz6: + *val = LSM6DSOX_16Hz6; + break; + case LSM6DSOX_8Hz30: + *val = LSM6DSOX_8Hz30; + break; + case LSM6DSOX_4Hz15: + *val = LSM6DSOX_4Hz15; + break; + default: + *val = LSM6DSOX_289Hz; + break; + } + return ret; +} + +/** + * @brief Selects accelerometer OIS channel full-scale.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of fs_xl_ois in + * reg CTRL3_OIS + * + */ +int32_t lsm6dsox_aux_xl_full_scale_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_fs_xl_ois_t val) +{ + lsm6dsox_ui_ctrl3_ois_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t*)®, 1); + if (ret == 0) { + reg.fs_xl_ois = (uint8_t)val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Selects accelerometer OIS channel full-scale.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of fs_xl_ois in reg CTRL3_OIS + * + */ +int32_t lsm6dsox_aux_xl_full_scale_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_fs_xl_ois_t *val) +{ + lsm6dsox_ui_ctrl3_ois_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t*)®, 1); + switch (reg.fs_xl_ois) { + case LSM6DSOX_AUX_2g: + *val = LSM6DSOX_AUX_2g; + break; + case LSM6DSOX_AUX_16g: + *val = LSM6DSOX_AUX_16g; + break; + case LSM6DSOX_AUX_4g: + *val = LSM6DSOX_AUX_4g; + break; + case LSM6DSOX_AUX_8g: + *val = LSM6DSOX_AUX_8g; + break; + default: + *val = LSM6DSOX_AUX_2g; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DSOX_ main_serial_interface + * @brief This section groups all the functions concerning main + * serial interface management (not auxiliary) + * @{ + * + */ + +/** + * @brief Connect/Disconnect SDO/SA0 internal pull-up.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of sdo_pu_en in + * reg PIN_CTRL + * + */ +int32_t lsm6dsox_sdo_sa0_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_sdo_pu_en_t val) +{ + lsm6dsox_pin_ctrl_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t*)®, 1); + if (ret == 0) { + reg.sdo_pu_en = (uint8_t)val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Connect/Disconnect SDO/SA0 internal pull-up.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of sdo_pu_en in reg PIN_CTRL + * + */ +int32_t lsm6dsox_sdo_sa0_mode_get(lsm6dsox_ctx_t *ctx, lsm6dsox_sdo_pu_en_t *val) +{ + lsm6dsox_pin_ctrl_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t*)®, 1); + switch (reg.sdo_pu_en) { + case LSM6DSOX_PULL_UP_DISC: + *val = LSM6DSOX_PULL_UP_DISC; + break; + case LSM6DSOX_PULL_UP_CONNECT: + *val = LSM6DSOX_PULL_UP_CONNECT; + break; + default: + *val = LSM6DSOX_PULL_UP_DISC; + break; + } + return ret; +} + +/** + * @brief SPI Serial Interface Mode selection.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of sim in reg CTRL3_C + * + */ +int32_t lsm6dsox_spi_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_sim_t val) +{ + lsm6dsox_ctrl3_c_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1); + if (ret == 0) { + reg.sim = (uint8_t)val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief SPI Serial Interface Mode selection.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of sim in reg CTRL3_C + * + */ +int32_t lsm6dsox_spi_mode_get(lsm6dsox_ctx_t *ctx, lsm6dsox_sim_t *val) +{ + lsm6dsox_ctrl3_c_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1); + switch (reg.sim) { + case LSM6DSOX_SPI_4_WIRE: + *val = LSM6DSOX_SPI_4_WIRE; + break; + case LSM6DSOX_SPI_3_WIRE: + *val = LSM6DSOX_SPI_3_WIRE; + break; + default: + *val = LSM6DSOX_SPI_4_WIRE; + break; + } + return ret; +} + +/** + * @brief Disable / Enable I2C interface.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of i2c_disable in + * reg CTRL4_C + * + */ +int32_t lsm6dsox_i2c_interface_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_i2c_disable_t val) +{ + lsm6dsox_ctrl4_c_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)®, 1); + if (ret == 0) { + reg.i2c_disable = (uint8_t)val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Disable / Enable I2C interface.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of i2c_disable in + * reg CTRL4_C + * + */ +int32_t lsm6dsox_i2c_interface_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_i2c_disable_t *val) +{ + lsm6dsox_ctrl4_c_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)®, 1); + switch (reg.i2c_disable) { + case LSM6DSOX_I2C_ENABLE: + *val = LSM6DSOX_I2C_ENABLE; + break; + case LSM6DSOX_I2C_DISABLE: + *val = LSM6DSOX_I2C_DISABLE; + break; + default: + *val = LSM6DSOX_I2C_ENABLE; + break; + } + return ret; +} + +/** + * @brief I3C Enable/Disable communication protocol[.set] + * + * @param ctx read / write interface definitions + * @param val change the values of i3c_disable + * in reg CTRL9_XL + * + */ +int32_t lsm6dsox_i3c_disable_set(lsm6dsox_ctx_t *ctx, lsm6dsox_i3c_disable_t val) +{ + lsm6dsox_i3c_bus_avb_t i3c_bus_avb; + lsm6dsox_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1); + if (ret == 0) { + ctrl9_xl.i3c_disable = ((uint8_t)val & 0x80U) >> 7; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1); + } + if (ret == 0) { + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_I3C_BUS_AVB, + (uint8_t*)&i3c_bus_avb, 1); + } + if (ret == 0) { + i3c_bus_avb.i3c_bus_avb_sel = (uint8_t)val & 0x03U; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_I3C_BUS_AVB, + (uint8_t*)&i3c_bus_avb, 1); + } + + return ret; +} + +/** + * @brief I3C Enable/Disable communication protocol.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of i3c_disable in + * reg CTRL9_XL + * + */ +int32_t lsm6dsox_i3c_disable_get(lsm6dsox_ctx_t *ctx, lsm6dsox_i3c_disable_t *val) +{ + lsm6dsox_ctrl9_xl_t ctrl9_xl; + lsm6dsox_i3c_bus_avb_t i3c_bus_avb; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_I3C_BUS_AVB, + (uint8_t*)&i3c_bus_avb, 1); + + switch ((ctrl9_xl.i3c_disable << 7) | i3c_bus_avb.i3c_bus_avb_sel) { + case LSM6DSOX_I3C_DISABLE: + *val = LSM6DSOX_I3C_DISABLE; + break; + case LSM6DSOX_I3C_ENABLE_T_50us: + *val = LSM6DSOX_I3C_ENABLE_T_50us; + break; + case LSM6DSOX_I3C_ENABLE_T_2us: + *val = LSM6DSOX_I3C_ENABLE_T_2us; + break; + case LSM6DSOX_I3C_ENABLE_T_1ms: + *val = LSM6DSOX_I3C_ENABLE_T_1ms; + break; + case LSM6DSOX_I3C_ENABLE_T_25ms: + *val = LSM6DSOX_I3C_ENABLE_T_25ms; + break; + default: + *val = LSM6DSOX_I3C_DISABLE; + break; + } + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DSOX_interrupt_pins + * @brief This section groups all the functions that manage interrup pins + * @{ + * + */ + +/** + * @brief Select the signal that need to route on int1 pad.[set] + * + * @param ctx read / write interface definitions + * @param val struct of registers: INT1_CTRL, + * MD1_CFG, EMB_FUNC_INT1, FSM_INT1_A, + * FSM_INT1_B + * + */ +int32_t lsm6dsox_pin_int1_route_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_pin_int1_route_t *val) +{ + lsm6dsox_pin_int2_route_t pin_int2_route; + lsm6dsox_tap_cfg2_t tap_cfg2; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); + if (ret == 0) { + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MLC_INT1, + (uint8_t*)&val->mlc_int1, 1); + } + if (ret == 0) { + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_INT1, + (uint8_t*)&val->emb_func_int1, 1); + } + if (ret == 0) { + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_INT1_A, + (uint8_t*)&val->fsm_int1_a, 1); + } + if (ret == 0) { + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_INT1_B, + (uint8_t*)&val->fsm_int1_b, 1); + } + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + + if (ret == 0) { + if ( ( val->emb_func_int1.int1_fsm_lc + | val->emb_func_int1.int1_sig_mot + | val->emb_func_int1.int1_step_detector + | val->emb_func_int1.int1_tilt + | val->fsm_int1_a.int1_fsm1 + | val->fsm_int1_a.int1_fsm2 + | val->fsm_int1_a.int1_fsm3 + | val->fsm_int1_a.int1_fsm4 + | val->fsm_int1_a.int1_fsm5 + | val->fsm_int1_a.int1_fsm6 + | val->fsm_int1_a.int1_fsm7 + | val->fsm_int1_a.int1_fsm8 + | val->fsm_int1_b.int1_fsm9 + | val->fsm_int1_b.int1_fsm10 + | val->fsm_int1_b.int1_fsm11 + | val->fsm_int1_b.int1_fsm12 + | val->fsm_int1_b.int1_fsm13 + | val->fsm_int1_b.int1_fsm14 + | val->fsm_int1_b.int1_fsm15 + | val->fsm_int1_b.int1_fsm16 + | val->mlc_int1.int1_mlc1 + | val->mlc_int1.int1_mlc2 + | val->mlc_int1.int1_mlc3 + | val->mlc_int1.int1_mlc4 + | val->mlc_int1.int1_mlc5 + | val->mlc_int1.int1_mlc6 + | val->mlc_int1.int1_mlc7 + | val->mlc_int1.int1_mlc8) != PROPERTY_DISABLE){ + val->md1_cfg.int1_emb_func = PROPERTY_ENABLE; + } + else{ + val->md1_cfg.int1_emb_func = PROPERTY_DISABLE; + } + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_INT1_CTRL, + (uint8_t*)&val->int1_ctrl, 1); + } + if (ret == 0) { + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MD1_CFG, (uint8_t*)&val->md1_cfg, 1); + } + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t*) &tap_cfg2, 1); + } + + if (ret == 0) { + ret = lsm6dsox_pin_int2_route_get(ctx, &pin_int2_route); + } + if (ret == 0) { + if ( ( pin_int2_route.int2_ctrl.int2_cnt_bdr + | pin_int2_route.int2_ctrl.int2_drdy_g + | pin_int2_route.int2_ctrl.int2_drdy_temp + | pin_int2_route.int2_ctrl.int2_drdy_xl + | pin_int2_route.int2_ctrl.int2_fifo_full + | pin_int2_route.int2_ctrl.int2_fifo_ovr + | pin_int2_route.int2_ctrl.int2_fifo_th + | pin_int2_route.md2_cfg.int2_6d + | pin_int2_route.md2_cfg.int2_double_tap + | pin_int2_route.md2_cfg.int2_ff + | pin_int2_route.md2_cfg.int2_wu + | pin_int2_route.md2_cfg.int2_single_tap + | pin_int2_route.md2_cfg.int2_sleep_change + | val->int1_ctrl.den_drdy_flag + | val->int1_ctrl.int1_boot + | val->int1_ctrl.int1_cnt_bdr + | val->int1_ctrl.int1_drdy_g + | val->int1_ctrl.int1_drdy_xl + | val->int1_ctrl.int1_fifo_full + | val->int1_ctrl.int1_fifo_ovr + | val->int1_ctrl.int1_fifo_th + | val->md1_cfg.int1_shub + | val->md1_cfg.int1_6d + | val->md1_cfg.int1_double_tap + | val->md1_cfg.int1_ff + | val->md1_cfg.int1_wu + | val->md1_cfg.int1_single_tap + | val->md1_cfg.int1_sleep_change) != PROPERTY_DISABLE) { + tap_cfg2.interrupts_enable = PROPERTY_ENABLE; + } + else{ + tap_cfg2.interrupts_enable = PROPERTY_DISABLE; + } + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t*) &tap_cfg2, 1); + } + return ret; +} + +/** + * @brief Select the signal that need to route on int1 pad.[get] + * + * @param ctx read / write interface definitions + * @param val struct of registers: INT1_CTRL, MD1_CFG, + * EMB_FUNC_INT1, FSM_INT1_A, FSM_INT1_B + * + */ +int32_t lsm6dsox_pin_int1_route_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_pin_int1_route_t *val) +{ + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MLC_INT1, + (uint8_t*)&val->mlc_int1, 1); + } + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_INT1, + (uint8_t*)&val->emb_func_int1, 1); + } + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_INT1_A, + (uint8_t*)&val->fsm_int1_a, 1); + } + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_INT1_B, + (uint8_t*)&val->fsm_int1_b, 1); + } + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + if (ret == 0) { + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT1_CTRL, + (uint8_t*)&val->int1_ctrl, 1); + } + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MD1_CFG, (uint8_t*)&val->md1_cfg, 1); + } + + return ret; +} + +/** + * @brief Select the signal that need to route on int2 pad.[set] + * + * @param ctx read / write interface definitions + * @param val union of registers INT2_CTRL, MD2_CFG, + * EMB_FUNC_INT2, FSM_INT2_A, FSM_INT2_B + * + */ +int32_t lsm6dsox_pin_int2_route_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_pin_int2_route_t *val) +{ + lsm6dsox_pin_int1_route_t pin_int1_route; + lsm6dsox_tap_cfg2_t tap_cfg2; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); + if (ret == 0) { + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MLC_INT1, + (uint8_t*)&val->mlc_int2, 1); + } + if (ret == 0) { + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_INT2, + (uint8_t*)&val->emb_func_int2, 1); + } + if (ret == 0) { + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_INT2_A, + (uint8_t*)&val->fsm_int2_a, 1); + } + if (ret == 0) { + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_INT2_B, + (uint8_t*)&val->fsm_int2_b, 1); + } + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + + if (ret == 0) { + if (( val->emb_func_int2.int2_fsm_lc + | val->emb_func_int2.int2_sig_mot + | val->emb_func_int2.int2_step_detector + | val->emb_func_int2.int2_tilt + | val->fsm_int2_a.int2_fsm1 + | val->fsm_int2_a.int2_fsm2 + | val->fsm_int2_a.int2_fsm3 + | val->fsm_int2_a.int2_fsm4 + | val->fsm_int2_a.int2_fsm5 + | val->fsm_int2_a.int2_fsm6 + | val->fsm_int2_a.int2_fsm7 + | val->fsm_int2_a.int2_fsm8 + | val->fsm_int2_b.int2_fsm9 + | val->fsm_int2_b.int2_fsm10 + | val->fsm_int2_b.int2_fsm11 + | val->fsm_int2_b.int2_fsm12 + | val->fsm_int2_b.int2_fsm13 + | val->fsm_int2_b.int2_fsm14 + | val->fsm_int2_b.int2_fsm15 + | val->fsm_int2_b.int2_fsm16 + | val->mlc_int2.int2_mlc1 + | val->mlc_int2.int2_mlc2 + | val->mlc_int2.int2_mlc3 + | val->mlc_int2.int2_mlc4 + | val->mlc_int2.int2_mlc5 + | val->mlc_int2.int2_mlc6 + | val->mlc_int2.int2_mlc7 + | val->mlc_int2.int2_mlc8)!= PROPERTY_DISABLE ){ + val->md2_cfg.int2_emb_func = PROPERTY_ENABLE; + } + else{ + val->md2_cfg.int2_emb_func = PROPERTY_DISABLE; + } + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_INT2_CTRL, + (uint8_t*)&val->int2_ctrl, 1); + } + if (ret == 0) { + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MD2_CFG, (uint8_t*)&val->md2_cfg, 1); + } + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t*) &tap_cfg2, 1); + } + + if (ret == 0) { + ret = lsm6dsox_pin_int1_route_get(ctx, &pin_int1_route); + } + + if (ret == 0) { + if ( ( val->int2_ctrl.int2_cnt_bdr + | val->int2_ctrl.int2_drdy_g + | val->int2_ctrl.int2_drdy_temp + | val->int2_ctrl.int2_drdy_xl + | val->int2_ctrl.int2_fifo_full + | val->int2_ctrl.int2_fifo_ovr + | val->int2_ctrl.int2_fifo_th + | val->md2_cfg.int2_6d + | val->md2_cfg.int2_double_tap + | val->md2_cfg.int2_ff + | val->md2_cfg.int2_wu + | val->md2_cfg.int2_single_tap + | val->md2_cfg.int2_sleep_change + | pin_int1_route.int1_ctrl.den_drdy_flag + | pin_int1_route.int1_ctrl.int1_boot + | pin_int1_route.int1_ctrl.int1_cnt_bdr + | pin_int1_route.int1_ctrl.int1_drdy_g + | pin_int1_route.int1_ctrl.int1_drdy_xl + | pin_int1_route.int1_ctrl.int1_fifo_full + | pin_int1_route.int1_ctrl.int1_fifo_ovr + | pin_int1_route.int1_ctrl.int1_fifo_th + | pin_int1_route.md1_cfg.int1_6d + | pin_int1_route.md1_cfg.int1_double_tap + | pin_int1_route.md1_cfg.int1_ff + | pin_int1_route.md1_cfg.int1_wu + | pin_int1_route.md1_cfg.int1_single_tap + | pin_int1_route.md1_cfg.int1_sleep_change ) != PROPERTY_DISABLE) { + tap_cfg2.interrupts_enable = PROPERTY_ENABLE; + } + else{ + tap_cfg2.interrupts_enable = PROPERTY_DISABLE; + } + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t*) &tap_cfg2, 1); + } + return ret; +} + +/** + * @brief Select the signal that need to route on int2 pad.[get] + * + * @param ctx read / write interface definitions + * @param val union of registers INT2_CTRL, MD2_CFG, + * EMB_FUNC_INT2, FSM_INT2_A, FSM_INT2_B + * + */ +int32_t lsm6dsox_pin_int2_route_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_pin_int2_route_t *val) +{ + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MLC_INT2, + (uint8_t*)&val->mlc_int2, 1); + } + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_INT2, + (uint8_t*)&val->emb_func_int2, 1); + } + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_INT2_A, + (uint8_t*)&val->fsm_int2_a, 1); + } + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_INT2_B, + (uint8_t*)&val->fsm_int2_b, 1); + } + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + if (ret == 0) { + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT2_CTRL, + (uint8_t*)&val->int2_ctrl, 1); + } + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MD2_CFG, (uint8_t*)&val->md2_cfg, 1); + } + return ret; +} + +/** + * @brief Push-pull/open drain selection on interrupt pads.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of pp_od in reg CTRL3_C + * + */ +int32_t lsm6dsox_pin_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_pp_od_t val) +{ + lsm6dsox_i3c_bus_avb_t i3c_bus_avb; + lsm6dsox_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&ctrl3_c, 1); + if (ret == 0) { + ctrl3_c.pp_od = (uint8_t)val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&ctrl3_c, 1); + } + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_I3C_BUS_AVB, + (uint8_t*)&i3c_bus_avb, 1); + } + if (ret == 0) { + i3c_bus_avb.pd_dis_int1 = ( (uint8_t) val & 0x02U ) >> 1; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_I3C_BUS_AVB, + (uint8_t*)&i3c_bus_avb, 1); + } + return ret; +} + +/** + * @brief Push-pull/open drain selection on interrupt pads.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of pp_od in reg CTRL3_C + * + */ +int32_t lsm6dsox_pin_mode_get(lsm6dsox_ctx_t *ctx, lsm6dsox_pp_od_t *val) +{ + lsm6dsox_i3c_bus_avb_t i3c_bus_avb; + lsm6dsox_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)&ctrl3_c, 1); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_I3C_BUS_AVB, + (uint8_t*)&i3c_bus_avb, 1); + } + + switch ( (i3c_bus_avb.pd_dis_int1 << 1) + ctrl3_c.pp_od) { + case LSM6DSOX_PUSH_PULL: + *val = LSM6DSOX_PUSH_PULL; + break; + case LSM6DSOX_OPEN_DRAIN: + *val = LSM6DSOX_OPEN_DRAIN; + break; + case LSM6DSOX_INT1_NOPULL_DOWN_INT2_PUSH_PULL: + *val = LSM6DSOX_INT1_NOPULL_DOWN_INT2_PUSH_PULL; + break; + case LSM6DSOX_INT1_NOPULL_DOWN_INT2_OPEN_DRAIN: + *val = LSM6DSOX_INT1_NOPULL_DOWN_INT2_OPEN_DRAIN; + break; + default: + *val = LSM6DSOX_PUSH_PULL; + break; + } + return ret; +} + +/** + * @brief Interrupt active-high/low.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of h_lactive in reg CTRL3_C + * + */ +int32_t lsm6dsox_pin_polarity_set(lsm6dsox_ctx_t *ctx, lsm6dsox_h_lactive_t val) +{ + lsm6dsox_ctrl3_c_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1); + if (ret == 0) { + reg.h_lactive = (uint8_t)val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1); + } + + return ret; +} + +/** + * @brief Interrupt active-high/low.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of h_lactive in reg CTRL3_C + * + */ +int32_t lsm6dsox_pin_polarity_get(lsm6dsox_ctx_t *ctx, lsm6dsox_h_lactive_t *val) +{ + lsm6dsox_ctrl3_c_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t*)®, 1); + + switch (reg.h_lactive) { + case LSM6DSOX_ACTIVE_HIGH: + *val = LSM6DSOX_ACTIVE_HIGH; + break; + case LSM6DSOX_ACTIVE_LOW: + *val = LSM6DSOX_ACTIVE_LOW; + break; + default: + *val = LSM6DSOX_ACTIVE_HIGH; + break; + } + return ret; +} + +/** + * @brief All interrupt signals become available on INT1 pin.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of int2_on_int1 in reg CTRL4_C + * + */ +int32_t lsm6dsox_all_on_int1_set(lsm6dsox_ctx_t *ctx, uint8_t val) +{ + lsm6dsox_ctrl4_c_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)®, 1); + if (ret == 0) { + reg.int2_on_int1 = val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)®, 1); + } + + return ret; +} + +/** + * @brief All interrupt signals become available on INT1 pin.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of int2_on_int1 in reg CTRL4_C + * + */ +int32_t lsm6dsox_all_on_int1_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_ctrl4_c_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)®, 1); + *val = reg.int2_on_int1; + + return ret; +} + +/** + * @brief Interrupt notification mode.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of lir in reg TAP_CFG0 + * + */ +int32_t lsm6dsox_int_notification_set(lsm6dsox_ctx_t *ctx, lsm6dsox_lir_t val) +{ + lsm6dsox_tap_cfg0_t tap_cfg0; + lsm6dsox_page_rw_t page_rw; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*) &tap_cfg0, 1); + if (ret == 0) { + tap_cfg0.lir = (uint8_t)val & 0x01U; + tap_cfg0.int_clr_on_read = (uint8_t)val & 0x01U; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*) &tap_cfg0, 1); + } + if (ret == 0) { + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); + } + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1); + } + if (ret == 0) { + page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1); + } + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + + return ret; +} + +/** + * @brief Interrupt notification mode.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of lir in reg TAP_CFG0 + * + */ +int32_t lsm6dsox_int_notification_get(lsm6dsox_ctx_t *ctx, lsm6dsox_lir_t *val) +{ + lsm6dsox_tap_cfg0_t tap_cfg0; + lsm6dsox_page_rw_t page_rw; + int32_t ret; + + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*) &tap_cfg0, 1); + if (ret == 0) { + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); + } + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1); + } + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + if (ret == 0) { + switch ((page_rw.emb_func_lir << 1) | tap_cfg0.lir) { + case LSM6DSOX_ALL_INT_PULSED: + *val = LSM6DSOX_ALL_INT_PULSED; + break; + case LSM6DSOX_BASE_LATCHED_EMB_PULSED: + *val = LSM6DSOX_BASE_LATCHED_EMB_PULSED; + break; + case LSM6DSOX_BASE_PULSED_EMB_LATCHED: + *val = LSM6DSOX_BASE_PULSED_EMB_LATCHED; + break; + case LSM6DSOX_ALL_INT_LATCHED: + *val = LSM6DSOX_ALL_INT_LATCHED; + break; + default: + *val = LSM6DSOX_ALL_INT_PULSED; + break; + } + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); + } + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t*) &page_rw, 1); + } + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DSOX_Wake_Up_event + * @brief This section groups all the functions that manage the Wake Up + * event generation. + * @{ + * + */ + +/** + * @brief Weight of 1 LSB of wakeup threshold.[set] + * 0: 1 LSB =FS_XL / 64 + * 1: 1 LSB = FS_XL / 256 + * + * @param ctx read / write interface definitions + * @param val change the values of wake_ths_w in + * reg WAKE_UP_DUR + * + */ +int32_t lsm6dsox_wkup_ths_weight_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_wake_ths_w_t val) +{ + lsm6dsox_wake_up_dur_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)®, 1); + if (ret == 0) { + reg.wake_ths_w = (uint8_t)val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Weight of 1 LSB of wakeup threshold.[get] + * 0: 1 LSB =FS_XL / 64 + * 1: 1 LSB = FS_XL / 256 + * + * @param ctx read / write interface definitions + * @param val Get the values of wake_ths_w in + * reg WAKE_UP_DUR + * + */ +int32_t lsm6dsox_wkup_ths_weight_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_wake_ths_w_t *val) +{ + lsm6dsox_wake_up_dur_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)®, 1); + + switch (reg.wake_ths_w) { + case LSM6DSOX_LSb_FS_DIV_64: + *val = LSM6DSOX_LSb_FS_DIV_64; + break; + case LSM6DSOX_LSb_FS_DIV_256: + *val = LSM6DSOX_LSb_FS_DIV_256; + break; + default: + *val = LSM6DSOX_LSb_FS_DIV_64; + break; + } + return ret; +} + +/** + * @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in + * WAKE_UP_DUR.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of wk_ths in reg WAKE_UP_THS + * + */ +int32_t lsm6dsox_wkup_threshold_set(lsm6dsox_ctx_t *ctx, uint8_t val) +{ + lsm6dsox_wake_up_ths_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t*)®, 1); + if (ret == 0) { + reg.wk_ths = val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in + * WAKE_UP_DUR.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of wk_ths in reg WAKE_UP_THS + * + */ +int32_t lsm6dsox_wkup_threshold_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_wake_up_ths_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t*)®, 1); + *val = reg.wk_ths; + + return ret; +} + +/** + * @brief Wake up duration event.[set] + * 1LSb = 1 / ODR + * + * @param ctx read / write interface definitions + * @param val change the values of usr_off_on_wu in reg WAKE_UP_THS + * + */ +int32_t lsm6dsox_xl_usr_offset_on_wkup_set(lsm6dsox_ctx_t *ctx, uint8_t val) +{ + lsm6dsox_wake_up_ths_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t*)®, 1); + if (ret == 0) { + reg.usr_off_on_wu = val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Wake up duration event.[get] + * 1LSb = 1 / ODR + * + * @param ctx read / write interface definitions + * @param val change the values of usr_off_on_wu in reg WAKE_UP_THS + * + */ +int32_t lsm6dsox_xl_usr_offset_on_wkup_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_wake_up_ths_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t*)®, 1); + *val = reg.usr_off_on_wu; + + return ret; +} + +/** + * @brief Wake up duration event.[set] + * 1LSb = 1 / ODR + * + * @param ctx read / write interface definitions + * @param val change the values of wake_dur in reg WAKE_UP_DUR + * + */ +int32_t lsm6dsox_wkup_dur_set(lsm6dsox_ctx_t *ctx, uint8_t val) +{ + lsm6dsox_wake_up_dur_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)®, 1); + if (ret == 0) { + reg.wake_dur = val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Wake up duration event.[get] + * 1LSb = 1 / ODR + * + * @param ctx read / write interface definitions + * @param val change the values of wake_dur in reg WAKE_UP_DUR + * + */ +int32_t lsm6dsox_wkup_dur_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_wake_up_dur_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)®, 1); + *val = reg.wake_dur; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DSOX_ Activity/Inactivity_detection + * @brief This section groups all the functions concerning + * activity/inactivity detection. + * @{ + * + */ + +/** + * @brief Enables gyroscope Sleep mode.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of sleep_g in reg CTRL4_C + * + */ +int32_t lsm6dsox_gy_sleep_mode_set(lsm6dsox_ctx_t *ctx, uint8_t val) +{ + lsm6dsox_ctrl4_c_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)®, 1); + if (ret == 0) { + reg.sleep_g = val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Enables gyroscope Sleep mode.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of sleep_g in reg CTRL4_C + * + */ +int32_t lsm6dsox_gy_sleep_mode_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_ctrl4_c_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t*)®, 1); + *val = reg.sleep_g; + + return ret; +} + +/** + * @brief Drives the sleep status instead of + * sleep change on INT pins + * (only if INT1_SLEEP_CHANGE or + * INT2_SLEEP_CHANGE bits are enabled).[set] + * + * @param ctx read / write interface definitions + * @param val change the values of sleep_status_on_int in reg TAP_CFG0 + * + */ +int32_t lsm6dsox_act_pin_notification_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_sleep_status_on_int_t val) +{ + lsm6dsox_tap_cfg0_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)®, 1); + if (ret == 0) { + reg.sleep_status_on_int = (uint8_t)val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Drives the sleep status instead of + * sleep change on INT pins (only if + * INT1_SLEEP_CHANGE or + * INT2_SLEEP_CHANGE bits are enabled).[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of sleep_status_on_int in reg TAP_CFG0 + * + */ +int32_t lsm6dsox_act_pin_notification_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_sleep_status_on_int_t *val) +{ + lsm6dsox_tap_cfg0_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)®, 1); + switch (reg.sleep_status_on_int) { + case LSM6DSOX_DRIVE_SLEEP_CHG_EVENT: + *val = LSM6DSOX_DRIVE_SLEEP_CHG_EVENT; + break; + case LSM6DSOX_DRIVE_SLEEP_STATUS: + *val = LSM6DSOX_DRIVE_SLEEP_STATUS; + break; + default: + *val = LSM6DSOX_DRIVE_SLEEP_CHG_EVENT; + break; + } + return ret; +} + +/** + * @brief Enable inactivity function.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of inact_en in reg TAP_CFG2 + * + */ +int32_t lsm6dsox_act_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_inact_en_t val) +{ + lsm6dsox_tap_cfg2_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t*)®, 1); + if (ret == 0) { + reg.inact_en = (uint8_t)val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Enable inactivity function.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of inact_en in reg TAP_CFG2 + * + */ +int32_t lsm6dsox_act_mode_get(lsm6dsox_ctx_t *ctx, lsm6dsox_inact_en_t *val) +{ + lsm6dsox_tap_cfg2_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t*)®, 1); + switch (reg.inact_en) { + case LSM6DSOX_XL_AND_GY_NOT_AFFECTED: + *val = LSM6DSOX_XL_AND_GY_NOT_AFFECTED; + break; + case LSM6DSOX_XL_12Hz5_GY_NOT_AFFECTED: + *val = LSM6DSOX_XL_12Hz5_GY_NOT_AFFECTED; + break; + case LSM6DSOX_XL_12Hz5_GY_SLEEP: + *val = LSM6DSOX_XL_12Hz5_GY_SLEEP; + break; + case LSM6DSOX_XL_12Hz5_GY_PD: + *val = LSM6DSOX_XL_12Hz5_GY_PD; + break; + default: + *val = LSM6DSOX_XL_AND_GY_NOT_AFFECTED; + break; + } + return ret; +} + +/** + * @brief Duration to go in sleep mode.[set] + * 1 LSb = 512 / ODR + * + * @param ctx read / write interface definitions + * @param val change the values of sleep_dur in reg WAKE_UP_DUR + * + */ +int32_t lsm6dsox_act_sleep_dur_set(lsm6dsox_ctx_t *ctx, uint8_t val) +{ + lsm6dsox_wake_up_dur_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)®, 1); + if (ret == 0) { + reg.sleep_dur = val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Duration to go in sleep mode.[get] + * 1 LSb = 512 / ODR + * + * @param ctx read / write interface definitions + * @param val change the values of sleep_dur in reg WAKE_UP_DUR + * + */ +int32_t lsm6dsox_act_sleep_dur_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_wake_up_dur_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)®, 1); + *val = reg.sleep_dur; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DSOX_tap_generator + * @brief This section groups all the functions that manage the + * tap and double tap event generation. + * @{ + * + */ + +/** + * @brief Enable Z direction in tap recognition.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of tap_z_en in reg TAP_CFG0 + * + */ +int32_t lsm6dsox_tap_detection_on_z_set(lsm6dsox_ctx_t *ctx, uint8_t val) +{ + lsm6dsox_tap_cfg0_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)®, 1); + if (ret == 0) { + reg.tap_z_en = val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Enable Z direction in tap recognition.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of tap_z_en in reg TAP_CFG0 + * + */ +int32_t lsm6dsox_tap_detection_on_z_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_tap_cfg0_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)®, 1); + *val = reg.tap_z_en; + + return ret; +} + +/** + * @brief Enable Y direction in tap recognition.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of tap_y_en in reg TAP_CFG0 + * + */ +int32_t lsm6dsox_tap_detection_on_y_set(lsm6dsox_ctx_t *ctx, uint8_t val) +{ + lsm6dsox_tap_cfg0_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)®, 1); + if (ret == 0) { + reg.tap_y_en = val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Enable Y direction in tap recognition.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of tap_y_en in reg TAP_CFG0 + * + */ +int32_t lsm6dsox_tap_detection_on_y_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_tap_cfg0_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)®, 1); + *val = reg.tap_y_en; + + return ret; +} + +/** + * @brief Enable X direction in tap recognition.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of tap_x_en in reg TAP_CFG0 + * + */ +int32_t lsm6dsox_tap_detection_on_x_set(lsm6dsox_ctx_t *ctx, uint8_t val) +{ + lsm6dsox_tap_cfg0_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)®, 1); + if (ret == 0) { + reg.tap_x_en = val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Enable X direction in tap recognition.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of tap_x_en in reg TAP_CFG0 + * + */ +int32_t lsm6dsox_tap_detection_on_x_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_tap_cfg0_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t*)®, 1); + *val = reg.tap_x_en; + + return ret; +} + +/** + * @brief X-axis tap recognition threshold.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of tap_ths_x in reg TAP_CFG1 + * + */ +int32_t lsm6dsox_tap_threshold_x_set(lsm6dsox_ctx_t *ctx, uint8_t val) +{ + lsm6dsox_tap_cfg1_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG1, (uint8_t*)®, 1); + if (ret == 0) { + reg.tap_ths_x = val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG1, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief X-axis tap recognition threshold.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of tap_ths_x in reg TAP_CFG1 + * + */ +int32_t lsm6dsox_tap_threshold_x_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_tap_cfg1_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG1, (uint8_t*)®, 1); + *val = reg.tap_ths_x; + + return ret; +} + +/** + * @brief Selection of axis priority for TAP detection.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of tap_priority in + * reg TAP_CFG1 + * + */ +int32_t lsm6dsox_tap_axis_priority_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_tap_priority_t val) +{ + lsm6dsox_tap_cfg1_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG1, (uint8_t*)®, 1); + if (ret == 0) { + reg.tap_priority = (uint8_t)val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG1, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Selection of axis priority for TAP detection.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of tap_priority in + * reg TAP_CFG1 + * + */ +int32_t lsm6dsox_tap_axis_priority_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_tap_priority_t *val) +{ + lsm6dsox_tap_cfg1_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG1, (uint8_t*)®, 1); + switch (reg.tap_priority) { + case LSM6DSOX_XYZ: + *val = LSM6DSOX_XYZ; + break; + case LSM6DSOX_YXZ: + *val = LSM6DSOX_YXZ; + break; + case LSM6DSOX_XZY: + *val = LSM6DSOX_XZY; + break; + case LSM6DSOX_ZYX: + *val = LSM6DSOX_ZYX; + break; + case LSM6DSOX_YZX: + *val = LSM6DSOX_YZX; + break; + case LSM6DSOX_ZXY: + *val = LSM6DSOX_ZXY; + break; + default: + *val = LSM6DSOX_XYZ; + break; + } + return ret; +} + +/** + * @brief Y-axis tap recognition threshold.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of tap_ths_y in reg TAP_CFG2 + * + */ +int32_t lsm6dsox_tap_threshold_y_set(lsm6dsox_ctx_t *ctx, uint8_t val) +{ + lsm6dsox_tap_cfg2_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t*)®, 1); + if (ret == 0) { + reg.tap_ths_y = val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Y-axis tap recognition threshold.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of tap_ths_y in reg TAP_CFG2 + * + */ +int32_t lsm6dsox_tap_threshold_y_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_tap_cfg2_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t*)®, 1); + *val = reg.tap_ths_y; + + return ret; +} + +/** + * @brief Z-axis recognition threshold.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of tap_ths_z in reg TAP_THS_6D + * + */ +int32_t lsm6dsox_tap_threshold_z_set(lsm6dsox_ctx_t *ctx, uint8_t val) +{ + lsm6dsox_tap_ths_6d_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t*)®, 1); + if (ret == 0) { + reg.tap_ths_z = val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Z-axis recognition threshold.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of tap_ths_z in reg TAP_THS_6D + * + */ +int32_t lsm6dsox_tap_threshold_z_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_tap_ths_6d_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t*)®, 1); + *val = reg.tap_ths_z; + + return ret; +} + +/** + * @brief Maximum duration is the maximum time of an + * over threshold signal detection to be recognized + * as a tap event. The default value of these bits + * is 00b which corresponds to 4*ODR_XL time. + * If the SHOCK[1:0] bits are set to a different + * value, 1LSB corresponds to 8*ODR_XL time.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of shock in reg INT_DUR2 + * + */ +int32_t lsm6dsox_tap_shock_set(lsm6dsox_ctx_t *ctx, uint8_t val) +{ + lsm6dsox_int_dur2_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t*)®, 1); + if (ret == 0) { + reg.shock = val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Maximum duration is the maximum time of an + * over threshold signal detection to be recognized + * as a tap event. The default value of these bits + * is 00b which corresponds to 4*ODR_XL time. + * If the SHOCK[1:0] bits are set to a different + * value, 1LSB corresponds to 8*ODR_XL time.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of shock in reg INT_DUR2 + * + */ +int32_t lsm6dsox_tap_shock_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_int_dur2_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t*)®, 1); + *val = reg.shock; + + return ret; +} + +/** + * @brief Quiet time is the time after the first detected + * tap in which there must not be any over threshold + * event. + * The default value of these bits is 00b which + * corresponds to 2*ODR_XL time. If the QUIET[1:0] + * bits are set to a different value, + * 1LSB corresponds to 4*ODR_XL time.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of quiet in reg INT_DUR2 + * + */ +int32_t lsm6dsox_tap_quiet_set(lsm6dsox_ctx_t *ctx, uint8_t val) +{ + lsm6dsox_int_dur2_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t*)®, 1); + if (ret == 0) { + reg.quiet = val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Quiet time is the time after the first detected + * tap in which there must not be any over threshold + * event. + * The default value of these bits is 00b which + * corresponds to 2*ODR_XL time. + * If the QUIET[1:0] bits are set to a different + * value, 1LSB corresponds to 4*ODR_XL time.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of quiet in reg INT_DUR2 + * + */ +int32_t lsm6dsox_tap_quiet_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_int_dur2_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t*)®, 1); + *val = reg.quiet; + + return ret; +} + +/** + * @brief When double tap recognition is enabled, + * this register expresses the maximum time + * between two consecutive detected taps to + * determine a double tap event. + * The default value of these bits is 0000b which + * corresponds to 16*ODR_XL time. + * If the DUR[3:0] bits are set to a different value, + * 1LSB corresponds to 32*ODR_XL time.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of dur in reg INT_DUR2 + * + */ +int32_t lsm6dsox_tap_dur_set(lsm6dsox_ctx_t *ctx, uint8_t val) +{ + lsm6dsox_int_dur2_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t*)®, 1); + if (ret == 0) { + reg.dur = val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief When double tap recognition is enabled, + * this register expresses the maximum time + * between two consecutive detected taps to + * determine a double tap event. + * The default value of these bits is 0000b which + * corresponds to 16*ODR_XL time. If the DUR[3:0] + * bits are set to a different value, + * 1LSB corresponds to 32*ODR_XL time.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of dur in reg INT_DUR2 + * + */ +int32_t lsm6dsox_tap_dur_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_int_dur2_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t*)®, 1); + *val = reg.dur; + + return ret; +} + +/** + * @brief Single/double-tap event enable.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of single_double_tap in reg WAKE_UP_THS + * + */ +int32_t lsm6dsox_tap_mode_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_single_double_tap_t val) +{ + lsm6dsox_wake_up_ths_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t*)®, 1); + if (ret == 0) { + reg.single_double_tap = (uint8_t)val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Single/double-tap event enable.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of single_double_tap in reg WAKE_UP_THS + * + */ +int32_t lsm6dsox_tap_mode_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_single_double_tap_t *val) +{ + lsm6dsox_wake_up_ths_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t*)®, 1); + + switch (reg.single_double_tap) { + case LSM6DSOX_ONLY_SINGLE: + *val = LSM6DSOX_ONLY_SINGLE; + break; + case LSM6DSOX_BOTH_SINGLE_DOUBLE: + *val = LSM6DSOX_BOTH_SINGLE_DOUBLE; + break; + default: + *val = LSM6DSOX_ONLY_SINGLE; + break; + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DSOX_ Six_position_detection(6D/4D) + * @brief This section groups all the functions concerning six position + * detection (6D). + * @{ + * + */ + +/** + * @brief Threshold for 4D/6D function.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of sixd_ths in reg TAP_THS_6D + * + */ +int32_t lsm6dsox_6d_threshold_set(lsm6dsox_ctx_t *ctx, lsm6dsox_sixd_ths_t val) +{ + lsm6dsox_tap_ths_6d_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t*)®, 1); + if (ret == 0) { + reg.sixd_ths = (uint8_t)val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Threshold for 4D/6D function.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of sixd_ths in reg TAP_THS_6D + * + */ +int32_t lsm6dsox_6d_threshold_get(lsm6dsox_ctx_t *ctx, lsm6dsox_sixd_ths_t *val) +{ + lsm6dsox_tap_ths_6d_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t*)®, 1); + switch (reg.sixd_ths) { + case LSM6DSOX_DEG_80: + *val = LSM6DSOX_DEG_80; + break; + case LSM6DSOX_DEG_70: + *val = LSM6DSOX_DEG_70; + break; + case LSM6DSOX_DEG_60: + *val = LSM6DSOX_DEG_60; + break; + case LSM6DSOX_DEG_50: + *val = LSM6DSOX_DEG_50; + break; + default: + *val = LSM6DSOX_DEG_80; + break; + } + return ret; +} + +/** + * @brief 4D orientation detection enable.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of d4d_en in reg TAP_THS_6D + * + */ +int32_t lsm6dsox_4d_mode_set(lsm6dsox_ctx_t *ctx, uint8_t val) +{ + lsm6dsox_tap_ths_6d_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t*)®, 1); + if (ret == 0) { + reg.d4d_en = val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief 4D orientation detection enable.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of d4d_en in reg TAP_THS_6D + * + */ +int32_t lsm6dsox_4d_mode_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_tap_ths_6d_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t*)®, 1); + *val = reg.d4d_en; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DSOX_free_fall + * @brief This section group all the functions concerning the free + * fall detection. + * @{ + * +*/ +/** + * @brief Free fall threshold setting.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of ff_ths in reg FREE_FALL + * + */ +int32_t lsm6dsox_ff_threshold_set(lsm6dsox_ctx_t *ctx, lsm6dsox_ff_ths_t val) +{ + lsm6dsox_free_fall_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FREE_FALL, (uint8_t*)®, 1); + if (ret == 0) { + reg.ff_ths = (uint8_t)val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FREE_FALL, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Free fall threshold setting.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of ff_ths in reg FREE_FALL + * + */ +int32_t lsm6dsox_ff_threshold_get(lsm6dsox_ctx_t *ctx, lsm6dsox_ff_ths_t *val) +{ + lsm6dsox_free_fall_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FREE_FALL, (uint8_t*)®, 1); + switch (reg.ff_ths) { + case LSM6DSOX_FF_TSH_156mg: + *val = LSM6DSOX_FF_TSH_156mg; + break; + case LSM6DSOX_FF_TSH_219mg: + *val = LSM6DSOX_FF_TSH_219mg; + break; + case LSM6DSOX_FF_TSH_250mg: + *val = LSM6DSOX_FF_TSH_250mg; + break; + case LSM6DSOX_FF_TSH_312mg: + *val = LSM6DSOX_FF_TSH_312mg; + break; + case LSM6DSOX_FF_TSH_344mg: + *val = LSM6DSOX_FF_TSH_344mg; + break; + case LSM6DSOX_FF_TSH_406mg: + *val = LSM6DSOX_FF_TSH_406mg; + break; + case LSM6DSOX_FF_TSH_469mg: + *val = LSM6DSOX_FF_TSH_469mg; + break; + case LSM6DSOX_FF_TSH_500mg: + *val = LSM6DSOX_FF_TSH_500mg; + break; + default: + *val = LSM6DSOX_FF_TSH_156mg; + break; + } + return ret; +} + +/** + * @brief Free-fall duration event.[set] + * 1LSb = 1 / ODR + * + * @param ctx read / write interface definitions + * @param val change the values of ff_dur in reg FREE_FALL + * + */ +int32_t lsm6dsox_ff_dur_set(lsm6dsox_ctx_t *ctx, uint8_t val) +{ + lsm6dsox_wake_up_dur_t wake_up_dur; + lsm6dsox_free_fall_t free_fall; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FREE_FALL, (uint8_t*)&free_fall, 1); + } + if (ret == 0) { + wake_up_dur.ff_dur = ((uint8_t)val & 0x20U) >> 5; + free_fall.ff_dur = (uint8_t)val & 0x1FU; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_WAKE_UP_DUR, + (uint8_t*)&wake_up_dur, 1); + } + if (ret == 0) { + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FREE_FALL, (uint8_t*)&free_fall, 1); + } + return ret; +} + +/** + * @brief Free-fall duration event.[get] + * 1LSb = 1 / ODR + * + * @param ctx read / write interface definitions + * @param val change the values of ff_dur in reg FREE_FALL + * + */ +int32_t lsm6dsox_ff_dur_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_wake_up_dur_t wake_up_dur; + lsm6dsox_free_fall_t free_fall; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FREE_FALL, (uint8_t*)&free_fall, 1); + *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DSOX_fifo + * @brief This section group all the functions concerning the fifo usage + * @{ + * + */ + +/** + * @brief FIFO watermark level selection.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of wtm in reg FIFO_CTRL1 + * + */ +int32_t lsm6dsox_fifo_watermark_set(lsm6dsox_ctx_t *ctx, uint16_t val) +{ + lsm6dsox_fifo_ctrl1_t fifo_ctrl1; + lsm6dsox_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1); + if (ret == 0) { + fifo_ctrl1.wtm = 0x00FFU & (uint8_t)val; + fifo_ctrl2.wtm = (uint8_t)(( 0x0100U & val ) >> 8); + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL1, (uint8_t*)&fifo_ctrl1, 1); + } + if (ret == 0) { + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1); + } + return ret; +} + +/** + * @brief FIFO watermark level selection.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of wtm in reg FIFO_CTRL1 + * + */ +int32_t lsm6dsox_fifo_watermark_get(lsm6dsox_ctx_t *ctx, uint16_t *val) +{ + lsm6dsox_fifo_ctrl1_t fifo_ctrl1; + lsm6dsox_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL1, (uint8_t*)&fifo_ctrl1, 1); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1); + *val = ((uint16_t)fifo_ctrl2.wtm << 8) + (uint16_t)fifo_ctrl1.wtm; + } + return ret; +} + +/** + * @brief FIFO compression feature initialization request [set]. + * + * @param ctx read / write interface definitions + * @param val change the values of FIFO_COMPR_INIT in + * reg EMB_FUNC_INIT_B + * + */ +int32_t lsm6dsox_compression_algo_init_set(lsm6dsox_ctx_t *ctx, uint8_t val) +{ + lsm6dsox_emb_func_init_b_t reg; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B, (uint8_t*)®, 1); + } + if (ret == 0) { + reg.fifo_compr_init = val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B, (uint8_t*)®, 1); + } + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + + return ret; +} + +/** + * @brief FIFO compression feature initialization request [get]. + * + * @param ctx read / write interface definitions + * @param val change the values of FIFO_COMPR_INIT in + * reg EMB_FUNC_INIT_B + * + */ +int32_t lsm6dsox_compression_algo_init_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_emb_func_init_b_t reg; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B, (uint8_t*)®, 1); + } + if (ret == 0) { + *val = reg.fifo_compr_init; + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + + return ret; +} + +/** + * @brief Enable and configure compression algo.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of uncoptr_rate in + * reg FIFO_CTRL2 + * + */ +int32_t lsm6dsox_compression_algo_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_uncoptr_rate_t val) +{ + lsm6dsox_emb_func_en_b_t emb_func_en_b; + lsm6dsox_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B, + (uint8_t*)&emb_func_en_b, 1); + } + if (ret == 0) { + emb_func_en_b.fifo_compr_en = ((uint8_t)val & 0x04U) >> 2; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B, + (uint8_t*)&emb_func_en_b, 1); + } + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + if (ret == 0) { + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, + (uint8_t*)&fifo_ctrl2, 1); + } + if (ret == 0) { + fifo_ctrl2.fifo_compr_rt_en = ((uint8_t)val & 0x04U) >> 2; + fifo_ctrl2.uncoptr_rate = (uint8_t)val & 0x03U; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL2, + (uint8_t*)&fifo_ctrl2, 1); + } + return ret; +} + +/** + * @brief Enable and configure compression algo.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of uncoptr_rate in + * reg FIFO_CTRL2 + * + */ +int32_t lsm6dsox_compression_algo_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_uncoptr_rate_t *val) +{ + lsm6dsox_fifo_ctrl2_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)®, 1); + + switch ((reg.fifo_compr_rt_en<<2) | reg.uncoptr_rate) { + case LSM6DSOX_CMP_DISABLE: + *val = LSM6DSOX_CMP_DISABLE; + break; + case LSM6DSOX_CMP_ALWAYS: + *val = LSM6DSOX_CMP_ALWAYS; + break; + case LSM6DSOX_CMP_8_TO_1: + *val = LSM6DSOX_CMP_8_TO_1; + break; + case LSM6DSOX_CMP_16_TO_1: + *val = LSM6DSOX_CMP_16_TO_1; + break; + case LSM6DSOX_CMP_32_TO_1: + *val = LSM6DSOX_CMP_32_TO_1; + break; + default: + *val = LSM6DSOX_CMP_DISABLE; + break; + } + return ret; +} + +/** + * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of odrchg_en in reg FIFO_CTRL2 + * + */ +int32_t lsm6dsox_fifo_virtual_sens_odr_chg_set(lsm6dsox_ctx_t *ctx, + uint8_t val) +{ + lsm6dsox_fifo_ctrl2_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)®, 1); + if (ret == 0) { + reg.odrchg_en = val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of odrchg_en in reg FIFO_CTRL2 + * + */ +int32_t lsm6dsox_fifo_virtual_sens_odr_chg_get(lsm6dsox_ctx_t *ctx, + uint8_t *val) +{ + lsm6dsox_fifo_ctrl2_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)®, 1); + *val = reg.odrchg_en; + + return ret; +} + +/** + * @brief Enables/Disables compression algorithm runtime.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of fifo_compr_rt_en in + * reg FIFO_CTRL2 + * + */ +int32_t lsm6dsox_compression_algo_real_time_set(lsm6dsox_ctx_t *ctx, + uint8_t val) +{ + lsm6dsox_fifo_ctrl2_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)®, 1); + if (ret == 0) { + reg.fifo_compr_rt_en = val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Enables/Disables compression algorithm runtime. [get] + * + * @param ctx read / write interface definitions + * @param val change the values of fifo_compr_rt_en in reg FIFO_CTRL2 + * + */ +int32_t lsm6dsox_compression_algo_real_time_get(lsm6dsox_ctx_t *ctx, + uint8_t *val) +{ + lsm6dsox_fifo_ctrl2_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)®, 1); + *val = reg.fifo_compr_rt_en; + + return ret; +} + +/** + * @brief Sensing chain FIFO stop values memorization at + * threshold level.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of stop_on_wtm in reg FIFO_CTRL2 + * + */ +int32_t lsm6dsox_fifo_stop_on_wtm_set(lsm6dsox_ctx_t *ctx, uint8_t val) +{ + lsm6dsox_fifo_ctrl2_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)®, 1); + if (ret == 0) { + reg.stop_on_wtm = val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Sensing chain FIFO stop values memorization at + * threshold level.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of stop_on_wtm in reg FIFO_CTRL2 + * + */ +int32_t lsm6dsox_fifo_stop_on_wtm_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_fifo_ctrl2_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t*)®, 1); + *val = reg.stop_on_wtm; + + return ret; +} + +/** + * @brief Selects Batching Data Rate (writing frequency in FIFO) + * for accelerometer data.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of bdr_xl in reg FIFO_CTRL3 + * + */ +int32_t lsm6dsox_fifo_xl_batch_set(lsm6dsox_ctx_t *ctx, lsm6dsox_bdr_xl_t val) +{ + lsm6dsox_fifo_ctrl3_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL3, (uint8_t*)®, 1); + if (ret == 0) { + reg.bdr_xl = (uint8_t)val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL3, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Selects Batching Data Rate (writing frequency in FIFO) + * for accelerometer data.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of bdr_xl in reg FIFO_CTRL3 + * + */ +int32_t lsm6dsox_fifo_xl_batch_get(lsm6dsox_ctx_t *ctx, lsm6dsox_bdr_xl_t *val) +{ + lsm6dsox_fifo_ctrl3_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL3, (uint8_t*)®, 1); + switch (reg.bdr_xl) { + case LSM6DSOX_XL_NOT_BATCHED: + *val = LSM6DSOX_XL_NOT_BATCHED; + break; + case LSM6DSOX_XL_BATCHED_AT_12Hz5: + *val = LSM6DSOX_XL_BATCHED_AT_12Hz5; + break; + case LSM6DSOX_XL_BATCHED_AT_26Hz: + *val = LSM6DSOX_XL_BATCHED_AT_26Hz; + break; + case LSM6DSOX_XL_BATCHED_AT_52Hz: + *val = LSM6DSOX_XL_BATCHED_AT_52Hz; + break; + case LSM6DSOX_XL_BATCHED_AT_104Hz: + *val = LSM6DSOX_XL_BATCHED_AT_104Hz; + break; + case LSM6DSOX_XL_BATCHED_AT_208Hz: + *val = LSM6DSOX_XL_BATCHED_AT_208Hz; + break; + case LSM6DSOX_XL_BATCHED_AT_417Hz: + *val = LSM6DSOX_XL_BATCHED_AT_417Hz; + break; + case LSM6DSOX_XL_BATCHED_AT_833Hz: + *val = LSM6DSOX_XL_BATCHED_AT_833Hz; + break; + case LSM6DSOX_XL_BATCHED_AT_1667Hz: + *val = LSM6DSOX_XL_BATCHED_AT_1667Hz; + break; + case LSM6DSOX_XL_BATCHED_AT_3333Hz: + *val = LSM6DSOX_XL_BATCHED_AT_3333Hz; + break; + case LSM6DSOX_XL_BATCHED_AT_6667Hz: + *val = LSM6DSOX_XL_BATCHED_AT_6667Hz; + break; + case LSM6DSOX_XL_BATCHED_AT_6Hz5: + *val = LSM6DSOX_XL_BATCHED_AT_6Hz5; + break; + default: + *val = LSM6DSOX_XL_NOT_BATCHED; + break; + } + + return ret; +} + +/** + * @brief Selects Batching Data Rate (writing frequency in FIFO) + * for gyroscope data.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of bdr_gy in reg FIFO_CTRL3 + * + */ +int32_t lsm6dsox_fifo_gy_batch_set(lsm6dsox_ctx_t *ctx, lsm6dsox_bdr_gy_t val) +{ + lsm6dsox_fifo_ctrl3_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL3, (uint8_t*)®, 1); + if (ret == 0) { + reg.bdr_gy = (uint8_t)val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL3, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Selects Batching Data Rate (writing frequency in FIFO) + * for gyroscope data.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of bdr_gy in reg FIFO_CTRL3 + * + */ +int32_t lsm6dsox_fifo_gy_batch_get(lsm6dsox_ctx_t *ctx, lsm6dsox_bdr_gy_t *val) +{ + lsm6dsox_fifo_ctrl3_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL3, (uint8_t*)®, 1); + switch (reg.bdr_gy) { + case LSM6DSOX_GY_NOT_BATCHED: + *val = LSM6DSOX_GY_NOT_BATCHED; + break; + case LSM6DSOX_GY_BATCHED_AT_12Hz5: + *val = LSM6DSOX_GY_BATCHED_AT_12Hz5; + break; + case LSM6DSOX_GY_BATCHED_AT_26Hz: + *val = LSM6DSOX_GY_BATCHED_AT_26Hz; + break; + case LSM6DSOX_GY_BATCHED_AT_52Hz: + *val = LSM6DSOX_GY_BATCHED_AT_52Hz; + break; + case LSM6DSOX_GY_BATCHED_AT_104Hz: + *val = LSM6DSOX_GY_BATCHED_AT_104Hz; + break; + case LSM6DSOX_GY_BATCHED_AT_208Hz: + *val = LSM6DSOX_GY_BATCHED_AT_208Hz; + break; + case LSM6DSOX_GY_BATCHED_AT_417Hz: + *val = LSM6DSOX_GY_BATCHED_AT_417Hz; + break; + case LSM6DSOX_GY_BATCHED_AT_833Hz: + *val = LSM6DSOX_GY_BATCHED_AT_833Hz; + break; + case LSM6DSOX_GY_BATCHED_AT_1667Hz: + *val = LSM6DSOX_GY_BATCHED_AT_1667Hz; + break; + case LSM6DSOX_GY_BATCHED_AT_3333Hz: + *val = LSM6DSOX_GY_BATCHED_AT_3333Hz; + break; + case LSM6DSOX_GY_BATCHED_AT_6667Hz: + *val = LSM6DSOX_GY_BATCHED_AT_6667Hz; + break; + case LSM6DSOX_GY_BATCHED_AT_6Hz5: + *val = LSM6DSOX_GY_BATCHED_AT_6Hz5; + break; + default: + *val = LSM6DSOX_GY_NOT_BATCHED; + break; + } + return ret; +} + +/** + * @brief FIFO mode selection.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of fifo_mode in reg FIFO_CTRL4 + * + */ +int32_t lsm6dsox_fifo_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_fifo_mode_t val) +{ + lsm6dsox_fifo_ctrl4_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t*)®, 1); + if (ret == 0) { + reg.fifo_mode = (uint8_t)val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief FIFO mode selection.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of fifo_mode in reg FIFO_CTRL4 + * + */ +int32_t lsm6dsox_fifo_mode_get(lsm6dsox_ctx_t *ctx, lsm6dsox_fifo_mode_t *val) +{ + lsm6dsox_fifo_ctrl4_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t*)®, 1); + + switch (reg.fifo_mode) { + case LSM6DSOX_BYPASS_MODE: + *val = LSM6DSOX_BYPASS_MODE; + break; + case LSM6DSOX_FIFO_MODE: + *val = LSM6DSOX_FIFO_MODE; + break; + case LSM6DSOX_STREAM_TO_FIFO_MODE: + *val = LSM6DSOX_STREAM_TO_FIFO_MODE; + break; + case LSM6DSOX_BYPASS_TO_STREAM_MODE: + *val = LSM6DSOX_BYPASS_TO_STREAM_MODE; + break; + case LSM6DSOX_STREAM_MODE: + *val = LSM6DSOX_STREAM_MODE; + break; + case LSM6DSOX_BYPASS_TO_FIFO_MODE: + *val = LSM6DSOX_BYPASS_TO_FIFO_MODE; + break; + default: + *val = LSM6DSOX_BYPASS_MODE; + break; + } + return ret; +} + +/** + * @brief Selects Batching Data Rate (writing frequency in FIFO) + * for temperature data.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of odr_t_batch in reg FIFO_CTRL4 + * + */ +int32_t lsm6dsox_fifo_temp_batch_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_odr_t_batch_t val) +{ + lsm6dsox_fifo_ctrl4_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t*)®, 1); + if (ret == 0) { + reg.odr_t_batch = (uint8_t)val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Selects Batching Data Rate (writing frequency in FIFO) + * for temperature data.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of odr_t_batch in reg FIFO_CTRL4 + * + */ +int32_t lsm6dsox_fifo_temp_batch_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_odr_t_batch_t *val) +{ + lsm6dsox_fifo_ctrl4_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t*)®, 1); + + switch (reg.odr_t_batch) { + case LSM6DSOX_TEMP_NOT_BATCHED: + *val = LSM6DSOX_TEMP_NOT_BATCHED; + break; + case LSM6DSOX_TEMP_BATCHED_AT_1Hz6: + *val = LSM6DSOX_TEMP_BATCHED_AT_1Hz6; + break; + case LSM6DSOX_TEMP_BATCHED_AT_12Hz5: + *val = LSM6DSOX_TEMP_BATCHED_AT_12Hz5; + break; + case LSM6DSOX_TEMP_BATCHED_AT_52Hz: + *val = LSM6DSOX_TEMP_BATCHED_AT_52Hz; + break; + default: + *val = LSM6DSOX_TEMP_NOT_BATCHED; + break; + } + return ret; +} + +/** + * @brief Selects decimation for timestamp batching in FIFO. + * Writing rate will be the maximum rate between XL and + * GYRO BDR divided by decimation decoder.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of odr_ts_batch in reg FIFO_CTRL4 + * + */ +int32_t lsm6dsox_fifo_timestamp_decimation_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_odr_ts_batch_t val) +{ + lsm6dsox_fifo_ctrl4_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t*)®, 1); + if (ret == 0) { + reg.odr_ts_batch = (uint8_t)val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Selects decimation for timestamp batching in FIFO. + * Writing rate will be the maximum rate between XL and + * GYRO BDR divided by decimation decoder.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of odr_ts_batch in reg FIFO_CTRL4 + * + */ +int32_t lsm6dsox_fifo_timestamp_decimation_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_odr_ts_batch_t *val) +{ + lsm6dsox_fifo_ctrl4_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t*)®, 1); + switch (reg.odr_ts_batch) { + case LSM6DSOX_NO_DECIMATION: + *val = LSM6DSOX_NO_DECIMATION; + break; + case LSM6DSOX_DEC_1: + *val = LSM6DSOX_DEC_1; + break; + case LSM6DSOX_DEC_8: + *val = LSM6DSOX_DEC_8; + break; + case LSM6DSOX_DEC_32: + *val = LSM6DSOX_DEC_32; + break; + default: + *val = LSM6DSOX_NO_DECIMATION; + break; + } + return ret; +} + +/** + * @brief Selects the trigger for the internal counter of batching events + * between XL and gyro.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of trig_counter_bdr + * in reg COUNTER_BDR_REG1 + * + */ +int32_t lsm6dsox_fifo_cnt_event_batch_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_trig_counter_bdr_t val) +{ + lsm6dsox_counter_bdr_reg1_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, (uint8_t*)®, 1); + if (ret == 0) { + reg.trig_counter_bdr = (uint8_t)val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Selects the trigger for the internal counter of batching events + * between XL and gyro.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of trig_counter_bdr + * in reg COUNTER_BDR_REG1 + * + */ +int32_t lsm6dsox_fifo_cnt_event_batch_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_trig_counter_bdr_t *val) +{ + lsm6dsox_counter_bdr_reg1_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, (uint8_t*)®, 1); + switch (reg.trig_counter_bdr) { + case LSM6DSOX_XL_BATCH_EVENT: + *val = LSM6DSOX_XL_BATCH_EVENT; + break; + case LSM6DSOX_GYRO_BATCH_EVENT: + *val = LSM6DSOX_GYRO_BATCH_EVENT; + break; + default: + *val = LSM6DSOX_XL_BATCH_EVENT; + break; + } + return ret; +} + +/** + * @brief Resets the internal counter of batching vents for a single sensor. + * This bit is automatically reset to zero if it was set to ‘1’.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of rst_counter_bdr in + * reg COUNTER_BDR_REG1 + * + */ +int32_t lsm6dsox_rst_batch_counter_set(lsm6dsox_ctx_t *ctx, uint8_t val) +{ + lsm6dsox_counter_bdr_reg1_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, (uint8_t*)®, 1); + if (ret == 0) { + reg.rst_counter_bdr = val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief Resets the internal counter of batching events for a single sensor. + * This bit is automatically reset to zero if it was set to ‘1’.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of rst_counter_bdr in + * reg COUNTER_BDR_REG1 + * + */ +int32_t lsm6dsox_rst_batch_counter_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_counter_bdr_reg1_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, (uint8_t*)®, 1); + *val = reg.rst_counter_bdr; + + return ret; +} + +/** + * @brief Batch data rate counter.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of cnt_bdr_th in + * reg COUNTER_BDR_REG2 and COUNTER_BDR_REG1. + * + */ +int32_t lsm6dsox_batch_counter_threshold_set(lsm6dsox_ctx_t *ctx, uint16_t val) +{ + lsm6dsox_counter_bdr_reg1_t counter_bdr_reg1; + lsm6dsox_counter_bdr_reg2_t counter_bdr_reg2; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, + (uint8_t*)&counter_bdr_reg1, 1); + if (ret == 0) { + counter_bdr_reg2.cnt_bdr_th = 0x00FFU & (uint8_t)val; + counter_bdr_reg1.cnt_bdr_th = (uint8_t)(0x0700U & val) >> 8; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, + (uint8_t*)&counter_bdr_reg1, 1); + } + if (ret == 0) { + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_COUNTER_BDR_REG2, + (uint8_t*)&counter_bdr_reg2, 1); + } + return ret; +} + +/** + * @brief Batch data rate counter.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of cnt_bdr_th in + * reg COUNTER_BDR_REG2 and COUNTER_BDR_REG1. + * + */ +int32_t lsm6dsox_batch_counter_threshold_get(lsm6dsox_ctx_t *ctx, uint16_t *val) +{ + lsm6dsox_counter_bdr_reg1_t counter_bdr_reg1; + lsm6dsox_counter_bdr_reg2_t counter_bdr_reg2; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, + (uint8_t*)&counter_bdr_reg1, 1); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG2, + (uint8_t*)&counter_bdr_reg2, 1); + + *val = ((uint16_t)counter_bdr_reg1.cnt_bdr_th << 8) + + (uint16_t)counter_bdr_reg2.cnt_bdr_th; + } + + return ret; +} + +/** + * @brief Number of unread sensor data(TAG + 6 bytes) stored in FIFO.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of diff_fifo in reg FIFO_STATUS1 + * + */ +int32_t lsm6dsox_fifo_data_level_get(lsm6dsox_ctx_t *ctx, uint16_t *val) +{ + lsm6dsox_fifo_status1_t fifo_status1; + lsm6dsox_fifo_status2_t fifo_status2; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_STATUS1, + (uint8_t*)&fifo_status1, 1); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_STATUS2, + (uint8_t*)&fifo_status2, 1); + *val = ((uint16_t)fifo_status2.diff_fifo << 8) + + (uint16_t)fifo_status1.diff_fifo; + } + return ret; +} + +/** + * @brief FIFO status.[get] + * + * @param ctx read / write interface definitions + * @param val registers FIFO_STATUS2 + * + */ +int32_t lsm6dsox_fifo_status_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_fifo_status2_t *val) +{ + int32_t ret; + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_STATUS2, (uint8_t*) val, 1); + return ret; +} + +/** + * @brief Smart FIFO full status.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of fifo_full_ia in reg FIFO_STATUS2 + * + */ +int32_t lsm6dsox_fifo_full_flag_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_fifo_status2_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_STATUS2, (uint8_t*)®, 1); + *val = reg.fifo_full_ia; + + return ret; +} + +/** + * @brief FIFO overrun status.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of fifo_over_run_latched in + * reg FIFO_STATUS2 + * + */ +int32_t lsm6dsox_fifo_ovr_flag_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_fifo_status2_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_STATUS2, (uint8_t*)®, 1); + *val = reg.fifo_ovr_ia; + + return ret; +} + +/** + * @brief FIFO watermark status.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of fifo_wtm_ia in reg FIFO_STATUS2 + * + */ +int32_t lsm6dsox_fifo_wtm_flag_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_fifo_status2_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_STATUS2, (uint8_t*)®, 1); + *val = reg.fifo_wtm_ia; + + return ret; +} + +/** + * @brief Identifies the sensor in FIFO_DATA_OUT.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of tag_sensor in reg FIFO_DATA_OUT_TAG + * + */ +int32_t lsm6dsox_fifo_sensor_tag_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_fifo_tag_t *val) +{ + lsm6dsox_fifo_data_out_tag_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_DATA_OUT_TAG, (uint8_t*)®, 1); + switch (reg.tag_sensor) { + case LSM6DSOX_GYRO_NC_TAG: + *val = LSM6DSOX_GYRO_NC_TAG; + break; + case LSM6DSOX_XL_NC_TAG: + *val = LSM6DSOX_XL_NC_TAG; + break; + case LSM6DSOX_TEMPERATURE_TAG: + *val = LSM6DSOX_TEMPERATURE_TAG; + break; + case LSM6DSOX_CFG_CHANGE_TAG: + *val = LSM6DSOX_CFG_CHANGE_TAG; + break; + case LSM6DSOX_XL_NC_T_2_TAG: + *val = LSM6DSOX_XL_NC_T_2_TAG; + break; + case LSM6DSOX_XL_NC_T_1_TAG: + *val = LSM6DSOX_XL_NC_T_1_TAG; + break; + case LSM6DSOX_XL_2XC_TAG: + *val = LSM6DSOX_XL_2XC_TAG; + break; + case LSM6DSOX_XL_3XC_TAG: + *val = LSM6DSOX_XL_3XC_TAG; + break; + case LSM6DSOX_GYRO_NC_T_2_TAG: + *val = LSM6DSOX_GYRO_NC_T_2_TAG; + break; + case LSM6DSOX_GYRO_NC_T_1_TAG: + *val = LSM6DSOX_GYRO_NC_T_1_TAG; + break; + case LSM6DSOX_GYRO_2XC_TAG: + *val = LSM6DSOX_GYRO_2XC_TAG; + break; + case LSM6DSOX_GYRO_3XC_TAG: + *val = LSM6DSOX_GYRO_3XC_TAG; + break; + case LSM6DSOX_SENSORHUB_SLAVE0_TAG: + *val = LSM6DSOX_SENSORHUB_SLAVE0_TAG; + break; + case LSM6DSOX_SENSORHUB_SLAVE1_TAG: + *val = LSM6DSOX_SENSORHUB_SLAVE1_TAG; + break; + case LSM6DSOX_SENSORHUB_SLAVE2_TAG: + *val = LSM6DSOX_SENSORHUB_SLAVE2_TAG; + break; + case LSM6DSOX_SENSORHUB_SLAVE3_TAG: + *val = LSM6DSOX_SENSORHUB_SLAVE3_TAG; + break; + case LSM6DSOX_STEP_CPUNTER_TAG: + *val = LSM6DSOX_STEP_CPUNTER_TAG; + break; + case LSM6DSOX_GAME_ROTATION_TAG: + *val = LSM6DSOX_GAME_ROTATION_TAG; + break; + case LSM6DSOX_GEOMAG_ROTATION_TAG: + *val = LSM6DSOX_GEOMAG_ROTATION_TAG; + break; + case LSM6DSOX_ROTATION_TAG: + *val = LSM6DSOX_ROTATION_TAG; + break; + case LSM6DSOX_SENSORHUB_NACK_TAG: + *val = LSM6DSOX_SENSORHUB_NACK_TAG; + break; + default: + *val = LSM6DSOX_GYRO_NC_TAG; + break; + } + return ret; +} + +/** + * @brief : Enable FIFO batching of pedometer embedded + * function values.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of gbias_fifo_en in + * reg LSM6DSOX_EMB_FUNC_FIFO_CFG + * + */ +int32_t lsm6dsox_fifo_pedo_batch_set(lsm6dsox_ctx_t *ctx, uint8_t val) +{ + lsm6dsox_emb_func_fifo_cfg_t reg; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_FIFO_CFG, (uint8_t*)®, 1); + } + if (ret == 0) { + reg.pedo_fifo_en = val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_FIFO_CFG, + (uint8_t*)®, 1); + } + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + return ret; +} + +/** + * @brief Enable FIFO batching of pedometer embedded function values.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of pedo_fifo_en in + * reg LSM6DSOX_EMB_FUNC_FIFO_CFG + * + */ +int32_t lsm6dsox_fifo_pedo_batch_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_emb_func_fifo_cfg_t reg; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_FIFO_CFG, (uint8_t*)®, 1); + } + if (ret == 0) { + *val = reg.pedo_fifo_en; + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + return ret; +} + +/** + * @brief Enable FIFO batching data of first slave.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of batch_ext_sens_0_en in + * reg SLV0_CONFIG + * + */ +int32_t lsm6dsox_sh_batch_slave_0_set(lsm6dsox_ctx_t *ctx, uint8_t val) +{ + lsm6dsox_slv0_config_t reg; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV0_CONFIG, (uint8_t*)®, 1); + } + if (ret == 0) { + reg.batch_ext_sens_0_en = val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV0_CONFIG, (uint8_t*)®, 1); + } + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + return ret; +} + +/** + * @brief Enable FIFO batching data of first slave.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of batch_ext_sens_0_en in + * reg SLV0_CONFIG + * + */ +int32_t lsm6dsox_sh_batch_slave_0_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_slv0_config_t reg; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV0_CONFIG, (uint8_t*)®, 1); + } + if (ret == 0) { + *val = reg.batch_ext_sens_0_en; + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + return ret; +} + +/** + * @brief Enable FIFO batching data of second slave.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of batch_ext_sens_1_en in + * reg SLV1_CONFIG + * + */ +int32_t lsm6dsox_sh_batch_slave_1_set(lsm6dsox_ctx_t *ctx, uint8_t val) +{ + lsm6dsox_slv1_config_t reg; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV1_CONFIG, (uint8_t*)®, 1); + } + if (ret == 0) { + reg.batch_ext_sens_1_en = val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV1_CONFIG, (uint8_t*)®, 1); + } + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + + return ret; +} + +/** + * @brief Enable FIFO batching data of second slave.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of batch_ext_sens_1_en in + * reg SLV1_CONFIG + * + */ +int32_t lsm6dsox_sh_batch_slave_1_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_slv1_config_t reg; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV1_CONFIG, (uint8_t*)®, 1); + *val = reg.batch_ext_sens_1_en; + } + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + return ret; +} + +/** + * @brief Enable FIFO batching data of third slave.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of batch_ext_sens_2_en in + * reg SLV2_CONFIG + * + */ +int32_t lsm6dsox_sh_batch_slave_2_set(lsm6dsox_ctx_t *ctx, uint8_t val) +{ + lsm6dsox_slv2_config_t reg; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); + + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV2_CONFIG, (uint8_t*)®, 1); + } + if (ret == 0) { + reg.batch_ext_sens_2_en = val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV2_CONFIG, (uint8_t*)®, 1); + } + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + return ret; +} + +/** + * @brief Enable FIFO batching data of third slave.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of batch_ext_sens_2_en in + * reg SLV2_CONFIG + * + */ +int32_t lsm6dsox_sh_batch_slave_2_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_slv2_config_t reg; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV2_CONFIG, (uint8_t*)®, 1); + } + if (ret == 0) { + *val = reg.batch_ext_sens_2_en; + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + + return ret; +} + +/** + * @brief Enable FIFO batching data of fourth slave.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of batch_ext_sens_3_en + * in reg SLV3_CONFIG + * + */ +int32_t lsm6dsox_sh_batch_slave_3_set(lsm6dsox_ctx_t *ctx, uint8_t val) +{ + lsm6dsox_slv3_config_t reg; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV3_CONFIG, (uint8_t*)®, 1); + } + if (ret == 0) { + reg.batch_ext_sens_3_en = val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV3_CONFIG, (uint8_t*)®, 1); + } + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + + return ret; +} + +/** + * @brief Enable FIFO batching data of fourth slave.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of batch_ext_sens_3_en in + * reg SLV3_CONFIG + * + */ +int32_t lsm6dsox_sh_batch_slave_3_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_slv3_config_t reg; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV3_CONFIG, (uint8_t*)®, 1); + } + if (ret == 0) { + *val = reg.batch_ext_sens_3_en; + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DSOX_DEN_functionality + * @brief This section groups all the functions concerning + * DEN functionality. + * @{ + * +*/ + +/** + * @brief DEN functionality marking mode.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of den_mode in reg CTRL6_C + * + */ +int32_t lsm6dsox_den_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_den_mode_t val) +{ + lsm6dsox_ctrl6_c_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*)®, 1); + if (ret == 0) { + reg.den_mode = (uint8_t)val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*)®, 1); + } + + return ret; +} + +/** + * @brief DEN functionality marking mode.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of den_mode in reg CTRL6_C + * + */ +int32_t lsm6dsox_den_mode_get(lsm6dsox_ctx_t *ctx, lsm6dsox_den_mode_t *val) +{ + lsm6dsox_ctrl6_c_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t*)®, 1); + + switch (reg.den_mode) { + case LSM6DSOX_DEN_DISABLE: + *val = LSM6DSOX_DEN_DISABLE; + break; + case LSM6DSOX_LEVEL_FIFO: + *val = LSM6DSOX_LEVEL_FIFO; + break; + case LSM6DSOX_LEVEL_LETCHED: + *val = LSM6DSOX_LEVEL_LETCHED; + break; + case LSM6DSOX_LEVEL_TRIGGER: + *val = LSM6DSOX_LEVEL_TRIGGER; + break; + case LSM6DSOX_EDGE_TRIGGER: + *val = LSM6DSOX_EDGE_TRIGGER; + break; + default: + *val = LSM6DSOX_DEN_DISABLE; + break; + } + return ret; +} + +/** + * @brief DEN active level configuration.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of den_lh in reg CTRL9_XL + * + */ +int32_t lsm6dsox_den_polarity_set(lsm6dsox_ctx_t *ctx, lsm6dsox_den_lh_t val) +{ + lsm6dsox_ctrl9_xl_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)®, 1); + if (ret == 0) { + reg.den_lh = (uint8_t)val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)®, 1); + } + + return ret; +} + +/** + * @brief DEN active level configuration.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of den_lh in reg CTRL9_XL + * + */ +int32_t lsm6dsox_den_polarity_get(lsm6dsox_ctx_t *ctx, lsm6dsox_den_lh_t *val) +{ + lsm6dsox_ctrl9_xl_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)®, 1); + + switch (reg.den_lh) { + case LSM6DSOX_DEN_ACT_LOW: + *val = LSM6DSOX_DEN_ACT_LOW; + break; + case LSM6DSOX_DEN_ACT_HIGH: + *val = LSM6DSOX_DEN_ACT_HIGH; + break; + default: + *val = LSM6DSOX_DEN_ACT_LOW; + break; + } + return ret; +} + +/** + * @brief DEN enable.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of den_xl_g in reg CTRL9_XL + * + */ +int32_t lsm6dsox_den_enable_set(lsm6dsox_ctx_t *ctx, lsm6dsox_den_xl_g_t val) +{ + lsm6dsox_ctrl9_xl_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)®, 1); + if (ret == 0) { + reg.den_xl_g = (uint8_t)val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)®, 1); + } + + return ret; +} + +/** + * @brief DEN enable.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of den_xl_g in reg CTRL9_XL + * + */ +int32_t lsm6dsox_den_enable_get(lsm6dsox_ctx_t *ctx, lsm6dsox_den_xl_g_t *val) +{ + lsm6dsox_ctrl9_xl_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)®, 1); + + switch (reg.den_xl_g) { + case LSM6DSOX_STAMP_IN_GY_DATA: + *val = LSM6DSOX_STAMP_IN_GY_DATA; + break; + case LSM6DSOX_STAMP_IN_XL_DATA: + *val = LSM6DSOX_STAMP_IN_XL_DATA; + break; + case LSM6DSOX_STAMP_IN_GY_XL_DATA: + *val = LSM6DSOX_STAMP_IN_GY_XL_DATA; + break; + default: + *val = LSM6DSOX_STAMP_IN_GY_DATA; + break; + } + return ret; +} + +/** + * @brief DEN value stored in LSB of X-axis.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of den_z in reg CTRL9_XL + * + */ +int32_t lsm6dsox_den_mark_axis_x_set(lsm6dsox_ctx_t *ctx, uint8_t val) +{ + lsm6dsox_ctrl9_xl_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)®, 1); + if (ret == 0) { + reg.den_z = val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)®, 1); + } + + return ret; +} + +/** + * @brief DEN value stored in LSB of X-axis.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of den_z in reg CTRL9_XL + * + */ +int32_t lsm6dsox_den_mark_axis_x_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_ctrl9_xl_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)®, 1); + *val = reg.den_z; + + return ret; +} + +/** + * @brief DEN value stored in LSB of Y-axis.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of den_y in reg CTRL9_XL + * + */ +int32_t lsm6dsox_den_mark_axis_y_set(lsm6dsox_ctx_t *ctx, uint8_t val) +{ + lsm6dsox_ctrl9_xl_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)®, 1); + if (ret == 0) { + reg.den_y = val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)®, 1); + } + + return ret; +} + +/** + * @brief DEN value stored in LSB of Y-axis.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of den_y in reg CTRL9_XL + * + */ +int32_t lsm6dsox_den_mark_axis_y_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_ctrl9_xl_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)®, 1); + *val = reg.den_y; + + return ret; +} + +/** + * @brief DEN value stored in LSB of Z-axis.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of den_x in reg CTRL9_XL + * + */ +int32_t lsm6dsox_den_mark_axis_z_set(lsm6dsox_ctx_t *ctx, uint8_t val) +{ + lsm6dsox_ctrl9_xl_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)®, 1); + if (ret == 0) { + reg.den_x = val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)®, 1); + } + + return ret; +} + +/** + * @brief DEN value stored in LSB of Z-axis.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of den_x in reg CTRL9_XL + * + */ +int32_t lsm6dsox_den_mark_axis_z_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_ctrl9_xl_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t*)®, 1); + *val = reg.den_x; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DSOX_Pedometer + * @brief This section groups all the functions that manage pedometer. + * @{ + * +*/ + +/** + * @brief Enable pedometer algorithm.[set] + * + * @param ctx read / write interface definitions + * @param val turn on and configure pedometer + * + */ +int32_t lsm6dsox_pedo_sens_set(lsm6dsox_ctx_t *ctx, lsm6dsox_pedo_md_t val) +{ + lsm6dsox_emb_func_en_a_t emb_func_en_a; + lsm6dsox_emb_func_en_b_t emb_func_en_b; + lsm6dsox_pedo_cmd_reg_t pedo_cmd_reg; + int32_t ret; + + ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_PEDO_CMD_REG, + (uint8_t*)&pedo_cmd_reg); + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); + } + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_A, + (uint8_t*)&emb_func_en_a, 1); + } + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B, + (uint8_t*)&emb_func_en_b, 1); + + emb_func_en_a.pedo_en = (uint8_t)val & 0x01U; + emb_func_en_b.mlc_en = ((uint8_t)val & 0x02U)>>1; + pedo_cmd_reg.fp_rejection_en = ((uint8_t)val & 0x10U)>>4; + pedo_cmd_reg.ad_det_en = ((uint8_t)val & 0x20U)>>5; + } + if (ret == 0) { + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_EN_A, + (uint8_t*)&emb_func_en_a, 1); + } + if (ret == 0) { + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B, + (uint8_t*)&emb_func_en_b, 1); + } + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + if (ret == 0) { + ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_PEDO_CMD_REG, + (uint8_t*)&pedo_cmd_reg); + } + return ret; +} + +/** + * @brief Enable pedometer algorithm.[get] + * + * @param ctx read / write interface definitions + * @param val turn on and configure pedometer + * + */ +int32_t lsm6dsox_pedo_sens_get(lsm6dsox_ctx_t *ctx, lsm6dsox_pedo_md_t *val) +{ + lsm6dsox_emb_func_en_a_t emb_func_en_a; + lsm6dsox_emb_func_en_b_t emb_func_en_b; + lsm6dsox_pedo_cmd_reg_t pedo_cmd_reg; + int32_t ret; + + ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_PEDO_CMD_REG, + (uint8_t*)&pedo_cmd_reg); + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); + } + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_A, + (uint8_t*)&emb_func_en_a, 1); + } + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B, + (uint8_t*)&emb_func_en_b, 1); + } + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + switch ( (pedo_cmd_reg.ad_det_en <<5) | (pedo_cmd_reg.fp_rejection_en << 4) | + (emb_func_en_b.mlc_en << 1) | emb_func_en_a.pedo_en) { + case LSM6DSOX_PEDO_DISABLE: + *val = LSM6DSOX_PEDO_DISABLE; + break; + case LSM6DSOX_PEDO_BASE_MODE: + *val = LSM6DSOX_PEDO_BASE_MODE; + break; + case LSM6DSOX_PEDO_ADV_MODE: + *val = LSM6DSOX_PEDO_ADV_MODE; + break; + case LSM6DSOX_FALSE_STEP_REJ: + *val = LSM6DSOX_FALSE_STEP_REJ; + break; + case LSM6DSOX_FALSE_STEP_REJ_ADV_MODE: + *val = LSM6DSOX_FALSE_STEP_REJ_ADV_MODE; + break; + default: + *val = LSM6DSOX_PEDO_DISABLE; + break; + } + return ret; +} + +/** + * @brief Interrupt status bit for step detection.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of is_step_det in reg EMB_FUNC_STATUS + * + */ +int32_t lsm6dsox_pedo_step_detect_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_emb_func_status_t reg; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_STATUS, (uint8_t*)®, 1); + } + if (ret == 0) { + *val = reg.is_step_det; + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + + return ret; +} + +/** + * @brief Pedometer debounce configuration register (r/w).[set] + * + * @param ctx read / write interface definitions + * @param buff buffer that contains data to write + * + */ +int32_t lsm6dsox_pedo_debounce_steps_set(lsm6dsox_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_PEDO_DEB_STEPS_CONF, buff); + return ret; +} + +/** + * @brief Pedometer debounce configuration register (r/w).[get] + * + * @param ctx read / write interface definitions + * @param buff buffer that stores data read + * + */ +int32_t lsm6dsox_pedo_debounce_steps_get(lsm6dsox_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_PEDO_DEB_STEPS_CONF, buff); + return ret; +} + +/** + * @brief Time period register for step detection on delta time (r/w).[set] + * + * @param ctx read / write interface definitions + * @param buff buffer that contains data to write + * + */ +int32_t lsm6dsox_pedo_steps_period_set(lsm6dsox_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + uint8_t index; + + index = 0x00U; + ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_PEDO_SC_DELTAT_L, &buff[index]); + if (ret == 0) { + index++; + ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_PEDO_SC_DELTAT_H, + &buff[index]); + } + return ret; +} + +/** + * @brief Time period register for step detection on delta time (r/w).[get] + * + * @param ctx read / write interface definitions + * @param buff buffer that stores data read + * + */ +int32_t lsm6dsox_pedo_steps_period_get(lsm6dsox_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + uint8_t index; + + index = 0x00U; + ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_PEDO_SC_DELTAT_L, &buff[index]); + if (ret == 0) { + index++; + ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_PEDO_SC_DELTAT_H, + &buff[index]); + } + return ret; +} + +/** + * @brief Set when user wants to generate interrupt on count overflow + * event/every step.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of carry_count_en in reg PEDO_CMD_REG + * + */ +int32_t lsm6dsox_pedo_int_mode_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_carry_count_en_t val) +{ + lsm6dsox_pedo_cmd_reg_t reg; + int32_t ret; + + ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_PEDO_CMD_REG, (uint8_t*)®); + if (ret == 0) { + reg.carry_count_en = (uint8_t)val; + ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_PEDO_CMD_REG, + (uint8_t*)®); + } + return ret; +} + +/** + * @brief Set when user wants to generate interrupt on count overflow + * event/every step.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of carry_count_en in reg PEDO_CMD_REG + * + */ +int32_t lsm6dsox_pedo_int_mode_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_carry_count_en_t *val) +{ + lsm6dsox_pedo_cmd_reg_t reg; + int32_t ret; + + ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_PEDO_CMD_REG, (uint8_t*)®); + switch (reg.carry_count_en) { + case LSM6DSOX_EVERY_STEP: + *val = LSM6DSOX_EVERY_STEP; + break; + case LSM6DSOX_COUNT_OVERFLOW: + *val = LSM6DSOX_COUNT_OVERFLOW; + break; + default: + *val = LSM6DSOX_EVERY_STEP; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DSOX_significant_motion + * @brief This section groups all the functions that manage the + * significant motion detection. + * @{ + * + */ + +/** + * @brief Enable significant motion detection function.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of sign_motion_en in reg EMB_FUNC_EN_A + * + */ +int32_t lsm6dsox_motion_sens_set(lsm6dsox_ctx_t *ctx, uint8_t val) +{ + lsm6dsox_emb_func_en_a_t reg; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_A, (uint8_t*)®, 1); + } + if (ret == 0) { + reg.sign_motion_en = val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_EN_A, (uint8_t*)®, 1); + } + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + return ret; +} + +/** + * @brief Enable significant motion detection function.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of sign_motion_en in reg EMB_FUNC_EN_A + * + */ +int32_t lsm6dsox_motion_sens_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_emb_func_en_a_t reg; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_A, (uint8_t*)®, 1); + } + if (ret == 0) { + *val = reg.sign_motion_en; + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + return ret; +} + +/** + * @brief Interrupt status bit for significant motion detection.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of is_sigmot in reg EMB_FUNC_STATUS + * + */ +int32_t lsm6dsox_motion_flag_data_ready_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_emb_func_status_t reg; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_STATUS, (uint8_t*)®, 1); + } + if (ret == 0) { + *val = reg.is_sigmot; + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DSOX_tilt_detection + * @brief This section groups all the functions that manage the tilt + * event detection. + * @{ + * + */ + +/** + * @brief Enable tilt calculation.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of tilt_en in reg EMB_FUNC_EN_A + * + */ +int32_t lsm6dsox_tilt_sens_set(lsm6dsox_ctx_t *ctx, uint8_t val) +{ + lsm6dsox_emb_func_en_a_t reg; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_A, (uint8_t*)®, 1); + } + if (ret == 0) { + reg.tilt_en = val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_EN_A, (uint8_t*)®, 1); + } + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + return ret; +} + +/** + * @brief Enable tilt calculation.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of tilt_en in reg EMB_FUNC_EN_A + * + */ +int32_t lsm6dsox_tilt_sens_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_emb_func_en_a_t reg; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_A, (uint8_t*)®, 1); + } + if (ret == 0) { + *val = reg.tilt_en; + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + + return ret; +} + +/** + * @brief Interrupt status bit for tilt detection.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of is_tilt in reg EMB_FUNC_STATUS + * + */ +int32_t lsm6dsox_tilt_flag_data_ready_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_emb_func_status_t reg; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_STATUS, (uint8_t*)®, 1); + } + if (ret == 0) { + *val = reg.is_tilt; + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DSOX_ magnetometer_sensor + * @brief This section groups all the functions that manage additional + * magnetometer sensor. + * @{ + * + */ + +/** + * @brief External magnetometer sensitivity value register for + * Sensor hub.[set] + * + * @param ctx read / write interface definitions + * @param buff buffer that contains data to write + * + */ +int32_t lsm6dsox_sh_mag_sensitivity_set(lsm6dsox_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + uint8_t index; + + index = 0x00U; + ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SENSITIVITY_L, + &buff[index]); + if (ret == 0) { + index++; + ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SENSITIVITY_H, + &buff[index]); + } + + return ret; +} + +/** + * @brief External magnetometer sensitivity value register for + * Sensor hub.[get] + * + * @param ctx read / write interface definitions + * @param buff buffer that stores data read + * + */ +int32_t lsm6dsox_sh_mag_sensitivity_get(lsm6dsox_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + uint8_t index; + + index = 0x00U; + ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SENSITIVITY_L, + &buff[index]); + if (ret == 0) { + index++; + ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SENSITIVITY_H, + &buff[index]); + } + + return ret; +} + +/** + * @brief External magnetometer sensitivity value register for + * Machine Learning Core.[set] + * + * @param ctx read / write interface definitions + * @param buff buffer that contains data to write + * + */ +int32_t lsm6dsox_mlc_mag_sensitivity_set(lsm6dsox_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + uint8_t index; + + index = 0x00U; + ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MLC_MAG_SENSITIVITY_L, + &buff[index]); + if (ret == 0) { + index++; + ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MLC_MAG_SENSITIVITY_H, + &buff[index]); + } + return ret; +} + +/** + * @brief External magnetometer sensitivity value register for + * Machine Learning Core.[get] + * + * @param ctx read / write interface definitions + * @param buff buffer that stores data read + * + */ +int32_t lsm6dsox_mlc_mag_sensitivity_get(lsm6dsox_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + uint8_t index; + + index = 0x00U; + ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MLC_MAG_SENSITIVITY_L, + &buff[index]); + if (ret == 0) { + index++; + ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MLC_MAG_SENSITIVITY_H, + &buff[index]); + } + return ret; +} + + +/** + * @brief Offset for hard-iron compensation register (r/w).[set] + * + * @param ctx read / write interface definitions + * @param buff buffer that contains data to write + * + */ +int32_t lsm6dsox_mag_offset_set(lsm6dsox_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + uint8_t index; + + index = 0x00U; + ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_OFFX_L, &buff[index]); + if (ret == 0) { + index++; + ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_OFFX_H, &buff[index]); + } + if (ret == 0) { + index++; + ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_OFFY_L, &buff[index]); + } + if (ret == 0) { + index++; + ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_OFFY_H, &buff[index]); + } + if (ret == 0) { + index++; + + ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_OFFZ_L, &buff[index]); + } + if (ret == 0) { + index++; + ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_OFFZ_H, &buff[index]); + } + + return ret; +} + +/** + * @brief Offset for hard-iron compensation register (r/w).[get] + * + * @param ctx read / write interface definitions + * @param buff buffer that stores data read + * + */ +int32_t lsm6dsox_mag_offset_get(lsm6dsox_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + uint8_t index; + + index = 0x00U; + ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_OFFX_L, &buff[index]); + if (ret == 0) { + index++; + ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_OFFX_H, &buff[index]); + } + if (ret == 0) { + index++; + + ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_OFFY_L, &buff[index]); + } + if (ret == 0) { + index++; + ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_OFFY_H, &buff[index]); + } + if (ret == 0) { + index++; + + ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_OFFZ_L, &buff[index]); + } + if (ret == 0) { + index++; + ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_OFFZ_H, &buff[index]); + } + return ret; +} + +/** + * @brief Soft-iron (3x3 symmetric) matrix correction + * register (r/w). The value is expressed as + * half-precision floating-point format: + * SEEEEEFFFFFFFFFF + * S: 1 sign bit; + * E: 5 exponent bits; + * F: 10 fraction bits).[set] + * + * @param ctx read / write interface definitions + * @param buff buffer that contains data to write + * + */ +int32_t lsm6dsox_mag_soft_iron_set(lsm6dsox_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + uint8_t index; + + index = 0x00U; + ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_XX_L, &buff[index]); + if (ret == 0) { + index++; + ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_XX_H, &buff[index]); + } + if (ret == 0) { + index++; + + ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_XY_L, &buff[index]); + } + if (ret == 0) { + index++; + ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_XY_H, &buff[index]); + } + if (ret == 0) { + index++; + + ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_XZ_L, &buff[index]); + } + if (ret == 0) { + index++; + ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_XZ_H, &buff[index]); + } + if (ret == 0) { + index++; + + ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_YY_L, &buff[index]); + } + if (ret == 0) { + index++; + ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_YY_H, &buff[index]); + } + if (ret == 0) { + index++; + + ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_YZ_L, &buff[index]); + } + if (ret == 0) { + index++; + ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_YZ_H, &buff[index]); + } + if (ret == 0) { + index++; + + ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_ZZ_L, &buff[index]); + } + if (ret == 0) { + index++; + ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_ZZ_H, &buff[index]); + } + + return ret; +} + +/** + * @brief Soft-iron (3x3 symmetric) matrix + * correction register (r/w). + * The value is expressed as half-precision + * floating-point format: + * SEEEEEFFFFFFFFFF + * S: 1 sign bit; + * E: 5 exponent bits; + * F: 10 fraction bits.[get] + * + * @param ctx read / write interface definitions + * @param buff buffer that stores data read + * + */ +int32_t lsm6dsox_mag_soft_iron_get(lsm6dsox_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + uint8_t index; + + index = 0x00U; + ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_XX_L, &buff[index]); + if (ret == 0) { + index++; + ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_XX_H, &buff[index]); + } + if (ret == 0) { + index++; + + ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_XY_L, &buff[index]); + } + if (ret == 0) { + index++; + ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_XY_H, &buff[index]); + } + if (ret == 0) { + index++; + + ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_XZ_L, &buff[index]); + } + if (ret == 0) { + index++; + ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_XZ_H, &buff[index]); + } + if (ret == 0) { + index++; + + ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_YY_L, &buff[index]); + } + if (ret == 0) { + index++; + ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_YY_H, &buff[index]); + } + if (ret == 0) { + index++; + + ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_YZ_L, &buff[index]); + } + if (ret == 0) { + index++; + ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_YZ_H, &buff[index]); + } + if (ret == 0) { + index++; + + ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_ZZ_L, &buff[index]); + } + if (ret == 0) { + index++; + ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_ZZ_H, &buff[index]); + } + + return ret; +} + +/** + * @brief Magnetometer Z-axis coordinates + * rotation (to be aligned to + * accelerometer/gyroscope axes + * orientation).[set] + * + * @param ctx read / write interface definitions + * @param val change the values of mag_z_axis in reg MAG_CFG_A + * + */ +int32_t lsm6dsox_mag_z_orient_set(lsm6dsox_ctx_t *ctx, lsm6dsox_mag_z_axis_t val) +{ + lsm6dsox_mag_cfg_a_t reg; + int32_t ret; + + ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_CFG_A, (uint8_t*)®); + if (ret == 0) { + reg.mag_z_axis = (uint8_t) val; + ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_CFG_A, (uint8_t*)®); + } + + return ret; +} + +/** + * @brief Magnetometer Z-axis coordinates + * rotation (to be aligned to + * accelerometer/gyroscope axes + * orientation).[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of mag_z_axis in reg MAG_CFG_A + * + */ +int32_t lsm6dsox_mag_z_orient_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_mag_z_axis_t *val) +{ + lsm6dsox_mag_cfg_a_t reg; + int32_t ret; + ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_CFG_A, (uint8_t*)®); + switch (reg.mag_z_axis) { + case LSM6DSOX_Z_EQ_Y: + *val = LSM6DSOX_Z_EQ_Y; + break; + case LSM6DSOX_Z_EQ_MIN_Y: + *val = LSM6DSOX_Z_EQ_MIN_Y; + break; + case LSM6DSOX_Z_EQ_X: + *val = LSM6DSOX_Z_EQ_X; + break; + case LSM6DSOX_Z_EQ_MIN_X: + *val = LSM6DSOX_Z_EQ_MIN_X; + break; + case LSM6DSOX_Z_EQ_MIN_Z: + *val = LSM6DSOX_Z_EQ_MIN_Z; + break; + case LSM6DSOX_Z_EQ_Z: + *val = LSM6DSOX_Z_EQ_Z; + break; + default: + *val = LSM6DSOX_Z_EQ_Y; + break; + } + return ret; +} + +/** + * @brief Magnetometer Y-axis coordinates + * rotation (to be aligned to + * accelerometer/gyroscope axes + * orientation).[set] + * + * @param ctx read / write interface definitions + * @param val change the values of mag_y_axis in reg MAG_CFG_A + * + */ +int32_t lsm6dsox_mag_y_orient_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_mag_y_axis_t val) +{ + lsm6dsox_mag_cfg_a_t reg; + int32_t ret; + + ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_CFG_A, (uint8_t*)®); + if (ret == 0) { + reg.mag_y_axis = (uint8_t)val; + ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_CFG_A,(uint8_t*) ®); + } + return ret; +} + +/** + * @brief Magnetometer Y-axis coordinates + * rotation (to be aligned to + * accelerometer/gyroscope axes + * orientation).[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of mag_y_axis in reg MAG_CFG_A + * + */ +int32_t lsm6dsox_mag_y_orient_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_mag_y_axis_t *val) +{ + lsm6dsox_mag_cfg_a_t reg; + int32_t ret; + + ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_CFG_A, (uint8_t*)®); + switch (reg.mag_y_axis) { + case LSM6DSOX_Y_EQ_Y: + *val = LSM6DSOX_Y_EQ_Y; + break; + case LSM6DSOX_Y_EQ_MIN_Y: + *val = LSM6DSOX_Y_EQ_MIN_Y; + break; + case LSM6DSOX_Y_EQ_X: + *val = LSM6DSOX_Y_EQ_X; + break; + case LSM6DSOX_Y_EQ_MIN_X: + *val = LSM6DSOX_Y_EQ_MIN_X; + break; + case LSM6DSOX_Y_EQ_MIN_Z: + *val = LSM6DSOX_Y_EQ_MIN_Z; + break; + case LSM6DSOX_Y_EQ_Z: + *val = LSM6DSOX_Y_EQ_Z; + break; + default: + *val = LSM6DSOX_Y_EQ_Y; + break; + } + return ret; +} + +/** + * @brief Magnetometer X-axis coordinates + * rotation (to be aligned to + * accelerometer/gyroscope axes + * orientation).[set] + * + * @param ctx read / write interface definitions + * @param val change the values of mag_x_axis in reg MAG_CFG_B + * + */ +int32_t lsm6dsox_mag_x_orient_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_mag_x_axis_t val) +{ + lsm6dsox_mag_cfg_b_t reg; + int32_t ret; + + ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_CFG_B, (uint8_t*)®); + if (ret == 0) { + reg.mag_x_axis = (uint8_t)val; + ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_CFG_B, (uint8_t*)®); + } + return ret; +} + +/** + * @brief Magnetometer X-axis coordinates + * rotation (to be aligned to + * accelerometer/gyroscope axes + * orientation).[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of mag_x_axis in reg MAG_CFG_B + * + */ +int32_t lsm6dsox_mag_x_orient_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_mag_x_axis_t *val) +{ + lsm6dsox_mag_cfg_b_t reg; + int32_t ret; + + ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_CFG_B, (uint8_t*)®); + switch (reg.mag_x_axis) { + case LSM6DSOX_X_EQ_Y: + *val = LSM6DSOX_X_EQ_Y; + break; + case LSM6DSOX_X_EQ_MIN_Y: + *val = LSM6DSOX_X_EQ_MIN_Y; + break; + case LSM6DSOX_X_EQ_X: + *val = LSM6DSOX_X_EQ_X; + break; + case LSM6DSOX_X_EQ_MIN_X: + *val = LSM6DSOX_X_EQ_MIN_X; + break; + case LSM6DSOX_X_EQ_MIN_Z: + *val = LSM6DSOX_X_EQ_MIN_Z; + break; + case LSM6DSOX_X_EQ_Z: + *val = LSM6DSOX_X_EQ_Z; + break; + default: + *val = LSM6DSOX_X_EQ_Y; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DSOX_significant_motion + * @brief This section groups all the functions that manage the + * state_machine. + * @{ + * + */ + +/** + * @brief Interrupt status bit for FSM long counter + * timeout interrupt event.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of is_fsm_lc in reg EMB_FUNC_STATUS + * + */ +int32_t lsm6dsox_long_cnt_flag_data_ready_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_emb_func_status_t reg; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_STATUS, (uint8_t*)®, 1); + } + if (ret == 0) { + *val = reg.is_fsm_lc; + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + return ret; +} + +/** + * @brief Finite State Machine global enable.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of fsm_en in reg EMB_FUNC_EN_B + * + */ +int32_t lsm6dsox_emb_fsm_en_set(lsm6dsox_ctx_t *ctx, uint8_t val) +{ + int32_t ret; + lsm6dsox_emb_func_en_b_t reg; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B, (uint8_t*)®, 1); + } + if (ret == 0) { + reg.fsm_en = val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B, (uint8_t*)®, 1); + } + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + return ret; +} + +/** + * @brief Finite State Machine global enable.[get] + * + * @param ctx read / write interface definitions + * @param uint8_t *: return the values of fsm_en in reg EMB_FUNC_EN_B + * + */ +int32_t lsm6dsox_emb_fsm_en_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + int32_t ret; + lsm6dsox_emb_func_en_b_t reg; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B, (uint8_t*)®, 1); + } + if (ret == 0) { + *val = reg.fsm_en; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B, (uint8_t*)®, 1); + } + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + + return ret; +} + +/** + * @brief Finite State Machine enable.[set] + * + * @param ctx read / write interface definitions + * @param val union of registers from FSM_ENABLE_A to FSM_ENABLE_B + * + */ +int32_t lsm6dsox_fsm_enable_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_emb_fsm_enable_t *val) +{ + int32_t ret; + lsm6dsox_emb_func_en_b_t reg; + + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); + if (ret == 0) { + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_ENABLE_A, + (uint8_t*)&val->fsm_enable_a, 1); + } + if (ret == 0) { + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_ENABLE_B, + (uint8_t*)&val->fsm_enable_b, 1); + } + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B, + (uint8_t*)®, 1); + } + if (ret == 0) { + if ( (val->fsm_enable_a.fsm1_en | + val->fsm_enable_a.fsm2_en | + val->fsm_enable_a.fsm3_en | + val->fsm_enable_a.fsm4_en | + val->fsm_enable_a.fsm5_en | + val->fsm_enable_a.fsm6_en | + val->fsm_enable_a.fsm7_en | + val->fsm_enable_a.fsm8_en | + val->fsm_enable_b.fsm9_en | + val->fsm_enable_b.fsm10_en | + val->fsm_enable_b.fsm11_en | + val->fsm_enable_b.fsm12_en | + val->fsm_enable_b.fsm13_en | + val->fsm_enable_b.fsm14_en | + val->fsm_enable_b.fsm15_en | + val->fsm_enable_b.fsm16_en ) + != PROPERTY_DISABLE){ + reg.fsm_en = PROPERTY_ENABLE; + } + else{ + reg.fsm_en = PROPERTY_DISABLE; + } + + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B, (uint8_t*)®, 1); + } + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + + return ret; +} + +/** + * @brief Finite State Machine enable.[get] + * + * @param ctx read / write interface definitions + * @param val union of registers from FSM_ENABLE_A to FSM_ENABLE_B + * + */ +int32_t lsm6dsox_fsm_enable_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_emb_fsm_enable_t *val) +{ + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_ENABLE_A, (uint8_t*) val, 2); + } + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + return ret; +} + +/** + * @brief FSM long counter status register. Long counter value is an + * unsigned integer value (16-bit format).[set] + * + * @param ctx read / write interface definitions + * @param buff buffer that contains data to write + * + */ +int32_t lsm6dsox_long_cnt_set(lsm6dsox_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); + if (ret == 0) { + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_LONG_COUNTER_L, buff, 2); + } + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + + return ret; +} + +/** + * @brief FSM long counter status register. Long counter value is an + * unsigned integer value (16-bit format).[get] + * + * @param ctx read / write interface definitions + * @param buff buffer that stores data read + * + */ +int32_t lsm6dsox_long_cnt_get(lsm6dsox_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_LONG_COUNTER_L, buff, 2); + } + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + + return ret; +} + +/** + * @brief Clear FSM long counter value.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of fsm_lc_clr in + * reg FSM_LONG_COUNTER_CLEAR + * + */ +int32_t lsm6dsox_long_clr_set(lsm6dsox_ctx_t *ctx, lsm6dsox_fsm_lc_clr_t val) +{ + lsm6dsox_fsm_long_counter_clear_t reg; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_LONG_COUNTER_CLEAR, + (uint8_t*)®, 1); + } + if (ret == 0) { + reg. fsm_lc_clr = (uint8_t)val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_LONG_COUNTER_CLEAR, + (uint8_t*)®, 1); + } + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + return ret; +} + +/** + * @brief Clear FSM long counter value.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of fsm_lc_clr in + * reg FSM_LONG_COUNTER_CLEAR + * + */ +int32_t lsm6dsox_long_clr_get(lsm6dsox_ctx_t *ctx, lsm6dsox_fsm_lc_clr_t *val) +{ + lsm6dsox_fsm_long_counter_clear_t reg; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_LONG_COUNTER_CLEAR, + (uint8_t*)®, 1); + } + if (ret == 0) { + switch (reg.fsm_lc_clr) { + case LSM6DSOX_LC_NORMAL: + *val = LSM6DSOX_LC_NORMAL; + break; + case LSM6DSOX_LC_CLEAR: + *val = LSM6DSOX_LC_CLEAR; + break; + case LSM6DSOX_LC_CLEAR_DONE: + *val = LSM6DSOX_LC_CLEAR_DONE; + break; + default: + *val = LSM6DSOX_LC_NORMAL; + break; + } + } + + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + + return ret; +} + +/** + * @brief FSM output registers[get] + * + * @param ctx read / write interface definitions + * @param val struct of registers from FSM_OUTS1 to FSM_OUTS16 + * + */ +int32_t lsm6dsox_fsm_out_get(lsm6dsox_ctx_t *ctx, lsm6dsox_fsm_out_t *val) +{ + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_OUTS1, (uint8_t*)val, 16); + } + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + + return ret; +} + +/** + * @brief Finite State Machine ODR configuration.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B + * + */ +int32_t lsm6dsox_fsm_data_rate_set(lsm6dsox_ctx_t *ctx, lsm6dsox_fsm_odr_t val) +{ + lsm6dsox_emb_func_odr_cfg_b_t reg; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_ODR_CFG_B, + (uint8_t*)®, 1); + } + if (ret == 0) { + reg.not_used_01 = 3; /* set default values */ + reg.not_used_02 = 2; /* set default values */ + reg.fsm_odr = (uint8_t)val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_ODR_CFG_B, + (uint8_t*)®, 1); + } + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + return ret; +} + +/** + * @brief Finite State Machine ODR configuration.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B + * + */ +int32_t lsm6dsox_fsm_data_rate_get(lsm6dsox_ctx_t *ctx, lsm6dsox_fsm_odr_t *val) +{ + lsm6dsox_emb_func_odr_cfg_b_t reg; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_ODR_CFG_B, + (uint8_t*)®, 1); + } + if (ret == 0) { + switch (reg.fsm_odr) { + case LSM6DSOX_ODR_FSM_12Hz5: + *val = LSM6DSOX_ODR_FSM_12Hz5; + break; + case LSM6DSOX_ODR_FSM_26Hz: + *val = LSM6DSOX_ODR_FSM_26Hz; + break; + case LSM6DSOX_ODR_FSM_52Hz: + *val = LSM6DSOX_ODR_FSM_52Hz; + break; + case LSM6DSOX_ODR_FSM_104Hz: + *val = LSM6DSOX_ODR_FSM_104Hz; + break; + default: + *val = LSM6DSOX_ODR_FSM_12Hz5; + break; + } + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + + return ret; +} + +/** + * @brief FSM initialization request.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of fsm_init in reg FSM_INIT + * + */ +int32_t lsm6dsox_fsm_init_set(lsm6dsox_ctx_t *ctx, uint8_t val) +{ + lsm6dsox_emb_func_init_b_t reg; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B, (uint8_t*)®, 1); + } + if (ret == 0) { + reg.fsm_init = val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B, (uint8_t*)®, 1); + } + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + + return ret; +} + +/** + * @brief FSM initialization request.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of fsm_init in reg FSM_INIT + * + */ +int32_t lsm6dsox_fsm_init_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_emb_func_init_b_t reg; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B, (uint8_t*)®, 1); + } + if (ret == 0) { + *val = reg.fsm_init; + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + return ret; +} + +/** + * @brief FSM long counter timeout register (r/w). The long counter + * timeout value is an unsigned integer value (16-bit format). + * When the long counter value reached this value, + * the FSM generates an interrupt.[set] + * + * @param ctx read / write interface definitions + * @param val the value of long counter + * + */ +int32_t lsm6dsox_long_cnt_int_value_set(lsm6dsox_ctx_t *ctx, uint16_t val) +{ + int32_t ret; + uint8_t add_l; + uint8_t add_h; + + add_h = (uint8_t)( ( val & 0xFF00U ) >> 8 ); + add_l = (uint8_t)( val & 0x00FFU ); + + ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_FSM_LC_TIMEOUT_L, &add_l); + if (ret == 0) { + ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_FSM_LC_TIMEOUT_H, &add_h); + } + + return ret; +} + +/** + * @brief FSM long counter timeout register (r/w). The long counter + * timeout value is an unsigned integer value (16-bit format). + * When the long counter value reached this value, + * the FSM generates an interrupt.[get] + * + * @param ctx read / write interface definitions + * @param val buffer that stores the value of long counter + * + */ +int32_t lsm6dsox_long_cnt_int_value_get(lsm6dsox_ctx_t *ctx, uint16_t *val) +{ + int32_t ret; + uint8_t add_l; + uint8_t add_h; + + ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_FSM_LC_TIMEOUT_L, &add_l); + if (ret == 0) { + ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_FSM_LC_TIMEOUT_H, &add_h); + *val = add_h; + *val = *val << 8; + *val += add_l; + } + + return ret; +} + +/** + * @brief FSM number of programs register.[set] + * + * @param ctx read / write interface definitions + * @param val value to write + * + */ +int32_t lsm6dsox_fsm_number_of_programs_set(lsm6dsox_ctx_t *ctx, uint8_t val) +{ + int32_t ret; + + ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_FSM_PROGRAMS, &val); + + return ret; +} + +/** + * @brief FSM number of programs register.[get] + * + * @param ctx read / write interface definitions + * @param val buffer that stores data read. + * + */ +int32_t lsm6dsox_fsm_number_of_programs_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + int32_t ret; + + ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_FSM_PROGRAMS, val); + + return ret; +} + +/** + * @brief FSM start address register (r/w). + * First available address is 0x033C.[set] + * + * @param ctx read / write interface definitions + * @param val the value of start address + * + */ +int32_t lsm6dsox_fsm_start_address_set(lsm6dsox_ctx_t *ctx, uint16_t val) +{ + int32_t ret; + uint8_t add_l; + uint8_t add_h; + + add_h = (uint8_t)( ( val & 0xFF00U ) >> 8 ); + add_l = (uint8_t)( val & 0x00FFU ); + + ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_FSM_START_ADD_L, &add_l); + if (ret == 0) { + ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_FSM_START_ADD_H, &add_h); + } + return ret; +} + +/** + * @brief FSM start address register (r/w). + * First available address is 0x033C.[get] + * + * @param ctx read / write interface definitions + * @param val buffer the value of start address. + * + */ +int32_t lsm6dsox_fsm_start_address_get(lsm6dsox_ctx_t *ctx, uint16_t *val) +{ + int32_t ret; + uint8_t add_l; + uint8_t add_h; + + ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_FSM_START_ADD_L, &add_l); + if (ret == 0) { + ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_FSM_START_ADD_H, &add_h); + *val = add_h; + *val = *val << 8; + *val += add_l; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @addtogroup Machine Learning Core + * @brief This section group all the functions concerning the + * usage of Machine Learning Core + * @{ + * + */ + +/** + * @brief Enable Machine Learning Core.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of mlc_en in + * reg EMB_FUNC_EN_B and mlc_init + * in EMB_FUNC_INIT_B + * + */ +int32_t lsm6dsox_mlc_set(lsm6dsox_ctx_t *ctx, uint8_t val) +{ + lsm6dsox_emb_func_en_b_t reg; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B, (uint8_t*)®, 1); + } + if (ret == 0) { + reg.mlc_en = val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B, (uint8_t*)®, 1); + } + if ((val != PROPERTY_DISABLE) && (ret == 0)){ + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B, + (uint8_t*)®, 1); + if (ret == 0) { + reg.mlc_en = val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B, + (uint8_t*)®, 1); + } + } + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + return ret; +} + +/** + * @brief Enable Machine Learning Core.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of mlc_en in + * reg EMB_FUNC_EN_B + * + */ +int32_t lsm6dsox_mlc_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_emb_func_en_b_t reg; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B, (uint8_t*)®, 1); + } + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + *val = reg.mlc_en; + } + return ret; +} + +/** + * @brief Machine Learning Core status register[get] + * + * @param ctx read / write interface definitions + * @param val register MLC_STATUS_MAINPAGE + * + */ +int32_t lsm6dsox_mlc_status_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_mlc_status_mainpage_t *val) +{ + return lsm6dsox_read_reg(ctx, LSM6DSOX_MLC_STATUS_MAINPAGE, + (uint8_t*) val, 1); +} + +/** + * @brief Machine Learning Core data rate selection.[set] + * + * @param ctx read / write interface definitions + * @param val get the values of mlc_odr in + * reg EMB_FUNC_ODR_CFG_C + * + */ +int32_t lsm6dsox_mlc_data_rate_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_mlc_odr_t val) +{ + lsm6dsox_emb_func_odr_cfg_c_t reg; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_ODR_CFG_C, + (uint8_t*)®, 1); + } + if (ret == 0) { + reg.mlc_odr = (uint8_t)val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_ODR_CFG_C, (uint8_t*)®, 1); + } + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + + return ret; +} + +/** + * @brief Machine Learning Core data rate selection.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of mlc_odr in + * reg EMB_FUNC_ODR_CFG_C + * + */ +int32_t lsm6dsox_mlc_data_rate_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_mlc_odr_t *val) +{ + lsm6dsox_emb_func_odr_cfg_c_t reg; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_ODR_CFG_C, + (uint8_t*)®, 1); + } + if (ret == 0) { + switch (reg.mlc_odr) { + case LSM6DSOX_ODR_PRGS_12Hz5: + *val = LSM6DSOX_ODR_PRGS_12Hz5; + break; + case LSM6DSOX_ODR_PRGS_26Hz: + *val = LSM6DSOX_ODR_PRGS_26Hz; + break; + case LSM6DSOX_ODR_PRGS_52Hz: + *val = LSM6DSOX_ODR_PRGS_52Hz; + break; + case LSM6DSOX_ODR_PRGS_104Hz: + *val = LSM6DSOX_ODR_PRGS_104Hz; + break; + default: + *val = LSM6DSOX_ODR_PRGS_12Hz5; + break; + } + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DSOX_Sensor_hub + * @brief This section groups all the functions that manage the + * sensor hub. + * @{ + * + */ + +/** +* @brief Sensor hub output registers.[get] +* +* @param ctx read / write interface definitions +* @param val union of registers from SENSOR_HUB_1 to SENSOR_HUB_18 +* + */ +int32_t lsm6dsox_sh_read_data_raw_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_emb_sh_read_t *val) +{ + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SENSOR_HUB_1, (uint8_t*) val, 18U); + } + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + + return ret; +} + +/** + * @brief Number of external sensors to be read by the sensor hub.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of aux_sens_on in reg MASTER_CONFIG + * + */ +int32_t lsm6dsox_sh_slave_connected_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_aux_sens_on_t val) +{ + lsm6dsox_master_config_t reg; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1); + } + if (ret == 0) { + reg.aux_sens_on = (uint8_t)val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1); + } + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + return ret; +} + +/** + * @brief Number of external sensors to be read by the sensor hub.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of aux_sens_on in reg MASTER_CONFIG + * + */ +int32_t lsm6dsox_sh_slave_connected_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_aux_sens_on_t *val) +{ + lsm6dsox_master_config_t reg; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1); + } + if (ret == 0) { + switch (reg.aux_sens_on) { + case LSM6DSOX_SLV_0: + *val = LSM6DSOX_SLV_0; + break; + case LSM6DSOX_SLV_0_1: + *val = LSM6DSOX_SLV_0_1; + break; + case LSM6DSOX_SLV_0_1_2: + *val = LSM6DSOX_SLV_0_1_2; + break; + case LSM6DSOX_SLV_0_1_2_3: + *val = LSM6DSOX_SLV_0_1_2_3; + break; + default: + *val = LSM6DSOX_SLV_0; + break; + } + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + + return ret; +} + +/** + * @brief Sensor hub I2C master enable.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of master_on in reg MASTER_CONFIG + * + */ +int32_t lsm6dsox_sh_master_set(lsm6dsox_ctx_t *ctx, uint8_t val) +{ + lsm6dsox_master_config_t reg; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1); + } + if (ret == 0) { + reg.master_on = val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1); + } + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + return ret; +} + +/** + * @brief Sensor hub I2C master enable.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of master_on in reg MASTER_CONFIG + * + */ +int32_t lsm6dsox_sh_master_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_master_config_t reg; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1); + } + if (ret == 0) { + *val = reg.master_on; + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + + return ret; +} + +/** + * @brief Master I2C pull-up enable.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of shub_pu_en in reg MASTER_CONFIG + * + */ +int32_t lsm6dsox_sh_pin_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_shub_pu_en_t val) +{ + lsm6dsox_master_config_t reg; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1); + } + if (ret == 0) { + reg.shub_pu_en = (uint8_t)val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1); + } + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + + return ret; +} + +/** + * @brief Master I2C pull-up enable.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of shub_pu_en in reg MASTER_CONFIG + * + */ +int32_t lsm6dsox_sh_pin_mode_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_shub_pu_en_t *val) +{ + lsm6dsox_master_config_t reg; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1); + } + if (ret == 0) { + switch (reg.shub_pu_en) { + case LSM6DSOX_EXT_PULL_UP: + *val = LSM6DSOX_EXT_PULL_UP; + break; + case LSM6DSOX_INTERNAL_PULL_UP: + *val = LSM6DSOX_INTERNAL_PULL_UP; + break; + default: + *val = LSM6DSOX_EXT_PULL_UP; + break; + } + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + + return ret; +} + +/** + * @brief I2C interface pass-through.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of pass_through_mode in + * reg MASTER_CONFIG + * + */ +int32_t lsm6dsox_sh_pass_through_set(lsm6dsox_ctx_t *ctx, uint8_t val) +{ + lsm6dsox_master_config_t reg; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1); + } + if (ret == 0) { + reg.pass_through_mode = val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1); + } + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + + return ret; +} + +/** + * @brief I2C interface pass-through.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of pass_through_mode in + * reg MASTER_CONFIG + * + */ +int32_t lsm6dsox_sh_pass_through_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_master_config_t reg; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1); + } + if (ret == 0) { + *val = reg.pass_through_mode; + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + + return ret; +} + +/** + * @brief Sensor hub trigger signal selection.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of start_config in reg MASTER_CONFIG + * + */ +int32_t lsm6dsox_sh_syncro_mode_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_start_config_t val) +{ + lsm6dsox_master_config_t reg; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1); + } + if (ret == 0) { + reg.start_config = (uint8_t)val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1); + } + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + + return ret; +} + +/** + * @brief Sensor hub trigger signal selection.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of start_config in reg MASTER_CONFIG + * + */ +int32_t lsm6dsox_sh_syncro_mode_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_start_config_t *val) +{ + lsm6dsox_master_config_t reg; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1); + } + if (ret == 0) { + switch (reg.start_config) { + case LSM6DSOX_EXT_ON_INT2_PIN: + *val = LSM6DSOX_EXT_ON_INT2_PIN; + break; + case LSM6DSOX_XL_GY_DRDY: + *val = LSM6DSOX_XL_GY_DRDY; + break; + default: + *val = LSM6DSOX_EXT_ON_INT2_PIN; + break; + } + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + return ret; +} + +/** + * @brief Slave 0 write operation is performed only at the first + * sensor hub cycle.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of write_once in reg MASTER_CONFIG + * + */ +int32_t lsm6dsox_sh_write_mode_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_write_once_t val) +{ + lsm6dsox_master_config_t reg; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1); + } + if (ret == 0) { + reg.write_once = (uint8_t)val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1); + } + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + + return ret; +} + +/** + * @brief Slave 0 write operation is performed only at the first sensor + * hub cycle.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of write_once in reg MASTER_CONFIG + * + */ +int32_t lsm6dsox_sh_write_mode_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_write_once_t *val) +{ + lsm6dsox_master_config_t reg; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1); + } + if (ret == 0) { + switch (reg.write_once) { + case LSM6DSOX_EACH_SH_CYCLE: + *val = LSM6DSOX_EACH_SH_CYCLE; + break; + case LSM6DSOX_ONLY_FIRST_CYCLE: + *val = LSM6DSOX_ONLY_FIRST_CYCLE; + break; + default: + *val = LSM6DSOX_EACH_SH_CYCLE; + break; + } + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + + return ret; +} + +/** + * @brief Reset Master logic and output registers.[set] + * + * @param ctx read / write interface definitions + * + */ +int32_t lsm6dsox_sh_reset_set(lsm6dsox_ctx_t *ctx) +{ + lsm6dsox_master_config_t reg; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1); + } + if (ret == 0) { + reg.rst_master_regs = PROPERTY_ENABLE; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1); + } + if (ret == 0) { + reg.rst_master_regs = PROPERTY_DISABLE; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1); + } + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + + return ret; +} + +/** + * @brief Reset Master logic and output registers.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of rst_master_regs in reg MASTER_CONFIG + * + */ +int32_t lsm6dsox_sh_reset_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_master_config_t reg; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t*)®, 1); + } + if (ret == 0) { + *val = reg.rst_master_regs; + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + return ret; +} + +/** + * @brief Rate at which the master communicates.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of shub_odr in reg slv1_CONFIG + * + */ +int32_t lsm6dsox_sh_data_rate_set(lsm6dsox_ctx_t *ctx, lsm6dsox_shub_odr_t val) +{ + lsm6dsox_slv0_config_t reg; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV1_CONFIG, (uint8_t*)®, 1); + } + if (ret == 0) { + reg.shub_odr = (uint8_t)val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV1_CONFIG, (uint8_t*)®, 1); + } + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + + return ret; +} + +/** + * @brief Rate at which the master communicates.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of shub_odr in reg slv1_CONFIG + * + */ +int32_t lsm6dsox_sh_data_rate_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_shub_odr_t *val) +{ + lsm6dsox_slv0_config_t reg; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV1_CONFIG, (uint8_t*)®, 1); + } + if (ret == 0) { + switch (reg.shub_odr) { + case LSM6DSOX_SH_ODR_104Hz: + *val = LSM6DSOX_SH_ODR_104Hz; + break; + case LSM6DSOX_SH_ODR_52Hz: + *val = LSM6DSOX_SH_ODR_52Hz; + break; + case LSM6DSOX_SH_ODR_26Hz: + *val = LSM6DSOX_SH_ODR_26Hz; + break; + case LSM6DSOX_SH_ODR_13Hz: + *val = LSM6DSOX_SH_ODR_13Hz; + break; + default: + *val = LSM6DSOX_SH_ODR_104Hz; + break; + } + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + + return ret; +} + +/** + * @brief Configure slave 0 for perform a write.[set] + * + * @param ctx read / write interface definitions + * @param val a structure that contain + * - uint8_t slv1_add; 8 bit i2c device address + * - uint8_t slv1_subadd; 8 bit register device address + * - uint8_t slv1_data; 8 bit data to write + * + */ +int32_t lsm6dsox_sh_cfg_write(lsm6dsox_ctx_t *ctx, lsm6dsox_sh_cfg_write_t *val) +{ + lsm6dsox_slv0_add_t reg; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); + if (ret == 0) { + reg.slave0 = val->slv0_add; + reg.rw_0 = 0; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV0_ADD, (uint8_t*)®, 1); + } + if (ret == 0) { + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV0_SUBADD, + &(val->slv0_subadd), 1); + } + if (ret == 0) { + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_DATAWRITE_SLV0, + &(val->slv0_data), 1); + } + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + return ret; +} + +/** + * @brief Configure slave 0 for perform a read.[set] + * + * @param ctx read / write interface definitions + * @param val Structure that contain + * - uint8_t slv1_add; 8 bit i2c device address + * - uint8_t slv1_subadd; 8 bit register device address + * - uint8_t slv1_len; num of bit to read + * + */ +int32_t lsm6dsox_sh_slv0_cfg_read(lsm6dsox_ctx_t *ctx, + lsm6dsox_sh_cfg_read_t *val) +{ + lsm6dsox_slv0_add_t slv0_add; + lsm6dsox_slv0_config_t slv0_config; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); + if (ret == 0) { + slv0_add.slave0 = val->slv_add; + slv0_add.rw_0 = 1; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV0_ADD, (uint8_t*)&slv0_add, 1); + } + if (ret == 0) { + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV0_SUBADD, + &(val->slv_subadd), 1); + } + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV0_CONFIG, + (uint8_t*)&slv0_config, 1); + } + if (ret == 0) { + slv0_config.slave0_numop = val->slv_len; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV0_CONFIG, + (uint8_t*)&slv0_config, 1); + } + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + + return ret; +} + +/** + * @brief Configure slave 0 for perform a write/read.[set] + * + * @param ctx read / write interface definitions + * @param val Structure that contain + * - uint8_t slv1_add; 8 bit i2c device address + * - uint8_t slv1_subadd; 8 bit register device address + * - uint8_t slv1_len; num of bit to read + * + */ +int32_t lsm6dsox_sh_slv1_cfg_read(lsm6dsox_ctx_t *ctx, + lsm6dsox_sh_cfg_read_t *val) +{ + lsm6dsox_slv1_add_t slv1_add; + lsm6dsox_slv1_config_t slv1_config; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); + if (ret == 0) { + slv1_add.slave1_add = val->slv_add; + slv1_add.r_1 = 1; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV1_ADD, (uint8_t*)&slv1_add, 1); + } + if (ret == 0) { + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV1_SUBADD, + &(val->slv_subadd), 1); + } + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV1_CONFIG, + (uint8_t*)&slv1_config, 1); + } + if (ret == 0) { + slv1_config.slave1_numop = val->slv_len; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV1_CONFIG, + (uint8_t*)&slv1_config, 1); + } + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + + return ret; +} + +/** + * @brief Configure slave 0 for perform a write/read.[set] + * + * @param ctx read / write interface definitions + * @param val Structure that contain + * - uint8_t slv2_add; 8 bit i2c device address + * - uint8_t slv2_subadd; 8 bit register device address + * - uint8_t slv2_len; num of bit to read + * + */ +int32_t lsm6dsox_sh_slv2_cfg_read(lsm6dsox_ctx_t *ctx, + lsm6dsox_sh_cfg_read_t *val) +{ + lsm6dsox_slv2_add_t slv2_add; + lsm6dsox_slv2_config_t slv2_config; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); + if (ret == 0) { + slv2_add.slave2_add = val->slv_add; + slv2_add.r_2 = 1; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV2_ADD, (uint8_t*)&slv2_add, 1); + } + if (ret == 0) { + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV2_SUBADD, + &(val->slv_subadd), 1); + } + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV2_CONFIG, + (uint8_t*)&slv2_config, 1); + } + if (ret == 0) { + slv2_config.slave2_numop = val->slv_len; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV2_CONFIG, + (uint8_t*)&slv2_config, 1); + } + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + return ret; +} + +/** + * @brief Configure slave 0 for perform a write/read.[set] + * + * @param ctx read / write interface definitions + * @param val Structure that contain + * - uint8_t slv3_add; 8 bit i2c device address + * - uint8_t slv3_subadd; 8 bit register device address + * - uint8_t slv3_len; num of bit to read + * + */ +int32_t lsm6dsox_sh_slv3_cfg_read(lsm6dsox_ctx_t *ctx, + lsm6dsox_sh_cfg_read_t *val) +{ + lsm6dsox_slv3_add_t slv3_add; + lsm6dsox_slv3_config_t slv3_config; + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); + if (ret == 0) { + slv3_add.slave3_add = val->slv_add; + slv3_add.r_3 = 1; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV3_ADD, (uint8_t*)&slv3_add, 1); + } + if (ret == 0) { + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV3_SUBADD, + &(val->slv_subadd), 1); + } + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV3_CONFIG, + (uint8_t*)&slv3_config, 1); + } + if (ret == 0) { + slv3_config.slave3_numop = val->slv_len; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV3_CONFIG, + (uint8_t*)&slv3_config, 1); + } + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + return ret; +} + +/** + * @brief Sensor hub source register.[get] + * + * @param ctx read / write interface definitions + * @param val union of registers from STATUS_MASTER to + * + */ +int32_t lsm6dsox_sh_status_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_status_master_t *val) +{ + int32_t ret; + + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_STATUS_MASTER, (uint8_t*) val, 1); + } + if (ret == 0) { + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + } + + return ret; +} + +/** + * @} + * + */ + + /** + * @addtogroup Sensors for Smart Mobile Devices + * @brief This section groups all the functions that manage the + * Sensors for Smart Mobile Devices. + * @{ + * + */ + +/** + * @brief s4s_tph_res: [set] Sensor synchronization time frame resolution + * + * @param *ctx read / write interface definitions + * @param val change the values of tph_h_sel in LSM6DSOX_S4S_TPH_L + * + */ +int32_t lsm6dsox_s4s_tph_res_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_s4s_tph_res_t val) +{ + lsm6dsox_s4s_tph_l_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_TPH_L, (uint8_t*)®, 1); + if (ret == 0) { + reg.tph_h_sel = (uint8_t)val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_S4S_TPH_L, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief s4s_tph_res: [get] Sensor synchronization time frame resolution + * + * @param *ctx read / write interface definitions + * @param val get the values of tph_h_sel in LSM6DSOX_S4S_TPH_L + * + */ +int32_t lsm6dsox_s4s_tph_res_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_s4s_tph_res_t *val) +{ + lsm6dsox_s4s_tph_l_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_TPH_L, (uint8_t*)®, 1); + switch (reg.tph_h_sel) { + case LSM6DSOX_S4S_TPH_7bit: + *val = LSM6DSOX_S4S_TPH_7bit; + break; + case LSM6DSOX_S4S_TPH_15bit: + *val = LSM6DSOX_S4S_TPH_15bit; + break; + default: + *val = LSM6DSOX_S4S_TPH_7bit; + break; + } + + return ret; +} + +/** + * @brief s4s_tph_val: [set] Sensor synchronization time frame + * + * @param *ctx read / write interface definitions + * @param val change the values of tph_l in S4S_TPH_L and + * tph_h in S4S_TPH_H + * + */ +int32_t lsm6dsox_s4s_tph_val_set(lsm6dsox_ctx_t *ctx, uint16_t val) +{ + lsm6dsox_s4s_tph_l_t s4s_tph_l; + lsm6dsox_s4s_tph_h_t s4s_tph_h; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_TPH_L, (uint8_t*)&s4s_tph_l, 1); + if (ret == 0) { + s4s_tph_l.tph_l = (uint8_t)(val & 0x007FU); + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_S4S_TPH_L, (uint8_t*)&s4s_tph_l, 1); + } + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_TPH_H, (uint8_t*)&s4s_tph_h, 1); + s4s_tph_h.tph_h = (uint8_t)(val & 0x7F80U) >> 7; + } + if (ret == 0) { + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_S4S_TPH_H, (uint8_t*)&s4s_tph_h, 1); + } + return ret; +} + +/** + * @brief s4s_tph_val: [get] Sensor synchronization time frame. + * + * @param *ctx read / write interface definitions + * @param val get the values of tph_l in S4S_TPH_L and + * tph_h in S4S_TPH_H + * + */ +int32_t lsm6dsox_s4s_tph_val_get(lsm6dsox_ctx_t *ctx, uint16_t *val) +{ + lsm6dsox_s4s_tph_l_t s4s_tph_l; + lsm6dsox_s4s_tph_h_t s4s_tph_h; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_TPH_L, (uint8_t*)&s4s_tph_l, 1); + if (ret == 0) { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_TPH_H, (uint8_t*)&s4s_tph_h, 1); + *val = s4s_tph_h.tph_h; + *val = *val << 7; + *val += s4s_tph_l.tph_l; + } + return ret; +} + +/** + * @brief s4s_res_ratio: [set]Sensor synchronization resolution + * ratio register. + * + * @param *ctx read / write interface definitions. + * @param val change the values of rr in S4S_RR. + * + */ +int32_t lsm6dsox_s4s_res_ratio_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_s4s_res_ratio_t val) +{ + lsm6dsox_s4s_rr_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_RR, (uint8_t*)®, 1); + if (ret == 0) { + reg.rr = (uint8_t)val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_S4S_RR, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief s4s_res_ratio: [get]Sensor synchronization resolution + * ratio register. + * + * @param *ctx read / write interface definitions + * @param val get the values of rr in S4S_RR + * + */ +int32_t lsm6dsox_s4s_res_ratio_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_s4s_res_ratio_t *val) +{ + lsm6dsox_s4s_rr_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_RR, (uint8_t*)®, 1); + switch (reg.rr) { + case LSM6DSOX_S4S_DT_RES_11: + *val = LSM6DSOX_S4S_DT_RES_11; + break; + case LSM6DSOX_S4S_DT_RES_12: + *val = LSM6DSOX_S4S_DT_RES_12; + break; + case LSM6DSOX_S4S_DT_RES_13: + *val = LSM6DSOX_S4S_DT_RES_13; + break; + case LSM6DSOX_S4S_DT_RES_14: + *val = LSM6DSOX_S4S_DT_RES_14; + break; + default: + *val = LSM6DSOX_S4S_DT_RES_11; + break; + } + return ret; +} + +/** + * @brief s4s_command: [set] s4s master command. + * + * @param *ctx read / write interface definitions. + * @param val change the values of S4S_ST_CMD_CODE. + * + */ +int32_t lsm6dsox_s4s_command_set(lsm6dsox_ctx_t *ctx, uint8_t val) +{ + lsm6dsox_s4s_st_cmd_code_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_ST_CMD_CODE, (uint8_t*)®, 1); + + if (ret == 0) { + reg.s4s_st_cmd_code = val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_S4S_ST_CMD_CODE, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief s4s_command: [get] s4s master command. + * + * @param *ctx read / write interface definitions. + * @param val get the values of S4S_ST_CMD_CODE. + * + */ +int32_t lsm6dsox_s4s_command_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_s4s_st_cmd_code_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_ST_CMD_CODE, (uint8_t*)®, 1); + *val = reg.s4s_st_cmd_code; + + return ret; +} + +/** + * @brief s4s_dt: [set] S4S DT register. + * + * @param *ctx read / write interface definitions. + * @param val change the values of S4S_DT_REG. + * + */ +int32_t lsm6dsox_s4s_dt_set(lsm6dsox_ctx_t *ctx, uint8_t val) +{ + lsm6dsox_s4s_dt_reg_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_DT_REG, (uint8_t*)®, 1); + if (ret == 0) { + reg.dt = val; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_S4S_DT_REG, (uint8_t*)®, 1); + } + return ret; +} + +/** + * @brief s4s_dt: [get] S4S DT register. + * + * @param *ctx read / write interface definitions. + * @param val get the values of S4S_DT_REG. + * + */ +int32_t lsm6dsox_s4s_dt_get(lsm6dsox_ctx_t *ctx, uint8_t *val) +{ + lsm6dsox_s4s_dt_reg_t reg; + int32_t ret; + + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_DT_REG, (uint8_t*)®, 1); + *val = reg.dt; + + return ret; +} + +/** + * @} + * + */ + +/** + * @} + * + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/LSM6DSOX/lsm6dsox_reg.h b/LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/LSM6DSOX/lsm6dsox_reg.h new file mode 100644 index 0000000..95ac566 --- /dev/null +++ b/LKExp-mbed-sensors/lib/mbed-ST_lib/Drivers/LSM6DSOX/lsm6dsox_reg.h @@ -0,0 +1,2935 @@ +/* + ****************************************************************************** + * @file lsm6dsox_reg.h + * @author Sensor Solutions Software Team + * @brief This file contains all the functions prototypes for the + * lsm6dsox_reg.c driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef LSM6DSOX_DRIVER_H +#define LSM6DSOX_DRIVER_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include +#include + +/** @addtogroup LSM6DSOX + * @{ + * + */ + +/** @defgroup LSM6DSOX_sensors_common_types + * @{ + * + */ + +#ifndef MEMS_SHARED_TYPES +#define MEMS_SHARED_TYPES + +/** + * @defgroup axisXbitXX_t + * @brief These unions are useful to represent different sensors data type. + * These unions are not need by the driver. + * + * REMOVING the unions you are compliant with: + * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " + * + * @{ + * + */ + +typedef union{ + int16_t i16bit[3]; + uint8_t u8bit[6]; +} axis3bit16_t; + +typedef union{ + int16_t i16bit; + uint8_t u8bit[2]; +} axis1bit16_t; + +typedef union{ + int32_t i32bit[3]; + uint8_t u8bit[12]; +} axis3bit32_t; + +typedef union{ + int32_t i32bit; + uint8_t u8bit[4]; +} axis1bit32_t; + +/** + * @} + * + */ + +typedef struct{ + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +} bitwise_t; + +#define PROPERTY_DISABLE (0U) +#define PROPERTY_ENABLE (1U) + +#endif /* MEMS_SHARED_TYPES */ + +/** + * @} + * + */ + +/** @addtogroup LSM6DSOX_Interfaces_Functions + * @brief This section provide a set of functions used to read and + * write a generic register of the device. + * MANDATORY: return 0 -> no Error. + * @{ + * + */ + +typedef int32_t (*lsm6dsox_write_ptr)(void *, uint8_t, uint8_t*, uint16_t); +typedef int32_t (*lsm6dsox_read_ptr) (void *, uint8_t, uint8_t*, uint16_t); + +typedef struct { + /** Component mandatory fields **/ + lsm6dsox_write_ptr write_reg; + lsm6dsox_read_ptr read_reg; + /** Customizable optional pointer **/ + void *handle; +} lsm6dsox_ctx_t; + +/** + * @} + * + */ + +/** @defgroup LSM6DSOX_Infos + * @{ + * + */ + +/** I2C Device Address 8 bit format if SA0=0 -> D5 if SA0=1 -> D7 **/ +#define LSM6DSOX_I2C_ADD_L 0xD5 +#define LSM6DSOX_I2C_ADD_H 0xD7 + +/** Device Identification (Who am I) **/ +#define LSM6DSOX_ID 0x6C + +/** + * @} + * + */ + +#define LSM6DSOX_FUNC_CFG_ACCESS 0x01U +typedef struct { + uint8_t ois_ctrl_from_ui : 1; + uint8_t not_used_01 : 5; + uint8_t reg_access : 2; /* shub_reg_access + func_cfg_access */ +} lsm6dsox_func_cfg_access_t; + +#define LSM6DSOX_PIN_CTRL 0x02U +typedef struct { + uint8_t not_used_01 : 6; + uint8_t sdo_pu_en : 1; + uint8_t ois_pu_dis : 1; +} lsm6dsox_pin_ctrl_t; + +#define LSM6DSOX_S4S_TPH_L 0x04U +typedef struct { + uint8_t tph_l : 7; + uint8_t tph_h_sel : 1; +} lsm6dsox_s4s_tph_l_t; + +#define LSM6DSOX_S4S_TPH_H 0x05U +typedef struct { + uint8_t tph_h : 8; +} lsm6dsox_s4s_tph_h_t; + +#define LSM6DSOX_S4S_RR 0x06U +typedef struct { + uint8_t rr : 2; + uint8_t not_used_01 : 6; +} lsm6dsox_s4s_rr_t; + +#define LSM6DSOX_FIFO_CTRL1 0x07U +typedef struct { + uint8_t wtm : 8; +} lsm6dsox_fifo_ctrl1_t; + +#define LSM6DSOX_FIFO_CTRL2 0x08U +typedef struct { + uint8_t wtm : 1; + uint8_t uncoptr_rate : 2; + uint8_t not_used_01 : 1; + uint8_t odrchg_en : 1; + uint8_t not_used_02 : 1; + uint8_t fifo_compr_rt_en : 1; + uint8_t stop_on_wtm : 1; +} lsm6dsox_fifo_ctrl2_t; + +#define LSM6DSOX_FIFO_CTRL3 0x09U +typedef struct { + uint8_t bdr_xl : 4; + uint8_t bdr_gy : 4; +} lsm6dsox_fifo_ctrl3_t; + +#define LSM6DSOX_FIFO_CTRL4 0x0AU +typedef struct { + uint8_t fifo_mode : 3; + uint8_t not_used_01 : 1; + uint8_t odr_t_batch : 2; + uint8_t odr_ts_batch : 2; +} lsm6dsox_fifo_ctrl4_t; + +#define LSM6DSOX_COUNTER_BDR_REG1 0x0BU +typedef struct { + uint8_t cnt_bdr_th : 3; + uint8_t not_used_01 : 2; + uint8_t trig_counter_bdr : 1; + uint8_t rst_counter_bdr : 1; + uint8_t dataready_pulsed : 1; +} lsm6dsox_counter_bdr_reg1_t; + +#define LSM6DSOX_COUNTER_BDR_REG2 0x0CU +typedef struct { + uint8_t cnt_bdr_th : 8; +} lsm6dsox_counter_bdr_reg2_t; + +#define LSM6DSOX_INT1_CTRL 0x0D +typedef struct { + uint8_t int1_drdy_xl : 1; + uint8_t int1_drdy_g : 1; + uint8_t int1_boot : 1; + uint8_t int1_fifo_th : 1; + uint8_t int1_fifo_ovr : 1; + uint8_t int1_fifo_full : 1; + uint8_t int1_cnt_bdr : 1; + uint8_t den_drdy_flag : 1; +} lsm6dsox_int1_ctrl_t; + +#define LSM6DSOX_INT2_CTRL 0x0EU +typedef struct { + uint8_t int2_drdy_xl : 1; + uint8_t int2_drdy_g : 1; + uint8_t int2_drdy_temp : 1; + uint8_t int2_fifo_th : 1; + uint8_t int2_fifo_ovr : 1; + uint8_t int2_fifo_full : 1; + uint8_t int2_cnt_bdr : 1; + uint8_t not_used_01 : 1; +} lsm6dsox_int2_ctrl_t; + +#define LSM6DSOX_WHO_AM_I 0x0FU +#define LSM6DSOX_CTRL1_XL 0x10U +typedef struct { + uint8_t not_used_01 : 1; + uint8_t lpf2_xl_en : 1; + uint8_t fs_xl : 2; + uint8_t odr_xl : 4; +} lsm6dsox_ctrl1_xl_t; + +#define LSM6DSOX_CTRL2_G 0x11U +typedef struct { + uint8_t not_used_01 : 1; + uint8_t fs_g : 3; /* fs_125 + fs_g */ + uint8_t odr_g : 4; +} lsm6dsox_ctrl2_g_t; + +#define LSM6DSOX_CTRL3_C 0x12U +typedef struct { + uint8_t sw_reset : 1; + uint8_t not_used_01 : 1; + uint8_t if_inc : 1; + uint8_t sim : 1; + uint8_t pp_od : 1; + uint8_t h_lactive : 1; + uint8_t bdu : 1; + uint8_t boot : 1; +} lsm6dsox_ctrl3_c_t; + +#define LSM6DSOX_CTRL4_C 0x13U +typedef struct { + uint8_t not_used_01 : 1; + uint8_t lpf1_sel_g : 1; + uint8_t i2c_disable : 1; + uint8_t drdy_mask : 1; + uint8_t not_used_02 : 1; + uint8_t int2_on_int1 : 1; + uint8_t sleep_g : 1; + uint8_t not_used_03 : 1; +} lsm6dsox_ctrl4_c_t; + +#define LSM6DSOX_CTRL5_C 0x14U +typedef struct { + uint8_t st_xl : 2; + uint8_t st_g : 2; + uint8_t rounding_status : 1; + uint8_t rounding : 2; + uint8_t xl_ulp_en : 1; +} lsm6dsox_ctrl5_c_t; + +#define LSM6DSOX_CTRL6_C 0x15U +typedef struct { + uint8_t ftype : 3; + uint8_t usr_off_w : 1; + uint8_t xl_hm_mode : 1; + uint8_t den_mode : 3; /* trig_en + lvl1_en + lvl2_en */ +} lsm6dsox_ctrl6_c_t; + +#define LSM6DSOX_CTRL7_G 0x16U +typedef struct { + uint8_t ois_on : 1; + uint8_t usr_off_on_out : 1; + uint8_t ois_on_en : 1; + uint8_t not_used_01 : 1; + uint8_t hpm_g : 2; + uint8_t hp_en_g : 1; + uint8_t g_hm_mode : 1; +} lsm6dsox_ctrl7_g_t; + +#define LSM6DSOX_CTRL8_XL 0x17U +typedef struct { + uint8_t low_pass_on_6d : 1; + uint8_t xl_fs_mode : 1; + uint8_t hp_slope_xl_en : 1; + uint8_t fastsettl_mode_xl : 1; + uint8_t hp_ref_mode_xl : 1; + uint8_t hpcf_xl : 3; +} lsm6dsox_ctrl8_xl_t; + +#define LSM6DSOX_CTRL9_XL 0x18U +typedef struct { + uint8_t not_used_01 : 1; + uint8_t i3c_disable : 1; + uint8_t den_lh : 1; + uint8_t den_xl_g : 2; /* den_xl_en + den_xl_g */ + uint8_t den_z : 1; + uint8_t den_y : 1; + uint8_t den_x : 1; +} lsm6dsox_ctrl9_xl_t; + +#define LSM6DSOX_CTRL10_C 0x19U +typedef struct { + uint8_t not_used_01 : 5; + uint8_t timestamp_en : 1; + uint8_t not_used_02 : 2; +} lsm6dsox_ctrl10_c_t; + +#define LSM6DSOX_ALL_INT_SRC 0x1AU +typedef struct { + uint8_t ff_ia : 1; + uint8_t wu_ia : 1; + uint8_t single_tap : 1; + uint8_t double_tap : 1; + uint8_t d6d_ia : 1; + uint8_t sleep_change_ia : 1; + uint8_t not_used_01 : 1; + uint8_t timestamp_endcount : 1; +} lsm6dsox_all_int_src_t; + +#define LSM6DSOX_WAKE_UP_SRC 0x1BU +typedef struct { + uint8_t z_wu : 1; + uint8_t y_wu : 1; + uint8_t x_wu : 1; + uint8_t wu_ia : 1; + uint8_t sleep_state : 1; + uint8_t ff_ia : 1; + uint8_t sleep_change_ia : 2; +} lsm6dsox_wake_up_src_t; + +#define LSM6DSOX_TAP_SRC 0x1CU +typedef struct { + uint8_t z_tap : 1; + uint8_t y_tap : 1; + uint8_t x_tap : 1; + uint8_t tap_sign : 1; + uint8_t double_tap : 1; + uint8_t single_tap : 1; + uint8_t tap_ia : 1; + uint8_t not_used_02 : 1; +} lsm6dsox_tap_src_t; + +#define LSM6DSOX_D6D_SRC 0x1DU +typedef struct { + uint8_t xl : 1; + uint8_t xh : 1; + uint8_t yl : 1; + uint8_t yh : 1; + uint8_t zl : 1; + uint8_t zh : 1; + uint8_t d6d_ia : 1; + uint8_t den_drdy : 1; +} lsm6dsox_d6d_src_t; + +#define LSM6DSOX_STATUS_REG 0x1EU +typedef struct { + uint8_t xlda : 1; + uint8_t gda : 1; + uint8_t tda : 1; + uint8_t not_used_01 : 5; +} lsm6dsox_status_reg_t; + +#define LSM6DSOX_OUT_TEMP_L 0x20U +#define LSM6DSOX_OUT_TEMP_H 0x21U +#define LSM6DSOX_OUTX_L_G 0x22U +#define LSM6DSOX_OUTX_H_G 0x23U +#define LSM6DSOX_OUTY_L_G 0x24U +#define LSM6DSOX_OUTY_H_G 0x25U +#define LSM6DSOX_OUTZ_L_G 0x26U +#define LSM6DSOX_OUTZ_H_G 0x27U +#define LSM6DSOX_OUTX_L_A 0x28U +#define LSM6DSOX_OUTX_H_A 0x29U +#define LSM6DSOX_OUTY_L_A 0x2AU +#define LSM6DSOX_OUTY_H_A 0x2BU +#define LSM6DSOX_OUTZ_L_A 0x2CU +#define LSM6DSOX_OUTZ_H_A 0x2DU +#define LSM6DSOX_EMB_FUNC_STATUS_MAINPAGE 0x35U +typedef struct { + uint8_t not_used_01 : 3; + uint8_t is_step_det : 1; + uint8_t is_tilt : 1; + uint8_t is_sigmot : 1; + uint8_t not_used_02 : 1; + uint8_t is_fsm_lc : 1; +} lsm6dsox_emb_func_status_mainpage_t; + +#define LSM6DSOX_FSM_STATUS_A_MAINPAGE 0x36U +typedef struct { + uint8_t is_fsm1 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm8 : 1; +} lsm6dsox_fsm_status_a_mainpage_t; + +#define LSM6DSOX_FSM_STATUS_B_MAINPAGE 0x37U +typedef struct { + uint8_t is_fsm9 : 1; + uint8_t is_fsm10 : 1; + uint8_t is_fsm11 : 1; + uint8_t is_fsm12 : 1; + uint8_t is_fsm13 : 1; + uint8_t is_fsm14 : 1; + uint8_t is_fsm15 : 1; + uint8_t is_fsm16 : 1; +} lsm6dsox_fsm_status_b_mainpage_t; + +#define LSM6DSOX_MLC_STATUS_MAINPAGE 0x38U +typedef struct { + uint8_t is_mlc1 : 1; + uint8_t is_mlc2 : 1; + uint8_t is_mlc3 : 1; + uint8_t is_mlc4 : 1; + uint8_t is_mlc5 : 1; + uint8_t is_mlc6 : 1; + uint8_t is_mlc7 : 1; + uint8_t is_mlc8 : 1; +} lsm6dsox_mlc_status_mainpage_t; + +#define LSM6DSOX_STATUS_MASTER_MAINPAGE 0x39U +typedef struct { + uint8_t sens_hub_endop : 1; + uint8_t not_used_01 : 2; + uint8_t slave0_nack : 1; + uint8_t slave1_nack : 1; + uint8_t slave2_nack : 1; + uint8_t slave3_nack : 1; + uint8_t wr_once_done : 1; +} lsm6dsox_status_master_mainpage_t; + +#define LSM6DSOX_FIFO_STATUS1 0x3AU +typedef struct { + uint8_t diff_fifo : 8; +} lsm6dsox_fifo_status1_t; + +#define LSM6DSOX_FIFO_STATUS2 0x3B +typedef struct { + uint8_t diff_fifo : 2; + uint8_t not_used_01 : 1; + uint8_t over_run_latched : 1; + uint8_t counter_bdr_ia : 1; + uint8_t fifo_full_ia : 1; + uint8_t fifo_ovr_ia : 1; + uint8_t fifo_wtm_ia : 1; +} lsm6dsox_fifo_status2_t; + +#define LSM6DSOX_TIMESTAMP0 0x40U +#define LSM6DSOX_TIMESTAMP1 0x41U +#define LSM6DSOX_TIMESTAMP2 0x42U +#define LSM6DSOX_TIMESTAMP3 0x43U +#define LSM6DSOX_UI_STATUS_REG_OIS 0x49U +typedef struct { + uint8_t xlda : 1; + uint8_t gda : 1; + uint8_t gyro_settling : 1; + uint8_t not_used_01 : 5; +} lsm6dsox_ui_status_reg_ois_t; + +#define LSM6DSOX_UI_OUTX_L_G_OIS 0x4AU +#define LSM6DSOX_UI_OUTX_H_G_OIS 0x4BU +#define LSM6DSOX_UI_OUTY_L_G_OIS 0x4CU +#define LSM6DSOX_UI_OUTY_H_G_OIS 0x4DU +#define LSM6DSOX_UI_OUTZ_L_G_OIS 0x4EU +#define LSM6DSOX_UI_OUTZ_H_G_OIS 0x4FU +#define LSM6DSOX_UI_OUTX_L_A_OIS 0x50U +#define LSM6DSOX_UI_OUTX_H_A_OIS 0x51U +#define LSM6DSOX_UI_OUTY_L_A_OIS 0x52U +#define LSM6DSOX_UI_OUTY_H_A_OIS 0x53U +#define LSM6DSOX_UI_OUTZ_L_A_OIS 0x54U +#define LSM6DSOX_UI_OUTZ_H_A_OIS 0x55U + +#define LSM6DSOX_TAP_CFG0 0x56U +typedef struct { + uint8_t lir : 1; + uint8_t tap_z_en : 1; + uint8_t tap_y_en : 1; + uint8_t tap_x_en : 1; + uint8_t slope_fds : 1; + uint8_t sleep_status_on_int : 1; + uint8_t int_clr_on_read : 1; + uint8_t not_used_01 : 1; +} lsm6dsox_tap_cfg0_t; + +#define LSM6DSOX_TAP_CFG1 0x57U +typedef struct { + uint8_t tap_ths_x : 5; + uint8_t tap_priority : 3; +} lsm6dsox_tap_cfg1_t; + +#define LSM6DSOX_TAP_CFG2 0x58U +typedef struct { + uint8_t tap_ths_y : 5; + uint8_t inact_en : 2; + uint8_t interrupts_enable : 1; +} lsm6dsox_tap_cfg2_t; + +#define LSM6DSOX_TAP_THS_6D 0x59U +typedef struct { + uint8_t tap_ths_z : 5; + uint8_t sixd_ths : 2; + uint8_t d4d_en : 1; +} lsm6dsox_tap_ths_6d_t; + +#define LSM6DSOX_INT_DUR2 0x5AU +typedef struct { + uint8_t shock : 2; + uint8_t quiet : 2; + uint8_t dur : 4; +} lsm6dsox_int_dur2_t; + +#define LSM6DSOX_WAKE_UP_THS 0x5BU +typedef struct { + uint8_t wk_ths : 6; + uint8_t usr_off_on_wu : 1; + uint8_t single_double_tap : 1; +} lsm6dsox_wake_up_ths_t; + +#define LSM6DSOX_WAKE_UP_DUR 0x5CU +typedef struct { + uint8_t sleep_dur : 4; + uint8_t wake_ths_w : 1; + uint8_t wake_dur : 2; + uint8_t ff_dur : 1; +} lsm6dsox_wake_up_dur_t; + +#define LSM6DSOX_FREE_FALL 0x5DU +typedef struct { + uint8_t ff_ths : 3; + uint8_t ff_dur : 5; +} lsm6dsox_free_fall_t; + +#define LSM6DSOX_MD1_CFG 0x5EU +typedef struct { + uint8_t int1_shub : 1; + uint8_t int1_emb_func : 1; + uint8_t int1_6d : 1; + uint8_t int1_double_tap : 1; + uint8_t int1_ff : 1; + uint8_t int1_wu : 1; + uint8_t int1_single_tap : 1; + uint8_t int1_sleep_change : 1; +} lsm6dsox_md1_cfg_t; + +#define LSM6DSOX_MD2_CFG 0x5FU +typedef struct { + uint8_t int2_timestamp : 1; + uint8_t int2_emb_func : 1; + uint8_t int2_6d : 1; + uint8_t int2_double_tap : 1; + uint8_t int2_ff : 1; + uint8_t int2_wu : 1; + uint8_t int2_single_tap : 1; + uint8_t int2_sleep_change : 1; +} lsm6dsox_md2_cfg_t; + +#define LSM6DSOX_S4S_ST_CMD_CODE 0x60U +typedef struct { + uint8_t s4s_st_cmd_code : 8; +} lsm6dsox_s4s_st_cmd_code_t; + +#define LSM6DSOX_S4S_DT_REG 0x61U +typedef struct { + uint8_t dt : 8; +} lsm6dsox_s4s_dt_reg_t; + +#define LSM6DSOX_I3C_BUS_AVB 0x62U +typedef struct { + uint8_t pd_dis_int1 : 1; + uint8_t not_used_01 : 2; + uint8_t i3c_bus_avb_sel : 2; + uint8_t not_used_02 : 3; +} lsm6dsox_i3c_bus_avb_t; + +#define LSM6DSOX_INTERNAL_FREQ_FINE 0x63U +typedef struct { + uint8_t freq_fine : 8; +} lsm6dsox_internal_freq_fine_t; + +#define LSM6DSOX_UI_INT_OIS 0x6F +typedef struct { + uint8_t not_used_01 : 3; + uint8_t spi2_read_en : 1; + uint8_t not_used_02 : 1; + uint8_t den_lh_ois : 1; + uint8_t lvl2_ois : 1; + uint8_t int2_drdy_ois : 1; +} lsm6dsox_ui_int_ois_t; + +#define LSM6DSOX_UI_CTRL1_OIS 0x70U +typedef struct { + uint8_t ois_en_spi2 : 1; + uint8_t fs_g_ois : 3; /* fs_125_ois + fs[1:0]_g_ois */ + uint8_t mode4_en : 1; + uint8_t sim_ois : 1; + uint8_t lvl1_ois : 1; + uint8_t not_used_01 : 1; +} lsm6dsox_ui_ctrl1_ois_t; + +#define LSM6DSOX_UI_CTRL2_OIS 0x71U +typedef struct { + uint8_t hp_en_ois : 1; + uint8_t ftype_ois : 2; + uint8_t not_used_01 : 1; + uint8_t hpm_ois : 2; + uint8_t not_used_02 : 2; +} lsm6dsox_ui_ctrl2_ois_t; + +#define LSM6DSOX_UI_CTRL3_OIS 0x72U +typedef struct { + uint8_t st_ois_clampdis : 1; + uint8_t not_used_01 : 2; + uint8_t filter_xl_conf_ois : 3; + uint8_t fs_xl_ois : 2; +} lsm6dsox_ui_ctrl3_ois_t; + +#define LSM6DSOX_X_OFS_USR 0x73U +#define LSM6DSOX_Y_OFS_USR 0x74U +#define LSM6DSOX_Z_OFS_USR 0x75U +#define LSM6DSOX_FIFO_DATA_OUT_TAG 0x78U +typedef struct { + uint8_t tag_parity : 1; + uint8_t tag_cnt : 2; + uint8_t tag_sensor : 5; +} lsm6dsox_fifo_data_out_tag_t; + +#define LSM6DSOX_FIFO_DATA_OUT_X_L 0x79 +#define LSM6DSOX_FIFO_DATA_OUT_X_H 0x7A +#define LSM6DSOX_FIFO_DATA_OUT_Y_L 0x7B +#define LSM6DSOX_FIFO_DATA_OUT_Y_H 0x7C +#define LSM6DSOX_FIFO_DATA_OUT_Z_L 0x7D +#define LSM6DSOX_FIFO_DATA_OUT_Z_H 0x7E + +#define LSM6DSOX_SPI2_WHO_AM_I 0x0F +#define LSM6DSOX_SPI2_STATUS_REG_OIS 0x1E +typedef struct { + uint8_t xlda : 1; + uint8_t gda : 1; + uint8_t gyro_settling : 1; + uint8_t not_used_01 : 5; +} lsm6dsox_spi2_status_reg_ois_t; + +#define LSM6DSOX_SPI2_OUT_TEMP_L 0x20 +#define LSM6DSOX_SPI2_OUT_TEMP_H 0x21 +#define LSM6DSOX_SPI2_OUTX_L_G_OIS 0x22 +#define LSM6DSOX_SPI2_OUTX_H_G_OIS 0x23 +#define LSM6DSOX_SPI2_OUTY_L_G_OIS 0x24 +#define LSM6DSOX_SPI2_OUTY_H_G_OIS 0x25 +#define LSM6DSOX_SPI2_OUTZ_L_G_OIS 0x26 +#define LSM6DSOX_SPI2_OUTZ_H_G_OIS 0x27 +#define LSM6DSOX_SPI2_OUTX_L_A_OIS 0x28 +#define LSM6DSOX_SPI2_OUTX_H_A_OIS 0x29 +#define LSM6DSOX_SPI2_OUTY_L_A_OIS 0x2A +#define LSM6DSOX_SPI2_OUTY_H_A_OIS 0x2B +#define LSM6DSOX_SPI2_OUTZ_L_A_OIS 0x2C +#define LSM6DSOX_SPI2_OUTZ_H_A_OIS 0x2D +#define LSM6DSOX_SPI2_INT_OIS 0x6F +typedef struct { + uint8_t st_xl_ois : 2; + uint8_t not_used_01 : 3; + uint8_t den_lh_ois : 1; + uint8_t lvl2_ois : 1; + uint8_t int2_drdy_ois : 1; +} lsm6dsox_spi2_int_ois_t; + +#define LSM6DSOX_SPI2_CTRL1_OIS 0x70U +typedef struct { + uint8_t ois_en_spi2 : 1; + uint8_t fs_g_ois : 3; /* fs_125_ois + fs[1:0]_g_ois */ + uint8_t mode4_en : 1; + uint8_t sim_ois : 1; + uint8_t lvl1_ois : 1; + uint8_t not_used_01 : 1; +} lsm6dsox_spi2_ctrl1_ois_t; + +#define LSM6DSOX_SPI2_CTRL2_OIS 0x71U +typedef struct { + uint8_t hp_en_ois : 1; + uint8_t ftype_ois : 2; + uint8_t not_used_01 : 1; + uint8_t hpm_ois : 2; + uint8_t not_used_02 : 2; +} lsm6dsox_spi2_ctrl2_ois_t; + +#define LSM6DSOX_SPI2_CTRL3_OIS 0x72U +typedef struct { + uint8_t st_ois_clampdis : 1; + uint8_t st_ois : 2; + uint8_t filter_xl_conf_ois : 3; + uint8_t fs_xl_ois : 2; +} lsm6dsox_spi2_ctrl3_ois_t; + +#define LSM6DSOX_PAGE_SEL 0x02U +typedef struct { + uint8_t not_used_01 : 4; + uint8_t page_sel : 4; +} lsm6dsox_page_sel_t; + +#define LSM6DSOX_EMB_FUNC_EN_A 0x04U +typedef struct { + uint8_t not_used_01 : 3; + uint8_t pedo_en : 1; + uint8_t tilt_en : 1; + uint8_t sign_motion_en : 1; + uint8_t not_used_02 : 2; +} lsm6dsox_emb_func_en_a_t; + +#define LSM6DSOX_EMB_FUNC_EN_B 0x05U +typedef struct { + uint8_t fsm_en : 1; + uint8_t not_used_01 : 2; + uint8_t fifo_compr_en : 1; + uint8_t mlc_en : 1; + uint8_t not_used_02 : 3; +} lsm6dsox_emb_func_en_b_t; + +#define LSM6DSOX_PAGE_ADDRESS 0x08U +typedef struct { + uint8_t page_addr : 8; +} lsm6dsox_page_address_t; + +#define LSM6DSOX_PAGE_VALUE 0x09U +typedef struct { + uint8_t page_value : 8; +} lsm6dsox_page_value_t; + +#define LSM6DSOX_EMB_FUNC_INT1 0x0AU +typedef struct { + uint8_t not_used_01 : 3; + uint8_t int1_step_detector : 1; + uint8_t int1_tilt : 1; + uint8_t int1_sig_mot : 1; + uint8_t not_used_02 : 1; + uint8_t int1_fsm_lc : 1; +} lsm6dsox_emb_func_int1_t; + +#define LSM6DSOX_FSM_INT1_A 0x0BU +typedef struct { + uint8_t int1_fsm1 : 1; + uint8_t int1_fsm2 : 1; + uint8_t int1_fsm3 : 1; + uint8_t int1_fsm4 : 1; + uint8_t int1_fsm5 : 1; + uint8_t int1_fsm6 : 1; + uint8_t int1_fsm7 : 1; + uint8_t int1_fsm8 : 1; +} lsm6dsox_fsm_int1_a_t; + +#define LSM6DSOX_FSM_INT1_B 0x0CU +typedef struct { + uint8_t int1_fsm9 : 1; + uint8_t int1_fsm10 : 1; + uint8_t int1_fsm11 : 1; + uint8_t int1_fsm12 : 1; + uint8_t int1_fsm13 : 1; + uint8_t int1_fsm14 : 1; + uint8_t int1_fsm15 : 1; + uint8_t int1_fsm16 : 1; +} lsm6dsox_fsm_int1_b_t; + +#define LSM6DSOX_MLC_INT1 0x0DU +typedef struct { + uint8_t int1_mlc1 : 1; + uint8_t int1_mlc2 : 1; + uint8_t int1_mlc3 : 1; + uint8_t int1_mlc4 : 1; + uint8_t int1_mlc5 : 1; + uint8_t int1_mlc6 : 1; + uint8_t int1_mlc7 : 1; + uint8_t int1_mlc8 : 1; +} lsm6dsox_mlc_int1_t; + +#define LSM6DSOX_EMB_FUNC_INT2 0x0EU +typedef struct { + uint8_t not_used_01 : 3; + uint8_t int2_step_detector : 1; + uint8_t int2_tilt : 1; + uint8_t int2_sig_mot : 1; + uint8_t not_used_02 : 1; + uint8_t int2_fsm_lc : 1; +} lsm6dsox_emb_func_int2_t; + +#define LSM6DSOX_FSM_INT2_A 0x0FU +typedef struct { + uint8_t int2_fsm1 : 1; + uint8_t int2_fsm2 : 1; + uint8_t int2_fsm3 : 1; + uint8_t int2_fsm4 : 1; + uint8_t int2_fsm5 : 1; + uint8_t int2_fsm6 : 1; + uint8_t int2_fsm7 : 1; + uint8_t int2_fsm8 : 1; +} lsm6dsox_fsm_int2_a_t; + +#define LSM6DSOX_FSM_INT2_B 0x10U +typedef struct { + uint8_t int2_fsm9 : 1; + uint8_t int2_fsm10 : 1; + uint8_t int2_fsm11 : 1; + uint8_t int2_fsm12 : 1; + uint8_t int2_fsm13 : 1; + uint8_t int2_fsm14 : 1; + uint8_t int2_fsm15 : 1; + uint8_t int2_fsm16 : 1; +} lsm6dsox_fsm_int2_b_t; + +#define LSM6DSOX_MLC_INT2 0x11U +typedef struct { + uint8_t int2_mlc1 : 1; + uint8_t int2_mlc2 : 1; + uint8_t int2_mlc3 : 1; + uint8_t int2_mlc4 : 1; + uint8_t int2_mlc5 : 1; + uint8_t int2_mlc6 : 1; + uint8_t int2_mlc7 : 1; + uint8_t int2_mlc8 : 1; +} lsm6dsox_mlc_int2_t; + +#define LSM6DSOX_EMB_FUNC_STATUS 0x12U +typedef struct { + uint8_t not_used_01 : 3; + uint8_t is_step_det : 1; + uint8_t is_tilt : 1; + uint8_t is_sigmot : 1; + uint8_t not_used_02 : 1; + uint8_t is_fsm_lc : 1; +} lsm6dsox_emb_func_status_t; + +#define LSM6DSOX_FSM_STATUS_A 0x13U +typedef struct { + uint8_t is_fsm1 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm8 : 1; +} lsm6dsox_fsm_status_a_t; + +#define LSM6DSOX_FSM_STATUS_B 0x14U +typedef struct { + uint8_t is_fsm9 : 1; + uint8_t is_fsm10 : 1; + uint8_t is_fsm11 : 1; + uint8_t is_fsm12 : 1; + uint8_t is_fsm13 : 1; + uint8_t is_fsm14 : 1; + uint8_t is_fsm15 : 1; + uint8_t is_fsm16 : 1; +} lsm6dsox_fsm_status_b_t; + +#define LSM6DSOX_MLC_STATUS 0x15U +typedef struct { + uint8_t is_mlc1 : 1; + uint8_t is_mlc2 : 1; + uint8_t is_mlc3 : 1; + uint8_t is_mlc4 : 1; + uint8_t is_mlc5 : 1; + uint8_t is_mlc6 : 1; + uint8_t is_mlc7 : 1; + uint8_t is_mlc8 : 1; +} lsm6dsox_mlc_status_t; + +#define LSM6DSOX_PAGE_RW 0x17U +typedef struct { + uint8_t not_used_01 : 5; + uint8_t page_rw : 2; /* page_write + page_read */ + uint8_t emb_func_lir : 1; +} lsm6dsox_page_rw_t; + +#define LSM6DSOX_EMB_FUNC_FIFO_CFG 0x44U +typedef struct { + uint8_t not_used_00 : 6; + uint8_t pedo_fifo_en : 1; + uint8_t not_used_01 : 1; +} lsm6dsox_emb_func_fifo_cfg_t; + +#define LSM6DSOX_FSM_ENABLE_A 0x46U +typedef struct { + uint8_t fsm1_en : 1; + uint8_t fsm2_en : 1; + uint8_t fsm3_en : 1; + uint8_t fsm4_en : 1; + uint8_t fsm5_en : 1; + uint8_t fsm6_en : 1; + uint8_t fsm7_en : 1; + uint8_t fsm8_en : 1; +} lsm6dsox_fsm_enable_a_t; + +#define LSM6DSOX_FSM_ENABLE_B 0x47U +typedef struct { + uint8_t fsm9_en : 1; + uint8_t fsm10_en : 1; + uint8_t fsm11_en : 1; + uint8_t fsm12_en : 1; + uint8_t fsm13_en : 1; + uint8_t fsm14_en : 1; + uint8_t fsm15_en : 1; + uint8_t fsm16_en : 1; +} lsm6dsox_fsm_enable_b_t; + +#define LSM6DSOX_FSM_LONG_COUNTER_L 0x48U +#define LSM6DSOX_FSM_LONG_COUNTER_H 0x49U +#define LSM6DSOX_FSM_LONG_COUNTER_CLEAR 0x4AU +typedef struct { + uint8_t fsm_lc_clr : 2; /* fsm_lc_cleared + fsm_lc_clear */ + uint8_t not_used_01 : 6; +} lsm6dsox_fsm_long_counter_clear_t; + +#define LSM6DSOX_FSM_OUTS1 0x4CU +typedef struct { + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +} lsm6dsox_fsm_outs1_t; + +#define LSM6DSOX_FSM_OUTS2 0x4DU +typedef struct { + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +} lsm6dsox_fsm_outs2_t; + +#define LSM6DSOX_FSM_OUTS3 0x4EU +typedef struct { + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +} lsm6dsox_fsm_outs3_t; + +#define LSM6DSOX_FSM_OUTS4 0x4FU +typedef struct { + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +} lsm6dsox_fsm_outs4_t; + +#define LSM6DSOX_FSM_OUTS5 0x50U +typedef struct { + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +} lsm6dsox_fsm_outs5_t; + +#define LSM6DSOX_FSM_OUTS6 0x51U +typedef struct { + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +} lsm6dsox_fsm_outs6_t; + +#define LSM6DSOX_FSM_OUTS7 0x52U +typedef struct { + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +} lsm6dsox_fsm_outs7_t; + +#define LSM6DSOX_FSM_OUTS8 0x53U +typedef struct { + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +} lsm6dsox_fsm_outs8_t; + +#define LSM6DSOX_FSM_OUTS9 0x54U +typedef struct { + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +} lsm6dsox_fsm_outs9_t; + +#define LSM6DSOX_FSM_OUTS10 0x55U +typedef struct { + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +} lsm6dsox_fsm_outs10_t; + +#define LSM6DSOX_FSM_OUTS11 0x56U +typedef struct { + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +} lsm6dsox_fsm_outs11_t; + +#define LSM6DSOX_FSM_OUTS12 0x57U +typedef struct { + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +} lsm6dsox_fsm_outs12_t; + +#define LSM6DSOX_FSM_OUTS13 0x58U +typedef struct { + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +} lsm6dsox_fsm_outs13_t; + +#define LSM6DSOX_FSM_OUTS14 0x59U +typedef struct { + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +} lsm6dsox_fsm_outs14_t; + +#define LSM6DSOX_FSM_OUTS15 0x5AU +typedef struct { + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +} lsm6dsox_fsm_outs15_t; + +#define LSM6DSOX_FSM_OUTS16 0x5BU +typedef struct { + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +} lsm6dsox_fsm_outs16_t; + +#define LSM6DSOX_EMB_FUNC_ODR_CFG_B 0x5FU +typedef struct { + uint8_t not_used_01 : 3; + uint8_t fsm_odr : 2; + uint8_t not_used_02 : 3; +} lsm6dsox_emb_func_odr_cfg_b_t; + +#define LSM6DSOX_EMB_FUNC_ODR_CFG_C 0x60U +typedef struct { + uint8_t not_used_01 : 4; + uint8_t mlc_odr : 2; + uint8_t not_used_02 : 2; +} lsm6dsox_emb_func_odr_cfg_c_t; + +#define LSM6DSOX_STEP_COUNTER_L 0x62U +#define LSM6DSOX_STEP_COUNTER_H 0x63U +#define LSM6DSOX_EMB_FUNC_SRC 0x64U +typedef struct { + uint8_t not_used_01 : 2; + uint8_t stepcounter_bit_set : 1; + uint8_t step_overflow : 1; + uint8_t step_count_delta_ia : 1; + uint8_t step_detected : 1; + uint8_t not_used_02 : 1; + uint8_t pedo_rst_step : 1; +} lsm6dsox_emb_func_src_t; + +#define LSM6DSOX_EMB_FUNC_INIT_A 0x66U +typedef struct { + uint8_t not_used_01 : 3; + uint8_t step_det_init : 1; + uint8_t tilt_init : 1; + uint8_t sig_mot_init : 1; + uint8_t not_used_02 : 2; +} lsm6dsox_emb_func_init_a_t; + +#define LSM6DSOX_EMB_FUNC_INIT_B 0x67U +typedef struct { + uint8_t fsm_init : 1; + uint8_t not_used_01 : 2; + uint8_t fifo_compr_init : 1; + uint8_t not_used_02 : 4; +} lsm6dsox_emb_func_init_b_t; + +#define LSM6DSOX_MLC0_SRC 0x70U +#define LSM6DSOX_MLC1_SRC 0x71U +#define LSM6DSOX_MLC2_SRC 0x72U +#define LSM6DSOX_MLC3_SRC 0x73U +#define LSM6DSOX_MLC4_SRC 0x74U +#define LSM6DSOX_MLC5_SRC 0x75U +#define LSM6DSOX_MLC6_SRC 0x76U +#define LSM6DSOX_MLC7_SRC 0x77U +#define LSM6DSOX_MAG_SENSITIVITY_L 0xBAU +#define LSM6DSOX_MAG_SENSITIVITY_H 0xBBU +#define LSM6DSOX_MAG_OFFX_L 0xC0U +#define LSM6DSOX_MAG_OFFX_H 0xC1U +#define LSM6DSOX_MAG_OFFY_L 0xC2U +#define LSM6DSOX_MAG_OFFY_H 0xC3U +#define LSM6DSOX_MAG_OFFZ_L 0xC4U +#define LSM6DSOX_MAG_OFFZ_H 0xC5U +#define LSM6DSOX_MAG_SI_XX_L 0xC6U +#define LSM6DSOX_MAG_SI_XX_H 0xC7U +#define LSM6DSOX_MAG_SI_XY_L 0xC8U +#define LSM6DSOX_MAG_SI_XY_H 0xC9U +#define LSM6DSOX_MAG_SI_XZ_L 0xCAU +#define LSM6DSOX_MAG_SI_XZ_H 0xCBU +#define LSM6DSOX_MAG_SI_YY_L 0xCCU +#define LSM6DSOX_MAG_SI_YY_H 0xCDU +#define LSM6DSOX_MAG_SI_YZ_L 0xCEU +#define LSM6DSOX_MAG_SI_YZ_H 0xCFU +#define LSM6DSOX_MAG_SI_ZZ_L 0xD0U +#define LSM6DSOX_MAG_SI_ZZ_H 0xD1U +#define LSM6DSOX_MAG_CFG_A 0xD4U +typedef struct { + uint8_t mag_z_axis : 3; + uint8_t not_used_01 : 1; + uint8_t mag_y_axis : 3; + uint8_t not_used_02 : 1; +} lsm6dsox_mag_cfg_a_t; + +#define LSM6DSOX_MAG_CFG_B 0xD5U +typedef struct { + uint8_t mag_x_axis : 3; + uint8_t not_used_01 : 5; +} lsm6dsox_mag_cfg_b_t; + +#define LSM6DSOX_FSM_LC_TIMEOUT_L 0x17AU +#define LSM6DSOX_FSM_LC_TIMEOUT_H 0x17BU +#define LSM6DSOX_FSM_PROGRAMS 0x17CU +#define LSM6DSOX_FSM_START_ADD_L 0x17EU +#define LSM6DSOX_FSM_START_ADD_H 0x17FU +#define LSM6DSOX_PEDO_CMD_REG 0x183U +typedef struct { + uint8_t ad_det_en : 1; + uint8_t not_used_01 : 1; + uint8_t fp_rejection_en : 1; + uint8_t carry_count_en : 1; + uint8_t not_used_02 : 4; +} lsm6dsox_pedo_cmd_reg_t; + +#define LSM6DSOX_PEDO_DEB_STEPS_CONF 0x184U +#define LSM6DSOX_PEDO_SC_DELTAT_L 0x1D0U +#define LSM6DSOX_PEDO_SC_DELTAT_H 0x1D1U + +#define LSM6DSOX_MLC_MAG_SENSITIVITY_L 0x1E8U +#define LSM6DSOX_MLC_MAG_SENSITIVITY_H 0x1E9U + +#define LSM6DSOX_SENSOR_HUB_1 0x02U +typedef struct { + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +} lsm6dsox_sensor_hub_1_t; + +#define LSM6DSOX_SENSOR_HUB_2 0x03U +typedef struct { + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +} lsm6dsox_sensor_hub_2_t; + +#define LSM6DSOX_SENSOR_HUB_3 0x04U +typedef struct { + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +} lsm6dsox_sensor_hub_3_t; + +#define LSM6DSOX_SENSOR_HUB_4 0x05U +typedef struct { + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +} lsm6dsox_sensor_hub_4_t; + +#define LSM6DSOX_SENSOR_HUB_5 0x06U +typedef struct { + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +} lsm6dsox_sensor_hub_5_t; + +#define LSM6DSOX_SENSOR_HUB_6 0x07U +typedef struct { + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +} lsm6dsox_sensor_hub_6_t; + +#define LSM6DSOX_SENSOR_HUB_7 0x08U +typedef struct { + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +} lsm6dsox_sensor_hub_7_t; + +#define LSM6DSOX_SENSOR_HUB_8 0x09U +typedef struct { + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +} lsm6dsox_sensor_hub_8_t; + +#define LSM6DSOX_SENSOR_HUB_9 0x0AU +typedef struct { + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +} lsm6dsox_sensor_hub_9_t; + +#define LSM6DSOX_SENSOR_HUB_10 0x0BU +typedef struct { + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +} lsm6dsox_sensor_hub_10_t; + +#define LSM6DSOX_SENSOR_HUB_11 0x0CU +typedef struct { + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +} lsm6dsox_sensor_hub_11_t; + +#define LSM6DSOX_SENSOR_HUB_12 0x0DU +typedef struct { + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +} lsm6dsox_sensor_hub_12_t; + +#define LSM6DSOX_SENSOR_HUB_13 0x0EU +typedef struct { + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +} lsm6dsox_sensor_hub_13_t; + +#define LSM6DSOX_SENSOR_HUB_14 0x0FU +typedef struct { + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +} lsm6dsox_sensor_hub_14_t; + +#define LSM6DSOX_SENSOR_HUB_15 0x10U +typedef struct { + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +} lsm6dsox_sensor_hub_15_t; + +#define LSM6DSOX_SENSOR_HUB_16 0x11U +typedef struct { + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +} lsm6dsox_sensor_hub_16_t; + +#define LSM6DSOX_SENSOR_HUB_17 0x12U +typedef struct { + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +} lsm6dsox_sensor_hub_17_t; + +#define LSM6DSOX_SENSOR_HUB_18 0x13U +typedef struct { + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +} lsm6dsox_sensor_hub_18_t; + +#define LSM6DSOX_MASTER_CONFIG 0x14U +typedef struct { + uint8_t aux_sens_on : 2; + uint8_t master_on : 1; + uint8_t shub_pu_en : 1; + uint8_t pass_through_mode : 1; + uint8_t start_config : 1; + uint8_t write_once : 1; + uint8_t rst_master_regs : 1; +} lsm6dsox_master_config_t; + +#define LSM6DSOX_SLV0_ADD 0x15U +typedef struct { + uint8_t rw_0 : 1; + uint8_t slave0 : 7; +} lsm6dsox_slv0_add_t; + +#define LSM6DSOX_SLV0_SUBADD 0x16U +typedef struct { + uint8_t slave0_reg : 8; +} lsm6dsox_slv0_subadd_t; + +#define LSM6DSOX_SLV0_CONFIG 0x17U +typedef struct { + uint8_t slave0_numop : 3; + uint8_t batch_ext_sens_0_en : 1; + uint8_t not_used_01 : 2; + uint8_t shub_odr : 2; +} lsm6dsox_slv0_config_t; + +#define LSM6DSOX_SLV1_ADD 0x18U +typedef struct { + uint8_t r_1 : 1; + uint8_t slave1_add : 7; +} lsm6dsox_slv1_add_t; + +#define LSM6DSOX_SLV1_SUBADD 0x19U +typedef struct { + uint8_t slave1_reg : 8; +} lsm6dsox_slv1_subadd_t; + +#define LSM6DSOX_SLV1_CONFIG 0x1AU +typedef struct { + uint8_t slave1_numop : 3; + uint8_t batch_ext_sens_1_en : 1; + uint8_t not_used_01 : 4; +} lsm6dsox_slv1_config_t; + +#define LSM6DSOX_SLV2_ADD 0x1BU +typedef struct { + uint8_t r_2 : 1; + uint8_t slave2_add : 7; +} lsm6dsox_slv2_add_t; + +#define LSM6DSOX_SLV2_SUBADD 0x1CU +typedef struct { + uint8_t slave2_reg : 8; +} lsm6dsox_slv2_subadd_t; + +#define LSM6DSOX_SLV2_CONFIG 0x1DU +typedef struct { + uint8_t slave2_numop : 3; + uint8_t batch_ext_sens_2_en : 1; + uint8_t not_used_01 : 4; +} lsm6dsox_slv2_config_t; + +#define LSM6DSOX_SLV3_ADD 0x1EU +typedef struct { + uint8_t r_3 : 1; + uint8_t slave3_add : 7; +} lsm6dsox_slv3_add_t; + +#define LSM6DSOX_SLV3_SUBADD 0x1FU +typedef struct { + uint8_t slave3_reg : 8; +} lsm6dsox_slv3_subadd_t; + +#define LSM6DSOX_SLV3_CONFIG 0x20U +typedef struct { + uint8_t slave3_numop : 3; + uint8_t batch_ext_sens_3_en : 1; + uint8_t not_used_01 : 4; +} lsm6dsox_slv3_config_t; + +#define LSM6DSOX_DATAWRITE_SLV0 0x21U +typedef struct { + uint8_t slave0_dataw : 8; +} lsm6dsox_datawrite_slv0_t; + +#define LSM6DSOX_STATUS_MASTER 0x22U +typedef struct { + uint8_t sens_hub_endop : 1; + uint8_t not_used_01 : 2; + uint8_t slave0_nack : 1; + uint8_t slave1_nack : 1; + uint8_t slave2_nack : 1; + uint8_t slave3_nack : 1; + uint8_t wr_once_done : 1; +} lsm6dsox_status_master_t; + +#define LSM6DSOX_START_FSM_ADD 0x0400U + +/** + * @defgroup LSM6DSOX_Register_Union + * @brief This union group all the registers that has a bitfield + * description. + * This union is useful but not need by the driver. + * + * REMOVING this union you are compliant with: + * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " + * + * @{ + * + */ +typedef union{ + lsm6dsox_func_cfg_access_t func_cfg_access; + lsm6dsox_pin_ctrl_t pin_ctrl; + lsm6dsox_s4s_tph_l_t s4s_tph_l; + lsm6dsox_s4s_tph_h_t s4s_tph_h; + lsm6dsox_s4s_rr_t s4s_rr; + lsm6dsox_fifo_ctrl1_t fifo_ctrl1; + lsm6dsox_fifo_ctrl2_t fifo_ctrl2; + lsm6dsox_fifo_ctrl3_t fifo_ctrl3; + lsm6dsox_fifo_ctrl4_t fifo_ctrl4; + lsm6dsox_counter_bdr_reg1_t counter_bdr_reg1; + lsm6dsox_counter_bdr_reg2_t counter_bdr_reg2; + lsm6dsox_int1_ctrl_t int1_ctrl; + lsm6dsox_int2_ctrl_t int2_ctrl; + lsm6dsox_ctrl1_xl_t ctrl1_xl; + lsm6dsox_ctrl2_g_t ctrl2_g; + lsm6dsox_ctrl3_c_t ctrl3_c; + lsm6dsox_ctrl4_c_t ctrl4_c; + lsm6dsox_ctrl5_c_t ctrl5_c; + lsm6dsox_ctrl6_c_t ctrl6_c; + lsm6dsox_ctrl7_g_t ctrl7_g; + lsm6dsox_ctrl8_xl_t ctrl8_xl; + lsm6dsox_ctrl9_xl_t ctrl9_xl; + lsm6dsox_ctrl10_c_t ctrl10_c; + lsm6dsox_all_int_src_t all_int_src; + lsm6dsox_wake_up_src_t wake_up_src; + lsm6dsox_tap_src_t tap_src; + lsm6dsox_d6d_src_t d6d_src; + lsm6dsox_status_reg_t status_reg; + lsm6dsox_fifo_status1_t fifo_status1; + lsm6dsox_fifo_status2_t fifo_status2; + lsm6dsox_ui_status_reg_ois_t ui_status_reg_ois; + lsm6dsox_tap_cfg0_t tap_cfg0; + lsm6dsox_tap_cfg1_t tap_cfg1; + lsm6dsox_tap_cfg2_t tap_cfg2; + lsm6dsox_tap_ths_6d_t tap_ths_6d; + lsm6dsox_int_dur2_t int_dur2; + lsm6dsox_wake_up_ths_t wake_up_ths; + lsm6dsox_wake_up_dur_t wake_up_dur; + lsm6dsox_free_fall_t free_fall; + lsm6dsox_md1_cfg_t md1_cfg; + lsm6dsox_md2_cfg_t md2_cfg; + lsm6dsox_s4s_st_cmd_code_t s4s_st_cmd_code; + lsm6dsox_s4s_dt_reg_t s4s_dt_reg; + lsm6dsox_i3c_bus_avb_t i3c_bus_avb; + lsm6dsox_internal_freq_fine_t internal_freq_fine; + lsm6dsox_ui_int_ois_t ui_int_ois; + lsm6dsox_ui_ctrl1_ois_t ui_ctrl1_ois; + lsm6dsox_ui_ctrl2_ois_t ui_ctrl2_ois; + lsm6dsox_ui_ctrl3_ois_t ui_ctrl3_ois; + lsm6dsox_fifo_data_out_tag_t fifo_data_out_tag; + lsm6dsox_spi2_status_reg_ois_t spi2_status_reg_ois; + lsm6dsox_spi2_int_ois_t spi2_int_ois; + lsm6dsox_spi2_ctrl1_ois_t spi2_ctrl1_ois; + lsm6dsox_spi2_ctrl2_ois_t spi2_ctrl2_ois; + lsm6dsox_spi2_ctrl3_ois_t spi2_ctrl3_ois; + lsm6dsox_page_sel_t page_sel; + lsm6dsox_emb_func_en_a_t emb_func_en_a; + lsm6dsox_emb_func_en_b_t emb_func_en_b; + lsm6dsox_page_address_t page_address; + lsm6dsox_page_value_t page_value; + lsm6dsox_emb_func_int1_t emb_func_int1; + lsm6dsox_fsm_int1_a_t fsm_int1_a; + lsm6dsox_fsm_int1_b_t fsm_int1_b; + lsm6dsox_emb_func_int2_t emb_func_int2; + lsm6dsox_fsm_int2_a_t fsm_int2_a; + lsm6dsox_fsm_int2_b_t fsm_int2_b; + lsm6dsox_emb_func_status_t emb_func_status; + lsm6dsox_fsm_status_a_t fsm_status_a; + lsm6dsox_fsm_status_b_t fsm_status_b; + lsm6dsox_page_rw_t page_rw; + lsm6dsox_emb_func_fifo_cfg_t emb_func_fifo_cfg; + lsm6dsox_fsm_enable_a_t fsm_enable_a; + lsm6dsox_fsm_enable_b_t fsm_enable_b; + lsm6dsox_fsm_long_counter_clear_t fsm_long_counter_clear; + lsm6dsox_fsm_outs1_t fsm_outs1; + lsm6dsox_fsm_outs2_t fsm_outs2; + lsm6dsox_fsm_outs3_t fsm_outs3; + lsm6dsox_fsm_outs4_t fsm_outs4; + lsm6dsox_fsm_outs5_t fsm_outs5; + lsm6dsox_fsm_outs6_t fsm_outs6; + lsm6dsox_fsm_outs7_t fsm_outs7; + lsm6dsox_fsm_outs8_t fsm_outs8; + lsm6dsox_fsm_outs9_t fsm_outs9; + lsm6dsox_fsm_outs10_t fsm_outs10; + lsm6dsox_fsm_outs11_t fsm_outs11; + lsm6dsox_fsm_outs12_t fsm_outs12; + lsm6dsox_fsm_outs13_t fsm_outs13; + lsm6dsox_fsm_outs14_t fsm_outs14; + lsm6dsox_fsm_outs15_t fsm_outs15; + lsm6dsox_fsm_outs16_t fsm_outs16; + lsm6dsox_emb_func_odr_cfg_b_t emb_func_odr_cfg_b; + lsm6dsox_emb_func_odr_cfg_c_t emb_func_odr_cfg_c; + lsm6dsox_emb_func_src_t emb_func_src; + lsm6dsox_emb_func_init_a_t emb_func_init_a; + lsm6dsox_emb_func_init_b_t emb_func_init_b; + lsm6dsox_mag_cfg_a_t mag_cfg_a; + lsm6dsox_mag_cfg_b_t mag_cfg_b; + lsm6dsox_pedo_cmd_reg_t pedo_cmd_reg; + lsm6dsox_sensor_hub_1_t sensor_hub_1; + lsm6dsox_sensor_hub_2_t sensor_hub_2; + lsm6dsox_sensor_hub_3_t sensor_hub_3; + lsm6dsox_sensor_hub_4_t sensor_hub_4; + lsm6dsox_sensor_hub_5_t sensor_hub_5; + lsm6dsox_sensor_hub_6_t sensor_hub_6; + lsm6dsox_sensor_hub_7_t sensor_hub_7; + lsm6dsox_sensor_hub_8_t sensor_hub_8; + lsm6dsox_sensor_hub_9_t sensor_hub_9; + lsm6dsox_sensor_hub_10_t sensor_hub_10; + lsm6dsox_sensor_hub_11_t sensor_hub_11; + lsm6dsox_sensor_hub_12_t sensor_hub_12; + lsm6dsox_sensor_hub_13_t sensor_hub_13; + lsm6dsox_sensor_hub_14_t sensor_hub_14; + lsm6dsox_sensor_hub_15_t sensor_hub_15; + lsm6dsox_sensor_hub_16_t sensor_hub_16; + lsm6dsox_sensor_hub_17_t sensor_hub_17; + lsm6dsox_sensor_hub_18_t sensor_hub_18; + lsm6dsox_master_config_t master_config; + lsm6dsox_slv0_add_t slv0_add; + lsm6dsox_slv0_subadd_t slv0_subadd; + lsm6dsox_slv0_config_t slv0_config; + lsm6dsox_slv1_add_t slv1_add; + lsm6dsox_slv1_subadd_t slv1_subadd; + lsm6dsox_slv1_config_t slv1_config; + lsm6dsox_slv2_add_t slv2_add; + lsm6dsox_slv2_subadd_t slv2_subadd; + lsm6dsox_slv2_config_t slv2_config; + lsm6dsox_slv3_add_t slv3_add; + lsm6dsox_slv3_subadd_t slv3_subadd; + lsm6dsox_slv3_config_t slv3_config; + lsm6dsox_datawrite_slv0_t datawrite_slv0; + lsm6dsox_status_master_t status_master; + bitwise_t bitwise; + uint8_t byte; +} lsm6dsox_reg_t; + +/** + * @} + * + */ + +int32_t lsm6dsox_read_reg(lsm6dsox_ctx_t *ctx, uint8_t reg, uint8_t* data, + uint16_t len); +int32_t lsm6dsox_write_reg(lsm6dsox_ctx_t *ctx, uint8_t reg, uint8_t* data, + uint16_t len); + +extern float_t lsm6dsox_from_fs2_to_mg(int16_t lsb); +extern float_t lsm6dsox_from_fs4_to_mg(int16_t lsb); +extern float_t lsm6dsox_from_fs8_to_mg(int16_t lsb); +extern float_t lsm6dsox_from_fs16_to_mg(int16_t lsb); +extern float_t lsm6dsox_from_fs125_to_mdps(int16_t lsb); +extern float_t lsm6dsox_from_fs500_to_mdps(int16_t lsb); +extern float_t lsm6dsox_from_fs250_to_mdps(int16_t lsb); +extern float_t lsm6dsox_from_fs1000_to_mdps(int16_t lsb); +extern float_t lsm6dsox_from_fs2000_to_mdps(int16_t lsb); +extern float_t lsm6dsox_from_lsb_to_celsius(int16_t lsb); +extern float_t lsm6dsox_from_lsb_to_nsec(int16_t lsb); + +typedef enum { + LSM6DSOX_2g = 0, + LSM6DSOX_16g = 1, /* if XL_FS_MODE = ‘1’ -> LSM6DSOX_2g */ + LSM6DSOX_4g = 2, + LSM6DSOX_8g = 3, +} lsm6dsox_fs_xl_t; +int32_t lsm6dsox_xl_full_scale_set(lsm6dsox_ctx_t *ctx, lsm6dsox_fs_xl_t val); +int32_t lsm6dsox_xl_full_scale_get(lsm6dsox_ctx_t *ctx, lsm6dsox_fs_xl_t *val); + +typedef enum { + LSM6DSOX_XL_ODR_OFF = 0, + LSM6DSOX_XL_ODR_12Hz5 = 1, + LSM6DSOX_XL_ODR_26Hz = 2, + LSM6DSOX_XL_ODR_52Hz = 3, + LSM6DSOX_XL_ODR_104Hz = 4, + LSM6DSOX_XL_ODR_208Hz = 5, + LSM6DSOX_XL_ODR_417Hz = 6, + LSM6DSOX_XL_ODR_833Hz = 7, + LSM6DSOX_XL_ODR_1667Hz = 8, + LSM6DSOX_XL_ODR_3333Hz = 9, + LSM6DSOX_XL_ODR_6667Hz = 10, + LSM6DSOX_XL_ODR_6Hz5 = 11, /* (low power only) */ +} lsm6dsox_odr_xl_t; +int32_t lsm6dsox_xl_data_rate_set(lsm6dsox_ctx_t *ctx, lsm6dsox_odr_xl_t val); +int32_t lsm6dsox_xl_data_rate_get(lsm6dsox_ctx_t *ctx, lsm6dsox_odr_xl_t *val); + +typedef enum { + LSM6DSOX_250dps = 0, + LSM6DSOX_125dps = 1, + LSM6DSOX_500dps = 2, + LSM6DSOX_1000dps = 4, + LSM6DSOX_2000dps = 6, +} lsm6dsox_fs_g_t; +int32_t lsm6dsox_gy_full_scale_set(lsm6dsox_ctx_t *ctx, lsm6dsox_fs_g_t val); +int32_t lsm6dsox_gy_full_scale_get(lsm6dsox_ctx_t *ctx, lsm6dsox_fs_g_t *val); + +typedef enum { + LSM6DSOX_GY_ODR_OFF = 0, + LSM6DSOX_GY_ODR_12Hz5 = 1, + LSM6DSOX_GY_ODR_26Hz = 2, + LSM6DSOX_GY_ODR_52Hz = 3, + LSM6DSOX_GY_ODR_104Hz = 4, + LSM6DSOX_GY_ODR_208Hz = 5, + LSM6DSOX_GY_ODR_417Hz = 6, + LSM6DSOX_GY_ODR_833Hz = 7, + LSM6DSOX_GY_ODR_1667Hz = 8, + LSM6DSOX_GY_ODR_3333Hz = 9, + LSM6DSOX_GY_ODR_6667Hz = 10, +} lsm6dsox_odr_g_t; +int32_t lsm6dsox_gy_data_rate_set(lsm6dsox_ctx_t *ctx, lsm6dsox_odr_g_t val); +int32_t lsm6dsox_gy_data_rate_get(lsm6dsox_ctx_t *ctx, lsm6dsox_odr_g_t *val); + +int32_t lsm6dsox_block_data_update_set(lsm6dsox_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_block_data_update_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +typedef enum { + LSM6DSOX_LSb_1mg = 0, + LSM6DSOX_LSb_16mg = 1, +} lsm6dsox_usr_off_w_t; +int32_t lsm6dsox_xl_offset_weight_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_usr_off_w_t val); +int32_t lsm6dsox_xl_offset_weight_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_usr_off_w_t *val); + +typedef enum { + LSM6DSOX_HIGH_PERFORMANCE_MD = 0, + LSM6DSOX_LOW_NORMAL_POWER_MD = 1, + LSM6DSOX_ULTRA_LOW_POWER_MD = 2, +} lsm6dsox_xl_hm_mode_t; +int32_t lsm6dsox_xl_power_mode_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_xl_hm_mode_t val); +int32_t lsm6dsox_xl_power_mode_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_xl_hm_mode_t *val); + +typedef enum { + LSM6DSOX_GY_HIGH_PERFORMANCE = 0, + LSM6DSOX_GY_NORMAL = 1, +} lsm6dsox_g_hm_mode_t; +int32_t lsm6dsox_gy_power_mode_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_g_hm_mode_t val); +int32_t lsm6dsox_gy_power_mode_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_g_hm_mode_t *val); + +typedef struct { + lsm6dsox_all_int_src_t all_int_src; + lsm6dsox_wake_up_src_t wake_up_src; + lsm6dsox_tap_src_t tap_src; + lsm6dsox_d6d_src_t d6d_src; + lsm6dsox_status_reg_t status_reg; + lsm6dsox_emb_func_status_t emb_func_status; + lsm6dsox_fsm_status_a_t fsm_status_a; + lsm6dsox_fsm_status_b_t fsm_status_b; + lsm6dsox_mlc_status_mainpage_t mlc_status; +} lsm6dsox_all_sources_t; +int32_t lsm6dsox_all_sources_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_all_sources_t *val); + +int32_t lsm6dsox_status_reg_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_status_reg_t *val); + +int32_t lsm6dsox_xl_flag_data_ready_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsox_gy_flag_data_ready_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsox_temp_flag_data_ready_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsox_xl_usr_offset_x_set(lsm6dsox_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dsox_xl_usr_offset_x_get(lsm6dsox_ctx_t *ctx, uint8_t *buff); + +int32_t lsm6dsox_xl_usr_offset_y_set(lsm6dsox_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dsox_xl_usr_offset_y_get(lsm6dsox_ctx_t *ctx, uint8_t *buff); + +int32_t lsm6dsox_xl_usr_offset_z_set(lsm6dsox_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dsox_xl_usr_offset_z_get(lsm6dsox_ctx_t *ctx, uint8_t *buff); + +int32_t lsm6dsox_xl_usr_offset_set(lsm6dsox_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_xl_usr_offset_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsox_timestamp_set(lsm6dsox_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_timestamp_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsox_timestamp_raw_get(lsm6dsox_ctx_t *ctx, uint8_t *buff); + +typedef enum { + LSM6DSOX_NO_ROUND = 0, + LSM6DSOX_ROUND_XL = 1, + LSM6DSOX_ROUND_GY = 2, + LSM6DSOX_ROUND_GY_XL = 3, +} lsm6dsox_rounding_t; +int32_t lsm6dsox_rounding_mode_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_rounding_t val); +int32_t lsm6dsox_rounding_mode_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_rounding_t *val); + +typedef enum { + LSM6DSOX_STAT_RND_DISABLE = 0, + LSM6DSOX_STAT_RND_ENABLE = 1, +} lsm6dsox_rounding_status_t; +int32_t lsm6dsox_rounding_on_status_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_rounding_status_t val); +int32_t lsm6dsox_rounding_on_status_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_rounding_status_t *val); + +int32_t lsm6dsox_temperature_raw_get(lsm6dsox_ctx_t *ctx, uint8_t *buff); + +int32_t lsm6dsox_angular_rate_raw_get(lsm6dsox_ctx_t *ctx, uint8_t *buff); + +int32_t lsm6dsox_acceleration_raw_get(lsm6dsox_ctx_t *ctx, uint8_t *buff); + +int32_t lsm6dsox_fifo_out_raw_get(lsm6dsox_ctx_t *ctx, uint8_t *buff); + +int32_t lsm6dsox_ois_angular_rate_raw_get(lsm6dsox_ctx_t *ctx, uint8_t *buff); + +int32_t lsm6dsox_ois_acceleration_raw_get(lsm6dsox_ctx_t *ctx, uint8_t *buff); + +int32_t lsm6dsox_aux_temperature_raw_get(lsm6dsox_ctx_t *ctx, uint8_t *buff); + +int32_t lsm6dsox_aux_ois_angular_rate_raw_get(lsm6dsox_ctx_t *ctx, uint8_t *buff); + +int32_t lsm6dsox_aux_ois_acceleration_raw_get(lsm6dsox_ctx_t *ctx, uint8_t *buff); + +int32_t lsm6dsox_number_of_steps_get(lsm6dsox_ctx_t *ctx, uint8_t *buff); + +int32_t lsm6dsox_steps_reset(lsm6dsox_ctx_t *ctx); + +int32_t lsm6dsox_mlc_out_get(lsm6dsox_ctx_t *ctx, uint8_t *buff); + +int32_t lsm6dsox_odr_cal_reg_set(lsm6dsox_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_odr_cal_reg_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +typedef enum { + LSM6DSOX_USER_BANK = 0, + LSM6DSOX_SENSOR_HUB_BANK = 1, + LSM6DSOX_EMBEDDED_FUNC_BANK = 2, +} lsm6dsox_reg_access_t; +int32_t lsm6dsox_mem_bank_set(lsm6dsox_ctx_t *ctx, lsm6dsox_reg_access_t val); +int32_t lsm6dsox_mem_bank_get(lsm6dsox_ctx_t *ctx, lsm6dsox_reg_access_t *val); + +int32_t lsm6dsox_ln_pg_write_byte(lsm6dsox_ctx_t *ctx, uint16_t address, + uint8_t *val); +int32_t lsm6dsox_ln_pg_read_byte(lsm6dsox_ctx_t *ctx, uint16_t address, + uint8_t *val); + +int32_t lsm6dsox_ln_pg_write(lsm6dsox_ctx_t *ctx, uint16_t address, + uint8_t *buf, uint8_t len); +int32_t lsm6dsox_ln_pg_read(lsm6dsox_ctx_t *ctx, uint16_t address, + uint8_t *val); + +typedef enum { + LSM6DSOX_DRDY_LATCHED = 0, + LSM6DSOX_DRDY_PULSED = 1, +} lsm6dsox_dataready_pulsed_t; +int32_t lsm6dsox_data_ready_mode_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_dataready_pulsed_t val); +int32_t lsm6dsox_data_ready_mode_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_dataready_pulsed_t *val); + +int32_t lsm6dsox_device_id_get(lsm6dsox_ctx_t *ctx, uint8_t *buff); + +int32_t lsm6dsox_reset_set(lsm6dsox_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_reset_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsox_auto_increment_set(lsm6dsox_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_auto_increment_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsox_boot_set(lsm6dsox_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_boot_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +typedef enum { + LSM6DSOX_XL_ST_DISABLE = 0, + LSM6DSOX_XL_ST_POSITIVE = 1, + LSM6DSOX_XL_ST_NEGATIVE = 2, +} lsm6dsox_st_xl_t; +int32_t lsm6dsox_xl_self_test_set(lsm6dsox_ctx_t *ctx, lsm6dsox_st_xl_t val); +int32_t lsm6dsox_xl_self_test_get(lsm6dsox_ctx_t *ctx, lsm6dsox_st_xl_t *val); + +typedef enum { + LSM6DSOX_GY_ST_DISABLE = 0, + LSM6DSOX_GY_ST_POSITIVE = 1, + LSM6DSOX_GY_ST_NEGATIVE = 3, +} lsm6dsox_st_g_t; +int32_t lsm6dsox_gy_self_test_set(lsm6dsox_ctx_t *ctx, lsm6dsox_st_g_t val); +int32_t lsm6dsox_gy_self_test_get(lsm6dsox_ctx_t *ctx, lsm6dsox_st_g_t *val); + +int32_t lsm6dsox_xl_filter_lp2_set(lsm6dsox_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_xl_filter_lp2_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsox_gy_filter_lp1_set(lsm6dsox_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_gy_filter_lp1_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsox_filter_settling_mask_set(lsm6dsox_ctx_t *ctx, + uint8_t val); +int32_t lsm6dsox_filter_settling_mask_get(lsm6dsox_ctx_t *ctx, + uint8_t *val); + +typedef enum { + LSM6DSOX_ULTRA_LIGHT = 0, + LSM6DSOX_VERY_LIGHT = 1, + LSM6DSOX_LIGHT = 2, + LSM6DSOX_MEDIUM = 3, + LSM6DSOX_STRONG = 4, + LSM6DSOX_VERY_STRONG = 5, + LSM6DSOX_AGGRESSIVE = 6, + LSM6DSOX_XTREME = 7, +} lsm6dsox_ftype_t; +int32_t lsm6dsox_gy_lp1_bandwidth_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_ftype_t val); +int32_t lsm6dsox_gy_lp1_bandwidth_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_ftype_t *val); + +int32_t lsm6dsox_xl_lp2_on_6d_set(lsm6dsox_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_xl_lp2_on_6d_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +typedef enum { + LSM6DSOX_HP_PATH_DISABLE_ON_OUT = 0x00, + LSM6DSOX_SLOPE_ODR_DIV_4 = 0x10, + LSM6DSOX_HP_ODR_DIV_10 = 0x11, + LSM6DSOX_HP_ODR_DIV_20 = 0x12, + LSM6DSOX_HP_ODR_DIV_45 = 0x13, + LSM6DSOX_HP_ODR_DIV_100 = 0x14, + LSM6DSOX_HP_ODR_DIV_200 = 0x15, + LSM6DSOX_HP_ODR_DIV_400 = 0x16, + LSM6DSOX_HP_ODR_DIV_800 = 0x17, + LSM6DSOX_HP_REF_MD_ODR_DIV_10 = 0x31, + LSM6DSOX_HP_REF_MD_ODR_DIV_20 = 0x32, + LSM6DSOX_HP_REF_MD_ODR_DIV_45 = 0x33, + LSM6DSOX_HP_REF_MD_ODR_DIV_100 = 0x34, + LSM6DSOX_HP_REF_MD_ODR_DIV_200 = 0x35, + LSM6DSOX_HP_REF_MD_ODR_DIV_400 = 0x36, + LSM6DSOX_HP_REF_MD_ODR_DIV_800 = 0x37, + LSM6DSOX_LP_ODR_DIV_10 = 0x01, + LSM6DSOX_LP_ODR_DIV_20 = 0x02, + LSM6DSOX_LP_ODR_DIV_45 = 0x03, + LSM6DSOX_LP_ODR_DIV_100 = 0x04, + LSM6DSOX_LP_ODR_DIV_200 = 0x05, + LSM6DSOX_LP_ODR_DIV_400 = 0x06, + LSM6DSOX_LP_ODR_DIV_800 = 0x07, +} lsm6dsox_hp_slope_xl_en_t; +int32_t lsm6dsox_xl_hp_path_on_out_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_hp_slope_xl_en_t val); +int32_t lsm6dsox_xl_hp_path_on_out_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_hp_slope_xl_en_t *val); + +int32_t lsm6dsox_xl_fast_settling_set(lsm6dsox_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_xl_fast_settling_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +typedef enum { + LSM6DSOX_USE_SLOPE = 0, + LSM6DSOX_USE_HPF = 1, +} lsm6dsox_slope_fds_t; +int32_t lsm6dsox_xl_hp_path_internal_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_slope_fds_t val); +int32_t lsm6dsox_xl_hp_path_internal_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_slope_fds_t *val); + +typedef enum { + LSM6DSOX_HP_FILTER_NONE = 0x00, + LSM6DSOX_HP_FILTER_16mHz = 0x80, + LSM6DSOX_HP_FILTER_65mHz = 0x81, + LSM6DSOX_HP_FILTER_260mHz = 0x82, + LSM6DSOX_HP_FILTER_1Hz04 = 0x83, +} lsm6dsox_hpm_g_t; +int32_t lsm6dsox_gy_hp_path_internal_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_hpm_g_t val); +int32_t lsm6dsox_gy_hp_path_internal_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_hpm_g_t *val); + +typedef enum { + LSM6DSOX_OIS_CTRL_AUX_DATA_UI = 0x00, + LSM6DSOX_OIS_CTRL_AUX_DATA_UI_AUX = 0x01, + LSM6DSOX_OIS_CTRL_UI_AUX_DATA_UI = 0x02, + LSM6DSOX_OIS_CTRL_UI_AUX_DATA_UI_AUX = 0x03, +} lsm6dsox_spi2_read_en_t; +int32_t lsm6dsox_ois_mode_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_spi2_read_en_t val); +int32_t lsm6dsox_ois_mode_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_spi2_read_en_t *val); + +typedef enum { + LSM6DSOX_AUX_PULL_UP_DISC = 0, + LSM6DSOX_AUX_PULL_UP_CONNECT = 1, +} lsm6dsox_ois_pu_dis_t; +int32_t lsm6dsox_aux_sdo_ocs_mode_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_ois_pu_dis_t val); +int32_t lsm6dsox_aux_sdo_ocs_mode_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_ois_pu_dis_t *val); + +typedef enum { + LSM6DSOX_AUX_ON = 1, + LSM6DSOX_AUX_ON_BY_AUX_INTERFACE = 0, +} lsm6dsox_ois_on_t; +int32_t lsm6dsox_aux_pw_on_ctrl_set(lsm6dsox_ctx_t *ctx, lsm6dsox_ois_on_t val); +int32_t lsm6dsox_aux_pw_on_ctrl_get(lsm6dsox_ctx_t *ctx, lsm6dsox_ois_on_t *val); + +typedef enum { + LSM6DSOX_USE_SAME_XL_FS = 0, + LSM6DSOX_USE_DIFFERENT_XL_FS = 1, +} lsm6dsox_xl_fs_mode_t; +int32_t lsm6dsox_aux_xl_fs_mode_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_xl_fs_mode_t val); +int32_t lsm6dsox_aux_xl_fs_mode_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_xl_fs_mode_t *val); + +int32_t lsm6dsox_aux_status_reg_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_spi2_status_reg_ois_t *val); + +int32_t lsm6dsox_aux_xl_flag_data_ready_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsox_aux_gy_flag_data_ready_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsox_aux_gy_flag_settling_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +typedef enum { + LSM6DSOX_AUX_DEN_ACTIVE_LOW = 0, + LSM6DSOX_AUX_DEN_ACTIVE_HIGH = 1, +} lsm6dsox_den_lh_ois_t; +int32_t lsm6dsox_aux_den_polarity_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_den_lh_ois_t val); +int32_t lsm6dsox_aux_den_polarity_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_den_lh_ois_t *val); + +typedef enum { + LSM6DSOX_AUX_DEN_DISABLE = 0, + LSM6DSOX_AUX_DEN_LEVEL_LATCH = 3, + LSM6DSOX_AUX_DEN_LEVEL_TRIG = 2, +} lsm6dsox_lvl2_ois_t; +int32_t lsm6dsox_aux_den_mode_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_lvl2_ois_t val); +int32_t lsm6dsox_aux_den_mode_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_lvl2_ois_t *val); + +int32_t lsm6dsox_aux_drdy_on_int2_set(lsm6dsox_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_aux_drdy_on_int2_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +typedef enum { + LSM6DSOX_AUX_DISABLE = 0, + LSM6DSOX_MODE_3_GY = 1, + LSM6DSOX_MODE_4_GY_XL = 3, +} lsm6dsox_ois_en_spi2_t; +int32_t lsm6dsox_aux_mode_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_ois_en_spi2_t val); +int32_t lsm6dsox_aux_mode_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_ois_en_spi2_t *val); + +typedef enum { + LSM6DSOX_250dps_AUX = 0, + LSM6DSOX_125dps_AUX = 1, + LSM6DSOX_500dps_AUX = 2, + LSM6DSOX_1000dps_AUX = 4, + LSM6DSOX_2000dps_AUX = 6, +} lsm6dsox_fs_g_ois_t; +int32_t lsm6dsox_aux_gy_full_scale_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_fs_g_ois_t val); +int32_t lsm6dsox_aux_gy_full_scale_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_fs_g_ois_t *val); + +typedef enum { + LSM6DSOX_AUX_SPI_4_WIRE = 0, + LSM6DSOX_AUX_SPI_3_WIRE = 1, +} lsm6dsox_sim_ois_t; +int32_t lsm6dsox_aux_spi_mode_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_sim_ois_t val); +int32_t lsm6dsox_aux_spi_mode_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_sim_ois_t *val); + +typedef enum { + LSM6DSOX_351Hz39 = 0, + LSM6DSOX_236Hz63 = 1, + LSM6DSOX_172Hz70 = 2, + LSM6DSOX_937Hz91 = 3, +} lsm6dsox_ftype_ois_t; +int32_t lsm6dsox_aux_gy_lp1_bandwidth_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_ftype_ois_t val); +int32_t lsm6dsox_aux_gy_lp1_bandwidth_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_ftype_ois_t *val); + +typedef enum { + LSM6DSOX_AUX_HP_DISABLE = 0x00, + LSM6DSOX_AUX_HP_Hz016 = 0x10, + LSM6DSOX_AUX_HP_Hz065 = 0x11, + LSM6DSOX_AUX_HP_Hz260 = 0x12, + LSM6DSOX_AUX_HP_1Hz040 = 0x13, +} lsm6dsox_hpm_ois_t; +int32_t lsm6dsox_aux_gy_hp_bandwidth_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_hpm_ois_t val); +int32_t lsm6dsox_aux_gy_hp_bandwidth_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_hpm_ois_t *val); + +typedef enum { + LSM6DSOX_ENABLE_CLAMP = 0, + LSM6DSOX_DISABLE_CLAMP = 1, +} lsm6dsox_st_ois_clampdis_t; +int32_t lsm6dsox_aux_gy_clamp_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_st_ois_clampdis_t val); +int32_t lsm6dsox_aux_gy_clamp_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_st_ois_clampdis_t *val); + +typedef enum { + LSM6DSOX_289Hz = 0, + LSM6DSOX_258Hz = 1, + LSM6DSOX_120Hz = 2, + LSM6DSOX_65Hz2 = 3, + LSM6DSOX_33Hz2 = 4, + LSM6DSOX_16Hz6 = 5, + LSM6DSOX_8Hz30 = 6, + LSM6DSOX_4Hz15 = 7, +} lsm6dsox_filter_xl_conf_ois_t; +int32_t lsm6dsox_aux_xl_bandwidth_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_filter_xl_conf_ois_t val); +int32_t lsm6dsox_aux_xl_bandwidth_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_filter_xl_conf_ois_t *val); + +typedef enum { + LSM6DSOX_AUX_2g = 0, + LSM6DSOX_AUX_16g = 1, + LSM6DSOX_AUX_4g = 2, + LSM6DSOX_AUX_8g = 3, +} lsm6dsox_fs_xl_ois_t; +int32_t lsm6dsox_aux_xl_full_scale_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_fs_xl_ois_t val); +int32_t lsm6dsox_aux_xl_full_scale_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_fs_xl_ois_t *val); + +typedef enum { + LSM6DSOX_PULL_UP_DISC = 0, + LSM6DSOX_PULL_UP_CONNECT = 1, +} lsm6dsox_sdo_pu_en_t; +int32_t lsm6dsox_sdo_sa0_mode_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_sdo_pu_en_t val); +int32_t lsm6dsox_sdo_sa0_mode_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_sdo_pu_en_t *val); + +typedef enum { + LSM6DSOX_SPI_4_WIRE = 0, + LSM6DSOX_SPI_3_WIRE = 1, +} lsm6dsox_sim_t; +int32_t lsm6dsox_spi_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_sim_t val); +int32_t lsm6dsox_spi_mode_get(lsm6dsox_ctx_t *ctx, lsm6dsox_sim_t *val); + +typedef enum { + LSM6DSOX_I2C_ENABLE = 0, + LSM6DSOX_I2C_DISABLE = 1, +} lsm6dsox_i2c_disable_t; +int32_t lsm6dsox_i2c_interface_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_i2c_disable_t val); +int32_t lsm6dsox_i2c_interface_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_i2c_disable_t *val); + +typedef enum { + LSM6DSOX_I3C_DISABLE = 0x80, + LSM6DSOX_I3C_ENABLE_T_50us = 0x00, + LSM6DSOX_I3C_ENABLE_T_2us = 0x01, + LSM6DSOX_I3C_ENABLE_T_1ms = 0x02, + LSM6DSOX_I3C_ENABLE_T_25ms = 0x03, +} lsm6dsox_i3c_disable_t; +int32_t lsm6dsox_i3c_disable_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_i3c_disable_t val); +int32_t lsm6dsox_i3c_disable_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_i3c_disable_t *val); +typedef struct { + lsm6dsox_int1_ctrl_t int1_ctrl; + lsm6dsox_md1_cfg_t md1_cfg; + lsm6dsox_emb_func_int1_t emb_func_int1; + lsm6dsox_fsm_int1_a_t fsm_int1_a; + lsm6dsox_fsm_int1_b_t fsm_int1_b; + lsm6dsox_mlc_int1_t mlc_int1; +} lsm6dsox_pin_int1_route_t; +int32_t lsm6dsox_pin_int1_route_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_pin_int1_route_t *val); +int32_t lsm6dsox_pin_int1_route_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_pin_int1_route_t *val); + +typedef struct { + lsm6dsox_int2_ctrl_t int2_ctrl; + lsm6dsox_md2_cfg_t md2_cfg; + lsm6dsox_emb_func_int2_t emb_func_int2; + lsm6dsox_fsm_int2_a_t fsm_int2_a; + lsm6dsox_fsm_int2_b_t fsm_int2_b; + lsm6dsox_mlc_int2_t mlc_int2; +} lsm6dsox_pin_int2_route_t; +int32_t lsm6dsox_pin_int2_route_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_pin_int2_route_t *val); +int32_t lsm6dsox_pin_int2_route_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_pin_int2_route_t *val); + +typedef enum { + LSM6DSOX_PUSH_PULL = 0x00, + LSM6DSOX_OPEN_DRAIN = 0x01, + LSM6DSOX_INT1_NOPULL_DOWN_INT2_PUSH_PULL = 0x02, + LSM6DSOX_INT1_NOPULL_DOWN_INT2_OPEN_DRAIN = 0x03, +} lsm6dsox_pp_od_t; +int32_t lsm6dsox_pin_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_pp_od_t val); +int32_t lsm6dsox_pin_mode_get(lsm6dsox_ctx_t *ctx, lsm6dsox_pp_od_t *val); + +typedef enum { + LSM6DSOX_ACTIVE_HIGH = 0, + LSM6DSOX_ACTIVE_LOW = 1, +} lsm6dsox_h_lactive_t; +int32_t lsm6dsox_pin_polarity_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_h_lactive_t val); +int32_t lsm6dsox_pin_polarity_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_h_lactive_t *val); + +int32_t lsm6dsox_all_on_int1_set(lsm6dsox_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_all_on_int1_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +typedef enum { + LSM6DSOX_ALL_INT_PULSED = 0, + LSM6DSOX_BASE_LATCHED_EMB_PULSED = 1, + LSM6DSOX_BASE_PULSED_EMB_LATCHED = 2, + LSM6DSOX_ALL_INT_LATCHED = 3, +} lsm6dsox_lir_t; +int32_t lsm6dsox_int_notification_set(lsm6dsox_ctx_t *ctx, lsm6dsox_lir_t val); +int32_t lsm6dsox_int_notification_get(lsm6dsox_ctx_t *ctx, lsm6dsox_lir_t *val); + +typedef enum { + LSM6DSOX_LSb_FS_DIV_64 = 0, + LSM6DSOX_LSb_FS_DIV_256 = 1, +} lsm6dsox_wake_ths_w_t; +int32_t lsm6dsox_wkup_ths_weight_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_wake_ths_w_t val); +int32_t lsm6dsox_wkup_ths_weight_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_wake_ths_w_t *val); + +int32_t lsm6dsox_wkup_threshold_set(lsm6dsox_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_wkup_threshold_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsox_xl_usr_offset_on_wkup_set(lsm6dsox_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_xl_usr_offset_on_wkup_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsox_wkup_dur_set(lsm6dsox_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_wkup_dur_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsox_gy_sleep_mode_set(lsm6dsox_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_gy_sleep_mode_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +typedef enum { + LSM6DSOX_DRIVE_SLEEP_CHG_EVENT = 0, + LSM6DSOX_DRIVE_SLEEP_STATUS = 1, +} lsm6dsox_sleep_status_on_int_t; +int32_t lsm6dsox_act_pin_notification_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_sleep_status_on_int_t val); +int32_t lsm6dsox_act_pin_notification_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_sleep_status_on_int_t *val); + +typedef enum { + LSM6DSOX_XL_AND_GY_NOT_AFFECTED = 0, + LSM6DSOX_XL_12Hz5_GY_NOT_AFFECTED = 1, + LSM6DSOX_XL_12Hz5_GY_SLEEP = 2, + LSM6DSOX_XL_12Hz5_GY_PD = 3, +} lsm6dsox_inact_en_t; +int32_t lsm6dsox_act_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_inact_en_t val); +int32_t lsm6dsox_act_mode_get(lsm6dsox_ctx_t *ctx, lsm6dsox_inact_en_t *val); + +int32_t lsm6dsox_act_sleep_dur_set(lsm6dsox_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_act_sleep_dur_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsox_tap_detection_on_z_set(lsm6dsox_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_tap_detection_on_z_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsox_tap_detection_on_y_set(lsm6dsox_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_tap_detection_on_y_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsox_tap_detection_on_x_set(lsm6dsox_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_tap_detection_on_x_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsox_tap_threshold_x_set(lsm6dsox_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_tap_threshold_x_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +typedef enum { + LSM6DSOX_XYZ = 0, + LSM6DSOX_YXZ = 1, + LSM6DSOX_XZY = 2, + LSM6DSOX_ZYX = 3, + LSM6DSOX_YZX = 5, + LSM6DSOX_ZXY = 6, +} lsm6dsox_tap_priority_t; +int32_t lsm6dsox_tap_axis_priority_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_tap_priority_t val); +int32_t lsm6dsox_tap_axis_priority_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_tap_priority_t *val); + +int32_t lsm6dsox_tap_threshold_y_set(lsm6dsox_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_tap_threshold_y_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsox_tap_threshold_z_set(lsm6dsox_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_tap_threshold_z_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsox_tap_shock_set(lsm6dsox_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_tap_shock_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsox_tap_quiet_set(lsm6dsox_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_tap_quiet_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsox_tap_dur_set(lsm6dsox_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_tap_dur_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +typedef enum { + LSM6DSOX_ONLY_SINGLE = 0, + LSM6DSOX_BOTH_SINGLE_DOUBLE = 1, +} lsm6dsox_single_double_tap_t; +int32_t lsm6dsox_tap_mode_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_single_double_tap_t val); +int32_t lsm6dsox_tap_mode_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_single_double_tap_t *val); + +typedef enum { + LSM6DSOX_DEG_80 = 0, + LSM6DSOX_DEG_70 = 1, + LSM6DSOX_DEG_60 = 2, + LSM6DSOX_DEG_50 = 3, +} lsm6dsox_sixd_ths_t; +int32_t lsm6dsox_6d_threshold_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_sixd_ths_t val); +int32_t lsm6dsox_6d_threshold_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_sixd_ths_t *val); + +int32_t lsm6dsox_4d_mode_set(lsm6dsox_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_4d_mode_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +typedef enum { + LSM6DSOX_FF_TSH_156mg = 0, + LSM6DSOX_FF_TSH_219mg = 1, + LSM6DSOX_FF_TSH_250mg = 2, + LSM6DSOX_FF_TSH_312mg = 3, + LSM6DSOX_FF_TSH_344mg = 4, + LSM6DSOX_FF_TSH_406mg = 5, + LSM6DSOX_FF_TSH_469mg = 6, + LSM6DSOX_FF_TSH_500mg = 7, +} lsm6dsox_ff_ths_t; +int32_t lsm6dsox_ff_threshold_set(lsm6dsox_ctx_t *ctx, lsm6dsox_ff_ths_t val); +int32_t lsm6dsox_ff_threshold_get(lsm6dsox_ctx_t *ctx, lsm6dsox_ff_ths_t *val); + +int32_t lsm6dsox_ff_dur_set(lsm6dsox_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_ff_dur_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsox_fifo_watermark_set(lsm6dsox_ctx_t *ctx, uint16_t val); +int32_t lsm6dsox_fifo_watermark_get(lsm6dsox_ctx_t *ctx, uint16_t *val); + +int32_t lsm6dsox_compression_algo_init_set(lsm6dsox_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_compression_algo_init_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +typedef enum { + LSM6DSOX_CMP_DISABLE = 0x00, + LSM6DSOX_CMP_ALWAYS = 0x04, + LSM6DSOX_CMP_8_TO_1 = 0x05, + LSM6DSOX_CMP_16_TO_1 = 0x06, + LSM6DSOX_CMP_32_TO_1 = 0x07, +} lsm6dsox_uncoptr_rate_t; +int32_t lsm6dsox_compression_algo_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_uncoptr_rate_t val); +int32_t lsm6dsox_compression_algo_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_uncoptr_rate_t *val); + +int32_t lsm6dsox_fifo_virtual_sens_odr_chg_set(lsm6dsox_ctx_t *ctx, + uint8_t val); +int32_t lsm6dsox_fifo_virtual_sens_odr_chg_get(lsm6dsox_ctx_t *ctx, + uint8_t *val); + +int32_t lsm6dsox_compression_algo_real_time_set(lsm6dsox_ctx_t *ctx, + uint8_t val); +int32_t lsm6dsox_compression_algo_real_time_get(lsm6dsox_ctx_t *ctx, + uint8_t *val); + +int32_t lsm6dsox_fifo_stop_on_wtm_set(lsm6dsox_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_fifo_stop_on_wtm_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +typedef enum { + LSM6DSOX_XL_NOT_BATCHED = 0, + LSM6DSOX_XL_BATCHED_AT_12Hz5 = 1, + LSM6DSOX_XL_BATCHED_AT_26Hz = 2, + LSM6DSOX_XL_BATCHED_AT_52Hz = 3, + LSM6DSOX_XL_BATCHED_AT_104Hz = 4, + LSM6DSOX_XL_BATCHED_AT_208Hz = 5, + LSM6DSOX_XL_BATCHED_AT_417Hz = 6, + LSM6DSOX_XL_BATCHED_AT_833Hz = 7, + LSM6DSOX_XL_BATCHED_AT_1667Hz = 8, + LSM6DSOX_XL_BATCHED_AT_3333Hz = 9, + LSM6DSOX_XL_BATCHED_AT_6667Hz = 10, + LSM6DSOX_XL_BATCHED_AT_6Hz5 = 11, +} lsm6dsox_bdr_xl_t; +int32_t lsm6dsox_fifo_xl_batch_set(lsm6dsox_ctx_t *ctx, lsm6dsox_bdr_xl_t val); +int32_t lsm6dsox_fifo_xl_batch_get(lsm6dsox_ctx_t *ctx, lsm6dsox_bdr_xl_t *val); + +typedef enum { + LSM6DSOX_GY_NOT_BATCHED = 0, + LSM6DSOX_GY_BATCHED_AT_12Hz5 = 1, + LSM6DSOX_GY_BATCHED_AT_26Hz = 2, + LSM6DSOX_GY_BATCHED_AT_52Hz = 3, + LSM6DSOX_GY_BATCHED_AT_104Hz = 4, + LSM6DSOX_GY_BATCHED_AT_208Hz = 5, + LSM6DSOX_GY_BATCHED_AT_417Hz = 6, + LSM6DSOX_GY_BATCHED_AT_833Hz = 7, + LSM6DSOX_GY_BATCHED_AT_1667Hz = 8, + LSM6DSOX_GY_BATCHED_AT_3333Hz = 9, + LSM6DSOX_GY_BATCHED_AT_6667Hz = 10, + LSM6DSOX_GY_BATCHED_AT_6Hz5 = 11, +} lsm6dsox_bdr_gy_t; +int32_t lsm6dsox_fifo_gy_batch_set(lsm6dsox_ctx_t *ctx, lsm6dsox_bdr_gy_t val); +int32_t lsm6dsox_fifo_gy_batch_get(lsm6dsox_ctx_t *ctx, lsm6dsox_bdr_gy_t *val); + +typedef enum { + LSM6DSOX_BYPASS_MODE = 0, + LSM6DSOX_FIFO_MODE = 1, + LSM6DSOX_STREAM_TO_FIFO_MODE = 3, + LSM6DSOX_BYPASS_TO_STREAM_MODE = 4, + LSM6DSOX_STREAM_MODE = 6, + LSM6DSOX_BYPASS_TO_FIFO_MODE = 7, +} lsm6dsox_fifo_mode_t; +int32_t lsm6dsox_fifo_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_fifo_mode_t val); +int32_t lsm6dsox_fifo_mode_get(lsm6dsox_ctx_t *ctx, lsm6dsox_fifo_mode_t *val); + +typedef enum { + LSM6DSOX_TEMP_NOT_BATCHED = 0, + LSM6DSOX_TEMP_BATCHED_AT_1Hz6 = 1, + LSM6DSOX_TEMP_BATCHED_AT_12Hz5 = 2, + LSM6DSOX_TEMP_BATCHED_AT_52Hz = 3, +} lsm6dsox_odr_t_batch_t; +int32_t lsm6dsox_fifo_temp_batch_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_odr_t_batch_t val); +int32_t lsm6dsox_fifo_temp_batch_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_odr_t_batch_t *val); + +typedef enum { + LSM6DSOX_NO_DECIMATION = 0, + LSM6DSOX_DEC_1 = 1, + LSM6DSOX_DEC_8 = 2, + LSM6DSOX_DEC_32 = 3, +} lsm6dsox_odr_ts_batch_t; +int32_t lsm6dsox_fifo_timestamp_decimation_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_odr_ts_batch_t val); +int32_t lsm6dsox_fifo_timestamp_decimation_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_odr_ts_batch_t *val); + +typedef enum { + LSM6DSOX_XL_BATCH_EVENT = 0, + LSM6DSOX_GYRO_BATCH_EVENT = 1, +} lsm6dsox_trig_counter_bdr_t; + +typedef enum { + LSM6DSOX_GYRO_NC_TAG = 1, + LSM6DSOX_XL_NC_TAG, + LSM6DSOX_TEMPERATURE_TAG, + LSM6DSOX_TIMESTAMP_TAG, + LSM6DSOX_CFG_CHANGE_TAG, + LSM6DSOX_XL_NC_T_2_TAG, + LSM6DSOX_XL_NC_T_1_TAG, + LSM6DSOX_XL_2XC_TAG, + LSM6DSOX_XL_3XC_TAG, + LSM6DSOX_GYRO_NC_T_2_TAG, + LSM6DSOX_GYRO_NC_T_1_TAG, + LSM6DSOX_GYRO_2XC_TAG, + LSM6DSOX_GYRO_3XC_TAG, + LSM6DSOX_SENSORHUB_SLAVE0_TAG, + LSM6DSOX_SENSORHUB_SLAVE1_TAG, + LSM6DSOX_SENSORHUB_SLAVE2_TAG, + LSM6DSOX_SENSORHUB_SLAVE3_TAG, + LSM6DSOX_STEP_CPUNTER_TAG, + LSM6DSOX_GAME_ROTATION_TAG, + LSM6DSOX_GEOMAG_ROTATION_TAG, + LSM6DSOX_ROTATION_TAG, + LSM6DSOX_SENSORHUB_NACK_TAG = 0x19, +} lsm6dsox_fifo_tag_t; +int32_t lsm6dsox_fifo_cnt_event_batch_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_trig_counter_bdr_t val); +int32_t lsm6dsox_fifo_cnt_event_batch_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_trig_counter_bdr_t *val); + +int32_t lsm6dsox_rst_batch_counter_set(lsm6dsox_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_rst_batch_counter_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsox_batch_counter_threshold_set(lsm6dsox_ctx_t *ctx, + uint16_t val); +int32_t lsm6dsox_batch_counter_threshold_get(lsm6dsox_ctx_t *ctx, + uint16_t *val); + +int32_t lsm6dsox_fifo_data_level_get(lsm6dsox_ctx_t *ctx, uint16_t *val); + +int32_t lsm6dsox_fifo_status_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_fifo_status2_t *val); + +int32_t lsm6dsox_fifo_full_flag_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsox_fifo_ovr_flag_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsox_fifo_wtm_flag_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsox_fifo_sensor_tag_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_fifo_tag_t *val); + +int32_t lsm6dsox_fifo_pedo_batch_set(lsm6dsox_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_fifo_pedo_batch_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsox_sh_batch_slave_0_set(lsm6dsox_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_sh_batch_slave_0_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsox_sh_batch_slave_1_set(lsm6dsox_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_sh_batch_slave_1_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsox_sh_batch_slave_2_set(lsm6dsox_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_sh_batch_slave_2_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsox_sh_batch_slave_3_set(lsm6dsox_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_sh_batch_slave_3_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +typedef enum { + LSM6DSOX_DEN_DISABLE = 0, + LSM6DSOX_LEVEL_FIFO = 6, + LSM6DSOX_LEVEL_LETCHED = 3, + LSM6DSOX_LEVEL_TRIGGER = 2, + LSM6DSOX_EDGE_TRIGGER = 4, +} lsm6dsox_den_mode_t; +int32_t lsm6dsox_den_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_den_mode_t val); +int32_t lsm6dsox_den_mode_get(lsm6dsox_ctx_t *ctx, lsm6dsox_den_mode_t *val); + +typedef enum { + LSM6DSOX_DEN_ACT_LOW = 0, + LSM6DSOX_DEN_ACT_HIGH = 1, +} lsm6dsox_den_lh_t; +int32_t lsm6dsox_den_polarity_set(lsm6dsox_ctx_t *ctx, lsm6dsox_den_lh_t val); +int32_t lsm6dsox_den_polarity_get(lsm6dsox_ctx_t *ctx, lsm6dsox_den_lh_t *val); + +typedef enum { + LSM6DSOX_STAMP_IN_GY_DATA = 0, + LSM6DSOX_STAMP_IN_XL_DATA = 1, + LSM6DSOX_STAMP_IN_GY_XL_DATA = 2, +} lsm6dsox_den_xl_g_t; +int32_t lsm6dsox_den_enable_set(lsm6dsox_ctx_t *ctx, lsm6dsox_den_xl_g_t val); +int32_t lsm6dsox_den_enable_get(lsm6dsox_ctx_t *ctx, lsm6dsox_den_xl_g_t *val); + +int32_t lsm6dsox_den_mark_axis_x_set(lsm6dsox_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_den_mark_axis_x_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsox_den_mark_axis_y_set(lsm6dsox_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_den_mark_axis_y_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsox_den_mark_axis_z_set(lsm6dsox_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_den_mark_axis_z_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +typedef enum { + LSM6DSOX_PEDO_DISABLE = 0x00, + LSM6DSOX_PEDO_BASE_MODE = 0x01, + LSM6DSOX_PEDO_ADV_MODE = 0x03, + LSM6DSOX_FALSE_STEP_REJ = 0x13, + LSM6DSOX_FALSE_STEP_REJ_ADV_MODE = 0x33, +} lsm6dsox_pedo_md_t; +int32_t lsm6dsox_pedo_sens_set(lsm6dsox_ctx_t *ctx, lsm6dsox_pedo_md_t val); +int32_t lsm6dsox_pedo_sens_get(lsm6dsox_ctx_t *ctx, lsm6dsox_pedo_md_t *val); + +int32_t lsm6dsox_pedo_step_detect_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsox_pedo_debounce_steps_set(lsm6dsox_ctx_t *ctx, + uint8_t *buff); +int32_t lsm6dsox_pedo_debounce_steps_get(lsm6dsox_ctx_t *ctx, + uint8_t *buff); + +int32_t lsm6dsox_pedo_steps_period_set(lsm6dsox_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dsox_pedo_steps_period_get(lsm6dsox_ctx_t *ctx, uint8_t *buff); + +int32_t lsm6dsox_pedo_adv_detection_set(lsm6dsox_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_pedo_adv_detection_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsox_pedo_false_step_rejection_set(lsm6dsox_ctx_t *ctx, + uint8_t val); +int32_t lsm6dsox_pedo_false_step_rejection_get(lsm6dsox_ctx_t *ctx, + uint8_t *val); + +typedef enum { + LSM6DSOX_EVERY_STEP = 0, + LSM6DSOX_COUNT_OVERFLOW = 1, +} lsm6dsox_carry_count_en_t; +int32_t lsm6dsox_pedo_int_mode_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_carry_count_en_t val); +int32_t lsm6dsox_pedo_int_mode_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_carry_count_en_t *val); + +int32_t lsm6dsox_motion_sens_set(lsm6dsox_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_motion_sens_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsox_motion_flag_data_ready_get(lsm6dsox_ctx_t *ctx, + uint8_t *val); + +int32_t lsm6dsox_tilt_sens_set(lsm6dsox_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_tilt_sens_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsox_tilt_flag_data_ready_get(lsm6dsox_ctx_t *ctx, + uint8_t *val); + +int32_t lsm6dsox_sh_mag_sensitivity_set(lsm6dsox_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dsox_sh_mag_sensitivity_get(lsm6dsox_ctx_t *ctx, uint8_t *buff); + +int32_t lsm6dsox_mlc_mag_sensitivity_set(lsm6dsox_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dsox_mlc_mag_sensitivity_get(lsm6dsox_ctx_t *ctx, uint8_t *buff); + +int32_t lsm6dsox_mag_offset_set(lsm6dsox_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dsox_mag_offset_get(lsm6dsox_ctx_t *ctx, uint8_t *buff); + +int32_t lsm6dsox_mag_soft_iron_set(lsm6dsox_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dsox_mag_soft_iron_get(lsm6dsox_ctx_t *ctx, uint8_t *buff); + +typedef enum { + LSM6DSOX_Z_EQ_Y = 0, + LSM6DSOX_Z_EQ_MIN_Y = 1, + LSM6DSOX_Z_EQ_X = 2, + LSM6DSOX_Z_EQ_MIN_X = 3, + LSM6DSOX_Z_EQ_MIN_Z = 4, + LSM6DSOX_Z_EQ_Z = 5, +} lsm6dsox_mag_z_axis_t; +int32_t lsm6dsox_mag_z_orient_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_mag_z_axis_t val); +int32_t lsm6dsox_mag_z_orient_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_mag_z_axis_t *val); + +typedef enum { + LSM6DSOX_Y_EQ_Y = 0, + LSM6DSOX_Y_EQ_MIN_Y = 1, + LSM6DSOX_Y_EQ_X = 2, + LSM6DSOX_Y_EQ_MIN_X = 3, + LSM6DSOX_Y_EQ_MIN_Z = 4, + LSM6DSOX_Y_EQ_Z = 5, +} lsm6dsox_mag_y_axis_t; +int32_t lsm6dsox_mag_y_orient_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_mag_y_axis_t val); +int32_t lsm6dsox_mag_y_orient_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_mag_y_axis_t *val); + +typedef enum { + LSM6DSOX_X_EQ_Y = 0, + LSM6DSOX_X_EQ_MIN_Y = 1, + LSM6DSOX_X_EQ_X = 2, + LSM6DSOX_X_EQ_MIN_X = 3, + LSM6DSOX_X_EQ_MIN_Z = 4, + LSM6DSOX_X_EQ_Z = 5, +} lsm6dsox_mag_x_axis_t; +int32_t lsm6dsox_mag_x_orient_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_mag_x_axis_t val); +int32_t lsm6dsox_mag_x_orient_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_mag_x_axis_t *val); + +int32_t lsm6dsox_long_cnt_flag_data_ready_get(lsm6dsox_ctx_t *ctx, + uint8_t *val); + +int32_t lsm6dsox_emb_fsm_en_set(lsm6dsox_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_emb_fsm_en_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +typedef struct { + lsm6dsox_fsm_enable_a_t fsm_enable_a; + lsm6dsox_fsm_enable_b_t fsm_enable_b; +} lsm6dsox_emb_fsm_enable_t; +int32_t lsm6dsox_fsm_enable_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_emb_fsm_enable_t *val); +int32_t lsm6dsox_fsm_enable_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_emb_fsm_enable_t *val); + +int32_t lsm6dsox_long_cnt_set(lsm6dsox_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dsox_long_cnt_get(lsm6dsox_ctx_t *ctx, uint8_t *buff); + +typedef enum { + LSM6DSOX_LC_NORMAL = 0, + LSM6DSOX_LC_CLEAR = 1, + LSM6DSOX_LC_CLEAR_DONE = 2, +} lsm6dsox_fsm_lc_clr_t; +int32_t lsm6dsox_long_clr_set(lsm6dsox_ctx_t *ctx, lsm6dsox_fsm_lc_clr_t val); +int32_t lsm6dsox_long_clr_get(lsm6dsox_ctx_t *ctx, lsm6dsox_fsm_lc_clr_t *val); + +typedef struct { + lsm6dsox_fsm_outs1_t fsm_outs1; + lsm6dsox_fsm_outs2_t fsm_outs2; + lsm6dsox_fsm_outs3_t fsm_outs3; + lsm6dsox_fsm_outs4_t fsm_outs4; + lsm6dsox_fsm_outs5_t fsm_outs5; + lsm6dsox_fsm_outs6_t fsm_outs6; + lsm6dsox_fsm_outs7_t fsm_outs7; + lsm6dsox_fsm_outs8_t fsm_outs8; + lsm6dsox_fsm_outs1_t fsm_outs9; + lsm6dsox_fsm_outs2_t fsm_outs10; + lsm6dsox_fsm_outs3_t fsm_outs11; + lsm6dsox_fsm_outs4_t fsm_outs12; + lsm6dsox_fsm_outs5_t fsm_outs13; + lsm6dsox_fsm_outs6_t fsm_outs14; + lsm6dsox_fsm_outs7_t fsm_outs15; + lsm6dsox_fsm_outs8_t fsm_outs16; +} lsm6dsox_fsm_out_t; +int32_t lsm6dsox_fsm_out_get(lsm6dsox_ctx_t *ctx, lsm6dsox_fsm_out_t *val); + +typedef enum { + LSM6DSOX_ODR_FSM_12Hz5 = 0, + LSM6DSOX_ODR_FSM_26Hz = 1, + LSM6DSOX_ODR_FSM_52Hz = 2, + LSM6DSOX_ODR_FSM_104Hz = 3, +} lsm6dsox_fsm_odr_t; +int32_t lsm6dsox_fsm_data_rate_set(lsm6dsox_ctx_t *ctx, lsm6dsox_fsm_odr_t val); +int32_t lsm6dsox_fsm_data_rate_get(lsm6dsox_ctx_t *ctx, lsm6dsox_fsm_odr_t *val); + +int32_t lsm6dsox_fsm_init_set(lsm6dsox_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_fsm_init_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsox_long_cnt_int_value_set(lsm6dsox_ctx_t *ctx, uint16_t val); +int32_t lsm6dsox_long_cnt_int_value_get(lsm6dsox_ctx_t *ctx, uint16_t *val); + +int32_t lsm6dsox_fsm_number_of_programs_set(lsm6dsox_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_fsm_number_of_programs_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsox_fsm_start_address_set(lsm6dsox_ctx_t *ctx, uint16_t val); +int32_t lsm6dsox_fsm_start_address_get(lsm6dsox_ctx_t *ctx, uint16_t *val); + +int32_t lsm6dsox_mlc_set(lsm6dsox_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_mlc_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsox_mlc_status_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_mlc_status_mainpage_t *val); + +typedef enum { + LSM6DSOX_ODR_PRGS_12Hz5 = 0, + LSM6DSOX_ODR_PRGS_26Hz = 1, + LSM6DSOX_ODR_PRGS_52Hz = 2, + LSM6DSOX_ODR_PRGS_104Hz = 3, +} lsm6dsox_mlc_odr_t; +int32_t lsm6dsox_mlc_data_rate_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_mlc_odr_t val); +int32_t lsm6dsox_mlc_data_rate_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_mlc_odr_t *val); + +typedef struct { + lsm6dsox_sensor_hub_1_t sh_byte_1; + lsm6dsox_sensor_hub_2_t sh_byte_2; + lsm6dsox_sensor_hub_3_t sh_byte_3; + lsm6dsox_sensor_hub_4_t sh_byte_4; + lsm6dsox_sensor_hub_5_t sh_byte_5; + lsm6dsox_sensor_hub_6_t sh_byte_6; + lsm6dsox_sensor_hub_7_t sh_byte_7; + lsm6dsox_sensor_hub_8_t sh_byte_8; + lsm6dsox_sensor_hub_9_t sh_byte_9; + lsm6dsox_sensor_hub_10_t sh_byte_10; + lsm6dsox_sensor_hub_11_t sh_byte_11; + lsm6dsox_sensor_hub_12_t sh_byte_12; + lsm6dsox_sensor_hub_13_t sh_byte_13; + lsm6dsox_sensor_hub_14_t sh_byte_14; + lsm6dsox_sensor_hub_15_t sh_byte_15; + lsm6dsox_sensor_hub_16_t sh_byte_16; + lsm6dsox_sensor_hub_17_t sh_byte_17; + lsm6dsox_sensor_hub_18_t sh_byte_18; +} lsm6dsox_emb_sh_read_t; +int32_t lsm6dsox_sh_read_data_raw_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_emb_sh_read_t *val); + +typedef enum { + LSM6DSOX_SLV_0 = 0, + LSM6DSOX_SLV_0_1 = 1, + LSM6DSOX_SLV_0_1_2 = 2, + LSM6DSOX_SLV_0_1_2_3 = 3, +} lsm6dsox_aux_sens_on_t; +int32_t lsm6dsox_sh_slave_connected_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_aux_sens_on_t val); +int32_t lsm6dsox_sh_slave_connected_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_aux_sens_on_t *val); + +int32_t lsm6dsox_sh_master_set(lsm6dsox_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_sh_master_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +typedef enum { + LSM6DSOX_EXT_PULL_UP = 0, + LSM6DSOX_INTERNAL_PULL_UP = 1, +} lsm6dsox_shub_pu_en_t; +int32_t lsm6dsox_sh_pin_mode_set(lsm6dsox_ctx_t *ctx, lsm6dsox_shub_pu_en_t val); +int32_t lsm6dsox_sh_pin_mode_get(lsm6dsox_ctx_t *ctx, lsm6dsox_shub_pu_en_t *val); + +int32_t lsm6dsox_sh_pass_through_set(lsm6dsox_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_sh_pass_through_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +typedef enum { + LSM6DSOX_EXT_ON_INT2_PIN = 0, + LSM6DSOX_XL_GY_DRDY = 1, +} lsm6dsox_start_config_t; +int32_t lsm6dsox_sh_syncro_mode_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_start_config_t val); +int32_t lsm6dsox_sh_syncro_mode_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_start_config_t *val); + +typedef enum { + LSM6DSOX_EACH_SH_CYCLE = 0, + LSM6DSOX_ONLY_FIRST_CYCLE = 1, +} lsm6dsox_write_once_t; +int32_t lsm6dsox_sh_write_mode_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_write_once_t val); +int32_t lsm6dsox_sh_write_mode_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_write_once_t *val); + +int32_t lsm6dsox_sh_reset_set(lsm6dsox_ctx_t *ctx); +int32_t lsm6dsox_sh_reset_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +typedef enum { + LSM6DSOX_SH_ODR_104Hz = 0, + LSM6DSOX_SH_ODR_52Hz = 1, + LSM6DSOX_SH_ODR_26Hz = 2, + LSM6DSOX_SH_ODR_13Hz = 3, +} lsm6dsox_shub_odr_t; +int32_t lsm6dsox_sh_data_rate_set(lsm6dsox_ctx_t *ctx, lsm6dsox_shub_odr_t val); +int32_t lsm6dsox_sh_data_rate_get(lsm6dsox_ctx_t *ctx, lsm6dsox_shub_odr_t *val); + +typedef struct{ + uint8_t slv0_add; + uint8_t slv0_subadd; + uint8_t slv0_data; +} lsm6dsox_sh_cfg_write_t; +int32_t lsm6dsox_sh_cfg_write(lsm6dsox_ctx_t *ctx, lsm6dsox_sh_cfg_write_t *val); + +typedef struct{ + uint8_t slv_add; + uint8_t slv_subadd; + uint8_t slv_len; +} lsm6dsox_sh_cfg_read_t; +int32_t lsm6dsox_sh_slv0_cfg_read(lsm6dsox_ctx_t *ctx, + lsm6dsox_sh_cfg_read_t *val); +int32_t lsm6dsox_sh_slv1_cfg_read(lsm6dsox_ctx_t *ctx, + lsm6dsox_sh_cfg_read_t *val); +int32_t lsm6dsox_sh_slv2_cfg_read(lsm6dsox_ctx_t *ctx, + lsm6dsox_sh_cfg_read_t *val); +int32_t lsm6dsox_sh_slv3_cfg_read(lsm6dsox_ctx_t *ctx, + lsm6dsox_sh_cfg_read_t *val); + +int32_t lsm6dsox_sh_status_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_status_master_t *val); +typedef enum { + LSM6DSOX_S4S_TPH_7bit = 0, + LSM6DSOX_S4S_TPH_15bit = 1, +} lsm6dsox_s4s_tph_res_t; +int32_t lsm6dsox_s4s_tph_res_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_s4s_tph_res_t val); +int32_t lsm6dsox_s4s_tph_res_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_s4s_tph_res_t *val); + +int32_t lsm6dsox_s4s_tph_val_set(lsm6dsox_ctx_t *ctx, uint16_t val); +int32_t lsm6dsox_s4s_tph_val_get(lsm6dsox_ctx_t *ctx, uint16_t *val); + +typedef enum { + LSM6DSOX_S4S_DT_RES_11 = 0, + LSM6DSOX_S4S_DT_RES_12 = 1, + LSM6DSOX_S4S_DT_RES_13 = 2, + LSM6DSOX_S4S_DT_RES_14 = 3, +} lsm6dsox_s4s_res_ratio_t; +int32_t lsm6dsox_s4s_res_ratio_set(lsm6dsox_ctx_t *ctx, + lsm6dsox_s4s_res_ratio_t val); +int32_t lsm6dsox_s4s_res_ratio_get(lsm6dsox_ctx_t *ctx, + lsm6dsox_s4s_res_ratio_t *val); + +int32_t lsm6dsox_s4s_command_set(lsm6dsox_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_s4s_command_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsox_s4s_dt_set(lsm6dsox_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_s4s_dt_get(lsm6dsox_ctx_t *ctx, uint8_t *val); + +/** + * @} + * + */ + +#ifdef __cplusplus +} +#endif + +#endif /*LSM6DSOX_DRIVER_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/LKExp-mbed-sensors/lib/mbed-ST_lib/Interface/DevI2C.h b/LKExp-mbed-sensors/lib/mbed-ST_lib/Interface/DevI2C.h new file mode 100644 index 0000000..c5449d5 --- /dev/null +++ b/LKExp-mbed-sensors/lib/mbed-ST_lib/Interface/DevI2C.h @@ -0,0 +1,122 @@ +/** + ****************************************************************************** + * @file DevI2C.h + * @author AST / EST + * @version V1.1.0 + * @date 21-January-2016 + * @brief Header file for a special I2C class DevI2C which provides some + * helper function for on-board communication + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent from recursive inclusion --------------------------------*/ +#ifndef __DEV_I2C_H +#define __DEV_I2C_H + +/* Includes ------------------------------------------------------------------*/ +#include "mbed.h" +#include "pinmap.h" + +/* Classes -------------------------------------------------------------------*/ +/** Helper class DevI2C providing functions for multi-register I2C communication + * common for a series of I2C devices + */ +class DevI2C : public I2C +{ +public: + /** Create a DevI2C Master interface, connected to the specified pins + * + * @param sda I2C data line pin + * @param scl I2C clock line pin + */ + DevI2C(PinName sda, PinName scl) : I2C(sda, scl) {} + + /** + * @brief Writes a buffer towards the I2C peripheral device. + * @param pBuffer pointer to the byte-array data to send + * @param DeviceAddr specifies the peripheral device slave address. + * @param RegisterAddr specifies the internal address register + * where to start writing to (must be correctly masked). + * @param NumByteToWrite number of bytes to be written. + * @retval 0 if ok, + * @retval -1 if an I2C error has occured, or + * @retval -2 on temporary buffer overflow (i.e. NumByteToWrite was too high) + * @note On some devices if NumByteToWrite is greater + * than one, the RegisterAddr must be masked correctly! + */ + int i2c_write(uint8_t* pBuffer, uint8_t DeviceAddr, uint8_t RegisterAddr, + uint16_t NumByteToWrite) { + int ret; + uint8_t tmp[TEMP_BUF_SIZE]; + + if(NumByteToWrite >= TEMP_BUF_SIZE) return -2; + + /* First, send device address. Then, send data and STOP condition */ + tmp[0] = RegisterAddr; + memcpy(tmp+1, pBuffer, NumByteToWrite); + + ret = write(DeviceAddr, (const char*)tmp, NumByteToWrite+1, false); + + if(ret) return -1; + return 0; + } + + /** + * @brief Reads a buffer from the I2C peripheral device. + * @param pBuffer pointer to the byte-array to read data in to + * @param DeviceAddr specifies the peripheral device slave address. + * @param RegisterAddr specifies the internal address register + * where to start reading from (must be correctly masked). + * @param NumByteToRead number of bytes to be read. + * @retval 0 if ok, + * @retval -1 if an I2C error has occured + * @note On some devices if NumByteToWrite is greater + * than one, the RegisterAddr must be masked correctly! + */ + int i2c_read(uint8_t* pBuffer, uint8_t DeviceAddr, uint8_t RegisterAddr, + uint16_t NumByteToRead) { + int ret; + + /* Send device address, with no STOP condition */ + ret = write(DeviceAddr, (const char*)&RegisterAddr, 1, true); + if(!ret) { + /* Read data, with STOP condition */ + ret = read(DeviceAddr, (char*)pBuffer, NumByteToRead, false); + } + + if(ret) return -1; + return 0; + } + +private: + static const unsigned int TEMP_BUF_SIZE = 32; +}; + +#endif /* __DEV_I2C_H */ diff --git a/LKExp-mbed-sensors/lib/mbed-os.lib b/LKExp-mbed-sensors/lib/mbed-os.lib new file mode 100644 index 0000000..1e79537 --- /dev/null +++ b/LKExp-mbed-sensors/lib/mbed-os.lib @@ -0,0 +1 @@ +https://github.com/ARMmbed/mbed-os/ \ No newline at end of file diff --git a/LKExp-mbed-sensors/mbed_app.json b/LKExp-mbed-sensors/mbed_app.json new file mode 100644 index 0000000..5aeb00c --- /dev/null +++ b/LKExp-mbed-sensors/mbed_app.json @@ -0,0 +1,8 @@ +{ + "target_overrides": { + "*": { + "target.features": [], + "target.components": [] + } + } +} diff --git a/LKExp-mbed-sensors/src/board.cpp b/LKExp-mbed-sensors/src/board.cpp new file mode 100644 index 0000000..3a2dacf --- /dev/null +++ b/LKExp-mbed-sensors/src/board.cpp @@ -0,0 +1,25 @@ +#include "board.h" + +Board::Board(PinName sda, PinName scl) : + dev_i2c(sda, scl), + ht_sensor(&dev_i2c), + magneto(&dev_i2c), + acc_gyro(&dev_i2c, LSM6DSOX_I2C_ADD_L) +{ + ht_sensor.init(NULL); + magneto.init(NULL); + acc_gyro.init(NULL); + + DigitalOut LSM6DSOX_INT1 (PIN_LSM6DSOX_INT1, 0); //Set to 1 to disable I2C and enable only I3C on LSM6DSOX +} + +void Board::check_id() { + uint8_t id; + + ht_sensor.read_id(&id); + if (id != HTS221_WHO_AM_I_VAL) _errorLED = 1; //(0xBC expected) + magneto.read_id(&id); + if (id != LSM303AGR_MAG_WHO_AM_I) _errorLED = 1; //(0x40 expected) + acc_gyro.read_id(&id); + if (id != LSM6DSOX_ID) _errorLED = 1; //(0x6C expected) +} diff --git a/LKExp-mbed-sensors/src/board.h b/LKExp-mbed-sensors/src/board.h new file mode 100644 index 0000000..9f3fabf --- /dev/null +++ b/LKExp-mbed-sensors/src/board.h @@ -0,0 +1,26 @@ +/* Pin definition ------------------------------------------------------------*/ +#define PIN_I2C_SDA (D14) +#define PIN_I2C_SCL (D15) +#define PIN_LSM6DSOX_INT1 (A5) + +/* Includes ------------------------------------------------------------------*/ +#include "mbed.h" +#include "HTS221Sensor.h" +#include "LSM303AGRMagSensor.h" +#include "LSM6DSOXSensor.h" +#include "DevI2C.h" + +/* Static variables ----------------------------------------------------------*/ +static DigitalOut _errorLED(LED1); + +class Board { +public: + Board(PinName sda=PIN_I2C_SDA, PinName scl=PIN_I2C_SCL); + + void check_id(); + + DevI2C dev_i2c; + HTS221Sensor ht_sensor; + LSM303AGRMagSensor magneto; + LSM6DSOXSensor acc_gyro; +}; diff --git a/LKExp-mbed-sensors/src/main.cpp b/LKExp-mbed-sensors/src/main.cpp new file mode 100644 index 0000000..626468d --- /dev/null +++ b/LKExp-mbed-sensors/src/main.cpp @@ -0,0 +1,9 @@ +#include "mbed.h" +#include "board.h" + +Board board; + +int main(void) { + printf("--- Starting new run ---\r\n"); + board.check_id(); +}