AND.L / OR.L timing mismatch

[dirkwhoffmann]

Tested: or.l D0, D0

Test case: https://github.com/dirkwhoffmann/vAmigaTS/tree/master/CPU/OR/or2

Musashi (vAmiga):

A real Amiga 500+ 🥰:

Conclusion:

Current:

{m68k_op_and_32_er_d         , 0xf1f8, 0xc080, {  6,   6,   2,   2}},
{m68k_op_or_32_er_d          , 0xf1f8, 0x8080, {  6,   6,   2,   2}},

Correct:

{m68k_op_and_32_er_d         , 0xf1f8, 0xc080, {  8,   6,   2,   2}},
{m68k_op_or_32_er_d          , 0xf1f8, 0x8080, {  8,   6,   2,   2}},

I cannot say anything about the 68010 timing, because I don’t have a real 68010 CPU available.