From 269a3ca37b05faee26aa774ff311a2866d2860cf Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 18 Oct 2024 13:18:35 -0700 Subject: [PATCH] Revert changes to comment format now that preprocessor is being used --- tests/coverage/WALLY-init-lib.h | 60 ++++---- tests/coverage/amoAccessFault.S | 54 +++---- tests/coverage/csrwrites.S | 52 +++---- tests/coverage/dcache1.S | 16 +- tests/coverage/dcache1.py | 2 +- tests/coverage/dcache2.S | 60 ++++---- tests/coverage/ebu.S | 54 +++---- tests/coverage/floatmisc.S | 8 +- tests/coverage/fpu.S | 136 ++++++++--------- tests/coverage/fround.S | 2 +- tests/coverage/gshare.S | 56 +++---- tests/coverage/hptwAccessFault.S | 56 +++---- tests/coverage/ieu.S | 102 ++++++------- tests/coverage/ifu.S | 114 +++++++-------- tests/coverage/ifuCamlineWrite.S | 64 ++++---- tests/coverage/lsu.S | 54 +++---- tests/coverage/nonleafpbmtfault.S | 56 +++---- tests/coverage/pmp.S | 234 +++++++++++++++--------------- tests/coverage/pmpadrdecs.S | 6 +- tests/coverage/pmpcbo.S | 6 +- tests/coverage/pmpcfg.S | 10 +- tests/coverage/pmpcfg1.S | 10 +- tests/coverage/pmpcfg2.S | 8 +- tests/coverage/pmppriority.S | 14 +- tests/coverage/priv.S | 54 +++---- tests/coverage/tlbASID.S | 104 ++++++------- tests/coverage/tlbGLB.S | 146 +++++++++---------- tests/coverage/tlbGP.S | 62 ++++---- tests/coverage/tlbKP.S | 60 ++++---- tests/coverage/tlbM3.S | 60 ++++---- tests/coverage/tlbMP.S | 124 ++++++++-------- tests/coverage/tlbMisaligned.S | 60 ++++---- tests/coverage/tlbNAPOT.S | 60 ++++---- tests/coverage/tlbTP.S | 60 ++++---- tests/coverage/tlbmisc.S | 54 +++---- tests/coverage/vm64check.S | 68 ++++----- 36 files changed, 1073 insertions(+), 1073 deletions(-) diff --git a/tests/coverage/WALLY-init-lib.h b/tests/coverage/WALLY-init-lib.h index f03fb6d1cf..0ce72fd6b8 100644 --- a/tests/coverage/WALLY-init-lib.h +++ b/tests/coverage/WALLY-init-lib.h @@ -1,32 +1,32 @@ -########################################## -# WALLY-init-lib.h -# -# Written: David_Harris@hmc.edu 21 March 2023 -# -# Purpose: Initialize stack, handle interrupts, terminate test case -# -# A component of the CORE-V-WALLY configurable RISC-V project. -# https://github.com/openhwgroup/cvw -# -# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You -# may obtain a copy of the License at -# -# https://solderpad.org/licenses/SHL-2.1/ -# -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions -# and limitations under the License. -############################################################################################## - -# load code to initalize stack, handle interrupts, terminate -# The PMP tests are sensitive to the exact addresses in this code, so unfortunately -# modifying anything breaks those tests. +/////////////////////////////////////////// +// WALLY-init-lib.h +// +// Written: David_Harris@hmc.edu 21 March 2023 +// +// Purpose: Initialize stack, handle interrupts, terminate test case +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +// load code to initalize stack, handle interrupts, terminate +// The PMP tests are sensitive to the exact addresses in this code, so unfortunately +// modifying anything breaks those tests. .section .text.init .global rvtest_entry_point @@ -128,7 +128,7 @@ trap_return: # return from trap handler self_loop: j self_loop # wait -# utility routines +// utility routines # put a 1 in msb of a0 (position XLEN-1); works for both RV32 and RV64 setmsb: diff --git a/tests/coverage/amoAccessFault.S b/tests/coverage/amoAccessFault.S index 45350a0e80..b69c545a4e 100644 --- a/tests/coverage/amoAccessFault.S +++ b/tests/coverage/amoAccessFault.S @@ -1,30 +1,30 @@ -########################################## -# hptwAccessFault.S -# -# Written: Rose Thompson rose@rosethompson.net -# -# Purpose: Checks that only Store/AMO access faults are generated on AMO operations -# -# A component of the CORE-V-WALLY configurable RISC-V project. -# https://#github.com/openhwgroup/cvw -# -# Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You -# may obtain a copy of the License at -# -# https://#solderpad.org/licenses/SHL-2.1/ -# -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions -# and limitations under the License. -############################################################################################### - -# load code to initalize stack, handle interrupts, terminate +/////////////////////////////////////////// +// hptwAccessFault.S +// +// Written: Rose Thompson rose@rosethompson.net +// +// Purpose: Checks that only Store/AMO access faults are generated on AMO operations +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +// load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" diff --git a/tests/coverage/csrwrites.S b/tests/coverage/csrwrites.S index d21463ef94..fb5cfd4368 100644 --- a/tests/coverage/csrwrites.S +++ b/tests/coverage/csrwrites.S @@ -1,30 +1,30 @@ -########################################## -# csrwrites.S -# -# Written: David_Harris@hmc.edu 21 March 2023 -# -# Purpose: Test writes to CSRs -# -# A component of the CORE-V-WALLY configurable RISC-V project. -# https://github.com/openhwgroup/cvw -# -# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You -# may obtain a copy of the License at -# -# https://solderpad.org/licenses/SHL-2.1/ -# -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions -# and limitations under the License. -############################################################################################## +/////////////////////////////////////////// +// csrwrites.S +// +// Written: David_Harris@hmc.edu 21 March 2023 +// +// Purpose: Test writes to CSRs +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// -# load code to initalize stack, handle interrupts, terminate +// load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" main: diff --git a/tests/coverage/dcache1.S b/tests/coverage/dcache1.S index 7703e4a545..4a9b3de15f 100644 --- a/tests/coverage/dcache1.S +++ b/tests/coverage/dcache1.S @@ -1,9 +1,9 @@ #include "WALLY-init-lib.h" main: - # start way test #1 + // start way test #1 li t0, 0x80100000 .align 6 - # i$ boundary, way test #1 + // i$ boundary, way test #1 .word 0x00000013 .word 0x00000013 .word 0x00000013 @@ -20,10 +20,10 @@ main: sd zero, 0(t0) .word 0x00000013 .word 0x00000013 - # start way test #2 + // start way test #2 li t0, 0x80101000 .align 6 - # i$ boundary, way test #2 + // i$ boundary, way test #2 .word 0x00000013 .word 0x00000013 .word 0x00000013 @@ -40,10 +40,10 @@ main: sd zero, 0(t0) .word 0x00000013 .word 0x00000013 - # start way test #3 + // start way test #3 li t0, 0x80102000 .align 6 - # i$ boundary, way test #3 + // i$ boundary, way test #3 .word 0x00000013 .word 0x00000013 .word 0x00000013 @@ -60,10 +60,10 @@ main: sd zero, 0(t0) .word 0x00000013 .word 0x00000013 - # start way test #4 + // start way test #4 li t0, 0x80103000 .align 6 - # i$ boundary, way test #4 + // i$ boundary, way test #4 .word 0x00000013 .word 0x00000013 .word 0x00000013 diff --git a/tests/coverage/dcache1.py b/tests/coverage/dcache1.py index 350fe348ad..d8740bdda0 100644 --- a/tests/coverage/dcache1.py +++ b/tests/coverage/dcache1.py @@ -44,7 +44,7 @@ def wl(line="", comment=None, fname=test_name): ".align" in line or "# include" in line) else True indent = 6 if instr else 0 - comment = "# " + comment if comment is not None else "" + comment = "// " + comment if comment is not None else "" to_write = " " * indent + line + comment + "\n" f.write(to_write) diff --git a/tests/coverage/dcache2.S b/tests/coverage/dcache2.S index d94a05821b..d5a18a708d 100644 --- a/tests/coverage/dcache2.S +++ b/tests/coverage/dcache2.S @@ -1,48 +1,48 @@ -########################################## -# dcache2.S -# -# Written: avercruysse@hmc.edu 18 April 2023 -# -# Purpose: Test Coverage for D$ -# (for all 4 cache ways, trigger a FlushStage while SetDirtyWay=1) -# -# A component of the CORE-V-WALLY configurable RISC-V project. -# https://github.com/openhwgroup/cvw -# -# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You -# may obtain a copy of the License at -# -# https://solderpad.org/licenses/SHL-2.1/ -# -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions -# and limitations under the License. -############################################################################################## +/////////////////////////////////////////// +// dcache2.S +// +// Written: avercruysse@hmc.edu 18 April 2023 +// +// Purpose: Test Coverage for D$ +// (for all 4 cache ways, trigger a FlushStage while SetDirtyWay=1) +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// #include "WALLY-init-lib.h" main: - # way 0 + // way 0 li t0, 0x80100770 sd zero, 0(t0) sd zero, 1(t0) - # way 1 + // way 1 li t0, 0x80101770 sd zero, 0(t0) sd zero, 1(t0) - # way 2 + // way 2 li t0, 0x80102770 sd zero, 0(t0) sd zero, 1(t0) - # way 3 + // way 3 li t0, 0x80103770 sd zero, 0(t0) sd zero, 1(t0) diff --git a/tests/coverage/ebu.S b/tests/coverage/ebu.S index fd888e3d15..872e373943 100644 --- a/tests/coverage/ebu.S +++ b/tests/coverage/ebu.S @@ -1,30 +1,30 @@ -########################################## -# ebu.S -# -# Written: David_Harris@hmc.edu 21 January 2024 -# -# Purpose: Test coverage for EBU -# -# A component of the CORE-V-WALLY configurable RISC-V project. -# https://github.com/openhwgroup/cvw -# -# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You -# may obtain a copy of the License at -# -# https://solderpad.org/licenses/SHL-2.1/ -# -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions -# and limitations under the License. -############################################################################################## - -# load code to initalize stack, handle interrupts, terminate +/////////////////////////////////////////// +// ebu.S +// +// Written: David_Harris@hmc.edu 21 January 2024 +// +// Purpose: Test coverage for EBU +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +// load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" diff --git a/tests/coverage/floatmisc.S b/tests/coverage/floatmisc.S index fc43ecd8a3..46bbc5418e 100644 --- a/tests/coverage/floatmisc.S +++ b/tests/coverage/floatmisc.S @@ -1,7 +1,7 @@ -# debug.S -# David_Harris@hmc.edu 4 February 2023 -# Small code snippets for the purpose of debugging issues -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// debug.S +// David_Harris@hmc.edu 4 February 2023 +// Small code snippets for the purpose of debugging issues +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 .global rvtest_entry_point rvtest_entry_point: diff --git a/tests/coverage/fpu.S b/tests/coverage/fpu.S index 2767b5fe11..7608983062 100644 --- a/tests/coverage/fpu.S +++ b/tests/coverage/fpu.S @@ -1,30 +1,30 @@ -########################################## -# fpu.S -# -# Written: David_Harris@hmc.edu 28 March 2023 -# -# Purpose: Test coverage for FPU -# -# A component of the CORE-V-WALLY configurable RISC-V project. -# https://github.com/openhwgroup/cvw -# -# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You -# may obtain a copy of the License at -# -# https://solderpad.org/licenses/SHL-2.1/ -# -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions -# and limitations under the License. -############################################################################################## - -# load code to initalize stack, handle interrupts, terminate +/////////////////////////////////////////// +// fpu.S +// +// Written: David_Harris@hmc.edu 28 March 2023 +// +// Purpose: Test coverage for FPU +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +// load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" main: @@ -120,9 +120,9 @@ main: fcvt.s.l ft0, t0 fcvt.s.lu ft0, t0 - # Tests verfying that half and quad floating point convertion instructions are not supported by rv64gc - # fcvt.h.d ft3, ft0 # Somehow this instruction is taking the route on line 124 - # idea: enable the Q extension for this to work properly? A: Q and halfs not supported in rv64gc + // Tests verfying that half and quad floating point convertion instructions are not supported by rv64gc + # fcvt.h.d ft3, ft0 // Somehow this instruction is taking the route on line 124 + // idea: enable the Q extension for this to work properly? A: Q and halfs not supported in rv64gc # fcvt.h.w ft3, a0 # fcvt.w.h a0, ft0 # fcvt.q.w ft3, a0 @@ -131,12 +131,12 @@ main: # half-precision NaN boxing la t0, TestData3 - fld ft2, 0(t0) # bad NaN-boxed number - fmadd.h ft1, ft2, ft2, ft2 # Test NaN boxing - fmadd.s ft1, ft2, ft2, ft2 # Test NaN boxing + fld ft2, 0(t0) // bad NaN-boxed number + fmadd.h ft1, ft2, ft2, ft2 // Test NaN boxing + fmadd.s ft1, ft2, ft2, ft2 // Test NaN boxing - # fdivsqrt: test busy->idle transition caused by a FlushE while divider is busy (when interrupt arrives) - # This code doesn't actually trigger a busy->idle transition because the pending timer interrupt doesn't occur until the division finishes. + // fdivsqrt: test busy->idle transition caused by a FlushE while divider is busy (when interrupt arrives) + // This code doesn't actually trigger a busy->idle transition because the pending timer interrupt doesn't occur until the division finishes. li t0, 0x3F812345 # random value slightly bigger than 1 li t1, 0x3F823456 fmv.w.x ft0, t0 # move int to fp register @@ -155,44 +155,44 @@ main: csrci mstatus, 0b1000 # disable interrupts with mstatus.MIE # Completing branch coverage in fctrl.sv - .word 0x38007553 # Testing the all False case for 119 - funct7 under, op = 101 0011 - .word 0x40000053 # Line 145 All False Test case - illegal instruction? - .word 0xd0400053 # Line 156 All False Test case - illegal instruction? - .word 0xc0400053 # Line 162 All False Test case - illegal instruction? - .word 0xd2400053 # Line 168 All False Test case - illegal instruction? - .word 0xc2400053 # Line 174 All False Test case - illegal instruction? + .word 0x38007553 // Testing the all False case for 119 - funct7 under, op = 101 0011 + .word 0x40000053 // Line 145 All False Test case - illegal instruction? + .word 0xd0400053 // Line 156 All False Test case - illegal instruction? + .word 0xc0400053 // Line 162 All False Test case - illegal instruction? + .word 0xd2400053 // Line 168 All False Test case - illegal instruction? + .word 0xc2400053 // Line 174 All False Test case - illegal instruction? # Increasing conditional coverage in fctrl.sv - .word 0xc5000007 # Attempting to toggle (Op7 != 7) to 0 on line 97 in fctrl, not sure what instruction this works out to - .word 0xe0101053 # toggling (Rs2D == 0) to 0 on line 139 in fctrl. Illegal Intsr (like fclass but incorrect rs2) - .word 0xe0100053 # toggling (Rs2D == 0) to 0 on line 141 in fctrl. Illegal Intsr (like fmv but incorrect rs2) - .word 0x40D00053 # toggling (Rs2D[4:2] == 0) to 0 on line 145 in fctrl. - .word 0x40300053 # toggling SupportFmt2 to 0 on line 145 in fctrl. - .word 0x42100053 # toggling (Rs2D[1:0] != 1) to 0 on line 147 in fctrl. Illegal Instr - .word 0xf0100053 # toggling (Rs2D == 0) to 0 on line 143 in fctrl. Illegal Instr + .word 0xc5000007 // Attempting to toggle (Op7 != 7) to 0 on line 97 in fctrl, not sure what instruction this works out to + .word 0xe0101053 // toggling (Rs2D == 0) to 0 on line 139 in fctrl. Illegal Intsr (like fclass but incorrect rs2) + .word 0xe0100053 // toggling (Rs2D == 0) to 0 on line 141 in fctrl. Illegal Intsr (like fmv but incorrect rs2) + .word 0x40D00053 // toggling (Rs2D[4:2] == 0) to 0 on line 145 in fctrl. + .word 0x40300053 // toggling SupportFmt2 to 0 on line 145 in fctrl. + .word 0x42100053 // toggling (Rs2D[1:0] != 1) to 0 on line 147 in fctrl. Illegal Instr + .word 0xf0100053 // toggling (Rs2D == 0) to 0 on line 143 in fctrl. Illegal Instr # Test illegal instructions are detected - .word 0x00000007 # illegal floating-point load (bad Funct3) - .word 0x00000027 # illegal floating-point store (bad Funct3) - .word 0x58F00053 # illegal fsqrt (bad Rs2D) - .word 0x20007053 # illegal fsgnj (bad Funct3) - .word 0x28007053 # illegal fmin/max (bad Funct3) - .word 0xA0007053 # illegal fcmp (bad Funct3) - .word 0xE0007053 # illegal fclass/fmv (bad Funct3) - .word 0xF0007053 # illegal fmv (bad Funct3) - .word 0x43007053 # illegal fcvt.d.* (bad Rs2D) - .word 0x42207053 # illegal fcvt.d.* (bad Rs2D[1]) - .word 0xD5F00053 # illegal fcvt.h.* (bad Rs2D) - .word 0xC5F00053 # illegal fcvt.*.h (bad Rs2D) - .word 0x04000043 # illegal fmadd.h (h not supported) - .word 0xC2800053 # illegal fcvtmod.w.d with rm rne - .word 0xF0101053 # illegal fli with Funct3D not 0 - .word 0xF0400053 # illegal fli with Rs2D not 1 - .word 0x44200053 # illegal instruction for f.cvt.h.h - - # Test divide by zero with rounding mode toward zero + .word 0x00000007 // illegal floating-point load (bad Funct3) + .word 0x00000027 // illegal floating-point store (bad Funct3) + .word 0x58F00053 // illegal fsqrt (bad Rs2D) + .word 0x20007053 // illegal fsgnj (bad Funct3) + .word 0x28007053 // illegal fmin/max (bad Funct3) + .word 0xA0007053 // illegal fcmp (bad Funct3) + .word 0xE0007053 // illegal fclass/fmv (bad Funct3) + .word 0xF0007053 // illegal fmv (bad Funct3) + .word 0x43007053 // illegal fcvt.d.* (bad Rs2D) + .word 0x42207053 // illegal fcvt.d.* (bad Rs2D[1]) + .word 0xD5F00053 // illegal fcvt.h.* (bad Rs2D) + .word 0xC5F00053 // illegal fcvt.*.h (bad Rs2D) + .word 0x04000043 // illegal fmadd.h (h not supported) + .word 0xC2800053 // illegal fcvtmod.w.d with rm rne + .word 0xF0101053 // illegal fli with Funct3D not 0 + .word 0xF0400053 // illegal fli with Rs2D not 1 + .word 0x44200053 // illegal instruction for f.cvt.h.h + + // Test divide by zero with rounding mode toward zero li t0, 1 - csrw frm, t0 # set rounding mode = 1 + csrw frm, t0 // set rounding mode = 1 li t0, 0x3f800000 fcvt.s.w ft1, t0 fcvt.s.w ft2, zero diff --git a/tests/coverage/fround.S b/tests/coverage/fround.S index 76d4c683cf..7d469d7738 100644 --- a/tests/coverage/fround.S +++ b/tests/coverage/fround.S @@ -1,4 +1,4 @@ -# fround.s +// fround.s #include "WALLY-init-lib.h" diff --git a/tests/coverage/gshare.S b/tests/coverage/gshare.S index 0b213ba34e..ef0fcab777 100644 --- a/tests/coverage/gshare.S +++ b/tests/coverage/gshare.S @@ -1,31 +1,31 @@ -########################################## -# gshare.S -# -# Written: Rose Thompson rose@rosethompson.net -# -# Purpose: basic check that global history and gshare branch npredictors are working as expected. Requires manual inspection. -# TODO: *** Automate checking prediction accuracy. -# -# A component of the CORE-V-WALLY configurable RISC-V project. -# https://github.com/openhwgroup/cvw -# -# Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You -# may obtain a copy of the License at -# -# https://solderpad.org/licenses/SHL-2.1/ -# -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions -# and limitations under the License. -############################################################################################## - -# load code to initalize stack, handle interrupts, terminate +/////////////////////////////////////////// +// gshare.S +// +// Written: Rose Thompson rose@rosethompson.net +// +// Purpose: basic check that global history and gshare branch npredictors are working as expected. Requires manual inspection. +// TODO: *** Automate checking prediction accuracy. +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +// load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" diff --git a/tests/coverage/hptwAccessFault.S b/tests/coverage/hptwAccessFault.S index dc7e43dd14..86f681d21c 100644 --- a/tests/coverage/hptwAccessFault.S +++ b/tests/coverage/hptwAccessFault.S @@ -1,31 +1,31 @@ -########################################## -# hptwAccessFault.S -# -# Written: Rose Thompson rose@rosethompson.net -# -# Purpose: Force the HPTW to walk a page table with invalid addresses so that the pma checker -# generate access faults. -# -# A component of the CORE-V-WALLY configurable RISC-V project. -# https://github.com/openhwgroup/cvw -# -# Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You -# may obtain a copy of the License at -# -# https://solderpad.org/licenses/SHL-2.1/ -# -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions -# and limitations under the License. -############################################################################################## - -# load code to initalize stack, handle interrupts, terminate +/////////////////////////////////////////// +// hptwAccessFault.S +// +// Written: Rose Thompson rose@rosethompson.net +// +// Purpose: Force the HPTW to walk a page table with invalid addresses so that the pma checker +// generate access faults. +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +// load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" diff --git a/tests/coverage/ieu.S b/tests/coverage/ieu.S index 2524887792..43e7b6604f 100644 --- a/tests/coverage/ieu.S +++ b/tests/coverage/ieu.S @@ -1,30 +1,30 @@ -########################################## -# ieu.S -# -# Written: David_Harris@hmc.edu 21 March 2023 -# -# Purpose: Test coverage for IEU -# -# A component of the CORE-V-WALLY configurable RISC-V project. -# https://github.com/openhwgroup/cvw -# -# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You -# may obtain a copy of the License at -# -# https://solderpad.org/licenses/SHL-2.1/ -# -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions -# and limitations under the License. -############################################################################################## +/////////////////////////////////////////// +// ieu.S +// +// Written: David_Harris@hmc.edu 21 March 2023 +// +// Purpose: Test coverage for IEU +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// -# load code to initalize stack, handle interrupts, terminate +// load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" main: @@ -56,31 +56,31 @@ main: # Test illegal instructions are detected - .word 0x80000033 # illegal R-type instruction - .word 0x00007003 # illegal Load instruction - .word 0x80005013 # illegal I-type instruction: srli: op = 0010011, funct3 = 101, funct7 = 1000000 - .word 0x00000000 # illegal instruction - .word 0x0000701B # Illegal IW instruction - .word 0x00004023 # Illegal store instruction - .word 0x0400003B # Illegal RW or MulDivW instruction - .word 0x00007067 # Illegal JALR instruction - .word 0x00002063 # Illegal branch instruction - .word 0x60F01013 # Illegal BMU sign extend / count instruction - .word 0x60801013 # Illegal BMU sign extend / count instruction - .word 0x60301013 # Illegal BMU sign extend / count instruction - .word 0x6BF05013 # Illegal BMU similar to rev8 - .word 0x69805013 # Illegal BMU similar to rev8 - .word 0x28F05013 # Illegal BMU similar to or.c - .word 0x60F0101B # Illegal BMU similar to count word - .word 0x6080101B # Illegal BMU similar to count word - .word 0x6030101B # Illegal BMU similar to count word - .word 0x0000202F # Illegal similar to LR - .word 0x1010202F # Illegal similar to LR - .word 0x00402003 # illegal similar to CMO - .word 0x00202003 # illegal similar to CMO - .word 0xFF00302F # illegal Atomic instruction - .word 0xFF00402F # illegal Atomic instruction - .word 0x00000873 # illegal CSR instruction + .word 0x80000033 // illegal R-type instruction + .word 0x00007003 // illegal Load instruction + .word 0x80005013 // illegal I-type instruction: srli: op = 0010011, funct3 = 101, funct7 = 1000000 + .word 0x00000000 // illegal instruction + .word 0x0000701B // Illegal IW instruction + .word 0x00004023 // Illegal store instruction + .word 0x0400003B // Illegal RW or MulDivW instruction + .word 0x00007067 // Illegal JALR instruction + .word 0x00002063 // Illegal branch instruction + .word 0x60F01013 // Illegal BMU sign extend / count instruction + .word 0x60801013 // Illegal BMU sign extend / count instruction + .word 0x60301013 // Illegal BMU sign extend / count instruction + .word 0x6BF05013 // Illegal BMU similar to rev8 + .word 0x69805013 // Illegal BMU similar to rev8 + .word 0x28F05013 // Illegal BMU similar to or.c + .word 0x60F0101B // Illegal BMU similar to count word + .word 0x6080101B // Illegal BMU similar to count word + .word 0x6030101B // Illegal BMU similar to count word + .word 0x0000202F // Illegal similar to LR + .word 0x1010202F // Illegal similar to LR + .word 0x00402003 // illegal similar to CMO + .word 0x00202003 // illegal similar to CMO + .word 0xFF00302F // illegal Atomic instruction + .word 0xFF00402F // illegal Atomic instruction + .word 0x00000873 // illegal CSR instruction # Illegal CMO instructions because envcfg is 0 and system is in user Mode li a0, 0 diff --git a/tests/coverage/ifu.S b/tests/coverage/ifu.S index 08a527f948..72c5152873 100644 --- a/tests/coverage/ifu.S +++ b/tests/coverage/ifu.S @@ -1,30 +1,30 @@ -########################################## -# ifu.S -# -# Written: sriley@g.hmc.edu 28 March 2023 -# -# Purpose: Test coverage for IFU -# -# A component of the CORE-V-WALLY configurable RISC-V project. -# https://github.com/openhwgroup/cvw -# -# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You -# may obtain a copy of the License at -# -# https://solderpad.org/licenses/SHL-2.1/ -# -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions -# and limitations under the License. -############################################################################################## +/////////////////////////////////////////// +// ifu.S +// +// Written: sriley@g.hmc.edu 28 March 2023 +// +// Purpose: Test coverage for IFU +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// -# load code to initalize stack, handle interrupts, terminate +// load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" main: @@ -33,47 +33,47 @@ main: csrs mstatus, t0 # calling compressed floating point load double instruction - #.hword 0x2000 # CL type compressed floating-point ld-->funct3,imm,rs1',imm,rd',op - # binary version 0000 0000 0000 0000 0010 0000 0000 0000 + //.hword 0x2000 // CL type compressed floating-point ld-->funct3,imm,rs1',imm,rd',op + // binary version 0000 0000 0000 0000 0010 0000 0000 0000 mv s0, sp - c.fld fs0, 0(s0) # Previously uncovered instructions + c.fld fs0, 0(s0) // Previously uncovered instructions c.fsd fs0, 0(s0) - .hword 0x2002 # c.fldsp fs0, 0 - .hword 0xA002 # c.fsdsp fs0, 0 - .hword 0x9C41 # line 134 Illegal compressed instruction + .hword 0x2002 // c.fldsp fs0, 0 + .hword 0xA002 // c.fsdsp fs0, 0 + .hword 0x9C41 // line 134 Illegal compressed instruction # Zcb coverage tests # could restore assembly language versions when GCC supports Zcb mv s0, sp - #c.lbu s1, 0(s0) # exercise c.lbu - .hword 0x8004 # c.lbu s1, 0(s0) - #c.lh s1, 0(s0) # exercise c.lh - .hword 0x8444 # c.lh s1, 0(s0) - #c.lhu s1, 0(s0) # exercise c.lhu - .hword 0x8404 # c.lhu s1, 0(s0) - #c.sb s1, 0(s0) # exercise c.sb - .hword 0x8804 # c.sb s1, 0(s0) - #c.sh s1, 0(s0) # exercise c.sh - .hword 0x8C04 # c.sh s1, 0(s0) + #c.lbu s1, 0(s0) // exercise c.lbu + .hword 0x8004 // c.lbu s1, 0(s0) + #c.lh s1, 0(s0) // exercise c.lh + .hword 0x8444 // c.lh s1, 0(s0) + #c.lhu s1, 0(s0) // exercise c.lhu + .hword 0x8404 // c.lhu s1, 0(s0) + #c.sb s1, 0(s0) // exercise c.sb + .hword 0x8804 // c.sb s1, 0(s0) + #c.sh s1, 0(s0) // exercise c.sh + .hword 0x8C04 // c.sh s1, 0(s0) - .hword 0x8C44 # Illegal compressed instruction with op = 00, Instr[15:10] = 100011, Instr[6] = 1 and 0's everywhere else. Line 119 illegal instruction - .hword 0x9C00 # Illegal compressed instruction with op = 00, Instr[15:10] = 100111, and 0's everywhere else. Line 119 illegal instruction + .hword 0x8C44 // Illegal compressed instruction with op = 00, Instr[15:10] = 100011, Instr[6] = 1 and 0's everywhere else. Line 119 illegal instruction + .hword 0x9C00 // Illegal compressed instruction with op = 00, Instr[15:10] = 100111, and 0's everywhere else. Line 119 illegal instruction li s0, 0xFF - # c.zext.b s0 # exercise c.zext.b - .hword 0x9C61 # c.zext.b s0 - # c.sext.b s0 # exercise c.sext.b - .hword 0x9C65 # c.sext.b s0 - # c.zext.h s0 # exercise c.zext.h - .hword 0x9C69 # c.zext.h s0 - # c.sext.h s0 # exercise c.sext.h - .hword 0x9C6D # c.sext.h s0 - # c.zext.w s0 # exercise c.zext.w - .hword 0x9C71 # c.zext.w s0 - # c.not s0 # exercise c.not - .hword 0x9C75 # c.not s0 + # c.zext.b s0 // exercise c.zext.b + .hword 0x9C61 // c.zext.b s0 + # c.sext.b s0 // exercise c.sext.b + .hword 0x9C65 // c.sext.b s0 + # c.zext.h s0 // exercise c.zext.h + .hword 0x9C69 // c.zext.h s0 + # c.sext.h s0 // exercise c.sext.h + .hword 0x9C6D // c.sext.h s0 + # c.zext.w s0 // exercise c.zext.w + .hword 0x9C71 // c.zext.w s0 + # c.not s0 // exercise c.not + .hword 0x9C75 // c.not s0 - .hword 0x9C7D # Reserved instruction from line 187 with op = 01, Instr[15:10] = 100111, Instr[6:5] = 11, and 0's everywhere else + .hword 0x9C7D // Reserved instruction from line 187 with op = 01, Instr[15:10] = 100111, Instr[6:5] = 11, and 0's everywhere else # exercise all the cache ways j way0code diff --git a/tests/coverage/ifuCamlineWrite.S b/tests/coverage/ifuCamlineWrite.S index f32ecd97dc..fed86756e0 100644 --- a/tests/coverage/ifuCamlineWrite.S +++ b/tests/coverage/ifuCamlineWrite.S @@ -1,33 +1,33 @@ -########################################## -# ifuCamlineWrite.S -# -# Written: Miles Cook and Kevin Box 4/17 -# -# Acknowledgements: The pagetable and outline for this test was written by Manuel Mendoza -# and Noah Limpert. -# -# Purpose: Test coverage for TLBCamlines in IFU -# -# A component of the CORE-V-WALLY configurable RISC-V project. -# https://github.com/openhwgroup/cvw -# -# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You -# may obtain a copy of the License at -# -# https://solderpad.org/licenses/SHL-2.1/ -# -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions -# and limitations under the License. -############################################################################################## - -# load code to initalize stack, handle interrupts, terminate +/////////////////////////////////////////// +// ifuCamlineWrite.S +// +// Written: Miles Cook and Kevin Box 4/17 +// +// Acknowledgements: The pagetable and outline for this test was written by Manuel Mendoza +// and Noah Limpert. +// +// Purpose: Test coverage for TLBCamlines in IFU +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +// load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" @@ -64,7 +64,7 @@ finished: .align 16 # Page table situated at 0x80010000 pagetable: - .8byte 0x200044C1 # old page table was 200040 which just pointed to itself! wrong + .8byte 0x200044C1 // old page table was 200040 which just pointed to itself! wrong .align 12 .8byte 0x0000000000000000 @@ -74,7 +74,7 @@ pagetable: .align 12 .8byte 0x0000000020004CC1 - #.8byte 0x00000200800CF# ADD IN THE MEGAPAGE should 3 nibbles of zeros be removed? + //.8byte 0x00000200800CF// ADD IN THE MEGAPAGE should 3 nibbles of zeros be removed? .align 12 #80000000 diff --git a/tests/coverage/lsu.S b/tests/coverage/lsu.S index f0c0494b7a..1c1d7fea6a 100644 --- a/tests/coverage/lsu.S +++ b/tests/coverage/lsu.S @@ -1,35 +1,35 @@ -########################################## -# lsu.S -# -# Written: Kevin Box and Miles Cook kbox@hmc.edu mdcook@hmc.edu 26 March 2023 -# -# Purpose: Test coverage for lsu -# -# A component of the CORE-V-WALLY configurable RISC-V project. -# https://github.com/openhwgroup/cvw -# -# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You -# may obtain a copy of the License at -# -# https://solderpad.org/licenses/SHL-2.1/ -# -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions -# and limitations under the License. -############################################################################################## +/////////////////////////////////////////// +// lsu.S +// +// Written: Kevin Box and Miles Cook kbox@hmc.edu mdcook@hmc.edu 26 March 2023 +// +// Purpose: Test coverage for lsu +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// -# load code to initalize stack, handle interrupts, terminate +// load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" main: - sfence.vma x0, x0 # sfence.vma to assert TLBFlush + sfence.vma x0, x0 // sfence.vma to assert TLBFlush li a0, 0x80000001 # misaligned address amoadd.w t0, a0, (a0) # amo access to misaligned address diff --git a/tests/coverage/nonleafpbmtfault.S b/tests/coverage/nonleafpbmtfault.S index 3ad0b914d4..d4aa723f7e 100644 --- a/tests/coverage/nonleafpbmtfault.S +++ b/tests/coverage/nonleafpbmtfault.S @@ -1,31 +1,31 @@ -########################################## -# hptwAccessFault.S -# -# Written: Rose Thompson rose@rosethompson.net -# -# Purpose: Force the HPTW to walk a page table with non-leaf non-zero PBMT bits. This will generate -# a load or store/amo page fault based on the original access type. -# -# A component of the CORE-V-WALLY configurable RISC-V project. -# https://github.com/openhwgroup/cvw -# -# Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You -# may obtain a copy of the License at -# -# https://solderpad.org/licenses/SHL-2.1/ -# -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions -# and limitations under the License. -############################################################################################## - -# load code to initalize stack, handle interrupts, terminate +/////////////////////////////////////////// +// hptwAccessFault.S +// +// Written: Rose Thompson rose@rosethompson.net +// +// Purpose: Force the HPTW to walk a page table with non-leaf non-zero PBMT bits. This will generate +// a load or store/amo page fault based on the original access type. +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +// load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" diff --git a/tests/coverage/pmp.S b/tests/coverage/pmp.S index b4c13527df..9680bfdeb6 100644 --- a/tests/coverage/pmp.S +++ b/tests/coverage/pmp.S @@ -1,8 +1,8 @@ -########################################## -# /content/sample_data/PMPConfigregs.S -# Kevin Box, kbox@hmc.edu -# Created 2023-04-09 23:20:54.863039 -########################################## +/////////////////////////////////////////// +// /content/sample_data/PMPConfigregs.S +// Kevin Box, kbox@hmc.edu +// Created 2023-04-09 23:20:54.863039 +/////////////////////////////////////////// @@ -11,10 +11,10 @@ main: -###########################################################################################################/ -# BEGIN Configuration and Testing Starting at Register: 0 -# -# Configuration +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// BEGIN Configuration and Testing Starting at Register: 0 +// +// Configuration # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments # |0 | 0x2000003f | 0x83 | 1 | 00 | 0 | 1 | 1 | 0 @@ -107,16 +107,16 @@ li t4, 1733894653101739012 csrw pmpcfg2, t4 -# Testing +// Testing -# END Configuration and Testing Starting at Register: 0 -###########################################################################################################/ +// END Configuration and Testing Starting at Register: 0 +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// -###########################################################################################################/ -# BEGIN Configuration and Testing Starting at Register: 1 -# -# Configuration +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// BEGIN Configuration and Testing Starting at Register: 1 +// +// Configuration # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments # |1 | 0x2000003f | 0x83 | 1 | 00 | 0 | 1 | 1 | 0 @@ -209,16 +209,16 @@ li t4, 1155173425015948313 csrw pmpcfg2, t4 -# Testing +// Testing -# END Configuration and Testing Starting at Register: 1 -###########################################################################################################/ +// END Configuration and Testing Starting at Register: 1 +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// -###########################################################################################################/ -# BEGIN Configuration and Testing Starting at Register: 2 -# -# Configuration +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// BEGIN Configuration and Testing Starting at Register: 2 +// +// Configuration # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments # |2 | 0x2000003f | 0x83 | 1 | 00 | 0 | 1 | 1 | 0 @@ -311,16 +311,16 @@ li t4, 576491624729942289 csrw pmpcfg2, t4 -# Testing +// Testing -# END Configuration and Testing Starting at Register: 2 -###########################################################################################################/ +// END Configuration and Testing Starting at Register: 2 +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// -###########################################################################################################/ -# BEGIN Configuration and Testing Starting at Register: 3 -# -# Configuration +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// BEGIN Configuration and Testing Starting at Register: 3 +// +// Configuration # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments # |3 | 0x2000003f | 0x83 | 1 | 00 | 0 | 1 | 1 | 0 @@ -413,16 +413,16 @@ li t4, 7903341188813065 csrw pmpcfg2, t4 -# Testing +// Testing -# END Configuration and Testing Starting at Register: 3 -###########################################################################################################/ +// END Configuration and Testing Starting at Register: 3 +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// -###########################################################################################################/ -# BEGIN Configuration and Testing Starting at Register: 4 -# -# Configuration +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// BEGIN Configuration and Testing Starting at Register: 4 +// +// Configuration # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments # |4 | 0x2000003f | 0x83 | 1 | 00 | 0 | 1 | 1 | 0 @@ -515,16 +515,16 @@ li t4, 2023255344336144641 csrw pmpcfg2, t4 -# Testing +// Testing -# END Configuration and Testing Starting at Register: 4 -###########################################################################################################/ +// END Configuration and Testing Starting at Register: 4 +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// -###########################################################################################################/ -# BEGIN Configuration and Testing Starting at Register: 5 -# -# Configuration +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// BEGIN Configuration and Testing Starting at Register: 5 +// +// Configuration # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments # |5 | 0x2000003f | 0x83 | 1 | 00 | 0 | 1 | 1 | 0 @@ -617,16 +617,16 @@ li t4, 1444534086185583003 csrw pmpcfg2, t4 -# Testing +// Testing -# END Configuration and Testing Starting at Register: 5 -###########################################################################################################/ +// END Configuration and Testing Starting at Register: 5 +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// -###########################################################################################################/ -# BEGIN Configuration and Testing Starting at Register: 6 -# -# Configuration +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// BEGIN Configuration and Testing Starting at Register: 6 +// +// Configuration # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments # |6 | 0x2000003f | 0x83 | 1 | 00 | 0 | 1 | 1 | 0 @@ -719,16 +719,16 @@ li t4, 865844589318216595 csrw pmpcfg2, t4 -# Testing +// Testing -# END Configuration and Testing Starting at Register: 6 -###########################################################################################################/ +// END Configuration and Testing Starting at Register: 6 +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// -###########################################################################################################/ -# BEGIN Configuration and Testing Starting at Register: 7 -# -# Configuration +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// BEGIN Configuration and Testing Starting at Register: 7 +// +// Configuration # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments # |7 | 0x2000003f | 0x83 | 1 | 00 | 0 | 1 | 1 | 0 @@ -821,16 +821,16 @@ li t4, 295285980948829067 csrw pmpcfg2, t4 -# Testing +// Testing -# END Configuration and Testing Starting at Register: 7 -###########################################################################################################/ +// END Configuration and Testing Starting at Register: 7 +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// -###########################################################################################################/ -# BEGIN Configuration and Testing Starting at Register: 8 -# -# Configuration +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// BEGIN Configuration and Testing Starting at Register: 8 +// +// Configuration # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments # |8 | 0x2000003f | 0x83 | 1 | 00 | 0 | 1 | 1 | 0 @@ -923,16 +923,16 @@ li t4, 1806234828062034819 csrw pmpcfg2, t4 -# Testing +// Testing -# END Configuration and Testing Starting at Register: 8 -###########################################################################################################/ +// END Configuration and Testing Starting at Register: 8 +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// -###########################################################################################################/ -# BEGIN Configuration and Testing Starting at Register: 9 -# -# Configuration +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// BEGIN Configuration and Testing Starting at Register: 9 +// +// Configuration # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments # |9 | 0x2000003f | 0x83 | 1 | 00 | 0 | 1 | 1 | 0 @@ -1025,16 +1025,16 @@ li t4, 1227514141142123288 csrw pmpcfg2, t4 -# Testing +// Testing -# END Configuration and Testing Starting at Register: 9 -###########################################################################################################/ +// END Configuration and Testing Starting at Register: 9 +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// -###########################################################################################################/ -# BEGIN Configuration and Testing Starting at Register: 10 -# -# Configuration +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// BEGIN Configuration and Testing Starting at Register: 10 +// +// Configuration # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments # |10 | 0x2000003f | 0x83 | 1 | 00 | 0 | 1 | 1 | 0 @@ -1127,16 +1127,16 @@ li t4, 648970879321184272 csrw pmpcfg2, t4 -# Testing +// Testing -# END Configuration and Testing Starting at Register: 10 -###########################################################################################################/ +// END Configuration and Testing Starting at Register: 10 +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// -###########################################################################################################/ -# BEGIN Configuration and Testing Starting at Register: 11 -# -# Configuration +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// BEGIN Configuration and Testing Starting at Register: 11 +// +// Configuration # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments # |11 | 0x2000003f | 0x83 | 1 | 00 | 0 | 1 | 1 | 0 @@ -1229,16 +1229,16 @@ li t4, 115848442837209096 csrw pmpcfg2, t4 -# Testing +// Testing -# END Configuration and Testing Starting at Register: 11 -###########################################################################################################/ +// END Configuration and Testing Starting at Register: 11 +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// -###########################################################################################################/ -# BEGIN Configuration and Testing Starting at Register: 12 -# -# Configuration +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// BEGIN Configuration and Testing Starting at Register: 12 +// +// Configuration # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments # |12 | 0x2000003f | 0x83 | 1 | 00 | 0 | 1 | 1 | 0 @@ -1331,16 +1331,16 @@ li t4, 11210457292615976960 csrw pmpcfg2, t4 -# Testing +// Testing -# END Configuration and Testing Starting at Register: 12 -###########################################################################################################/ +// END Configuration and Testing Starting at Register: 12 +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// -###########################################################################################################/ -# BEGIN Configuration and Testing Starting at Register: 13 -# -# Configuration +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// BEGIN Configuration and Testing Starting at Register: 13 +// +// Configuration # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments # |13 | 0x2000003f | 0x83 | 1 | 00 | 0 | 1 | 1 | 0 @@ -1433,16 +1433,16 @@ li t4, 10631735484709601308 csrw pmpcfg2, t4 -# Testing +// Testing -# END Configuration and Testing Starting at Register: 13 -###########################################################################################################/ +// END Configuration and Testing Starting at Register: 13 +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// -###########################################################################################################/ -# BEGIN Configuration and Testing Starting at Register: 14 -# -# Configuration +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// BEGIN Configuration and Testing Starting at Register: 14 +// +// Configuration # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments # |14 | 0x2000003f | 0x83 | 1 | 00 | 0 | 1 | 1 | 0 @@ -1535,16 +1535,16 @@ li t4, 10052905250353847316 csrw pmpcfg2, t4 -# Testing +// Testing -# END Configuration and Testing Starting at Register: 14 -###########################################################################################################/ +// END Configuration and Testing Starting at Register: 14 +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// -###########################################################################################################/ -# BEGIN Configuration and Testing Starting at Register: 15 -# -# Configuration +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// BEGIN Configuration and Testing Starting at Register: 15 +// +// Configuration # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments # |15 | 0x2000003f | 0x83 | 1 | 00 | 0 | 1 | 1 | 0 @@ -1637,10 +1637,10 @@ li t4, 9446317844957238284 csrw pmpcfg2, t4 -# Testing +// Testing -# END Configuration and Testing Starting at Register: 15 -###########################################################################################################/ +// END Configuration and Testing Starting at Register: 15 +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// j done diff --git a/tests/coverage/pmpadrdecs.S b/tests/coverage/pmpadrdecs.S index 5b99929316..8e6701d8ec 100644 --- a/tests/coverage/pmpadrdecs.S +++ b/tests/coverage/pmpadrdecs.S @@ -1,6 +1,6 @@ -# pmpadrdecs -# Liam Chalk, lchalk@hmc.edu, 4/27/2023 -# Setting AdrMode to 2 or 3 for pmpadrdecs[0-4] +// pmpadrdecs +// Liam Chalk, lchalk@hmc.edu, 4/27/2023 +// Setting AdrMode to 2 or 3 for pmpadrdecs[0-4] #include "WALLY-init-lib.h" main: diff --git a/tests/coverage/pmpcbo.S b/tests/coverage/pmpcbo.S index 25f16fdaa6..3a76384049 100644 --- a/tests/coverage/pmpcbo.S +++ b/tests/coverage/pmpcbo.S @@ -1,6 +1,6 @@ -# pmpcbo.S -# David_Harris@hmc.edu 1/21/24 -# Cover PMP checks of cache management instructions +// pmpcbo.S +// David_Harris@hmc.edu 1/21/24 +// Cover PMP checks of cache management instructions #include "WALLY-init-lib.h" main: diff --git a/tests/coverage/pmpcfg.S b/tests/coverage/pmpcfg.S index 22cb7a2239..1013439b76 100644 --- a/tests/coverage/pmpcfg.S +++ b/tests/coverage/pmpcfg.S @@ -1,8 +1,8 @@ -# pmpcfg part 1 -# Kevin Wan, kewan@hmc.edu, 4/18/2023 -# Liam Chalk, lchalk@hmc.edu, 4/25/2023 -# locks each pmpXcfg bit field in order, from X = 15 to X = 0, with the A[1:0] field set to TOR. -# See the next part in pmpcfg1.S +// pmpcfg part 1 +// Kevin Wan, kewan@hmc.edu, 4/18/2023 +// Liam Chalk, lchalk@hmc.edu, 4/25/2023 +// locks each pmpXcfg bit field in order, from X = 15 to X = 0, with the A[1:0] field set to TOR. +// See the next part in pmpcfg1.S #include "WALLY-init-lib.h" main: diff --git a/tests/coverage/pmpcfg1.S b/tests/coverage/pmpcfg1.S index b91400ef21..37dcec14b2 100644 --- a/tests/coverage/pmpcfg1.S +++ b/tests/coverage/pmpcfg1.S @@ -1,9 +1,9 @@ -# another set of pmpcfg tests. A new file is made because pmpcfg register fields are -# locked forever after writing 1 to the lock bit for the first time. +// another set of pmpcfg tests. A new file is made because pmpcfg register fields are +// locked forever after writing 1 to the lock bit for the first time. -# Kevin Wan, kewan@hmc.edu, 4/13/2023 -# This set tests locking the pmpXcfg fields in descending order again, without setting the TOR bits. -# for the other part of the tests, see pmpcfg.S +// Kevin Wan, kewan@hmc.edu, 4/13/2023 +// This set tests locking the pmpXcfg fields in descending order again, without setting the TOR bits. +// for the other part of the tests, see pmpcfg.S #include "WALLY-init-lib.h" main: diff --git a/tests/coverage/pmpcfg2.S b/tests/coverage/pmpcfg2.S index ffc380438d..4e0002e6e4 100644 --- a/tests/coverage/pmpcfg2.S +++ b/tests/coverage/pmpcfg2.S @@ -1,7 +1,7 @@ -# pmpcfg part 3 -# Kevin Wan, kewan@hmc.edu, 4/18/2023 -# locks each pmpXcfg bit field in order, from X = 15 to X = 0, with the A[1:0] field set to TOR. -# See the next part in pmpcfg1.S +// pmpcfg part 3 +// Kevin Wan, kewan@hmc.edu, 4/18/2023 +// locks each pmpXcfg bit field in order, from X = 15 to X = 0, with the A[1:0] field set to TOR. +// See the next part in pmpcfg1.S #include "WALLY-init-lib.h" main: diff --git a/tests/coverage/pmppriority.S b/tests/coverage/pmppriority.S index ac8e65c634..8a30c6019d 100644 --- a/tests/coverage/pmppriority.S +++ b/tests/coverage/pmppriority.S @@ -1,15 +1,15 @@ -# pmppriority test cases -# Kevin Wan kewan@hmc.edu 4/27/2023 -# want memory ranges to match: -# 1. only the most significant address and none of the lower ones, -# 2. the most significant address and ANY of the lower ones. +// pmppriority test cases +// Kevin Wan kewan@hmc.edu 4/27/2023 +// want memory ranges to match: +// 1. only the most significant address and none of the lower ones, +// 2. the most significant address and ANY of the lower ones. #include "WALLY-init-lib.h" main: - li t1, 0x21FFFFFF # start at 0x8000000 with a range of 1000000. Address format is set to NAPOT in pmpcfg. + li t1, 0x21FFFFFF // start at 0x8000000 with a range of 1000000. Address format is set to NAPOT in pmpcfg. csrw pmpaddr0, t1 csrw pmpaddr1, t1 csrw pmpaddr2, t1 @@ -30,7 +30,7 @@ main: li t0, 0x1F - csrw pmpcfg0, t0 #set to XWR and NAPOT + csrw pmpcfg0, t0 //set to XWR and NAPOT sw zero, 0(sp) li t0, 0x1F00 diff --git a/tests/coverage/priv.S b/tests/coverage/priv.S index 61417e83e9..1af15add75 100644 --- a/tests/coverage/priv.S +++ b/tests/coverage/priv.S @@ -1,30 +1,30 @@ -########################################## -# priv.S -# -# Written: David_Harris@hmc.edu 23 March 2023 -# -# Purpose: Test coverage for EBU -# -# A component of the CORE-V-WALLY configurable RISC-V project. -# https://github.com/openhwgroup/cvw -# -# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You -# may obtain a copy of the License at -# -# https://solderpad.org/licenses/SHL-2.1/ -# -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions -# and limitations under the License. -############################################################################################## - -# load code to initalize stack, handle interrupts, terminate +/////////////////////////////////////////// +// priv.S +// +// Written: David_Harris@hmc.edu 23 March 2023 +// +// Purpose: Test coverage for EBU +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +// load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" main: diff --git a/tests/coverage/tlbASID.S b/tests/coverage/tlbASID.S index f7fc56e742..bb870429a9 100644 --- a/tests/coverage/tlbASID.S +++ b/tests/coverage/tlbASID.S @@ -1,41 +1,41 @@ -########################################## -# tlbASID.S -# -# Written: mmendozamanriquez@hmc.edu 4 April 2023 -# nlimpert@hmc.edu -# -# Purpose: Test coverage for IFU TLB camlines with mismatched ASID values. This file tests odd -# numbered camlines. tlbASID2.S covers even numbered tlb camlines. These two files are identical. -# -# A component of the CORE-V-WALLY configurable RISC-V project. -# https://github.com/openhwgroup/cvw -# -# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You -# may obtain a copy of the License at -# -# https://solderpad.org/licenses/SHL-2.1/ -# -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions -# and limitations under the License. -############################################################################################## - - - -# load code to initalize stack, handle interrupts, terminate +/////////////////////////////////////////// +// tlbASID.S +// +// Written: mmendozamanriquez@hmc.edu 4 April 2023 +// nlimpert@hmc.edu +// +// Purpose: Test coverage for IFU TLB camlines with mismatched ASID values. This file tests odd +// numbered camlines. tlbASID2.S covers even numbered tlb camlines. These two files are identical. +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + + + +// load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" # run-elf.bash find this in project description main: # Page table root address at 0x80010000 - li t5, 0x9000000000080080 # try making asid = 0. + li t5, 0x9000000000080080 // try making asid = 0. csrw satp, t5 # sfence.vma x0, x0 @@ -47,7 +47,7 @@ main: li t0, 0xC0000000 li t2, 0 # i = 0 - li t5, 0 # j = 0 # now use as a counter for new asid loop + li t5, 0 # j = 0 // now use as a counter for new asid loop li t3, 32 # Max amount of Loops = 32 loop: bge t2, t3, finished # exit loop if i >= loops @@ -56,10 +56,10 @@ loop: bge t2, t3, finished # exit loop if i >= loops sw t1, 0(t0) fence.I jalr t0 - li t5, 0x9001000000080080 # try making asid = 1 + li t5, 0x9001000000080080 // try making asid = 1 csrw satp, t5 jalr t0 - li t5, 0x9000000000080080 # try making asid = 0 + li t5, 0x9000000000080080 // try making asid = 0 csrw satp, t5 li t4, 0x1000 add t0, t0, t4 @@ -75,57 +75,57 @@ finished: pagetable: .8byte 0x200204C1 -.align 12 # level 2 page table, contains direction to a gigapage +.align 12 // level 2 page table, contains direction to a gigapage .8byte 0x0 .8byte 0x0 - .8byte 0x200000CF # gigapage that starts at 8000 0000 goes to C000 0000 - .8byte 0x200208C1 # pointer to next page table entry at 8008 2000 + .8byte 0x200000CF // gigapage that starts at 8000 0000 goes to C000 0000 + .8byte 0x200208C1 // pointer to next page table entry at 8008 2000 -.align 12 # level 1 page table, points to level 0 page table +.align 12 // level 1 page table, points to level 0 page table .8byte 0x20020CC1 -.align 12 # level 0 page table, points to address C000 0000 # FOR NOW ALL OF THESE GO TO 8 instead of C cause they start with 2 - .8byte 0x200000CF # access xC000 0000 - .8byte 0x200004CF # access xC000 1000 - .8byte 0x200008CF # access xC000 2000 - .8byte 0x20000CCF # access xC000 3000 +.align 12 // level 0 page table, points to address C000 0000 // FOR NOW ALL OF THESE GO TO 8 instead of C cause they start with 2 + .8byte 0x200000CF // access xC000 0000 + .8byte 0x200004CF // access xC000 1000 + .8byte 0x200008CF // access xC000 2000 + .8byte 0x20000CCF // access xC000 3000 - .8byte 0x200010CF # access xC000 4000 + .8byte 0x200010CF // access xC000 4000 .8byte 0x200014CF .8byte 0x200018CF .8byte 0x20001CCF - .8byte 0x200020CF # access xC000 8000 + .8byte 0x200020CF // access xC000 8000 .8byte 0x200024CF .8byte 0x200028CF .8byte 0x20002CCF - .8byte 0x200030CF # access xC000 C000 + .8byte 0x200030CF // access xC000 C000 .8byte 0x200034CF .8byte 0x200038CF .8byte 0x20003CCF - .8byte 0x200040CF # access xC001 0000 + .8byte 0x200040CF // access xC001 0000 .8byte 0x200044CF .8byte 0x200048CF .8byte 0x20004CCF - .8byte 0x200050CF # access xC001 4000 + .8byte 0x200050CF // access xC001 4000 .8byte 0x200054CF .8byte 0x200058CF .8byte 0x20005CCF - .8byte 0x200060CF # access xC001 8000 + .8byte 0x200060CF // access xC001 8000 .8byte 0x200064CF .8byte 0x200068CF .8byte 0x20006CCF - .8byte 0x200070CF # access xC001 C000 + .8byte 0x200070CF // access xC001 C000 .8byte 0x200074CF .8byte 0x200078CF .8byte 0x20007CCF - .8byte 0x200080CF # access xC002 0000 + .8byte 0x200080CF // access xC002 0000 .8byte 0x200084CF .8byte 0x200088CF .8byte 0x20008CCF diff --git a/tests/coverage/tlbGLB.S b/tests/coverage/tlbGLB.S index 523b027180..affc4e49d2 100644 --- a/tests/coverage/tlbGLB.S +++ b/tests/coverage/tlbGLB.S @@ -1,40 +1,40 @@ -########################################## -# tlbGLB.S -# -# Written: mmendozamanriquez@hmc.edu 4 April 2023 -# nlimpert@hmc.edu -# Modified: kevin.j.thomas@okstate.edu May/4/20203 -# -# Purpose: Coverage for the Page Table Entry Global flag check. -# -# A component of the CORE-V-WALLY configurable RISC-V project. -# https://github.com/openhwgroup/cvw -# -# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You -# may obtain a copy of the License at -# -# https://solderpad.org/licenses/SHL-2.1/ -# -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions -# and limitations under the License. -############################################################################################## - - -# load code to initalize stack, handle interrupts, terminate +/////////////////////////////////////////// +// tlbGLB.S +// +// Written: mmendozamanriquez@hmc.edu 4 April 2023 +// nlimpert@hmc.edu +// Modified: kevin.j.thomas@okstate.edu May/4/20203 +// +// Purpose: Coverage for the Page Table Entry Global flag check. +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + + +// load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" # run-elf.bash find this in project description main: # Page table root address at 0x80010000 - li t5, 0x9000000000080080 # try making asid = 0. + li t5, 0x9000000000080080 // try making asid = 0. csrw satp, t5 # switch to supervisor mode @@ -42,39 +42,39 @@ main: ecall li t5, 0 # j = 0, run nASID only once - li t3, 32 #Max amount of Loops = 32 - li t4, 0x1000 #offset between addressses. - li t1, 0x00008067 #load in jalr x0 x1 0 instruction to be stored + li t3, 32 //Max amount of Loops = 32 + li t4, 0x1000 //offset between addressses. + li t1, 0x00008067 //load in jalr x0 x1 0 instruction to be stored setup: - li t0, 0xC0000000 #starting address + li t0, 0xC0000000 //starting address li t2, 0 # i = 0 - beq t5, zero, loop #jump to first loop + beq t5, zero, loop //jump to first loop loop2: #jump to each of the addresses in different address space bge t2, t3, done - jalr t0 #jump to instruction at the virtual address - add t0, t0, t4 #change address for next loop - addi t2, t2, 1 #keep track of number of loops ran + jalr t0 //jump to instruction at the virtual address + add t0, t0, t4 //change address for next loop + addi t2, t2, 1 //keep track of number of loops ran j loop2 loop: #store jalr across memory bge t2, t3, nASID # exit loop if i >= loops - sw t1, 0(t0) #stores this jalr in the virtual address - fence.I #invalidate instruction cache - jalr t0 #jump to instruction at the virtual address - add t0, t0, t4 #change address for next loop - addi t2, t2, 1 #keep track of number of loops ran + sw t1, 0(t0) //stores this jalr in the virtual address + fence.I //invalidate instruction cache + jalr t0 //jump to instruction at the virtual address + add t0, t0, t4 //change address for next loop + addi t2, t2, 1 //keep track of number of loops ran j loop nASID: #swap to different address space -> jump to each address - li a0, 3 #swap to machine mode + li a0, 3 //swap to machine mode ecall - li t5, 0x9000100000080080 #swap to address space 1 from 0 + li t5, 0x9000100000080080 //swap to address space 1 from 0 csrw satp, t5 - li a0, 1 # change back to supervisor mode. + li a0, 1 // change back to supervisor mode. ecall - li t5, 1 #flag for finished after loops + li t5, 1 //flag for finished after loops j setup @@ -85,97 +85,97 @@ nASID: #swap to different address space -> jump to each address pagetable: .8byte 0x200204C1 -.align 12 # level 2 page table, contains direction to a gigapageg +.align 12 // level 2 page table, contains direction to a gigapageg .8byte 0x0 .8byte 0x0 - .8byte 0x200000EF # gigapage that starts at 8000 0000 goes to C000 0000 - .8byte 0x200208E1 # pointer to next page table entry at 8008 2000 + .8byte 0x200000EF // gigapage that starts at 8000 0000 goes to C000 0000 + .8byte 0x200208E1 // pointer to next page table entry at 8008 2000 -.align 12 # level 1 page table, points to level 0 page table +.align 12 // level 1 page table, points to level 0 page table .8byte 0x20020CE1 -.align 12 # level 0 page table, points to address C000 0000 # FOR NOW ALL OF THESE GO TO 8 instead of C cause they start with 2 - .8byte 0x200000EF # access xC000 0000 - .8byte 0x200004EF # access xC000 1000 - .8byte 0x200008EF # access xC000 2000 - .8byte 0x20000CEF # access xC000 3000 +.align 12 // level 0 page table, points to address C000 0000 // FOR NOW ALL OF THESE GO TO 8 instead of C cause they start with 2 + .8byte 0x200000EF // access xC000 0000 + .8byte 0x200004EF // access xC000 1000 + .8byte 0x200008EF // access xC000 2000 + .8byte 0x20000CEF // access xC000 3000 - .8byte 0x200010EF # access xC000 4000 + .8byte 0x200010EF // access xC000 4000 .8byte 0x200014EF .8byte 0x200018EF .8byte 0x20001CEF - .8byte 0x200020EF # access xC000 8000 + .8byte 0x200020EF // access xC000 8000 .8byte 0x200024EF .8byte 0x200028EF .8byte 0x20002CEF - .8byte 0x200030EF # access xC000 C000 + .8byte 0x200030EF // access xC000 C000 .8byte 0x200034EF .8byte 0x200038EF .8byte 0x20003CEF - .8byte 0x200040EF # access xC001 0000 + .8byte 0x200040EF // access xC001 0000 .8byte 0x200044EF .8byte 0x200048EF .8byte 0x20004CEF - .8byte 0x200050EF # access xC001 4000 + .8byte 0x200050EF // access xC001 4000 .8byte 0x200054EF .8byte 0x200058EF .8byte 0x20005CEF - .8byte 0x200060EF # access xC001 8000 + .8byte 0x200060EF // access xC001 8000 .8byte 0x200064EF .8byte 0x200068EF .8byte 0x20006CEF - .8byte 0x200070EF # access xC001 C000 + .8byte 0x200070EF // access xC001 C000 .8byte 0x200074eF .8byte 0x200078EF .8byte 0x20007CEF - .8byte 0x200080EF # access xC002 0000 + .8byte 0x200080EF // access xC002 0000 .8byte 0x200084EF .8byte 0x200088EF .8byte 0x20008CEF - .8byte 0x200010EF # access xC000 4000 + .8byte 0x200010EF // access xC000 4000 .8byte 0x200014EF .8byte 0x200018EF .8byte 0x20001CEF - .8byte 0x200020EF # access xC000 8000 + .8byte 0x200020EF // access xC000 8000 .8byte 0x200024EF .8byte 0x200028EF .8byte 0x20002CEF - .8byte 0x200030EF # access xC000 C000 + .8byte 0x200030EF // access xC000 C000 .8byte 0x200034EF .8byte 0x200038EF .8byte 0x20003CEF - .8byte 0x200040EF # access xC001 0000 + .8byte 0x200040EF // access xC001 0000 .8byte 0x200044EF .8byte 0x200048EF .8byte 0x20004CEF - .8byte 0x200050EF # access xC001 4000 + .8byte 0x200050EF // access xC001 4000 .8byte 0x200054EF .8byte 0x200058EF .8byte 0x20005CEF - .8byte 0x200060EF # access xC001 8000 + .8byte 0x200060EF // access xC001 8000 .8byte 0x200064EF .8byte 0x200068EF .8byte 0x20006CEF - .8byte 0x200070EF # access xC001 C000 + .8byte 0x200070EF // access xC001 C000 .8byte 0x200074eF .8byte 0x200078EF .8byte 0x20007CEF - .8byte 0x200080EF # access xC002 0000 + .8byte 0x200080EF // access xC002 0000 .8byte 0x200084EF .8byte 0x200088EF .8byte 0x20008CEF diff --git a/tests/coverage/tlbGP.S b/tests/coverage/tlbGP.S index 58295195b6..da1301cb06 100644 --- a/tests/coverage/tlbGP.S +++ b/tests/coverage/tlbGP.S @@ -1,31 +1,31 @@ -########################################## -# tlbGP.S -# -# Written: mmendozamanriquez@hmc.edu 4 April 2023 -# nlimpert@hmc.edu -# -# Purpose: Create Page tables and access gigapages -# -# A component of the CORE-V-WALLY configurable RISC-V project. -# https://github.com/openhwgroup/cvw -# -# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You -# may obtain a copy of the License at -# -# https://solderpad.org/licenses/SHL-2.1/ -# -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions -# and limitations under the License. -############################################################################################## - -# load code to initalize stack, handle interrupts, terminate +/////////////////////////////////////////// +// tlbGP.S +// +// Written: mmendozamanriquez@hmc.edu 4 April 2023 +// nlimpert@hmc.edu +// +// Purpose: Create Page tables and access gigapages +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +// load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" @@ -41,8 +41,8 @@ main: li a0, 1 ecall li t5, 0 - li t0, 0xC0200000 # go to first gigapage - li t4, 0x40000000 # put this outside the loop. + li t0, 0xC0200000 // go to first gigapage + li t4, 0x40000000 // put this outside the loop. li t2, 0 # i = 0 li t3, 64 # Max amount of Loops = 16 @@ -67,7 +67,7 @@ pagetable: .8byte 0x200044C1 .align 12 - .8byte 0x000000CF #8000 0000 + .8byte 0x000000CF //8000 0000 .8byte 0x100000CF .8byte 0x200000CF .8byte 0x200000CF diff --git a/tests/coverage/tlbKP.S b/tests/coverage/tlbKP.S index 1881f305e0..ca72a16dbd 100644 --- a/tests/coverage/tlbKP.S +++ b/tests/coverage/tlbKP.S @@ -1,31 +1,31 @@ -########################################## -# lsu_test.S -# -# Written: mmendozamanriquez@hmc.edu 4 April 2023 -# nlimpert@hmc.edu -# -# Purpose: Test coverage for LSU -# -# A component of the CORE-V-WALLY configurable RISC-V project. -# https://github.com/openhwgroup/cvw -# -# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You -# may obtain a copy of the License at -# -# https://solderpad.org/licenses/SHL-2.1/ -# -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions -# and limitations under the License. -############################################################################################## - -# load code to initalize stack, handle interrupts, terminate +/////////////////////////////////////////// +// lsu_test.S +// +// Written: mmendozamanriquez@hmc.edu 4 April 2023 +// nlimpert@hmc.edu +// +// Purpose: Test coverage for LSU +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +// load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" @@ -61,7 +61,7 @@ finished: .align 16 # Page table situated at 0x80010000 pagetable: - .8byte 0x200044C1 # old page table was 200040 which just pointed to itself! wrong + .8byte 0x200044C1 // old page table was 200040 which just pointed to itself! wrong .align 12 .8byte 0x0000000000000000 @@ -71,7 +71,7 @@ pagetable: .align 12 .8byte 0x0000000020004CC1 - #.8byte 0x00000200800CF# ADD IN THE MEGAPAGE should 3 nibbles of zeros be removed? + //.8byte 0x00000200800CF// ADD IN THE MEGAPAGE should 3 nibbles of zeros be removed? .align 12 #80000000 diff --git a/tests/coverage/tlbM3.S b/tests/coverage/tlbM3.S index 2cc6b45374..986fb378a8 100644 --- a/tests/coverage/tlbM3.S +++ b/tests/coverage/tlbM3.S @@ -1,31 +1,31 @@ -########################################## -# tlbKP.S -# -# Written: mmendozamanriquez@hmc.edu 4 April 2023 -# nlimpert@hmc.edu -# -# Purpose: Test coverage for LSU -# -# A component of the CORE-V-WALLY configurable RISC-V project. -# https://github.com/openhwgroup/cvw -# -# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You -# may obtain a copy of the License at -# -# https://solderpad.org/licenses/SHL-2.1/ -# -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions -# and limitations under the License. -############################################################################################## - -# load code to initalize stack, handle interrupts, terminate +/////////////////////////////////////////// +// tlbKP.S +// +// Written: mmendozamanriquez@hmc.edu 4 April 2023 +// nlimpert@hmc.edu +// +// Purpose: Test coverage for LSU +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +// load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" @@ -73,7 +73,7 @@ finished: .align 16 # Page table situated at 0x80010000 pagetable: - .8byte 0x200044C1 # old page table was 200040 which just pointed to itself! wrong + .8byte 0x200044C1 // old page table was 200040 which just pointed to itself! wrong .align 12 .8byte 0x00000000200048C1 @@ -83,7 +83,7 @@ pagetable: .align 12 .8byte 0x0000000020004CC1 - #.8byte 0x00000200800CF# ADD IN THE MEGAPAGE should 3 nibbles of zeros be removed? + //.8byte 0x00000200800CF// ADD IN THE MEGAPAGE should 3 nibbles of zeros be removed? .align 12 #80000000 diff --git a/tests/coverage/tlbMP.S b/tests/coverage/tlbMP.S index 72f4af2732..5f35c5879d 100644 --- a/tests/coverage/tlbMP.S +++ b/tests/coverage/tlbMP.S @@ -1,31 +1,31 @@ -########################################## -# tlbMP.S -# -# Written: mmendozamanriquez@hmc.edu 4 April 2023 -# nlimpert@hmc.edu -# -# Purpose: Test coverage for LSU -# -# A component of the CORE-V-WALLY configurable RISC-V project. -# https://github.com/openhwgroup/cvw -# -# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You -# may obtain a copy of the License at -# -# https://solderpad.org/licenses/SHL-2.1/ -# -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions -# and limitations under the License. -############################################################################################## - -# load code to initalize stack, handle interrupts, terminate +/////////////////////////////////////////// +// tlbMP.S +// +// Written: mmendozamanriquez@hmc.edu 4 April 2023 +// nlimpert@hmc.edu +// +// Purpose: Test coverage for LSU +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +// load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" @@ -42,8 +42,8 @@ main: ecall li t5, 0 - li t0, 0x84000000 # go to first megapage - li t4, 0x200000 # put this outside the loop. + li t0, 0x84000000 // go to first megapage + li t4, 0x200000 // put this outside the loop. li t2, 0 # i = 0 li t3, 32 # Max amount of Loops = 16 @@ -72,93 +72,93 @@ pagetable: .8byte 0x00000000200048C1 -.align 12 # megapages starting at 8000 0000 going to 8480 0000 (32*2 MiB beyond that) +.align 12 // megapages starting at 8000 0000 going to 8480 0000 (32*2 MiB beyond that) - .8byte 0x200000CF # access 8000,0000 - .8byte 0x200800CF # access 8020,0000 - .8byte 0x201000CF # acesss 8040,0000 - .8byte 0x201800CF # acesss 8060,0000 + .8byte 0x200000CF // access 8000,0000 + .8byte 0x200800CF // access 8020,0000 + .8byte 0x201000CF // acesss 8040,0000 + .8byte 0x201800CF // acesss 8060,0000 - .8byte 0x202000CF # access 8080,0000 - .8byte 0x202800CF # access 80A0,0000 - .8byte 0x203000CF # access 80C0,0000 - .8byte 0x203800CF # access 80E0,0000 + .8byte 0x202000CF // access 8080,0000 + .8byte 0x202800CF // access 80A0,0000 + .8byte 0x203000CF // access 80C0,0000 + .8byte 0x203800CF // access 80E0,0000 - .8byte 0x204000CF # access 8100,0000 + .8byte 0x204000CF // access 8100,0000 .8byte 0x204800CF .8byte 0x205000CF .8byte 0x205800CF - .8byte 0x206000CF # access 8180,0000 + .8byte 0x206000CF // access 8180,0000 .8byte 0x206800CF .8byte 0x207000CF .8byte 0x207800CF - .8byte 0x208000CF # access 8200,0000 + .8byte 0x208000CF // access 8200,0000 .8byte 0x208800CF .8byte 0x209000CF .8byte 0x209800CF - .8byte 0x20A000CF # access 8280,0000 + .8byte 0x20A000CF // access 8280,0000 .8byte 0x20A800CF .8byte 0x20B000CF .8byte 0x20B800CF - .8byte 0x20C000CF # access 8300,0000 + .8byte 0x20C000CF // access 8300,0000 .8byte 0x20C800CF .8byte 0x20D000CF .8byte 0x20D800CF - .8byte 0x20E000CF # access 8380,0000 + .8byte 0x20E000CF // access 8380,0000 .8byte 0x20E800CF .8byte 0x20F000CF .8byte 0x20F800CF - .8byte 0x200000CF # access 8000,0000 I AM REPEATING PTE TO SAVE TIME. - .8byte 0x200800CF # access 8020,0000 - .8byte 0x201000CF # acesss 8040,0000 - .8byte 0x201800CF # acesss 8060,0000 + .8byte 0x200000CF // access 8000,0000 I AM REPEATING PTE TO SAVE TIME. + .8byte 0x200800CF // access 8020,0000 + .8byte 0x201000CF // acesss 8040,0000 + .8byte 0x201800CF // acesss 8060,0000 - .8byte 0x202000CF # access 8080,0000 - .8byte 0x202800CF # access 80A0,0000 - .8byte 0x203000CF # access 80C0,0000 - .8byte 0x203800CF # access 80E0,0000 + .8byte 0x202000CF // access 8080,0000 + .8byte 0x202800CF // access 80A0,0000 + .8byte 0x203000CF // access 80C0,0000 + .8byte 0x203800CF // access 80E0,0000 - .8byte 0x204000CF # access 8100,0000 + .8byte 0x204000CF // access 8100,0000 .8byte 0x204800CF .8byte 0x205000CF .8byte 0x205800CF - .8byte 0x206000CF # access 8180,0000 + .8byte 0x206000CF // access 8180,0000 .8byte 0x206800CF .8byte 0x207000CF .8byte 0x207800CF - .8byte 0x208000CF # access 8200,0000 + .8byte 0x208000CF // access 8200,0000 .8byte 0x208800CF .8byte 0x209000CF .8byte 0x209800CF - .8byte 0x20A000CF # access 8280,0000 + .8byte 0x20A000CF // access 8280,0000 .8byte 0x20A800CF .8byte 0x20B000CF .8byte 0x20B800CF - .8byte 0x20C000CF # access 8300,0000 + .8byte 0x20C000CF // access 8300,0000 .8byte 0x20C800CF .8byte 0x20D000CF .8byte 0x20D800CF - .8byte 0x20E000CF # access 8380,0000 + .8byte 0x20E000CF // access 8380,0000 .8byte 0x20E800CF .8byte 0x20F000CF .8byte 0x20F800CF .8byte 0x20004CC1 - # Kilopage entry, for addresses from 8400, 0000 to 841F, FFFF - # point to ... + // Kilopage entry, for addresses from 8400, 0000 to 841F, FFFF + // point to ... -.align 12 # should start at 84000000 +.align 12 // should start at 84000000 .8byte 0x210000CF .8byte 0x210004CF .8byte 0x210008CF diff --git a/tests/coverage/tlbMisaligned.S b/tests/coverage/tlbMisaligned.S index 6c72a6be82..13506646d1 100644 --- a/tests/coverage/tlbMisaligned.S +++ b/tests/coverage/tlbMisaligned.S @@ -1,30 +1,30 @@ -########################################## -# tlbMisaligned.S -# -# Written: Rose Thompson rose@rosethompson.net -# -# Purpose: Create a page table with misaligned load and store access. Checks TLB misses prevent misaligned load/store fault. -# -# A component of the CORE-V-WALLY configurable RISC-V project. -# https://github.com/openhwgroup/cvw -# -# Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You -# may obtain a copy of the License at -# -# https://solderpad.org/licenses/SHL-2.1/ -# -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions -# and limitations under the License. -############################################################################################## - -# load code to initalize stack, handle interrupts, terminate +/////////////////////////////////////////// +// tlbMisaligned.S +// +// Written: Rose Thompson rose@rosethompson.net +// +// Purpose: Create a page table with misaligned load and store access. Checks TLB misses prevent misaligned load/store fault. +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +// load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" @@ -46,8 +46,8 @@ main: ecall li t5, 0 li t2, 0x1000 - li t0, 0x1000 # go to first gigapage - li t4, 0x40000000 # put this outside the loop. + li t0, 0x1000 // go to first gigapage + li t4, 0x40000000 // put this outside the loop. lw t1, 1(t0) # load a misaligned aligned cached address li t1, 0x00008067 #load in jalr @@ -79,7 +79,7 @@ pagetable: .align 12 .8byte 0x0000000020004CC1 - #.8byte 0x00000200800CF# ADD IN THE MEGAPAGE should 3 nibbles of zeros be removed? + //.8byte 0x00000200800CF// ADD IN THE MEGAPAGE should 3 nibbles of zeros be removed? .align 12 #80000000 diff --git a/tests/coverage/tlbNAPOT.S b/tests/coverage/tlbNAPOT.S index 68fb08d317..c38472ad09 100644 --- a/tests/coverage/tlbNAPOT.S +++ b/tests/coverage/tlbNAPOT.S @@ -1,32 +1,32 @@ -########################################## -# tlbNAPOT.S -# -# Written: mmendozamanriquez@hmc.edu 4 April 2023 -# nlimpert@hmc.edu -# Adapted David_Harris@hmc.edu 8/29/23 to exercise NAPOT huge pages -# -# Purpose: Test coverage for LSU NAPOT -# -# A component of the CORE-V-WALLY configurable RISC-V project. -# https://github.com/openhwgroup/cvw -# -# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You -# may obtain a copy of the License at -# -# https://solderpad.org/licenses/SHL-2.1/ -# -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions -# and limitations under the License. -############################################################################################## - -# load code to initalize stack, handle interrupts, terminate +/////////////////////////////////////////// +// tlbNAPOT.S +// +// Written: mmendozamanriquez@hmc.edu 4 April 2023 +// nlimpert@hmc.edu +// Adapted David_Harris@hmc.edu 8/29/23 to exercise NAPOT huge pages +// +// Purpose: Test coverage for LSU NAPOT +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +// load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" @@ -138,7 +138,7 @@ ipf: .align 16 # root Page table situated at 0x80010000 pagetable: - .8byte 0x200044C1 # old page table was 200040 which just pointed to itself! wrong + .8byte 0x200044C1 // old page table was 200040 which just pointed to itself! wrong # next page table at 0x80011000 .align 12 diff --git a/tests/coverage/tlbTP.S b/tests/coverage/tlbTP.S index 45f751745b..89b5d1ec7a 100644 --- a/tests/coverage/tlbTP.S +++ b/tests/coverage/tlbTP.S @@ -1,31 +1,31 @@ -########################################## -# tlbTP.S -# -# Written: mmendozamanriquez@hmc.edu 4 April 2023 -# nlimpert@hmc.edu -# -# Purpose: Test coverage for LSU -# -# A component of the CORE-V-WALLY configurable RISC-V project. -# https://github.com/openhwgroup/cvw -# -# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You -# may obtain a copy of the License at -# -# https://solderpad.org/licenses/SHL-2.1/ -# -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions -# and limitations under the License. -############################################################################################## - -# load code to initalize stack, handle interrupts, terminate +/////////////////////////////////////////// +// tlbTP.S +// +// Written: mmendozamanriquez@hmc.edu 4 April 2023 +// nlimpert@hmc.edu +// +// Purpose: Test coverage for LSU +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +// load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" @@ -41,8 +41,8 @@ main: li a0, 1 ecall li t5, 0 - li t0, 0x80000000 # go to first gigapage - li t4, 0x8000000000 # put this outside the loop. + li t0, 0x80000000 // go to first gigapage + li t4, 0x8000000000 // put this outside the loop. li t2, 0 # i = 0 li t3, 64 # run through 64 PTEs diff --git a/tests/coverage/tlbmisc.S b/tests/coverage/tlbmisc.S index d47678dbd9..9e660bdc44 100644 --- a/tests/coverage/tlbmisc.S +++ b/tests/coverage/tlbmisc.S @@ -1,30 +1,30 @@ -########################################## -# tlbmisc.S -# -# Written David_Harris@hmc.edu 1/1/24 -# -# Purpose: Test coverage for other TLB issues -# -# A component of the CORE-V-WALLY configurable RISC-V project. -# https://github.com/openhwgroup/cvw -# -# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You -# may obtain a copy of the License at -# -# https://solderpad.org/licenses/SHL-2.1/ -# -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions -# and limitations under the License. -############################################################################################## - -# load code to initalize stack, handle interrupts, terminate +/////////////////////////////////////////// +// tlbmisc.S +// +// Written David_Harris@hmc.edu 1/1/24 +// +// Purpose: Test coverage for other TLB issues +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +// load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" diff --git a/tests/coverage/vm64check.S b/tests/coverage/vm64check.S index 1b8d73aff5..0cc16ef8d5 100644 --- a/tests/coverage/vm64check.S +++ b/tests/coverage/vm64check.S @@ -1,34 +1,34 @@ -########################################## -# vm64check.S -# -# Written: David_Harris@hmc.edu 7 April 2023 -# -# Purpose: vm64check coverage -# -# A component of the CORE-V-WALLY configurable RISC-V project. -# https://github.com/openhwgroup/cvw -# -# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You -# may obtain a copy of the License at -# -# https://solderpad.org/licenses/SHL-2.1/ -# -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions -# and limitations under the License. -############################################################################################## - -# Cover IMMU vm64check block by jumping to illegal virtual addresses -# Need a nonstandard trap handler to deal with returns from theses jumps -# assign eq_46_38 = &(VAdr[46:38]) | ~|(VAdr[46:38]); - # assign eq_63_47 = &(VAdr[63:47]) | ~|(VAdr[63:47]); - # assign UpperBitsUnequal = SV39Mode ? ~(eq_63_47 & eq_46_38) : ~eq_63_47; +/////////////////////////////////////////// +// vm64check.S +// +// Written: David_Harris@hmc.edu 7 April 2023 +// +// Purpose: vm64check coverage +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +// Cover IMMU vm64check block by jumping to illegal virtual addresses +// Need a nonstandard trap handler to deal with returns from theses jumps +// assign eq_46_38 = &(VAdr[46:38]) | ~|(VAdr[46:38]); + // assign eq_63_47 = &(VAdr[63:47]) | ~|(VAdr[63:47]); + // assign UpperBitsUnequal = SV39Mode ? ~(eq_63_47 & eq_46_38) : ~eq_63_47; .section .text.init .global rvtest_entry_point @@ -47,9 +47,9 @@ rvtest_entry_point: # SATP in non-39 mode csrw satp, zero - # vm64check coverage + // vm64check coverage check1: - # check virtual addresses with bits 63:47 and/or 46:38 being equal or unequal + // check virtual addresses with bits 63:47 and/or 46:38 being equal or unequal li t0, 0x00000001800F0000 # unimplemented memory with upper and lower all zero la ra, check2 jalr t0 @@ -79,7 +79,7 @@ check11: li t0, 0x8000000000000000 csrw satp, t0 - # check virtual addresses with bits 63:47 and/or 46:38 being equal or unequal + // check virtual addresses with bits 63:47 and/or 46:38 being equal or unequal li t0, 0x00000001800F0000 # unimplemented memory with upper and lower all zero la ra, check12 jalr t0