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	(text "This outputs at 3.3V logic levels, which\nare compatible with the Sega's 5V TTL\nsystem.  We rely on this fact so that\nthe cart can remain compatible with both\nthe Sega and the FlashKit programmer.\nIf we made the right side 5V, then the\nminimum high level for data input would\nbe 3.5V (VccB * 0.7), which would cause\n3.3V inputs not to work right.\n\nBy using 3.3V on both sides, we can\ntake advantage of the chip's 5V-\ntolerant input so that anything over\n3.3V * 0.7 (= 2.31V) is considered\nhigh, and the input when writing can\nbe 3.3V."
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	(text "~{OE} is connected to ~{CE_3V} via ~{DATA_OE_INT}\nand ~{CE_3V_INT}.  Throughput (in either direction)\nwill be enabled any time the address space\nindicates reading or writing flash (0-2MB)."
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	(text "DIR is high,\ndata always flows\nA => B."
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	(text "These bridges can be used to snoop on these signals,\nor cut with a knife to hijack them."
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	(text "This is where the cartridge \"ROM\" image is stored.\nNot an actual ROM, or EPROM, but Flash RAM,\nwhich is way cheaper.\n\nMaximum ROM size is 2MB.\n\nThe flash chip is compatible with the Krikzz\nFlashkit MD Programmer.  This chip gets its own\nvoltage regulator so that this base cartridge\nboard can be programmed directly without any\nother boards attached.\n\nThis 3.3V chip talks through a series of level\ntranslators.  Because the FlashKit programmer\nuses 3.3V logic, all inputs to this sheet must\nwork as either 5V or 3.3V.  The translators\nwill tolerate 5V input at all supply voltages,\nso we supply both sides with 3.3V.\n\nIf we used 5V for VccA, then the minimum high\nlevel for input would 3.5V (VCC * 0.7), and the\nlevels from our 3.3V programmer would not work.\n\nThis arrangement allows for compatibility with\nboth 3.3V signals from the FlashKit Programmer\nand 5V signals from the Sega."
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	(text "DIR is high to pass data from A to B.\nDIR is connected to ~{WE} via DATA_DIR_INT.\n~{WE} is high when we're reading.\nTherefore the reading side (flash chip side)\nshould be A."
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	(text "DIR is high,\ndata always flows\nA => B."
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