Applicability to the other Amiga custom chips

[DavidGriffith]

How much of this do you expect this project to be directly applicable to producing similar hardware for the other Amiga custom chips?

[jbilander]

Hi,

FPGA re-implementation of the custom chips Denise, Buster and Gary is already done (not by me) and the 8250 CIA is being worked on by a couple of persons, for example Niklas. Left to-do is Paula, but I think no publicly available schematics exists of her and that is why she hasn't been implemented as a drop-in replacement by anyone so far. There is no point in designing a PCB for Paula if there's no one who knows how to implement her in HDL (as a standalone chip). Paula was implemented in the minimig project but that is together with the other custom chips in the one and same FPGA, a standalone drop-in replacement is a different beast.

Denise (Martin Åberg, https://github.com/endofexclusive/deniser)
Gary (Matthias Heinrichs, https://gitlab.com/MHeinrichs)
Buster (Matt Harlum, https://github.com/LIV2/Bluster)
CIA (Niklas Ekström, https://github.com/niklasekstrom/cia-verilog)

[niklasekstrom]

I think Frederic Requin mentioned that his Paula implementation (https://github.com/nonarkitten/amiga_replacement_project/blob/master/paula/Paula.v) has been tested to work as a stand-alone chip.

Otherwise adopting the Paula code from Minimig (https://github.com/MiSTer-devel/Minimig-AGA_MiSTer/tree/MiSTer/rtl) should be doable.

[DavidGriffith]

I'm aware of those other projects doing fpga reimplementation. I was curious about the other half of such efforts, the creation of physical hardware to receive the programming and then drop into an Amiga.

[jbilander]

Hi,

The creation of the physical hardware, designing a PCB with an FPGA and some level shifters, is the easy part in this case. The hard part is to implement the HDL so that the FPGA behaves just like the original chip produced by Commodore, not to mention all the testing needed to verify that it is 100% compatible. Often you need timing diagrams/specifications/equations or you'll have to do some serious trial and error reverse engineering of all the signals from the original chip. That is very time-consuming work.

[mbtaylor1982]

@jbilander I'm working on a reimplementation of the SDMAC rev4 and wanted to see if you'd be interested in helping adapt this design for that purpose. The Verilog is at an advanced stage and my test bench code shows several of the modules appear to work as expected. if interested let me know.

[jbilander]

Hi, great work. I have limited time right now since I focus my spare time on development for the SF2000 card, but I can help if you have questions and perhaps later in a month or so I will have more spare time to help adapt a PCB design. The Intel 10 Max FPGAs are not in stock anywhere, and that has been the case for a long time now, so the first thing you need to decide on is what FPGA to use. Also BGA-packaging is not so DIY friendly, so that is worth considering as well when designing. Right now Trion and Gowin FPGAs are available.