-
Notifications
You must be signed in to change notification settings - Fork 0
/
vga_buffer_beh.vhd
executable file
·206 lines (146 loc) · 5.67 KB
/
vga_buffer_beh.vhd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
----------------------------------------------------------------------------------
-- LIBRARIES --
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
----------------------------------------------------------------------------------
-- ARCHITECTURE --
----------------------------------------------------------------------------------
architecture beh of vga_buffer is
constant T_HBP : integer := 216;
constant T_HFP : integer := 40;
constant T_EP : integer := 800;
constant T_VBP : integer := 35;
constant T_VFP : integer := 10;
constant COLOR_BIT_WIDTH : integer := 3 * COLOR_DATA_WIDTH;
type VGA_STATE_TYPE is
(
INIT_VGA,
VGA_EXECUTE
);
type HSYNC_STATE_TYPE is
(
HSYNC_START,
HSYNC_PULLHIGH,
HSYNC_EXECUTE,
HSYNC_FRONTPORCH
);
type VSYNC_STATE_TYPE is
(
VSYNC_START,
VSYNC_PULLHIGH,
VSYNC_EXECUTE,
VSYNC_FRONTPORCH
);
signal clk_cnt, clk_cnt_next : integer := 0;
signal vga_state, vga_state_next : VGA_STATE_TYPE := INIT_VGA;
signal hsync_state, hsync_state_next : HSYNC_STATE_TYPE := HSYNC_START;
signal hsync_ctr, hsync_ctr_next : integer := 0;
signal vsync_state, vsync_state_next : VSYNC_STATE_TYPE := VSYNC_START;
signal vsync_ctr, vsync_ctr_next : integer := 0;
begin
vga_proc : process(clk,vga_state,hsync_state,vsync_state,clk_cnt,hsync_ctr,vsync_ctr,rdata1)
begin
vga_state_next <= vga_state;
hsync_state_next <= hsync_state;
vsync_state_next <= vsync_state;
clk_cnt_next <= clk_cnt;
hsync_ctr_next <= hsync_ctr;
vsync_ctr_next <= vsync_ctr;
rd1 <= '0';
hsync <= '0';
vsync <= '0';
den <= '0';
r <= (others => '0');
g <= (others => '0');
b <= (others => '0');
raddr1 <= (others => '0');
case vga_state is
when INIT_VGA =>
hsync <= '1';
vsync <= '1';
den <= '0';
vga_state_next <= VGA_EXECUTE;
hsync_state_next <= HSYNC_START;
vsync_state_next <= VSYNC_START;
when VGA_EXECUTE =>
-- PULL VSYNC HIGH --
case vsync_state is
when VSYNC_START =>
vsync_state_next <= VSYNC_PULLHIGH;
clk_cnt_next <= 0;
den <= '0';
vsync_ctr_next <= 0;
when VSYNC_PULLHIGH =>
vsync <= '1';
if (clk_cnt = T_VBP) then
vsync_state_next <= VSYNC_EXECUTE;
hsync_state_next <= HSYNC_START;
clk_cnt_next <= 0;
end if;
when VSYNC_EXECUTE =>
case hsync_state is
when HSYNC_START =>
hsync_state_next <= HSYNC_PULLHIGH;
clk_cnt_next <= 0;
when HSYNC_PULLHIGH =>
hsync <= '1';
if (clk_cnt = T_HBP) then
hsync_state_next <= HSYNC_EXECUTE;
clk_cnt_next <= 0;
hsync_ctr_next <= 0;
end if;
when HSYNC_EXECUTE =>
den <= '1';
rd1 <= '1';
raddr1 <= std_logic_vector( to_unsigned( vsync_ctr * V_PIXEL + clk_cnt , RAM_DATA_WIDTH ) );
-- OUTPUT BUFFER TO RGB --
r <= rdata1( COLOR_DATA_WIDTH * 3 - 1 downto COLOR_DATA_WIDTH * 2 );
g <= rdata1( COLOR_DATA_WIDTH * 2 - 1 downto COLOR_DATA_WIDTH );
b <= rdata1( COLOR_DATA_WIDTH - 1 downto 0 );
if (clk_cnt = T_EP) then
hsync_state_next <= HSYNC_FRONTPORCH;
clk_cnt_next <= 0;
end if;
when HSYNC_FRONTPORCH =>
den <= '0';
if (clk_cnt = T_HFP) then
vsync_state_next <= VSYNC_FRONTPORCH;
clk_cnt_next <= 0;
end if;
end case;
when VSYNC_FRONTPORCH =>
if (clk_cnt = T_VFP) then
if(vsync_ctr < V_PIXEL) then
vsync_ctr_next <= vsync_ctr + 1;
else
vsync_ctr_next <= 0;
end if;
vsync_state_next <= VSYNC_START;
end if;
end case;
end case;
end process vga_proc;
vga_sync : process(clk, res_n,vga_state_next,hsync_state_next,hsync_ctr_next,vsync_state_next,vsync_ctr_next,clk_cnt_next)
begin
if res_n = '0' then
vga_state <= INIT_VGA;
hsync_state <= HSYNC_START;
vsync_state <= VSYNC_START;
hsync_ctr <= 0;
vsync_ctr <= 0;
clk_cnt <= 0;
nclk <= '0';
elsif rising_edge(clk) then
vga_state <= vga_state_next;
hsync_state <= hsync_state_next;
hsync_ctr <= hsync_ctr_next;
vsync_state <= vsync_state_next;
vsync_ctr <= vsync_ctr_next;
clk_cnt <= clk_cnt_next + 1;
nclk <= clk;
end if;
end process vga_sync;
end architecture beh;
--- EOF ---