New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Logic gates bugging? #1362

Open

Kzitold opened this issue Nov 7, 2024 · 2 comments

Kzitold commented Nov 7, 2024

2024-11-07.18-36-32.mp4

Owner

hneemann commented Nov 8, 2024

What do you expect with a CMOS gate if one of the inputs is left open? See #665

Author

Kzitold commented Nov 8, 2024 •

edited

Loading

What do you expect with a CMOS gate if one of the inputs is left open? See #665

What's a CMOS-gate?

Edit: Ohh... The randomness is intentional.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment