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port_map.hpp
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#pragma once
//=========================================================================//
/*! @file
@brief RX671 グループ・ポート・マッピング @n
・ペリフェラル型に従って、ポートの設定をグループ化して設定
@author 平松邦仁 ([email protected])
@copyright Copyright (C) 2024 Kunihito Hiramatsu @n
Released under the MIT license @n
https://github.com/hirakuni45/RX/blob/master/LICENSE
*/
//=========================================================================//
#include "RX671/peripheral.hpp"
#include "RX671/port.hpp"
#include "RX671/mpc.hpp"
#include "RX600/port_map_order.hpp"
namespace device {
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++//
/*!
@brief RX671 ポート・マッピング・ユーティリティー
*/
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++//
class port_map : public port_map_order {
static bool cmtw0_(ORDER odr, bool enable, OPTIONAL opt) noexcept
{
switch(odr) {
case ORDER::FIRST:
if(opt == OPTIONAL::CMTW_TOC0) {
// TOC0: PC7
PORTC::PMR.B7 = 0;
MPC::PC7PFS.PSEL = enable ? 0b01'1101 : 0;
PORTC::PMR.B7 = enable;
} else if(opt == OPTIONAL::CMTW_TIC0) {
// TIC0: PC6
PORTC::PMR.B6 = 0;
MPC::PC6PFS.PSEL = enable ? 0b01'1101 : 0;
PORTC::PMR.B6 = enable;
} else if(opt == OPTIONAL::CMTW_TOC1) {
// TOC1: PE7
PORTE::PMR.B7 = 0;
MPC::PE7PFS.PSEL = enable ? 0b01'1101 : 0;
PORTE::PMR.B7 = enable;
} else if(opt == OPTIONAL::CMTW_TIC1) {
// TIC1: PE6
PORTE::PMR.B6 = 0;
MPC::PE6PFS.PSEL = enable ? 0b01'1101 : 0;
PORTE::PMR.B6 = enable;
} else {
return false;
}
default:
return false;
}
return true;
}
static bool cmtw1_(ORDER odr, bool enable, OPTIONAL opt) noexcept
{
switch(odr) {
case ORDER::FIRST:
if(opt == OPTIONAL::CMTW_TOC0) {
// TOC2: PD3
PORTD::PMR.B3 = 0;
MPC::PD3PFS.PSEL = enable ? 0b01'1101 : 0;
PORTD::PMR.B3 = enable;
} else if(opt == OPTIONAL::CMTW_TIC0) {
// TIC2: PD2
PORTD::PMR.B2 = 0;
MPC::PD2PFS.PSEL = enable ? 0b01'1101 : 0;
PORTD::PMR.B2 = enable;
} else if(opt == OPTIONAL::CMTW_TOC1) {
// TOC3: PE3
PORTE::PMR.B3 = 0;
MPC::PE3PFS.PSEL = enable ? 0b01'1101 : 0;
PORTE::PMR.B3 = enable;
} else if(opt == OPTIONAL::CMTW_TIC1) {
// TIC3: PE2
PORTE::PMR.B2 = 0;
MPC::PE2PFS.PSEL = enable ? 0b01'1101 : 0;
PORTE::PMR.B2 = enable;
} else {
return false;
}
default:
return false;
}
return true;
}
static bool sci0_(ORDER odr, bool enable, OPTIONAL opt) noexcept
{
uint8_t i2c = 0;
bool spi = false;
if(opt == OPTIONAL::SCI_I2C) { i2c = 1; }
else if(opt == OPTIONAL::SCI_SPI) { spi = true; }
uint8_t sel = enable ? 0b00'1010 : 0;
switch(odr) {
case ORDER::FIRST:
// RXD0: P21
// TXD0: P20
// SCK0: P22
PORT2::PMR.B1 = 0;
PORT2::PDR.B1 = i2c;
MPC::P21PFS.PSEL = sel; // ok
PORT2::PMR.B1 = enable;
PORT2::PMR.B0 = 0;
PORT2::ODR.B0 = i2c;
MPC::P20PFS.PSEL = sel; // ok
PORT2::PMR.B0 = enable;
if(spi) {
PORT2::PMR.B2 = 0;
MPC::P22PFS.PSEL = sel; // ok
PORT2::PMR.B2 = enable;
}
break;
case ORDER::SECOND:
// RXD0: P33
// TXD0: P32
// SCK0: P34
PORT3::PMR.B3 = 0;
PORT3::ODR.B3 = i2c;
MPC::P33PFS.PSEL = sel; // ok
PORT3::PMR.B3 = enable;
PORT3::PMR.B2 = 0;
PORT3::ODR.B2 = i2c;
MPC::P32PFS.PSEL = sel; // ok
PORT3::PMR.B2 = enable;
if(spi) {
PORT3::PMR.B4 = 0;
MPC::P34PFS.PSEL = sel; // ok
PORT3::PMR.B4 = enable;
}
break;
default:
return false;
}
return true;
}
static bool sci1_(ORDER odr, bool enable, OPTIONAL opt) noexcept
{
uint8_t i2c = 0;
bool spi = false;
if(opt == OPTIONAL::SCI_I2C) { i2c = 1; }
else if(opt == OPTIONAL::SCI_SPI) { spi = true; }
uint8_t sel = enable ? 0b00'1010 : 0;
switch(odr) {
case ORDER::FIRST:
// RXD1: P15
// TXD1: P16
// SCK1: P17
PORT1::PMR.B5 = 0;
PORT1::PDR.B5 = i2c;
MPC::P15PFS.PSEL = sel; // ok
PORT1::PMR.B5 = enable;
PORT1::PMR.B6 = 0;
PORT1::ODR.B6 = i2c;
MPC::P16PFS.PSEL = sel; // ok
PORT1::PMR.B6 = enable;
if(spi) {
PORT1::PMR.B7 = 0;
MPC::P17PFS.PSEL = sel; // ok
PORT1::PMR.B7 = enable;
}
break;
case ORDER::SECOND:
// RXD1: P30
// TXD1: P26
// SCK1: P27
PORT3::PMR.B0 = 0;
PORT3::ODR.B0 = i2c;
MPC::P30PFS.PSEL = sel; // ok
PORT3::PMR.B0 = enable;
PORT2::PMR.B6 = 0;
PORT2::ODR.B6 = i2c;
MPC::P26PFS.PSEL = sel; // ok
PORT2::PMR.B6 = enable;
if(spi) {
PORT2::PMR.B7 = 0;
MPC::P27PFS.PSEL = sel; // ok
PORT2::PMR.B7 = enable;
}
break;
default:
return false;
}
return true;
}
static bool sci2_(ORDER odr, bool enable, OPTIONAL opt) noexcept
{
uint8_t i2c = 0;
bool spi = false;
if(opt == OPTIONAL::SCI_I2C) { i2c = 1; }
else if(opt == OPTIONAL::SCI_SPI) { spi = true; }
uint8_t sel = enable ? 0b00'1010 : 0;
switch(odr) {
case ORDER::FIRST:
// RXD2: P12
// TXD2: P13
// SCK2: P51
PORT1::PMR.B2 = 0;
PORT1::ODR.B2 = i2c;
MPC::P12PFS.PSEL = sel; // ok
PORT1::PMR.B2 = enable;
PORT1::PMR.B3 = 0;
PORT1::ODR.B3 = i2c;
MPC::P13PFS.PSEL = sel; // ok
PORT1::PMR.B3 = enable;
if(spi) {
PORT5::PMR.B1 = 0;
MPC::P51PFS.PSEL = sel; // ok
PORT5::PMR.B1 = enable;
}
break;
case ORDER::SECOND:
// RXD2: P52
// TXD2: P50
// SCK2: P51
PORT5::PMR.B2 = 0;
PORT5::ODR.B2 = i2c;
MPC::P52PFS.PSEL = sel; // ok
PORT5::PMR.B2 = enable;
PORT5::PMR.B0 = 0;
PORT5::ODR.B0 = i2c;
MPC::P50PFS.PSEL = sel; // ok
PORT5::PMR.B0 = enable;
if(spi) {
PORT5::PMR.B1 = 0;
MPC::P51PFS.PSEL = sel; // ok
PORT5::PMR.B1 = enable;
}
break;
default:
return false;
}
return true;
}
static bool sci3_(ORDER odr, bool enable, OPTIONAL opt) noexcept
{
uint8_t i2c = 0;
bool spi = false;
if(opt == OPTIONAL::SCI_I2C) { i2c = 1; }
else if(opt == OPTIONAL::SCI_SPI) { spi = true; }
uint8_t sel = 0;
switch(odr) {
case ORDER::FIRST:
// RXD3: P16
// TXD3: P17
// SCK3: P15
sel = enable ? 0b00'1011 : 0;
PORT1::PMR.B6 = 0;
PORT1::ODR.B6 = i2c;
MPC::P16PFS.PSEL = sel; // ok
PORT1::PMR.B6 = enable;
PORT1::PMR.B7 = 0;
PORT1::ODR.B7 = i2c;
MPC::P17PFS.PSEL = sel; // ok
PORT1::PMR.B7 = enable;
if(spi) {
PORT1::PMR.B5 = 0;
MPC::P15PFS.PSEL = sel; // ok
PORT1::PMR.B5 = enable;
}
break;
case ORDER::SECOND:
// RXD3: P25
// TXD3: P23
// SCK3: P24
sel = enable ? 0b00'1010 : 0;
PORT2::PMR.B5 = 0;
PORT2::ODR.B5 = i2c;
MPC::P25PFS.PSEL = sel; // ok
PORT2::PMR.B5 = enable;
PORT2::PMR.B3 = 0;
PORT2::ODR.B3 = i2c;
MPC::P23PFS.PSEL = sel; // ok
PORT2::PMR.B3 = enable;
if(spi) {
PORT2::PMR.B4 = 0;
MPC::P24PFS.PSEL = sel; // ok
PORT2::PMR.B4 = enable;
}
break;
default:
return false;
}
return true;
}
static bool sci4_(ORDER odr, bool enable, OPTIONAL opt) noexcept
{
uint8_t i2c = 0;
bool spi = false;
if(opt == OPTIONAL::SCI_I2C) { i2c = 1; }
else if(opt == OPTIONAL::SCI_SPI) { spi = true; }
uint8_t sel = enable ? 0b00'1010 : 0;
switch(odr) {
case ORDER::FIRST:
// RXD4: PB0
// TXD4: PB1
// SCK4: PB3
PORTB::PMR.B0 = 0;
PORTB::ODR.B0 = i2c;
MPC::PB0PFS.PSEL = sel; // ok
PORTB::PMR.B0 = enable;
PORTB::PMR.B1 = 0;
PORTB::ODR.B1 = i2c;
MPC::PB1PFS.PSEL = sel; // ok
PORTB::PMR.B1 = enable;
if(spi) {
PORTB::PMR.B3 = 0;
MPC::PB3PFS.PSEL = sel; // ok
PORTB::PMR.B3 = enable;
}
break;
default:
return false;
}
return true;
}
static bool sci5_(ORDER odr, bool enable, OPTIONAL opt) noexcept
{
uint8_t i2c = 0;
bool spi = false;
if(opt == OPTIONAL::SCI_I2C) { i2c = 1; }
else if(opt == OPTIONAL::SCI_SPI) { spi = true; }
uint8_t sel = 0;
switch(odr) {
case ORDER::FIRST:
// RXD5: PA2
// TXD5: PA4
// SCK5: PA1
sel = enable ? 0b0'1010 : 0;
PORTA::PMR.B2 = 0;
PORTA::ODR.B2 = i2c;
MPC::PA2PFS.PSEL = sel; // ok
PORTA::PMR.B2 = enable;
PORTA::PMR.B4 = 0;
PORTA::ODR.B4 = i2c;
MPC::PA4PFS.PSEL = sel; // ok
PORTA::PMR.B4 = enable;
if(spi) {
PORTA::PMR.B1 = 0;
MPC::PA1PFS.PSEL = sel; // ok
PORTA::PMR.B1 = enable;
}
break;
case ORDER::SECOND:
// RXD5: PA3
// TXD5: PA4
// SCK5: PA1
sel = enable ? 0b0'1010 : 0;
PORTA::PMR.B3 = 0;
PORTA::ODR.B3 = i2c;
MPC::PA3PFS.PSEL = sel; // ok
PORTA::PMR.B3 = enable;
PORTA::PMR.B4 = 0;
PORTA::ODR.B4 = i2c;
MPC::PA4PFS.PSEL = sel; // ok
PORTA::PMR.B4 = enable;
if(spi) {
PORTA::PMR.B1 = 0;
MPC::PA1PFS.PSEL = sel; // ok
PORTA::PMR.B1 = enable;
}
break;
case ORDER::THIRD:
// RXD5: PC2
// TXD5: PC3
// SCK5: PC1
sel = enable ? 0b0'1010 : 0;
PORTC::PMR.B2 = 0;
PORTC::ODR.B2 = i2c;
MPC::PC2PFS.PSEL = sel;
PORTC::PMR.B2 = enable;
PORTC::PMR.B3 = 0;
PORTC::ODR.B3 = i2c;
MPC::PC3PFS.PSEL = sel;
PORTC::PMR.B3 = enable;
if(spi) {
PORTC::PMR.B1 = 0;
MPC::PC1PFS.PSEL = sel;
PORTC::PMR.B1 = enable;
}
break;
case ORDER::FOURTH:
// RXD5: PC2
// TXD5: PC3
// SCK5: PC4
sel = enable ? 0b0'1010 : 0;
PORTC::PMR.B2 = 0;
PORTC::ODR.B2 = i2c;
MPC::PC2PFS.PSEL = sel; // ok
PORTC::PMR.B2 = enable;
PORTC::PMR.B3 = 0;
PORTC::ODR.B3 = i2c;
MPC::PC3PFS.PSEL = sel; // ok
PORTC::PMR.B3 = enable;
if(spi) {
PORTC::PMR.B4 = 0;
MPC::PC4PFS.PSEL = sel; // ok
PORTC::PMR.B4 = enable;
}
break;
default:
return false;
}
return true;
}
static bool sci6_(ORDER odr, bool enable, OPTIONAL opt) noexcept
{
uint8_t i2c = 0;
bool spi = false;
if(opt == OPTIONAL::SCI_I2C) { i2c = 1; }
else if(opt == OPTIONAL::SCI_SPI) { spi = true; }
uint8_t sel = enable ? 0b00'1010 : 0;
switch(odr) {
case ORDER::FIRST:
// RXD6: P01
// TXD6: P00
// SCK6: P02
sel = enable ? 0b00'1010 : 0;
PORT0::PMR.B1 = 0;
PORT0::ODR.B1 = i2c;
MPC::P01PFS.PSEL = sel; // ok
PORT0::PMR.B1 = enable;
PORT0::PMR.B0 = 0;
PORT0::ODR.B0 = i2c;
MPC::P00PFS.PSEL = sel; // ok
PORT0::PMR.B0 = enable;
if(spi) {
PORT0::PMR.B2 = 0;
MPC::P02PFS.PSEL = sel; // ok
PORT0::PMR.B2 = enable;
}
break;
case ORDER::SECOND:
// RXD6: P33
// TXD6: P32
// SCK6: P34
sel = enable ? 0b00'1010 : 0;
PORT3::PMR.B3 = 0;
PORT3::ODR.B3 = i2c;
MPC::P33PFS.PSEL = sel; // ok
PORT3::PMR.B3 = enable;
PORT3::PMR.B2 = 0;
PORT3::ODR.B2 = i2c;
MPC::P32PFS.PSEL = sel; // ok
PORT3::PMR.B2 = enable;
if(spi) {
PORT3::PMR.B4 = 0;
MPC::P34PFS.PSEL = sel; // ok
PORT3::PMR.B4 = enable;
}
break;
case ORDER::THIRD:
// RXD6: PB0
// TXD6: PB1
// SCK6: PB3
sel = enable ? 0b00'1011 : 0;
PORTB::PMR.B1 = 0;
PORTB::ODR.B1 = i2c;
MPC::PB1PFS.PSEL = sel; // ok
PORTB::PMR.B1 = enable;
PORTB::PMR.B0 = 0;
PORTB::ODR.B0 = i2c;
MPC::PB0PFS.PSEL = sel; // ok
PORTB::PMR.B0 = enable;
if(spi) {
PORTB::PMR.B3 = 0;
MPC::PB3PFS.PSEL = sel; // ok
PORTB::PMR.B3 = enable;
}
break;
default:
return false;
}
return true;
}
static bool sci7_(ORDER odr, bool enable, OPTIONAL opt) noexcept
{
uint8_t i2c = 0;
bool spi = false;
if(opt == OPTIONAL::SCI_I2C) { i2c = 1; }
else if(opt == OPTIONAL::SCI_SPI) { spi = true; }
uint8_t sel = enable ? 0b00'1010 : 0;
switch(odr) {
case ORDER::FIRST:
// RXD7: P92
// TXD7: P90
// SCK7: P91
PORT9::PMR.B2 = 0;
PORT9::ODR.B2 = i2c;
MPC::P92PFS.PSEL = sel; // ok
PORT9::PMR.B2 = enable;
PORT9::PMR.B0 = 0;
PORT9::ODR.B0 = i2c;
MPC::P90PFS.PSEL = sel; // ok
PORT9::PMR.B0 = enable;
if(spi) {
PORT9::PMR.B1 = 0;
MPC::P91PFS.PSEL = sel;
PORT9::PMR.B1 = enable;
}
break;
case ORDER::SECOND:
// RXD7: P92
// TXD7: P90
// SCK7: P91
PORT9::PMR.B2 = 0;
PORT9::ODR.B2 = i2c;
MPC::P92PFS.PSEL = sel; // ok
PORT9::PMR.B2 = enable;
PORT9::PMR.B0 = 0;
PORT9::ODR.B0 = i2c;
MPC::P90PFS.PSEL = sel; // ok
PORT9::PMR.B0 = enable;
if(spi) {
PORT9::PMR.B1 = 0;
MPC::P91PFS.PSEL = sel; // ok
PORT9::PMR.B1 = enable;
}
break;
default:
return false;
}
return true;
}
static bool sci8_(ORDER odr, bool enable, OPTIONAL opt) noexcept
{
uint8_t i2c = 0;
bool spi = false;
if(opt == OPTIONAL::SCI_I2C) { i2c = 1; }
else if(opt == OPTIONAL::SCI_SPI) { spi = true; }
uint8_t sel = enable ? 0b00'1010 : 0;
switch(odr) {
case ORDER::FIRST:
// RXD8: PC6
// TXD8: PC7
// SCK8: PC5
PORTC::PMR.B6 = 0;
PORTC::ODR.B6 = i2c;
MPC::PC6PFS.PSEL = sel; // ok
PORTC::PMR.B6 = enable;
PORTC::PMR.B7 = 0;
PORTC::ODR.B7 = i2c;
MPC::PC7PFS.PSEL = sel; // ok
PORTC::PMR.B7 = enable;
if(spi) {
PORTC::PMR.B5 = 0;
MPC::PC5PFS.PSEL = sel; // ok
PORTC::PMR.B5 = enable;
}
break;
default:
return false;
}
return true;
}
static bool sci9_(ORDER odr, bool enable, OPTIONAL opt) noexcept
{
uint8_t i2c = 0;
bool spi = false;
if(opt == OPTIONAL::SCI_I2C) { i2c = 1; }
else if(opt == OPTIONAL::SCI_SPI) { spi = true; }
uint8_t sel = enable ? 0b00'1010 : 0;
switch(odr) {
case ORDER::FIRST:
// RXD9: PB6
// TXD9: PB7
// SCK9: PB5
PORTB::PMR.B6 = 0;
PORTB::ODR.B6 = i2c;
MPC::PB6PFS.PSEL = sel; // ok
PORTB::PMR.B6 = enable;
PORTB::PMR.B7 = 0;
PORTB::ODR.B7 = i2c;
MPC::PB7PFS.PSEL = sel; // ok
PORTB::PMR.B7 = enable;
if(spi) {
PORTB::PMR.B5 = 0;
MPC::PB5PFS.PSEL = sel; // ok
PORTB::PMR.B5 = enable;
}
break;
default:
return false;
}
return true;
}
static bool sci10_(ORDER odr, bool enable, OPTIONAL opt) noexcept
{
uint8_t i2c = 0;
bool spi = false;
if(opt == OPTIONAL::SCI_I2C) { i2c = 1; }
else if(opt == OPTIONAL::SCI_SPI) { spi = true; }
uint8_t sel = 0;
switch(odr) {
case ORDER::FIRST:
// RXD10: P81
// TXD10: P82
// SCK10: P80
sel = enable ? 0b00'1010 : 0;
PORTB::PMR.B1 = 0;
PORTB::ODR.B1 = i2c;
MPC::PB1PFS.PSEL = sel; // ok
PORTB::PMR.B1 = enable;
PORTB::PMR.B2 = 0;
PORTB::ODR.B2 = i2c;
MPC::PB2PFS.PSEL = sel; // ok
PORTB::PMR.B2 = enable;
if(spi) {
PORT8::PMR.B0 = 0;
MPC::P80PFS.PSEL = sel; // ok
PORT8::PMR.B0 = enable;
}
break;
case ORDER::SECOND:
// RXD10: P86
// TXD10: P87
// SCK10: P83
sel = enable ? 0b00'1010 : 0;
PORT8::PMR.B6 = 0;
PORT8::ODR.B6 = i2c;
MPC::P86PFS.PSEL = sel; // ok
PORT8::PMR.B6 = enable;
PORT8::PMR.B7 = 0;
PORT8::ODR.B7 = i2c;
MPC::P87PFS.PSEL = sel; // ok
PORT8::PMR.B7 = enable;
if(spi) {
PORT8::PMR.B3 = 0;
MPC::P83PFS.PSEL = sel; // ok
PORT8::PMR.B3 = enable;
}
break;
case ORDER::THIRD:
// RXD10: PC6
// TXD10: PC7
// SCK10: PC5
sel = enable ? 0b01'0100 : 0;
PORTC::PMR.B6 = 0;
PORTC::ODR.B6 = i2c;
MPC::PC6PFS.PSEL = sel; // ok
PORTC::PMR.B6 = enable;
PORTC::PMR.B7 = 0;
PORTC::ODR.B7 = i2c;
MPC::PC7PFS.PSEL = sel; // ok
PORTC::PMR.B7 = enable;
if(spi) {
PORTC::PMR.B5 = 0;
MPC::PC5PFS.PSEL = sel; // ok
PORTC::PMR.B5 = enable;
}
break;
default:
return false;
}
return true;
}
static bool sci11_(ORDER odr, bool enable, OPTIONAL opt) noexcept
{
uint8_t i2c = 0;
bool spi = false;
if(opt == OPTIONAL::SCI_I2C) { i2c = 1; }
else if(opt == OPTIONAL::SCI_SPI) { spi = true; }
uint8_t sel = 0;
switch(odr) {
case ORDER::FIRST:
// RXD11: P76
// TXD11: P77
// SCK11: P75
sel = enable ? 0b00'1010 : 0;
PORT7::PMR.B6 = 0;
PORT7::ODR.B6 = i2c;
MPC::P76PFS.PSEL = sel; // ok
PORT7::PMR.B6 = enable;
PORT7::PMR.B7 = 0;
PORT7::ODR.B7 = i2c;
MPC::P77PFS.PSEL = sel; // ok
PORT7::PMR.B7 = enable;
if(spi) {
PORT7::PMR.B5 = 0;
MPC::P75PFS.PSEL = sel; // ok
PORT7::PMR.B5 = enable;
}
break;
case ORDER::SECOND:
// RXD11: PB6
// TXD11: PB7
// SCK11: PB5
sel = enable ? 0b10'0100 : 0;
PORTB::PMR.B6 = 0;
PORTB::ODR.B6 = i2c;
MPC::PB6PFS.PSEL = sel; // ok
PORTB::PMR.B6 = enable;
PORTB::PMR.B7 = 0;
PORTB::ODR.B7 = i2c;
MPC::PB7PFS.PSEL = sel; // ok
PORTB::PMR.B7 = enable;
if(spi) {
PORTB::PMR.B5 = 0;
MPC::PB5PFS.PSEL = sel; // ok
PORTB::PMR.B5 = enable;
}
break;
default:
return false;
}
return true;
}
static bool sci12_(ORDER odr, bool enable, OPTIONAL opt) noexcept
{
uint8_t i2c = 0;
bool spi = false;
if(opt == OPTIONAL::SCI_I2C) { i2c = 1; }
else if(opt == OPTIONAL::SCI_SPI) { spi = true; }
uint8_t sel = 0;
switch(odr) {
case ORDER::FIRST:
// RXD12: PE2
// TXD12: PE1
// SCK12: PE0
sel = enable ? 0b00'1100 : 0;
PORTE::PMR.B2 = 0;
PORTE::ODR.B2 = i2c;
MPC::PE2PFS.PSEL = sel; // ok
PORTE::PMR.B2 = enable;
PORTE::PMR.B1 = 0;
PORTE::ODR.B1 = i2c;
MPC::PE1PFS.PSEL = sel; // ok
PORTE::PMR.B1 = enable;
if(spi) {
PORTE::PMR.B0 = 0;
MPC::PE0PFS.PSEL = sel; // ok
PORTE::PMR.B0 = enable;
}
break;
case ORDER::SECOND:
// RXD12: PA2
// TXD12: PA4
// SCK12: PA1
sel = enable ? 0b00'1010 : 0;
PORTA::PMR.B2 = 0;
PORTA::ODR.B2 = i2c;
MPC::PA2PFS.PSEL = sel; // ok
PORTA::PMR.B2 = enable;
PORTA::PMR.B4 = 0;
PORTA::ODR.B4 = i2c;
MPC::PA4PFS.PSEL = sel; // ok
PORTA::PMR.B4 = enable;
if(spi) {
PORTA::PMR.B1 = 0;
MPC::PA1PFS.PSEL = sel; // ok
PORTA::PMR.B1 = enable;
}
break;
default:
return false;
}
return true;
}
static bool rsci10_(ORDER odr, bool enable, OPTIONAL opt) noexcept
{
uint8_t i2c = 0;
bool spi = false;
if(opt == OPTIONAL::SCI_I2C) { i2c = 1; }
else if(opt == OPTIONAL::SCI_SPI) { spi = true; }
uint8_t sel = 0;
switch(odr) {
case ORDER::FIRST:
// RXD010: P81
// TXD010: P82
// SCK010: P80
sel = enable ? 0b10'1100 : 0;
PORT8::PMR.B1 = 0;
PORT8::ODR.B1 = i2c;
MPC::P81PFS.PSEL = sel; // ok
PORT8::PMR.B1 = enable;
PORT8::PMR.B2 = 0;
PORT8::ODR.B2 = i2c;
MPC::P82PFS.PSEL = sel; // ok
PORT8::PMR.B2 = enable;
if(spi) {
PORT8::PMR.B0 = 0;
MPC::P80PFS.PSEL = sel; // ok
PORT8::PMR.B0 = enable;
}
break;
case ORDER::SECOND:
// RXD010: P86
// TXD010: P87
// SCK010: P83
sel = enable ? 0b10'1100 : 0;
PORT8::PMR.B6 = 0;
PORT8::ODR.B6 = i2c;
MPC::P86PFS.PSEL = sel; // ok
PORT8::PMR.B6 = enable;
PORT8::PMR.B7 = 0;
PORT8::ODR.B7 = i2c;
MPC::P87PFS.PSEL = sel; // ok
PORT8::PMR.B7 = enable;
if(spi) {
PORT8::PMR.B3 = 0;
MPC::P83PFS.PSEL = sel; // ok
PORT8::PMR.B3 = enable;
}
break;
case ORDER::THIRD:
// RXD010: PC6
// TXD010: PC7
// SCK010: PC5
sel = enable ? 0b10'1100 : 0;
PORTC::PMR.B6 = 0;
PORTC::ODR.B6 = i2c;
MPC::PC6PFS.PSEL = sel; // ok
PORTC::PMR.B6 = enable;
PORTC::PMR.B7 = 0;
PORTC::ODR.B7 = i2c;
MPC::PC7PFS.PSEL = sel; // ok
PORTC::PMR.B7 = enable;
if(spi) {
PORTC::PMR.B5 = 0;
MPC::PC5PFS.PSEL = sel; // ok
PORTC::PMR.B5 = enable;
}
break;
default:
return false;
}
return true;
}
static bool rsci10_de_(ORDER odr, bool enable) noexcept
{
uint8_t sel = enable ? 0b10'1110 : 0;
switch(odr) {
case ORDER::FIRST: // DE010: P80
PORT8::PMR.B0 = 0;
MPC::P80PFS.PSEL = sel; // ok
PORT8::PMR.B0 = enable;
break;
case ORDER::SECOND: // DE010: PC4
PORTC::PMR.B4 = 0;
MPC::PC4PFS.PSEL = sel; // ok
PORTC::PMR.B4 = enable;
break;
default:
return false;
}
return true;
}
static bool rsci11_(ORDER odr, bool enable, OPTIONAL opt) noexcept
{
uint8_t i2c = 0;
bool spi = false;
if(opt == OPTIONAL::SCI_I2C) { i2c = 1; }
else if(opt == OPTIONAL::SCI_SPI) { spi = true; }
uint8_t sel = 0;
switch(odr) {
case ORDER::FIRST:
// RXD011: P76
// TXD011: P77
// SCK011: P75
sel = enable ? 0b10'1100 : 0;
PORT7::PMR.B6 = 0;
PORT7::ODR.B6 = i2c;
MPC::P76PFS.PSEL = sel; // ok
PORT7::PMR.B6 = enable;
PORT7::PMR.B7 = 0;
PORT7::ODR.B7 = i2c;
MPC::P77PFS.PSEL = sel; // ok
PORT7::PMR.B7 = enable;
if(spi) {
PORT7::PMR.B5 = 0;
MPC::P75PFS.PSEL = sel; // ok
PORT7::PMR.B5 = enable;
}
break;
case ORDER::SECOND:
// RXD011: PB6
// TXD011: PB7
// SCK011: PB5
sel = enable ? 0b10'1100 : 0;
PORTB::PMR.B6 = 0;
PORTB::ODR.B6 = i2c;
MPC::PB6PFS.PSEL = sel; // ok
PORTB::PMR.B6 = enable;
PORTB::PMR.B7 = 0;
PORTB::ODR.B7 = i2c;
MPC::PB7PFS.PSEL = sel; // ok
PORTB::PMR.B7 = enable;
if(spi) {
PORTB::PMR.B5 = 0;
MPC::PB5PFS.PSEL = sel; // ok
PORTB::PMR.B5 = enable;
}
break;
case ORDER::THIRD:
// RXD011: PC0
// TXD011: PC1
// SCK011: PB5
sel = enable ? 0b10'1100 : 0;
PORTC::PMR.B0 = 0;
PORTC::ODR.B0 = i2c;
MPC::PC0PFS.PSEL = sel; // ok
PORTC::PMR.B0 = enable;
PORTC::PMR.B1 = 0;
PORTC::ODR.B1 = i2c;
MPC::PC1PFS.PSEL = sel; // ok
PORTC::PMR.B1 = enable;
if(spi) {
PORTB::PMR.B5 = 0;
MPC::PB5PFS.PSEL = sel; // ok
PORTB::PMR.B5 = enable;
}
break;
default:
return false;
}
return true;
}
static bool rsci11_de_(ORDER odr, bool enable) noexcept
{
uint8_t sel = enable ? 0b10'1110 : 0;
switch(odr) {
case ORDER::FIRST: // DE011: P75
PORT7::PMR.B5 = 0;
MPC::P75PFS.PSEL = sel; // ok
PORT7::PMR.B5 = enable;
break;
case ORDER::SECOND: // DE011: PB4
PORTB::PMR.B4 = 0;
MPC::PB4PFS.PSEL = sel; // ok
PORTB::PMR.B4 = enable;
break;
default:
return false;
}
return true;
}
static bool riic0_(ORDER odr, bool enable) noexcept
{
uint8_t sel = enable ? 0b00'1111 : 0;
switch(odr) {
case ORDER::FIRST:
// SCL0: P12
// SDA0: P13
PORT1::PMR.B2 = 0;
MPC::P12PFS.PSEL = sel; // ok
PORT1::PMR.B2 = enable;
PORT1::PMR.B3 = 0;
MPC::P13PFS.PSEL = sel; // ok
PORT1::PMR.B3 = enable;
break;
default:
return false;
}
return true;
}
static bool riic1_(ORDER odr, bool enable) noexcept
{
uint8_t sel = enable ? 0b00'1111 : 0;
switch(odr) {
case ORDER::FIRST:
// SCL1: P21
// SDA1: P20
PORT2::PMR.B1 = 0;
MPC::P21PFS.PSEL = sel; // ok
PORT2::PMR.B1 = enable;
PORT2::PMR.B0 = 0;
MPC::P20PFS.PSEL = sel; // ok
PORT2::PMR.B0 = enable;
break;
default:
return false;
}
return true;
}
static bool riic2_(ORDER odr, bool enable) noexcept
{