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port_map_gpt.hpp
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#pragma once
//=========================================================================//
/*! @file
@brief RX24T/RX24U グループ・ポート・マッピング (GPTB)
@author 平松邦仁 ([email protected])
@copyright Copyright (C) 2022, 2024 Kunihito Hiramatsu @n
Released under the MIT license @n
https://github.com/hirakuni45/RX/blob/master/LICENSE
*/
//=========================================================================//
#if defined(SIG_RX24T)
#include "RX24T/peripheral.hpp"
#elif defined(SIG_RX24U)
#include "RX24U/peripheral.hpp"
#endif
#include "RX24T/port.hpp"
#include "RX24T/mpc.hpp"
#include "RX600/port_map_order.hpp"
namespace device {
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++//
/*!
@brief RX24T/GPTB ポート・マッピング・ユーティリティー
*/
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++//
class port_map_gpt : public port_map_order {
static bool gpt0_(CHANNEL ch, bool ena, ORDER odr, bool neg) noexcept
{
bool ret = true;
uint8_t sel = ena ? (neg ? 0b10110 : 0b10100) : 0;
switch(ch) {
case CHANNEL::A: // GTIOC0A
// P71
// PD7
switch(odr) {
case ORDER::FIRST:
PORT7::PMR.B1 = 0;
MPC::P71PFS.PSEL = sel; // ok
PORT7::PMR.B1 = ena;
break;
case ORDER::SECOND:
PORTD::PMR.B7 = 0;
MPC::PD7PFS.PSEL = sel; // ok
PORTD::PMR.B7 = ena;
break;
default:
ret = false;
break;
}
break;
case CHANNEL::B: // GTIOC0B
// P74
// PD1
switch(odr) {
case ORDER::FIRST:
PORT7::PMR.B4 = 0;
MPC::P74PFS.PSEL = sel; // ok
PORT7::PMR.B4 = ena;
break;
case ORDER::SECOND:
PORTD::PMR.B1 = 0;
MPC::PD1PFS.PSEL = sel; // ok
PORTD::PMR.B1 = ena;
break;
default:
ret = false;
break;
}
break;
default:
ret = false;
break;
}
return ret;
}
static bool gpt1_(CHANNEL ch, bool ena, ORDER odr, bool neg) noexcept
{
bool ret = true;
uint8_t sel = ena ? (neg ? 0b10110 : 0b10100) : 0;
switch(ch) {
case CHANNEL::A: // GTIOC1A
// P72
// PD0
switch(odr) {
case ORDER::FIRST:
PORT7::PMR.B2 = 0;
MPC::P72PFS.PSEL = sel; // ok
PORT7::PMR.B2 = ena;
break;
case ORDER::SECOND:
PORTD::PMR.B0 = 0;
MPC::PD0PFS.PSEL = sel; // ok
PORTD::PMR.B0 = ena;
break;
default:
ret = false;
break;
}
break;
case CHANNEL::B: // GTIOC1B
// P75
// PB7
switch(odr) {
case ORDER::FIRST:
PORT7::PMR.B5 = 0;
MPC::P75PFS.PSEL = sel; // ok
PORT7::PMR.B5 = ena;
break;
case ORDER::SECOND:
PORTB::PMR.B7 = 0;
MPC::PB7PFS.PSEL = sel; // ok
PORTB::PMR.B7 = ena;
break;
default:
ret = false;
break;
}
break;
default:
ret = false;
break;
}
return ret;
}
static bool gpt2_(CHANNEL ch, bool ena, ORDER odr, bool neg) noexcept
{
bool ret = true;
uint8_t sel = ena ? (neg ? 0b10110 : 0b10100) : 0;
switch(ch) {
case CHANNEL::A: // GTIOC2A
// P73
// PB6
switch(odr) {
case ORDER::FIRST:
PORT7::PMR.B3 = 0;
MPC::P73PFS.PSEL = sel; // ok
PORT7::PMR.B3 = ena;
break;
case ORDER::SECOND:
PORTB::PMR.B6 = 0;
MPC::PB6PFS.PSEL = sel; // ok
PORTB::PMR.B6 = ena;
break;
default:
ret = false;
break;
}
break;
case CHANNEL::B: // GTIOC2B
// P76
// PB5
switch(odr) {
case ORDER::FIRST:
PORT7::PMR.B6 = 0;
MPC::P76PFS.PSEL = sel; // ok
PORT7::PMR.B6 = ena;
break;
case ORDER::SECOND:
PORTB::PMR.B5 = 0;
MPC::PB5PFS.PSEL = sel; // ok
PORTB::PMR.B5 = ena;
break;
default:
ret = false;
break;
}
break;
default:
ret = false;
break;
}
return ret;
}
static bool gpt3_(CHANNEL ch, bool ena, ORDER odr, bool neg) noexcept
{
bool ret = true;
uint8_t sel = ena ? (neg ? 0b10110 : 0b10100) : 0;
switch(ch) {
case CHANNEL::A: // GTIOC3A
// PD7
switch(odr) {
PORTD::PMR.B7 = 0;
MPC::PD7PFS.PSEL = sel; // ok
PORTD::PMR.B7 = ena;
break;
default:
ret = false;
break;
}
break;
case CHANNEL::B: // GTIOC3B
// PD6
switch(odr) {
case ORDER::FIRST:
PORTD::PMR.B6 = 0;
MPC::PD6PFS.PSEL = sel; // ok
PORTD::PMR.B6 = ena;
break;
default:
ret = false;
break;
}
break;
default:
ret = false;
break;
}
return ret;
}
public:
//-----------------------------------------------------------------//
/*!
@brief GPT 関係、チャネル別ポート切り替え
@param[in] per 周辺機器タイプ
@param[in] ch チャネル
@param[in] ena 無効にする場合「false」
@param[in] odr 候補選択
@param[in] neg 反転入出力の場合「true」（サポートしない）
@return 無効な周辺機器の場合「false」
*/
//-----------------------------------------------------------------//
static bool turn(peripheral per, CHANNEL ch, bool ena = true, ORDER odr = ORDER::FIRST, bool neg = false) noexcept
{
if(odr == ORDER::BYPASS) return true;
MPC::PWPR.B0WI = 0; // PWPR 書き込み許可
MPC::PWPR.PFSWE = 1; // PxxPFS 書き込み許可
bool ret = true;
switch(per) {
case peripheral::GPT0:
ret = gpt0_(ch, ena, odr, neg);
break;
case peripheral::GPT1:
ret = gpt1_(ch, ena, odr, neg);
break;
case peripheral::GPT2:
ret = gpt2_(ch, ena, odr, neg);
break;
case peripheral::GPT3:
ret = gpt3_(ch, ena, odr, neg);
break;
default:
ret = false;
break;
}
MPC::PWPR = device::MPC::PWPR.B0WI.b();
return ret;
}
#if 0
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++//
/*!
@brief GPT 系、トリガーポート切り替え
@param[in] ch チャネル
@param[in] ena 無効にする場合場合「false」
@param[in] odr 候補選択
@param[in] neg 反転入出力の場合「true」（サポートしない）
@return 無効な周辺機器の場合「false」
*/
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++//
static bool turn_trigger(CHANNEL ch, bool ena = true, ORDER odr = ORDER::FIRST, bool neg = false) noexcept
{
bool ret = true;
if(odr == ORDER::BYPASS) return true;
if(neg) return false;
MPC::PWPR.B0WI = 0; // PWPR 書き込み許可
MPC::PWPR.PFSWE = 1; // PxxPFS 書き込み許可
switch(ch) {
case CHANNEL::CLK_A:
// ret = trg0_(odr, ena);
break;
case CHANNEL::CLK_B:
// ret = trg1_(odr, ena);
break;
default:
ret = false;
break;
}
MPC::PWPR = MPC::PWPR.B0WI.b();
return ret;
}
#endif
};
}