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port_map_mtu.hpp
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#pragma once
//=========================================================================//
/*! @file
@brief RX220 グループ・ポート・マッピング (MTU2a)
@author 平松邦仁 ([email protected])
@copyright Copyright (C) 2022 Kunihito Hiramatsu @n
Released under the MIT license @n
https://github.com/hirakuni45/RX/blob/master/LICENSE
*/
//=========================================================================//
#include "RX220/peripheral.hpp"
#include "RX220/port.hpp"
#include "RX220/mpc.hpp"
#include "RX600/port_map_order.hpp"
namespace device {
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++//
/*!
@brief RX220/MTU ポート・マッピング・ユーティリティー
*/
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++//
class port_map_mtu : public port_map_order {
static bool mtu0_(CHANNEL ch, bool ena, ORDER odr) noexcept
{
bool ret = true;
uint8_t sel = ena ? 0b0001 : 0;
switch(ch) {
case CHANNEL::A: // MTIOC0A
// P34
// PB3
switch(odr) {
case ORDER::FIRST:
PORT3::PMR.B4 = 0;
MPC::P34PFS.PSEL = sel; // ok
PORT3::PMR.B4 = ena;
break;
case ORDER::SECOND:
PORTB::PMR.B3 = 0;
MPC::PB3PFS.PSEL = sel; // ok
PORTB::PMR.B3 = ena;
break;
default:
ret = false;
break;
}
break;
case CHANNEL::B: // MTIOC0B
// P13
// P15
// PA1
switch(odr) {
case ORDER::FIRST:
PORT1::PMR.B3 = 0;
MPC::P13PFS.PSEL = sel; // ok
PORT1::PMR.B3 = ena;
break;
case ORDER::SECOND:
PORT1::PMR.B5 = 0;
MPC::P15PFS.PSEL = sel; // ok
PORT1::PMR.B5 = ena;
break;
case ORDER::THIRD:
PORTA::PMR.B1 = 0;
MPC::PA1PFS.PSEL = sel; // ok
PORTA::PMR.B1 = ena;
break;
default:
ret = false;
break;
}
break;
case CHANNEL::C: // MTIOC0C
// P32
// PB1
switch(odr) {
case ORDER::FIRST:
PORT3::PMR.B2 = 0;
MPC::P32PFS.PSEL = sel; // ok
PORT3::PMR.B2 = ena;
break;
case ORDER::SECOND:
PORTB::PMR.B1 = 0;
MPC::PB1PFS.PSEL = sel; // ok
PORTB::PMR.B1 = ena;
break;
default:
ret = false;
break;
}
break;
case CHANNEL::D: // MTIOC0D
// P33
// PA3
switch(odr) {
case ORDER::FIRST:
PORT3::PMR.B3 = 0;
MPC::P33PFS.PSEL = sel; // ok
PORT3::PMR.B3 = ena;
break;
case ORDER::SECOND:
PORTA::PMR.B3 = 0;
MPC::PA3PFS.PSEL = sel; // ok
PORTA::PMR.B3 = ena;
break;
default:
ret = false;
break;
}
break;
default:
ret = false;
break;
}
return ret;
}
static bool mtu1_(CHANNEL ch, bool ena, ORDER odr) noexcept
{
bool ret = true;
switch(ch) {
case CHANNEL::A: // MTIOC1A
// P20
// PE4
switch(odr) {
case ORDER::FIRST:
PORT2::PMR.B0 = 0;
MPC::P20PFS.PSEL = ena ? 0b0001 : 0; // ok
PORT2::PMR.B0 = ena;
break;
case ORDER::SECOND:
PORTE::PMR.B4 = 0;
MPC::PE4PFS.PSEL = ena ? 0b0010 : 0; // ok
PORTE::PMR.B4 = ena;
break;
default:
ret = false;
break;
}
break;
case CHANNEL::B: // MTIOC1B
// P21
// PB5
switch(odr) {
case ORDER::FIRST:
PORT2::PMR.B1 = 0;
MPC::P21PFS.PSEL = ena ? 0b0001 : 0; // ok
PORT2::PMR.B1 = ena;
break;
case ORDER::SECOND:
PORTB::PMR.B5 = 0;
MPC::PB5PFS.PSEL = ena ? 0b0010 : 0; // ok
PORTB::PMR.B5 = ena;
break;
default:
ret = false;
break;
}
break;
default:
ret = false;
break;
}
return ret;
}
static bool mtu2_(CHANNEL ch, bool ena, ORDER odr) noexcept
{
bool ret = true;
uint8_t sel = ena ? 0b0001 : 0;
switch(ch) {
case CHANNEL::A: // MTIOC2A
// P26
// PB5
switch(odr) {
case ORDER::FIRST:
PORT2::PMR.B6 = 0;
MPC::P26PFS.PSEL = sel; // ok
PORT2::PMR.B6 = ena;
break;
case ORDER::SECOND:
PORTB::PMR.B5 = 0;
MPC::PB5PFS.PSEL = sel; // ok
PORTB::PMR.B5 = ena;
break;
default:
ret = false;
break;
}
break;
case CHANNEL::B: // MTIOC2B
// P27
// PE5
switch(odr) {
case ORDER::FIRST:
PORT2::PMR.B7 = 0;
MPC::P27PFS.PSEL = sel; // ok
PORT2::PMR.B7 = ena;
break;
case ORDER::SECOND:
PORTE::PMR.B5 = 0;
MPC::PE5PFS.PSEL = ena ? 0b0010 : 0; // ok
PORTE::PMR.B5 = ena;
break;
default:
ret = false;
break;
}
break;
default:
ret = false;
break;
}
return ret;
}
static bool mtu3_(CHANNEL ch, bool ena, ORDER odr) noexcept
{
bool ret = true;
uint8_t sel = ena ? 0b0001 : 0;
switch(ch) {
case CHANNEL::A: // MTIOC3A
// P14
// P17
// PC1
// PC7
// PJ1
switch(odr) {
case ORDER::FIRST:
PORT1::PMR.B4 = 0;
MPC::P14PFS.PSEL = sel; // ok
PORT1::PMR.B4 = ena;
break;
case ORDER::SECOND:
PORT1::PMR.B7 = 0;
MPC::P17PFS.PSEL = sel; // ok
PORT1::PMR.B7 = ena;
break;
case ORDER::THIRD:
PORTC::PMR.B1 = 0;
MPC::PC1PFS.PSEL = sel; // ok
PORTC::PMR.B1 = ena;
break;
case ORDER::FOURTH:
PORTC::PMR.B7 = 0;
MPC::PC7PFS.PSEL = sel; // ok
PORTC::PMR.B7 = ena;
break;
case ORDER::FIFTH:
PORTJ::PMR.B1 = 0;
MPC::PJ1PFS.PSEL = sel; // ok
PORTJ::PMR.B1 = ena;
break;
default:
ret = false;
break;
}
break;
case CHANNEL::B: // MTIOC3B
// P17
// P22
// PB7
// PC5
switch(odr) {
case ORDER::FIRST:
PORT1::PMR.B7 = 0;
MPC::P17PFS.PSEL = ena ? 0b0010 : 0; // ok
PORT1::PMR.B7 = ena;
break;
case ORDER::SECOND:
PORT2::PMR.B2 = 0;
MPC::P22PFS.PSEL = sel; // ok
PORT2::PMR.B2 = ena;
break;
case ORDER::THIRD:
PORTB::PMR.B7 = 0;
MPC::PB7PFS.PSEL = sel; // ok
PORTB::PMR.B7 = ena;
break;
case ORDER::FOURTH:
PORTC::PMR.B5 = 0;
MPC::PC5PFS.PSEL = sel; // ok
PORTC::PMR.B5 = ena;
break;
default:
ret = false;
break;
}
break;
case CHANNEL::C: // MTIOC3C
// P16
// PC0
// PC6
// PJ3
switch(odr) {
case ORDER::FIRST:
PORT1::PMR.B6 = 0;
MPC::P16PFS.PSEL = sel; // ok
PORT1::PMR.B6 = ena;
break;
case ORDER::SECOND:
PORTC::PMR.B0 = 0;
MPC::PC0PFS.PSEL = sel; // ok
PORTC::PMR.B0 = ena;
break;
case ORDER::THIRD:
PORTC::PMR.B6 = 0;
MPC::PC6PFS.PSEL = sel; // ok
PORTC::PMR.B6 = ena;
break;
case ORDER::FOURTH:
PORTJ::PMR.B3 = 0;
MPC::PJ3PFS.PSEL = sel; // ok
PORTJ::PMR.B3 = ena;
break;
default:
ret = false;
break;
}
break;
case CHANNEL::D: // MTIOC3D
// P16
// P23
// PB6
// PC4
switch(odr) {
case ORDER::FIRST:
PORT1::PMR.B6 = 0;
MPC::P16PFS.PSEL = ena ? 0b0010 : 0; // ok
PORT1::PMR.B6 = ena;
break;
case ORDER::SECOND:
PORT2::PMR.B3 = 0;
MPC::P23PFS.PSEL = sel; // ok
PORT2::PMR.B3 = ena;
break;
case ORDER::THIRD:
PORTB::PMR.B6 = 0;
MPC::PB6PFS.PSEL = sel; // ok
PORTB::PMR.B6 = ena;
break;
case ORDER::FOURTH:
PORTC::PMR.B4 = 0;
MPC::PC4PFS.PSEL = sel; // ok
PORTC::PMR.B4 = ena;
break;
default:
ret = false;
break;
}
break;
default:
ret = false;
break;
}
return ret;
}
static bool mtu4_(CHANNEL ch, bool ena, ORDER odr) noexcept
{
bool ret = true;
uint8_t sel = ena ? 0b0001 : 0;
switch(ch) {
case CHANNEL::A: // MTIOC4A
// P24
// PA0
// PB3
// PE2
switch(odr) {
case ORDER::FIRST:
PORT2::PMR.B4 = 0;
MPC::P24PFS.PSEL = sel; // ok
PORT2::PMR.B4 = ena;
break;
case ORDER::SECOND:
PORTA::PMR.B0 = 0;
MPC::PA0PFS.PSEL = sel; // ok
PORTA::PMR.B0 = ena;
break;
case ORDER::THIRD:
PORTB::PMR.B3 = 0;
MPC::PB3PFS.PSEL = ena ? 0b0010 : 0; // ok
PORTB::PMR.B3 = ena;
break;
case ORDER::FOURTH:
PORTE::PMR.B2 = 0;
MPC::PE2PFS.PSEL = sel; // ok
PORTE::PMR.B2 = ena;
break;
default:
ret = false;
break;
}
break;
case CHANNEL::B: // MTIOC4B
// P30
// P54
// PC2
// PD1
// PE3
switch(odr) {
case ORDER::FIRST:
PORT3::PMR.B0 = 0;
MPC::P30PFS.PSEL = sel; // ok
PORT3::PMR.B0 = ena;
break;
case ORDER::SECOND:
PORT5::PMR.B4 = 0;
MPC::P54PFS.PSEL = sel; // ok
PORT5::PMR.B4 = ena;
break;
case ORDER::THIRD:
PORTC::PMR.B2 = 0;
MPC::PC2PFS.PSEL = sel; // ok
PORTC::PMR.B2 = ena;
break;
case ORDER::FOURTH:
PORTD::PMR.B1 = 0;
MPC::PD1PFS.PSEL = sel; // ok
PORTD::PMR.B1 = ena;
break;
case ORDER::FIFTH:
PORTE::PMR.B3 = 0;
MPC::PE3PFS.PSEL = sel; // ok
PORTE::PMR.B3 = ena;
break;
default:
ret = false;
break;
}
break;
case CHANNEL::C: // MTIOC4C
// P25
// PB1
// PE1
// PE5
switch(odr) {
case ORDER::FIRST:
PORT2::PMR.B5 = 0;
MPC::P25PFS.PSEL = sel; // ok
PORT2::PMR.B5 = ena;
break;
case ORDER::SECOND:
PORTB::PMR.B1 = 0;
MPC::PB1PFS.PSEL = ena ? 0b0010 : 0; // ok
PORTB::PMR.B1 = ena;
break;
case ORDER::THIRD:
PORTE::PMR.B1 = 0;
MPC::PE1PFS.PSEL = sel; // ok
PORTE::PMR.B1 = ena;
break;
case ORDER::FOURTH:
PORTE::PMR.B5 = 0;
MPC::PE5PFS.PSEL = sel; // ok
PORTE::PMR.B5 = ena;
break;
default:
ret = false;
break;
}
break;
case CHANNEL::D: // MTIOC4D
// P31
// P55
// PC3
// PD2
// PE4
switch(odr) {
case ORDER::FIRST:
PORT3::PMR.B1 = 0;
MPC::P31PFS.PSEL = sel; // ok
PORT3::PMR.B1 = ena;
break;
case ORDER::SECOND:
PORT5::PMR.B5 = 0;
MPC::P55PFS.PSEL = sel; // ok
PORT5::PMR.B5 = ena;
break;
case ORDER::THIRD:
PORTC::PMR.B3 = 0;
MPC::PC3PFS.PSEL = sel; // ok
PORTC::PMR.B3 = ena;
break;
case ORDER::FOURTH:
PORTD::PMR.B2 = 0;
MPC::PD2PFS.PSEL = sel; // ok
PORTD::PMR.B2 = ena;
break;
case ORDER::FIFTH:
PORTE::PMR.B4 = 0;
MPC::PE4PFS.PSEL = sel; // ok
PORTE::PMR.B4 = ena;
break;
default:
ret = false;
break;
}
break;
default:
ret = false;
break;
}
return ret;
}
static bool mtu5_(CHANNEL ch, bool ena, ORDER odr) noexcept
{
bool ret = true;
uint8_t sel = ena ? 0b0001 : 0;
switch(ch) {
case CHANNEL::U: // MTIOC5U
// PA4
// PD7
switch(odr) {
case ORDER::FIRST:
PORTA::PMR.B4 = 0;
MPC::PA4PFS.PSEL = sel; // ok
PORTA::PMR.B4 = ena;
break;
case ORDER::SECOND:
PORTD::PMR.B7 = 0;
MPC::PD7PFS.PSEL = sel; // ok
PORTD::PMR.B7 = ena;
break;
default:
ret = false;
break;
}
break;
case CHANNEL::V: // MTIOC5V
// PA6
// PD6
switch(odr) {
case ORDER::FIRST:
PORTA::PMR.B6 = 0;
MPC::PA6PFS.PSEL = sel; // ok
PORTA::PMR.B6 = ena;
break;
case ORDER::SECOND:
PORTD::PMR.B6 = 0;
MPC::PD6PFS.PSEL = sel; // ok
PORTD::PMR.B6 = ena;
break;
default:
ret = false;
break;
}
break;
case CHANNEL::W: // MTIOC5W
// PB0
// PD5
switch(odr) {
case ORDER::FIRST:
PORTB::PMR.B0 = 0;
MPC::PB0PFS.PSEL = sel; // ok
PORTB::PMR.B0 = ena;
break;
case ORDER::SECOND:
PORTD::PMR.B5 = 0;
MPC::PD5PFS.PSEL = sel; // ok
PORTD::PMR.B5 = ena;
break;
default:
ret = false;
break;
}
break;
default:
ret = false;
break;
}
return ret;
}
static bool clk_a_(ORDER odr, bool ena) noexcept
{
// P14
// P24
// PA4
// PC6
uint8_t sel = ena ? 0b00010 : 0;
switch(odr) {
case ORDER::FIRST:
PORT1::PMR.B4 = 0;
MPC::P14PFS.PSEL = sel; // ok
PORT1::PMR.B4 = ena;
break;
case ORDER::SECOND:
PORT2::PMR.B4 = 0;
MPC::P24PFS.PSEL = sel; // ok
PORT2::PMR.B4 = ena;
break;
case ORDER::THIRD:
PORTA::PMR.B4 = 0;
MPC::PA4PFS.PSEL = sel; // ok
PORTA::PMR.B4 = ena;
break;
case ORDER::FOURTH:
PORTC::PMR.B6 = 0;
MPC::PC6PFS.PSEL = sel; // ok
PORTC::PMR.B6 = ena;
break;
default:
return false;
break;
}
return true;
}
static bool clk_b_(ORDER odr, bool ena) noexcept
{
// P15
// P25
// PA6
// PC7
uint8_t sel = ena ? 0b00010 : 0;
switch(odr) {
case ORDER::FIRST:
PORT1::PMR.B5 = 0;
MPC::P15PFS.PSEL = sel; // ok
PORT1::PMR.B5 = ena;
break;
case ORDER::SECOND:
PORT2::PMR.B5 = 0;
MPC::P25PFS.PSEL = sel; // ok
PORT2::PMR.B5 = ena;
break;
case ORDER::THIRD:
PORTA::PMR.B6 = 0;
MPC::PA6PFS.PSEL = sel; // ok
PORTA::PMR.B6 = ena;
break;
case ORDER::FOURTH:
PORTC::PMR.B7 = 0;
MPC::PC7PFS.PSEL = sel; // ok
PORTC::PMR.B7 = ena;
break;
default:
return false;
break;
}
return true;
}
static bool clk_c_(ORDER odr, bool ena) noexcept
{
// P22
// PA1
// PC4
uint8_t sel = ena ? 0b00010 : 0;
switch(odr) {
case ORDER::FIRST:
PORT2::PMR.B2 = 0;
MPC::P22PFS.PSEL = sel; // ok
PORT2::PMR.B2 = ena;
break;
case ORDER::SECOND:
PORTA::PMR.B1 = 0;
MPC::PA1PFS.PSEL = sel; // ok
PORTA::PMR.B1 = ena;
break;
case ORDER::THIRD:
PORTC::PMR.B4 = 0;
MPC::PC4PFS.PSEL = sel; // ok
PORTC::PMR.B4 = ena;
break;
default:
return false;
break;
}
return true;
}
static bool clk_d_(ORDER odr, bool ena) noexcept
{
// P23
// PA3
// PC5
uint8_t sel = ena ? 0b00010 : 0;
switch(odr) {
case ORDER::FIRST:
PORT2::PMR.B3 = 0;
MPC::P23PFS.PSEL = sel; // ok
PORT2::PMR.B3 = ena;
break;
case ORDER::SECOND:
PORTA::PMR.B3 = 0;
MPC::PA3PFS.PSEL = sel; // ok
PORTA::PMR.B3 = ena;
break;
case ORDER::THIRD:
PORTC::PMR.B5 = 0;
MPC::PC5PFS.PSEL = sel; // ok
PORTC::PMR.B5 = ena;
break;
default:
return false;
break;
}
return true;
}
public:
//-----------------------------------------------------------------//
/*!
@brief MTU3d 関係、チャネル別ポート切り替え
@param[in] per 周辺機器タイプ
@param[in] ch チャネル
@param[in] ena 無効にする場合「false」
@param[in] odr 候補選択
@param[in] neg 反転入出力の場合「true」 @n
RX220 では、反転入出力をサポートしないので、設定するとエラーになる
@param[in] inp 入力として利用する場合「true」（無視される）
@return 無効な周辺機器の場合「false」
*/
//-----------------------------------------------------------------//
static bool turn(peripheral per, CHANNEL ch, bool ena = true, ORDER odr = ORDER::FIRST, bool neg = false, bool inp = false) noexcept
{
if(odr == ORDER::BYPASS) return true;
if(neg) return false;
MPC::PWPR.B0WI = 0; // PWPR 書き込み許可
MPC::PWPR.PFSWE = 1; // PxxPFS 書き込み許可
bool ret = true;
switch(per) {
case peripheral::MTU0:
ret = mtu0_(ch, ena, odr);
break;
case peripheral::MTU1:
ret = mtu1_(ch, ena, odr);
break;
case peripheral::MTU2:
ret = mtu2_(ch, ena, odr);
break;
case peripheral::MTU3:
ret = mtu3_(ch, ena, odr);
break;
case peripheral::MTU4:
ret = mtu4_(ch, ena, odr);
break;
case peripheral::MTU5:
ret = mtu5_(ch, ena, odr);
break;
default:
ret = false;
break;
}
MPC::PWPR = device::MPC::PWPR.B0WI.b();
return ret;
}
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++//
/*!
@brief タイマー系、クロックポート切り替え
@param[in] ch チャネル
@param[in] ena 無効にする場合場合「false」
@param[in] odr 候補選択
@param[in] neg 反転入出力の場合「true」 @n
RX220 では、反転入出力をサポートしないので、設定するとエラーになる
@return 無効な周辺機器の場合「false」
*/
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++//
static bool turn_clock(CHANNEL ch, bool ena = true, ORDER odr = ORDER::FIRST, bool neg = false) noexcept
{
if(odr == ORDER::BYPASS) return true;
if(neg) return false;
MPC::PWPR.B0WI = 0; // PWPR 書き込み許可
MPC::PWPR.PFSWE = 1; // PxxPFS 書き込み許可
bool ret = true;
switch(ch) {
case CHANNEL::CLK_A:
ret = clk_a_(odr, ena);
break;
case CHANNEL::CLK_B:
ret = clk_b_(odr, ena);
break;
case CHANNEL::CLK_C:
ret = clk_c_(odr, ena);
break;
case CHANNEL::CLK_D:
ret = clk_d_(odr, ena);
break;
default:
ret = false;
break;
}
MPC::PWPR = MPC::PWPR.B0WI.b();
return ret;
}
};
}