From 7ce4cfa638a86bfabd7ce8147ea5468d69c1af21 Mon Sep 17 00:00:00 2001 From: maidnl Date: Fri, 8 Sep 2023 10:12:03 +0200 Subject: [PATCH 1/2] renesas: added wait function for IN transaction This fixes a problem found on MSD class where data read from from disks were sometimes partially overwritten by the status MSD message ("USBS..."). The function introduced wait for the hw fifo pipe to be empty, that prevent that new writing in the fife overwrite data which are not yet be transmitted by hw. --- src/portable/renesas/rusb2/dcd_rusb2.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index 3ec1b70b5b..68ef5890f3 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -266,6 +266,13 @@ static void pipe_read_packet_ff(rusb2_reg_t * rusb, tu_fifo_t *f, volatile void tu_fifo_advance_write_pointer(f, count); } + +static void wait_pipe_fifo_empty(rusb2_reg_t* rusb, uint8_t num) { + TU_ASSERT(num); + while( (rusb->PIPE_CTR[num-1] & RUSB2_PIPE_CTR_INBUFM_Msk) > 0 ) {} +} + + //--------------------------------------------------------------------+ // Pipe Transfer //--------------------------------------------------------------------+ @@ -339,6 +346,7 @@ static bool pipe_xfer_in(rusb2_reg_t* rusb, unsigned num) const unsigned rem = pipe->remaining; if (!rem) { + wait_pipe_fifo_empty(rusb, num); pipe->buf = NULL; return true; } From 228acbeac2642534753beffd866db2a7eab45e31 Mon Sep 17 00:00:00 2001 From: maidnl Date: Fri, 8 Sep 2023 15:48:05 +0200 Subject: [PATCH 2/2] wait_pipe_fifo_empty() now returns bool (as expected using TU_ASSERT macro) --- src/portable/renesas/rusb2/dcd_rusb2.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index 68ef5890f3..24edc30e7a 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -267,9 +267,10 @@ static void pipe_read_packet_ff(rusb2_reg_t * rusb, tu_fifo_t *f, volatile void } -static void wait_pipe_fifo_empty(rusb2_reg_t* rusb, uint8_t num) { +static bool wait_pipe_fifo_empty(rusb2_reg_t* rusb, uint8_t num) { TU_ASSERT(num); while( (rusb->PIPE_CTR[num-1] & RUSB2_PIPE_CTR_INBUFM_Msk) > 0 ) {} + return true; }