diff --git a/drivers/net/ethernet/renesas/rswitch.c b/drivers/net/ethernet/renesas/rswitch.c
index 4b431e6bbc7b..16c232245f34 100644
--- a/drivers/net/ethernet/renesas/rswitch.c
+++ b/drivers/net/ethernet/renesas/rswitch.c
@@ -943,6 +943,7 @@ struct rswitch_ext_ts_desc {
 struct rswitch_etha {
 	int index;
 	void __iomem *addr;
+	void __iomem *serdes_common_addr;
 	void __iomem *serdes_addr;
 	bool external_phy;
 	struct mii_bus *mii;
@@ -1427,9 +1428,29 @@ static int rswitch_serdes_reg_wait(void __iomem *addr, u32 offs, u32 bank, u32 m
 	return -ETIMEDOUT;
 }
 
+static int rswitch_serdes_common_initialize_sram(struct rswitch_etha *etha)
+{
+	int ret;
+
+	ret = rswitch_serdes_reg_wait(etha->serdes_common_addr, VR_XS_PMA_MP_12G_16G_25G_SRAM,
+				      BANK_180, BIT(0), 0x01);
+	if (ret)
+		return ret;
+
+	rswitch_serdes_write32(etha->serdes_common_addr, VR_XS_PMA_MP_12G_16G_25G_SRAM,
+			       BANK_180, 0x3);
+
+	ret = rswitch_serdes_reg_wait(etha->serdes_common_addr, SR_XS_PCS_CTRL1, BANK_300,
+				      BIT(15), 0);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
 static int rswitch_serdes_common_setting(struct rswitch_etha *etha, enum rswitch_serdes_mode mode)
 {
-	void __iomem *addr = etha->serdes_addr;
+	void __iomem *addr = etha->serdes_common_addr;
 
 	switch (mode) {
 	case SGMII:
@@ -1450,7 +1471,6 @@ static int rswitch_serdes_common_setting(struct rswitch_etha *etha, enum rswitch
 static int rswitch_serdes_chan_setting(struct rswitch_etha *etha, enum rswitch_serdes_mode mode)
 {
 	void __iomem *addr = etha->serdes_addr;
-	u32 val;
 	int ret;
 
 	switch (mode) {
@@ -1458,13 +1478,7 @@ static int rswitch_serdes_chan_setting(struct rswitch_etha *etha, enum rswitch_s
 		rswitch_serdes_write32(addr, SR_XS_PCS_CTRL2, BANK_300, 0x01);
 		rswitch_serdes_write32(addr, VR_XS_PCS_DIG_CTRL1, BANK_380, 0x2000);
 
-		/* Set common settings*/
-		ret = rswitch_serdes_common_setting(etha, mode);
-		if (ret)
-			return ret;
-
-		rswitch_serdes_write32(addr, VR_XS_PMA_MP_12G_16G_25G_MPLL_CMN_CTRL,
-				       BANK_180, 0x11);
+		rswitch_serdes_write32(addr, VR_XS_PMA_MP_12G_16G_25G_MPLL_CMN_CTRL, BANK_180, 0x11);
 		rswitch_serdes_write32(addr, VR_XS_PMA_MP_12G_16G_25G_VCO_CAL_LD0, BANK_180, 0x540);
 		rswitch_serdes_write32(addr, VR_XS_PMA_MP_12G_VCO_CAL_REF0, BANK_180, 0x15);
 		rswitch_serdes_write32(addr, VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL1, BANK_180, 0x100);
@@ -1477,20 +1491,25 @@ static int rswitch_serdes_chan_setting(struct rswitch_etha *etha, enum rswitch_s
 		rswitch_serdes_write32(addr, VR_XS_PMA_MP_12G_RX_EQ_CTRL0, BANK_180, 0x07);
 		rswitch_serdes_write32(addr, VR_XS_PMA_MP_10G_RX_IQ_CTRL0, BANK_180, 0);
 		rswitch_serdes_write32(addr, VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1, BANK_180, 0x310);
-		rswitch_serdes_write32(addr, VR_XS_PCS_DIG_CTRL1, BANK_380, 0xa000);
-		ret = rswitch_serdes_reg_wait(addr, VR_XS_PCS_DIG_CTRL1, BANK_380, BIT(15), 0);
+
+		rswitch_serdes_write32(addr, VR_XS_PMA_MP_12G_16G_TX_GENCTRL2, BANK_180, 0x0101);
+		ret = rswitch_serdes_reg_wait(addr, VR_XS_PMA_MP_12G_16G_TX_GENCTRL2, BANK_180, BIT(0), 0);
 		if (ret)
 			return ret;
 
-		rswitch_serdes_write32(addr, VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1,
-				       BANK_180, 0x1310);
-		rswitch_serdes_write32(addr, VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL0,
-				       BANK_180, 0x1800);
-		rswitch_serdes_write32(addr, VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL1, BANK_180, 0);
+		rswitch_serdes_write32(addr, VR_XS_PMA_MP_12G_16G_RX_GENCTRL2, BANK_180, 0x101);
+		ret = rswitch_serdes_reg_wait(addr, VR_XS_PMA_MP_12G_16G_RX_GENCTRL2, BANK_180, BIT(0), 0);
+		if (ret)
+			return ret;
 
-		val = rswitch_serdes_read32(addr, VR_MII_AN_CTRL, BANK_1F80);
-		rswitch_serdes_write32(addr, VR_MII_AN_CTRL, BANK_1F80, val | 0x100);
+		rswitch_serdes_write32(addr, VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1, BANK_180, 0x1310);
+		rswitch_serdes_write32(addr, VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL0, BANK_180, 0x1800);
+		rswitch_serdes_write32(addr, VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL1, BANK_180, 0);
 
+		rswitch_serdes_write32(addr, VR_XS_PCS_DIG_CTRL1, BANK_380, 0x2100);
+		ret = rswitch_serdes_reg_wait(addr, VR_XS_PCS_DIG_CTRL1, BANK_380, BIT(8), 0);
+		if (ret)
+			return ret;
 		break;
 	default:
 		return -EOPNOTSUPP;
@@ -1537,19 +1556,25 @@ static int __maybe_unused rswitch_serdes_init(struct rswitch_etha *etha)
 		return -EOPNOTSUPP;
 	}
 
+	/* Initialize SRAM */
+	ret = rswitch_serdes_common_initialize_sram(etha);
+	if (ret)
+		return ret;
+
 	/* Disable FUSE_OVERRIDE_EN */
 	if (ioread32(etha->serdes_addr + RSWITCH_SERDES_FUSE_OVERRIDE(etha->index)))
 		iowrite32(0, etha->serdes_addr + RSWITCH_SERDES_FUSE_OVERRIDE(etha->index));
 
-	/* Initialize SRAM */
-	ret = rswitch_serdes_reg_wait(etha->serdes_addr, VR_XS_PMA_MP_12G_16G_25G_SRAM, BANK_180,
-				      BIT(0), 0x01);
+	/* Set common settings*/
+	ret = rswitch_serdes_common_setting(etha, mode);
 	if (ret)
 		return ret;
 
-	rswitch_serdes_write32(etha->serdes_addr, VR_XS_PMA_MP_12G_16G_25G_SRAM, BANK_180, 0x3);
+	/* Assert softreset for PHY */
+	rswitch_serdes_write32(etha->serdes_common_addr, VR_XS_PCS_DIG_CTRL1, BANK_380, 0x8000);
 
-	ret = rswitch_serdes_reg_wait(etha->serdes_addr, SR_XS_PCS_CTRL1, BANK_300, BIT(15), 0);
+	/* Initialize SRAM */
+	ret = rswitch_serdes_common_initialize_sram(etha);
 	if (ret)
 		return ret;
 
@@ -2287,6 +2312,7 @@ static int rswitch_ndev_register(struct rswitch_private *priv, int index)
 
 	ndev->features = NETIF_F_RXCSUM;
 	ndev->hw_features = NETIF_F_RXCSUM;
+	ndev->hw_features = NETIF_F_HW_TC;
 	ndev->base_addr = (unsigned long)rdev->addr;
 	snprintf(ndev->name, IFNAMSIZ, "tsn%d", index);
 	ndev->netdev_ops = &rswitch_netdev_ops;