diff --git a/.github/workflows/integration.yaml b/.github/workflows/integration.yaml index 732e5c4f38..f894414d3e 100644 --- a/.github/workflows/integration.yaml +++ b/.github/workflows/integration.yaml @@ -78,7 +78,7 @@ jobs: zig: needs: build_zig_test_binary - name: Zig (${{ matrix.os.name }}, ${{ matrix.arch }}, ${{ matrix.compiler }}) + name: Zig (${{ matrix.os.name }}, ${{ matrix.arch }}) runs-on: ${{ matrix.os.version }} strategy: fail-fast: false # don't fail fast as sometimes failures are arch/OS specific @@ -92,18 +92,15 @@ jobs: name: macOS - version: windows-2022 name: Windows - compiler: [baseline] arch: [amd64] include: - os: version: macos-14 name: macOS - compiler: optimizing arch: "arm64" - os: version: ubuntu-22.04 name: Ubuntu - compiler: optimizing arch: "amd64" go-version: "1.21" @@ -129,7 +126,7 @@ jobs: - name: Run built test binaries run: | cd ${{ env.STDLIB_TESTS }} - go test -bench='BenchmarkZig/${{ matrix.compiler }}' + go test -bench='BenchmarkZig' -timeout=20m build_tinygo_test_binary: name: Build TinyGo test binary @@ -168,7 +165,7 @@ jobs: tinygo: needs: build_tinygo_test_binary - name: TinyGo (${{ matrix.os.name }}, ${{ matrix.arch }}, ${{ matrix.compiler }}) + name: TinyGo (${{ matrix.os.name }}, ${{ matrix.arch }}) runs-on: ${{ matrix.os.version }} strategy: fail-fast: false # don't fail fast as sometimes failures are arch/OS specific @@ -182,18 +179,15 @@ jobs: name: macOS - version: windows-2022 name: Windows - compiler: [baseline] arch: [amd64] include: - os: version: macos-14 name: macOS - compiler: optimizing arch: "arm64" - os: version: ubuntu-22.04 name: Ubuntu - compiler: optimizing arch: "amd64" go-version: "1.21" @@ -219,7 +213,7 @@ jobs: - name: Run test binaries run: | cd ${{ env.STDLIB_TESTS }} - go test -bench='BenchmarkTinyGo/${{ matrix.compiler }}' + go test -bench='BenchmarkTinyGo' -timeout=20m wasi-testsuite: name: wasi-testsuite @@ -280,7 +274,7 @@ jobs: go_tests: # Due to the embedding of the GOROOT of the building env(https://github.com/golang/go/blob/3c59639b902fada0a2e5a6a35bafd10fc9183b89/src/os/os_test.go#L112), # we have to build and cache on each OS unlike others in this file. - name: Go-${{ matrix.go-version }} (${{ matrix.os.name }}, ${{ matrix.arch }}, ${{ matrix.compiler }}) + name: Go-${{ matrix.go-version }} (${{ matrix.os.name }}, ${{ matrix.arch }}) runs-on: ${{ matrix.os.version }} strategy: fail-fast: false # don't fail fast as sometimes failures are arch/OS specific @@ -294,7 +288,6 @@ jobs: name: macOS - version: windows-2022 name: Windows - compiler: [baseline] arch: [amd64] go-version: - "1.21" @@ -303,25 +296,21 @@ jobs: - os: version: macos-14 name: macOS - compiler: optimizing arch: "arm64" go-version: "1.21" - os: version: macos-14 name: macOS - compiler: optimizing arch: "arm64" go-version: "1.22" - os: version: ubuntu-22.04 name: Ubuntu - compiler: optimizing arch: "amd64" go-version: "1.21" - os: version: ubuntu-22.04 name: Ubuntu - compiler: optimizing arch: "amd64" go-version: "1.22" @@ -358,10 +347,10 @@ jobs: - name: Run built test binaries run: | cd ${{ env.STDLIB_TESTS }} - go test -bench='BenchmarkWasip1/${{ matrix.compiler }}' + go test -bench='BenchmarkWasip1' -timeout=20m libsodium: - name: libsodium (${{ matrix.os.name }}, ${{ matrix.os.arch }}, optimizing) + name: libsodium (${{ matrix.os.name }}, ${{ matrix.os.arch }}) runs-on: ${{ matrix.os.version }} strategy: fail-fast: false # don't fail fast as sometimes failures are arch/OS specific diff --git a/.github/workflows/release.yaml b/.github/workflows/release.yaml index 935bc06d4f..b8c3b56ef5 100644 --- a/.github/workflows/release.yaml +++ b/.github/workflows/release.yaml @@ -48,9 +48,13 @@ jobs: # windows-2022 is missing osslsigncode (no issue, yet) - name: "Install osslsigncode, infozip; setup wix" run: | + # Find "C:\Program Files (x86)\WiX Toolset \" + WIXDIR=`ls '/c/Program Files (x86)'|grep WiX` + WIXBIN="C:\\Program Files (x86)\\$WIXDIR\\bin" + echo WIXBIN=$WIXBIN + echo $WIXBIN >> $GITHUB_PATH choco install osslsigncode -y choco install zip -y - echo "C:\Program Files (x86)\WiX Toolset v3.11\bin" >> $GITHUB_PATH - name: Download Windows code signing certificate env: diff --git a/Makefile b/Makefile index ffc7c8cd13..47990b4d81 100644 --- a/Makefile +++ b/Makefile @@ -23,7 +23,6 @@ go_test_options ?= -timeout 300s ensureCompilerFastest := -ldflags '-X github.com/tetratelabs/wazero/internal/integration_test/vs.ensureCompilerFastest=true' .PHONY: bench bench: - @go test -run=NONE -benchmem -bench=. ./internal/engine/compiler/... @go build ./internal/integration_test/bench/... @# Don't use -test.benchmem as it isn't accurate when comparing against CGO libs @for d in vs/time vs/wasmedge vs/wasmtime ; do \ diff --git a/RATIONALE.md b/RATIONALE.md index a1ebb61629..484e1f525f 100644 --- a/RATIONALE.md +++ b/RATIONALE.md @@ -1536,7 +1536,38 @@ If a module reaches this limit, an error is returned at the compilation phase. ## Compiler engine implementation -See [compiler/RATIONALE.md](internal/engine/compiler/RATIONALE.md). +### Why it's safe to execute runtime-generated machine codes against async Goroutine preemption + +Goroutine preemption is the mechanism of the Go runtime to switch goroutines contexts on an OS thread. +There are two types of preemption: cooperative preemption and async preemption. The former happens, for example, +when making a function call, and it is not an issue for our runtime-generated functions as they do not make +direct function calls to Go-implemented functions. On the other hand, the latter, async preemption, can be problematic +since it tries to interrupt the execution of Goroutine at any point of function, and manipulates CPU register states. + +Fortunately, our runtime-generated machine codes do not need to take the async preemption into account. +All the assembly codes are entered via the trampoline implemented as Go Assembler Function (e.g. [arch_amd64.s](./arch_amd64.s)), +and as of Go 1.20, these assembler functions are considered as _unsafe_ for async preemption: +- https://github.com/golang/go/blob/go1.20rc1/src/runtime/preempt.go#L406-L407 +- https://github.com/golang/go/blob/9f0234214473dfb785a5ad84a8fc62a6a395cbc3/src/runtime/traceback.go#L227 + +From the Go runtime point of view, the execution of runtime-generated machine codes is considered as a part of +that trampoline function. Therefore, runtime-generated machine code is also correctly considered unsafe for async preemption. + +## Why context cancellation is handled in Go code rather than native code + +Since [wazero v1.0.0-pre.9](https://github.com/tetratelabs/wazero/releases/tag/v1.0.0-pre.9), the runtime +supports integration with Go contexts to interrupt execution after a timeout, or in response to explicit cancellation. +This support is internally implemented as a special opcode `builtinFunctionCheckExitCode` that triggers the execution of +a Go function (`ModuleInstance.FailIfClosed`) that atomically checks a sentinel value at strategic points in the code +(e.g. [within loops][checkexitcode_loop]). + +[It _is indeed_ possible to check the sentinel value directly, without leaving the native world][native_check], thus sparing some cycles; +however, because native code never preempts (see section above), this may lead to a state where the other goroutines +never get the chance to run, and thus never get the chance to set the sentinel value; effectively preventing +cancellation from taking place. + +[checkexitcode_loop]: https://github.com/tetratelabs/wazero/blob/86444c67a37dbf9e693ae5b365901f64968d9025/internal/wazeroir/compiler.go#L467-L476 +[native_check]: https://github.com/tetratelabs/wazero/issues/1409 ## Golang patterns diff --git a/README.md b/README.md index e986cfd0f7..657da29594 100644 --- a/README.md +++ b/README.md @@ -41,8 +41,6 @@ during `Runtime.CompileModule`. This means your WebAssembly functions execute natively at runtime. Compiler is faster than Interpreter, often by order of magnitude (10x) or more. This is done without host-specific dependencies. -If interested, check out the [RATIONALE.md][8] and help us optimize further! - ### Conformance Both runtimes pass WebAssembly Core [1.0][7] and [2.0][14] specification tests @@ -123,7 +121,6 @@ wazero is a registered trademark of Tetrate.io, Inc. in the United States and/or [5]: https://github.com/WebAssembly/WASI [6]: https://pkg.go.dev/golang.org/x/sys/unix [7]: https://github.com/WebAssembly/spec/tree/wg-1.0/test/core -[8]: internal/engine/compiler/RATIONALE.md [9]: https://github.com/tetratelabs/wazero/issues/506 [10]: https://go.dev/doc/devel/release [11]: https://github.com/actions/virtual-environments diff --git a/builder_test.go b/builder_test.go index dc13221dd6..2e80fe48ba 100644 --- a/builder_test.go +++ b/builder_test.go @@ -308,9 +308,7 @@ func TestNewHostModuleBuilder_Compile(t *testing.T) { tc := tt t.Run(tc.name, func(t *testing.T) { - cfg := NewRuntimeConfig() - cfg.(*runtimeConfig).EnableOptimizingCompiler() - b := tc.input(NewRuntimeWithConfig(testCtx, cfg)).(*hostModuleBuilder) + b := tc.input(NewRuntime(testCtx)).(*hostModuleBuilder) compiled, err := b.Compile(testCtx) require.NoError(t, err) m := compiled.(*compiledModule) diff --git a/cmd/wazero/wazero.go b/cmd/wazero/wazero.go index a58e0e1376..d4667049ee 100644 --- a/cmd/wazero/wazero.go +++ b/cmd/wazero/wazero.go @@ -19,7 +19,6 @@ import ( "github.com/tetratelabs/wazero/api" "github.com/tetratelabs/wazero/experimental" "github.com/tetratelabs/wazero/experimental/logging" - "github.com/tetratelabs/wazero/experimental/opt" "github.com/tetratelabs/wazero/experimental/sock" "github.com/tetratelabs/wazero/experimental/sysfs" "github.com/tetratelabs/wazero/imports/wasi_snapshot_preview1" @@ -160,10 +159,6 @@ func doRun(args []string, stdOut io.Writer, stdErr logging.Writer) int { flags.BoolVar(&useInterpreter, "interpreter", false, "Interprets WebAssembly modules instead of compiling them into native code.") - var useOptimizingCompiler bool - flags.BoolVar(&useOptimizingCompiler, "optimizing-compiler", false, - "[Experimental] Compiles WebAssembly modules using the optimizing compiler.") - var envs sliceFlag flags.Var(&envs, "env", "key=value pair of environment variable to expose to the binary. "+ "Can be specified multiple times.") @@ -272,8 +267,6 @@ func doRun(args []string, stdOut io.Writer, stdErr logging.Writer) int { var rtc wazero.RuntimeConfig if useInterpreter { rtc = wazero.NewRuntimeConfigInterpreter() - } else if useOptimizingCompiler { - rtc = opt.NewRuntimeConfigOptimizingCompiler() } else { rtc = wazero.NewRuntimeConfig() } diff --git a/config.go b/config.go index 00e223031d..04bce10e3c 100644 --- a/config.go +++ b/config.go @@ -12,7 +12,6 @@ import ( "github.com/tetratelabs/wazero/api" experimentalsys "github.com/tetratelabs/wazero/experimental/sys" - "github.com/tetratelabs/wazero/internal/engine/compiler" "github.com/tetratelabs/wazero/internal/engine/interpreter" "github.com/tetratelabs/wazero/internal/engine/wazevo" "github.com/tetratelabs/wazero/internal/filecache" @@ -158,7 +157,7 @@ type RuntimeConfig interface { // This is especially useful when one wants to run untrusted Wasm binaries since otherwise, any invocation of // api.Function can potentially block the corresponding Goroutine forever. Moreover, it might block the // entire underlying OS thread which runs the api.Function call. See "Why it's safe to execute runtime-generated - // machine codes against async Goroutine preemption" section in internal/engine/compiler/RATIONALE.md for detail. + // machine codes against async Goroutine preemption" section in RATIONALE.md for detail. // // Note that this comes with a bit of extra cost when enabled. The reason is that internally this forces // interpreter and compiler runtimes to insert the periodical checks on the conditions above. For that reason, @@ -191,11 +190,6 @@ type runtimeConfig struct { ensureTermination bool } -// EnableOptimizingCompiler implements experimental/opt/enabler.EnableOptimizingCompiler. -func (c *runtimeConfig) EnableOptimizingCompiler() { - c.newEngine = wazevo.NewEngine -} - // engineLessConfig helps avoid copy/pasting the wrong defaults. var engineLessConfig = &runtimeConfig{ enabledFeatures: api.CoreFeaturesV2, @@ -229,7 +223,7 @@ const ( func NewRuntimeConfigCompiler() RuntimeConfig { ret := engineLessConfig.clone() ret.engineKind = engineKindCompiler - ret.newEngine = compiler.NewEngine + ret.newEngine = wazevo.NewEngine return ret } diff --git a/experimental/checkpoint_example_test.go b/experimental/checkpoint_example_test.go index d995befea3..2c9cbeed69 100644 --- a/experimental/checkpoint_example_test.go +++ b/experimental/checkpoint_example_test.go @@ -23,7 +23,8 @@ type snapshotsKey struct{} func Example_enableSnapshotterKey() { ctx := context.Background() - rt := wazero.NewRuntime(ctx) + // TODO: currently, only the interpreter is supported for snapshotting. + rt := wazero.NewRuntimeWithConfig(ctx, wazero.NewRuntimeConfigInterpreter()) defer rt.Close(ctx) // This closes everything this Runtime created. // Enable experimental snapshotting functionality by setting it to context. We use this diff --git a/experimental/checkpoint_test.go b/experimental/checkpoint_test.go index 3abf921f9b..07e71a9272 100644 --- a/experimental/checkpoint_test.go +++ b/experimental/checkpoint_test.go @@ -13,7 +13,8 @@ import ( func TestSnapshotNestedWasmInvocation(t *testing.T) { ctx := context.Background() - rt := wazero.NewRuntime(ctx) + // TODO: currently, only the interpreter is supported for snapshotting. + rt := wazero.NewRuntimeWithConfig(ctx, wazero.NewRuntimeConfigInterpreter()) defer rt.Close(ctx) sidechannel := 0 @@ -69,7 +70,8 @@ func TestSnapshotNestedWasmInvocation(t *testing.T) { func TestSnapshotMultipleWasmInvocations(t *testing.T) { ctx := context.Background() - rt := wazero.NewRuntime(ctx) + // TODO: currently, only the interpreter is supported for snapshotting. + rt := wazero.NewRuntimeWithConfig(ctx, wazero.NewRuntimeConfigInterpreter()) defer rt.Close(ctx) _, err := rt.NewHostModuleBuilder("example"). diff --git a/experimental/features_example_test.go b/experimental/features_example_test.go index efb62cf556..383e955b53 100644 --- a/experimental/features_example_test.go +++ b/experimental/features_example_test.go @@ -6,9 +6,10 @@ import ( "fmt" "log" "runtime" + "sync" "sync/atomic" - wazero "github.com/tetratelabs/wazero" + "github.com/tetratelabs/wazero" "github.com/tetratelabs/wazero/api" "github.com/tetratelabs/wazero/experimental" "github.com/tetratelabs/wazero/imports/wasi_snapshot_preview1" @@ -33,7 +34,9 @@ func ExampleCoreFeaturesThreads() { ctx := context.Background() // Threads support must be enabled explicitly in addition to standard V2 features. - cfg := wazero.NewRuntimeConfig().WithCoreFeatures(api.CoreFeaturesV2 | experimental.CoreFeaturesThreads) + + // TODO: currently, only the interpreter is supported for snapshotting. + cfg := wazero.NewRuntimeConfigInterpreter().WithCoreFeatures(api.CoreFeaturesV2 | experimental.CoreFeaturesThreads) r := wazero.NewRuntimeWithConfig(ctx, cfg) defer r.Close(ctx) @@ -102,12 +105,17 @@ type childModule struct { var prevTID uint32 +var childModuleMu sync.Mutex + // wasi sdk maintains a stack per thread within memory, so we must allocate one separately per child // module, corresponding to a host thread, or the stack accesses would collide. wasi sdk does not // currently plan to implement this so we must implement it ourselves. We allocate memory for a stack, // initialize a pthread struct at the beginning of the stack, and set globals to reference it. // https://github.com/WebAssembly/wasi-threads/issues/45 func createChildModule(rt wazero.Runtime, root api.Module, wasmCompiled wazero.CompiledModule) *childModule { + childModuleMu.Lock() + defer childModuleMu.Unlock() + ctx := context.Background() // Not executing function so the current stack pointer is end of stack @@ -145,8 +153,8 @@ func createChildModule(rt wazero.Runtime, root api.Module, wasmCompiled wazero.C // This is relying on libc implementation details. The structure has been stable for a long time // though it is possible it could change if compiling with a different version of wasi sdk. tid := atomic.AddUint32(&prevTID, 1) - root.Memory().WriteUint32Le(ptr, ptr) - root.Memory().WriteUint32Le(ptr+20, tid) + child.Memory().WriteUint32Le(ptr, ptr) + child.Memory().WriteUint32Le(ptr+20, tid) child.ExportedGlobal("__stack_pointer").(api.MutableGlobal).Set(uint64(ptr) + size) ret := &childModule{ diff --git a/experimental/listener_test.go b/experimental/listener_test.go index f9d78f68bf..c634451b2b 100644 --- a/experimental/listener_test.go +++ b/experimental/listener_test.go @@ -8,9 +8,7 @@ import ( "github.com/tetratelabs/wazero" "github.com/tetratelabs/wazero/api" "github.com/tetratelabs/wazero/experimental" - "github.com/tetratelabs/wazero/experimental/opt" "github.com/tetratelabs/wazero/experimental/wazerotest" - "github.com/tetratelabs/wazero/internal/platform" "github.com/tetratelabs/wazero/internal/testing/binaryencoding" "github.com/tetratelabs/wazero/internal/testing/require" "github.com/tetratelabs/wazero/internal/wasm" @@ -75,12 +73,7 @@ func TestFunctionListenerFactory(t *testing.T) { }, }) - var r wazero.Runtime - if platform.CompilerSupported() { - r = wazero.NewRuntimeWithConfig(ctx, opt.NewRuntimeConfigOptimizingCompiler()) - } else { - r = wazero.NewRuntime(ctx) - } + r := wazero.NewRuntime(ctx) defer r.Close(ctx) // This closes everything this Runtime created. _, err := r.NewHostModuleBuilder("host").NewFunctionBuilder().WithFunc(func() {}).Export("").Instantiate(ctx) diff --git a/experimental/opt/opt.go b/experimental/opt/opt.go deleted file mode 100644 index fa796731b4..0000000000 --- a/experimental/opt/opt.go +++ /dev/null @@ -1,18 +0,0 @@ -package opt - -import ( - "github.com/tetratelabs/wazero" -) - -type enabler interface { - // EnableOptimizingCompiler enables the optimizing compiler. - // This is only implemented the internal type of wazero.runtimeConfig. - EnableOptimizingCompiler() -} - -// NewRuntimeConfigOptimizingCompiler returns a new RuntimeConfig with the optimizing compiler enabled. -func NewRuntimeConfigOptimizingCompiler() wazero.RuntimeConfig { - c := wazero.NewRuntimeConfig() - c.(enabler).EnableOptimizingCompiler() - return c -} diff --git a/experimental/opt/opt_test.go b/experimental/opt/opt_test.go deleted file mode 100644 index a1996f7892..0000000000 --- a/experimental/opt/opt_test.go +++ /dev/null @@ -1,20 +0,0 @@ -package opt_test - -import ( - "context" - "testing" - - "github.com/tetratelabs/wazero" - "github.com/tetratelabs/wazero/experimental/opt" - "github.com/tetratelabs/wazero/internal/platform" - "github.com/tetratelabs/wazero/internal/testing/require" -) - -func TestUseOptimizingCompiler(t *testing.T) { - if !platform.CompilerSupported() { - return - } - c := opt.NewRuntimeConfigOptimizingCompiler() - r := wazero.NewRuntimeWithConfig(context.Background(), c) - require.NoError(t, r.Close(context.Background())) -} diff --git a/imports/emscripten/emscripten_test.go b/imports/emscripten/emscripten_test.go index 8a5e9bfb5e..dd5eb95b53 100644 --- a/imports/emscripten/emscripten_test.go +++ b/imports/emscripten/emscripten_test.go @@ -548,7 +548,11 @@ func TestInstantiateForModule(t *testing.T) { results, err := mod.ExportedFunction(tc.funcName).Call(testCtx, params...) require.NoError(t, err) - require.Equal(t, tc.expectedResults, results) + l := len(tc.expectedResults) + require.Equal(t, l, len(results)) + if l > 0 { + require.Equal(t, tc.expectedResults, results) + } // We expect to see the dynamic function call target require.Equal(t, tc.expectedLog, log.String()) diff --git a/imports/wasi_snapshot_preview1/testdata/zig/build.zig b/imports/wasi_snapshot_preview1/testdata/zig/build.zig index 6bfd17bdac..3cff682136 100644 --- a/imports/wasi_snapshot_preview1/testdata/zig/build.zig +++ b/imports/wasi_snapshot_preview1/testdata/zig/build.zig @@ -12,5 +12,5 @@ pub fn build(b: *std.build.Builder) void { .optimize = optimize, }); - exe.install(); + std.Build.installArtifact(b, exe); } diff --git a/internal/asm/amd64/assembler.go b/internal/asm/amd64/assembler.go deleted file mode 100644 index db744dcfa7..0000000000 --- a/internal/asm/amd64/assembler.go +++ /dev/null @@ -1,108 +0,0 @@ -package amd64 - -import ( - "github.com/tetratelabs/wazero/internal/asm" -) - -// Assembler is the interface used by amd64 compiler. -type Assembler interface { - asm.AssemblerBase - - // CompileJumpToMemory adds jump-type instruction whose destination is stored in the memory address specified by `baseReg+offset`, - // and returns the corresponding Node in the assembled linked list. - CompileJumpToMemory(jmpInstruction asm.Instruction, baseReg asm.Register, offset asm.ConstantValue) - - // CompileRegisterToRegisterWithArg adds an instruction where source and destination - // are `from` and `to` registers. - CompileRegisterToRegisterWithArg(instruction asm.Instruction, from, to asm.Register, arg byte) - - // CompileMemoryWithIndexToRegister adds an instruction where source operand is the memory address - // specified as `srcBaseReg + srcOffsetConst + srcIndex*srcScale` and destination is the register `dstReg`. - // Note: sourceScale must be one of 1, 2, 4, 8. - CompileMemoryWithIndexToRegister( - instruction asm.Instruction, - srcBaseReg asm.Register, - srcOffsetConst int64, - srcIndex asm.Register, - srcScale int16, - dstReg asm.Register, - ) - - // CompileMemoryWithIndexAndArgToRegister is the same as CompileMemoryWithIndexToRegister except that this - // also accepts one argument. - CompileMemoryWithIndexAndArgToRegister( - instruction asm.Instruction, - srcBaseReg asm.Register, - srcOffsetConst int64, - srcIndex asm.Register, - srcScale int16, - dstReg asm.Register, - arg byte, - ) - - // CompileRegisterToMemoryWithIndex adds an instruction where source operand is the register `srcReg`, - // and the destination is the memory address specified as `dstBaseReg + dstOffsetConst + dstIndex*dstScale` - // Note: dstScale must be one of 1, 2, 4, 8. - CompileRegisterToMemoryWithIndex( - instruction asm.Instruction, - srcReg asm.Register, - dstBaseReg asm.Register, - dstOffsetConst int64, - dstIndex asm.Register, - dstScale int16, - ) - - // CompileRegisterToMemoryWithIndexAndArg is the same as CompileRegisterToMemoryWithIndex except that this - // also accepts one argument. - CompileRegisterToMemoryWithIndexAndArg( - instruction asm.Instruction, - srcReg asm.Register, - dstBaseReg asm.Register, - dstOffsetConst int64, - dstIndex asm.Register, - dstScale int16, - arg byte, - ) - - // CompileRegisterToMemoryWithIndexAndLock is the same as CompileRegisterToMemoryWithIndex but with LOCK prefix. - CompileRegisterToMemoryWithIndexAndLock( - instruction asm.Instruction, - srcReg asm.Register, - dstBaseReg asm.Register, - dstOffsetConst int64, - dstIndex asm.Register, - dstScale int16, - ) - - // CompileRegisterToConst adds an instruction where source operand is the register `srcRegister`, - // and the destination is the const `value`. - CompileRegisterToConst(instruction asm.Instruction, srcRegister asm.Register, value int64) asm.Node - - // CompileRegisterToNone adds an instruction where source operand is the register `register`, - // and there's no destination operand. - CompileRegisterToNone(instruction asm.Instruction, register asm.Register) - - // CompileNoneToRegister adds an instruction where destination operand is the register `register`, - // and there's no source operand. - CompileNoneToRegister(instruction asm.Instruction, register asm.Register) - - // CompileNoneToMemory adds an instruction where destination operand is the memory address specified - // as `baseReg+offset`. and there's no source operand. - CompileNoneToMemory(instruction asm.Instruction, baseReg asm.Register, offset int64) - - // CompileConstToMemory adds an instruction where source operand is the constant `value` and - // the destination is the memory address specified as `dstBaseReg+dstOffset`. - CompileConstToMemory(instruction asm.Instruction, value int64, dstBaseReg asm.Register, dstOffset int64) asm.Node - - // CompileMemoryToConst adds an instruction where source operand is the memory address, and - // the destination is the constant `value`. - CompileMemoryToConst(instruction asm.Instruction, srcBaseReg asm.Register, srcOffset int64, value int64) asm.Node - - // CompileStaticConstToRegister adds an instruction where the source operand is asm.StaticConst located in the - // memory and the destination is the dstReg. - CompileStaticConstToRegister(instruction asm.Instruction, c *asm.StaticConst, dstReg asm.Register) error - - // CompileRegisterToStaticConst adds an instruction where the destination operand is asm.StaticConst located in the - // memory and the source is the srcReg. - CompileRegisterToStaticConst(instruction asm.Instruction, srcReg asm.Register, c *asm.StaticConst) error -} diff --git a/internal/asm/amd64/consts.go b/internal/asm/amd64/consts.go deleted file mode 100644 index 5ed66b7a74..0000000000 --- a/internal/asm/amd64/consts.go +++ /dev/null @@ -1,1310 +0,0 @@ -package amd64 - -import ( - "fmt" - - "github.com/tetratelabs/wazero/internal/asm" -) - -// AMD64-specific conditional register states. -// -// See https://www.lri.fr/~filliatr/ens/compil/x86-64.pdf -// See https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf -const ( - // ConditionalRegisterStateE is the e (equal to zero) condition code - ConditionalRegisterStateE = asm.ConditionalRegisterStateUnset + 1 + iota // ZF equal to zero - // ConditionalRegisterStateNE is the ne (not equal to zero) condition code - ConditionalRegisterStateNE // ˜ZF not equal to zero - // ConditionalRegisterStateS is the s (negative) condition code - ConditionalRegisterStateS // SF negative - // ConditionalRegisterStateNS is the ns (non-negative) condition code - ConditionalRegisterStateNS // ˜SF non-negative - // ConditionalRegisterStateG is the g (greater) condition code - ConditionalRegisterStateG // ˜(SF xor OF) & ˜ ZF greater (signed >) - // ConditionalRegisterStateGE is the ge (greater or equal) condition code - ConditionalRegisterStateGE // ˜(SF xor OF) greater or equal (signed >=) - // ConditionalRegisterStateL is the l (less) condition code - ConditionalRegisterStateL // SF xor OF less (signed <) - // ConditionalRegisterStateLE is the le (less or equal) condition code - ConditionalRegisterStateLE // (SF xor OF) | ZF less or equal (signed <=) - // ConditionalRegisterStateA is the a (above) condition code - ConditionalRegisterStateA // ˜CF & ˜ZF above (unsigned >) - // ConditionalRegisterStateAE is the ae (above or equal) condition code - ConditionalRegisterStateAE // ˜CF above or equal (unsigned >=) - // ConditionalRegisterStateB is the b (below) condition code - ConditionalRegisterStateB // CF below (unsigned <) - // ConditionalRegisterStateBE is the be (below or equal) condition code - ConditionalRegisterStateBE // CF | ZF below or equal (unsigned <=) -) - -// AMD64-specific instructions. -// -// Note: This only defines amd64 instructions used by wazero's compiler. -// Note: Naming conventions intentionally match the Go assembler: https://go.dev/doc/asm -// See https://www.felixcloutier.com/x86/index.html -const ( - // NONE is not a real instruction but represents the lack of an instruction - NONE asm.Instruction = iota - // ADDL is the ADD instruction in 32-bit mode. https://www.felixcloutier.com/x86/add - ADDL - // ADDQ is the ADD instruction in 64-bit mode. https://www.felixcloutier.com/x86/add - ADDQ - // ADDSD is the ADDSD instruction. https://www.felixcloutier.com/x86/addsd - ADDSD - // ADDSS is the ADDSS instruction. https://www.felixcloutier.com/x86/addss - ADDSS - // ANDL is the AND instruction in 32-bit mode. https://www.felixcloutier.com/x86/and - ANDL - // ANDPD is the ANDPD instruction. https://www.felixcloutier.com/x86/andpd - ANDPD - // ANDPS is the ANDPS instruction. https://www.felixcloutier.com/x86/andps - ANDPS - // ANDQ is the AND instruction in 64-bit mode. https://www.felixcloutier.com/x86/and - ANDQ - // BSRL is the BSR instruction in 32-bit mode. https://www.felixcloutier.com/x86/bsr - BSRL - // BSRQ is the BSR instruction in 64-bit mode. https://www.felixcloutier.com/x86/bsr - BSRQ - // CDQ is the CDQ instruction. https://www.felixcloutier.com/x86/cwd:cdq:cqo - CDQ - // CLD is the CLD instruction. https://www.felixcloutier.com/x86/cld - CLD - // CMOVQCS is the CMOVC (move if carry) instruction in 64-bit mode. https://www.felixcloutier.com/x86/cmovcc - CMOVQCS - // CMPL is the CMP instruction in 32-bit mode. https://www.felixcloutier.com/x86/cmp - CMPL - // CMPQ is the CMP instruction in 64-bit mode. https://www.felixcloutier.com/x86/cmp - CMPQ - // CMPXCHGQ is the CMPXCHG instruction in 64-bit mode. https://www.felixcloutier.com/x86/cmpxchg - CMPXCHGQ - // CMPXCHGL is the CMPXCHG instruction in 32-bit mode. https://www.felixcloutier.com/x86/cmpxchg - CMPXCHGL - // CMPXCHGW is the CMPXCHG instruction in 16-bit mode. https://www.felixcloutier.com/x86/cmpxchg - CMPXCHGW - // CMPXCHGW is the CMPXCHG instruction in 8-bit mode. https://www.felixcloutier.com/x86/cmpxchg - CMPXCHGB - // COMISD is the COMISD instruction. https://www.felixcloutier.com/x86/comisd - COMISD - // COMISS is the COMISS instruction. https://www.felixcloutier.com/x86/comiss - COMISS - // CQO is the CQO instruction. https://www.felixcloutier.com/x86/cwd:cdq:cqo - CQO - // CVTSD2SS is the CVTSD2SS instruction. https://www.felixcloutier.com/x86/cvtsd2ss - CVTSD2SS - // CVTSL2SD is the CVTSI2SD instruction in 32-bit mode. https://www.felixcloutier.com/x86/cvtsi2sd - CVTSL2SD - // CVTSL2SS is the CVTSI2SS instruction in 32-bit mode. https://www.felixcloutier.com/x86/cvtsi2ss - CVTSL2SS - // CVTSQ2SD is the CVTSI2SD instruction in 64-bit mode. https://www.felixcloutier.com/x86/cvtsi2sd - CVTSQ2SD - // CVTSQ2SS is the CVTSI2SS instruction in 64-bit mode. https://www.felixcloutier.com/x86/cvtsi2ss - CVTSQ2SS - // CVTSS2SD is the CVTSS2SD instruction. https://www.felixcloutier.com/x86/cvtss2sd - CVTSS2SD - // CVTTSD2SL is the CVTTSD2SI instruction in 32-bit mode. https://www.felixcloutier.com/x86/cvttsd2si - CVTTSD2SL - // CVTTSD2SQ is the CVTTSD2SI instruction in 64-bit mode. https://www.felixcloutier.com/x86/cvttsd2si - CVTTSD2SQ - // CVTTSS2SL is the CVTTSS2SI instruction in 32-bit mode. https://www.felixcloutier.com/x86/cvttss2si - CVTTSS2SL - // CVTTSS2SQ is the CVTTSS2SI instruction in 64-bit mode. https://www.felixcloutier.com/x86/cvttss2si - CVTTSS2SQ - // DECQ is the DEC instruction in 64-bit mode. https://www.felixcloutier.com/x86/dec - DECQ - // DIVL is the DIV instruction in 32-bit mode. https://www.felixcloutier.com/x86/div - DIVL - // DIVQ is the DIV instruction in 64-bit mode. https://www.felixcloutier.com/x86/div - DIVQ - // DIVSD is the DIVSD instruction. https://www.felixcloutier.com/x86/divsd - DIVSD - // DIVSS is the DIVSS instruction. https://www.felixcloutier.com/x86/divss - DIVSS - // IDIVL is the IDIV instruction in 32-bit mode. https://www.felixcloutier.com/x86/idiv - IDIVL - // IDIVQ is the IDIV instruction in 64-bit mode. https://www.felixcloutier.com/x86/idiv - IDIVQ - // INCQ is the INC instruction in 64-bit mode. https://www.felixcloutier.com/x86/inc - INCQ - // JCC is the JAE (jump if above or equal) instruction. https://www.felixcloutier.com/x86/jcc - JCC - // JCS is the JB (jump if below) instruction. https://www.felixcloutier.com/x86/jcc - JCS - // JEQ is the JE (jump if equal) instruction. https://www.felixcloutier.com/x86/jcc - JEQ - // JGE is the JGE (jump if greater or equal) instruction. https://www.felixcloutier.com/x86/jcc - JGE - // JGT is the JG (jump if greater) instruction. https://www.felixcloutier.com/x86/jcc - JGT - // JHI is the JNBE (jump if not below or equal) instruction. https://www.felixcloutier.com/x86/jcc - JHI - // JLE is the JLE (jump if less or equal) instruction. https://www.felixcloutier.com/x86/jcc - JLE - // JLS is the JNA (jump if not above) instruction. https://www.felixcloutier.com/x86/jcc - JLS - // JLT is the JL (jump if less) instruction. https://www.felixcloutier.com/x86/jcc - JLT - // JMI is the JS (jump if sign) instruction. https://www.felixcloutier.com/x86/jcc - JMI - // JNE is the JNE (jump if not equal) instruction. https://www.felixcloutier.com/x86/jcc - JNE - // JPC is the JPO (jump if parity odd) instruction. https://www.felixcloutier.com/x86/jcc - JPC - // JPL is the JNS (jump if not sign) instruction. https://www.felixcloutier.com/x86/jcc - JPL - // JPS is the JPE (jump if parity even) instruction. https://www.felixcloutier.com/x86/jcc - JPS - // LEAQ is the LEA instruction in 64-bit mode. https://www.felixcloutier.com/x86/lea - LEAQ - // LZCNTL is the LZCNT instruction in 32-bit mode. https://www.felixcloutier.com/x86/lzcnt - LZCNTL - // LZCNTQ is the LZCNT instruction in 64-bit mode. https://www.felixcloutier.com/x86/lzcnt - LZCNTQ - // MAXSD is the MAXSD instruction. https://www.felixcloutier.com/x86/maxsd - MAXSD - // MAXSS is the MAXSS instruction. https://www.felixcloutier.com/x86/maxss - MAXSS - // MINSD is the MINSD instruction. https://www.felixcloutier.com/x86/minsd - MINSD - // MINSS is the MINSS instruction. https://www.felixcloutier.com/x86/minss - MINSS - // MOVB is the MOV instruction for a single byte. https://www.felixcloutier.com/x86/mov - MOVB - // MOVBLSX is the MOVSX instruction for single byte in 32-bit mode. https://www.felixcloutier.com/x86/movsx:movsxd - MOVBLSX - // MOVBLZX is the MOVZX instruction for single-byte in 32-bit mode. https://www.felixcloutier.com/x86/movzx - MOVBLZX - // MOVBQSX is the MOVSX instruction for single byte in 64-bit mode. https://www.felixcloutier.com/x86/movsx:movsxd - MOVBQSX - // MOVBQZX is the MOVZX instruction for single-byte in 64-bit mode. https://www.felixcloutier.com/x86/movzx - MOVBQZX - // MOVL is the MOV instruction for a double word. - MOVL - // MOVLQSX is the MOVSXD instruction. https://www.felixcloutier.com/x86/movsx:movsxd - MOVLQSX - // MOVLQZX is the MOVZX instruction for a word to a doubleword. https://www.felixcloutier.com/x86/movzx - MOVLQZX - // MOVQ is the MOV instruction for a doubleword. https://www.felixcloutier.com/x86/mov - MOVQ - // MOVW is the MOV instruction for a word. https://www.felixcloutier.com/x86/mov - MOVW - // MOVWLSX is the MOVSX instruction for a word in 32-bit mode. https://www.felixcloutier.com/x86/movsx:movsxd - MOVWLSX - // MOVWLZX is the MOVZX instruction for a word in 32-bit mode. https://www.felixcloutier.com/x86/movzx - MOVWLZX - // MOVWQSX is the MOVSX instruction for a word in 64-bit mode. https://www.felixcloutier.com/x86/movsx:movsxd - MOVWQSX - // MOVWQZX is the MOVZX instruction for a word in 64-bit mode. https://www.felixcloutier.com/x86/movzx - MOVWQZX - // MULL is the MUL instruction in 32-bit mode. https://www.felixcloutier.com/x86/mul - MULL - // MULQ is the MUL instruction in 64-bit mode. https://www.felixcloutier.com/x86/mul - MULQ - // IMULQ is the IMUL instruction in 64-bit mode. https://www.felixcloutier.com/x86/imul - IMULQ - // MULSD is the MULSD instruction. https://www.felixcloutier.com/x86/mulsd - MULSD - // MULSS is the MULSS instruction. https://www.felixcloutier.com/x86/mulss - MULSS - // NEGQ is the NEG instruction in 64-bit mode. https://www.felixcloutier.com/x86/neg - NEGQ - // NEGL is the NEG instruction in 32-bit mode. https://www.felixcloutier.com/x86/neg - NEGL - // NEGW is the NEG instruction in 16-bit mode. https://www.felixcloutier.com/x86/neg - NEGW - // NEGB is the NEG instruction in 8-bit mode. https://www.felixcloutier.com/x86/neg - NEGB - // ORL is the OR instruction in 32-bit mode. https://www.felixcloutier.com/x86/or - ORL - // ORPD is the ORPD instruction. https://www.felixcloutier.com/x86/orpd - ORPD - // ORPS is the ORPS instruction. https://www.felixcloutier.com/x86/orps - ORPS - // ORQ is the OR instruction in 64-bit mode. https://www.felixcloutier.com/x86/or - ORQ - // POPCNTL is the POPCNT instruction in 32-bit mode. https://www.felixcloutier.com/x86/popcnt - POPCNTL - // POPCNTQ is the POPCNT instruction in 64-bit mode. https://www.felixcloutier.com/x86/popcnt - POPCNTQ - // PSLLD is the PSLLD instruction. https://www.felixcloutier.com/x86/psllw:pslld:psllq - PSLLD - // PSLLQ is the PSLLQ instruction. https://www.felixcloutier.com/x86/psllw:pslld:psllq - PSLLQ - // PSRLD is the PSRLD instruction. https://www.felixcloutier.com/x86/psrlw:psrld:psrlq - PSRLD - // PSRLQ is the PSRLQ instruction. https://www.felixcloutier.com/x86/psrlw:psrld:psrlq - PSRLQ - // REPMOVSQ is the REP MOVSQ instruction in 64-bit mode. https://www.felixcloutier.com/x86/movs:movsb:movsw:movsd:movsq https://www.felixcloutier.com/x86/rep:repe:repz:repne:repnz - REPMOVSQ - // REPSTOSQ is the REP STOSQ instruction in 64-bit mode. https://www.felixcloutier.com/x86/stos:stosb:stosw:stosd:stosq https://www.felixcloutier.com/x86/rep:repe:repz:repne:repnz - REPSTOSQ - // ROLL is the ROL instruction in 32-bit mode. https://www.felixcloutier.com/x86/rcl:rcr:rol:ror - ROLL - // ROLQ is the ROL instruction in 64-bit mode. https://www.felixcloutier.com/x86/rcl:rcr:rol:ror - ROLQ - // RORL is the ROR instruction in 32-bit mode. https://www.felixcloutier.com/x86/rcl:rcr:rol:ror - RORL - // RORQ is the ROR instruction in 64-bit mode. https://www.felixcloutier.com/x86/rcl:rcr:rol:ror - RORQ - // ROUNDSD is the ROUNDSD instruction. https://www.felixcloutier.com/x86/roundsd - ROUNDSD - // ROUNDSS is the ROUNDSS instruction. https://www.felixcloutier.com/x86/roundss - ROUNDSS - // SARL is the SAR instruction in 32-bit mode. https://www.felixcloutier.com/x86/sal:sar:shl:shr - SARL - // SARQ is the SAR instruction in 64-bit mode. https://www.felixcloutier.com/x86/sal:sar:shl:shr - SARQ - // SETCC is the SETAE (set if above or equal) instruction. https://www.felixcloutier.com/x86/setcc - SETCC - // SETCS is the SETB (set if below) instruction. https://www.felixcloutier.com/x86/setcc - SETCS - // SETEQ is the SETE (set if equal) instruction. https://www.felixcloutier.com/x86/setcc - SETEQ - // SETGE is the SETGE (set if greater or equal) instruction. https://www.felixcloutier.com/x86/setcc - SETGE - // SETGT is the SETG (set if greater) instruction. https://www.felixcloutier.com/x86/setcc - SETGT - // SETHI is the SETNBE (set if not below or equal) instruction. https://www.felixcloutier.com/x86/setcc - SETHI - // SETLE is the SETLE (set if less or equal) instruction. https://www.felixcloutier.com/x86/setcc - SETLE - // SETLS is the SETNA (set if not above) instruction. https://www.felixcloutier.com/x86/setcc - SETLS - // SETLT is the SETL (set if less) instruction. https://www.felixcloutier.com/x86/setcc - SETLT - // SETMI is the SETS (set if sign) instruction. https://www.felixcloutier.com/x86/setcc - SETMI - // SETNE is the SETNE (set if not equal) instruction. https://www.felixcloutier.com/x86/setcc - SETNE - // SETPC is the SETNP (set if not parity) instruction. https://www.felixcloutier.com/x86/setcc - SETPC - // SETPL is the SETNS (set if not sign) instruction. https://www.felixcloutier.com/x86/setcc - SETPL - // SETPS is the SETP (set if parity) instruction. https://www.felixcloutier.com/x86/setcc - SETPS - // SHLL is the SHL instruction in 32-bit mode. https://www.felixcloutier.com/x86/sal:sar:shl:shr - SHLL - // SHLQ is the SHL instruction in 64-bit mode. https://www.felixcloutier.com/x86/sal:sar:shl:shr - SHLQ - // SHRL is the SHR instruction in 32-bit mode. https://www.felixcloutier.com/x86/sal:sar:shl:shr - SHRL - // SHRQ is the SHR instruction in 64-bit mode. https://www.felixcloutier.com/x86/sal:sar:shl:shr - SHRQ - // SQRTSD is the SQRTSD instruction. https://www.felixcloutier.com/x86/sqrtsd - SQRTSD - // SQRTSS is the SQRTSS instruction. https://www.felixcloutier.com/x86/sqrtss - SQRTSS - // STD is the STD instruction. https://www.felixcloutier.com/x86/std - STD - // SUBL is the SUB instruction in 32-bit mode. https://www.felixcloutier.com/x86/sub - SUBL - // SUBQ is the SUB instruction in 64-bit mode. https://www.felixcloutier.com/x86/sub - SUBQ - // SUBSD is the SUBSD instruction. https://www.felixcloutier.com/x86/subsd - SUBSD - // SUBSS is the SUBSS instruction. https://www.felixcloutier.com/x86/subss - SUBSS - // TESTL is the TEST instruction in 32-bit mode. https://www.felixcloutier.com/x86/test - TESTL - // TESTQ is the TEST instruction in 64-bit mode. https://www.felixcloutier.com/x86/test - TESTQ - // TZCNTL is the TZCNT instruction in 32-bit mode. https://www.felixcloutier.com/x86/tzcnt - TZCNTL - // TZCNTQ is the TZCNT instruction in 64-bit mode. https://www.felixcloutier.com/x86/tzcnt - TZCNTQ - // UCOMISD is the UCOMISD instruction. https://www.felixcloutier.com/x86/ucomisd - UCOMISD - // UCOMISS is the UCOMISS instruction. https://www.felixcloutier.com/x86/ucomisd - UCOMISS - // XORL is the XOR instruction in 32-bit mode. https://www.felixcloutier.com/x86/xor - XORL - // XORPD is the XORPD instruction. https://www.felixcloutier.com/x86/xorpd - XORPD - // XORPS is the XORPS instruction. https://www.felixcloutier.com/x86/xorps - XORPS - // XORQ is the XOR instruction in 64-bit mode. https://www.felixcloutier.com/x86/xor - XORQ - // XCHGQ is the XCHG instruction in 64-bit mode. https://www.felixcloutier.com/x86/xchg - XCHGQ - // XCHGW is the XCHG instruction in 32-bit mode. https://www.felixcloutier.com/x86/xchg - XCHGW - // XCHGL is the XCHG instruction in 16-bit mode. https://www.felixcloutier.com/x86/xchg - XCHGL - // XCHGB is the XCHG instruction in 8-bit mode. https://www.felixcloutier.com/x86/xchg - XCHGB - // RET is the RET instruction. https://www.felixcloutier.com/x86/ret - RET - // JMP is the JMP instruction. https://www.felixcloutier.com/x86/jmp - JMP - // NOP is the NOP instruction. https://www.felixcloutier.com/x86/nop - NOP - // UD2 is the UD2 instruction. https://www.felixcloutier.com/x86/ud - UD2 - // MOVDQU is the MOVDQU instruction in 64-bit mode. https://www.felixcloutier.com/x86/movdqu:vmovdqu8:vmovdqu16:vmovdqu32:vmovdqu64 - MOVDQU - // MOVDQA is the MOVDQA instruction in 64-bit mode. https://www.felixcloutier.com/x86/movdqa:vmovdqa32:vmovdqa64 - MOVDQA - // PINSRB is the PINSRB instruction. https://www.felixcloutier.com/x86/pinsrb:pinsrd:pinsrq - PINSRB - // PINSRW is the PINSRW instruction. https://www.felixcloutier.com/x86/pinsrw - PINSRW - // PINSRD is the PINSRD instruction. https://www.felixcloutier.com/x86/pinsrb:pinsrd:pinsrq - PINSRD - // PINSRQ is the PINSRQ instruction. https://www.felixcloutier.com/x86/pinsrb:pinsrd:pinsrq - PINSRQ - // PADDB is the PADDB instruction. https://www.felixcloutier.com/x86/paddb:paddw:paddd:paddq - PADDB - // PADDW is the PADDW instruction. https://www.felixcloutier.com/x86/paddb:paddw:paddd:paddq - PADDW - // PADDD is the PADDD instruction. https://www.felixcloutier.com/x86/paddb:paddw:paddd:paddq - PADDD - // PADDQ is the PADDQ instruction. https://www.felixcloutier.com/x86/paddb:paddw:paddd:paddq - PADDQ - // PSUBB is the PSUBB instruction. https://www.felixcloutier.com/x86/psubb:psubw:psubd - PSUBB - // PSUBW is the PSUBW instruction. https://www.felixcloutier.com/x86/psubb:psubw:psubd - PSUBW - // PSUBD is the PSUBD instruction. https://www.felixcloutier.com/x86/psubb:psubw:psubd - PSUBD - // PSUBQ is the PSUBQ instruction. https://www.felixcloutier.com/x86/psubq - PSUBQ - // ADDPS is the ADDPS instruction. https://www.felixcloutier.com/x86/addps - ADDPS - // ADDPD is the ADDPD instruction. https://www.felixcloutier.com/x86/addpd - ADDPD - // SUBPS is the SUBPS instruction. https://www.felixcloutier.com/x86/subps - SUBPS - // SUBPD is the SUBPD instruction. https://www.felixcloutier.com/x86/subpd - SUBPD - // PMOVSXBW is the PMOVSXBW instruction https://www.felixcloutier.com/x86/pmovsx - PMOVSXBW - // PMOVSXWD is the PMOVSXWD instruction https://www.felixcloutier.com/x86/pmovsx - PMOVSXWD - // PMOVSXDQ is the PMOVSXDQ instruction https://www.felixcloutier.com/x86/pmovsx - PMOVSXDQ - // PMOVZXBW is the PMOVZXBW instruction https://www.felixcloutier.com/x86/pmovzx - PMOVZXBW - // PMOVZXWD is the PMOVZXWD instruction https://www.felixcloutier.com/x86/pmovzx - PMOVZXWD - // PMOVZXDQ is the PMOVZXDQ instruction https://www.felixcloutier.com/x86/pmovzx - PMOVZXDQ - // PSHUFB is the PSHUFB instruction https://www.felixcloutier.com/x86/pshufb - PSHUFB - // PSHUFD is the PSHUFD instruction https://www.felixcloutier.com/x86/pshufd - PSHUFD - // PXOR is the PXOR instruction https://www.felixcloutier.com/x86/pxor - PXOR - // PEXTRB is the PEXTRB instruction https://www.felixcloutier.com/x86/pextrb:pextrd:pextrq - PEXTRB - // PEXTRW is the PEXTRW instruction https://www.felixcloutier.com/x86/pextrw - PEXTRW - // PEXTRD is the PEXTRD instruction https://www.felixcloutier.com/x86/pextrb:pextrd:pextrq - PEXTRD - // PEXTRQ is the PEXTRQ instruction https://www.felixcloutier.com/x86/pextrb:pextrd:pextrq - PEXTRQ - // MOVLHPS is the MOVLHPS instruction https://www.felixcloutier.com/x86/movlhps - MOVLHPS - // INSERTPS is the INSERTPS instruction https://www.felixcloutier.com/x86/insertps - INSERTPS - // PTEST is the PTEST instruction https://www.felixcloutier.com/x86/ptest - PTEST - // PCMPEQB is the PCMPEQB instruction https://www.felixcloutier.com/x86/pcmpeqb:pcmpeqw:pcmpeqd - PCMPEQB - // PCMPEQW is the PCMPEQW instruction https://www.felixcloutier.com/x86/pcmpeqb:pcmpeqw:pcmpeqd - PCMPEQW - // PCMPEQD is the PCMPEQD instruction https://www.felixcloutier.com/x86/pcmpeqb:pcmpeqw:pcmpeqd - PCMPEQD - // PCMPEQQ is the PCMPEQQ instruction https://www.felixcloutier.com/x86/pcmpeqq - PCMPEQQ - // PADDUSB is the PADDUSB instruction https://www.felixcloutier.com/x86/paddusb:paddusw - PADDUSB - // MOVSD is the MOVSD instruction https://www.felixcloutier.com/x86/movsd - MOVSD - // PACKSSWB is the PACKSSWB instruction https://www.felixcloutier.com/x86/packsswb:packssdw - PACKSSWB - // PMOVMSKB is the PMOVMSKB instruction https://www.felixcloutier.com/x86/pmovmskb - PMOVMSKB - // MOVMSKPS is the MOVMSKPS instruction https://www.felixcloutier.com/x86/movmskps - MOVMSKPS - // MOVMSKPD is the MOVMSKPD instruction https://www.felixcloutier.com/x86/movmskpd - MOVMSKPD - // PAND is the PAND instruction https://www.felixcloutier.com/x86/pand - PAND - // POR is the POR instruction https://www.felixcloutier.com/x86/por - POR - // PANDN is the PANDN instruction https://www.felixcloutier.com/x86/pandn - PANDN - // PSRAD is the PSRAD instruction https://www.felixcloutier.com/x86/psraw:psrad:psraq - PSRAD - // PSRAW is the PSRAW instruction https://www.felixcloutier.com/x86/psraw:psrad:psraq - PSRAW - // PSRLW is the PSRLW instruction https://www.felixcloutier.com/x86/psrlw:psrld:psrlq - PSRLW - // PSLLW is the PSLLW instruction https://www.felixcloutier.com/x86/psllw:pslld:psllq - PSLLW - // PUNPCKLBW is the PUNPCKLBW instruction https://www.felixcloutier.com/x86/punpcklbw:punpcklwd:punpckldq:punpcklqdq - PUNPCKLBW - // PUNPCKHBW is the PUNPCKHBW instruction https://www.felixcloutier.com/x86/punpckhbw:punpckhwd:punpckhdq:punpckhqdq - PUNPCKHBW - // CMPPS is the CMPPS instruction https://www.felixcloutier.com/x86/cmpps - CMPPS - // CMPPD is the https://www.felixcloutier.com/x86/cmppd - CMPPD - // PCMPGTQ is the PCMPGTQ instruction https://www.felixcloutier.com/x86/pcmpgtq - PCMPGTQ - // PCMPGTD is the PCMPGTD instruction https://www.felixcloutier.com/x86/pcmpgtb:pcmpgtw:pcmpgtd - PCMPGTD - // PCMPGTW is the PCMPGTW instruction https://www.felixcloutier.com/x86/pcmpgtb:pcmpgtw:pcmpgtd - PCMPGTW - // PCMPGTB is the PCMPGTB instruction https://www.felixcloutier.com/x86/pcmpgtb:pcmpgtw:pcmpgtd - PCMPGTB - // PMINSD is the PMINSD instruction https://www.felixcloutier.com/x86/pminsd:pminsq - PMINSD - // PMINSW is the PMINSW instruction https://www.felixcloutier.com/x86/pminsb:pminsw - PMINSW - // PMINSB is the PMINSB instruction https://www.felixcloutier.com/x86/pminsb:pminsw - PMINSB - // PMAXSD is the PMAXSD instruction https://www.felixcloutier.com/x86/pmaxsb:pmaxsw:pmaxsd:pmaxsq - PMAXSD - // PMAXSW is the PMAXSW instruction https://www.felixcloutier.com/x86/pmaxsb:pmaxsw:pmaxsd:pmaxsq - PMAXSW - // PMAXSB is the PMAXSB instruction https://www.felixcloutier.com/x86/pmaxsb:pmaxsw:pmaxsd:pmaxsq - PMAXSB - // PMINUD is the PMINUD instruction https://www.felixcloutier.com/x86/pminud:pminuq - PMINUD - // PMINUW is the PMINUW instruction https://www.felixcloutier.com/x86/pminub:pminuw - PMINUW - // PMINUB is the PMINUB instruction https://www.felixcloutier.com/x86/pminub:pminuw - PMINUB - // PMAXUD is the PMAXUD instruction https://www.felixcloutier.com/x86/pmaxud:pmaxuq - PMAXUD - // PMAXUW is the PMAXUW instruction https://www.felixcloutier.com/x86/pmaxub:pmaxuw - PMAXUW - // PMAXUB is the PMAXUB instruction https://www.felixcloutier.com/x86/pmaxub:pmaxuw - PMAXUB - // PMULLW is the PMULLW instruction https://www.felixcloutier.com/x86/pmullw - PMULLW - // PMULLD is the PMULLD instruction https://www.felixcloutier.com/x86/pmulld:pmullq - PMULLD - // PMULUDQ is the PMULUDQ instruction https://www.felixcloutier.com/x86/pmuludq - PMULUDQ - // PSUBSB is the PSUBSB instruction https://www.felixcloutier.com/x86/psubsb:psubsw - PSUBSB - // PSUBSW is the PSUBSW instruction https://www.felixcloutier.com/x86/psubsb:psubsw - PSUBSW - // PSUBUSB is the PSUBUSB instruction https://www.felixcloutier.com/x86/psubusb:psubusw - PSUBUSB - // PSUBUSW is the PSUBUSW instruction https://www.felixcloutier.com/x86/psubusb:psubusw - PSUBUSW - // PADDSW is the PADDSW instruction https://www.felixcloutier.com/x86/paddsb:paddsw - PADDSW - // PADDSB is the PADDSB instruction https://www.felixcloutier.com/x86/paddsb:paddsw - PADDSB - // PADDUSW is the PADDUSW instruction https://www.felixcloutier.com/x86/paddusb:paddusw - PADDUSW - // PAVGB is the PAVGB instruction https://www.felixcloutier.com/x86/pavgb:pavgw - PAVGB - // PAVGW is the PAVGW instruction https://www.felixcloutier.com/x86/pavgb:pavgw - PAVGW - // PABSB is the PABSB instruction https://www.felixcloutier.com/x86/pabsb:pabsw:pabsd:pabsq - PABSB - // PABSW is the PABSW instruction https://www.felixcloutier.com/x86/pabsb:pabsw:pabsd:pabsq - PABSW - // PABSD is the PABSD instruction https://www.felixcloutier.com/x86/pabsb:pabsw:pabsd:pabsq - PABSD - // BLENDVPD is the BLENDVPD instruction https://www.felixcloutier.com/x86/blendvpd - BLENDVPD - // MAXPD is the MAXPD instruction https://www.felixcloutier.com/x86/maxpd - MAXPD - // MAXPS is the MAXPS instruction https://www.felixcloutier.com/x86/maxps - MAXPS - // MINPD is the MINPD instruction https://www.felixcloutier.com/x86/minpd - MINPD - // MINPS is the MINPS instruction https://www.felixcloutier.com/x86/minps - MINPS - // ANDNPD is the ANDNPD instruction https://www.felixcloutier.com/x86/andnpd - ANDNPD - // ANDNPS is the ANDNPS instruction https://www.felixcloutier.com/x86/andnps - ANDNPS - // MULPS is the MULPS instruction https://www.felixcloutier.com/x86/mulps - MULPS - // MULPD is the MULPD instruction https://www.felixcloutier.com/x86/mulpd - MULPD - // DIVPS is the DIVPS instruction https://www.felixcloutier.com/x86/divps - DIVPS - // DIVPD is the DIVPD instruction https://www.felixcloutier.com/x86/divpd - DIVPD - // SQRTPS is the SQRTPS instruction https://www.felixcloutier.com/x86/sqrtps - SQRTPS - // SQRTPD is the SQRTPD instruction https://www.felixcloutier.com/x86/sqrtpd - SQRTPD - // ROUNDPS is the ROUNDPS instruction https://www.felixcloutier.com/x86/roundps - ROUNDPS - // ROUNDPD is the ROUNDPD instruction https://www.felixcloutier.com/x86/roundpd - ROUNDPD - // PALIGNR is the PALIGNR instruction https://www.felixcloutier.com/x86/palignr - PALIGNR - // PUNPCKLWD is the PUNPCKLWD instruction https://www.felixcloutier.com/x86/punpcklbw:punpcklwd:punpckldq:punpcklqdq - PUNPCKLWD - // PUNPCKHWD is the PUNPCKHWD instruction https://www.felixcloutier.com/x86/punpckhbw:punpckhwd:punpckhdq:punpckhqdq - PUNPCKHWD - // PMULHUW is the PMULHUW instruction https://www.felixcloutier.com/x86/pmulhuw - PMULHUW - // PMULDQ is the PMULDQ instruction https://www.felixcloutier.com/x86/pmuldq - PMULDQ - // PMULHRSW is the PMULHRSW instruction https://www.felixcloutier.com/x86/pmulhrsw - PMULHRSW - // PMULHW is the PMULHW instruction https://www.felixcloutier.com/x86/pmulhw - PMULHW - // CMPEQPS is the CMPEQPS instruction https://www.felixcloutier.com/x86/cmpps - CMPEQPS - // CMPEQPD is the CMPEQPD instruction https://www.felixcloutier.com/x86/cmppd - CMPEQPD - // CVTTPS2DQ is the CVTTPS2DQ instruction https://www.felixcloutier.com/x86/cvttps2dq - CVTTPS2DQ - // CVTDQ2PS is the CVTDQ2PS instruction https://www.felixcloutier.com/x86/cvtdq2ps - CVTDQ2PS - // MOVUPD is the MOVUPD instruction https://www.felixcloutier.com/x86/movupd - MOVUPD - // SHUFPS is the SHUFPS instruction https://www.felixcloutier.com/x86/shufps - SHUFPS - // PMADDWD is the PMADDWD instruction https://www.felixcloutier.com/x86/pmaddwd - PMADDWD - // CVTDQ2PD is the CVTDQ2PD instruction https://www.felixcloutier.com/x86/cvtdq2pd - CVTDQ2PD - // UNPCKLPS is the UNPCKLPS instruction https://www.felixcloutier.com/x86/unpcklps - UNPCKLPS - // PACKUSWB is the PACKUSWB instruction https://www.felixcloutier.com/x86/packuswb - PACKUSWB - // PACKSSDW is the PACKSSDW instruction https://www.felixcloutier.com/x86/packsswb:packssdw - PACKSSDW - // PACKUSDW is the PACKUSDW instruction https://www.felixcloutier.com/x86/packusdw - PACKUSDW - // CVTPS2PD is the CVTPS2PD instruction https://www.felixcloutier.com/x86/cvtps2pd - CVTPS2PD - // CVTPD2PS is the CVTPD2PS instruction https://www.felixcloutier.com/x86/cvtpd2ps - CVTPD2PS - // PMADDUBSW is the PMADDUBSW instruction https://www.felixcloutier.com/x86/pmaddubsw - PMADDUBSW - // CVTTPD2DQ is the CVTTPD2DQ instruction https://www.felixcloutier.com/x86/cvttpd2dq - CVTTPD2DQ - - // XADDQ is the XADD instruction in 64-bit mode https://www.felixcloutier.com/x86/xadd - XADDQ - // XADDW is the XADD instruction in 16-bit mode https://www.felixcloutier.com/x86/xadd - XADDW - // XADDL is the XADD instruction in 32-bit mode https://www.felixcloutier.com/x86/xadd - XADDL - // XADDB is the XADD instruction in 8-bit mode https://www.felixcloutier.com/x86/xadd - XADDB - - // MFENCE is the MFENCE instrution https://www.felixcloutier.com/x86/mfence - MFENCE - - // instructionEnd is always placed at the bottom of this iota definition to be used in the test. - instructionEnd -) - -// InstructionName returns the name for an instruction -func InstructionName(instruction asm.Instruction) string { - switch instruction { - case ADDL: - return "ADDL" - case ADDQ: - return "ADDQ" - case ADDSD: - return "ADDSD" - case ADDSS: - return "ADDSS" - case ANDL: - return "ANDL" - case ANDPD: - return "ANDPD" - case ANDPS: - return "ANDPS" - case ANDQ: - return "ANDQ" - case BSRL: - return "BSRL" - case BSRQ: - return "BSRQ" - case CDQ: - return "CDQ" - case CLD: - return "CLD" - case CMOVQCS: - return "CMOVQCS" - case CMPL: - return "CMPL" - case CMPQ: - return "CMPQ" - case CMPXCHGQ: - return "CMPXCHGQ" - case CMPXCHGL: - return "CMPXCHGL" - case CMPXCHGW: - return "CMPXCHGW" - case CMPXCHGB: - return "CMPXCHGB" - case COMISD: - return "COMISD" - case COMISS: - return "COMISS" - case CQO: - return "CQO" - case CVTSD2SS: - return "CVTSD2SS" - case CVTSL2SD: - return "CVTSL2SD" - case CVTSL2SS: - return "CVTSL2SS" - case CVTSQ2SD: - return "CVTSQ2SD" - case CVTSQ2SS: - return "CVTSQ2SS" - case CVTSS2SD: - return "CVTSS2SD" - case CVTTSD2SL: - return "CVTTSD2SL" - case CVTTSD2SQ: - return "CVTTSD2SQ" - case CVTTSS2SL: - return "CVTTSS2SL" - case CVTTSS2SQ: - return "CVTTSS2SQ" - case DECQ: - return "DECQ" - case DIVL: - return "DIVL" - case DIVQ: - return "DIVQ" - case DIVSD: - return "DIVSD" - case DIVSS: - return "DIVSS" - case IDIVL: - return "IDIVL" - case IDIVQ: - return "IDIVQ" - case INCQ: - return "INCQ" - case JCC: - return "JCC" - case JCS: - return "JCS" - case JEQ: - return "JEQ" - case JGE: - return "JGE" - case JGT: - return "JGT" - case JHI: - return "JHI" - case JLE: - return "JLE" - case JLS: - return "JLS" - case JLT: - return "JLT" - case JMI: - return "JMI" - case JNE: - return "JNE" - case JPC: - return "JPC" - case JPL: - return "JPL" - case JPS: - return "JPS" - case LEAQ: - return "LEAQ" - case LZCNTL: - return "LZCNTL" - case LZCNTQ: - return "LZCNTQ" - case MAXSD: - return "MAXSD" - case MAXSS: - return "MAXSS" - case MINSD: - return "MINSD" - case MINSS: - return "MINSS" - case MOVB: - return "MOVB" - case MOVBLSX: - return "MOVBLSX" - case MOVBLZX: - return "MOVBLZX" - case MOVBQSX: - return "MOVBQSX" - case MOVBQZX: - return "MOVBQZX" - case MOVL: - return "MOVL" - case MOVLQSX: - return "MOVLQSX" - case MOVLQZX: - return "MOVLQZX" - case MOVQ: - return "MOVQ" - case MOVW: - return "MOVW" - case MOVWLSX: - return "MOVWLSX" - case MOVWLZX: - return "MOVWLZX" - case MOVWQSX: - return "MOVWQSX" - case MOVWQZX: - return "MOVWQZX" - case MULL: - return "MULL" - case MULQ: - return "MULQ" - case IMULQ: - return "IMULQ" - case MULSD: - return "MULSD" - case MULSS: - return "MULSS" - case ORL: - return "ORL" - case ORPD: - return "ORPD" - case ORPS: - return "ORPS" - case ORQ: - return "ORQ" - case POPCNTL: - return "POPCNTL" - case POPCNTQ: - return "POPCNTQ" - case PSLLD: - return "PSLLD" - case PSLLQ: - return "PSLLQ" - case PSRLD: - return "PSRLD" - case PSRLQ: - return "PSRLQ" - case REPMOVSQ: - return "REP MOVSQ" - case REPSTOSQ: - return "REP STOSQ" - case ROLL: - return "ROLL" - case ROLQ: - return "ROLQ" - case RORL: - return "RORL" - case RORQ: - return "RORQ" - case ROUNDSD: - return "ROUNDSD" - case ROUNDSS: - return "ROUNDSS" - case SARL: - return "SARL" - case SARQ: - return "SARQ" - case SETCC: - return "SETCC" - case SETCS: - return "SETCS" - case SETEQ: - return "SETEQ" - case SETGE: - return "SETGE" - case SETGT: - return "SETGT" - case SETHI: - return "SETHI" - case SETLE: - return "SETLE" - case SETLS: - return "SETLS" - case SETLT: - return "SETLT" - case SETMI: - return "SETMI" - case SETNE: - return "SETNE" - case SETPC: - return "SETPC" - case SETPL: - return "SETPL" - case SETPS: - return "SETPS" - case SHLL: - return "SHLL" - case SHLQ: - return "SHLQ" - case SHRL: - return "SHRL" - case SHRQ: - return "SHRQ" - case SQRTSD: - return "SQRTSD" - case SQRTSS: - return "SQRTSS" - case STD: - return "STD" - case SUBL: - return "SUBL" - case SUBQ: - return "SUBQ" - case SUBSD: - return "SUBSD" - case SUBSS: - return "SUBSS" - case TESTL: - return "TESTL" - case TESTQ: - return "TESTQ" - case TZCNTL: - return "TZCNTL" - case TZCNTQ: - return "TZCNTQ" - case UCOMISD: - return "UCOMISD" - case UCOMISS: - return "UCOMISS" - case XORL: - return "XORL" - case XORPD: - return "XORPD" - case XORPS: - return "XORPS" - case XORQ: - return "XORQ" - case XCHGQ: - return "XCHGQ" - case XCHGW: - return "XCHGW" - case XCHGL: - return "XCHGL" - case XCHGB: - return "XCHGB" - case RET: - return "RET" - case JMP: - return "JMP" - case NOP: - return "NOP" - case UD2: - return "UD2" - case MOVDQU: - return "MOVDQU" - case PINSRB: - return "PINSRB" - case PINSRW: - return "PINSRW" - case PINSRD: - return "PINSRD" - case PINSRQ: - return "PINSRQ" - case PADDB: - return "PADDB" - case PADDW: - return "PADDW" - case PADDD: - return "PADDD" - case PADDQ: - return "PADDQ" - case ADDPS: - return "ADDPS" - case ADDPD: - return "ADDPD" - case PSUBB: - return "PSUBB" - case PSUBW: - return "PSUBW" - case PSUBD: - return "PSUBD" - case PSUBQ: - return "PSUBQ" - case SUBPS: - return "SUBPS" - case SUBPD: - return "SUBPD" - case PMOVSXBW: - return "PMOVSXBW" - case PMOVSXWD: - return "PMOVSXWD" - case PMOVSXDQ: - return "PMOVSXDQ" - case PMOVZXBW: - return "PMOVZXBW" - case PMOVZXWD: - return "PMOVZXWD" - case PMOVZXDQ: - return "PMOVZXDQ" - case PSHUFB: - return "PSHUFB" - case PSHUFD: - return "PSHUFD" - case PXOR: - return "PXOR" - case PEXTRB: - return "PEXTRB" - case PEXTRW: - return "PEXTRW" - case PEXTRD: - return "PEXTRD" - case PEXTRQ: - return "PEXTRQ" - case INSERTPS: - return "INSERTPS" - case MOVLHPS: - return "MOVLHPS" - case PTEST: - return "PTEST" - case PCMPEQB: - return "PCMPEQB" - case PCMPEQW: - return "PCMPEQW" - case PCMPEQD: - return "PCMPEQD" - case PCMPEQQ: - return "PCMPEQQ" - case PADDUSB: - return "PADDUSB" - case MOVDQA: - return "MOVDQA" - case MOVSD: - return "MOVSD" - case PACKSSWB: - return "PACKSSWB" - case PMOVMSKB: - return "PMOVMSKB" - case MOVMSKPS: - return "MOVMSKPS" - case MOVMSKPD: - return "MOVMSKPD" - case PAND: - return "PAND" - case POR: - return "POR" - case PANDN: - return "PANDN" - case PSRAD: - return "PSRAD" - case PSRAW: - return "PSRAW" - case PSRLW: - return "PSRLW" - case PSLLW: - return "PSLLW" - case PUNPCKLBW: - return "PUNPCKLBW" - case PUNPCKHBW: - return "PUNPCKHBW" - case NEGQ: - return "NEGQ" - case NEGL: - return "NEGL" - case NEGW: - return "NEGW" - case NEGB: - return "NEGB" - case NONE: - return "NONE" - case CMPPS: - return "CMPPS" - case CMPPD: - return "CMPPD" - case PCMPGTQ: - return "PCMPGTQ" - case PCMPGTD: - return "PCMPGTD" - case PMINSD: - return "PMINSD" - case PMAXSD: - return "PMAXSD" - case PMINSW: - return "PMINSW" - case PCMPGTB: - return "PCMPGTB" - case PMINSB: - return "PMINSB" - case PMINUD: - return "PMINUD" - case PMINUW: - return "PMINUW" - case PMINUB: - return "PMINUB" - case PMAXUD: - return "PMAXUD" - case PMAXUW: - return "PMAXUW" - case PMAXUB: - return "PMAXUB" - case PCMPGTW: - return "PCMPGTW" - case PMAXSW: - return "PMAXSW" - case PMAXSB: - return "PMAXSB" - case PMULLW: - return "PMULLW" - case PMULLD: - return "PMULLD" - case PMULUDQ: - return "PMULUDQ" - case PSUBSB: - return "PSUBSB" - case PSUBUSB: - return "PSUBUSB" - case PADDSW: - return "PADDSW" - case PADDSB: - return "PADDSB" - case PADDUSW: - return "PADDUSW" - case PSUBSW: - return "PSUBSW" - case PSUBUSW: - return "PSUBUSW" - case PAVGB: - return "PAVGB" - case PAVGW: - return "PAVGW" - case PABSB: - return "PABSB" - case PABSW: - return "PABSW" - case PABSD: - return "PABSD" - case BLENDVPD: - return "BLENDVPD" - case MAXPD: - return "MAXPD" - case MAXPS: - return "MAXPS" - case MINPD: - return "MINPD" - case MINPS: - return "MINPS" - case ANDNPD: - return "ANDNPD" - case ANDNPS: - return "ANDNPS" - case MULPS: - return "MULPS" - case MULPD: - return "MULPD" - case DIVPS: - return "DIVPS" - case DIVPD: - return "DIVPD" - case SQRTPS: - return "SQRTPS" - case SQRTPD: - return "SQRTPD" - case ROUNDPS: - return "ROUNDPS" - case ROUNDPD: - return "ROUNDPD" - case PALIGNR: - return "PALIGNR" - case PUNPCKLWD: - return "PUNPCKLWD" - case PUNPCKHWD: - return "PUNPCKHWD" - case PMULHUW: - return "PMULHUW" - case PMULDQ: - return "PMULDQ" - case PMULHRSW: - return "PMULHRSW" - case PMULHW: - return "PMULHW" - case CMPEQPS: - return "CMPEQPS" - case CMPEQPD: - return "CMPEQPD" - case CVTTPS2DQ: - return "CVTTPS2DQ" - case CVTDQ2PS: - return "CVTDQ2PS" - case MOVUPD: - return "MOVUPD" - case SHUFPS: - return "SHUFPS" - case PMADDWD: - return "PMADDWD" - case CVTDQ2PD: - return "CVTDQ2PD" - case UNPCKLPS: - return "UNPCKLPS" - case PACKUSWB: - return "PACKUSWB" - case PACKSSDW: - return "PACKSSDW" - case PACKUSDW: - return "PACKUSDW" - case CVTPS2PD: - return "CVTPS2PD" - case CVTPD2PS: - return "CVTPD2PS" - case PMADDUBSW: - return "PMADDUBSW" - case CVTTPD2DQ: - return "CVTTPD2DQ" - case XADDW: - return "XADDW" - case XADDQ: - return "XADDQ" - case XADDL: - return "XADDL" - case XADDB: - return "XADDB" - case MFENCE: - return "MFENCE" - } - panic(fmt.Errorf("unknown instruction %d", instruction)) -} - -// Amd64-specific registers. -// -// Note: naming convention intentionally matches the Go assembler: https://go.dev/doc/asm -// See https://www.lri.fr/~filliatr/ens/compil/x86-64.pdf -// See https://cs.brown.edu/courses/cs033/docs/guides/x64_cheatsheet.pdf -const ( - // RegAX is the ax register - RegAX = asm.NilRegister + 1 + iota - // RegCX is the cx register - RegCX - // RegDX is the dx register - RegDX - // RegBX is the bx register - RegBX - // RegSP is the sp register - RegSP - // RegBP is the bp register - RegBP - // RegSI is the si register - RegSI - // RegDI is the di register - RegDI - // RegR8 is the r8 register - RegR8 - // RegR9 is the r9 register - RegR9 - // RegR10 is the r10 register - RegR10 - // RegR11 is the r11 register - RegR11 - // RegR12 is the r12 register - RegR12 - // RegR13 is the r13 register - RegR13 - // RegR14 is the r14 register - RegR14 - // RegR15 is the r15 register - RegR15 - // RegX0 is the x0 register - RegX0 - // RegX1 is the x1 register - RegX1 - // RegX2 is the x2 register - RegX2 - // RegX3 is the x3 register - RegX3 - // RegX4 is the x4 register - RegX4 - // RegX5 is the x5 register - RegX5 - // RegX6 is the x6 register - RegX6 - // RegX7 is the x7 register - RegX7 - // RegX8 is the x8 register - RegX8 - // RegX9 is the x9 register - RegX9 - // RegX10 is the x10 register - RegX10 - // RegX11 is the x11 register - RegX11 - // RegX12 is the x12 register - RegX12 - // RegX13 is the x13 register - RegX13 - // RegX14 is the x14 register - RegX14 - // RegX15 is the x15 register - RegX15 -) - -// RegisterName returns the name for a register -func RegisterName(reg asm.Register) string { - switch reg { - case RegAX: - return "AX" - case RegCX: - return "CX" - case RegDX: - return "DX" - case RegBX: - return "BX" - case RegSP: - return "SP" - case RegBP: - return "BP" - case RegSI: - return "SI" - case RegDI: - return "DI" - case RegR8: - return "R8" - case RegR9: - return "R9" - case RegR10: - return "R10" - case RegR11: - return "R11" - case RegR12: - return "R12" - case RegR13: - return "R13" - case RegR14: - return "R14" - case RegR15: - return "R15" - case RegX0: - return "X0" - case RegX1: - return "X1" - case RegX2: - return "X2" - case RegX3: - return "X3" - case RegX4: - return "X4" - case RegX5: - return "X5" - case RegX6: - return "X6" - case RegX7: - return "X7" - case RegX8: - return "X8" - case RegX9: - return "X9" - case RegX10: - return "X10" - case RegX11: - return "X11" - case RegX12: - return "X12" - case RegX13: - return "X13" - case RegX14: - return "X14" - case RegX15: - return "X15" - default: - return "nil" - } -} diff --git a/internal/asm/amd64/consts_test.go b/internal/asm/amd64/consts_test.go deleted file mode 100644 index 6d9964b3f3..0000000000 --- a/internal/asm/amd64/consts_test.go +++ /dev/null @@ -1,15 +0,0 @@ -package amd64 - -import ( - "testing" - - "github.com/tetratelabs/wazero/internal/asm" - "github.com/tetratelabs/wazero/internal/testing/require" -) - -// TestInstructionName ensures that all the instruction's name is defined. -func TestInstructionName(t *testing.T) { - for inst := asm.Instruction(0); inst < instructionEnd; inst++ { - require.NotEqual(t, "", InstructionName(inst)) - } -} diff --git a/internal/asm/amd64/impl.go b/internal/asm/amd64/impl.go deleted file mode 100644 index 1dec696a1c..0000000000 --- a/internal/asm/amd64/impl.go +++ /dev/null @@ -1,2928 +0,0 @@ -package amd64 - -import ( - "encoding/binary" - "errors" - "fmt" - "math" - - "github.com/tetratelabs/wazero/internal/asm" -) - -// nodeImpl implements asm.Node for amd64. -type nodeImpl struct { - // jumpTarget holds the target node in the linked for the jump-kind instruction. - jumpTarget *nodeImpl - - // prev and next hold the prev/next node from this node in the assembled linked list. - prev, next *nodeImpl - - // forwardJumpOrigins hold all the nodes trying to jump into this node as a - // singly linked list. In other words, all the nodes with .jumpTarget == this. - forwardJumpOrigins *nodeImpl - - staticConst *asm.StaticConst - - dstConst asm.ConstantValue - offsetInBinary asm.NodeOffsetInBinary - srcConst asm.ConstantValue - instruction asm.Instruction - - // readInstructionAddressBeforeTargetInstruction holds the instruction right before the target of - // read instruction address instruction. See asm.assemblerBase.CompileReadInstructionAddress. - readInstructionAddressBeforeTargetInstruction asm.Instruction - flag nodeFlag - types operandTypes - srcReg, dstReg asm.Register - srcMemIndex, dstMemIndex asm.Register - srcMemScale, dstMemScale byte - arg byte - - // staticConstReferrersAdded true if this node is already added into AssemblerImpl.staticConstReferrers. - // Only used when staticConst is not nil. Through re-assembly, we might end up adding multiple times which causes unnecessary - // allocations, so we use this flag to do it once. - staticConstReferrersAdded bool -} - -type nodeFlag byte - -const ( - // nodeFlagInitializedForEncoding is always set to indicate that node is already initialized. Notably, this is used to judge - // whether a jump is backward or forward before encoding. - nodeFlagInitializedForEncoding nodeFlag = 1 << iota - nodeFlagBackwardJump - // nodeFlagShortForwardJump is set to false by default and only used by forward branch jumps, which means .jumpTarget != nil and - // the target node is encoded after this node. False by default means that we Encode all the jumps with jumpTarget - // as short jump (i.e. relative signed 8-bit integer offset jump) and try to Encode as small as possible. - nodeFlagShortForwardJump - // nodeFlagLock indicates the encoded instruction should include the LOCK prefix - nodeFlagLock -) - -func (n *nodeImpl) isInitializedForEncoding() bool { - return n.flag&nodeFlagInitializedForEncoding != 0 -} - -func (n *nodeImpl) isJumpNode() bool { - return n.jumpTarget != nil -} - -func (n *nodeImpl) isBackwardJump() bool { - return n.isJumpNode() && (n.flag&nodeFlagBackwardJump != 0) -} - -func (n *nodeImpl) isForwardJump() bool { - return n.isJumpNode() && (n.flag&nodeFlagBackwardJump == 0) -} - -func (n *nodeImpl) isForwardShortJump() bool { - return n.isForwardJump() && n.flag&nodeFlagShortForwardJump != 0 -} - -func (n *nodeImpl) isLock() bool { - return n.flag&nodeFlagLock != 0 -} - -// AssignJumpTarget implements asm.Node.AssignJumpTarget. -func (n *nodeImpl) AssignJumpTarget(target asm.Node) { - n.jumpTarget = target.(*nodeImpl) -} - -// AssignDestinationConstant implements asm.Node.AssignDestinationConstant. -func (n *nodeImpl) AssignDestinationConstant(value asm.ConstantValue) { - n.dstConst = value -} - -// AssignSourceConstant implements asm.Node.AssignSourceConstant. -func (n *nodeImpl) AssignSourceConstant(value asm.ConstantValue) { - n.srcConst = value -} - -// OffsetInBinary implements asm.Node.OffsetInBinary. -func (n *nodeImpl) OffsetInBinary() asm.NodeOffsetInBinary { - return n.offsetInBinary -} - -// String implements fmt.Stringer. -// -// This is for debugging purpose, and the format is almost same as the AT&T assembly syntax, -// meaning that this should look like "INSTRUCTION ${from}, ${to}" where each operand -// might be embraced by '[]' to represent the memory location. -func (n *nodeImpl) String() (ret string) { - instName := InstructionName(n.instruction) - switch n.types { - case operandTypesNoneToNone: - ret = instName - case operandTypesNoneToRegister: - ret = fmt.Sprintf("%s %s", instName, RegisterName(n.dstReg)) - case operandTypesNoneToMemory: - if n.dstMemIndex != asm.NilRegister { - ret = fmt.Sprintf("%s [%s + 0x%x + %s*0x%x]", instName, - RegisterName(n.dstReg), n.dstConst, RegisterName(n.dstMemIndex), n.dstMemScale) - } else { - ret = fmt.Sprintf("%s [%s + 0x%x]", instName, RegisterName(n.dstReg), n.dstConst) - } - case operandTypesNoneToBranch: - ret = fmt.Sprintf("%s {%v}", instName, n.jumpTarget) - case operandTypesRegisterToNone: - ret = fmt.Sprintf("%s %s", instName, RegisterName(n.srcReg)) - case operandTypesRegisterToRegister: - ret = fmt.Sprintf("%s %s, %s", instName, RegisterName(n.srcReg), RegisterName(n.dstReg)) - case operandTypesRegisterToMemory: - if n.dstMemIndex != asm.NilRegister { - ret = fmt.Sprintf("%s %s, [%s + 0x%x + %s*0x%x]", instName, RegisterName(n.srcReg), - RegisterName(n.dstReg), n.dstConst, RegisterName(n.dstMemIndex), n.dstMemScale) - } else { - ret = fmt.Sprintf("%s %s, [%s + 0x%x]", instName, RegisterName(n.srcReg), RegisterName(n.dstReg), n.dstConst) - } - case operandTypesRegisterToConst: - ret = fmt.Sprintf("%s %s, 0x%x", instName, RegisterName(n.srcReg), n.dstConst) - case operandTypesMemoryToRegister: - if n.srcMemIndex != asm.NilRegister { - ret = fmt.Sprintf("%s [%s + %#x + %s*%#x], %s", instName, - RegisterName(n.srcReg), n.srcConst, RegisterName(n.srcMemIndex), n.srcMemScale, RegisterName(n.dstReg)) - } else { - ret = fmt.Sprintf("%s [%s + 0x%x], %s", instName, RegisterName(n.srcReg), n.srcConst, RegisterName(n.dstReg)) - } - case operandTypesMemoryToConst: - if n.srcMemIndex != asm.NilRegister { - ret = fmt.Sprintf("%s [%s + %#x + %s*0x%x], 0x%x", instName, - RegisterName(n.srcReg), n.srcConst, RegisterName(n.srcMemIndex), n.srcMemScale, n.dstConst) - } else { - ret = fmt.Sprintf("%s [%s + %#x], 0x%x", instName, RegisterName(n.srcReg), n.srcConst, n.dstConst) - } - case operandTypesConstToMemory: - if n.dstMemIndex != asm.NilRegister { - ret = fmt.Sprintf("%s 0x%x, [%s + 0x%x + %s*0x%x]", instName, n.srcConst, - RegisterName(n.dstReg), n.dstConst, RegisterName(n.dstMemIndex), n.dstMemScale) - } else { - ret = fmt.Sprintf("%s 0x%x, [%s + 0x%x]", instName, n.srcConst, RegisterName(n.dstReg), n.dstConst) - } - case operandTypesConstToRegister: - ret = fmt.Sprintf("%s 0x%x, %s", instName, n.srcConst, RegisterName(n.dstReg)) - case operandTypesStaticConstToRegister: - ret = fmt.Sprintf("%s $%#x, %s", instName, n.staticConst.Raw, RegisterName(n.dstReg)) - case operandTypesRegisterToStaticConst: - ret = fmt.Sprintf("%s %s, $%#x", instName, RegisterName(n.srcReg), n.staticConst.Raw) - } - return -} - -type operandTypes byte - -const ( - operandTypesNoneToNone operandTypes = iota - operandTypesNoneToRegister - operandTypesNoneToMemory - operandTypesNoneToBranch - operandTypesRegisterToNone - operandTypesRegisterToRegister - operandTypesRegisterToMemory - operandTypesRegisterToConst - operandTypesMemoryToRegister - operandTypesMemoryToConst - operandTypesConstToRegister - operandTypesConstToMemory - operandTypesStaticConstToRegister - operandTypesRegisterToStaticConst -) - -// String implements fmt.Stringer -func (o operandTypes) String() (ret string) { - switch o { - case operandTypesNoneToNone: - ret = "NoneToNone" - case operandTypesNoneToRegister: - ret = "NoneToRegister" - case operandTypesNoneToMemory: - ret = "NoneToMemory" - case operandTypesNoneToBranch: - ret = "NoneToBranch" - case operandTypesRegisterToNone: - ret = "RegisterToNone" - case operandTypesRegisterToRegister: - ret = "RegisterToRegister" - case operandTypesRegisterToMemory: - ret = "RegisterToMemory" - case operandTypesRegisterToConst: - ret = "RegisterToConst" - case operandTypesMemoryToRegister: - ret = "MemoryToRegister" - case operandTypesMemoryToConst: - ret = "MemoryToConst" - case operandTypesConstToRegister: - ret = "ConstToRegister" - case operandTypesConstToMemory: - ret = "ConstToMemory" - case operandTypesStaticConstToRegister: - ret = "StaticConstToRegister" - case operandTypesRegisterToStaticConst: - ret = "RegisterToStaticConst" - } - return -} - -type ( - // AssemblerImpl implements Assembler. - AssemblerImpl struct { - root *nodeImpl - current *nodeImpl - asm.BaseAssemblerImpl - readInstructionAddressNodes []*nodeImpl - - // staticConstReferrers maintains the list of static const referrers which requires the - // offset resolution after finalizing the binary layout. - staticConstReferrers []staticConstReferrer - - nodePool nodePool - pool asm.StaticConstPool - - // MaxDisplacementForConstantPool is fixed to defaultMaxDisplacementForConstantPool - // but have it as an exported field here for testability. - MaxDisplacementForConstantPool int - - forceReAssemble bool - } - - // staticConstReferrer represents a referrer of a asm.StaticConst. - staticConstReferrer struct { - n *nodeImpl - // instLen is the encoded length of the instruction for `n`. - instLen int - } -) - -func NewAssembler() *AssemblerImpl { - return &AssemblerImpl{ - nodePool: nodePool{index: nodePageSize}, - pool: asm.NewStaticConstPool(), - MaxDisplacementForConstantPool: defaultMaxDisplacementForConstantPool, - } -} - -const nodePageSize = 128 - -type nodePage = [nodePageSize]nodeImpl - -// nodePool is the central allocation pool for nodeImpl used by a single AssemblerImpl. -// This reduces the allocations over compilation by reusing AssemblerImpl. -type nodePool struct { - pages []*nodePage - index int -} - -// allocNode allocates a new nodeImpl for use from the pool. -// This expands the pool if there is no space left for it. -func (n *nodePool) allocNode() *nodeImpl { - if n.index == nodePageSize { - if len(n.pages) == cap(n.pages) { - n.pages = append(n.pages, new(nodePage)) - } else { - i := len(n.pages) - n.pages = n.pages[:i+1] - if n.pages[i] == nil { - n.pages[i] = new(nodePage) - } - } - n.index = 0 - } - ret := &n.pages[len(n.pages)-1][n.index] - n.index++ - return ret -} - -func (n *nodePool) reset() { - for _, ns := range n.pages { - pages := ns[:] - for i := range pages { - pages[i] = nodeImpl{} - } - } - n.pages = n.pages[:0] - n.index = nodePageSize -} - -// AllocateNOP implements asm.AssemblerBase. -func (a *AssemblerImpl) AllocateNOP() asm.Node { - n := a.nodePool.allocNode() - n.instruction = NOP - n.types = operandTypesNoneToNone - return n -} - -// Add implements asm.AssemblerBase. -func (a *AssemblerImpl) Add(n asm.Node) { - a.addNode(n.(*nodeImpl)) -} - -// Reset implements asm.AssemblerBase. -func (a *AssemblerImpl) Reset() { - pool := a.pool - pool.Reset() - *a = AssemblerImpl{ - nodePool: a.nodePool, - pool: pool, - readInstructionAddressNodes: a.readInstructionAddressNodes[:0], - staticConstReferrers: a.staticConstReferrers[:0], - BaseAssemblerImpl: asm.BaseAssemblerImpl{ - SetBranchTargetOnNextNodes: a.SetBranchTargetOnNextNodes[:0], - JumpTableEntries: a.JumpTableEntries[:0], - }, - } - a.nodePool.reset() -} - -// newNode creates a new Node and appends it into the linked list. -func (a *AssemblerImpl) newNode(instruction asm.Instruction, types operandTypes) *nodeImpl { - n := a.nodePool.allocNode() - n.instruction = instruction - n.types = types - a.addNode(n) - return n -} - -// addNode appends the new node into the linked list. -func (a *AssemblerImpl) addNode(node *nodeImpl) { - if a.root == nil { - a.root = node - a.current = node - } else { - parent := a.current - parent.next = node - node.prev = parent - a.current = node - } - - for _, o := range a.SetBranchTargetOnNextNodes { - origin := o.(*nodeImpl) - origin.jumpTarget = node - } - // Reuse the underlying slice to avoid re-allocations. - a.SetBranchTargetOnNextNodes = a.SetBranchTargetOnNextNodes[:0] -} - -// encodeNode encodes the given node into writer. -func (a *AssemblerImpl) encodeNode(buf asm.Buffer, n *nodeImpl) (err error) { - switch n.types { - case operandTypesNoneToNone: - err = a.encodeNoneToNone(buf, n) - case operandTypesNoneToRegister: - err = a.encodeNoneToRegister(buf, n) - case operandTypesNoneToMemory: - err = a.encodeNoneToMemory(buf, n) - case operandTypesNoneToBranch: - // Branching operand can be encoded as relative jumps. - err = a.encodeRelativeJump(buf, n) - case operandTypesRegisterToNone: - err = a.encodeRegisterToNone(buf, n) - case operandTypesRegisterToRegister: - err = a.encodeRegisterToRegister(buf, n) - case operandTypesRegisterToMemory: - err = a.encodeRegisterToMemory(buf, n) - case operandTypesRegisterToConst: - err = a.encodeRegisterToConst(buf, n) - case operandTypesMemoryToRegister: - err = a.encodeMemoryToRegister(buf, n) - case operandTypesMemoryToConst: - err = a.encodeMemoryToConst(buf, n) - case operandTypesConstToRegister: - err = a.encodeConstToRegister(buf, n) - case operandTypesConstToMemory: - err = a.encodeConstToMemory(buf, n) - case operandTypesStaticConstToRegister: - err = a.encodeStaticConstToRegister(buf, n) - case operandTypesRegisterToStaticConst: - err = a.encodeRegisterToStaticConst(buf, n) - default: - err = fmt.Errorf("encoder undefined for [%s] operand type", n.types) - } - if err != nil { - err = fmt.Errorf("%w: %s", err, n) // Ensure the error is debuggable by including the string value of the node. - } - return -} - -// Assemble implements asm.AssemblerBase -func (a *AssemblerImpl) Assemble(buf asm.Buffer) error { - a.initializeNodesForEncoding() - - // Continue encoding until we are not forced to re-assemble which happens when - // a short relative jump ends up the offset larger than 8-bit length. - for { - err := a.encode(buf) - if err != nil { - return err - } - - if !a.forceReAssemble { - break - } else { - // We reset the length of buffer but don't delete the underlying slice since - // the binary size will roughly the same after reassemble. - buf.Reset() - // Reset the re-assemble flag in order to avoid the infinite loop! - a.forceReAssemble = false - } - } - - code := buf.Bytes() - for _, n := range a.readInstructionAddressNodes { - if err := a.finalizeReadInstructionAddressNode(code, n); err != nil { - return err - } - } - - // Now that we've finished the layout, fill out static consts offsets. - for i := range a.staticConstReferrers { - ref := &a.staticConstReferrers[i] - n, instLen := ref.n, ref.instLen - // Calculate the displacement between the RIP (the offset _after_ n) and the static constant. - displacement := int(n.staticConst.OffsetInBinary) - int(n.OffsetInBinary()) - instLen - // The offset must be stored at the 4 bytes from the tail of this n. See AssemblerImpl.encodeStaticConstImpl for detail. - displacementOffsetInInstruction := n.OffsetInBinary() + uint64(instLen-4) - binary.LittleEndian.PutUint32(code[displacementOffsetInInstruction:], uint32(int32(displacement))) - } - - return a.FinalizeJumpTableEntry(code) -} - -// initializeNodesForEncoding initializes nodeImpl.flag and determine all the jumps -// are forward or backward jump. -func (a *AssemblerImpl) initializeNodesForEncoding() { - for n := a.root; n != nil; n = n.next { - n.flag |= nodeFlagInitializedForEncoding - if target := n.jumpTarget; target != nil { - if target.isInitializedForEncoding() { - // This means the target exists behind. - n.flag |= nodeFlagBackwardJump - } else { - // Otherwise, this is forward jump. - // We start with assuming that the jump can be short (8-bit displacement). - // If it doens't fit, we change this flag in resolveRelativeForwardJump. - n.flag |= nodeFlagShortForwardJump - - // If the target node is also the branching instruction, we replace the target with the NOP - // node so that we can avoid the collision of the target.forwardJumpOrigins both as destination and origins. - if target.types == operandTypesNoneToBranch { - // Allocate the NOP node from the pool. - nop := a.nodePool.allocNode() - nop.instruction = NOP - nop.types = operandTypesNoneToNone - // Insert it between target.prev and target: [target.prev, target] -> [target.prev, nop, target] - prev := target.prev - nop.prev = prev - prev.next = nop - nop.next = target - target.prev = nop - n.jumpTarget = nop - target = nop - } - - // We add this node `n` into the end of the linked list (.forwardJumpOrigins) beginning from the `target.forwardJumpOrigins`. - // Insert the current `n` as the head of the list. - n.forwardJumpOrigins = target.forwardJumpOrigins - target.forwardJumpOrigins = n - } - } - } -} - -func (a *AssemblerImpl) encode(buf asm.Buffer) error { - for n := a.root; n != nil; n = n.next { - // If an instruction needs NOP padding, we do so before encoding it. - // - // This is necessary to avoid Intel's jump erratum; see in Section 2.1 - // in for when we have to pad NOP: - // https://www.intel.com/content/dam/support/us/en/documents/processors/mitigations-jump-conditional-code-erratum.pdf - // - // This logic used to be implemented in a function called maybeNOPPadding, - // but the complexity of the logic made it impossible for the compiler to - // inline. Since this function is on a hot code path, we inlined the - // initial checks to skip the function call when instructions do not need - // NOP padding. - switch info := nopPaddingInfo[n.instruction]; { - case info.jmp: - if err := a.encodeJmpNOPPadding(buf, n); err != nil { - return err - } - case info.onNextJmp: - if err := a.encodeOnNextJmpNOPPAdding(buf, n); err != nil { - return err - } - } - - // After the padding, we can finalize the offset of this instruction in the binary. - n.offsetInBinary = uint64(buf.Len()) - - if err := a.encodeNode(buf, n); err != nil { - return err - } - - if n.forwardJumpOrigins != nil { - if err := a.resolveForwardRelativeJumps(buf, n); err != nil { - return fmt.Errorf("invalid relative forward jumps: %w", err) - } - } - - a.maybeFlushConstants(buf, n.next == nil) - } - return nil -} - -var nopPaddingInfo = [instructionEnd]struct { - jmp, onNextJmp bool -}{ - RET: {jmp: true}, - JMP: {jmp: true}, - JCC: {jmp: true}, - JCS: {jmp: true}, - JEQ: {jmp: true}, - JGE: {jmp: true}, - JGT: {jmp: true}, - JHI: {jmp: true}, - JLE: {jmp: true}, - JLS: {jmp: true}, - JLT: {jmp: true}, - JMI: {jmp: true}, - JNE: {jmp: true}, - JPC: {jmp: true}, - JPS: {jmp: true}, - // The possible fused jump instructions if the next node is a conditional jump instruction. - CMPL: {onNextJmp: true}, - CMPQ: {onNextJmp: true}, - TESTL: {onNextJmp: true}, - TESTQ: {onNextJmp: true}, - ADDL: {onNextJmp: true}, - ADDQ: {onNextJmp: true}, - SUBL: {onNextJmp: true}, - SUBQ: {onNextJmp: true}, - ANDL: {onNextJmp: true}, - ANDQ: {onNextJmp: true}, - INCQ: {onNextJmp: true}, - DECQ: {onNextJmp: true}, -} - -func (a *AssemblerImpl) encodeJmpNOPPadding(buf asm.Buffer, n *nodeImpl) error { - // In order to know the instruction length before writing into the binary, - // we try encoding it. - prevLen := buf.Len() - - // Assign the temporary offset which may or may not be correct depending on the padding decision. - n.offsetInBinary = uint64(prevLen) - - // Encode the node and get the instruction length. - if err := a.encodeNode(buf, n); err != nil { - return err - } - instructionLen := int32(buf.Len() - prevLen) - - // Revert the written bytes. - buf.Truncate(prevLen) - return a.encodeNOPPadding(buf, instructionLen) -} - -func (a *AssemblerImpl) encodeOnNextJmpNOPPAdding(buf asm.Buffer, n *nodeImpl) error { - instructionLen, err := a.fusedInstructionLength(buf, n) - if err != nil { - return err - } - return a.encodeNOPPadding(buf, instructionLen) -} - -// encodeNOPPadding maybe appends NOP instructions before the node `n`. -// This is necessary to avoid Intel's jump erratum: -// https://www.intel.com/content/dam/support/us/en/documents/processors/mitigations-jump-conditional-code-erratum.pdf -func (a *AssemblerImpl) encodeNOPPadding(buf asm.Buffer, instructionLen int32) error { - const boundaryInBytes int32 = 32 - const mask = boundaryInBytes - 1 - var padNum int - currentPos := int32(buf.Len()) - if used := currentPos & mask; used+instructionLen >= boundaryInBytes { - padNum = int(boundaryInBytes - used) - } - a.padNOP(buf, padNum) - return nil -} - -// fusedInstructionLength returns the length of "macro fused instruction" if the -// instruction sequence starting from `n` can be fused by processor. Otherwise, -// returns zero. -func (a *AssemblerImpl) fusedInstructionLength(buf asm.Buffer, n *nodeImpl) (ret int32, err error) { - // Find the next non-NOP instruction. - next := n.next - for ; next != nil && next.instruction == NOP; next = next.next { - } - - if next == nil { - return - } - - inst, jmpInst := n.instruction, next.instruction - - if !nopPaddingInfo[jmpInst].jmp { - // If the next instruction is not jump kind, the instruction will not be fused. - return - } - - // How to determine whether the instruction can be fused is described in - // Section 3.4.2.2 of "Intel Optimization Manual": - // https://www.intel.com/content/dam/doc/manual/64-ia-32-architectures-optimization-manual.pdf - isTest := inst == TESTL || inst == TESTQ - isCmp := inst == CMPQ || inst == CMPL - isTestCmp := isTest || isCmp - if isTestCmp && (n.types == operandTypesMemoryToConst || n.types == operandTypesConstToMemory) { - // The manual says: "CMP and TEST can not be fused when comparing MEM-IMM". - return - } - - // Implement the decision according to the table 3-1 in the manual. - isAnd := inst == ANDL || inst == ANDQ - if !isTest && !isAnd { - if jmpInst == JMI || jmpInst == JPL || jmpInst == JPS || jmpInst == JPC { - // These jumps are only fused for TEST or AND. - return - } - isAdd := inst == ADDL || inst == ADDQ - isSub := inst == SUBL || inst == SUBQ - if !isCmp && !isAdd && !isSub { - if jmpInst == JCS || jmpInst == JCC || jmpInst == JHI || jmpInst == JLS { - // Thses jumpst are only fused for TEST, AND, CMP, ADD, or SUB. - return - } - } - } - - // Now the instruction is ensured to be fused by the processor. - // In order to know the fused instruction length before writing into the binary, - // we try encoding it. - savedLen := uint64(buf.Len()) - - // Encode the nodes into the buffer. - if err = a.encodeNode(buf, n); err != nil { - return - } - if err = a.encodeNode(buf, next); err != nil { - return - } - - ret = int32(uint64(buf.Len()) - savedLen) - - // Revert the written bytes. - buf.Truncate(int(savedLen)) - return -} - -// nopOpcodes is the multi byte NOP instructions table derived from section 5.8 "Code Padding with Operand-Size Override and Multibyte NOP" -// in "AMD Software Optimization Guide for AMD Family 15h Processors" https://www.amd.com/system/files/TechDocs/47414_15h_sw_opt_guide.pdf -var nopOpcodes = [][11]byte{ - {0x90}, - {0x66, 0x90}, - {0x0f, 0x1f, 0x00}, - {0x0f, 0x1f, 0x40, 0x00}, - {0x0f, 0x1f, 0x44, 0x00, 0x00}, - {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00}, - {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00}, - {0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00}, - {0x66, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00}, - {0x66, 0x66, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00}, - {0x66, 0x66, 0x66, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00}, -} - -func (a *AssemblerImpl) padNOP(buf asm.Buffer, num int) { - for num > 0 { - singleNopNum := num - if singleNopNum > len(nopOpcodes) { - singleNopNum = len(nopOpcodes) - } - buf.AppendBytes(nopOpcodes[singleNopNum-1][:singleNopNum]) - num -= singleNopNum - } -} - -// CompileStandAlone implements the same method as documented on asm.AssemblerBase. -func (a *AssemblerImpl) CompileStandAlone(instruction asm.Instruction) asm.Node { - return a.newNode(instruction, operandTypesNoneToNone) -} - -// CompileConstToRegister implements the same method as documented on asm.AssemblerBase. -func (a *AssemblerImpl) CompileConstToRegister( - instruction asm.Instruction, - value asm.ConstantValue, - destinationReg asm.Register, -) (inst asm.Node) { - n := a.newNode(instruction, operandTypesConstToRegister) - n.srcConst = value - n.dstReg = destinationReg - return n -} - -// CompileRegisterToRegister implements the same method as documented on asm.AssemblerBase. -func (a *AssemblerImpl) CompileRegisterToRegister(instruction asm.Instruction, from, to asm.Register) { - n := a.newNode(instruction, operandTypesRegisterToRegister) - n.srcReg = from - n.dstReg = to -} - -// CompileMemoryToRegister implements the same method as documented on asm.AssemblerBase. -func (a *AssemblerImpl) CompileMemoryToRegister( - instruction asm.Instruction, - sourceBaseReg asm.Register, - sourceOffsetConst asm.ConstantValue, - destinationReg asm.Register, -) { - n := a.newNode(instruction, operandTypesMemoryToRegister) - n.srcReg = sourceBaseReg - n.srcConst = sourceOffsetConst - n.dstReg = destinationReg -} - -// CompileRegisterToMemoryWithIndexAndLock implements the same method as documented on asm.AssemblerBase. -func (a *AssemblerImpl) CompileRegisterToMemoryWithIndexAndLock( - instruction asm.Instruction, - srcReg asm.Register, - dstBaseReg asm.Register, - dstOffsetConst int64, - dstIndex asm.Register, - dstScale int16, -) { - n := a.newNode(instruction, operandTypesRegisterToMemory) - n.srcReg = srcReg - n.dstReg = dstBaseReg - n.dstConst = dstOffsetConst - n.dstMemIndex = dstIndex - n.dstMemScale = byte(dstScale) - n.flag |= nodeFlagLock -} - -// CompileRegisterToMemory implements the same method as documented on asm.AssemblerBase. -func (a *AssemblerImpl) CompileRegisterToMemory( - instruction asm.Instruction, - sourceRegister, destinationBaseRegister asm.Register, - destinationOffsetConst asm.ConstantValue, -) { - n := a.newNode(instruction, operandTypesRegisterToMemory) - n.srcReg = sourceRegister - n.dstReg = destinationBaseRegister - n.dstConst = destinationOffsetConst -} - -// CompileJump implements the same method as documented on asm.AssemblerBase. -func (a *AssemblerImpl) CompileJump(jmpInstruction asm.Instruction) asm.Node { - return a.newNode(jmpInstruction, operandTypesNoneToBranch) -} - -// CompileJumpToMemory implements the same method as documented on asm.AssemblerBase. -func (a *AssemblerImpl) CompileJumpToMemory( - jmpInstruction asm.Instruction, - baseReg asm.Register, - offset asm.ConstantValue, -) { - n := a.newNode(jmpInstruction, operandTypesNoneToMemory) - n.dstReg = baseReg - n.dstConst = offset -} - -// CompileJumpToRegister implements the same method as documented on asm.AssemblerBase. -func (a *AssemblerImpl) CompileJumpToRegister(jmpInstruction asm.Instruction, reg asm.Register) { - n := a.newNode(jmpInstruction, operandTypesNoneToRegister) - n.dstReg = reg -} - -// CompileReadInstructionAddress implements the same method as documented on asm.AssemblerBase. -func (a *AssemblerImpl) CompileReadInstructionAddress( - destinationRegister asm.Register, - beforeAcquisitionTargetInstruction asm.Instruction, -) { - n := a.newNode(LEAQ, operandTypesMemoryToRegister) - n.dstReg = destinationRegister - n.readInstructionAddressBeforeTargetInstruction = beforeAcquisitionTargetInstruction -} - -// CompileRegisterToRegisterWithArg implements the same method as documented on amd64.Assembler. -func (a *AssemblerImpl) CompileRegisterToRegisterWithArg( - instruction asm.Instruction, - from, to asm.Register, - arg byte, -) { - n := a.newNode(instruction, operandTypesRegisterToRegister) - n.srcReg = from - n.dstReg = to - n.arg = arg -} - -// CompileMemoryWithIndexToRegister implements the same method as documented on amd64.Assembler. -func (a *AssemblerImpl) CompileMemoryWithIndexToRegister( - instruction asm.Instruction, - srcBaseReg asm.Register, - srcOffsetConst asm.ConstantValue, - srcIndex asm.Register, - srcScale int16, - dstReg asm.Register, -) { - n := a.newNode(instruction, operandTypesMemoryToRegister) - n.srcReg = srcBaseReg - n.srcConst = srcOffsetConst - n.srcMemIndex = srcIndex - n.srcMemScale = byte(srcScale) - n.dstReg = dstReg -} - -// CompileMemoryWithIndexAndArgToRegister implements the same method as documented on amd64.Assembler. -func (a *AssemblerImpl) CompileMemoryWithIndexAndArgToRegister( - instruction asm.Instruction, - srcBaseReg asm.Register, - srcOffsetConst asm.ConstantValue, - srcIndex asm.Register, - srcScale int16, - dstReg asm.Register, - arg byte, -) { - n := a.newNode(instruction, operandTypesMemoryToRegister) - n.srcReg = srcBaseReg - n.srcConst = srcOffsetConst - n.srcMemIndex = srcIndex - n.srcMemScale = byte(srcScale) - n.dstReg = dstReg - n.arg = arg -} - -// CompileRegisterToMemoryWithIndex implements the same method as documented on amd64.Assembler. -func (a *AssemblerImpl) CompileRegisterToMemoryWithIndex( - instruction asm.Instruction, - srcReg, dstBaseReg asm.Register, - dstOffsetConst asm.ConstantValue, - dstIndex asm.Register, - dstScale int16, -) { - n := a.newNode(instruction, operandTypesRegisterToMemory) - n.srcReg = srcReg - n.dstReg = dstBaseReg - n.dstConst = dstOffsetConst - n.dstMemIndex = dstIndex - n.dstMemScale = byte(dstScale) -} - -// CompileRegisterToMemoryWithIndexAndArg implements the same method as documented on amd64.Assembler. -func (a *AssemblerImpl) CompileRegisterToMemoryWithIndexAndArg( - instruction asm.Instruction, - srcReg, dstBaseReg asm.Register, - dstOffsetConst asm.ConstantValue, - dstIndex asm.Register, - dstScale int16, - arg byte, -) { - n := a.newNode(instruction, operandTypesRegisterToMemory) - n.srcReg = srcReg - n.dstReg = dstBaseReg - n.dstConst = dstOffsetConst - n.dstMemIndex = dstIndex - n.dstMemScale = byte(dstScale) - n.arg = arg -} - -// CompileRegisterToConst implements the same method as documented on amd64.Assembler. -func (a *AssemblerImpl) CompileRegisterToConst( - instruction asm.Instruction, - srcRegister asm.Register, - value asm.ConstantValue, -) asm.Node { - n := a.newNode(instruction, operandTypesRegisterToConst) - n.srcReg = srcRegister - n.dstConst = value - return n -} - -// CompileRegisterToNone implements the same method as documented on amd64.Assembler. -func (a *AssemblerImpl) CompileRegisterToNone(instruction asm.Instruction, register asm.Register) { - n := a.newNode(instruction, operandTypesRegisterToNone) - n.srcReg = register -} - -// CompileNoneToRegister implements the same method as documented on amd64.Assembler. -func (a *AssemblerImpl) CompileNoneToRegister(instruction asm.Instruction, register asm.Register) { - n := a.newNode(instruction, operandTypesNoneToRegister) - n.dstReg = register -} - -// CompileNoneToMemory implements the same method as documented on amd64.Assembler. -func (a *AssemblerImpl) CompileNoneToMemory( - instruction asm.Instruction, - baseReg asm.Register, - offset asm.ConstantValue, -) { - n := a.newNode(instruction, operandTypesNoneToMemory) - n.dstReg = baseReg - n.dstConst = offset -} - -// CompileConstToMemory implements the same method as documented on amd64.Assembler. -func (a *AssemblerImpl) CompileConstToMemory( - instruction asm.Instruction, - value asm.ConstantValue, - dstbaseReg asm.Register, - dstOffset asm.ConstantValue, -) asm.Node { - n := a.newNode(instruction, operandTypesConstToMemory) - n.srcConst = value - n.dstReg = dstbaseReg - n.dstConst = dstOffset - return n -} - -// CompileMemoryToConst implements the same method as documented on amd64.Assembler. -func (a *AssemblerImpl) CompileMemoryToConst( - instruction asm.Instruction, - srcBaseReg asm.Register, - srcOffset, value asm.ConstantValue, -) asm.Node { - n := a.newNode(instruction, operandTypesMemoryToConst) - n.srcReg = srcBaseReg - n.srcConst = srcOffset - n.dstConst = value - return n -} - -func errorEncodingUnsupported(n *nodeImpl) error { - return fmt.Errorf("%s is unsupported for %s type", InstructionName(n.instruction), n.types) -} - -func (a *AssemblerImpl) encodeNoneToNone(buf asm.Buffer, n *nodeImpl) (err error) { - // Throughout the encoding methods, we use this pair of base offset and - // code buffer to write instructions. - // - // The code buffer is allocated at the end of the current buffer to a size - // large enough to hold all the bytes that may be written by the method. - // - // We use Go's append builtin to write to the buffer because it allows the - // compiler to generate much better code than if we made calls to write - // methods to mutate an encapsulated byte slice. - // - // At the end of the method, we truncate the buffer size back to the base - // plus the length of the code buffer so the end of the buffer points right - // after the last byte that was written. - base := buf.Len() - code := buf.Append(4)[:0] - - switch n.instruction { - case CDQ: - // https://www.felixcloutier.com/x86/cwd:cdq:cqo - code = append(code, 0x99) - case CQO: - // https://www.felixcloutier.com/x86/cwd:cdq:cqo - code = append(code, rexPrefixW, 0x99) - case NOP: - // Simply optimize out the NOP instructions. - case RET: - // https://www.felixcloutier.com/x86/ret - code = append(code, 0xc3) - case UD2: - // https://mudongliang.github.io/x86/html/file_module_x86_id_318.html - code = append(code, 0x0f, 0x0b) - case REPMOVSQ: - code = append(code, 0xf3, rexPrefixW, 0xa5) - case REPSTOSQ: - code = append(code, 0xf3, rexPrefixW, 0xab) - case STD: - code = append(code, 0xfd) - case CLD: - code = append(code, 0xfc) - case MFENCE: - code = append(code, 0x0f, 0xae, 0xf0) - default: - err = errorEncodingUnsupported(n) - } - - buf.Truncate(base + len(code)) - return -} - -func (a *AssemblerImpl) encodeNoneToRegister(buf asm.Buffer, n *nodeImpl) (err error) { - regBits, prefix := register3bits(n.dstReg, registerSpecifierPositionModRMFieldRM) - - // https://wiki.osdev.org/X86-64_Instruction_Encoding#ModR.2FM - modRM := 0b11_000_000 | // Specifying that opeand is register. - regBits - var mandatoryPrefix byte - switch n.instruction { - case JMP: - // JMP's opcode is defined as "FF /4" meaning that we have to have "4" - // in 4-6th bits in the ModRM byte. https://www.felixcloutier.com/x86/jmp - modRM |= 0b00_100_000 - case NEGQ: - prefix |= rexPrefixW - modRM |= 0b00_011_000 - case NEGL: - modRM |= 0b00_011_000 - case NEGW: - // Note: Need 0x66 to indicate that the operand size is 16-bit. - // https://wiki.osdev.org/X86-64_Instruction_Encoding#Operand-size_and_address-size_override_prefix - mandatoryPrefix = 0x66 - modRM |= 0b00_011_000 - case NEGB: - modRM |= 0b00_011_000 - // 1 byte register operands need default prefix for the following registers. - if n.srcReg >= RegSP && n.srcReg <= RegDI { - prefix |= rexPrefixDefault - } - case INCQ: - prefix |= rexPrefixW - case DECQ: - prefix |= rexPrefixW - modRM |= 0b00_001_000 - default: - if RegSP <= n.dstReg && n.dstReg <= RegDI { - // If the destination is one byte length register, we need to have the default prefix. - // https: //wiki.osdev.org/X86-64_Instruction_Encoding#Registers - prefix |= rexPrefixDefault - } - } - - base := buf.Len() - code := buf.Append(8)[:0] - - if mandatoryPrefix != 0 { - // https://wiki.osdev.org/X86-64_Instruction_Encoding#Mandatory_prefix - code = append(code, mandatoryPrefix) - } - - if prefix != rexPrefixNone { - // https://wiki.osdev.org/X86-64_Instruction_Encoding#Encoding - code = append(code, prefix) - } - - switch n.instruction { - case JMP: - // https://www.felixcloutier.com/x86/jmp - code = append(code, 0xff, modRM) - case SETCC: - // https://www.felixcloutier.com/x86/setcc - code = append(code, 0x0f, 0x93, modRM) - case SETCS: - // https://www.felixcloutier.com/x86/setcc - code = append(code, 0x0f, 0x92, modRM) - case SETEQ: - // https://www.felixcloutier.com/x86/setcc - code = append(code, 0x0f, 0x94, modRM) - case SETGE: - // https://www.felixcloutier.com/x86/setcc - code = append(code, 0x0f, 0x9d, modRM) - case SETGT: - // https://www.felixcloutier.com/x86/setcc - code = append(code, 0x0f, 0x9f, modRM) - case SETHI: - // https://www.felixcloutier.com/x86/setcc - code = append(code, 0x0f, 0x97, modRM) - case SETLE: - // https://www.felixcloutier.com/x86/setcc - code = append(code, 0x0f, 0x9e, modRM) - case SETLS: - // https://www.felixcloutier.com/x86/setcc - code = append(code, 0x0f, 0x96, modRM) - case SETLT: - // https://www.felixcloutier.com/x86/setcc - code = append(code, 0x0f, 0x9c, modRM) - case SETNE: - // https://www.felixcloutier.com/x86/setcc - code = append(code, 0x0f, 0x95, modRM) - case SETPC: - // https://www.felixcloutier.com/x86/setcc - code = append(code, 0x0f, 0x9b, modRM) - case SETPS: - // https://www.felixcloutier.com/x86/setcc - code = append(code, 0x0f, 0x9a, modRM) - case NEGQ, NEGL, NEGW: - // https://www.felixcloutier.com/x86/neg - code = append(code, 0xf7, modRM) - case NEGB: - // https://www.felixcloutier.com/x86/neg - code = append(code, 0xf6, modRM) - case INCQ: - // https://www.felixcloutier.com/x86/inc - code = append(code, 0xff, modRM) - case DECQ: - // https://www.felixcloutier.com/x86/dec - code = append(code, 0xff, modRM) - default: - err = errorEncodingUnsupported(n) - } - - buf.Truncate(base + len(code)) - return -} - -func (a *AssemblerImpl) encodeNoneToMemory(buf asm.Buffer, n *nodeImpl) (err error) { - rexPrefix, modRM, sbi, sbiExist, displacementWidth, err := n.getMemoryLocation(true) - if err != nil { - return err - } - - var opcode byte - switch n.instruction { - case INCQ: - // https://www.felixcloutier.com/x86/inc - rexPrefix |= rexPrefixW - opcode = 0xff - case DECQ: - // https://www.felixcloutier.com/x86/dec - rexPrefix |= rexPrefixW - modRM |= 0b00_001_000 // DEC needs "/1" extension in ModRM. - opcode = 0xff - case JMP: - // https://www.felixcloutier.com/x86/jmp - modRM |= 0b00_100_000 // JMP needs "/4" extension in ModRM. - opcode = 0xff - default: - return errorEncodingUnsupported(n) - } - - base := buf.Len() - code := buf.Append(12)[:0] - - if rexPrefix != rexPrefixNone { - code = append(code, rexPrefix) - } - - code = append(code, opcode, modRM) - - if sbiExist { - code = append(code, sbi) - } - - if displacementWidth != 0 { - code = appendConst(code, n.dstConst, displacementWidth) - } - - buf.Truncate(base + len(code)) - return -} - -type relativeJumpOpcode struct{ short, long []byte } - -func (o relativeJumpOpcode) instructionLen(short bool) int64 { - if short { - return int64(len(o.short)) + 1 // 1 byte = 8 bit offset - } else { - return int64(len(o.long)) + 4 // 4 byte = 32 bit offset - } -} - -var relativeJumpOpcodes = [...]relativeJumpOpcode{ - // https://www.felixcloutier.com/x86/jcc - JCC: {short: []byte{0x73}, long: []byte{0x0f, 0x83}}, - JCS: {short: []byte{0x72}, long: []byte{0x0f, 0x82}}, - JEQ: {short: []byte{0x74}, long: []byte{0x0f, 0x84}}, - JGE: {short: []byte{0x7d}, long: []byte{0x0f, 0x8d}}, - JGT: {short: []byte{0x7f}, long: []byte{0x0f, 0x8f}}, - JHI: {short: []byte{0x77}, long: []byte{0x0f, 0x87}}, - JLE: {short: []byte{0x7e}, long: []byte{0x0f, 0x8e}}, - JLS: {short: []byte{0x76}, long: []byte{0x0f, 0x86}}, - JLT: {short: []byte{0x7c}, long: []byte{0x0f, 0x8c}}, - JMI: {short: []byte{0x78}, long: []byte{0x0f, 0x88}}, - JPL: {short: []byte{0x79}, long: []byte{0x0f, 0x89}}, - JNE: {short: []byte{0x75}, long: []byte{0x0f, 0x85}}, - JPC: {short: []byte{0x7b}, long: []byte{0x0f, 0x8b}}, - JPS: {short: []byte{0x7a}, long: []byte{0x0f, 0x8a}}, - // https://www.felixcloutier.com/x86/jmp - JMP: {short: []byte{0xeb}, long: []byte{0xe9}}, -} - -func (a *AssemblerImpl) resolveForwardRelativeJumps(buf asm.Buffer, target *nodeImpl) (err error) { - offsetInBinary := int64(target.OffsetInBinary()) - origin := target.forwardJumpOrigins - for ; origin != nil; origin = origin.forwardJumpOrigins { - shortJump := origin.isForwardShortJump() - op := relativeJumpOpcodes[origin.instruction] - instructionLen := op.instructionLen(shortJump) - - // Calculate the offset from the EIP (at the time of executing this jump instruction) - // to the target instruction. This value is always >= 0 as here we only handle forward jumps. - offset := offsetInBinary - (int64(origin.OffsetInBinary()) + instructionLen) - if shortJump { - if offset > math.MaxInt8 { - // This forces reassemble in the outer loop inside AssemblerImpl.Assemble(). - a.forceReAssemble = true - // From the next reAssemble phases, this forward jump will be encoded long jump and - // allocate 32-bit offset bytes by default. This means that this `origin` node - // will always enter the "long jump offset encoding" block below - origin.flag ^= nodeFlagShortForwardJump - } else { - buf.Bytes()[origin.OffsetInBinary()+uint64(instructionLen)-1] = byte(offset) - } - } else { // long jump offset encoding. - if offset > math.MaxInt32 { - return fmt.Errorf("too large jump offset %d for encoding %s", offset, InstructionName(origin.instruction)) - } - binary.LittleEndian.PutUint32(buf.Bytes()[origin.OffsetInBinary()+uint64(instructionLen)-4:], uint32(offset)) - } - } - return nil -} - -func (a *AssemblerImpl) encodeRelativeJump(buf asm.Buffer, n *nodeImpl) (err error) { - if n.jumpTarget == nil { - err = fmt.Errorf("jump target must not be nil for relative %s", InstructionName(n.instruction)) - return - } - - op := relativeJumpOpcodes[n.instruction] - var isShortJump bool - // offsetOfEIP means the offset of EIP register at the time of executing this jump instruction. - // Relative jump instructions can be encoded with the signed 8-bit or 32-bit integer offsets from the EIP. - var offsetOfEIP int64 = 0 // We set zero and resolve later once the target instruction is encoded for forward jumps - if n.isBackwardJump() { - // If this is the backward jump, we can calculate the exact offset now. - offsetOfJumpInstruction := int64(n.jumpTarget.OffsetInBinary()) - int64(n.OffsetInBinary()) - isShortJump = offsetOfJumpInstruction-2 >= math.MinInt8 - offsetOfEIP = offsetOfJumpInstruction - op.instructionLen(isShortJump) - } else { - // For forward jumps, we resolve the offset when we Encode the target node. See AssemblerImpl.ResolveForwardRelativeJumps. - isShortJump = n.isForwardShortJump() - } - - if offsetOfEIP < math.MinInt32 { // offsetOfEIP is always <= 0 as we don't calculate it for forward jump here. - return fmt.Errorf("too large jump offset %d for encoding %s", offsetOfEIP, InstructionName(n.instruction)) - } - - base := buf.Len() - code := buf.Append(6)[:0] - - if isShortJump { - code = append(code, op.short...) - code = append(code, byte(offsetOfEIP)) - } else { - code = append(code, op.long...) - code = appendUint32(code, uint32(offsetOfEIP)) - } - - buf.Truncate(base + len(code)) - return -} - -func (a *AssemblerImpl) encodeRegisterToNone(buf asm.Buffer, n *nodeImpl) (err error) { - regBits, prefix := register3bits(n.srcReg, registerSpecifierPositionModRMFieldRM) - - // https://wiki.osdev.org/X86-64_Instruction_Encoding#ModR.2FM - modRM := 0b11_000_000 | // Specifying that opeand is register. - regBits - - var opcode byte - switch n.instruction { - case DIVL: - // https://www.felixcloutier.com/x86/div - modRM |= 0b00_110_000 - opcode = 0xf7 - case DIVQ: - // https://www.felixcloutier.com/x86/div - prefix |= rexPrefixW - modRM |= 0b00_110_000 - opcode = 0xf7 - case IDIVL: - // https://www.felixcloutier.com/x86/idiv - modRM |= 0b00_111_000 - opcode = 0xf7 - case IDIVQ: - // https://www.felixcloutier.com/x86/idiv - prefix |= rexPrefixW - modRM |= 0b00_111_000 - opcode = 0xf7 - case MULL: - // https://www.felixcloutier.com/x86/mul - modRM |= 0b00_100_000 - opcode = 0xf7 - case MULQ: - // https://www.felixcloutier.com/x86/mul - prefix |= rexPrefixW - modRM |= 0b00_100_000 - opcode = 0xf7 - default: - err = errorEncodingUnsupported(n) - } - - base := buf.Len() - code := buf.Append(3)[:0] - - if prefix != rexPrefixNone { - code = append(code, prefix) - } - - code = append(code, opcode, modRM) - - buf.Truncate(base + len(code)) - return -} - -var registerToRegisterOpcode = [instructionEnd]*struct { - opcode []byte - rPrefix rexPrefix - mandatoryPrefix byte - srcOnModRMReg bool - isSrc8bit bool - needArg bool -}{ - // https://www.felixcloutier.com/x86/add - ADDL: {opcode: []byte{0x1}, srcOnModRMReg: true}, - ADDQ: {opcode: []byte{0x1}, rPrefix: rexPrefixW, srcOnModRMReg: true}, - // https://www.felixcloutier.com/x86/and - ANDL: {opcode: []byte{0x21}, srcOnModRMReg: true}, - ANDQ: {opcode: []byte{0x21}, rPrefix: rexPrefixW, srcOnModRMReg: true}, - // https://www.felixcloutier.com/x86/cmp - CMPL: {opcode: []byte{0x39}}, - CMPQ: {opcode: []byte{0x39}, rPrefix: rexPrefixW}, - // https://www.felixcloutier.com/x86/cmovcc - CMOVQCS: {opcode: []byte{0x0f, 0x42}, rPrefix: rexPrefixW}, - // https://www.felixcloutier.com/x86/addsd - ADDSD: {mandatoryPrefix: 0xf2, opcode: []byte{0x0f, 0x58}}, - // https://www.felixcloutier.com/x86/addss - ADDSS: {mandatoryPrefix: 0xf3, opcode: []byte{0x0f, 0x58}}, - // https://www.felixcloutier.com/x86/addpd - ANDPD: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x54}}, - // https://www.felixcloutier.com/x86/addps - ANDPS: {opcode: []byte{0x0f, 0x54}}, - // https://www.felixcloutier.com/x86/bsr - BSRL: {opcode: []byte{0xf, 0xbd}}, - BSRQ: {opcode: []byte{0xf, 0xbd}, rPrefix: rexPrefixW}, - // https://www.felixcloutier.com/x86/comisd - COMISD: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x2f}}, - // https://www.felixcloutier.com/x86/comiss - COMISS: {opcode: []byte{0x0f, 0x2f}}, - // https://www.felixcloutier.com/x86/cvtsd2ss - CVTSD2SS: {mandatoryPrefix: 0xf2, opcode: []byte{0x0f, 0x5a}}, - // https://www.felixcloutier.com/x86/cvtsi2sd - CVTSL2SD: {mandatoryPrefix: 0xf2, opcode: []byte{0x0f, 0x2a}}, - // https://www.felixcloutier.com/x86/cvtsi2sd - CVTSQ2SD: {mandatoryPrefix: 0xf2, opcode: []byte{0x0f, 0x2a}, rPrefix: rexPrefixW}, - // https://www.felixcloutier.com/x86/cvtsi2ss - CVTSL2SS: {mandatoryPrefix: 0xf3, opcode: []byte{0x0f, 0x2a}}, - // https://www.felixcloutier.com/x86/cvtsi2ss - CVTSQ2SS: {mandatoryPrefix: 0xf3, opcode: []byte{0x0f, 0x2a}, rPrefix: rexPrefixW}, - // https://www.felixcloutier.com/x86/cvtss2sd - CVTSS2SD: {mandatoryPrefix: 0xf3, opcode: []byte{0x0f, 0x5a}}, - // https://www.felixcloutier.com/x86/cvttsd2si - CVTTSD2SL: {mandatoryPrefix: 0xf2, opcode: []byte{0x0f, 0x2c}}, - CVTTSD2SQ: {mandatoryPrefix: 0xf2, opcode: []byte{0x0f, 0x2c}, rPrefix: rexPrefixW}, - // https://www.felixcloutier.com/x86/cvttss2si - CVTTSS2SL: {mandatoryPrefix: 0xf3, opcode: []byte{0x0f, 0x2c}}, - CVTTSS2SQ: {mandatoryPrefix: 0xf3, opcode: []byte{0x0f, 0x2c}, rPrefix: rexPrefixW}, - // https://www.felixcloutier.com/x86/divsd - DIVSD: {mandatoryPrefix: 0xf2, opcode: []byte{0x0f, 0x5e}}, - // https://www.felixcloutier.com/x86/divss - DIVSS: {mandatoryPrefix: 0xf3, opcode: []byte{0x0f, 0x5e}}, - // https://www.felixcloutier.com/x86/lzcnt - LZCNTL: {mandatoryPrefix: 0xf3, opcode: []byte{0x0f, 0xbd}}, - LZCNTQ: {mandatoryPrefix: 0xf3, opcode: []byte{0x0f, 0xbd}, rPrefix: rexPrefixW}, - // https://www.felixcloutier.com/x86/maxsd - MAXSD: {mandatoryPrefix: 0xf2, opcode: []byte{0x0f, 0x5f}}, - // https://www.felixcloutier.com/x86/maxss - MAXSS: {mandatoryPrefix: 0xf3, opcode: []byte{0x0f, 0x5f}}, - // https://www.felixcloutier.com/x86/minsd - MINSD: {mandatoryPrefix: 0xf2, opcode: []byte{0x0f, 0x5d}}, - // https://www.felixcloutier.com/x86/minss - MINSS: {mandatoryPrefix: 0xf3, opcode: []byte{0x0f, 0x5d}}, - // https://www.felixcloutier.com/x86/movsx:movsxd - MOVBLSX: {opcode: []byte{0x0f, 0xbe}, isSrc8bit: true}, - // https://www.felixcloutier.com/x86/movzx - MOVBLZX: {opcode: []byte{0x0f, 0xb6}, isSrc8bit: true}, - // https://www.felixcloutier.com/x86/movzx - MOVWLZX: {opcode: []byte{0x0f, 0xb7}, isSrc8bit: true}, - // https://www.felixcloutier.com/x86/movsx:movsxd - MOVBQSX: {opcode: []byte{0x0f, 0xbe}, rPrefix: rexPrefixW, isSrc8bit: true}, - // https://www.felixcloutier.com/x86/movsx:movsxd - MOVLQSX: {opcode: []byte{0x63}, rPrefix: rexPrefixW}, - // https://www.felixcloutier.com/x86/movsx:movsxd - MOVWQSX: {opcode: []byte{0x0f, 0xbf}, rPrefix: rexPrefixW}, - // https://www.felixcloutier.com/x86/movsx:movsxd - MOVWLSX: {opcode: []byte{0x0f, 0xbf}}, - // https://www.felixcloutier.com/x86/imul - IMULQ: {opcode: []byte{0x0f, 0xaf}, rPrefix: rexPrefixW}, - // https://www.felixcloutier.com/x86/mulss - MULSS: {mandatoryPrefix: 0xf3, opcode: []byte{0x0f, 0x59}}, - // https://www.felixcloutier.com/x86/mulsd - MULSD: {mandatoryPrefix: 0xf2, opcode: []byte{0x0f, 0x59}}, - // https://www.felixcloutier.com/x86/or - ORL: {opcode: []byte{0x09}, srcOnModRMReg: true}, - ORQ: {opcode: []byte{0x09}, rPrefix: rexPrefixW, srcOnModRMReg: true}, - // https://www.felixcloutier.com/x86/orpd - ORPD: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x56}}, - // https://www.felixcloutier.com/x86/orps - ORPS: {opcode: []byte{0x0f, 0x56}}, - // https://www.felixcloutier.com/x86/popcnt - POPCNTL: {mandatoryPrefix: 0xf3, opcode: []byte{0x0f, 0xb8}}, - POPCNTQ: {mandatoryPrefix: 0xf3, opcode: []byte{0x0f, 0xb8}, rPrefix: rexPrefixW}, - // https://www.felixcloutier.com/x86/roundss - ROUNDSS: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x3a, 0x0a}, needArg: true}, - // https://www.felixcloutier.com/x86/roundsd - ROUNDSD: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x3a, 0x0b}, needArg: true}, - // https://www.felixcloutier.com/x86/sqrtss - SQRTSS: {mandatoryPrefix: 0xf3, opcode: []byte{0x0f, 0x51}}, - // https://www.felixcloutier.com/x86/sqrtsd - SQRTSD: {mandatoryPrefix: 0xf2, opcode: []byte{0x0f, 0x51}}, - // https://www.felixcloutier.com/x86/sub - SUBL: {opcode: []byte{0x29}, srcOnModRMReg: true}, - SUBQ: {opcode: []byte{0x29}, rPrefix: rexPrefixW, srcOnModRMReg: true}, - // https://www.felixcloutier.com/x86/subss - SUBSS: {mandatoryPrefix: 0xf3, opcode: []byte{0x0f, 0x5c}}, - // https://www.felixcloutier.com/x86/subsd - SUBSD: {mandatoryPrefix: 0xf2, opcode: []byte{0x0f, 0x5c}}, - // https://www.felixcloutier.com/x86/test - TESTL: {opcode: []byte{0x85}, srcOnModRMReg: true}, - TESTQ: {opcode: []byte{0x85}, rPrefix: rexPrefixW, srcOnModRMReg: true}, - // https://www.felixcloutier.com/x86/tzcnt - TZCNTL: {mandatoryPrefix: 0xf3, opcode: []byte{0x0f, 0xbc}}, - TZCNTQ: {mandatoryPrefix: 0xf3, opcode: []byte{0x0f, 0xbc}, rPrefix: rexPrefixW}, - // https://www.felixcloutier.com/x86/ucomisd - UCOMISD: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x2e}}, - // https://www.felixcloutier.com/x86/ucomiss - UCOMISS: {opcode: []byte{0x0f, 0x2e}}, - // https://www.felixcloutier.com/x86/xchg - XCHGQ: {opcode: []byte{0x87}, rPrefix: rexPrefixW, srcOnModRMReg: true}, - // https://www.felixcloutier.com/x86/xor - XORL: {opcode: []byte{0x31}, srcOnModRMReg: true}, - XORQ: {opcode: []byte{0x31}, rPrefix: rexPrefixW, srcOnModRMReg: true}, - // https://www.felixcloutier.com/x86/xorpd - XORPD: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x57}}, - XORPS: {opcode: []byte{0x0f, 0x57}}, - // https://www.felixcloutier.com/x86/pinsrb:pinsrd:pinsrq - PINSRB: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x3a, 0x20}, needArg: true}, - // https://www.felixcloutier.com/x86/pinsrw - PINSRW: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0xc4}, needArg: true}, - // https://www.felixcloutier.com/x86/pinsrb:pinsrd:pinsrq - PINSRD: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x3a, 0x22}, needArg: true}, - // https://www.felixcloutier.com/x86/pinsrb:pinsrd:pinsrq - PINSRQ: {mandatoryPrefix: 0x66, rPrefix: rexPrefixW, opcode: []byte{0x0f, 0x3a, 0x22}, needArg: true}, - // https://www.felixcloutier.com/x86/movdqu:vmovdqu8:vmovdqu16:vmovdqu32:vmovdqu64 - MOVDQU: {mandatoryPrefix: 0xf3, opcode: []byte{0x0f, 0x6f}}, - // https://www.felixcloutier.com/x86/movdqa:vmovdqa32:vmovdqa64 - MOVDQA: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x6f}}, - // https://www.felixcloutier.com/x86/paddb:paddw:paddd:paddq - PADDB: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0xfc}}, - PADDW: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0xfd}}, - PADDD: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0xfe}}, - PADDQ: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0xd4}}, - // https://www.felixcloutier.com/x86/psubb:psubw:psubd - PSUBB: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0xf8}}, - PSUBW: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0xf9}}, - PSUBD: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0xfa}}, - // https://www.felixcloutier.com/x86/psubq - PSUBQ: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0xfb}}, - // https://www.felixcloutier.com/x86/addps - ADDPS: {opcode: []byte{0x0f, 0x58}}, - // https://www.felixcloutier.com/x86/addpd - ADDPD: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x58}}, - // https://www.felixcloutier.com/x86/subps - SUBPS: {opcode: []byte{0x0f, 0x5c}}, - // https://www.felixcloutier.com/x86/subpd - SUBPD: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x5c}}, - // https://www.felixcloutier.com/x86/pxor - PXOR: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0xef}}, - // https://www.felixcloutier.com/x86/pand - PAND: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0xdb}}, - // https://www.felixcloutier.com/x86/por - POR: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0xeb}}, - // https://www.felixcloutier.com/x86/pandn - PANDN: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0xdf}}, - // https://www.felixcloutier.com/x86/pshufb - PSHUFB: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x38, 0x0}}, - // https://www.felixcloutier.com/x86/pshufd - PSHUFD: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x70}, needArg: true}, - // https://www.felixcloutier.com/x86/pextrb:pextrd:pextrq - PEXTRB: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x3a, 0x14}, needArg: true, srcOnModRMReg: true}, - // https://www.felixcloutier.com/x86/pextrw - PEXTRW: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0xc5}, needArg: true}, - // https://www.felixcloutier.com/x86/pextrb:pextrd:pextrq - PEXTRD: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x3a, 0x16}, needArg: true, srcOnModRMReg: true}, - // https://www.felixcloutier.com/x86/pextrb:pextrd:pextrq - PEXTRQ: {rPrefix: rexPrefixW, mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x3a, 0x16}, needArg: true, srcOnModRMReg: true}, - // https://www.felixcloutier.com/x86/insertps - INSERTPS: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x3a, 0x21}, needArg: true}, - // https://www.felixcloutier.com/x86/movlhps - MOVLHPS: {opcode: []byte{0x0f, 0x16}}, - // https://www.felixcloutier.com/x86/ptest - PTEST: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x38, 0x17}}, - // https://www.felixcloutier.com/x86/pcmpeqb:pcmpeqw:pcmpeqd - PCMPEQB: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x74}}, - PCMPEQW: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x75}}, - PCMPEQD: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x76}}, - // https://www.felixcloutier.com/x86/pcmpeqq - PCMPEQQ: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x38, 0x29}}, - // https://www.felixcloutier.com/x86/paddusb:paddusw - PADDUSB: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0xdc}}, - // https://www.felixcloutier.com/x86/movsd - MOVSD: {mandatoryPrefix: 0xf2, opcode: []byte{0x0f, 0x10}}, - // https://www.felixcloutier.com/x86/packsswb:packssdw - PACKSSWB: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x63}}, - // https://www.felixcloutier.com/x86/pmovmskb - PMOVMSKB: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0xd7}}, - // https://www.felixcloutier.com/x86/movmskps - MOVMSKPS: {opcode: []byte{0x0f, 0x50}}, - // https://www.felixcloutier.com/x86/movmskpd - MOVMSKPD: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x50}}, - // https://www.felixcloutier.com/x86/psraw:psrad:psraq - PSRAD: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0xe2}}, - // https://www.felixcloutier.com/x86/psraw:psrad:psraq - PSRAW: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0xe1}}, - // https://www.felixcloutier.com/x86/psrlw:psrld:psrlq - PSRLQ: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0xd3}}, - // https://www.felixcloutier.com/x86/psrlw:psrld:psrlq - PSRLD: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0xd2}}, - // https://www.felixcloutier.com/x86/psrlw:psrld:psrlq - PSRLW: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0xd1}}, - // https://www.felixcloutier.com/x86/psllw:pslld:psllq - PSLLW: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0xf1}}, - // https://www.felixcloutier.com/x86/psllw:pslld:psllq - PSLLD: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0xf2}}, - // https://www.felixcloutier.com/x86/psllw:pslld:psllq - PSLLQ: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0xf3}}, - // https://www.felixcloutier.com/x86/punpcklbw:punpcklwd:punpckldq:punpcklqdq - PUNPCKLBW: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x60}}, - // https://www.felixcloutier.com/x86/punpckhbw:punpckhwd:punpckhdq:punpckhqdq - PUNPCKHBW: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x68}}, - // https://www.felixcloutier.com/x86/cmpps - CMPPS: {opcode: []byte{0x0f, 0xc2}, needArg: true}, - // https://www.felixcloutier.com/x86/cmppd - CMPPD: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0xc2}, needArg: true}, - // https://www.felixcloutier.com/x86/pcmpgtq - PCMPGTQ: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x38, 0x37}}, - // https://www.felixcloutier.com/x86/pcmpgtb:pcmpgtw:pcmpgtd - PCMPGTD: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x66}}, - // https://www.felixcloutier.com/x86/pcmpgtb:pcmpgtw:pcmpgtd - PCMPGTW: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x65}}, - // https://www.felixcloutier.com/x86/pcmpgtb:pcmpgtw:pcmpgtd - PCMPGTB: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x64}}, - // https://www.felixcloutier.com/x86/pminsd:pminsq - PMINSD: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x38, 0x39}}, - // https://www.felixcloutier.com/x86/pmaxsb:pmaxsw:pmaxsd:pmaxsq - PMAXSD: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x38, 0x3d}}, - // https://www.felixcloutier.com/x86/pmaxsb:pmaxsw:pmaxsd:pmaxsq - PMAXSW: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0xee}}, - // https://www.felixcloutier.com/x86/pmaxsb:pmaxsw:pmaxsd:pmaxsq - PMAXSB: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x38, 0x3c}}, - // https://www.felixcloutier.com/x86/pminsb:pminsw - PMINSW: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0xea}}, - // https://www.felixcloutier.com/x86/pminsb:pminsw - PMINSB: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x38, 0x38}}, - // https://www.felixcloutier.com/x86/pminud:pminuq - PMINUD: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x38, 0x3b}}, - // https://www.felixcloutier.com/x86/pminub:pminuw - PMINUW: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x38, 0x3a}}, - // https://www.felixcloutier.com/x86/pminub:pminuw - PMINUB: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0xda}}, - // https://www.felixcloutier.com/x86/pmaxud:pmaxuq - PMAXUD: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x38, 0x3f}}, - // https://www.felixcloutier.com/x86/pmaxub:pmaxuw - PMAXUW: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x38, 0x3e}}, - // https://www.felixcloutier.com/x86/pmaxub:pmaxuw - PMAXUB: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0xde}}, - // https://www.felixcloutier.com/x86/pmullw - PMULLW: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0xd5}}, - // https://www.felixcloutier.com/x86/pmulld:pmullq - PMULLD: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x38, 0x40}}, - // https://www.felixcloutier.com/x86/pmuludq - PMULUDQ: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0xf4}}, - // https://www.felixcloutier.com/x86/psubsb:psubsw - PSUBSB: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0xe8}}, - // https://www.felixcloutier.com/x86/psubsb:psubsw - PSUBSW: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0xe9}}, - // https://www.felixcloutier.com/x86/psubusb:psubusw - PSUBUSB: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0xd8}}, - // https://www.felixcloutier.com/x86/psubusb:psubusw - PSUBUSW: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0xd9}}, - // https://www.felixcloutier.com/x86/paddsb:paddsw - PADDSW: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0xed}}, - // https://www.felixcloutier.com/x86/paddsb:paddsw - PADDSB: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0xec}}, - // https://www.felixcloutier.com/x86/paddusb:paddusw - PADDUSW: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0xdd}}, - // https://www.felixcloutier.com/x86/pavgb:pavgw - PAVGB: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0xe0}}, - // https://www.felixcloutier.com/x86/pavgb:pavgw - PAVGW: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0xe3}}, - // https://www.felixcloutier.com/x86/pabsb:pabsw:pabsd:pabsq - PABSB: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x38, 0x1c}}, - // https://www.felixcloutier.com/x86/pabsb:pabsw:pabsd:pabsq - PABSW: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x38, 0x1d}}, - // https://www.felixcloutier.com/x86/pabsb:pabsw:pabsd:pabsq - PABSD: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x38, 0x1e}}, - // https://www.felixcloutier.com/x86/blendvpd - BLENDVPD: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x38, 0x15}}, - // https://www.felixcloutier.com/x86/maxpd - MAXPD: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x5f}}, - // https://www.felixcloutier.com/x86/maxps - MAXPS: {opcode: []byte{0x0f, 0x5f}}, - // https://www.felixcloutier.com/x86/minpd - MINPD: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x5d}}, - // https://www.felixcloutier.com/x86/minps - MINPS: {opcode: []byte{0x0f, 0x5d}}, - // https://www.felixcloutier.com/x86/andnpd - ANDNPD: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x55}}, - // https://www.felixcloutier.com/x86/andnps - ANDNPS: {opcode: []byte{0x0f, 0x55}}, - // https://www.felixcloutier.com/x86/mulps - MULPS: {opcode: []byte{0x0f, 0x59}}, - // https://www.felixcloutier.com/x86/mulpd - MULPD: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x59}}, - // https://www.felixcloutier.com/x86/divps - DIVPS: {opcode: []byte{0x0f, 0x5e}}, - // https://www.felixcloutier.com/x86/divpd - DIVPD: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x5e}}, - // https://www.felixcloutier.com/x86/sqrtps - SQRTPS: {opcode: []byte{0x0f, 0x51}}, - // https://www.felixcloutier.com/x86/sqrtpd - SQRTPD: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x51}}, - // https://www.felixcloutier.com/x86/roundps - ROUNDPS: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x3a, 0x08}, needArg: true}, - // https://www.felixcloutier.com/x86/roundpd - ROUNDPD: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x3a, 0x09}, needArg: true}, - // https://www.felixcloutier.com/x86/palignr - PALIGNR: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x3a, 0x0f}, needArg: true}, - // https://www.felixcloutier.com/x86/punpcklbw:punpcklwd:punpckldq:punpcklqdq - PUNPCKLWD: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x61}}, - // https://www.felixcloutier.com/x86/punpckhbw:punpckhwd:punpckhdq:punpckhqdq - PUNPCKHWD: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x69}}, - // https://www.felixcloutier.com/x86/pmulhuw - PMULHUW: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0xe4}}, - // https://www.felixcloutier.com/x86/pmuldq - PMULDQ: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x38, 0x28}}, - // https://www.felixcloutier.com/x86/pmulhrsw - PMULHRSW: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x38, 0x0b}}, - // https://www.felixcloutier.com/x86/pmovsx - PMOVSXBW: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x38, 0x20}}, - // https://www.felixcloutier.com/x86/pmovsx - PMOVSXWD: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x38, 0x23}}, - // https://www.felixcloutier.com/x86/pmovsx - PMOVSXDQ: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x38, 0x25}}, - // https://www.felixcloutier.com/x86/pmovzx - PMOVZXBW: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x38, 0x30}}, - // https://www.felixcloutier.com/x86/pmovzx - PMOVZXWD: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x38, 0x33}}, - // https://www.felixcloutier.com/x86/pmovzx - PMOVZXDQ: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x38, 0x35}}, - // https://www.felixcloutier.com/x86/pmulhw - PMULHW: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0xe5}}, - // https://www.felixcloutier.com/x86/cmpps - CMPEQPS: {opcode: []byte{0x0f, 0xc2}, needArg: true}, - // https://www.felixcloutier.com/x86/cmppd - CMPEQPD: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0xc2}, needArg: true}, - // https://www.felixcloutier.com/x86/cvttps2dq - CVTTPS2DQ: {mandatoryPrefix: 0xf3, opcode: []byte{0x0f, 0x5b}}, - // https://www.felixcloutier.com/x86/cvtdq2ps - CVTDQ2PS: {opcode: []byte{0x0f, 0x5b}}, - // https://www.felixcloutier.com/x86/cvtdq2pd - CVTDQ2PD: {mandatoryPrefix: 0xf3, opcode: []byte{0x0f, 0xe6}}, - // https://www.felixcloutier.com/x86/cvtpd2ps - CVTPD2PS: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x5a}}, - // https://www.felixcloutier.com/x86/cvtps2pd - CVTPS2PD: {opcode: []byte{0x0f, 0x5a}}, - // https://www.felixcloutier.com/x86/movupd - MOVUPD: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x10}}, - // https://www.felixcloutier.com/x86/shufps - SHUFPS: {opcode: []byte{0x0f, 0xc6}, needArg: true}, - // https://www.felixcloutier.com/x86/pmaddwd - PMADDWD: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0xf5}}, - // https://www.felixcloutier.com/x86/unpcklps - UNPCKLPS: {opcode: []byte{0x0f, 0x14}}, - // https://www.felixcloutier.com/x86/packuswb - PACKUSWB: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x67}}, - // https://www.felixcloutier.com/x86/packsswb:packssdw - PACKSSDW: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x6b}}, - // https://www.felixcloutier.com/x86/packusdw - PACKUSDW: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x38, 0x2b}}, - // https://www.felixcloutier.com/x86/pmaddubsw - PMADDUBSW: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x38, 0x04}}, - // https://www.felixcloutier.com/x86/cvttpd2dq - CVTTPD2DQ: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0xe6}}, -} - -var registerToRegisterShiftOpcode = [instructionEnd]*struct { - opcode []byte - rPrefix rexPrefix - modRMExtension byte -}{ - // https://www.felixcloutier.com/x86/rcl:rcr:rol:ror - ROLL: {opcode: []byte{0xd3}}, - ROLQ: {opcode: []byte{0xd3}, rPrefix: rexPrefixW}, - RORL: {opcode: []byte{0xd3}, modRMExtension: 0b00_001_000}, - RORQ: {opcode: []byte{0xd3}, modRMExtension: 0b00_001_000, rPrefix: rexPrefixW}, - // https://www.felixcloutier.com/x86/sal:sar:shl:shr - SARL: {opcode: []byte{0xd3}, modRMExtension: 0b00_111_000}, - SARQ: {opcode: []byte{0xd3}, modRMExtension: 0b00_111_000, rPrefix: rexPrefixW}, - SHLL: {opcode: []byte{0xd3}, modRMExtension: 0b00_100_000}, - SHLQ: {opcode: []byte{0xd3}, modRMExtension: 0b00_100_000, rPrefix: rexPrefixW}, - SHRL: {opcode: []byte{0xd3}, modRMExtension: 0b00_101_000}, - SHRQ: {opcode: []byte{0xd3}, modRMExtension: 0b00_101_000, rPrefix: rexPrefixW}, -} - -func (a *AssemblerImpl) encodeRegisterToRegister(buf asm.Buffer, n *nodeImpl) (err error) { - // Alias for readability - inst := n.instruction - base := buf.Len() - code := buf.Append(8)[:0] - - switch inst { - case MOVL, MOVQ: - var ( - opcode []byte - mandatoryPrefix byte - srcOnModRMReg bool - rPrefix rexPrefix - ) - srcIsFloat, dstIsFloat := isVectorRegister(n.srcReg), isVectorRegister(n.dstReg) - f2f := srcIsFloat && dstIsFloat - if f2f { - // https://www.felixcloutier.com/x86/movq - opcode, mandatoryPrefix = []byte{0x0f, 0x7e}, 0xf3 - } else if srcIsFloat && !dstIsFloat { - // https://www.felixcloutier.com/x86/movd:movq - opcode, mandatoryPrefix, srcOnModRMReg = []byte{0x0f, 0x7e}, 0x66, true - } else if !srcIsFloat && dstIsFloat { - // https://www.felixcloutier.com/x86/movd:movq - opcode, mandatoryPrefix, srcOnModRMReg = []byte{0x0f, 0x6e}, 0x66, false - } else { - // https://www.felixcloutier.com/x86/mov - opcode, srcOnModRMReg = []byte{0x89}, true - } - - rexPrefix, modRM, err := n.getRegisterToRegisterModRM(srcOnModRMReg) - if err != nil { - return err - } - rexPrefix |= rPrefix - - if inst == MOVQ && !f2f { - rexPrefix |= rexPrefixW - } - if mandatoryPrefix != 0 { - code = append(code, mandatoryPrefix) - } - if rexPrefix != rexPrefixNone { - code = append(code, rexPrefix) - } - code = append(code, opcode...) - code = append(code, modRM) - buf.Truncate(base + len(code)) - return nil - } - - if op := registerToRegisterOpcode[inst]; op != nil { - rexPrefix, modRM, err := n.getRegisterToRegisterModRM(op.srcOnModRMReg) - if err != nil { - return err - } - rexPrefix |= op.rPrefix - - if op.isSrc8bit && RegSP <= n.srcReg && n.srcReg <= RegDI { - // If an operand register is 8-bit length of SP, BP, DI, or SI register, we need to have the default prefix. - // https://wiki.osdev.org/X86-64_Instruction_Encoding#Registers - rexPrefix |= rexPrefixDefault - } - - if op.mandatoryPrefix != 0 { - code = append(code, op.mandatoryPrefix) - } - - if rexPrefix != rexPrefixNone { - code = append(code, rexPrefix) - } - code = append(code, op.opcode...) - code = append(code, modRM) - - if op.needArg { - code = append(code, n.arg) - } - } else if op := registerToRegisterShiftOpcode[inst]; op != nil { - reg3bits, rexPrefix := register3bits(n.dstReg, registerSpecifierPositionModRMFieldRM) - rexPrefix |= op.rPrefix - if rexPrefix != rexPrefixNone { - code = append(code, rexPrefix) - } - - // https://wiki.osdev.org/X86-64_Instruction_Encoding#ModR.2FM - modRM := 0b11_000_000 | - (op.modRMExtension) | - reg3bits - code = append(code, op.opcode...) - code = append(code, modRM) - } else { - return errorEncodingUnsupported(n) - } - - buf.Truncate(base + len(code)) - return nil -} - -func (a *AssemblerImpl) encodeRegisterToMemory(buf asm.Buffer, n *nodeImpl) (err error) { - rexPrefix, modRM, sbi, sbiExist, displacementWidth, err := n.getMemoryLocation(true) - if err != nil { - return err - } - - var opcode []byte - var mandatoryPrefix byte - var isShiftInstruction bool - var needArg bool - switch n.instruction { - case CMPL: - // https://www.felixcloutier.com/x86/cmp - opcode = []byte{0x3b} - case CMPQ: - // https://www.felixcloutier.com/x86/cmp - rexPrefix |= rexPrefixW - opcode = []byte{0x3b} - case MOVB: - // https://www.felixcloutier.com/x86/mov - opcode = []byte{0x88} - // 1 byte register operands need default prefix for the following registers. - if n.srcReg >= RegSP && n.srcReg <= RegDI { - rexPrefix |= rexPrefixDefault - } - case MOVL: - if isVectorRegister(n.srcReg) { - // https://www.felixcloutier.com/x86/movd:movq - opcode = []byte{0x0f, 0x7e} - mandatoryPrefix = 0x66 - } else { - // https://www.felixcloutier.com/x86/mov - opcode = []byte{0x89} - } - case MOVQ: - if isVectorRegister(n.srcReg) { - // https://www.felixcloutier.com/x86/movq - opcode = []byte{0x0f, 0xd6} - mandatoryPrefix = 0x66 - } else { - // https://www.felixcloutier.com/x86/mov - rexPrefix |= rexPrefixW - opcode = []byte{0x89} - } - case MOVW: - // https://www.felixcloutier.com/x86/mov - // Note: Need 0x66 to indicate that the operand size is 16-bit. - // https://wiki.osdev.org/X86-64_Instruction_Encoding#Operand-size_and_address-size_override_prefix - mandatoryPrefix = 0x66 - opcode = []byte{0x89} - case SARL: - // https://www.felixcloutier.com/x86/sal:sar:shl:shr - modRM |= 0b00_111_000 - opcode = []byte{0xd3} - isShiftInstruction = true - case SARQ: - // https://www.felixcloutier.com/x86/sal:sar:shl:shr - rexPrefix |= rexPrefixW - modRM |= 0b00_111_000 - opcode = []byte{0xd3} - isShiftInstruction = true - case SHLL: - // https://www.felixcloutier.com/x86/sal:sar:shl:shr - modRM |= 0b00_100_000 - opcode = []byte{0xd3} - isShiftInstruction = true - case SHLQ: - // https://www.felixcloutier.com/x86/sal:sar:shl:shr - rexPrefix |= rexPrefixW - modRM |= 0b00_100_000 - opcode = []byte{0xd3} - isShiftInstruction = true - case SHRL: - // https://www.felixcloutier.com/x86/sal:sar:shl:shr - modRM |= 0b00_101_000 - opcode = []byte{0xd3} - isShiftInstruction = true - case SHRQ: - // https://www.felixcloutier.com/x86/sal:sar:shl:shr - rexPrefix |= rexPrefixW - modRM |= 0b00_101_000 - opcode = []byte{0xd3} - isShiftInstruction = true - case ROLL: - // https://www.felixcloutier.com/x86/rcl:rcr:rol:ror - opcode = []byte{0xd3} - isShiftInstruction = true - case ROLQ: - // https://www.felixcloutier.com/x86/rcl:rcr:rol:ror - rexPrefix |= rexPrefixW - opcode = []byte{0xd3} - isShiftInstruction = true - case RORL: - // https://www.felixcloutier.com/x86/rcl:rcr:rol:ror - modRM |= 0b00_001_000 - opcode = []byte{0xd3} - isShiftInstruction = true - case RORQ: - // https://www.felixcloutier.com/x86/rcl:rcr:rol:ror - rexPrefix |= rexPrefixW - opcode = []byte{0xd3} - modRM |= 0b00_001_000 - isShiftInstruction = true - case MOVDQU: - // https://www.felixcloutier.com/x86/movdqu:vmovdqu8:vmovdqu16:vmovdqu32:vmovdqu64 - mandatoryPrefix = 0xf3 - opcode = []byte{0x0f, 0x7f} - case PEXTRB: // https://www.felixcloutier.com/x86/pextrb:pextrd:pextrq - mandatoryPrefix = 0x66 - opcode = []byte{0x0f, 0x3a, 0x14} - needArg = true - case PEXTRW: // https://www.felixcloutier.com/x86/pextrw - mandatoryPrefix = 0x66 - opcode = []byte{0x0f, 0x3a, 0x15} - needArg = true - case PEXTRD: // https://www.felixcloutier.com/x86/pextrb:pextrd:pextrq - mandatoryPrefix = 0x66 - opcode = []byte{0x0f, 0x3a, 0x16} - needArg = true - case PEXTRQ: // https://www.felixcloutier.com/x86/pextrb:pextrd:pextrq - mandatoryPrefix = 0x66 - rexPrefix |= rexPrefixW // REX.W - opcode = []byte{0x0f, 0x3a, 0x16} - needArg = true - case XCHGB: - // https://www.felixcloutier.com/x86/xchg - opcode = []byte{0x86} - // 1 byte register operands need default prefix for the following registers. - if n.srcReg >= RegSP && n.srcReg <= RegDI { - rexPrefix |= rexPrefixDefault - } - case XCHGW: - // https://www.felixcloutier.com/x86/mov - // Note: Need 0x66 to indicate that the operand size is 16-bit. - // https://wiki.osdev.org/X86-64_Instruction_Encoding#Operand-size_and_address-size_override_prefix - mandatoryPrefix = 0x66 - opcode = []byte{0x87} - case XCHGL: - // https://www.felixcloutier.com/x86/xchg - opcode = []byte{0x87} - case XCHGQ: - // https://www.felixcloutier.com/x86/mxchg - rexPrefix |= rexPrefixW - opcode = []byte{0x87} - case XADDB: - // https://www.felixcloutier.com/x86/xadd - opcode = []byte{0x0F, 0xC0} - // 1 byte register operands need default prefix for the following registers. - if n.srcReg >= RegSP && n.srcReg <= RegDI { - rexPrefix |= rexPrefixDefault - } - case XADDW: - // https://www.felixcloutier.com/x86/xadd - // Note: Need 0x66 to indicate that the operand size is 16-bit. - // https://wiki.osdev.org/X86-64_Instruction_Encoding#Operand-size_and_address-size_override_prefix - mandatoryPrefix = 0x66 - opcode = []byte{0x0F, 0xC1} - case XADDL: - // https://www.felixcloutier.com/x86/xadd - opcode = []byte{0x0F, 0xC1} - case XADDQ: - // https://www.felixcloutier.com/x86/xadd - rexPrefix |= rexPrefixW - opcode = []byte{0x0F, 0xC1} - case CMPXCHGB: - // https://www.felixcloutier.com/x86/cmpxchg - opcode = []byte{0x0F, 0xB0} - // 1 byte register operands need default prefix for the following registers. - if n.srcReg >= RegSP && n.srcReg <= RegDI { - rexPrefix |= rexPrefixDefault - } - case CMPXCHGW: - // https://www.felixcloutier.com/x86/cmpxchg - // Note: Need 0x66 to indicate that the operand size is 16-bit. - // https://wiki.osdev.org/X86-64_Instruction_Encoding#Operand-size_and_address-size_override_prefix - mandatoryPrefix = 0x66 - opcode = []byte{0x0F, 0xB1} - case CMPXCHGL: - // https://www.felixcloutier.com/x86/cmpxchg - opcode = []byte{0x0F, 0xB1} - case CMPXCHGQ: - // https://www.felixcloutier.com/x86/cmpxchg - rexPrefix |= rexPrefixW - opcode = []byte{0x0F, 0xB1} - default: - return errorEncodingUnsupported(n) - } - - if !isShiftInstruction { - srcReg3Bits, prefix := register3bits(n.srcReg, registerSpecifierPositionModRMFieldReg) - - rexPrefix |= prefix - modRM |= srcReg3Bits << 3 // Place the source register on ModRM:reg - } else { - if n.srcReg != RegCX { - return fmt.Errorf("shifting instruction %s require CX register as src but got %s", InstructionName(n.instruction), RegisterName(n.srcReg)) - } - } - - base := buf.Len() - code := buf.Append(16)[:0] - - if mandatoryPrefix != 0 { - // https://wiki.osdev.org/X86-64_Instruction_Encoding#Mandatory_prefix - code = append(code, mandatoryPrefix) - } - - if n.isLock() { - code = append(code, lockPrefix) - } - - if rexPrefix != rexPrefixNone { - code = append(code, rexPrefix) - } - - code = append(code, opcode...) - code = append(code, modRM) - - if sbiExist { - code = append(code, sbi) - } - - if displacementWidth != 0 { - code = appendConst(code, n.dstConst, displacementWidth) - } - - if needArg { - code = append(code, n.arg) - } - - buf.Truncate(base + len(code)) - return -} - -func (a *AssemblerImpl) encodeRegisterToConst(buf asm.Buffer, n *nodeImpl) (err error) { - regBits, prefix := register3bits(n.srcReg, registerSpecifierPositionModRMFieldRM) - - base := buf.Len() - code := buf.Append(10)[:0] - - switch n.instruction { - case CMPL, CMPQ: - if n.instruction == CMPQ { - prefix |= rexPrefixW - } - if prefix != rexPrefixNone { - code = append(code, prefix) - } - is8bitConst := fitInSigned8bit(n.dstConst) - // https://www.felixcloutier.com/x86/cmp - if n.srcReg == RegAX && !is8bitConst { - code = append(code, 0x3d) - } else { - // https://wiki.osdev.org/X86-64_Instruction_Encoding#ModR.2FM - modRM := 0b11_000_000 | // Specifying that opeand is register. - 0b00_111_000 | // CMP with immediate needs "/7" extension. - regBits - if is8bitConst { - code = append(code, 0x83, modRM) - } else { - code = append(code, 0x81, modRM) - } - } - default: - err = errorEncodingUnsupported(n) - } - - if fitInSigned8bit(n.dstConst) { - code = append(code, byte(n.dstConst)) - } else { - code = appendUint32(code, uint32(n.dstConst)) - } - - buf.Truncate(base + len(code)) - return -} - -func (a *AssemblerImpl) finalizeReadInstructionAddressNode(code []byte, n *nodeImpl) (err error) { - // Find the target instruction node. - targetNode := n - for ; targetNode != nil; targetNode = targetNode.next { - if targetNode.instruction == n.readInstructionAddressBeforeTargetInstruction { - targetNode = targetNode.next - break - } - } - - if targetNode == nil { - return errors.New("BUG: target instruction not found for read instruction address") - } - - offset := targetNode.OffsetInBinary() - (n.OffsetInBinary() + 7 /* 7 = the length of the LEAQ instruction */) - if offset >= math.MaxInt32 { - return errors.New("BUG: too large offset for LEAQ instruction") - } - - binary.LittleEndian.PutUint32(code[n.OffsetInBinary()+3:], uint32(int32(offset))) - return nil -} - -func (a *AssemblerImpl) encodeReadInstructionAddress(buf asm.Buffer, n *nodeImpl) error { - dstReg3Bits, rexPrefix := register3bits(n.dstReg, registerSpecifierPositionModRMFieldReg) - - a.readInstructionAddressNodes = append(a.readInstructionAddressNodes, n) - - // https://www.felixcloutier.com/x86/lea - opcode := byte(0x8d) - rexPrefix |= rexPrefixW - - // https://wiki.osdev.org/X86-64_Instruction_Encoding#32.2F64-bit_addressing - modRM := 0b00_000_101 | // Indicate "LEAQ [RIP + 32bit displacement], dstReg" encoding. - (dstReg3Bits << 3) // Place the dstReg on ModRM:reg. - - code := buf.Append(7) - code[0] = rexPrefix - code[1] = opcode - code[2] = modRM - binary.LittleEndian.PutUint32(code[3:], 0) // Preserve - return nil -} - -func (a *AssemblerImpl) encodeMemoryToRegister(buf asm.Buffer, n *nodeImpl) (err error) { - if n.instruction == LEAQ && n.readInstructionAddressBeforeTargetInstruction != NONE { - return a.encodeReadInstructionAddress(buf, n) - } - - rexPrefix, modRM, sbi, sbiExist, displacementWidth, err := n.getMemoryLocation(false) - if err != nil { - return err - } - - dstReg3Bits, prefix := register3bits(n.dstReg, registerSpecifierPositionModRMFieldReg) - rexPrefix |= prefix - modRM |= dstReg3Bits << 3 // Place the destination register on ModRM:reg - - var mandatoryPrefix byte - var opcode []byte - var needArg bool - - switch n.instruction { - case ADDL: - // https://www.felixcloutier.com/x86/add - opcode = []byte{0x03} - case ADDQ: - // https://www.felixcloutier.com/x86/add - rexPrefix |= rexPrefixW - opcode = []byte{0x03} - case CMPL: - // https://www.felixcloutier.com/x86/cmp - opcode = []byte{0x39} - case CMPQ: - // https://www.felixcloutier.com/x86/cmp - rexPrefix |= rexPrefixW - opcode = []byte{0x39} - case LEAQ: - // https://www.felixcloutier.com/x86/lea - rexPrefix |= rexPrefixW - opcode = []byte{0x8d} - case MOVBLSX: - // https://www.felixcloutier.com/x86/movsx:movsxd - opcode = []byte{0x0f, 0xbe} - case MOVBLZX: - // https://www.felixcloutier.com/x86/movzx - opcode = []byte{0x0f, 0xb6} - case MOVBQSX: - // https://www.felixcloutier.com/x86/movsx:movsxd - rexPrefix |= rexPrefixW - opcode = []byte{0x0f, 0xbe} - case MOVBQZX: - // https://www.felixcloutier.com/x86/movzx - rexPrefix |= rexPrefixW - opcode = []byte{0x0f, 0xb6} - case MOVLQSX: - // https://www.felixcloutier.com/x86/movsx:movsxd - rexPrefix |= rexPrefixW - opcode = []byte{0x63} - case MOVLQZX: - // https://www.felixcloutier.com/x86/mov - // Note: MOVLQZX means zero extending 32bit reg to 64-bit reg and - // that is semantically equivalent to MOV 32bit to 32bit. - opcode = []byte{0x8B} - case MOVL: - // https://www.felixcloutier.com/x86/mov - // Note: MOVLQZX means zero extending 32bit reg to 64-bit reg and - // that is semantically equivalent to MOV 32bit to 32bit. - if isVectorRegister(n.dstReg) { - // https://www.felixcloutier.com/x86/movd:movq - opcode = []byte{0x0f, 0x6e} - mandatoryPrefix = 0x66 - } else { - // https://www.felixcloutier.com/x86/mov - opcode = []byte{0x8B} - } - case MOVQ: - if isVectorRegister(n.dstReg) { - // https://www.felixcloutier.com/x86/movq - opcode = []byte{0x0f, 0x7e} - mandatoryPrefix = 0xf3 - } else { - // https://www.felixcloutier.com/x86/mov - rexPrefix |= rexPrefixW - opcode = []byte{0x8B} - } - case MOVWLSX: - // https://www.felixcloutier.com/x86/movsx:movsxd - opcode = []byte{0x0f, 0xbf} - case MOVWLZX: - // https://www.felixcloutier.com/x86/movzx - opcode = []byte{0x0f, 0xb7} - case MOVWQSX: - // https://www.felixcloutier.com/x86/movsx:movsxd - rexPrefix |= rexPrefixW - opcode = []byte{0x0f, 0xbf} - case MOVWQZX: - // https://www.felixcloutier.com/x86/movzx - rexPrefix |= rexPrefixW - opcode = []byte{0x0f, 0xb7} - case SUBQ: - // https://www.felixcloutier.com/x86/sub - rexPrefix |= rexPrefixW - opcode = []byte{0x2b} - case SUBSD: - // https://www.felixcloutier.com/x86/subsd - opcode = []byte{0x0f, 0x5c} - mandatoryPrefix = 0xf2 - case SUBSS: - // https://www.felixcloutier.com/x86/subss - opcode = []byte{0x0f, 0x5c} - mandatoryPrefix = 0xf3 - case UCOMISD: - // https://www.felixcloutier.com/x86/ucomisd - opcode = []byte{0x0f, 0x2e} - mandatoryPrefix = 0x66 - case UCOMISS: - // https://www.felixcloutier.com/x86/ucomiss - opcode = []byte{0x0f, 0x2e} - case MOVDQU: - // https://www.felixcloutier.com/x86/movdqu:vmovdqu8:vmovdqu16:vmovdqu32:vmovdqu64 - mandatoryPrefix = 0xf3 - opcode = []byte{0x0f, 0x6f} - case PMOVSXBW: // https://www.felixcloutier.com/x86/pmovsx - mandatoryPrefix = 0x66 - opcode = []byte{0x0f, 0x38, 0x20} - case PMOVSXWD: // https://www.felixcloutier.com/x86/pmovsx - mandatoryPrefix = 0x66 - opcode = []byte{0x0f, 0x38, 0x23} - case PMOVSXDQ: // https://www.felixcloutier.com/x86/pmovsx - mandatoryPrefix = 0x66 - opcode = []byte{0x0f, 0x38, 0x25} - case PMOVZXBW: // https://www.felixcloutier.com/x86/pmovzx - mandatoryPrefix = 0x66 - opcode = []byte{0x0f, 0x38, 0x30} - case PMOVZXWD: // https://www.felixcloutier.com/x86/pmovzx - mandatoryPrefix = 0x66 - opcode = []byte{0x0f, 0x38, 0x33} - case PMOVZXDQ: // https://www.felixcloutier.com/x86/pmovzx - mandatoryPrefix = 0x66 - opcode = []byte{0x0f, 0x38, 0x35} - case PINSRB: // https://www.felixcloutier.com/x86/pinsrb:pinsrd:pinsrq - mandatoryPrefix = 0x66 - opcode = []byte{0x0f, 0x3a, 0x20} - needArg = true - case PINSRW: // https://www.felixcloutier.com/x86/pinsrw - mandatoryPrefix = 0x66 - opcode = []byte{0x0f, 0xc4} - needArg = true - case PINSRD: // https://www.felixcloutier.com/x86/pinsrb:pinsrd:pinsrq - mandatoryPrefix = 0x66 - opcode = []byte{0x0f, 0x3a, 0x22} - needArg = true - case PINSRQ: // https://www.felixcloutier.com/x86/pinsrb:pinsrd:pinsrq - rexPrefix |= rexPrefixW - mandatoryPrefix = 0x66 - opcode = []byte{0x0f, 0x3a, 0x22} - needArg = true - default: - return errorEncodingUnsupported(n) - } - - base := buf.Len() - code := buf.Append(16)[:0] - - if mandatoryPrefix != 0 { - // https://wiki.osdev.org/X86-64_Instruction_Encoding#Mandatory_prefix - code = append(code, mandatoryPrefix) - } - - if rexPrefix != rexPrefixNone { - code = append(code, rexPrefix) - } - - code = append(code, opcode...) - code = append(code, modRM) - - if sbiExist { - code = append(code, sbi) - } - - if displacementWidth != 0 { - code = appendConst(code, n.srcConst, displacementWidth) - } - - if needArg { - code = append(code, n.arg) - } - - buf.Truncate(base + len(code)) - return -} - -func (a *AssemblerImpl) encodeConstToRegister(buf asm.Buffer, n *nodeImpl) (err error) { - regBits, rexPrefix := register3bits(n.dstReg, registerSpecifierPositionModRMFieldRM) - - isFloatReg := isVectorRegister(n.dstReg) - switch n.instruction { - case PSLLD, PSLLQ, PSRLD, PSRLQ, PSRAW, PSRLW, PSLLW, PSRAD: - if !isFloatReg { - return fmt.Errorf("%s needs float register but got %s", InstructionName(n.instruction), RegisterName(n.dstReg)) - } - default: - if isFloatReg { - return fmt.Errorf("%s needs int register but got %s", InstructionName(n.instruction), RegisterName(n.dstReg)) - } - } - - if n.instruction != MOVQ && !fitIn32bit(n.srcConst) { - return fmt.Errorf("constant must fit in 32-bit integer for %s, but got %d", InstructionName(n.instruction), n.srcConst) - } else if (n.instruction == SHLQ || n.instruction == SHRQ) && (n.srcConst < 0 || n.srcConst > math.MaxUint8) { - return fmt.Errorf("constant must fit in positive 8-bit integer for %s, but got %d", InstructionName(n.instruction), n.srcConst) - } else if (n.instruction == PSLLD || - n.instruction == PSLLQ || - n.instruction == PSRLD || - n.instruction == PSRLQ) && (n.srcConst < math.MinInt8 || n.srcConst > math.MaxInt8) { - return fmt.Errorf("constant must fit in signed 8-bit integer for %s, but got %d", InstructionName(n.instruction), n.srcConst) - } - - base := buf.Len() - code := buf.Append(32)[:0] - - isSigned8bitConst := fitInSigned8bit(n.srcConst) - switch inst := n.instruction; inst { - case ADDQ: - // https://www.felixcloutier.com/x86/add - rexPrefix |= rexPrefixW - if n.dstReg == RegAX && !isSigned8bitConst { - code = append(code, rexPrefix, 0x05) - } else { - modRM := 0b11_000_000 | // Specifying that opeand is register. - regBits - if isSigned8bitConst { - code = append(code, rexPrefix, 0x83, modRM) - } else { - code = append(code, rexPrefix, 0x81, modRM) - } - } - if isSigned8bitConst { - code = append(code, byte(n.srcConst)) - } else { - code = appendUint32(code, uint32(n.srcConst)) - } - case ANDQ: - // https://www.felixcloutier.com/x86/and - rexPrefix |= rexPrefixW - if n.dstReg == RegAX && !isSigned8bitConst { - code = append(code, rexPrefix, 0x25) - } else { - modRM := 0b11_000_000 | // Specifying that opeand is register. - 0b00_100_000 | // AND with immediate needs "/4" extension. - regBits - if isSigned8bitConst { - code = append(code, rexPrefix, 0x83, modRM) - } else { - code = append(code, rexPrefix, 0x81, modRM) - } - } - if fitInSigned8bit(n.srcConst) { - code = append(code, byte(n.srcConst)) - } else { - code = appendUint32(code, uint32(n.srcConst)) - } - case TESTQ: - // https://www.felixcloutier.com/x86/test - rexPrefix |= rexPrefixW - if n.dstReg == RegAX && !isSigned8bitConst { - code = append(code, rexPrefix, 0xa9) - } else { - modRM := 0b11_000_000 | // Specifying that operand is register - regBits - code = append(code, rexPrefix, 0xf7, modRM) - } - code = appendUint32(code, uint32(n.srcConst)) - case MOVL: - // https://www.felixcloutier.com/x86/mov - if rexPrefix != rexPrefixNone { - code = append(code, rexPrefix) - } - code = append(code, 0xb8|regBits) - code = appendUint32(code, uint32(n.srcConst)) - case MOVQ: - // https://www.felixcloutier.com/x86/mov - if fitIn32bit(n.srcConst) { - if n.srcConst > math.MaxInt32 { - if rexPrefix != rexPrefixNone { - code = append(code, rexPrefix) - } - code = append(code, 0xb8|regBits) - } else { - rexPrefix |= rexPrefixW - modRM := 0b11_000_000 | // Specifying that opeand is register. - regBits - code = append(code, rexPrefix, 0xc7, modRM) - } - code = appendUint32(code, uint32(n.srcConst)) - } else { - rexPrefix |= rexPrefixW - code = append(code, rexPrefix, 0xb8|regBits) - code = appendUint64(code, uint64(n.srcConst)) - } - case SHLQ: - // https://www.felixcloutier.com/x86/sal:sar:shl:shr - rexPrefix |= rexPrefixW - modRM := 0b11_000_000 | // Specifying that opeand is register. - 0b00_100_000 | // SHL with immediate needs "/4" extension. - regBits - if n.srcConst == 1 { - code = append(code, rexPrefix, 0xd1, modRM) - } else { - code = append(code, rexPrefix, 0xc1, modRM, byte(n.srcConst)) - } - case SHRQ: - // https://www.felixcloutier.com/x86/sal:sar:shl:shr - rexPrefix |= rexPrefixW - modRM := 0b11_000_000 | // Specifying that opeand is register. - 0b00_101_000 | // SHR with immediate needs "/5" extension. - regBits - if n.srcConst == 1 { - code = append(code, rexPrefix, 0xd1, modRM) - } else { - code = append(code, rexPrefix, 0xc1, modRM, byte(n.srcConst)) - } - case PSLLD: - // https://www.felixcloutier.com/x86/psllw:pslld:psllq - modRM := 0b11_000_000 | // Specifying that opeand is register. - 0b00_110_000 | // PSLL with immediate needs "/6" extension. - regBits - if rexPrefix != rexPrefixNone { - code = append(code, 0x66, rexPrefix, 0x0f, 0x72, modRM, byte(n.srcConst)) - } else { - code = append(code, 0x66, 0x0f, 0x72, modRM, byte(n.srcConst)) - } - case PSLLQ: - // https://www.felixcloutier.com/x86/psllw:pslld:psllq - modRM := 0b11_000_000 | // Specifying that opeand is register. - 0b00_110_000 | // PSLL with immediate needs "/6" extension. - regBits - if rexPrefix != rexPrefixNone { - code = append(code, 0x66, rexPrefix, 0x0f, 0x73, modRM, byte(n.srcConst)) - } else { - code = append(code, 0x66, 0x0f, 0x73, modRM, byte(n.srcConst)) - } - case PSRLD: - // https://www.felixcloutier.com/x86/psrlw:psrld:psrlq - // https://www.felixcloutier.com/x86/psllw:pslld:psllq - modRM := 0b11_000_000 | // Specifying that operand is register. - 0b00_010_000 | // PSRL with immediate needs "/2" extension. - regBits - if rexPrefix != rexPrefixNone { - code = append(code, 0x66, rexPrefix, 0x0f, 0x72, modRM, byte(n.srcConst)) - } else { - code = append(code, 0x66, 0x0f, 0x72, modRM, byte(n.srcConst)) - } - case PSRLQ: - // https://www.felixcloutier.com/x86/psrlw:psrld:psrlq - modRM := 0b11_000_000 | // Specifying that operand is register. - 0b00_010_000 | // PSRL with immediate needs "/2" extension. - regBits - if rexPrefix != rexPrefixNone { - code = append(code, 0x66, rexPrefix, 0x0f, 0x73, modRM, byte(n.srcConst)) - } else { - code = append(code, 0x66, 0x0f, 0x73, modRM, byte(n.srcConst)) - } - case PSRAW, PSRAD: - // https://www.felixcloutier.com/x86/psraw:psrad:psraq - modRM := 0b11_000_000 | // Specifying that operand is register. - 0b00_100_000 | // PSRAW with immediate needs "/4" extension. - regBits - code = append(code, 0x66) - if rexPrefix != rexPrefixNone { - code = append(code, rexPrefix) - } - - var op byte - if inst == PSRAD { - op = 0x72 - } else { // PSRAW - op = 0x71 - } - - code = append(code, 0x0f, op, modRM, byte(n.srcConst)) - case PSRLW: - // https://www.felixcloutier.com/x86/psrlw:psrld:psrlq - modRM := 0b11_000_000 | // Specifying that operand is register. - 0b00_010_000 | // PSRLW with immediate needs "/2" extension. - regBits - code = append(code, 0x66) - if rexPrefix != rexPrefixNone { - code = append(code, rexPrefix) - } - code = append(code, 0x0f, 0x71, modRM, byte(n.srcConst)) - case PSLLW: - // https://www.felixcloutier.com/x86/psllw:pslld:psllq - modRM := 0b11_000_000 | // Specifying that operand is register. - 0b00_110_000 | // PSLLW with immediate needs "/6" extension. - regBits - code = append(code, 0x66) - if rexPrefix != rexPrefixNone { - code = append(code, rexPrefix) - } - code = append(code, 0x0f, 0x71, modRM, byte(n.srcConst)) - case XORL, XORQ: - // https://www.felixcloutier.com/x86/xor - if inst == XORQ { - rexPrefix |= rexPrefixW - } - if rexPrefix != rexPrefixNone { - code = append(code, rexPrefix) - } - if n.dstReg == RegAX && !isSigned8bitConst { - code = append(code, 0x35) - } else { - modRM := 0b11_000_000 | // Specifying that opeand is register. - 0b00_110_000 | // XOR with immediate needs "/6" extension. - regBits - if isSigned8bitConst { - code = append(code, 0x83, modRM) - } else { - code = append(code, 0x81, modRM) - } - } - if fitInSigned8bit(n.srcConst) { - code = append(code, byte(n.srcConst)) - } else { - code = appendUint32(code, uint32(n.srcConst)) - } - default: - err = errorEncodingUnsupported(n) - } - - buf.Truncate(base + len(code)) - return -} - -func (a *AssemblerImpl) encodeMemoryToConst(buf asm.Buffer, n *nodeImpl) (err error) { - if !fitIn32bit(n.dstConst) { - return fmt.Errorf("too large target const %d for %s", n.dstConst, InstructionName(n.instruction)) - } - - rexPrefix, modRM, sbi, sbiExist, displacementWidth, err := n.getMemoryLocation(false) - if err != nil { - return err - } - - // Alias for readability. - c := n.dstConst - - var opcode, constWidth byte - switch n.instruction { - case CMPL: - // https://www.felixcloutier.com/x86/cmp - if fitInSigned8bit(c) { - opcode = 0x83 - constWidth = 8 - } else { - opcode = 0x81 - constWidth = 32 - } - modRM |= 0b00_111_000 - default: - return errorEncodingUnsupported(n) - } - - base := buf.Len() - code := buf.Append(20)[:0] - - if rexPrefix != rexPrefixNone { - code = append(code, rexPrefix) - } - - code = append(code, opcode, modRM) - - if sbiExist { - code = append(code, sbi) - } - - if displacementWidth != 0 { - code = appendConst(code, n.srcConst, displacementWidth) - } - - code = appendConst(code, c, constWidth) - buf.Truncate(base + len(code)) - return -} - -func (a *AssemblerImpl) encodeConstToMemory(buf asm.Buffer, n *nodeImpl) (err error) { - rexPrefix, modRM, sbi, sbiExist, displacementWidth, err := n.getMemoryLocation(true) - if err != nil { - return err - } - - // Alias for readability. - inst := n.instruction - c := n.srcConst - - if inst == MOVB && !fitInSigned8bit(c) { - return fmt.Errorf("too large load target const %d for MOVB", c) - } else if !fitIn32bit(c) { - return fmt.Errorf("too large load target const %d for %s", c, InstructionName(n.instruction)) - } - - var constWidth, opcode byte - switch inst { - case MOVB: - opcode = 0xc6 - constWidth = 8 - case MOVL: - opcode = 0xc7 - constWidth = 32 - case MOVQ: - rexPrefix |= rexPrefixW - opcode = 0xc7 - constWidth = 32 - default: - return errorEncodingUnsupported(n) - } - - base := buf.Len() - code := buf.Append(20)[:0] - - if rexPrefix != rexPrefixNone { - code = append(code, rexPrefix) - } - - code = append(code, opcode, modRM) - - if sbiExist { - code = append(code, sbi) - } - - if displacementWidth != 0 { - code = appendConst(code, n.dstConst, displacementWidth) - } - - code = appendConst(code, c, constWidth) - - buf.Truncate(base + len(code)) - return -} - -func appendUint32(code []byte, v uint32) []byte { - b := [4]byte{} - binary.LittleEndian.PutUint32(b[:], uint32(v)) - return append(code, b[:]...) -} - -func appendUint64(code []byte, v uint64) []byte { - b := [8]byte{} - binary.LittleEndian.PutUint64(b[:], uint64(v)) - return append(code, b[:]...) -} - -func appendConst(code []byte, v int64, length byte) []byte { - switch length { - case 8: - return append(code, byte(v)) - case 32: - return appendUint32(code, uint32(v)) - default: - return appendUint64(code, uint64(v)) - } -} - -func (n *nodeImpl) getMemoryLocation(dstMem bool) (p rexPrefix, modRM byte, sbi byte, sbiExist bool, displacementWidth byte, err error) { - var baseReg, indexReg asm.Register - var offset asm.ConstantValue - var scale byte - if dstMem { - baseReg, offset, indexReg, scale = n.dstReg, n.dstConst, n.dstMemIndex, n.dstMemScale - } else { - baseReg, offset, indexReg, scale = n.srcReg, n.srcConst, n.srcMemIndex, n.srcMemScale - } - - if !fitIn32bit(offset) { - err = errors.New("offset does not fit in 32-bit integer") - return - } - - if baseReg == asm.NilRegister && indexReg != asm.NilRegister { - // [(index*scale) + displacement] addressing is possible, but we haven't used it for now. - err = errors.New("addressing without base register but with index is not implemented") - } else if baseReg == asm.NilRegister { - modRM = 0b00_000_100 // Indicate that the memory location is specified by SIB. - sbi, sbiExist = byte(0b00_100_101), true - displacementWidth = 32 - } else if indexReg == asm.NilRegister { - modRM, p = register3bits(baseReg, registerSpecifierPositionModRMFieldRM) - - // Create ModR/M byte so that this instruction takes [R/M + displacement] operand if displacement !=0 - // and otherwise [R/M]. - withoutDisplacement := offset == 0 && - // If the target register is R13 or BP, we have to keep [R/M + displacement] even if the value - // is zero since it's not [R/M] operand is not defined for these two registers. - // https://wiki.osdev.org/X86-64_Instruction_Encoding#32.2F64-bit_addressing - baseReg != RegR13 && baseReg != RegBP - if withoutDisplacement { - // https://wiki.osdev.org/X86-64_Instruction_Encoding#ModR.2FM - modRM |= 0b00_000_000 // Specifying that operand is memory without displacement - displacementWidth = 0 - } else if fitInSigned8bit(offset) { - // https://wiki.osdev.org/X86-64_Instruction_Encoding#ModR.2FM - modRM |= 0b01_000_000 // Specifying that operand is memory + 8bit displacement. - displacementWidth = 8 - } else { - // https://wiki.osdev.org/X86-64_Instruction_Encoding#ModR.2FM - modRM |= 0b10_000_000 // Specifying that operand is memory + 32bit displacement. - displacementWidth = 32 - } - - // For SP and R12 register, we have [SIB + displacement] if the const is non-zero, otherwise [SIP]. - // https://wiki.osdev.org/X86-64_Instruction_Encoding#32.2F64-bit_addressing - // - // Thefore we emit the SIB byte before the const so that [SIB + displacement] ends up [register + displacement]. - // https://wiki.osdev.org/X86-64_Instruction_Encoding#32.2F64-bit_addressing_2 - if baseReg == RegSP || baseReg == RegR12 { - sbi, sbiExist = byte(0b00_100_100), true - } - } else { - if indexReg == RegSP { - err = errors.New("SP cannot be used for SIB index") - return - } - - modRM = 0b00_000_100 // Indicate that the memory location is specified by SIB. - - withoutDisplacement := offset == 0 && - // For R13 and BP, base registers cannot be encoded "without displacement" mod (i.e. 0b00 mod). - baseReg != RegR13 && baseReg != RegBP - if withoutDisplacement { - // https://wiki.osdev.org/X86-64_Instruction_Encoding#ModR.2FM - modRM |= 0b00_000_000 // Specifying that operand is SIB without displacement - displacementWidth = 0 - } else if fitInSigned8bit(offset) { - // https://wiki.osdev.org/X86-64_Instruction_Encoding#ModR.2FM - modRM |= 0b01_000_000 // Specifying that operand is SIB + 8bit displacement. - displacementWidth = 8 - } else { - // https://wiki.osdev.org/X86-64_Instruction_Encoding#ModR.2FM - modRM |= 0b10_000_000 // Specifying that operand is SIB + 32bit displacement. - displacementWidth = 32 - } - - var baseRegBits byte - baseRegBits, p = register3bits(baseReg, registerSpecifierPositionModRMFieldRM) - - var indexRegBits byte - var indexRegPrefix rexPrefix - indexRegBits, indexRegPrefix = register3bits(indexReg, registerSpecifierPositionSIBIndex) - p |= indexRegPrefix - - sbi, sbiExist = baseRegBits|(indexRegBits<<3), true - switch scale { - case 1: - sbi |= 0b00_000_000 - case 2: - sbi |= 0b01_000_000 - case 4: - sbi |= 0b10_000_000 - case 8: - sbi |= 0b11_000_000 - default: - err = fmt.Errorf("scale in SIB must be one of 1, 2, 4, 8 but got %d", scale) - return - } - - } - return -} - -// getRegisterToRegisterModRM does XXXX -// -// TODO: srcOnModRMReg can be deleted after golang-asm removal. This is necessary to match our implementation -// with golang-asm, but in practice, there are equivalent opcodes to always have src on ModRM:reg without ambiguity. -func (n *nodeImpl) getRegisterToRegisterModRM(srcOnModRMReg bool) (rexPrefix, modRM byte, err error) { - var reg3bits, rm3bits byte - if srcOnModRMReg { - reg3bits, rexPrefix = register3bits(n.srcReg, - // Indicate that srcReg will be specified by ModRM:reg. - registerSpecifierPositionModRMFieldReg) - - var dstRexPrefix byte - rm3bits, dstRexPrefix = register3bits(n.dstReg, - // Indicate that dstReg will be specified by ModRM:r/m. - registerSpecifierPositionModRMFieldRM) - rexPrefix |= dstRexPrefix - } else { - rm3bits, rexPrefix = register3bits(n.srcReg, - // Indicate that srcReg will be specified by ModRM:r/m. - registerSpecifierPositionModRMFieldRM) - - var dstRexPrefix byte - reg3bits, dstRexPrefix = register3bits(n.dstReg, - // Indicate that dstReg will be specified by ModRM:reg. - registerSpecifierPositionModRMFieldReg) - rexPrefix |= dstRexPrefix - } - - // https://wiki.osdev.org/X86-64_Instruction_Encoding#ModR.2FM - modRM = 0b11_000_000 | // Specifying that dst operand is register. - (reg3bits << 3) | - rm3bits - - return -} - -// RexPrefix represents REX prefix https://wiki.osdev.org/X86-64_Instruction_Encoding#REX_prefix -type rexPrefix = byte - -// REX prefixes are independent of each other and can be combined with OR. -const ( - rexPrefixNone rexPrefix = 0x0000_0000 // Indicates that the instruction doesn't need RexPrefix. - rexPrefixDefault rexPrefix = 0b0100_0000 - rexPrefixW = 0b0000_1000 | rexPrefixDefault // REX.W - rexPrefixR = 0b0000_0100 | rexPrefixDefault // REX.R - rexPrefixX = 0b0000_0010 | rexPrefixDefault // REX.X - rexPrefixB = 0b0000_0001 | rexPrefixDefault // REX.B -) - -// lockPrefix represents the LOCK prefix https://wiki.osdev.org/X86-64_Instruction_Encoding#Legacy_Prefixes -const lockPrefix = 0xF0 - -// registerSpecifierPosition represents the position in the instruction bytes where an operand register is placed. -type registerSpecifierPosition byte - -const ( - registerSpecifierPositionModRMFieldReg registerSpecifierPosition = iota - registerSpecifierPositionModRMFieldRM - registerSpecifierPositionSIBIndex -) - -var regInfo = [...]struct { - bits byte - needRex bool -}{ - RegAX: {bits: 0b000}, - RegCX: {bits: 0b001}, - RegDX: {bits: 0b010}, - RegBX: {bits: 0b011}, - RegSP: {bits: 0b100}, - RegBP: {bits: 0b101}, - RegSI: {bits: 0b110}, - RegDI: {bits: 0b111}, - RegR8: {bits: 0b000, needRex: true}, - RegR9: {bits: 0b001, needRex: true}, - RegR10: {bits: 0b010, needRex: true}, - RegR11: {bits: 0b011, needRex: true}, - RegR12: {bits: 0b100, needRex: true}, - RegR13: {bits: 0b101, needRex: true}, - RegR14: {bits: 0b110, needRex: true}, - RegR15: {bits: 0b111, needRex: true}, - RegX0: {bits: 0b000}, - RegX1: {bits: 0b001}, - RegX2: {bits: 0b010}, - RegX3: {bits: 0b011}, - RegX4: {bits: 0b100}, - RegX5: {bits: 0b101}, - RegX6: {bits: 0b110}, - RegX7: {bits: 0b111}, - RegX8: {bits: 0b000, needRex: true}, - RegX9: {bits: 0b001, needRex: true}, - RegX10: {bits: 0b010, needRex: true}, - RegX11: {bits: 0b011, needRex: true}, - RegX12: {bits: 0b100, needRex: true}, - RegX13: {bits: 0b101, needRex: true}, - RegX14: {bits: 0b110, needRex: true}, - RegX15: {bits: 0b111, needRex: true}, -} - -func register3bits( - reg asm.Register, - registerSpecifierPosition registerSpecifierPosition, -) (bits byte, prefix rexPrefix) { - info := regInfo[reg] - bits = info.bits - if info.needRex { - // https://wiki.osdev.org/X86-64_Instruction_Encoding#REX_prefix - switch registerSpecifierPosition { - case registerSpecifierPositionModRMFieldReg: - prefix = rexPrefixR - case registerSpecifierPositionModRMFieldRM: - prefix = rexPrefixB - case registerSpecifierPositionSIBIndex: - prefix = rexPrefixX - } - } - return -} - -func fitIn32bit(v int64) bool { - return math.MinInt32 <= v && v <= math.MaxUint32 -} - -func fitInSigned8bit(v int64) bool { - return math.MinInt8 <= v && v <= math.MaxInt8 -} - -func isVectorRegister(r asm.Register) bool { - return RegX0 <= r && r <= RegX15 -} diff --git a/internal/asm/amd64/impl_1_test.go b/internal/asm/amd64/impl_1_test.go deleted file mode 100644 index 162b08a2f2..0000000000 --- a/internal/asm/amd64/impl_1_test.go +++ /dev/null @@ -1,1751 +0,0 @@ -package amd64 - -import ( - "strconv" - "testing" - - "github.com/tetratelabs/wazero/internal/asm" - "github.com/tetratelabs/wazero/internal/testing/require" -) - -func TestNodePool_allocNode(t *testing.T) { - np := nodePool{index: nodePageSize} - - for i := 0; i < nodePageSize; i++ { - n := np.allocNode() - require.Equal(t, &np.pages[0][i], n) - require.Equal(t, i+1, np.index) - require.Equal(t, 1, len(np.pages)) - } - require.Equal(t, nodePageSize, np.index) - - // Reached the next page. - secondPageBegin := np.allocNode() - require.Equal(t, 1, np.index) - require.Equal(t, 2, len(np.pages)) - require.Equal(t, &np.pages[1][0], secondPageBegin) -} - -func TestAssemblerImpl_Reset(t *testing.T) { - // Existing values. - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - buf := code.NextCodeSection() - buf.AppendBytes([]byte{0, 0, 0, 0, 0}) - - staticConsts := asm.NewStaticConstPool() - staticConsts.AddConst(asm.NewStaticConst(nil), 1234) - readInstructionAddressNodes := make([]*nodeImpl, 5) - ba := asm.BaseAssemblerImpl{ - SetBranchTargetOnNextNodes: make([]asm.Node, 5), - JumpTableEntries: make([]asm.JumpTableEntry, 10), - } - - // Create assembler and reset. - a := &AssemblerImpl{ - nodePool: nodePool{ - pages: []*nodePage{new(nodePage), new(nodePage)}, - index: 12, - }, - pool: staticConsts, - readInstructionAddressNodes: readInstructionAddressNodes, - BaseAssemblerImpl: ba, - } - a.Reset() - buf.Reset() - - // Check each field. - require.Equal(t, 65536, buf.Cap()) - require.Equal(t, 0, buf.Len()) - - require.Zero(t, len(a.nodePool.pages)) - require.Equal(t, nodePageSize, a.nodePool.index) - - require.NotEqual(t, staticConsts, a.pool) - - require.Equal(t, 0, len(a.readInstructionAddressNodes)) - require.Equal(t, cap(readInstructionAddressNodes), cap(a.readInstructionAddressNodes)) - - require.Equal(t, 0, len(a.SetBranchTargetOnNextNodes)) - require.Equal(t, cap(ba.SetBranchTargetOnNextNodes), cap(a.SetBranchTargetOnNextNodes)) - - require.Equal(t, 0, len(a.JumpTableEntries)) - require.Equal(t, cap(ba.JumpTableEntries), cap(a.JumpTableEntries)) -} - -func TestNodeImpl_AssignJumpTarget(t *testing.T) { - n := &nodeImpl{} - target := &nodeImpl{} - n.AssignJumpTarget(target) - require.Equal(t, n.jumpTarget, target) -} - -func TestNodeImpl_AssignDestinationConstant(t *testing.T) { - n := &nodeImpl{} - n.AssignDestinationConstant(12345) - require.Equal(t, int64(12345), n.dstConst) -} - -func TestNodeImpl_AssignSourceConstant(t *testing.T) { - n := &nodeImpl{} - n.AssignSourceConstant(12345) - require.Equal(t, int64(12345), n.srcConst) -} - -func TestAssemblerImpl_Assemble(t *testing.T) { - t.Run("no reassemble", func(t *testing.T) { - a := NewAssembler() - - jmp := a.CompileJump(JCC) - const dummyInstruction = CDQ - a.CompileStandAlone(dummyInstruction) - a.CompileStandAlone(dummyInstruction) - a.CompileStandAlone(dummyInstruction) - target := a.CompileStandAlone(dummyInstruction) - jmp.AssignJumpTarget(target) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - buf := code.NextCodeSection() - err := a.Assemble(buf) - require.NoError(t, err) - - actual := buf.Bytes() - require.Equal(t, []byte{0x73, 0x3, 0x99, 0x99, 0x99, 0x99}, actual) - }) - t.Run("re-assemble", func(t *testing.T) { - a := NewAssembler() - jmp := a.CompileJump(JCC) - const dummyInstruction = CDQ - // Ensure that at least 128 bytes between JCC and the target which results in - // reassemble as we have to convert the forward jump as long variant. - for i := 0; i < 128; i++ { - a.CompileStandAlone(dummyInstruction) - } - jmp.AssignJumpTarget(a.CompileStandAlone(dummyInstruction)) - - a.initializeNodesForEncoding() - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // For the first encoding, we must be forced to reassemble. - err := a.encode(code.NextCodeSection()) - require.NoError(t, err) - require.True(t, a.forceReAssemble) - }) -} - -func TestNodeImpl_String(t *testing.T) { - tests := []struct { - in *nodeImpl - exp string - }{ - { - in: &nodeImpl{instruction: NOP}, - exp: "NOP", - }, - { - in: &nodeImpl{instruction: SETCC, types: operandTypesNoneToRegister, dstReg: RegAX}, - exp: "SETCC AX", - }, - { - in: &nodeImpl{instruction: JMP, types: operandTypesNoneToMemory, dstReg: RegAX, dstConst: 100}, - exp: "JMP [AX + 0x64]", - }, - { - in: &nodeImpl{instruction: JMP, types: operandTypesNoneToMemory, dstReg: RegAX, dstConst: 100, dstMemScale: 8, dstMemIndex: RegR11}, - exp: "JMP [AX + 0x64 + R11*0x8]", - }, - { - in: &nodeImpl{instruction: JMP, types: operandTypesNoneToBranch, jumpTarget: &nodeImpl{instruction: JMP, types: operandTypesNoneToMemory, dstReg: RegAX, dstConst: 100}}, - exp: "JMP {JMP [AX + 0x64]}", - }, - { - in: &nodeImpl{instruction: IDIVQ, types: operandTypesRegisterToNone, srcReg: RegDX}, - exp: "IDIVQ DX", - }, - { - in: &nodeImpl{instruction: ADDL, types: operandTypesRegisterToRegister, srcReg: RegDX, dstReg: RegR14}, - exp: "ADDL DX, R14", - }, - { - in: &nodeImpl{ - instruction: MOVQ, types: operandTypesRegisterToMemory, - srcReg: RegDX, dstReg: RegR14, dstConst: 100, - }, - exp: "MOVQ DX, [R14 + 0x64]", - }, - { - in: &nodeImpl{ - instruction: MOVQ, types: operandTypesRegisterToMemory, - srcReg: RegDX, dstReg: RegR14, dstConst: 100, dstMemIndex: RegCX, dstMemScale: 4, - }, - exp: "MOVQ DX, [R14 + 0x64 + CX*0x4]", - }, - { - in: &nodeImpl{ - instruction: CMPL, types: operandTypesRegisterToConst, - srcReg: RegDX, dstConst: 100, - }, - exp: "CMPL DX, 0x64", - }, - { - in: &nodeImpl{ - instruction: MOVL, types: operandTypesMemoryToRegister, - srcReg: RegDX, srcConst: 1, dstReg: RegAX, - }, - exp: "MOVL [DX + 0x1], AX", - }, - { - in: &nodeImpl{ - instruction: MOVL, types: operandTypesMemoryToRegister, - srcReg: RegDX, srcConst: 1, srcMemIndex: RegR12, srcMemScale: 2, - dstReg: RegAX, - }, - exp: "MOVL [DX + 0x1 + R12*0x2], AX", - }, - { - in: &nodeImpl{ - instruction: CMPQ, types: operandTypesMemoryToConst, - srcReg: RegDX, srcConst: 1, srcMemIndex: RegR12, srcMemScale: 2, - dstConst: 123, - }, - exp: "CMPQ [DX + 0x1 + R12*0x2], 0x7b", - }, - { - in: &nodeImpl{instruction: CMPQ, types: operandTypesMemoryToConst, srcReg: RegDX, srcConst: 1, dstConst: 123}, - exp: "CMPQ [DX + 0x1], 0x7b", - }, - { - in: &nodeImpl{instruction: MOVQ, types: operandTypesConstToMemory, srcConst: 123, dstReg: RegAX, dstConst: 100, dstMemScale: 8, dstMemIndex: RegR11}, - exp: "MOVQ 0x7b, [AX + 0x64 + R11*0x8]", - }, - { - in: &nodeImpl{instruction: MOVQ, types: operandTypesConstToMemory, srcConst: 123, dstReg: RegAX, dstConst: 100}, - exp: "MOVQ 0x7b, [AX + 0x64]", - }, - { - in: &nodeImpl{instruction: MOVQ, types: operandTypesConstToRegister, srcConst: 123, dstReg: RegAX}, - exp: "MOVQ 0x7b, AX", - }, - { - in: &nodeImpl{instruction: LEAQ, types: operandTypesStaticConstToRegister, staticConst: &asm.StaticConst{Raw: []byte{0xff, 0x01, 0x2, 0xff}}, dstReg: RegAX}, - exp: "LEAQ $0xff0102ff, AX", - }, - { - in: &nodeImpl{instruction: CMPQ, types: operandTypesRegisterToStaticConst, staticConst: &asm.StaticConst{Raw: []byte{0xff, 0x01, 0x2, 0xff}}, srcReg: RegAX}, - exp: "CMPQ AX, $0xff0102ff", - }, - } - - for _, tt := range tests { - tc := tt - require.Equal(t, tc.exp, tc.in.String()) - } -} - -func TestAssemblerImpl_addNode(t *testing.T) { - a := NewAssembler() - - root := &nodeImpl{} - a.addNode(root) - require.Equal(t, a.root, root) - require.Equal(t, a.current, root) - require.Nil(t, root.next) - - next := &nodeImpl{} - a.addNode(next) - require.Equal(t, a.root, root) - require.Equal(t, a.current, next) - require.Equal(t, next, root.next) - require.Equal(t, next.prev, root) - require.Nil(t, next.next) -} - -func TestAssemblerImpl_newNode(t *testing.T) { - a := NewAssembler() - actual := a.newNode(ADDL, operandTypesConstToMemory) - require.Equal(t, ADDL, actual.instruction) - require.Equal(t, operandTypesConstToMemory, actual.types) - require.Equal(t, actual, a.root) - require.Equal(t, actual, a.current) -} - -func TestAssemblerImpl_encodeNode(t *testing.T) { - a := NewAssembler() - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - buf := code.NextCodeSection() - err := a.encodeNode(buf, &nodeImpl{ - instruction: ADDPD, - types: operandTypesRegisterToMemory, - }) - require.EqualError(t, err, "ADDPD is unsupported for RegisterToMemory type: ADDPD nil, [nil + 0x0]") -} - -func TestAssemblerImpl_padNOP(t *testing.T) { - tests := []struct { - num int - expected []byte - }{ - {num: 1, expected: nopOpcodes[0][:1]}, - {num: 2, expected: nopOpcodes[1][:2]}, - {num: 3, expected: nopOpcodes[2][:3]}, - {num: 4, expected: nopOpcodes[3][:4]}, - {num: 5, expected: nopOpcodes[4][:5]}, - {num: 6, expected: nopOpcodes[5][:6]}, - {num: 7, expected: nopOpcodes[6][:7]}, - {num: 8, expected: nopOpcodes[7][:8]}, - {num: 9, expected: nopOpcodes[8][:9]}, - {num: 10, expected: nopOpcodes[9][:10]}, - {num: 11, expected: nopOpcodes[10][:11]}, - {num: 12, expected: append(nopOpcodes[10][:11], nopOpcodes[0][:1]...)}, - {num: 13, expected: append(nopOpcodes[10][:11], nopOpcodes[1][:2]...)}, - {num: 14, expected: append(nopOpcodes[10][:11], nopOpcodes[2][:3]...)}, - {num: 15, expected: append(nopOpcodes[10][:11], nopOpcodes[3][:4]...)}, - {num: 16, expected: append(nopOpcodes[10][:11], nopOpcodes[4][:5]...)}, - {num: 17, expected: append(nopOpcodes[10][:11], nopOpcodes[5][:6]...)}, - {num: 18, expected: append(nopOpcodes[10][:11], nopOpcodes[6][:7]...)}, - {num: 19, expected: append(nopOpcodes[10][:11], nopOpcodes[7][:8]...)}, - {num: 20, expected: append(nopOpcodes[10][:11], nopOpcodes[8][:9]...)}, - } - - for _, tt := range tests { - tc := tt - t.Run(strconv.Itoa(tc.num), func(t *testing.T) { - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - buf := code.NextCodeSection() - - a := NewAssembler() - a.padNOP(buf, tc.num) - - actual := buf.Bytes() - require.Equal(t, tc.expected, actual) - }) - } -} - -func TestAssemblerImpl_CompileStandAlone(t *testing.T) { - a := NewAssembler() - a.CompileStandAlone(RET) - actualNode := a.current - require.Equal(t, RET, actualNode.instruction) - require.Equal(t, operandTypesNoneToNone, actualNode.types) -} - -func TestAssemblerImpl_CompileConstToRegister(t *testing.T) { - a := NewAssembler() - a.CompileConstToRegister(MOVQ, 1000, RegAX) - actualNode := a.current - require.Equal(t, MOVQ, actualNode.instruction) - require.Equal(t, int64(1000), actualNode.srcConst) - require.Equal(t, RegAX, actualNode.dstReg) - require.Equal(t, operandTypesConstToRegister, actualNode.types) -} - -func TestAssemblerImpl_CompileRegisterToRegister(t *testing.T) { - a := NewAssembler() - a.CompileRegisterToRegister(MOVQ, RegBX, RegAX) - actualNode := a.current - require.Equal(t, MOVQ, actualNode.instruction) - require.Equal(t, RegBX, actualNode.srcReg) - require.Equal(t, RegAX, actualNode.dstReg) - require.Equal(t, operandTypesRegisterToRegister, actualNode.types) -} - -func TestAssemblerImpl_CompileMemoryToRegister(t *testing.T) { - a := NewAssembler() - a.CompileMemoryToRegister(MOVQ, RegBX, 100, RegAX) - actualNode := a.current - require.Equal(t, MOVQ, actualNode.instruction) - require.Equal(t, RegBX, actualNode.srcReg) - require.Equal(t, int64(100), actualNode.srcConst) - require.Equal(t, RegAX, actualNode.dstReg) - require.Equal(t, operandTypesMemoryToRegister, actualNode.types) -} - -func TestAssemblerImpl_CompileRegisterToMemory(t *testing.T) { - a := NewAssembler() - a.CompileRegisterToMemory(MOVQ, RegBX, RegAX, 100) - actualNode := a.current - require.Equal(t, MOVQ, actualNode.instruction) - require.Equal(t, RegBX, actualNode.srcReg) - require.Equal(t, RegAX, actualNode.dstReg) - require.Equal(t, int64(100), actualNode.dstConst) - require.Equal(t, operandTypesRegisterToMemory, actualNode.types) -} - -func TestAssemblerImpl_CompileJump(t *testing.T) { - a := NewAssembler() - a.CompileJump(JMP) - actualNode := a.current - require.Equal(t, JMP, actualNode.instruction) - require.Equal(t, operandTypesNoneToBranch, actualNode.types) -} - -func TestAssemblerImpl_CompileJumpToRegister(t *testing.T) { - a := NewAssembler() - a.CompileJumpToRegister(JNE, RegAX) - actualNode := a.current - require.Equal(t, JNE, actualNode.instruction) - require.Equal(t, RegAX, actualNode.dstReg) - require.Equal(t, operandTypesNoneToRegister, actualNode.types) -} - -func TestAssemblerImpl_CompileJumpToMemory(t *testing.T) { - a := NewAssembler() - a.CompileJumpToMemory(JNE, RegAX, 100) - actualNode := a.current - require.Equal(t, JNE, actualNode.instruction) - require.Equal(t, RegAX, actualNode.dstReg) - require.Equal(t, int64(100), actualNode.dstConst) - require.Equal(t, operandTypesNoneToMemory, actualNode.types) -} - -func TestAssemblerImpl_CompileReadInstructionAddress(t *testing.T) { - a := NewAssembler() - a.CompileReadInstructionAddress(RegR10, RET) - actualNode := a.current - require.Equal(t, LEAQ, actualNode.instruction) - require.Equal(t, RegR10, actualNode.dstReg) - require.Equal(t, operandTypesMemoryToRegister, actualNode.types) - require.Equal(t, RET, actualNode.readInstructionAddressBeforeTargetInstruction) -} - -func TestAssemblerImpl_CompileRegisterToRegisterWithArg(t *testing.T) { - a := NewAssembler() - a.CompileRegisterToRegisterWithArg(MOVQ, RegBX, RegAX, 123) - actualNode := a.current - require.Equal(t, MOVQ, actualNode.instruction) - require.Equal(t, RegBX, actualNode.srcReg) - require.Equal(t, RegAX, actualNode.dstReg) - require.Equal(t, byte(123), actualNode.arg) - require.Equal(t, operandTypesRegisterToRegister, actualNode.types) -} - -func TestAssemblerImpl_CompileMemoryWithIndexToRegister(t *testing.T) { - a := NewAssembler() - a.CompileMemoryWithIndexToRegister(MOVQ, RegBX, 100, RegR10, 8, RegAX) - actualNode := a.current - require.Equal(t, MOVQ, actualNode.instruction) - require.Equal(t, RegBX, actualNode.srcReg) - require.Equal(t, int64(100), actualNode.srcConst) - require.Equal(t, RegR10, actualNode.srcMemIndex) - require.Equal(t, byte(8), actualNode.srcMemScale) - require.Equal(t, RegAX, actualNode.dstReg) - require.Equal(t, operandTypesMemoryToRegister, actualNode.types) -} - -func TestAssemblerImpl_CompileRegisterToConst(t *testing.T) { - a := NewAssembler() - a.CompileRegisterToConst(MOVQ, RegBX, 123) - actualNode := a.current - require.Equal(t, RegBX, actualNode.srcReg) - require.Equal(t, int64(123), actualNode.dstConst) - require.Equal(t, operandTypesRegisterToConst, actualNode.types) -} - -func TestAssemblerImpl_CompileRegisterToNone(t *testing.T) { - a := NewAssembler() - a.CompileRegisterToNone(MOVQ, RegBX) - actualNode := a.current - require.Equal(t, RegBX, actualNode.srcReg) - require.Equal(t, operandTypesRegisterToNone, actualNode.types) -} - -func TestAssemblerImpl_CompileNoneToRegister(t *testing.T) { - a := NewAssembler() - a.CompileNoneToRegister(MOVQ, RegBX) - actualNode := a.current - require.Equal(t, RegBX, actualNode.dstReg) - require.Equal(t, operandTypesNoneToRegister, actualNode.types) -} - -func TestAssemblerImpl_CompileNoneToMemory(t *testing.T) { - a := NewAssembler() - a.CompileNoneToMemory(MOVQ, RegBX, 1234) - actualNode := a.current - require.Equal(t, RegBX, actualNode.dstReg) - require.Equal(t, int64(1234), actualNode.dstConst) - require.Equal(t, operandTypesNoneToMemory, actualNode.types) -} - -func TestAssemblerImpl_CompileConstToMemory(t *testing.T) { - a := NewAssembler() - a.CompileConstToMemory(MOVQ, -9999, RegBX, 1234) - actualNode := a.current - require.Equal(t, RegBX, actualNode.dstReg) - require.Equal(t, int64(-9999), actualNode.srcConst) - require.Equal(t, int64(1234), actualNode.dstConst) - require.Equal(t, operandTypesConstToMemory, actualNode.types) -} - -func TestAssemblerImpl_CompileMemoryToConst(t *testing.T) { - a := NewAssembler() - a.CompileMemoryToConst(MOVQ, RegBX, 1234, -9999) - actualNode := a.current - require.Equal(t, RegBX, actualNode.srcReg) - require.Equal(t, int64(1234), actualNode.srcConst) - require.Equal(t, int64(-9999), actualNode.dstConst) - require.Equal(t, operandTypesMemoryToConst, actualNode.types) -} - -func TestAssemblerImpl_encodeNoneToNone(t *testing.T) { - tests := []struct { - name string - inst asm.Instruction - exp []byte - expErr bool - }{ - {name: "addl", inst: ADDL, expErr: true}, - {name: "cltd", inst: CDQ, exp: []byte{0x99}}, - {name: "cqto", inst: CQO, exp: []byte{0x48, 0x99}}, - {name: "nop", inst: NOP, exp: nil}, - {name: "retq", inst: RET, exp: []byte{0xc3}}, - {name: "rep movsq (%rsi), (%rdi)", inst: REPMOVSQ, exp: []byte{0xf3, 0x48, 0xa5}}, - {name: "rep stosq %rax, (%rdi)", inst: REPSTOSQ, exp: []byte{0xf3, 0x48, 0xab}}, - {name: "std", inst: STD, exp: []byte{0xfd}}, - {name: "cld", inst: CLD, exp: []byte{0xfc}}, - {name: "mfence", inst: MFENCE, exp: []byte{0x0f, 0xae, 0xf0}}, - } - - for _, tt := range tests { - tc := tt - t.Run(tc.name, func(t *testing.T) { - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - a := NewAssembler() - buf := code.NextCodeSection() - err := a.encodeNoneToNone(buf, &nodeImpl{instruction: tc.inst, types: operandTypesNoneToNone}) - if tc.expErr { - require.Error(t, err) - } else { - require.NoError(t, err) - require.Equal(t, tc.exp, buf.Bytes()) - } - }) - } -} - -func TestAssemblerImpl_EncodeMemoryToRegister(t *testing.T) { - tests := []struct { - name string - n *nodeImpl - exp []byte - }{ - {name: "MOVDQU", n: &nodeImpl{instruction: MOVDQU, srcReg: RegAX, dstReg: RegX3, srcConst: 10}, exp: []byte{0xf3, 0xf, 0x6f, 0x58, 0xa}}, - {name: "MOVDQU/2", n: &nodeImpl{instruction: MOVDQU, srcReg: RegR13, dstReg: RegX3, srcConst: 10}, exp: []byte{0xf3, 0x41, 0xf, 0x6f, 0x5d, 0xa}}, - {name: "PINSRB/src=AX/index=R12/scale=1/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x4, 0x20, 0x0}}, - {name: "PINSRB/src=AX/index=R12/scale=1/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x4, 0x20, 0x1}}, - {name: "PINSRB/src=AX/index=R12/scale=1/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x44, 0x20, 0x1, 0x0}}, - {name: "PINSRB/src=AX/index=R12/scale=1/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x44, 0x20, 0x1, 0x1}}, - {name: "PINSRB/src=AX/index=R12/scale=1/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x84, 0x20, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRB/src=AX/index=R12/scale=1/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x84, 0x20, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRB/src=AX/index=AX/scale=1/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0x0, 0x0}}, - {name: "PINSRB/src=AX/index=AX/scale=1/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0x0, 0x1}}, - {name: "PINSRB/src=AX/index=AX/scale=1/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0x0, 0x1, 0x0}}, - {name: "PINSRB/src=AX/index=AX/scale=1/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0x0, 0x1, 0x1}}, - {name: "PINSRB/src=AX/index=AX/scale=1/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0x0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRB/src=AX/index=AX/scale=1/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0x0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRB/src=AX/index=BP/scale=1/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0x28, 0x0}}, - {name: "PINSRB/src=AX/index=BP/scale=1/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0x28, 0x1}}, - {name: "PINSRB/src=AX/index=BP/scale=1/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0x28, 0x1, 0x0}}, - {name: "PINSRB/src=AX/index=BP/scale=1/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0x28, 0x1, 0x1}}, - {name: "PINSRB/src=AX/index=BP/scale=1/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0x28, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRB/src=AX/index=BP/scale=1/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0x28, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRB/src=AX/index=SI/scale=1/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0x30, 0x0}}, - {name: "PINSRB/src=AX/index=SI/scale=1/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0x30, 0x1}}, - {name: "PINSRB/src=AX/index=SI/scale=1/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0x30, 0x1, 0x0}}, - {name: "PINSRB/src=AX/index=SI/scale=1/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0x30, 0x1, 0x1}}, - {name: "PINSRB/src=AX/index=SI/scale=1/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0x30, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRB/src=AX/index=SI/scale=1/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0x30, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRB/src=AX/index=R12/scale=1/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0x2c, 0x20, 0x0}}, - {name: "PINSRB/src=AX/index=R12/scale=1/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0x2c, 0x20, 0x1}}, - {name: "PINSRB/src=AX/index=R12/scale=1/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0x6c, 0x20, 0x1, 0x0}}, - {name: "PINSRB/src=AX/index=R12/scale=1/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0x6c, 0x20, 0x1, 0x1}}, - {name: "PINSRB/src=AX/index=R12/scale=1/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0xac, 0x20, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRB/src=AX/index=R12/scale=1/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0xac, 0x20, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRB/src=AX/index=AX/scale=1/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0x0, 0x0}}, - {name: "PINSRB/src=AX/index=AX/scale=1/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0x0, 0x1}}, - {name: "PINSRB/src=AX/index=AX/scale=1/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0x0, 0x1, 0x0}}, - {name: "PINSRB/src=AX/index=AX/scale=1/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0x0, 0x1, 0x1}}, - {name: "PINSRB/src=AX/index=AX/scale=1/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0x0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRB/src=AX/index=AX/scale=1/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0x0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRB/src=AX/index=BP/scale=1/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0x28, 0x0}}, - {name: "PINSRB/src=AX/index=BP/scale=1/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0x28, 0x1}}, - {name: "PINSRB/src=AX/index=BP/scale=1/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0x28, 0x1, 0x0}}, - {name: "PINSRB/src=AX/index=BP/scale=1/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0x28, 0x1, 0x1}}, - {name: "PINSRB/src=AX/index=BP/scale=1/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0x28, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRB/src=AX/index=BP/scale=1/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0x28, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRB/src=AX/index=SI/scale=1/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0x30, 0x0}}, - {name: "PINSRB/src=AX/index=SI/scale=1/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0x30, 0x1}}, - {name: "PINSRB/src=AX/index=SI/scale=1/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0x30, 0x1, 0x0}}, - {name: "PINSRB/src=AX/index=SI/scale=1/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0x30, 0x1, 0x1}}, - {name: "PINSRB/src=AX/index=SI/scale=1/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0x30, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRB/src=AX/index=SI/scale=1/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0x30, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRB/src=AX/index=R12/scale=2/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x4, 0x60, 0x0}}, - {name: "PINSRB/src=AX/index=R12/scale=2/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x4, 0x60, 0x1}}, - {name: "PINSRB/src=AX/index=R12/scale=2/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x44, 0x60, 0x1, 0x0}}, - {name: "PINSRB/src=AX/index=R12/scale=2/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x44, 0x60, 0x1, 0x1}}, - {name: "PINSRB/src=AX/index=R12/scale=2/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x84, 0x60, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRB/src=AX/index=R12/scale=2/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x84, 0x60, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRB/src=AX/index=AX/scale=2/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0x40, 0x0}}, - {name: "PINSRB/src=AX/index=AX/scale=2/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0x40, 0x1}}, - {name: "PINSRB/src=AX/index=AX/scale=2/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0x40, 0x1, 0x0}}, - {name: "PINSRB/src=AX/index=AX/scale=2/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0x40, 0x1, 0x1}}, - {name: "PINSRB/src=AX/index=AX/scale=2/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0x40, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRB/src=AX/index=AX/scale=2/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0x40, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRB/src=AX/index=BP/scale=2/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0x68, 0x0}}, - {name: "PINSRB/src=AX/index=BP/scale=2/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0x68, 0x1}}, - {name: "PINSRB/src=AX/index=BP/scale=2/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0x68, 0x1, 0x0}}, - {name: "PINSRB/src=AX/index=BP/scale=2/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0x68, 0x1, 0x1}}, - {name: "PINSRB/src=AX/index=BP/scale=2/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0x68, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRB/src=AX/index=BP/scale=2/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0x68, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRB/src=AX/index=SI/scale=2/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0x70, 0x0}}, - {name: "PINSRB/src=AX/index=SI/scale=2/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0x70, 0x1}}, - {name: "PINSRB/src=AX/index=SI/scale=2/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0x70, 0x1, 0x0}}, - {name: "PINSRB/src=AX/index=SI/scale=2/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0x70, 0x1, 0x1}}, - {name: "PINSRB/src=AX/index=SI/scale=2/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0x70, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRB/src=AX/index=SI/scale=2/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0x70, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRB/src=AX/index=R12/scale=2/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0x2c, 0x60, 0x0}}, - {name: "PINSRB/src=AX/index=R12/scale=2/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0x2c, 0x60, 0x1}}, - {name: "PINSRB/src=AX/index=R12/scale=2/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0x6c, 0x60, 0x1, 0x0}}, - {name: "PINSRB/src=AX/index=R12/scale=2/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0x6c, 0x60, 0x1, 0x1}}, - {name: "PINSRB/src=AX/index=R12/scale=2/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0xac, 0x60, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRB/src=AX/index=R12/scale=2/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0xac, 0x60, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRB/src=AX/index=AX/scale=2/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0x40, 0x0}}, - {name: "PINSRB/src=AX/index=AX/scale=2/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0x40, 0x1}}, - {name: "PINSRB/src=AX/index=AX/scale=2/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0x40, 0x1, 0x0}}, - {name: "PINSRB/src=AX/index=AX/scale=2/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0x40, 0x1, 0x1}}, - {name: "PINSRB/src=AX/index=AX/scale=2/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0x40, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRB/src=AX/index=AX/scale=2/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0x40, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRB/src=AX/index=BP/scale=2/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0x68, 0x0}}, - {name: "PINSRB/src=AX/index=BP/scale=2/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0x68, 0x1}}, - {name: "PINSRB/src=AX/index=BP/scale=2/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0x68, 0x1, 0x0}}, - {name: "PINSRB/src=AX/index=BP/scale=2/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0x68, 0x1, 0x1}}, - {name: "PINSRB/src=AX/index=BP/scale=2/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0x68, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRB/src=AX/index=BP/scale=2/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0x68, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRB/src=AX/index=SI/scale=2/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0x70, 0x0}}, - {name: "PINSRB/src=AX/index=SI/scale=2/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0x70, 0x1}}, - {name: "PINSRB/src=AX/index=SI/scale=2/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0x70, 0x1, 0x0}}, - {name: "PINSRB/src=AX/index=SI/scale=2/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0x70, 0x1, 0x1}}, - {name: "PINSRB/src=AX/index=SI/scale=2/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0x70, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRB/src=AX/index=SI/scale=2/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0x70, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRB/src=AX/index=R12/scale=4/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x4, 0xa0, 0x0}}, - {name: "PINSRB/src=AX/index=R12/scale=4/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x4, 0xa0, 0x1}}, - {name: "PINSRB/src=AX/index=R12/scale=4/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x44, 0xa0, 0x1, 0x0}}, - {name: "PINSRB/src=AX/index=R12/scale=4/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x44, 0xa0, 0x1, 0x1}}, - {name: "PINSRB/src=AX/index=R12/scale=4/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x84, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRB/src=AX/index=R12/scale=4/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x84, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRB/src=AX/index=AX/scale=4/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0x80, 0x0}}, - {name: "PINSRB/src=AX/index=AX/scale=4/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0x80, 0x1}}, - {name: "PINSRB/src=AX/index=AX/scale=4/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0x80, 0x1, 0x0}}, - {name: "PINSRB/src=AX/index=AX/scale=4/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0x80, 0x1, 0x1}}, - {name: "PINSRB/src=AX/index=AX/scale=4/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRB/src=AX/index=AX/scale=4/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRB/src=AX/index=BP/scale=4/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0xa8, 0x0}}, - {name: "PINSRB/src=AX/index=BP/scale=4/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0xa8, 0x1}}, - {name: "PINSRB/src=AX/index=BP/scale=4/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0xa8, 0x1, 0x0}}, - {name: "PINSRB/src=AX/index=BP/scale=4/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0xa8, 0x1, 0x1}}, - {name: "PINSRB/src=AX/index=BP/scale=4/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0xa8, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRB/src=AX/index=BP/scale=4/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0xa8, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRB/src=AX/index=SI/scale=4/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0xb0, 0x0}}, - {name: "PINSRB/src=AX/index=SI/scale=4/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0xb0, 0x1}}, - {name: "PINSRB/src=AX/index=SI/scale=4/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0xb0, 0x1, 0x0}}, - {name: "PINSRB/src=AX/index=SI/scale=4/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0xb0, 0x1, 0x1}}, - {name: "PINSRB/src=AX/index=SI/scale=4/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0xb0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRB/src=AX/index=SI/scale=4/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0xb0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRB/src=AX/index=R12/scale=4/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0x2c, 0xa0, 0x0}}, - {name: "PINSRB/src=AX/index=R12/scale=4/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0x2c, 0xa0, 0x1}}, - {name: "PINSRB/src=AX/index=R12/scale=4/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0x6c, 0xa0, 0x1, 0x0}}, - {name: "PINSRB/src=AX/index=R12/scale=4/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0x6c, 0xa0, 0x1, 0x1}}, - {name: "PINSRB/src=AX/index=R12/scale=4/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0xac, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRB/src=AX/index=R12/scale=4/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0xac, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRB/src=AX/index=AX/scale=4/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0x80, 0x0}}, - {name: "PINSRB/src=AX/index=AX/scale=4/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0x80, 0x1}}, - {name: "PINSRB/src=AX/index=AX/scale=4/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0x80, 0x1, 0x0}}, - {name: "PINSRB/src=AX/index=AX/scale=4/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0x80, 0x1, 0x1}}, - {name: "PINSRB/src=AX/index=AX/scale=4/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRB/src=AX/index=AX/scale=4/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRB/src=AX/index=BP/scale=4/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0xa8, 0x0}}, - {name: "PINSRB/src=AX/index=BP/scale=4/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0xa8, 0x1}}, - {name: "PINSRB/src=AX/index=BP/scale=4/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0xa8, 0x1, 0x0}}, - {name: "PINSRB/src=AX/index=BP/scale=4/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0xa8, 0x1, 0x1}}, - {name: "PINSRB/src=AX/index=BP/scale=4/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0xa8, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRB/src=AX/index=BP/scale=4/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0xa8, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRB/src=AX/index=SI/scale=4/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0xb0, 0x0}}, - {name: "PINSRB/src=AX/index=SI/scale=4/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0xb0, 0x1}}, - {name: "PINSRB/src=AX/index=SI/scale=4/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0xb0, 0x1, 0x0}}, - {name: "PINSRB/src=AX/index=SI/scale=4/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0xb0, 0x1, 0x1}}, - {name: "PINSRB/src=AX/index=SI/scale=4/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0xb0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRB/src=AX/index=SI/scale=4/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0xb0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRB/src=AX/index=R12/scale=8/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x4, 0xe0, 0x0}}, - {name: "PINSRB/src=AX/index=R12/scale=8/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x4, 0xe0, 0x1}}, - {name: "PINSRB/src=AX/index=R12/scale=8/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x44, 0xe0, 0x1, 0x0}}, - {name: "PINSRB/src=AX/index=R12/scale=8/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x44, 0xe0, 0x1, 0x1}}, - {name: "PINSRB/src=AX/index=R12/scale=8/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x84, 0xe0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRB/src=AX/index=R12/scale=8/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x84, 0xe0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRB/src=AX/index=AX/scale=8/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0xc0, 0x0}}, - {name: "PINSRB/src=AX/index=AX/scale=8/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0xc0, 0x1}}, - {name: "PINSRB/src=AX/index=AX/scale=8/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0xc0, 0x1, 0x0}}, - {name: "PINSRB/src=AX/index=AX/scale=8/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0xc0, 0x1, 0x1}}, - {name: "PINSRB/src=AX/index=AX/scale=8/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0xc0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRB/src=AX/index=AX/scale=8/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0xc0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRB/src=AX/index=BP/scale=8/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0xe8, 0x0}}, - {name: "PINSRB/src=AX/index=BP/scale=8/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0xe8, 0x1}}, - {name: "PINSRB/src=AX/index=BP/scale=8/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0xe8, 0x1, 0x0}}, - {name: "PINSRB/src=AX/index=BP/scale=8/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0xe8, 0x1, 0x1}}, - {name: "PINSRB/src=AX/index=BP/scale=8/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0xe8, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRB/src=AX/index=BP/scale=8/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0xe8, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRB/src=AX/index=SI/scale=8/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0xf0, 0x0}}, - {name: "PINSRB/src=AX/index=SI/scale=8/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0xf0, 0x1}}, - {name: "PINSRB/src=AX/index=SI/scale=8/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0xf0, 0x1, 0x0}}, - {name: "PINSRB/src=AX/index=SI/scale=8/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0xf0, 0x1, 0x1}}, - {name: "PINSRB/src=AX/index=SI/scale=8/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0xf0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRB/src=AX/index=SI/scale=8/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0xf0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRB/src=AX/index=R12/scale=8/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0x2c, 0xe0, 0x0}}, - {name: "PINSRB/src=AX/index=R12/scale=8/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0x2c, 0xe0, 0x1}}, - {name: "PINSRB/src=AX/index=R12/scale=8/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0x6c, 0xe0, 0x1, 0x0}}, - {name: "PINSRB/src=AX/index=R12/scale=8/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0x6c, 0xe0, 0x1, 0x1}}, - {name: "PINSRB/src=AX/index=R12/scale=8/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0xac, 0xe0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRB/src=AX/index=R12/scale=8/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0xac, 0xe0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRB/src=AX/index=AX/scale=8/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0xc0, 0x0}}, - {name: "PINSRB/src=AX/index=AX/scale=8/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0xc0, 0x1}}, - {name: "PINSRB/src=AX/index=AX/scale=8/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0xc0, 0x1, 0x0}}, - {name: "PINSRB/src=AX/index=AX/scale=8/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0xc0, 0x1, 0x1}}, - {name: "PINSRB/src=AX/index=AX/scale=8/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0xc0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRB/src=AX/index=AX/scale=8/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0xc0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRB/src=AX/index=BP/scale=8/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0xe8, 0x0}}, - {name: "PINSRB/src=AX/index=BP/scale=8/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0xe8, 0x1}}, - {name: "PINSRB/src=AX/index=BP/scale=8/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0xe8, 0x1, 0x0}}, - {name: "PINSRB/src=AX/index=BP/scale=8/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0xe8, 0x1, 0x1}}, - {name: "PINSRB/src=AX/index=BP/scale=8/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0xe8, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRB/src=AX/index=BP/scale=8/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0xe8, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRB/src=AX/index=SI/scale=8/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0xf0, 0x0}}, - {name: "PINSRB/src=AX/index=SI/scale=8/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0xf0, 0x1}}, - {name: "PINSRB/src=AX/index=SI/scale=8/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0xf0, 0x1, 0x0}}, - {name: "PINSRB/src=AX/index=SI/scale=8/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0xf0, 0x1, 0x1}}, - {name: "PINSRB/src=AX/index=SI/scale=8/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0xf0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRB/src=AX/index=SI/scale=8/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0xf0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRW/src=AX/index=R12/scale=1/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x4, 0x20, 0x0}}, - {name: "PINSRW/src=AX/index=R12/scale=1/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x4, 0x20, 0x1}}, - {name: "PINSRW/src=AX/index=R12/scale=1/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x44, 0x20, 0x1, 0x0}}, - {name: "PINSRW/src=AX/index=R12/scale=1/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x44, 0x20, 0x1, 0x1}}, - {name: "PINSRW/src=AX/index=R12/scale=1/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x84, 0x20, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRW/src=AX/index=R12/scale=1/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x84, 0x20, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRW/src=AX/index=AX/scale=1/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0x0, 0x0}}, - {name: "PINSRW/src=AX/index=AX/scale=1/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0x0, 0x1}}, - {name: "PINSRW/src=AX/index=AX/scale=1/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0x0, 0x1, 0x0}}, - {name: "PINSRW/src=AX/index=AX/scale=1/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0x0, 0x1, 0x1}}, - {name: "PINSRW/src=AX/index=AX/scale=1/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0x0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRW/src=AX/index=AX/scale=1/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0x0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRW/src=AX/index=BP/scale=1/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0x28, 0x0}}, - {name: "PINSRW/src=AX/index=BP/scale=1/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0x28, 0x1}}, - {name: "PINSRW/src=AX/index=BP/scale=1/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0x28, 0x1, 0x0}}, - {name: "PINSRW/src=AX/index=BP/scale=1/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0x28, 0x1, 0x1}}, - {name: "PINSRW/src=AX/index=BP/scale=1/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0x28, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRW/src=AX/index=BP/scale=1/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0x28, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRW/src=AX/index=SI/scale=1/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0x30, 0x0}}, - {name: "PINSRW/src=AX/index=SI/scale=1/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0x30, 0x1}}, - {name: "PINSRW/src=AX/index=SI/scale=1/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0x30, 0x1, 0x0}}, - {name: "PINSRW/src=AX/index=SI/scale=1/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0x30, 0x1, 0x1}}, - {name: "PINSRW/src=AX/index=SI/scale=1/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0x30, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRW/src=AX/index=SI/scale=1/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0x30, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRW/src=AX/index=R12/scale=1/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0x2c, 0x20, 0x0}}, - {name: "PINSRW/src=AX/index=R12/scale=1/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0x2c, 0x20, 0x1}}, - {name: "PINSRW/src=AX/index=R12/scale=1/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0x6c, 0x20, 0x1, 0x0}}, - {name: "PINSRW/src=AX/index=R12/scale=1/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0x6c, 0x20, 0x1, 0x1}}, - {name: "PINSRW/src=AX/index=R12/scale=1/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0xac, 0x20, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRW/src=AX/index=R12/scale=1/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0xac, 0x20, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRW/src=AX/index=AX/scale=1/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0x0, 0x0}}, - {name: "PINSRW/src=AX/index=AX/scale=1/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0x0, 0x1}}, - {name: "PINSRW/src=AX/index=AX/scale=1/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0x0, 0x1, 0x0}}, - {name: "PINSRW/src=AX/index=AX/scale=1/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0x0, 0x1, 0x1}}, - {name: "PINSRW/src=AX/index=AX/scale=1/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0x0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRW/src=AX/index=AX/scale=1/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0x0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRW/src=AX/index=BP/scale=1/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0x28, 0x0}}, - {name: "PINSRW/src=AX/index=BP/scale=1/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0x28, 0x1}}, - {name: "PINSRW/src=AX/index=BP/scale=1/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0x28, 0x1, 0x0}}, - {name: "PINSRW/src=AX/index=BP/scale=1/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0x28, 0x1, 0x1}}, - {name: "PINSRW/src=AX/index=BP/scale=1/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0x28, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRW/src=AX/index=BP/scale=1/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0x28, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRW/src=AX/index=SI/scale=1/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0x30, 0x0}}, - {name: "PINSRW/src=AX/index=SI/scale=1/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0x30, 0x1}}, - {name: "PINSRW/src=AX/index=SI/scale=1/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0x30, 0x1, 0x0}}, - {name: "PINSRW/src=AX/index=SI/scale=1/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0x30, 0x1, 0x1}}, - {name: "PINSRW/src=AX/index=SI/scale=1/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0x30, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRW/src=AX/index=SI/scale=1/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0x30, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRW/src=AX/index=R12/scale=2/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x4, 0x60, 0x0}}, - {name: "PINSRW/src=AX/index=R12/scale=2/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x4, 0x60, 0x1}}, - {name: "PINSRW/src=AX/index=R12/scale=2/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x44, 0x60, 0x1, 0x0}}, - {name: "PINSRW/src=AX/index=R12/scale=2/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x44, 0x60, 0x1, 0x1}}, - {name: "PINSRW/src=AX/index=R12/scale=2/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x84, 0x60, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRW/src=AX/index=R12/scale=2/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x84, 0x60, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRW/src=AX/index=AX/scale=2/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0x40, 0x0}}, - {name: "PINSRW/src=AX/index=AX/scale=2/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0x40, 0x1}}, - {name: "PINSRW/src=AX/index=AX/scale=2/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0x40, 0x1, 0x0}}, - {name: "PINSRW/src=AX/index=AX/scale=2/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0x40, 0x1, 0x1}}, - {name: "PINSRW/src=AX/index=AX/scale=2/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0x40, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRW/src=AX/index=AX/scale=2/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0x40, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRW/src=AX/index=BP/scale=2/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0x68, 0x0}}, - {name: "PINSRW/src=AX/index=BP/scale=2/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0x68, 0x1}}, - {name: "PINSRW/src=AX/index=BP/scale=2/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0x68, 0x1, 0x0}}, - {name: "PINSRW/src=AX/index=BP/scale=2/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0x68, 0x1, 0x1}}, - {name: "PINSRW/src=AX/index=BP/scale=2/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0x68, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRW/src=AX/index=BP/scale=2/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0x68, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRW/src=AX/index=SI/scale=2/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0x70, 0x0}}, - {name: "PINSRW/src=AX/index=SI/scale=2/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0x70, 0x1}}, - {name: "PINSRW/src=AX/index=SI/scale=2/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0x70, 0x1, 0x0}}, - {name: "PINSRW/src=AX/index=SI/scale=2/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0x70, 0x1, 0x1}}, - {name: "PINSRW/src=AX/index=SI/scale=2/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0x70, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRW/src=AX/index=SI/scale=2/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0x70, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRW/src=AX/index=R12/scale=2/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0x2c, 0x60, 0x0}}, - {name: "PINSRW/src=AX/index=R12/scale=2/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0x2c, 0x60, 0x1}}, - {name: "PINSRW/src=AX/index=R12/scale=2/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0x6c, 0x60, 0x1, 0x0}}, - {name: "PINSRW/src=AX/index=R12/scale=2/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0x6c, 0x60, 0x1, 0x1}}, - {name: "PINSRW/src=AX/index=R12/scale=2/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0xac, 0x60, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRW/src=AX/index=R12/scale=2/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0xac, 0x60, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRW/src=AX/index=AX/scale=2/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0x40, 0x0}}, - {name: "PINSRW/src=AX/index=AX/scale=2/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0x40, 0x1}}, - {name: "PINSRW/src=AX/index=AX/scale=2/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0x40, 0x1, 0x0}}, - {name: "PINSRW/src=AX/index=AX/scale=2/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0x40, 0x1, 0x1}}, - {name: "PINSRW/src=AX/index=AX/scale=2/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0x40, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRW/src=AX/index=AX/scale=2/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0x40, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRW/src=AX/index=BP/scale=2/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0x68, 0x0}}, - {name: "PINSRW/src=AX/index=BP/scale=2/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0x68, 0x1}}, - {name: "PINSRW/src=AX/index=BP/scale=2/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0x68, 0x1, 0x0}}, - {name: "PINSRW/src=AX/index=BP/scale=2/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0x68, 0x1, 0x1}}, - {name: "PINSRW/src=AX/index=BP/scale=2/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0x68, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRW/src=AX/index=BP/scale=2/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0x68, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRW/src=AX/index=SI/scale=2/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0x70, 0x0}}, - {name: "PINSRW/src=AX/index=SI/scale=2/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0x70, 0x1}}, - {name: "PINSRW/src=AX/index=SI/scale=2/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0x70, 0x1, 0x0}}, - {name: "PINSRW/src=AX/index=SI/scale=2/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0x70, 0x1, 0x1}}, - {name: "PINSRW/src=AX/index=SI/scale=2/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0x70, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRW/src=AX/index=SI/scale=2/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0x70, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRW/src=AX/index=R12/scale=4/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x4, 0xa0, 0x0}}, - {name: "PINSRW/src=AX/index=R12/scale=4/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x4, 0xa0, 0x1}}, - {name: "PINSRW/src=AX/index=R12/scale=4/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x44, 0xa0, 0x1, 0x0}}, - {name: "PINSRW/src=AX/index=R12/scale=4/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x44, 0xa0, 0x1, 0x1}}, - {name: "PINSRW/src=AX/index=R12/scale=4/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x84, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRW/src=AX/index=R12/scale=4/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x84, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRW/src=AX/index=AX/scale=4/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0x80, 0x0}}, - {name: "PINSRW/src=AX/index=AX/scale=4/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0x80, 0x1}}, - {name: "PINSRW/src=AX/index=AX/scale=4/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0x80, 0x1, 0x0}}, - {name: "PINSRW/src=AX/index=AX/scale=4/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0x80, 0x1, 0x1}}, - {name: "PINSRW/src=AX/index=AX/scale=4/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRW/src=AX/index=AX/scale=4/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRW/src=AX/index=BP/scale=4/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0xa8, 0x0}}, - {name: "PINSRW/src=AX/index=BP/scale=4/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0xa8, 0x1}}, - {name: "PINSRW/src=AX/index=BP/scale=4/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0xa8, 0x1, 0x0}}, - {name: "PINSRW/src=AX/index=BP/scale=4/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0xa8, 0x1, 0x1}}, - {name: "PINSRW/src=AX/index=BP/scale=4/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0xa8, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRW/src=AX/index=BP/scale=4/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0xa8, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRW/src=AX/index=SI/scale=4/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0xb0, 0x0}}, - {name: "PINSRW/src=AX/index=SI/scale=4/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0xb0, 0x1}}, - {name: "PINSRW/src=AX/index=SI/scale=4/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0xb0, 0x1, 0x0}}, - {name: "PINSRW/src=AX/index=SI/scale=4/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0xb0, 0x1, 0x1}}, - {name: "PINSRW/src=AX/index=SI/scale=4/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0xb0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRW/src=AX/index=SI/scale=4/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0xb0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRW/src=AX/index=R12/scale=4/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0x2c, 0xa0, 0x0}}, - {name: "PINSRW/src=AX/index=R12/scale=4/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0x2c, 0xa0, 0x1}}, - {name: "PINSRW/src=AX/index=R12/scale=4/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0x6c, 0xa0, 0x1, 0x0}}, - {name: "PINSRW/src=AX/index=R12/scale=4/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0x6c, 0xa0, 0x1, 0x1}}, - {name: "PINSRW/src=AX/index=R12/scale=4/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0xac, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRW/src=AX/index=R12/scale=4/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0xac, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRW/src=AX/index=AX/scale=4/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0x80, 0x0}}, - {name: "PINSRW/src=AX/index=AX/scale=4/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0x80, 0x1}}, - {name: "PINSRW/src=AX/index=AX/scale=4/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0x80, 0x1, 0x0}}, - {name: "PINSRW/src=AX/index=AX/scale=4/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0x80, 0x1, 0x1}}, - {name: "PINSRW/src=AX/index=AX/scale=4/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRW/src=AX/index=AX/scale=4/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRW/src=AX/index=BP/scale=4/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0xa8, 0x0}}, - {name: "PINSRW/src=AX/index=BP/scale=4/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0xa8, 0x1}}, - {name: "PINSRW/src=AX/index=BP/scale=4/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0xa8, 0x1, 0x0}}, - {name: "PINSRW/src=AX/index=BP/scale=4/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0xa8, 0x1, 0x1}}, - {name: "PINSRW/src=AX/index=BP/scale=4/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0xa8, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRW/src=AX/index=BP/scale=4/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0xa8, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRW/src=AX/index=SI/scale=4/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0xb0, 0x0}}, - {name: "PINSRW/src=AX/index=SI/scale=4/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0xb0, 0x1}}, - {name: "PINSRW/src=AX/index=SI/scale=4/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0xb0, 0x1, 0x0}}, - {name: "PINSRW/src=AX/index=SI/scale=4/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0xb0, 0x1, 0x1}}, - {name: "PINSRW/src=AX/index=SI/scale=4/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0xb0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRW/src=AX/index=SI/scale=4/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0xb0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRW/src=AX/index=R12/scale=8/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x4, 0xe0, 0x0}}, - {name: "PINSRW/src=AX/index=R12/scale=8/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x4, 0xe0, 0x1}}, - {name: "PINSRW/src=AX/index=R12/scale=8/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x44, 0xe0, 0x1, 0x0}}, - {name: "PINSRW/src=AX/index=R12/scale=8/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x44, 0xe0, 0x1, 0x1}}, - {name: "PINSRW/src=AX/index=R12/scale=8/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x84, 0xe0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRW/src=AX/index=R12/scale=8/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x84, 0xe0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRW/src=AX/index=AX/scale=8/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0xc0, 0x0}}, - {name: "PINSRW/src=AX/index=AX/scale=8/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0xc0, 0x1}}, - {name: "PINSRW/src=AX/index=AX/scale=8/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0xc0, 0x1, 0x0}}, - {name: "PINSRW/src=AX/index=AX/scale=8/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0xc0, 0x1, 0x1}}, - {name: "PINSRW/src=AX/index=AX/scale=8/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0xc0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRW/src=AX/index=AX/scale=8/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0xc0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRW/src=AX/index=BP/scale=8/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0xe8, 0x0}}, - {name: "PINSRW/src=AX/index=BP/scale=8/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0xe8, 0x1}}, - {name: "PINSRW/src=AX/index=BP/scale=8/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0xe8, 0x1, 0x0}}, - {name: "PINSRW/src=AX/index=BP/scale=8/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0xe8, 0x1, 0x1}}, - {name: "PINSRW/src=AX/index=BP/scale=8/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0xe8, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRW/src=AX/index=BP/scale=8/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0xe8, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRW/src=AX/index=SI/scale=8/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0xf0, 0x0}}, - {name: "PINSRW/src=AX/index=SI/scale=8/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0xf0, 0x1}}, - {name: "PINSRW/src=AX/index=SI/scale=8/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0xf0, 0x1, 0x0}}, - {name: "PINSRW/src=AX/index=SI/scale=8/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0xf0, 0x1, 0x1}}, - {name: "PINSRW/src=AX/index=SI/scale=8/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0xf0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRW/src=AX/index=SI/scale=8/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0xf0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRW/src=AX/index=R12/scale=8/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0x2c, 0xe0, 0x0}}, - {name: "PINSRW/src=AX/index=R12/scale=8/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0x2c, 0xe0, 0x1}}, - {name: "PINSRW/src=AX/index=R12/scale=8/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0x6c, 0xe0, 0x1, 0x0}}, - {name: "PINSRW/src=AX/index=R12/scale=8/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0x6c, 0xe0, 0x1, 0x1}}, - {name: "PINSRW/src=AX/index=R12/scale=8/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0xac, 0xe0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRW/src=AX/index=R12/scale=8/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0xac, 0xe0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRW/src=AX/index=AX/scale=8/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0xc0, 0x0}}, - {name: "PINSRW/src=AX/index=AX/scale=8/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0xc0, 0x1}}, - {name: "PINSRW/src=AX/index=AX/scale=8/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0xc0, 0x1, 0x0}}, - {name: "PINSRW/src=AX/index=AX/scale=8/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0xc0, 0x1, 0x1}}, - {name: "PINSRW/src=AX/index=AX/scale=8/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0xc0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRW/src=AX/index=AX/scale=8/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0xc0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRW/src=AX/index=BP/scale=8/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0xe8, 0x0}}, - {name: "PINSRW/src=AX/index=BP/scale=8/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0xe8, 0x1}}, - {name: "PINSRW/src=AX/index=BP/scale=8/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0xe8, 0x1, 0x0}}, - {name: "PINSRW/src=AX/index=BP/scale=8/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0xe8, 0x1, 0x1}}, - {name: "PINSRW/src=AX/index=BP/scale=8/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0xe8, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRW/src=AX/index=BP/scale=8/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0xe8, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRW/src=AX/index=SI/scale=8/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0xf0, 0x0}}, - {name: "PINSRW/src=AX/index=SI/scale=8/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0xf0, 0x1}}, - {name: "PINSRW/src=AX/index=SI/scale=8/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0xf0, 0x1, 0x0}}, - {name: "PINSRW/src=AX/index=SI/scale=8/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0xf0, 0x1, 0x1}}, - {name: "PINSRW/src=AX/index=SI/scale=8/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0xf0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRW/src=AX/index=SI/scale=8/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0xf0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRD/src=AX/index=R12/scale=1/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x4, 0x20, 0x0}}, - {name: "PINSRD/src=AX/index=R12/scale=1/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x4, 0x20, 0x1}}, - {name: "PINSRD/src=AX/index=R12/scale=1/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x44, 0x20, 0x1, 0x0}}, - {name: "PINSRD/src=AX/index=R12/scale=1/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x44, 0x20, 0x1, 0x1}}, - {name: "PINSRD/src=AX/index=R12/scale=1/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x84, 0x20, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRD/src=AX/index=R12/scale=1/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x84, 0x20, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRD/src=AX/index=AX/scale=1/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0x0, 0x0}}, - {name: "PINSRD/src=AX/index=AX/scale=1/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0x0, 0x1}}, - {name: "PINSRD/src=AX/index=AX/scale=1/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0x0, 0x1, 0x0}}, - {name: "PINSRD/src=AX/index=AX/scale=1/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0x0, 0x1, 0x1}}, - {name: "PINSRD/src=AX/index=AX/scale=1/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0x0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRD/src=AX/index=AX/scale=1/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0x0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRD/src=AX/index=BP/scale=1/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0x28, 0x0}}, - {name: "PINSRD/src=AX/index=BP/scale=1/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0x28, 0x1}}, - {name: "PINSRD/src=AX/index=BP/scale=1/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0x28, 0x1, 0x0}}, - {name: "PINSRD/src=AX/index=BP/scale=1/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0x28, 0x1, 0x1}}, - {name: "PINSRD/src=AX/index=BP/scale=1/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0x28, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRD/src=AX/index=BP/scale=1/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0x28, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRD/src=AX/index=SI/scale=1/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0x30, 0x0}}, - {name: "PINSRD/src=AX/index=SI/scale=1/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0x30, 0x1}}, - {name: "PINSRD/src=AX/index=SI/scale=1/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0x30, 0x1, 0x0}}, - {name: "PINSRD/src=AX/index=SI/scale=1/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0x30, 0x1, 0x1}}, - {name: "PINSRD/src=AX/index=SI/scale=1/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0x30, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRD/src=AX/index=SI/scale=1/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0x30, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRD/src=AX/index=R12/scale=1/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0x2c, 0x20, 0x0}}, - {name: "PINSRD/src=AX/index=R12/scale=1/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0x2c, 0x20, 0x1}}, - {name: "PINSRD/src=AX/index=R12/scale=1/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0x6c, 0x20, 0x1, 0x0}}, - {name: "PINSRD/src=AX/index=R12/scale=1/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0x6c, 0x20, 0x1, 0x1}}, - {name: "PINSRD/src=AX/index=R12/scale=1/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0xac, 0x20, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRD/src=AX/index=R12/scale=1/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0xac, 0x20, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRD/src=AX/index=AX/scale=1/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0x0, 0x0}}, - {name: "PINSRD/src=AX/index=AX/scale=1/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0x0, 0x1}}, - {name: "PINSRD/src=AX/index=AX/scale=1/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0x0, 0x1, 0x0}}, - {name: "PINSRD/src=AX/index=AX/scale=1/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0x0, 0x1, 0x1}}, - {name: "PINSRD/src=AX/index=AX/scale=1/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0x0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRD/src=AX/index=AX/scale=1/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0x0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRD/src=AX/index=BP/scale=1/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0x28, 0x0}}, - {name: "PINSRD/src=AX/index=BP/scale=1/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0x28, 0x1}}, - {name: "PINSRD/src=AX/index=BP/scale=1/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0x28, 0x1, 0x0}}, - {name: "PINSRD/src=AX/index=BP/scale=1/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0x28, 0x1, 0x1}}, - {name: "PINSRD/src=AX/index=BP/scale=1/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0x28, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRD/src=AX/index=BP/scale=1/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0x28, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRD/src=AX/index=SI/scale=1/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0x30, 0x0}}, - {name: "PINSRD/src=AX/index=SI/scale=1/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0x30, 0x1}}, - {name: "PINSRD/src=AX/index=SI/scale=1/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0x30, 0x1, 0x0}}, - {name: "PINSRD/src=AX/index=SI/scale=1/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0x30, 0x1, 0x1}}, - {name: "PINSRD/src=AX/index=SI/scale=1/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0x30, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRD/src=AX/index=SI/scale=1/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0x30, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRD/src=AX/index=R12/scale=2/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x4, 0x60, 0x0}}, - {name: "PINSRD/src=AX/index=R12/scale=2/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x4, 0x60, 0x1}}, - {name: "PINSRD/src=AX/index=R12/scale=2/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x44, 0x60, 0x1, 0x0}}, - {name: "PINSRD/src=AX/index=R12/scale=2/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x44, 0x60, 0x1, 0x1}}, - {name: "PINSRD/src=AX/index=R12/scale=2/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x84, 0x60, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRD/src=AX/index=R12/scale=2/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x84, 0x60, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRD/src=AX/index=AX/scale=2/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0x40, 0x0}}, - {name: "PINSRD/src=AX/index=AX/scale=2/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0x40, 0x1}}, - {name: "PINSRD/src=AX/index=AX/scale=2/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0x40, 0x1, 0x0}}, - {name: "PINSRD/src=AX/index=AX/scale=2/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0x40, 0x1, 0x1}}, - {name: "PINSRD/src=AX/index=AX/scale=2/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0x40, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRD/src=AX/index=AX/scale=2/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0x40, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRD/src=AX/index=BP/scale=2/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0x68, 0x0}}, - {name: "PINSRD/src=AX/index=BP/scale=2/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0x68, 0x1}}, - {name: "PINSRD/src=AX/index=BP/scale=2/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0x68, 0x1, 0x0}}, - {name: "PINSRD/src=AX/index=BP/scale=2/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0x68, 0x1, 0x1}}, - {name: "PINSRD/src=AX/index=BP/scale=2/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0x68, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRD/src=AX/index=BP/scale=2/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0x68, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRD/src=AX/index=SI/scale=2/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0x70, 0x0}}, - {name: "PINSRD/src=AX/index=SI/scale=2/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0x70, 0x1}}, - {name: "PINSRD/src=AX/index=SI/scale=2/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0x70, 0x1, 0x0}}, - {name: "PINSRD/src=AX/index=SI/scale=2/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0x70, 0x1, 0x1}}, - {name: "PINSRD/src=AX/index=SI/scale=2/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0x70, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRD/src=AX/index=SI/scale=2/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0x70, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRD/src=AX/index=R12/scale=2/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0x2c, 0x60, 0x0}}, - {name: "PINSRD/src=AX/index=R12/scale=2/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0x2c, 0x60, 0x1}}, - {name: "PINSRD/src=AX/index=R12/scale=2/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0x6c, 0x60, 0x1, 0x0}}, - {name: "PINSRD/src=AX/index=R12/scale=2/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0x6c, 0x60, 0x1, 0x1}}, - {name: "PINSRD/src=AX/index=R12/scale=2/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0xac, 0x60, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRD/src=AX/index=R12/scale=2/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0xac, 0x60, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRD/src=AX/index=AX/scale=2/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0x40, 0x0}}, - {name: "PINSRD/src=AX/index=AX/scale=2/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0x40, 0x1}}, - {name: "PINSRD/src=AX/index=AX/scale=2/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0x40, 0x1, 0x0}}, - {name: "PINSRD/src=AX/index=AX/scale=2/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0x40, 0x1, 0x1}}, - {name: "PINSRD/src=AX/index=AX/scale=2/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0x40, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRD/src=AX/index=AX/scale=2/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0x40, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRD/src=AX/index=BP/scale=2/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0x68, 0x0}}, - {name: "PINSRD/src=AX/index=BP/scale=2/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0x68, 0x1}}, - {name: "PINSRD/src=AX/index=BP/scale=2/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0x68, 0x1, 0x0}}, - {name: "PINSRD/src=AX/index=BP/scale=2/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0x68, 0x1, 0x1}}, - {name: "PINSRD/src=AX/index=BP/scale=2/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0x68, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRD/src=AX/index=BP/scale=2/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0x68, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRD/src=AX/index=SI/scale=2/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0x70, 0x0}}, - {name: "PINSRD/src=AX/index=SI/scale=2/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0x70, 0x1}}, - {name: "PINSRD/src=AX/index=SI/scale=2/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0x70, 0x1, 0x0}}, - {name: "PINSRD/src=AX/index=SI/scale=2/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0x70, 0x1, 0x1}}, - {name: "PINSRD/src=AX/index=SI/scale=2/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0x70, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRD/src=AX/index=SI/scale=2/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0x70, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRD/src=AX/index=R12/scale=4/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x4, 0xa0, 0x0}}, - {name: "PINSRD/src=AX/index=R12/scale=4/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x4, 0xa0, 0x1}}, - {name: "PINSRD/src=AX/index=R12/scale=4/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x44, 0xa0, 0x1, 0x0}}, - {name: "PINSRD/src=AX/index=R12/scale=4/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x44, 0xa0, 0x1, 0x1}}, - {name: "PINSRD/src=AX/index=R12/scale=4/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x84, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRD/src=AX/index=R12/scale=4/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x84, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRD/src=AX/index=AX/scale=4/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0x80, 0x0}}, - {name: "PINSRD/src=AX/index=AX/scale=4/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0x80, 0x1}}, - {name: "PINSRD/src=AX/index=AX/scale=4/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0x80, 0x1, 0x0}}, - {name: "PINSRD/src=AX/index=AX/scale=4/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0x80, 0x1, 0x1}}, - {name: "PINSRD/src=AX/index=AX/scale=4/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRD/src=AX/index=AX/scale=4/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRD/src=AX/index=BP/scale=4/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0xa8, 0x0}}, - {name: "PINSRD/src=AX/index=BP/scale=4/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0xa8, 0x1}}, - {name: "PINSRD/src=AX/index=BP/scale=4/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0xa8, 0x1, 0x0}}, - {name: "PINSRD/src=AX/index=BP/scale=4/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0xa8, 0x1, 0x1}}, - {name: "PINSRD/src=AX/index=BP/scale=4/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0xa8, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRD/src=AX/index=BP/scale=4/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0xa8, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRD/src=AX/index=SI/scale=4/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0xb0, 0x0}}, - {name: "PINSRD/src=AX/index=SI/scale=4/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0xb0, 0x1}}, - {name: "PINSRD/src=AX/index=SI/scale=4/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0xb0, 0x1, 0x0}}, - {name: "PINSRD/src=AX/index=SI/scale=4/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0xb0, 0x1, 0x1}}, - {name: "PINSRD/src=AX/index=SI/scale=4/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0xb0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRD/src=AX/index=SI/scale=4/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0xb0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRD/src=AX/index=R12/scale=4/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0x2c, 0xa0, 0x0}}, - {name: "PINSRD/src=AX/index=R12/scale=4/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0x2c, 0xa0, 0x1}}, - {name: "PINSRD/src=AX/index=R12/scale=4/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0x6c, 0xa0, 0x1, 0x0}}, - {name: "PINSRD/src=AX/index=R12/scale=4/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0x6c, 0xa0, 0x1, 0x1}}, - {name: "PINSRD/src=AX/index=R12/scale=4/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0xac, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRD/src=AX/index=R12/scale=4/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0xac, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRD/src=AX/index=AX/scale=4/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0x80, 0x0}}, - {name: "PINSRD/src=AX/index=AX/scale=4/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0x80, 0x1}}, - {name: "PINSRD/src=AX/index=AX/scale=4/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0x80, 0x1, 0x0}}, - {name: "PINSRD/src=AX/index=AX/scale=4/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0x80, 0x1, 0x1}}, - {name: "PINSRD/src=AX/index=AX/scale=4/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRD/src=AX/index=AX/scale=4/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRD/src=AX/index=BP/scale=4/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0xa8, 0x0}}, - {name: "PINSRD/src=AX/index=BP/scale=4/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0xa8, 0x1}}, - {name: "PINSRD/src=AX/index=BP/scale=4/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0xa8, 0x1, 0x0}}, - {name: "PINSRD/src=AX/index=BP/scale=4/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0xa8, 0x1, 0x1}}, - {name: "PINSRD/src=AX/index=BP/scale=4/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0xa8, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRD/src=AX/index=BP/scale=4/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0xa8, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRD/src=AX/index=SI/scale=4/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0xb0, 0x0}}, - {name: "PINSRD/src=AX/index=SI/scale=4/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0xb0, 0x1}}, - {name: "PINSRD/src=AX/index=SI/scale=4/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0xb0, 0x1, 0x0}}, - {name: "PINSRD/src=AX/index=SI/scale=4/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0xb0, 0x1, 0x1}}, - {name: "PINSRD/src=AX/index=SI/scale=4/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0xb0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRD/src=AX/index=SI/scale=4/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0xb0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRD/src=AX/index=R12/scale=8/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x4, 0xe0, 0x0}}, - {name: "PINSRD/src=AX/index=R12/scale=8/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x4, 0xe0, 0x1}}, - {name: "PINSRD/src=AX/index=R12/scale=8/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x44, 0xe0, 0x1, 0x0}}, - {name: "PINSRD/src=AX/index=R12/scale=8/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x44, 0xe0, 0x1, 0x1}}, - {name: "PINSRD/src=AX/index=R12/scale=8/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x84, 0xe0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRD/src=AX/index=R12/scale=8/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x84, 0xe0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRD/src=AX/index=AX/scale=8/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0xc0, 0x0}}, - {name: "PINSRD/src=AX/index=AX/scale=8/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0xc0, 0x1}}, - {name: "PINSRD/src=AX/index=AX/scale=8/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0xc0, 0x1, 0x0}}, - {name: "PINSRD/src=AX/index=AX/scale=8/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0xc0, 0x1, 0x1}}, - {name: "PINSRD/src=AX/index=AX/scale=8/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0xc0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRD/src=AX/index=AX/scale=8/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0xc0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRD/src=AX/index=BP/scale=8/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0xe8, 0x0}}, - {name: "PINSRD/src=AX/index=BP/scale=8/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0xe8, 0x1}}, - {name: "PINSRD/src=AX/index=BP/scale=8/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0xe8, 0x1, 0x0}}, - {name: "PINSRD/src=AX/index=BP/scale=8/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0xe8, 0x1, 0x1}}, - {name: "PINSRD/src=AX/index=BP/scale=8/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0xe8, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRD/src=AX/index=BP/scale=8/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0xe8, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRD/src=AX/index=SI/scale=8/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0xf0, 0x0}}, - {name: "PINSRD/src=AX/index=SI/scale=8/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0xf0, 0x1}}, - {name: "PINSRD/src=AX/index=SI/scale=8/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0xf0, 0x1, 0x0}}, - {name: "PINSRD/src=AX/index=SI/scale=8/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0xf0, 0x1, 0x1}}, - {name: "PINSRD/src=AX/index=SI/scale=8/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0xf0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRD/src=AX/index=SI/scale=8/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0xf0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRD/src=AX/index=R12/scale=8/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0x2c, 0xe0, 0x0}}, - {name: "PINSRD/src=AX/index=R12/scale=8/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0x2c, 0xe0, 0x1}}, - {name: "PINSRD/src=AX/index=R12/scale=8/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0x6c, 0xe0, 0x1, 0x0}}, - {name: "PINSRD/src=AX/index=R12/scale=8/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0x6c, 0xe0, 0x1, 0x1}}, - {name: "PINSRD/src=AX/index=R12/scale=8/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0xac, 0xe0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRD/src=AX/index=R12/scale=8/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0xac, 0xe0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRD/src=AX/index=AX/scale=8/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0xc0, 0x0}}, - {name: "PINSRD/src=AX/index=AX/scale=8/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0xc0, 0x1}}, - {name: "PINSRD/src=AX/index=AX/scale=8/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0xc0, 0x1, 0x0}}, - {name: "PINSRD/src=AX/index=AX/scale=8/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0xc0, 0x1, 0x1}}, - {name: "PINSRD/src=AX/index=AX/scale=8/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0xc0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRD/src=AX/index=AX/scale=8/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0xc0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRD/src=AX/index=BP/scale=8/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0xe8, 0x0}}, - {name: "PINSRD/src=AX/index=BP/scale=8/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0xe8, 0x1}}, - {name: "PINSRD/src=AX/index=BP/scale=8/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0xe8, 0x1, 0x0}}, - {name: "PINSRD/src=AX/index=BP/scale=8/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0xe8, 0x1, 0x1}}, - {name: "PINSRD/src=AX/index=BP/scale=8/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0xe8, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRD/src=AX/index=BP/scale=8/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0xe8, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRD/src=AX/index=SI/scale=8/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0xf0, 0x0}}, - {name: "PINSRD/src=AX/index=SI/scale=8/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0xf0, 0x1}}, - {name: "PINSRD/src=AX/index=SI/scale=8/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0xf0, 0x1, 0x0}}, - {name: "PINSRD/src=AX/index=SI/scale=8/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0xf0, 0x1, 0x1}}, - {name: "PINSRD/src=AX/index=SI/scale=8/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0xf0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRD/src=AX/index=SI/scale=8/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0xf0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRQ/src=AX/index=R12/scale=1/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x4, 0x20, 0x0}}, - {name: "PINSRQ/src=AX/index=R12/scale=1/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x4, 0x20, 0x1}}, - {name: "PINSRQ/src=AX/index=R12/scale=1/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x44, 0x20, 0x1, 0x0}}, - {name: "PINSRQ/src=AX/index=R12/scale=1/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x44, 0x20, 0x1, 0x1}}, - {name: "PINSRQ/src=AX/index=R12/scale=1/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x84, 0x20, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRQ/src=AX/index=R12/scale=1/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x84, 0x20, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRQ/src=AX/index=AX/scale=1/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0x0, 0x0}}, - {name: "PINSRQ/src=AX/index=AX/scale=1/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0x0, 0x1}}, - {name: "PINSRQ/src=AX/index=AX/scale=1/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0x0, 0x1, 0x0}}, - {name: "PINSRQ/src=AX/index=AX/scale=1/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0x0, 0x1, 0x1}}, - {name: "PINSRQ/src=AX/index=AX/scale=1/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0x0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRQ/src=AX/index=AX/scale=1/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0x0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRQ/src=AX/index=BP/scale=1/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0x28, 0x0}}, - {name: "PINSRQ/src=AX/index=BP/scale=1/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0x28, 0x1}}, - {name: "PINSRQ/src=AX/index=BP/scale=1/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0x28, 0x1, 0x0}}, - {name: "PINSRQ/src=AX/index=BP/scale=1/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0x28, 0x1, 0x1}}, - {name: "PINSRQ/src=AX/index=BP/scale=1/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0x28, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRQ/src=AX/index=BP/scale=1/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0x28, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRQ/src=AX/index=SI/scale=1/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0x30, 0x0}}, - {name: "PINSRQ/src=AX/index=SI/scale=1/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0x30, 0x1}}, - {name: "PINSRQ/src=AX/index=SI/scale=1/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0x30, 0x1, 0x0}}, - {name: "PINSRQ/src=AX/index=SI/scale=1/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0x30, 0x1, 0x1}}, - {name: "PINSRQ/src=AX/index=SI/scale=1/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0x30, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRQ/src=AX/index=SI/scale=1/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0x30, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRQ/src=AX/index=R12/scale=1/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0x2c, 0x20, 0x0}}, - {name: "PINSRQ/src=AX/index=R12/scale=1/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0x2c, 0x20, 0x1}}, - {name: "PINSRQ/src=AX/index=R12/scale=1/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0x6c, 0x20, 0x1, 0x0}}, - {name: "PINSRQ/src=AX/index=R12/scale=1/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0x6c, 0x20, 0x1, 0x1}}, - {name: "PINSRQ/src=AX/index=R12/scale=1/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0xac, 0x20, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRQ/src=AX/index=R12/scale=1/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0xac, 0x20, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRQ/src=AX/index=AX/scale=1/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0x0, 0x0}}, - {name: "PINSRQ/src=AX/index=AX/scale=1/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0x0, 0x1}}, - {name: "PINSRQ/src=AX/index=AX/scale=1/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0x0, 0x1, 0x0}}, - {name: "PINSRQ/src=AX/index=AX/scale=1/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0x0, 0x1, 0x1}}, - {name: "PINSRQ/src=AX/index=AX/scale=1/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0x0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRQ/src=AX/index=AX/scale=1/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0x0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRQ/src=AX/index=BP/scale=1/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0x28, 0x0}}, - {name: "PINSRQ/src=AX/index=BP/scale=1/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0x28, 0x1}}, - {name: "PINSRQ/src=AX/index=BP/scale=1/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0x28, 0x1, 0x0}}, - {name: "PINSRQ/src=AX/index=BP/scale=1/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0x28, 0x1, 0x1}}, - {name: "PINSRQ/src=AX/index=BP/scale=1/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0x28, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRQ/src=AX/index=BP/scale=1/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0x28, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRQ/src=AX/index=SI/scale=1/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0x30, 0x0}}, - {name: "PINSRQ/src=AX/index=SI/scale=1/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0x30, 0x1}}, - {name: "PINSRQ/src=AX/index=SI/scale=1/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0x30, 0x1, 0x0}}, - {name: "PINSRQ/src=AX/index=SI/scale=1/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0x30, 0x1, 0x1}}, - {name: "PINSRQ/src=AX/index=SI/scale=1/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0x30, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRQ/src=AX/index=SI/scale=1/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0x30, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRQ/src=AX/index=R12/scale=2/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x4, 0x60, 0x0}}, - {name: "PINSRQ/src=AX/index=R12/scale=2/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x4, 0x60, 0x1}}, - {name: "PINSRQ/src=AX/index=R12/scale=2/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x44, 0x60, 0x1, 0x0}}, - {name: "PINSRQ/src=AX/index=R12/scale=2/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x44, 0x60, 0x1, 0x1}}, - {name: "PINSRQ/src=AX/index=R12/scale=2/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x84, 0x60, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRQ/src=AX/index=R12/scale=2/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x84, 0x60, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRQ/src=AX/index=AX/scale=2/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0x40, 0x0}}, - {name: "PINSRQ/src=AX/index=AX/scale=2/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0x40, 0x1}}, - {name: "PINSRQ/src=AX/index=AX/scale=2/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0x40, 0x1, 0x0}}, - {name: "PINSRQ/src=AX/index=AX/scale=2/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0x40, 0x1, 0x1}}, - {name: "PINSRQ/src=AX/index=AX/scale=2/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0x40, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRQ/src=AX/index=AX/scale=2/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0x40, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRQ/src=AX/index=BP/scale=2/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0x68, 0x0}}, - {name: "PINSRQ/src=AX/index=BP/scale=2/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0x68, 0x1}}, - {name: "PINSRQ/src=AX/index=BP/scale=2/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0x68, 0x1, 0x0}}, - {name: "PINSRQ/src=AX/index=BP/scale=2/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0x68, 0x1, 0x1}}, - {name: "PINSRQ/src=AX/index=BP/scale=2/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0x68, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRQ/src=AX/index=BP/scale=2/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0x68, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRQ/src=AX/index=SI/scale=2/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0x70, 0x0}}, - {name: "PINSRQ/src=AX/index=SI/scale=2/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0x70, 0x1}}, - {name: "PINSRQ/src=AX/index=SI/scale=2/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0x70, 0x1, 0x0}}, - {name: "PINSRQ/src=AX/index=SI/scale=2/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0x70, 0x1, 0x1}}, - {name: "PINSRQ/src=AX/index=SI/scale=2/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0x70, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRQ/src=AX/index=SI/scale=2/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0x70, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRQ/src=AX/index=R12/scale=2/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0x2c, 0x60, 0x0}}, - {name: "PINSRQ/src=AX/index=R12/scale=2/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0x2c, 0x60, 0x1}}, - {name: "PINSRQ/src=AX/index=R12/scale=2/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0x6c, 0x60, 0x1, 0x0}}, - {name: "PINSRQ/src=AX/index=R12/scale=2/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0x6c, 0x60, 0x1, 0x1}}, - {name: "PINSRQ/src=AX/index=R12/scale=2/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0xac, 0x60, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRQ/src=AX/index=R12/scale=2/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0xac, 0x60, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRQ/src=AX/index=AX/scale=2/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0x40, 0x0}}, - {name: "PINSRQ/src=AX/index=AX/scale=2/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0x40, 0x1}}, - {name: "PINSRQ/src=AX/index=AX/scale=2/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0x40, 0x1, 0x0}}, - {name: "PINSRQ/src=AX/index=AX/scale=2/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0x40, 0x1, 0x1}}, - {name: "PINSRQ/src=AX/index=AX/scale=2/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0x40, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRQ/src=AX/index=AX/scale=2/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0x40, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRQ/src=AX/index=BP/scale=2/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0x68, 0x0}}, - {name: "PINSRQ/src=AX/index=BP/scale=2/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0x68, 0x1}}, - {name: "PINSRQ/src=AX/index=BP/scale=2/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0x68, 0x1, 0x0}}, - {name: "PINSRQ/src=AX/index=BP/scale=2/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0x68, 0x1, 0x1}}, - {name: "PINSRQ/src=AX/index=BP/scale=2/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0x68, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRQ/src=AX/index=BP/scale=2/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0x68, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRQ/src=AX/index=SI/scale=2/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0x70, 0x0}}, - {name: "PINSRQ/src=AX/index=SI/scale=2/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0x70, 0x1}}, - {name: "PINSRQ/src=AX/index=SI/scale=2/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0x70, 0x1, 0x0}}, - {name: "PINSRQ/src=AX/index=SI/scale=2/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0x70, 0x1, 0x1}}, - {name: "PINSRQ/src=AX/index=SI/scale=2/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0x70, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRQ/src=AX/index=SI/scale=2/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0x70, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRQ/src=AX/index=R12/scale=4/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x4, 0xa0, 0x0}}, - {name: "PINSRQ/src=AX/index=R12/scale=4/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x4, 0xa0, 0x1}}, - {name: "PINSRQ/src=AX/index=R12/scale=4/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x44, 0xa0, 0x1, 0x0}}, - {name: "PINSRQ/src=AX/index=R12/scale=4/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x44, 0xa0, 0x1, 0x1}}, - {name: "PINSRQ/src=AX/index=R12/scale=4/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x84, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRQ/src=AX/index=R12/scale=4/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x84, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRQ/src=AX/index=AX/scale=4/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0x80, 0x0}}, - {name: "PINSRQ/src=AX/index=AX/scale=4/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0x80, 0x1}}, - {name: "PINSRQ/src=AX/index=AX/scale=4/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0x80, 0x1, 0x0}}, - {name: "PINSRQ/src=AX/index=AX/scale=4/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0x80, 0x1, 0x1}}, - {name: "PINSRQ/src=AX/index=AX/scale=4/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRQ/src=AX/index=AX/scale=4/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRQ/src=AX/index=BP/scale=4/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0xa8, 0x0}}, - {name: "PINSRQ/src=AX/index=BP/scale=4/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0xa8, 0x1}}, - {name: "PINSRQ/src=AX/index=BP/scale=4/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0xa8, 0x1, 0x0}}, - {name: "PINSRQ/src=AX/index=BP/scale=4/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0xa8, 0x1, 0x1}}, - {name: "PINSRQ/src=AX/index=BP/scale=4/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0xa8, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRQ/src=AX/index=BP/scale=4/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0xa8, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRQ/src=AX/index=SI/scale=4/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0xb0, 0x0}}, - {name: "PINSRQ/src=AX/index=SI/scale=4/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0xb0, 0x1}}, - {name: "PINSRQ/src=AX/index=SI/scale=4/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0xb0, 0x1, 0x0}}, - {name: "PINSRQ/src=AX/index=SI/scale=4/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0xb0, 0x1, 0x1}}, - {name: "PINSRQ/src=AX/index=SI/scale=4/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0xb0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRQ/src=AX/index=SI/scale=4/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0xb0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRQ/src=AX/index=R12/scale=4/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0x2c, 0xa0, 0x0}}, - {name: "PINSRQ/src=AX/index=R12/scale=4/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0x2c, 0xa0, 0x1}}, - {name: "PINSRQ/src=AX/index=R12/scale=4/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0x6c, 0xa0, 0x1, 0x0}}, - {name: "PINSRQ/src=AX/index=R12/scale=4/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0x6c, 0xa0, 0x1, 0x1}}, - {name: "PINSRQ/src=AX/index=R12/scale=4/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0xac, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRQ/src=AX/index=R12/scale=4/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0xac, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRQ/src=AX/index=AX/scale=4/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0x80, 0x0}}, - {name: "PINSRQ/src=AX/index=AX/scale=4/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0x80, 0x1}}, - {name: "PINSRQ/src=AX/index=AX/scale=4/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0x80, 0x1, 0x0}}, - {name: "PINSRQ/src=AX/index=AX/scale=4/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0x80, 0x1, 0x1}}, - {name: "PINSRQ/src=AX/index=AX/scale=4/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRQ/src=AX/index=AX/scale=4/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRQ/src=AX/index=BP/scale=4/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0xa8, 0x0}}, - {name: "PINSRQ/src=AX/index=BP/scale=4/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0xa8, 0x1}}, - {name: "PINSRQ/src=AX/index=BP/scale=4/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0xa8, 0x1, 0x0}}, - {name: "PINSRQ/src=AX/index=BP/scale=4/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0xa8, 0x1, 0x1}}, - {name: "PINSRQ/src=AX/index=BP/scale=4/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0xa8, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRQ/src=AX/index=BP/scale=4/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0xa8, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRQ/src=AX/index=SI/scale=4/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0xb0, 0x0}}, - {name: "PINSRQ/src=AX/index=SI/scale=4/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0xb0, 0x1}}, - {name: "PINSRQ/src=AX/index=SI/scale=4/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0xb0, 0x1, 0x0}}, - {name: "PINSRQ/src=AX/index=SI/scale=4/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0xb0, 0x1, 0x1}}, - {name: "PINSRQ/src=AX/index=SI/scale=4/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0xb0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRQ/src=AX/index=SI/scale=4/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0xb0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRQ/src=AX/index=R12/scale=8/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x4, 0xe0, 0x0}}, - {name: "PINSRQ/src=AX/index=R12/scale=8/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x4, 0xe0, 0x1}}, - {name: "PINSRQ/src=AX/index=R12/scale=8/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x44, 0xe0, 0x1, 0x0}}, - {name: "PINSRQ/src=AX/index=R12/scale=8/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x44, 0xe0, 0x1, 0x1}}, - {name: "PINSRQ/src=AX/index=R12/scale=8/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x84, 0xe0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRQ/src=AX/index=R12/scale=8/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x84, 0xe0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRQ/src=AX/index=AX/scale=8/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0xc0, 0x0}}, - {name: "PINSRQ/src=AX/index=AX/scale=8/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0xc0, 0x1}}, - {name: "PINSRQ/src=AX/index=AX/scale=8/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0xc0, 0x1, 0x0}}, - {name: "PINSRQ/src=AX/index=AX/scale=8/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0xc0, 0x1, 0x1}}, - {name: "PINSRQ/src=AX/index=AX/scale=8/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0xc0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRQ/src=AX/index=AX/scale=8/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0xc0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRQ/src=AX/index=BP/scale=8/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0xe8, 0x0}}, - {name: "PINSRQ/src=AX/index=BP/scale=8/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0xe8, 0x1}}, - {name: "PINSRQ/src=AX/index=BP/scale=8/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0xe8, 0x1, 0x0}}, - {name: "PINSRQ/src=AX/index=BP/scale=8/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0xe8, 0x1, 0x1}}, - {name: "PINSRQ/src=AX/index=BP/scale=8/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0xe8, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRQ/src=AX/index=BP/scale=8/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0xe8, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRQ/src=AX/index=SI/scale=8/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0xf0, 0x0}}, - {name: "PINSRQ/src=AX/index=SI/scale=8/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0xf0, 0x1}}, - {name: "PINSRQ/src=AX/index=SI/scale=8/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0xf0, 0x1, 0x0}}, - {name: "PINSRQ/src=AX/index=SI/scale=8/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0xf0, 0x1, 0x1}}, - {name: "PINSRQ/src=AX/index=SI/scale=8/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0xf0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRQ/src=AX/index=SI/scale=8/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0xf0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRQ/src=AX/index=R12/scale=8/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0x2c, 0xe0, 0x0}}, - {name: "PINSRQ/src=AX/index=R12/scale=8/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0x2c, 0xe0, 0x1}}, - {name: "PINSRQ/src=AX/index=R12/scale=8/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0x6c, 0xe0, 0x1, 0x0}}, - {name: "PINSRQ/src=AX/index=R12/scale=8/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0x6c, 0xe0, 0x1, 0x1}}, - {name: "PINSRQ/src=AX/index=R12/scale=8/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0xac, 0xe0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRQ/src=AX/index=R12/scale=8/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0xac, 0xe0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRQ/src=AX/index=AX/scale=8/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0xc0, 0x0}}, - {name: "PINSRQ/src=AX/index=AX/scale=8/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0xc0, 0x1}}, - {name: "PINSRQ/src=AX/index=AX/scale=8/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0xc0, 0x1, 0x0}}, - {name: "PINSRQ/src=AX/index=AX/scale=8/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0xc0, 0x1, 0x1}}, - {name: "PINSRQ/src=AX/index=AX/scale=8/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0xc0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRQ/src=AX/index=AX/scale=8/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0xc0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRQ/src=AX/index=BP/scale=8/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0xe8, 0x0}}, - {name: "PINSRQ/src=AX/index=BP/scale=8/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0xe8, 0x1}}, - {name: "PINSRQ/src=AX/index=BP/scale=8/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0xe8, 0x1, 0x0}}, - {name: "PINSRQ/src=AX/index=BP/scale=8/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0xe8, 0x1, 0x1}}, - {name: "PINSRQ/src=AX/index=BP/scale=8/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0xe8, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRQ/src=AX/index=BP/scale=8/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0xe8, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PINSRQ/src=AX/index=SI/scale=8/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0xf0, 0x0}}, - {name: "PINSRQ/src=AX/index=SI/scale=8/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0xf0, 0x1}}, - {name: "PINSRQ/src=AX/index=SI/scale=8/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0xf0, 0x1, 0x0}}, - {name: "PINSRQ/src=AX/index=SI/scale=8/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0xf0, 0x1, 0x1}}, - {name: "PINSRQ/src=AX/index=SI/scale=8/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0xf0, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PINSRQ/src=AX/index=SI/scale=8/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0xf0, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "ADDL/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: ADDL, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x3, 0x8}}, - {name: "ADDL/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: ADDL, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0x3, 0xc, 0xb0}}, - {name: "ADDL/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: ADDL, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x3, 0x48, 0x1}}, - {name: "ADDL/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: ADDL, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0x3, 0x4c, 0xb0, 0x1}}, - {name: "ADDL/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: ADDL, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x3, 0x88, 0xff, 0xff, 0xff, 0x7f}}, - {name: "ADDL/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: ADDL, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0x3, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "ADDL/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: ADDL, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x41, 0x3, 0xa}}, - {name: "ADDL/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: ADDL, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0x3, 0xc, 0xb2}}, - {name: "ADDL/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: ADDL, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x41, 0x3, 0x4a, 0x1}}, - {name: "ADDL/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: ADDL, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0x3, 0x4c, 0xb2, 0x1}}, - {name: "ADDL/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: ADDL, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x41, 0x3, 0x8a, 0xff, 0xff, 0xff, 0x7f}}, - {name: "ADDL/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: ADDL, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0x3, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, - {name: "ADDQ/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: ADDQ, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x48, 0x3, 0x8}}, - {name: "ADDQ/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: ADDQ, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x3, 0xc, 0xb0}}, - {name: "ADDQ/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: ADDQ, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x48, 0x3, 0x48, 0x1}}, - {name: "ADDQ/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: ADDQ, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x3, 0x4c, 0xb0, 0x1}}, - {name: "ADDQ/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: ADDQ, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x48, 0x3, 0x88, 0xff, 0xff, 0xff, 0x7f}}, - {name: "ADDQ/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: ADDQ, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x3, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "ADDQ/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: ADDQ, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x49, 0x3, 0xa}}, - {name: "ADDQ/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: ADDQ, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x3, 0xc, 0xb2}}, - {name: "ADDQ/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: ADDQ, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x49, 0x3, 0x4a, 0x1}}, - {name: "ADDQ/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: ADDQ, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x3, 0x4c, 0xb2, 0x1}}, - {name: "ADDQ/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: ADDQ, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x49, 0x3, 0x8a, 0xff, 0xff, 0xff, 0x7f}}, - {name: "ADDQ/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: ADDQ, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x3, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPL/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: CMPL, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x39, 0x8}}, - {name: "CMPL/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: CMPL, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0x39, 0xc, 0xb0}}, - {name: "CMPL/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: CMPL, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x39, 0x48, 0x1}}, - {name: "CMPL/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: CMPL, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0x39, 0x4c, 0xb0, 0x1}}, - {name: "CMPL/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: CMPL, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x39, 0x88, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPL/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: CMPL, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0x39, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPL/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: CMPL, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x41, 0x39, 0xa}}, - {name: "CMPL/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: CMPL, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0x39, 0xc, 0xb2}}, - {name: "CMPL/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: CMPL, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x41, 0x39, 0x4a, 0x1}}, - {name: "CMPL/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: CMPL, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0x39, 0x4c, 0xb2, 0x1}}, - {name: "CMPL/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: CMPL, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x41, 0x39, 0x8a, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPL/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: CMPL, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0x39, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPQ/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: CMPQ, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x48, 0x39, 0x8}}, - {name: "CMPQ/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: CMPQ, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x39, 0xc, 0xb0}}, - {name: "CMPQ/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: CMPQ, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x48, 0x39, 0x48, 0x1}}, - {name: "CMPQ/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: CMPQ, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x39, 0x4c, 0xb0, 0x1}}, - {name: "CMPQ/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: CMPQ, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x48, 0x39, 0x88, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPQ/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: CMPQ, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x39, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPQ/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: CMPQ, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x49, 0x39, 0xa}}, - {name: "CMPQ/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: CMPQ, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x39, 0xc, 0xb2}}, - {name: "CMPQ/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: CMPQ, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x49, 0x39, 0x4a, 0x1}}, - {name: "CMPQ/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: CMPQ, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x39, 0x4c, 0xb2, 0x1}}, - {name: "CMPQ/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: CMPQ, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x49, 0x39, 0x8a, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPQ/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: CMPQ, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x39, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, - {name: "LEAQ/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: LEAQ, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x48, 0x8d, 0x8}}, - {name: "LEAQ/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: LEAQ, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x8d, 0xc, 0xb0}}, - {name: "LEAQ/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: LEAQ, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x48, 0x8d, 0x48, 0x1}}, - {name: "LEAQ/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: LEAQ, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x8d, 0x4c, 0xb0, 0x1}}, - {name: "LEAQ/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: LEAQ, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x48, 0x8d, 0x88, 0xff, 0xff, 0xff, 0x7f}}, - {name: "LEAQ/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: LEAQ, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x8d, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "LEAQ/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: LEAQ, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x49, 0x8d, 0xa}}, - {name: "LEAQ/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: LEAQ, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x8d, 0xc, 0xb2}}, - {name: "LEAQ/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: LEAQ, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x49, 0x8d, 0x4a, 0x1}}, - {name: "LEAQ/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: LEAQ, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x8d, 0x4c, 0xb2, 0x1}}, - {name: "LEAQ/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: LEAQ, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x49, 0x8d, 0x8a, 0xff, 0xff, 0xff, 0x7f}}, - {name: "LEAQ/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: LEAQ, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x8d, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVBLSX/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVBLSX, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0xf, 0xbe, 0x8}}, - {name: "MOVBLSX/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBLSX, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0xf, 0xbe, 0xc, 0xb0}}, - {name: "MOVBLSX/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVBLSX, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0xf, 0xbe, 0x48, 0x1}}, - {name: "MOVBLSX/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBLSX, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0xf, 0xbe, 0x4c, 0xb0, 0x1}}, - {name: "MOVBLSX/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVBLSX, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0xf, 0xbe, 0x88, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVBLSX/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBLSX, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0xf, 0xbe, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVBLSX/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVBLSX, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x41, 0xf, 0xbe, 0xa}}, - {name: "MOVBLSX/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBLSX, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0xf, 0xbe, 0xc, 0xb2}}, - {name: "MOVBLSX/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVBLSX, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x41, 0xf, 0xbe, 0x4a, 0x1}}, - {name: "MOVBLSX/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBLSX, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0xf, 0xbe, 0x4c, 0xb2, 0x1}}, - {name: "MOVBLSX/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVBLSX, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x41, 0xf, 0xbe, 0x8a, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVBLSX/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBLSX, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0xf, 0xbe, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVBLZX/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVBLZX, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0xf, 0xb6, 0x8}}, - {name: "MOVBLZX/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBLZX, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0xf, 0xb6, 0xc, 0xb0}}, - {name: "MOVBLZX/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVBLZX, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0xf, 0xb6, 0x48, 0x1}}, - {name: "MOVBLZX/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBLZX, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0xf, 0xb6, 0x4c, 0xb0, 0x1}}, - {name: "MOVBLZX/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVBLZX, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0xf, 0xb6, 0x88, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVBLZX/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBLZX, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0xf, 0xb6, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVBLZX/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVBLZX, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x41, 0xf, 0xb6, 0xa}}, - {name: "MOVBLZX/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBLZX, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0xf, 0xb6, 0xc, 0xb2}}, - {name: "MOVBLZX/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVBLZX, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x41, 0xf, 0xb6, 0x4a, 0x1}}, - {name: "MOVBLZX/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBLZX, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0xf, 0xb6, 0x4c, 0xb2, 0x1}}, - {name: "MOVBLZX/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVBLZX, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x41, 0xf, 0xb6, 0x8a, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVBLZX/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBLZX, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0xf, 0xb6, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVBQSX/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVBQSX, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x48, 0xf, 0xbe, 0x8}}, - {name: "MOVBQSX/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBQSX, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0xf, 0xbe, 0xc, 0xb0}}, - {name: "MOVBQSX/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVBQSX, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x48, 0xf, 0xbe, 0x48, 0x1}}, - {name: "MOVBQSX/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBQSX, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0xf, 0xbe, 0x4c, 0xb0, 0x1}}, - {name: "MOVBQSX/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVBQSX, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x48, 0xf, 0xbe, 0x88, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVBQSX/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBQSX, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0xf, 0xbe, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVBQSX/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVBQSX, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x49, 0xf, 0xbe, 0xa}}, - {name: "MOVBQSX/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBQSX, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0xf, 0xbe, 0xc, 0xb2}}, - {name: "MOVBQSX/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVBQSX, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x49, 0xf, 0xbe, 0x4a, 0x1}}, - {name: "MOVBQSX/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBQSX, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0xf, 0xbe, 0x4c, 0xb2, 0x1}}, - {name: "MOVBQSX/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVBQSX, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x49, 0xf, 0xbe, 0x8a, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVBQSX/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBQSX, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0xf, 0xbe, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVBQZX/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVBQZX, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x48, 0xf, 0xb6, 0x8}}, - {name: "MOVBQZX/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBQZX, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0xf, 0xb6, 0xc, 0xb0}}, - {name: "MOVBQZX/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVBQZX, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x48, 0xf, 0xb6, 0x48, 0x1}}, - {name: "MOVBQZX/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBQZX, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0xf, 0xb6, 0x4c, 0xb0, 0x1}}, - {name: "MOVBQZX/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVBQZX, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x48, 0xf, 0xb6, 0x88, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVBQZX/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBQZX, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0xf, 0xb6, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVBQZX/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVBQZX, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x49, 0xf, 0xb6, 0xa}}, - {name: "MOVBQZX/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBQZX, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0xf, 0xb6, 0xc, 0xb2}}, - {name: "MOVBQZX/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVBQZX, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x49, 0xf, 0xb6, 0x4a, 0x1}}, - {name: "MOVBQZX/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBQZX, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0xf, 0xb6, 0x4c, 0xb2, 0x1}}, - {name: "MOVBQZX/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVBQZX, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x49, 0xf, 0xb6, 0x8a, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVBQZX/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBQZX, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0xf, 0xb6, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVLQSX/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVLQSX, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x48, 0x63, 0x8}}, - {name: "MOVLQSX/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVLQSX, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x63, 0xc, 0xb0}}, - {name: "MOVLQSX/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVLQSX, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x48, 0x63, 0x48, 0x1}}, - {name: "MOVLQSX/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVLQSX, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x63, 0x4c, 0xb0, 0x1}}, - {name: "MOVLQSX/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVLQSX, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x48, 0x63, 0x88, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVLQSX/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVLQSX, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x63, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVLQSX/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVLQSX, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x49, 0x63, 0xa}}, - {name: "MOVLQSX/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVLQSX, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x63, 0xc, 0xb2}}, - {name: "MOVLQSX/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVLQSX, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x49, 0x63, 0x4a, 0x1}}, - {name: "MOVLQSX/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVLQSX, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x63, 0x4c, 0xb2, 0x1}}, - {name: "MOVLQSX/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVLQSX, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x49, 0x63, 0x8a, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVLQSX/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVLQSX, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x63, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVLQZX/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVLQZX, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x8b, 0x8}}, - {name: "MOVLQZX/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVLQZX, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0x8b, 0xc, 0xb0}}, - {name: "MOVLQZX/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVLQZX, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x8b, 0x48, 0x1}}, - {name: "MOVLQZX/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVLQZX, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0x8b, 0x4c, 0xb0, 0x1}}, - {name: "MOVLQZX/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVLQZX, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x8b, 0x88, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVLQZX/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVLQZX, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0x8b, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVLQZX/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVLQZX, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x41, 0x8b, 0xa}}, - {name: "MOVLQZX/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVLQZX, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0x8b, 0xc, 0xb2}}, - {name: "MOVLQZX/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVLQZX, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x41, 0x8b, 0x4a, 0x1}}, - {name: "MOVLQZX/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVLQZX, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0x8b, 0x4c, 0xb2, 0x1}}, - {name: "MOVLQZX/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVLQZX, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x41, 0x8b, 0x8a, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVLQZX/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVLQZX, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0x8b, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVL/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVL, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x8b, 0x8}}, - {name: "MOVL/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVL, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0x8b, 0xc, 0xb0}}, - {name: "MOVL/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVL, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x8b, 0x48, 0x1}}, - {name: "MOVL/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVL, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0x8b, 0x4c, 0xb0, 0x1}}, - {name: "MOVL/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVL, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x8b, 0x88, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVL/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVL, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0x8b, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVL/baseReg=AX/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: MOVL, srcReg: RegAX, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x6e, 0x18}}, - {name: "MOVL/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: MOVL, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x6e, 0x1c, 0xb0}}, - {name: "MOVL/baseReg=AX/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: MOVL, srcReg: RegAX, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x6e, 0x58, 0x1}}, - {name: "MOVL/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: MOVL, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x6e, 0x5c, 0xb0, 0x1}}, - {name: "MOVL/baseReg=AX/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: MOVL, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x6e, 0x98, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVL/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: MOVL, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x6e, 0x9c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVL/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVL, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x41, 0x8b, 0xa}}, - {name: "MOVL/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVL, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0x8b, 0xc, 0xb2}}, - {name: "MOVL/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVL, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x41, 0x8b, 0x4a, 0x1}}, - {name: "MOVL/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVL, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0x8b, 0x4c, 0xb2, 0x1}}, - {name: "MOVL/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVL, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x41, 0x8b, 0x8a, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVL/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVL, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0x8b, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVL/baseReg=R10/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: MOVL, srcReg: RegR10, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x6e, 0x1a}}, - {name: "MOVL/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: MOVL, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x6e, 0x1c, 0xb2}}, - {name: "MOVL/baseReg=R10/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: MOVL, srcReg: RegR10, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x6e, 0x5a, 0x1}}, - {name: "MOVL/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: MOVL, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x6e, 0x5c, 0xb2, 0x1}}, - {name: "MOVL/baseReg=R10/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: MOVL, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x6e, 0x9a, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVL/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: MOVL, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x6e, 0x9c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVQ/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVQ, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x48, 0x8b, 0x8}}, - {name: "MOVQ/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVQ, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x8b, 0xc, 0xb0}}, - {name: "MOVQ/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVQ, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x48, 0x8b, 0x48, 0x1}}, - {name: "MOVQ/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVQ, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x8b, 0x4c, 0xb0, 0x1}}, - {name: "MOVQ/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVQ, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x48, 0x8b, 0x88, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVQ/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVQ, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x8b, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVQ/baseReg=AX/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: MOVQ, srcReg: RegAX, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0xf3, 0xf, 0x7e, 0x18}}, - {name: "MOVQ/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: MOVQ, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf3, 0x42, 0xf, 0x7e, 0x1c, 0xb0}}, - {name: "MOVQ/baseReg=AX/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: MOVQ, srcReg: RegAX, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0xf3, 0xf, 0x7e, 0x58, 0x1}}, - {name: "MOVQ/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: MOVQ, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf3, 0x42, 0xf, 0x7e, 0x5c, 0xb0, 0x1}}, - {name: "MOVQ/baseReg=AX/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: MOVQ, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0xf3, 0xf, 0x7e, 0x98, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVQ/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: MOVQ, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf3, 0x42, 0xf, 0x7e, 0x9c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVQ/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVQ, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x49, 0x8b, 0xa}}, - {name: "MOVQ/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVQ, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x8b, 0xc, 0xb2}}, - {name: "MOVQ/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVQ, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x49, 0x8b, 0x4a, 0x1}}, - {name: "MOVQ/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVQ, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x8b, 0x4c, 0xb2, 0x1}}, - {name: "MOVQ/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVQ, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x49, 0x8b, 0x8a, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVQ/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVQ, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x8b, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVQ/baseReg=R10/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: MOVQ, srcReg: RegR10, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0xf3, 0x41, 0xf, 0x7e, 0x1a}}, - {name: "MOVQ/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: MOVQ, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf3, 0x43, 0xf, 0x7e, 0x1c, 0xb2}}, - {name: "MOVQ/baseReg=R10/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: MOVQ, srcReg: RegR10, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0xf3, 0x41, 0xf, 0x7e, 0x5a, 0x1}}, - {name: "MOVQ/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: MOVQ, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf3, 0x43, 0xf, 0x7e, 0x5c, 0xb2, 0x1}}, - {name: "MOVQ/baseReg=R10/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: MOVQ, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0xf3, 0x41, 0xf, 0x7e, 0x9a, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVQ/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: MOVQ, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf3, 0x43, 0xf, 0x7e, 0x9c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVWLSX/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVWLSX, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0xf, 0xbf, 0x8}}, - {name: "MOVWLSX/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWLSX, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0xf, 0xbf, 0xc, 0xb0}}, - {name: "MOVWLSX/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVWLSX, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0xf, 0xbf, 0x48, 0x1}}, - {name: "MOVWLSX/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWLSX, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0xf, 0xbf, 0x4c, 0xb0, 0x1}}, - {name: "MOVWLSX/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVWLSX, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0xf, 0xbf, 0x88, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVWLSX/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWLSX, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0xf, 0xbf, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVWLSX/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVWLSX, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x41, 0xf, 0xbf, 0xa}}, - {name: "MOVWLSX/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWLSX, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0xf, 0xbf, 0xc, 0xb2}}, - {name: "MOVWLSX/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVWLSX, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x41, 0xf, 0xbf, 0x4a, 0x1}}, - {name: "MOVWLSX/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWLSX, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0xf, 0xbf, 0x4c, 0xb2, 0x1}}, - {name: "MOVWLSX/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVWLSX, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x41, 0xf, 0xbf, 0x8a, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVWLSX/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWLSX, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0xf, 0xbf, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVWLZX/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVWLZX, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0xf, 0xb7, 0x8}}, - {name: "MOVWLZX/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWLZX, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0xf, 0xb7, 0xc, 0xb0}}, - {name: "MOVWLZX/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVWLZX, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0xf, 0xb7, 0x48, 0x1}}, - {name: "MOVWLZX/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWLZX, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0xf, 0xb7, 0x4c, 0xb0, 0x1}}, - {name: "MOVWLZX/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVWLZX, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0xf, 0xb7, 0x88, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVWLZX/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWLZX, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0xf, 0xb7, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVWLZX/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVWLZX, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x41, 0xf, 0xb7, 0xa}}, - {name: "MOVWLZX/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWLZX, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0xf, 0xb7, 0xc, 0xb2}}, - {name: "MOVWLZX/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVWLZX, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x41, 0xf, 0xb7, 0x4a, 0x1}}, - {name: "MOVWLZX/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWLZX, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0xf, 0xb7, 0x4c, 0xb2, 0x1}}, - {name: "MOVWLZX/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVWLZX, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x41, 0xf, 0xb7, 0x8a, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVWLZX/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWLZX, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0xf, 0xb7, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVWQSX/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVWQSX, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x48, 0xf, 0xbf, 0x8}}, - {name: "MOVWQSX/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWQSX, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0xf, 0xbf, 0xc, 0xb0}}, - {name: "MOVWQSX/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVWQSX, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x48, 0xf, 0xbf, 0x48, 0x1}}, - {name: "MOVWQSX/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWQSX, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0xf, 0xbf, 0x4c, 0xb0, 0x1}}, - {name: "MOVWQSX/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVWQSX, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x48, 0xf, 0xbf, 0x88, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVWQSX/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWQSX, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0xf, 0xbf, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVWQSX/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVWQSX, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x49, 0xf, 0xbf, 0xa}}, - {name: "MOVWQSX/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWQSX, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0xf, 0xbf, 0xc, 0xb2}}, - {name: "MOVWQSX/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVWQSX, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x49, 0xf, 0xbf, 0x4a, 0x1}}, - {name: "MOVWQSX/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWQSX, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0xf, 0xbf, 0x4c, 0xb2, 0x1}}, - {name: "MOVWQSX/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVWQSX, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x49, 0xf, 0xbf, 0x8a, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVWQSX/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWQSX, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0xf, 0xbf, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVWQZX/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVWQZX, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x48, 0xf, 0xb7, 0x8}}, - {name: "MOVWQZX/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWQZX, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0xf, 0xb7, 0xc, 0xb0}}, - {name: "MOVWQZX/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVWQZX, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x48, 0xf, 0xb7, 0x48, 0x1}}, - {name: "MOVWQZX/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWQZX, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0xf, 0xb7, 0x4c, 0xb0, 0x1}}, - {name: "MOVWQZX/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVWQZX, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x48, 0xf, 0xb7, 0x88, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVWQZX/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWQZX, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0xf, 0xb7, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVWQZX/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVWQZX, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x49, 0xf, 0xb7, 0xa}}, - {name: "MOVWQZX/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWQZX, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0xf, 0xb7, 0xc, 0xb2}}, - {name: "MOVWQZX/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVWQZX, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x49, 0xf, 0xb7, 0x4a, 0x1}}, - {name: "MOVWQZX/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWQZX, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0xf, 0xb7, 0x4c, 0xb2, 0x1}}, - {name: "MOVWQZX/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVWQZX, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x49, 0xf, 0xb7, 0x8a, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVWQZX/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWQZX, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0xf, 0xb7, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, - {name: "SUBQ/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: SUBQ, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x48, 0x2b, 0x8}}, - {name: "SUBQ/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: SUBQ, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x2b, 0xc, 0xb0}}, - {name: "SUBQ/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: SUBQ, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x48, 0x2b, 0x48, 0x1}}, - {name: "SUBQ/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: SUBQ, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x2b, 0x4c, 0xb0, 0x1}}, - {name: "SUBQ/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: SUBQ, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x48, 0x2b, 0x88, 0xff, 0xff, 0xff, 0x7f}}, - {name: "SUBQ/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: SUBQ, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x2b, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "SUBQ/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: SUBQ, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x49, 0x2b, 0xa}}, - {name: "SUBQ/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: SUBQ, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x2b, 0xc, 0xb2}}, - {name: "SUBQ/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: SUBQ, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x49, 0x2b, 0x4a, 0x1}}, - {name: "SUBQ/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: SUBQ, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x2b, 0x4c, 0xb2, 0x1}}, - {name: "SUBQ/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: SUBQ, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x49, 0x2b, 0x8a, 0xff, 0xff, 0xff, 0x7f}}, - {name: "SUBQ/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: SUBQ, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x2b, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, - {name: "SUBSD/baseReg=AX/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: SUBSD, srcReg: RegAX, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0xf2, 0xf, 0x5c, 0x18}}, - {name: "SUBSD/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: SUBSD, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf2, 0x42, 0xf, 0x5c, 0x1c, 0xb0}}, - {name: "SUBSD/baseReg=AX/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: SUBSD, srcReg: RegAX, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0xf2, 0xf, 0x5c, 0x58, 0x1}}, - {name: "SUBSD/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: SUBSD, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf2, 0x42, 0xf, 0x5c, 0x5c, 0xb0, 0x1}}, - {name: "SUBSD/baseReg=AX/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: SUBSD, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0xf2, 0xf, 0x5c, 0x98, 0xff, 0xff, 0xff, 0x7f}}, - {name: "SUBSD/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: SUBSD, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf2, 0x42, 0xf, 0x5c, 0x9c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "SUBSD/baseReg=R10/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: SUBSD, srcReg: RegR10, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0xf2, 0x41, 0xf, 0x5c, 0x1a}}, - {name: "SUBSD/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: SUBSD, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf2, 0x43, 0xf, 0x5c, 0x1c, 0xb2}}, - {name: "SUBSD/baseReg=R10/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: SUBSD, srcReg: RegR10, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0xf2, 0x41, 0xf, 0x5c, 0x5a, 0x1}}, - {name: "SUBSD/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: SUBSD, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf2, 0x43, 0xf, 0x5c, 0x5c, 0xb2, 0x1}}, - {name: "SUBSD/baseReg=R10/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: SUBSD, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0xf2, 0x41, 0xf, 0x5c, 0x9a, 0xff, 0xff, 0xff, 0x7f}}, - {name: "SUBSD/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: SUBSD, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf2, 0x43, 0xf, 0x5c, 0x9c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, - {name: "SUBSS/baseReg=AX/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: SUBSS, srcReg: RegAX, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0xf3, 0xf, 0x5c, 0x18}}, - {name: "SUBSS/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: SUBSS, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf3, 0x42, 0xf, 0x5c, 0x1c, 0xb0}}, - {name: "SUBSS/baseReg=AX/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: SUBSS, srcReg: RegAX, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0xf3, 0xf, 0x5c, 0x58, 0x1}}, - {name: "SUBSS/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: SUBSS, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf3, 0x42, 0xf, 0x5c, 0x5c, 0xb0, 0x1}}, - {name: "SUBSS/baseReg=AX/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: SUBSS, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0xf3, 0xf, 0x5c, 0x98, 0xff, 0xff, 0xff, 0x7f}}, - {name: "SUBSS/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: SUBSS, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf3, 0x42, 0xf, 0x5c, 0x9c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "SUBSS/baseReg=R10/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: SUBSS, srcReg: RegR10, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0xf3, 0x41, 0xf, 0x5c, 0x1a}}, - {name: "SUBSS/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: SUBSS, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf3, 0x43, 0xf, 0x5c, 0x1c, 0xb2}}, - {name: "SUBSS/baseReg=R10/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: SUBSS, srcReg: RegR10, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0xf3, 0x41, 0xf, 0x5c, 0x5a, 0x1}}, - {name: "SUBSS/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: SUBSS, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf3, 0x43, 0xf, 0x5c, 0x5c, 0xb2, 0x1}}, - {name: "SUBSS/baseReg=R10/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: SUBSS, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0xf3, 0x41, 0xf, 0x5c, 0x9a, 0xff, 0xff, 0xff, 0x7f}}, - {name: "SUBSS/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: SUBSS, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf3, 0x43, 0xf, 0x5c, 0x9c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, - {name: "UCOMISD/baseReg=AX/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: UCOMISD, srcReg: RegAX, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x2e, 0x18}}, - {name: "UCOMISD/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: UCOMISD, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x2e, 0x1c, 0xb0}}, - {name: "UCOMISD/baseReg=AX/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: UCOMISD, srcReg: RegAX, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x2e, 0x58, 0x1}}, - {name: "UCOMISD/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: UCOMISD, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x2e, 0x5c, 0xb0, 0x1}}, - {name: "UCOMISD/baseReg=AX/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: UCOMISD, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x2e, 0x98, 0xff, 0xff, 0xff, 0x7f}}, - {name: "UCOMISD/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: UCOMISD, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x2e, 0x9c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "UCOMISD/baseReg=R10/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: UCOMISD, srcReg: RegR10, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x2e, 0x1a}}, - {name: "UCOMISD/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: UCOMISD, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x2e, 0x1c, 0xb2}}, - {name: "UCOMISD/baseReg=R10/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: UCOMISD, srcReg: RegR10, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x2e, 0x5a, 0x1}}, - {name: "UCOMISD/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: UCOMISD, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x2e, 0x5c, 0xb2, 0x1}}, - {name: "UCOMISD/baseReg=R10/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: UCOMISD, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x2e, 0x9a, 0xff, 0xff, 0xff, 0x7f}}, - {name: "UCOMISD/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: UCOMISD, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x2e, 0x9c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, - {name: "UCOMISS/baseReg=AX/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: UCOMISS, srcReg: RegAX, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0xf, 0x2e, 0x18}}, - {name: "UCOMISS/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: UCOMISS, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x42, 0xf, 0x2e, 0x1c, 0xb0}}, - {name: "UCOMISS/baseReg=AX/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: UCOMISS, srcReg: RegAX, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0xf, 0x2e, 0x58, 0x1}}, - {name: "UCOMISS/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: UCOMISS, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x42, 0xf, 0x2e, 0x5c, 0xb0, 0x1}}, - {name: "UCOMISS/baseReg=AX/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: UCOMISS, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0xf, 0x2e, 0x98, 0xff, 0xff, 0xff, 0x7f}}, - {name: "UCOMISS/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: UCOMISS, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x42, 0xf, 0x2e, 0x9c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "UCOMISS/baseReg=R10/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: UCOMISS, srcReg: RegR10, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0x41, 0xf, 0x2e, 0x1a}}, - {name: "UCOMISS/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: UCOMISS, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x43, 0xf, 0x2e, 0x1c, 0xb2}}, - {name: "UCOMISS/baseReg=R10/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: UCOMISS, srcReg: RegR10, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0x41, 0xf, 0x2e, 0x5a, 0x1}}, - {name: "UCOMISS/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: UCOMISS, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x43, 0xf, 0x2e, 0x5c, 0xb2, 0x1}}, - {name: "UCOMISS/baseReg=R10/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: UCOMISS, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0x41, 0xf, 0x2e, 0x9a, 0xff, 0xff, 0xff, 0x7f}}, - {name: "UCOMISS/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: UCOMISS, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x43, 0xf, 0x2e, 0x9c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, - {name: "PMOVSXBW/baseReg=AX/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: PMOVSXBW, srcReg: RegAX, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x20, 0x18}}, - {name: "PMOVSXBW/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXBW, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x20, 0x1c, 0xb0}}, - {name: "PMOVSXBW/baseReg=AX/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: PMOVSXBW, srcReg: RegAX, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x20, 0x58, 0x1}}, - {name: "PMOVSXBW/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXBW, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x20, 0x5c, 0xb0, 0x1}}, - {name: "PMOVSXBW/baseReg=AX/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: PMOVSXBW, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x20, 0x98, 0xff, 0xff, 0xff, 0x7f}}, - {name: "PMOVSXBW/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXBW, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x20, 0x9c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "PMOVSXBW/baseReg=R10/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: PMOVSXBW, srcReg: RegR10, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x20, 0x1a}}, - {name: "PMOVSXBW/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXBW, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x20, 0x1c, 0xb2}}, - {name: "PMOVSXBW/baseReg=R10/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: PMOVSXBW, srcReg: RegR10, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x20, 0x5a, 0x1}}, - {name: "PMOVSXBW/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXBW, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x20, 0x5c, 0xb2, 0x1}}, - {name: "PMOVSXBW/baseReg=R10/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: PMOVSXBW, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x20, 0x9a, 0xff, 0xff, 0xff, 0x7f}}, - {name: "PMOVSXBW/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXBW, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x20, 0x9c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, - {name: "PMOVSXWD/baseReg=AX/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: PMOVSXWD, srcReg: RegAX, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x23, 0x18}}, - {name: "PMOVSXWD/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXWD, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x23, 0x1c, 0xb0}}, - {name: "PMOVSXWD/baseReg=AX/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: PMOVSXWD, srcReg: RegAX, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x23, 0x58, 0x1}}, - {name: "PMOVSXWD/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXWD, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x23, 0x5c, 0xb0, 0x1}}, - {name: "PMOVSXWD/baseReg=AX/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: PMOVSXWD, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x23, 0x98, 0xff, 0xff, 0xff, 0x7f}}, - {name: "PMOVSXWD/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXWD, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x23, 0x9c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "PMOVSXWD/baseReg=R10/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: PMOVSXWD, srcReg: RegR10, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x23, 0x1a}}, - {name: "PMOVSXWD/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXWD, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x23, 0x1c, 0xb2}}, - {name: "PMOVSXWD/baseReg=R10/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: PMOVSXWD, srcReg: RegR10, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x23, 0x5a, 0x1}}, - {name: "PMOVSXWD/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXWD, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x23, 0x5c, 0xb2, 0x1}}, - {name: "PMOVSXWD/baseReg=R10/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: PMOVSXWD, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x23, 0x9a, 0xff, 0xff, 0xff, 0x7f}}, - {name: "PMOVSXWD/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXWD, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x23, 0x9c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, - {name: "PMOVSXDQ/baseReg=AX/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: PMOVSXDQ, srcReg: RegAX, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x25, 0x18}}, - {name: "PMOVSXDQ/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXDQ, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x25, 0x1c, 0xb0}}, - {name: "PMOVSXDQ/baseReg=AX/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: PMOVSXDQ, srcReg: RegAX, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x25, 0x58, 0x1}}, - {name: "PMOVSXDQ/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXDQ, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x25, 0x5c, 0xb0, 0x1}}, - {name: "PMOVSXDQ/baseReg=AX/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: PMOVSXDQ, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x25, 0x98, 0xff, 0xff, 0xff, 0x7f}}, - {name: "PMOVSXDQ/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXDQ, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x25, 0x9c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "PMOVSXDQ/baseReg=R10/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: PMOVSXDQ, srcReg: RegR10, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x25, 0x1a}}, - {name: "PMOVSXDQ/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXDQ, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x25, 0x1c, 0xb2}}, - {name: "PMOVSXDQ/baseReg=R10/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: PMOVSXDQ, srcReg: RegR10, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x25, 0x5a, 0x1}}, - {name: "PMOVSXDQ/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXDQ, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x25, 0x5c, 0xb2, 0x1}}, - {name: "PMOVSXDQ/baseReg=R10/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: PMOVSXDQ, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x25, 0x9a, 0xff, 0xff, 0xff, 0x7f}}, - {name: "PMOVSXDQ/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXDQ, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x25, 0x9c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, - {name: "PMOVZXBW/baseReg=AX/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: PMOVZXBW, srcReg: RegAX, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x30, 0x18}}, - {name: "PMOVZXBW/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXBW, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x30, 0x1c, 0xb0}}, - {name: "PMOVZXBW/baseReg=AX/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: PMOVZXBW, srcReg: RegAX, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x30, 0x58, 0x1}}, - {name: "PMOVZXBW/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXBW, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x30, 0x5c, 0xb0, 0x1}}, - {name: "PMOVZXBW/baseReg=AX/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: PMOVZXBW, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x30, 0x98, 0xff, 0xff, 0xff, 0x7f}}, - {name: "PMOVZXBW/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXBW, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x30, 0x9c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "PMOVZXBW/baseReg=R10/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: PMOVZXBW, srcReg: RegR10, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x30, 0x1a}}, - {name: "PMOVZXBW/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXBW, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x30, 0x1c, 0xb2}}, - {name: "PMOVZXBW/baseReg=R10/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: PMOVZXBW, srcReg: RegR10, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x30, 0x5a, 0x1}}, - {name: "PMOVZXBW/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXBW, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x30, 0x5c, 0xb2, 0x1}}, - {name: "PMOVZXBW/baseReg=R10/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: PMOVZXBW, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x30, 0x9a, 0xff, 0xff, 0xff, 0x7f}}, - {name: "PMOVZXBW/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXBW, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x30, 0x9c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, - {name: "PMOVZXWD/baseReg=AX/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: PMOVZXWD, srcReg: RegAX, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x33, 0x18}}, - {name: "PMOVZXWD/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXWD, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x33, 0x1c, 0xb0}}, - {name: "PMOVZXWD/baseReg=AX/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: PMOVZXWD, srcReg: RegAX, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x33, 0x58, 0x1}}, - {name: "PMOVZXWD/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXWD, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x33, 0x5c, 0xb0, 0x1}}, - {name: "PMOVZXWD/baseReg=AX/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: PMOVZXWD, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x33, 0x98, 0xff, 0xff, 0xff, 0x7f}}, - {name: "PMOVZXWD/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXWD, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x33, 0x9c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "PMOVZXWD/baseReg=R10/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: PMOVZXWD, srcReg: RegR10, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x33, 0x1a}}, - {name: "PMOVZXWD/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXWD, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x33, 0x1c, 0xb2}}, - {name: "PMOVZXWD/baseReg=R10/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: PMOVZXWD, srcReg: RegR10, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x33, 0x5a, 0x1}}, - {name: "PMOVZXWD/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXWD, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x33, 0x5c, 0xb2, 0x1}}, - {name: "PMOVZXWD/baseReg=R10/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: PMOVZXWD, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x33, 0x9a, 0xff, 0xff, 0xff, 0x7f}}, - {name: "PMOVZXWD/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXWD, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x33, 0x9c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, - {name: "PMOVZXDQ/baseReg=AX/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: PMOVZXDQ, srcReg: RegAX, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x35, 0x18}}, - {name: "PMOVZXDQ/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXDQ, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x35, 0x1c, 0xb0}}, - {name: "PMOVZXDQ/baseReg=AX/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: PMOVZXDQ, srcReg: RegAX, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x35, 0x58, 0x1}}, - {name: "PMOVZXDQ/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXDQ, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x35, 0x5c, 0xb0, 0x1}}, - {name: "PMOVZXDQ/baseReg=AX/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: PMOVZXDQ, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x35, 0x98, 0xff, 0xff, 0xff, 0x7f}}, - {name: "PMOVZXDQ/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXDQ, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x35, 0x9c, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "PMOVZXDQ/baseReg=R10/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: PMOVZXDQ, srcReg: RegR10, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x35, 0x1a}}, - {name: "PMOVZXDQ/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXDQ, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x35, 0x1c, 0xb2}}, - {name: "PMOVZXDQ/baseReg=R10/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: PMOVZXDQ, srcReg: RegR10, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x35, 0x5a, 0x1}}, - {name: "PMOVZXDQ/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXDQ, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x35, 0x5c, 0xb2, 0x1}}, - {name: "PMOVZXDQ/baseReg=R10/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: PMOVZXDQ, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x35, 0x9a, 0xff, 0xff, 0xff, 0x7f}}, - {name: "PMOVZXDQ/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXDQ, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x35, 0x9c, 0xb2, 0xff, 0xff, 0xff, 0x7f}}, - } - - for _, tc := range tests { - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - tc.n.types = operandTypesMemoryToRegister - a := NewAssembler() - buf := code.NextCodeSection() - err := a.encodeMemoryToRegister(buf, tc.n) - require.NoError(t, err, tc.name) - - err = a.Assemble(buf) - require.NoError(t, err, tc.name) - - actual := buf.Bytes() - require.Equal(t, tc.exp, actual, tc.name) - } -} - -func TestAssemblerImpl_EncodeConstToRegister(t *testing.T) { - tests := []struct { - name string - n *nodeImpl - exp []byte - }{ - { - name: "psraw xmm10, 1", - n: &nodeImpl{instruction: PSRAW, types: operandTypesRegisterToRegister, srcConst: 1, dstReg: RegX10}, - exp: []byte{0x66, 0x41, 0xf, 0x71, 0xe2, 0x1}, - }, - { - name: "psraw xmm10, 8", - n: &nodeImpl{instruction: PSRAW, types: operandTypesRegisterToRegister, srcConst: 8, dstReg: RegX10}, - exp: []byte{0x66, 0x41, 0xf, 0x71, 0xe2, 0x8}, - }, - { - name: "psrlw xmm10, 1", - n: &nodeImpl{instruction: PSRLW, types: operandTypesRegisterToRegister, srcConst: 1, dstReg: RegX10}, - exp: []byte{0x66, 0x41, 0xf, 0x71, 0xd2, 0x1}, - }, - { - name: "psrlw xmm10, 8", - n: &nodeImpl{instruction: PSRLW, types: operandTypesRegisterToRegister, srcConst: 8, dstReg: RegX10}, - exp: []byte{0x66, 0x41, 0xf, 0x71, 0xd2, 0x8}, - }, - { - name: "psllw xmm10, 1", - n: &nodeImpl{instruction: PSLLW, types: operandTypesRegisterToRegister, srcConst: 1, dstReg: RegX10}, - exp: []byte{0x66, 0x41, 0xf, 0x71, 0xf2, 0x1}, - }, - { - name: "psllw xmm10, 8", - n: &nodeImpl{instruction: PSLLW, types: operandTypesRegisterToRegister, srcConst: 8, dstReg: RegX10}, - exp: []byte{0x66, 0x41, 0xf, 0x71, 0xf2, 0x8}, - }, - { - name: "psrad xmm10, 0x1f", - n: &nodeImpl{instruction: PSRAD, types: operandTypesRegisterToRegister, srcConst: 0x1f, dstReg: RegX10}, - exp: []byte{0x66, 0x41, 0xf, 0x72, 0xe2, 0x1f}, - }, - } - - for _, tt := range tests { - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - tc := tt - a := NewAssembler() - buf := code.NextCodeSection() - err := a.encodeConstToRegister(buf, tc.n) - require.NoError(t, err, tc.name) - - err = a.Assemble(buf) - require.NoError(t, err, tc.name) - - actual := buf.Bytes() - require.Equal(t, tc.exp, actual, tc.name) - } -} diff --git a/internal/asm/amd64/impl_2_test.go b/internal/asm/amd64/impl_2_test.go deleted file mode 100644 index a1522b294d..0000000000 --- a/internal/asm/amd64/impl_2_test.go +++ /dev/null @@ -1,1308 +0,0 @@ -package amd64 - -import ( - "testing" - - "github.com/tetratelabs/wazero/internal/asm" - "github.com/tetratelabs/wazero/internal/testing/require" -) - -func TestAssemblerImpl_EncodeNoneToRegister(t *testing.T) { - t.Run("error", func(t *testing.T) { - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - a := NewAssembler() - buf := code.NextCodeSection() - err := a.encodeNoneToRegister(buf, &nodeImpl{ - instruction: ADDL, - types: operandTypesNoneToRegister, dstReg: RegAX, - }) - require.Error(t, err) - - t.Run("error", func(t *testing.T) { - tests := []struct { - n *nodeImpl - expErr string - }{ - { - n: &nodeImpl{instruction: ADDL, types: operandTypesNoneToRegister, dstReg: RegAX}, - expErr: "ADDL is unsupported for NoneToRegister type", - }, - } - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - for _, tt := range tests { - a := NewAssembler() - buf := code.NextCodeSection() - err := a.encodeNoneToRegister(buf, tt.n) - require.EqualError(t, err, tt.expErr, tt.expErr) - } - }) - }) - - tests := []struct { - name string - inst asm.Instruction - dst asm.Register - exp []byte - }{ - {name: "inst=JMP/reg=AX", inst: JMP, dst: RegAX, exp: []byte{0xff, 0xe0}}, - {name: "inst=JMP/reg=BX", inst: JMP, dst: RegBX, exp: []byte{0xff, 0xe3}}, - {name: "inst=JMP/reg=SP", inst: JMP, dst: RegSP, exp: []byte{0xff, 0xe4}}, - {name: "inst=JMP/reg=BP", inst: JMP, dst: RegBP, exp: []byte{0xff, 0xe5}}, - {name: "inst=JMP/reg=SI", inst: JMP, dst: RegSI, exp: []byte{0xff, 0xe6}}, - {name: "inst=JMP/reg=DI", inst: JMP, dst: RegDI, exp: []byte{0xff, 0xe7}}, - {name: "inst=JMP/reg=R8", inst: JMP, dst: RegR8, exp: []byte{0x41, 0xff, 0xe0}}, - {name: "inst=JMP/reg=R9", inst: JMP, dst: RegR9, exp: []byte{0x41, 0xff, 0xe1}}, - {name: "inst=JMP/reg=R13", inst: JMP, dst: RegR13, exp: []byte{0x41, 0xff, 0xe5}}, - {name: "inst=JMP/reg=R14", inst: JMP, dst: RegR14, exp: []byte{0x41, 0xff, 0xe6}}, - {name: "inst=JMP/reg=R15", inst: JMP, dst: RegR15, exp: []byte{0x41, 0xff, 0xe7}}, - {name: "inst=SETCC/reg=AX", inst: SETCC, dst: RegAX, exp: []byte{0xf, 0x93, 0xc0}}, - {name: "inst=SETCC/reg=BX", inst: SETCC, dst: RegBX, exp: []byte{0xf, 0x93, 0xc3}}, - {name: "inst=SETCC/reg=SP", inst: SETCC, dst: RegSP, exp: []byte{0x40, 0xf, 0x93, 0xc4}}, - {name: "inst=SETCC/reg=BP", inst: SETCC, dst: RegBP, exp: []byte{0x40, 0xf, 0x93, 0xc5}}, - {name: "inst=SETCC/reg=SI", inst: SETCC, dst: RegSI, exp: []byte{0x40, 0xf, 0x93, 0xc6}}, - {name: "inst=SETCC/reg=DI", inst: SETCC, dst: RegDI, exp: []byte{0x40, 0xf, 0x93, 0xc7}}, - {name: "inst=SETCC/reg=R8", inst: SETCC, dst: RegR8, exp: []byte{0x41, 0xf, 0x93, 0xc0}}, - {name: "inst=SETCC/reg=R9", inst: SETCC, dst: RegR9, exp: []byte{0x41, 0xf, 0x93, 0xc1}}, - {name: "inst=SETCC/reg=R13", inst: SETCC, dst: RegR13, exp: []byte{0x41, 0xf, 0x93, 0xc5}}, - {name: "inst=SETCC/reg=R14", inst: SETCC, dst: RegR14, exp: []byte{0x41, 0xf, 0x93, 0xc6}}, - {name: "inst=SETCC/reg=R15", inst: SETCC, dst: RegR15, exp: []byte{0x41, 0xf, 0x93, 0xc7}}, - {name: "inst=SETCS/reg=AX", inst: SETCS, dst: RegAX, exp: []byte{0xf, 0x92, 0xc0}}, - {name: "inst=SETCS/reg=BX", inst: SETCS, dst: RegBX, exp: []byte{0xf, 0x92, 0xc3}}, - {name: "inst=SETCS/reg=SP", inst: SETCS, dst: RegSP, exp: []byte{0x40, 0xf, 0x92, 0xc4}}, - {name: "inst=SETCS/reg=BP", inst: SETCS, dst: RegBP, exp: []byte{0x40, 0xf, 0x92, 0xc5}}, - {name: "inst=SETCS/reg=SI", inst: SETCS, dst: RegSI, exp: []byte{0x40, 0xf, 0x92, 0xc6}}, - {name: "inst=SETCS/reg=DI", inst: SETCS, dst: RegDI, exp: []byte{0x40, 0xf, 0x92, 0xc7}}, - {name: "inst=SETCS/reg=R8", inst: SETCS, dst: RegR8, exp: []byte{0x41, 0xf, 0x92, 0xc0}}, - {name: "inst=SETCS/reg=R9", inst: SETCS, dst: RegR9, exp: []byte{0x41, 0xf, 0x92, 0xc1}}, - {name: "inst=SETCS/reg=R13", inst: SETCS, dst: RegR13, exp: []byte{0x41, 0xf, 0x92, 0xc5}}, - {name: "inst=SETCS/reg=R14", inst: SETCS, dst: RegR14, exp: []byte{0x41, 0xf, 0x92, 0xc6}}, - {name: "inst=SETCS/reg=R15", inst: SETCS, dst: RegR15, exp: []byte{0x41, 0xf, 0x92, 0xc7}}, - {name: "inst=SETEQ/reg=AX", inst: SETEQ, dst: RegAX, exp: []byte{0xf, 0x94, 0xc0}}, - {name: "inst=SETEQ/reg=BX", inst: SETEQ, dst: RegBX, exp: []byte{0xf, 0x94, 0xc3}}, - {name: "inst=SETEQ/reg=SP", inst: SETEQ, dst: RegSP, exp: []byte{0x40, 0xf, 0x94, 0xc4}}, - {name: "inst=SETEQ/reg=BP", inst: SETEQ, dst: RegBP, exp: []byte{0x40, 0xf, 0x94, 0xc5}}, - {name: "inst=SETEQ/reg=SI", inst: SETEQ, dst: RegSI, exp: []byte{0x40, 0xf, 0x94, 0xc6}}, - {name: "inst=SETEQ/reg=DI", inst: SETEQ, dst: RegDI, exp: []byte{0x40, 0xf, 0x94, 0xc7}}, - {name: "inst=SETEQ/reg=R8", inst: SETEQ, dst: RegR8, exp: []byte{0x41, 0xf, 0x94, 0xc0}}, - {name: "inst=SETEQ/reg=R9", inst: SETEQ, dst: RegR9, exp: []byte{0x41, 0xf, 0x94, 0xc1}}, - {name: "inst=SETEQ/reg=R13", inst: SETEQ, dst: RegR13, exp: []byte{0x41, 0xf, 0x94, 0xc5}}, - {name: "inst=SETEQ/reg=R14", inst: SETEQ, dst: RegR14, exp: []byte{0x41, 0xf, 0x94, 0xc6}}, - {name: "inst=SETEQ/reg=R15", inst: SETEQ, dst: RegR15, exp: []byte{0x41, 0xf, 0x94, 0xc7}}, - {name: "inst=SETGE/reg=AX", inst: SETGE, dst: RegAX, exp: []byte{0xf, 0x9d, 0xc0}}, - {name: "inst=SETGE/reg=BX", inst: SETGE, dst: RegBX, exp: []byte{0xf, 0x9d, 0xc3}}, - {name: "inst=SETGE/reg=SP", inst: SETGE, dst: RegSP, exp: []byte{0x40, 0xf, 0x9d, 0xc4}}, - {name: "inst=SETGE/reg=BP", inst: SETGE, dst: RegBP, exp: []byte{0x40, 0xf, 0x9d, 0xc5}}, - {name: "inst=SETGE/reg=SI", inst: SETGE, dst: RegSI, exp: []byte{0x40, 0xf, 0x9d, 0xc6}}, - {name: "inst=SETGE/reg=DI", inst: SETGE, dst: RegDI, exp: []byte{0x40, 0xf, 0x9d, 0xc7}}, - {name: "inst=SETGE/reg=R8", inst: SETGE, dst: RegR8, exp: []byte{0x41, 0xf, 0x9d, 0xc0}}, - {name: "inst=SETGE/reg=R9", inst: SETGE, dst: RegR9, exp: []byte{0x41, 0xf, 0x9d, 0xc1}}, - {name: "inst=SETGE/reg=R13", inst: SETGE, dst: RegR13, exp: []byte{0x41, 0xf, 0x9d, 0xc5}}, - {name: "inst=SETGE/reg=R14", inst: SETGE, dst: RegR14, exp: []byte{0x41, 0xf, 0x9d, 0xc6}}, - {name: "inst=SETGE/reg=R15", inst: SETGE, dst: RegR15, exp: []byte{0x41, 0xf, 0x9d, 0xc7}}, - {name: "inst=SETGT/reg=AX", inst: SETGT, dst: RegAX, exp: []byte{0xf, 0x9f, 0xc0}}, - {name: "inst=SETGT/reg=BX", inst: SETGT, dst: RegBX, exp: []byte{0xf, 0x9f, 0xc3}}, - {name: "inst=SETGT/reg=SP", inst: SETGT, dst: RegSP, exp: []byte{0x40, 0xf, 0x9f, 0xc4}}, - {name: "inst=SETGT/reg=BP", inst: SETGT, dst: RegBP, exp: []byte{0x40, 0xf, 0x9f, 0xc5}}, - {name: "inst=SETGT/reg=SI", inst: SETGT, dst: RegSI, exp: []byte{0x40, 0xf, 0x9f, 0xc6}}, - {name: "inst=SETGT/reg=DI", inst: SETGT, dst: RegDI, exp: []byte{0x40, 0xf, 0x9f, 0xc7}}, - {name: "inst=SETGT/reg=R8", inst: SETGT, dst: RegR8, exp: []byte{0x41, 0xf, 0x9f, 0xc0}}, - {name: "inst=SETGT/reg=R9", inst: SETGT, dst: RegR9, exp: []byte{0x41, 0xf, 0x9f, 0xc1}}, - {name: "inst=SETGT/reg=R13", inst: SETGT, dst: RegR13, exp: []byte{0x41, 0xf, 0x9f, 0xc5}}, - {name: "inst=SETGT/reg=R14", inst: SETGT, dst: RegR14, exp: []byte{0x41, 0xf, 0x9f, 0xc6}}, - {name: "inst=SETGT/reg=R15", inst: SETGT, dst: RegR15, exp: []byte{0x41, 0xf, 0x9f, 0xc7}}, - {name: "inst=SETHI/reg=AX", inst: SETHI, dst: RegAX, exp: []byte{0xf, 0x97, 0xc0}}, - {name: "inst=SETHI/reg=BX", inst: SETHI, dst: RegBX, exp: []byte{0xf, 0x97, 0xc3}}, - {name: "inst=SETHI/reg=SP", inst: SETHI, dst: RegSP, exp: []byte{0x40, 0xf, 0x97, 0xc4}}, - {name: "inst=SETHI/reg=BP", inst: SETHI, dst: RegBP, exp: []byte{0x40, 0xf, 0x97, 0xc5}}, - {name: "inst=SETHI/reg=SI", inst: SETHI, dst: RegSI, exp: []byte{0x40, 0xf, 0x97, 0xc6}}, - {name: "inst=SETHI/reg=DI", inst: SETHI, dst: RegDI, exp: []byte{0x40, 0xf, 0x97, 0xc7}}, - {name: "inst=SETHI/reg=R8", inst: SETHI, dst: RegR8, exp: []byte{0x41, 0xf, 0x97, 0xc0}}, - {name: "inst=SETHI/reg=R9", inst: SETHI, dst: RegR9, exp: []byte{0x41, 0xf, 0x97, 0xc1}}, - {name: "inst=SETHI/reg=R13", inst: SETHI, dst: RegR13, exp: []byte{0x41, 0xf, 0x97, 0xc5}}, - {name: "inst=SETHI/reg=R14", inst: SETHI, dst: RegR14, exp: []byte{0x41, 0xf, 0x97, 0xc6}}, - {name: "inst=SETHI/reg=R15", inst: SETHI, dst: RegR15, exp: []byte{0x41, 0xf, 0x97, 0xc7}}, - {name: "inst=SETLE/reg=AX", inst: SETLE, dst: RegAX, exp: []byte{0xf, 0x9e, 0xc0}}, - {name: "inst=SETLE/reg=BX", inst: SETLE, dst: RegBX, exp: []byte{0xf, 0x9e, 0xc3}}, - {name: "inst=SETLE/reg=SP", inst: SETLE, dst: RegSP, exp: []byte{0x40, 0xf, 0x9e, 0xc4}}, - {name: "inst=SETLE/reg=BP", inst: SETLE, dst: RegBP, exp: []byte{0x40, 0xf, 0x9e, 0xc5}}, - {name: "inst=SETLE/reg=SI", inst: SETLE, dst: RegSI, exp: []byte{0x40, 0xf, 0x9e, 0xc6}}, - {name: "inst=SETLE/reg=DI", inst: SETLE, dst: RegDI, exp: []byte{0x40, 0xf, 0x9e, 0xc7}}, - {name: "inst=SETLE/reg=R8", inst: SETLE, dst: RegR8, exp: []byte{0x41, 0xf, 0x9e, 0xc0}}, - {name: "inst=SETLE/reg=R9", inst: SETLE, dst: RegR9, exp: []byte{0x41, 0xf, 0x9e, 0xc1}}, - {name: "inst=SETLE/reg=R13", inst: SETLE, dst: RegR13, exp: []byte{0x41, 0xf, 0x9e, 0xc5}}, - {name: "inst=SETLE/reg=R14", inst: SETLE, dst: RegR14, exp: []byte{0x41, 0xf, 0x9e, 0xc6}}, - {name: "inst=SETLE/reg=R15", inst: SETLE, dst: RegR15, exp: []byte{0x41, 0xf, 0x9e, 0xc7}}, - {name: "inst=SETLS/reg=AX", inst: SETLS, dst: RegAX, exp: []byte{0xf, 0x96, 0xc0}}, - {name: "inst=SETLS/reg=BX", inst: SETLS, dst: RegBX, exp: []byte{0xf, 0x96, 0xc3}}, - {name: "inst=SETLS/reg=SP", inst: SETLS, dst: RegSP, exp: []byte{0x40, 0xf, 0x96, 0xc4}}, - {name: "inst=SETLS/reg=BP", inst: SETLS, dst: RegBP, exp: []byte{0x40, 0xf, 0x96, 0xc5}}, - {name: "inst=SETLS/reg=SI", inst: SETLS, dst: RegSI, exp: []byte{0x40, 0xf, 0x96, 0xc6}}, - {name: "inst=SETLS/reg=DI", inst: SETLS, dst: RegDI, exp: []byte{0x40, 0xf, 0x96, 0xc7}}, - {name: "inst=SETLS/reg=R8", inst: SETLS, dst: RegR8, exp: []byte{0x41, 0xf, 0x96, 0xc0}}, - {name: "inst=SETLS/reg=R9", inst: SETLS, dst: RegR9, exp: []byte{0x41, 0xf, 0x96, 0xc1}}, - {name: "inst=SETLS/reg=R13", inst: SETLS, dst: RegR13, exp: []byte{0x41, 0xf, 0x96, 0xc5}}, - {name: "inst=SETLS/reg=R14", inst: SETLS, dst: RegR14, exp: []byte{0x41, 0xf, 0x96, 0xc6}}, - {name: "inst=SETLS/reg=R15", inst: SETLS, dst: RegR15, exp: []byte{0x41, 0xf, 0x96, 0xc7}}, - {name: "inst=SETLT/reg=AX", inst: SETLT, dst: RegAX, exp: []byte{0xf, 0x9c, 0xc0}}, - {name: "inst=SETLT/reg=BX", inst: SETLT, dst: RegBX, exp: []byte{0xf, 0x9c, 0xc3}}, - {name: "inst=SETLT/reg=SP", inst: SETLT, dst: RegSP, exp: []byte{0x40, 0xf, 0x9c, 0xc4}}, - {name: "inst=SETLT/reg=BP", inst: SETLT, dst: RegBP, exp: []byte{0x40, 0xf, 0x9c, 0xc5}}, - {name: "inst=SETLT/reg=SI", inst: SETLT, dst: RegSI, exp: []byte{0x40, 0xf, 0x9c, 0xc6}}, - {name: "inst=SETLT/reg=DI", inst: SETLT, dst: RegDI, exp: []byte{0x40, 0xf, 0x9c, 0xc7}}, - {name: "inst=SETLT/reg=R8", inst: SETLT, dst: RegR8, exp: []byte{0x41, 0xf, 0x9c, 0xc0}}, - {name: "inst=SETLT/reg=R9", inst: SETLT, dst: RegR9, exp: []byte{0x41, 0xf, 0x9c, 0xc1}}, - {name: "inst=SETLT/reg=R13", inst: SETLT, dst: RegR13, exp: []byte{0x41, 0xf, 0x9c, 0xc5}}, - {name: "inst=SETLT/reg=R14", inst: SETLT, dst: RegR14, exp: []byte{0x41, 0xf, 0x9c, 0xc6}}, - {name: "inst=SETLT/reg=R15", inst: SETLT, dst: RegR15, exp: []byte{0x41, 0xf, 0x9c, 0xc7}}, - {name: "inst=SETNE/reg=AX", inst: SETNE, dst: RegAX, exp: []byte{0xf, 0x95, 0xc0}}, - {name: "inst=SETNE/reg=BX", inst: SETNE, dst: RegBX, exp: []byte{0xf, 0x95, 0xc3}}, - {name: "inst=SETNE/reg=SP", inst: SETNE, dst: RegSP, exp: []byte{0x40, 0xf, 0x95, 0xc4}}, - {name: "inst=SETNE/reg=BP", inst: SETNE, dst: RegBP, exp: []byte{0x40, 0xf, 0x95, 0xc5}}, - {name: "inst=SETNE/reg=SI", inst: SETNE, dst: RegSI, exp: []byte{0x40, 0xf, 0x95, 0xc6}}, - {name: "inst=SETNE/reg=DI", inst: SETNE, dst: RegDI, exp: []byte{0x40, 0xf, 0x95, 0xc7}}, - {name: "inst=SETNE/reg=R8", inst: SETNE, dst: RegR8, exp: []byte{0x41, 0xf, 0x95, 0xc0}}, - {name: "inst=SETNE/reg=R9", inst: SETNE, dst: RegR9, exp: []byte{0x41, 0xf, 0x95, 0xc1}}, - {name: "inst=SETNE/reg=R13", inst: SETNE, dst: RegR13, exp: []byte{0x41, 0xf, 0x95, 0xc5}}, - {name: "inst=SETNE/reg=R14", inst: SETNE, dst: RegR14, exp: []byte{0x41, 0xf, 0x95, 0xc6}}, - {name: "inst=SETNE/reg=R15", inst: SETNE, dst: RegR15, exp: []byte{0x41, 0xf, 0x95, 0xc7}}, - {name: "inst=SETPC/reg=AX", inst: SETPC, dst: RegAX, exp: []byte{0xf, 0x9b, 0xc0}}, - {name: "inst=SETPC/reg=BX", inst: SETPC, dst: RegBX, exp: []byte{0xf, 0x9b, 0xc3}}, - {name: "inst=SETPC/reg=SP", inst: SETPC, dst: RegSP, exp: []byte{0x40, 0xf, 0x9b, 0xc4}}, - {name: "inst=SETPC/reg=BP", inst: SETPC, dst: RegBP, exp: []byte{0x40, 0xf, 0x9b, 0xc5}}, - {name: "inst=SETPC/reg=SI", inst: SETPC, dst: RegSI, exp: []byte{0x40, 0xf, 0x9b, 0xc6}}, - {name: "inst=SETPC/reg=DI", inst: SETPC, dst: RegDI, exp: []byte{0x40, 0xf, 0x9b, 0xc7}}, - {name: "inst=SETPC/reg=R8", inst: SETPC, dst: RegR8, exp: []byte{0x41, 0xf, 0x9b, 0xc0}}, - {name: "inst=SETPC/reg=R9", inst: SETPC, dst: RegR9, exp: []byte{0x41, 0xf, 0x9b, 0xc1}}, - {name: "inst=SETPC/reg=R13", inst: SETPC, dst: RegR13, exp: []byte{0x41, 0xf, 0x9b, 0xc5}}, - {name: "inst=SETPC/reg=R14", inst: SETPC, dst: RegR14, exp: []byte{0x41, 0xf, 0x9b, 0xc6}}, - {name: "inst=SETPC/reg=R15", inst: SETPC, dst: RegR15, exp: []byte{0x41, 0xf, 0x9b, 0xc7}}, - {name: "inst=SETPS/reg=AX", inst: SETPS, dst: RegAX, exp: []byte{0xf, 0x9a, 0xc0}}, - {name: "inst=SETPS/reg=BX", inst: SETPS, dst: RegBX, exp: []byte{0xf, 0x9a, 0xc3}}, - {name: "inst=SETPS/reg=SP", inst: SETPS, dst: RegSP, exp: []byte{0x40, 0xf, 0x9a, 0xc4}}, - {name: "inst=SETPS/reg=BP", inst: SETPS, dst: RegBP, exp: []byte{0x40, 0xf, 0x9a, 0xc5}}, - {name: "inst=SETPS/reg=SI", inst: SETPS, dst: RegSI, exp: []byte{0x40, 0xf, 0x9a, 0xc6}}, - {name: "inst=SETPS/reg=DI", inst: SETPS, dst: RegDI, exp: []byte{0x40, 0xf, 0x9a, 0xc7}}, - {name: "inst=SETPS/reg=R8", inst: SETPS, dst: RegR8, exp: []byte{0x41, 0xf, 0x9a, 0xc0}}, - {name: "inst=SETPS/reg=R9", inst: SETPS, dst: RegR9, exp: []byte{0x41, 0xf, 0x9a, 0xc1}}, - {name: "inst=SETPS/reg=R13", inst: SETPS, dst: RegR13, exp: []byte{0x41, 0xf, 0x9a, 0xc5}}, - {name: "inst=SETPS/reg=R14", inst: SETPS, dst: RegR14, exp: []byte{0x41, 0xf, 0x9a, 0xc6}}, - {name: "inst=SETPS/reg=R15", inst: SETPS, dst: RegR15, exp: []byte{0x41, 0xf, 0x9a, 0xc7}}, - {name: "negq %rax", inst: NEGQ, dst: RegAX, exp: []byte{0x48, 0xf7, 0xd8}}, - {name: "negq %rbx", inst: NEGQ, dst: RegBX, exp: []byte{0x48, 0xf7, 0xdb}}, - {name: "negq %rsp", inst: NEGQ, dst: RegSP, exp: []byte{0x48, 0xf7, 0xdc}}, - {name: "negq %rbp", inst: NEGQ, dst: RegBP, exp: []byte{0x48, 0xf7, 0xdd}}, - {name: "negq %rsi", inst: NEGQ, dst: RegSI, exp: []byte{0x48, 0xf7, 0xde}}, - {name: "negq %rdi", inst: NEGQ, dst: RegDI, exp: []byte{0x48, 0xf7, 0xdf}}, - {name: "negq %r8", inst: NEGQ, dst: RegR8, exp: []byte{0x49, 0xf7, 0xd8}}, - {name: "negq %r9", inst: NEGQ, dst: RegR9, exp: []byte{0x49, 0xf7, 0xd9}}, - {name: "negq %r13", inst: NEGQ, dst: RegR13, exp: []byte{0x49, 0xf7, 0xdd}}, - {name: "negq %r14", inst: NEGQ, dst: RegR14, exp: []byte{0x49, 0xf7, 0xde}}, - {name: "negq %r15", inst: NEGQ, dst: RegR15, exp: []byte{0x49, 0xf7, 0xdf}}, - {name: "negw %ax", inst: NEGW, dst: RegAX, exp: []byte{0x66, 0xf7, 0xd8}}, - {name: "negw %bx", inst: NEGW, dst: RegBX, exp: []byte{0x66, 0xf7, 0xdb}}, - {name: "negw %sp", inst: NEGW, dst: RegSP, exp: []byte{0x66, 0xf7, 0xdc}}, - {name: "negw %bp", inst: NEGW, dst: RegBP, exp: []byte{0x66, 0xf7, 0xdd}}, - {name: "negw %si", inst: NEGW, dst: RegSI, exp: []byte{0x66, 0xf7, 0xde}}, - {name: "negw %di", inst: NEGW, dst: RegDI, exp: []byte{0x66, 0xf7, 0xdf}}, - {name: "negw %r8w", inst: NEGW, dst: RegR8, exp: []byte{0x66, 0x41, 0xf7, 0xd8}}, - {name: "negw %r9w", inst: NEGW, dst: RegR9, exp: []byte{0x66, 0x41, 0xf7, 0xd9}}, - {name: "negw %r13w", inst: NEGW, dst: RegR13, exp: []byte{0x66, 0x41, 0xf7, 0xdd}}, - {name: "negw %r15w", inst: NEGW, dst: RegR14, exp: []byte{0x66, 0x41, 0xf7, 0xde}}, - {name: "negw %r15w", inst: NEGW, dst: RegR15, exp: []byte{0x66, 0x41, 0xf7, 0xdf}}, - {name: "negl %eax", inst: NEGL, dst: RegAX, exp: []byte{0xf7, 0xd8}}, - {name: "negl %ebx", inst: NEGL, dst: RegBX, exp: []byte{0xf7, 0xdb}}, - {name: "negl %esp", inst: NEGL, dst: RegSP, exp: []byte{0xf7, 0xdc}}, - {name: "negl %ebp", inst: NEGL, dst: RegBP, exp: []byte{0xf7, 0xdd}}, - {name: "negl %esi", inst: NEGL, dst: RegSI, exp: []byte{0xf7, 0xde}}, - {name: "negl %edi", inst: NEGL, dst: RegDI, exp: []byte{0xf7, 0xdf}}, - {name: "negl %r8d", inst: NEGL, dst: RegR8, exp: []byte{0x41, 0xf7, 0xd8}}, - {name: "negl %r9d", inst: NEGL, dst: RegR9, exp: []byte{0x41, 0xf7, 0xd9}}, - {name: "negl %r13d", inst: NEGL, dst: RegR13, exp: []byte{0x41, 0xf7, 0xdd}}, - {name: "negl %r14d", inst: NEGL, dst: RegR14, exp: []byte{0x41, 0xf7, 0xde}}, - {name: "negl %r15d", inst: NEGL, dst: RegR15, exp: []byte{0x41, 0xf7, 0xdf}}, - {name: "negb %al", inst: NEGB, dst: RegAX, exp: []byte{0xf6, 0xd8}}, - {name: "negb %bl", inst: NEGB, dst: RegBX, exp: []byte{0xf6, 0xdb}}, - {name: "negb %ah", inst: NEGB, dst: RegSP, exp: []byte{0xf6, 0xdc}}, - {name: "negb %ch", inst: NEGB, dst: RegBP, exp: []byte{0xf6, 0xdd}}, - {name: "negb %dh", inst: NEGB, dst: RegSI, exp: []byte{0xf6, 0xde}}, - {name: "negb %bh", inst: NEGB, dst: RegDI, exp: []byte{0xf6, 0xdf}}, - {name: "negb %r8b", inst: NEGB, dst: RegR8, exp: []byte{0x41, 0xf6, 0xd8}}, - {name: "negb %r9b", inst: NEGB, dst: RegR9, exp: []byte{0x41, 0xf6, 0xd9}}, - {name: "negb %r13b", inst: NEGB, dst: RegR13, exp: []byte{0x41, 0xf6, 0xdd}}, - {name: "negb %r14b", inst: NEGB, dst: RegR14, exp: []byte{0x41, 0xf6, 0xde}}, - {name: "negb %r15b", inst: NEGB, dst: RegR15, exp: []byte{0x41, 0xf6, 0xdf}}, - {name: "inst=INCQ/reg=AX", inst: INCQ, dst: RegAX, exp: []byte{0x48, 0xff, 0xc0}}, - {name: "inst=INCQ/reg=BX", inst: INCQ, dst: RegBX, exp: []byte{0x48, 0xff, 0xc3}}, - {name: "inst=INCQ/reg=SP", inst: INCQ, dst: RegSP, exp: []byte{0x48, 0xff, 0xc4}}, - {name: "inst=INCQ/reg=BP", inst: INCQ, dst: RegBP, exp: []byte{0x48, 0xff, 0xc5}}, - {name: "inst=INCQ/reg=SI", inst: INCQ, dst: RegSI, exp: []byte{0x48, 0xff, 0xc6}}, - {name: "inst=INCQ/reg=DI", inst: INCQ, dst: RegDI, exp: []byte{0x48, 0xff, 0xc7}}, - {name: "inst=INCQ/reg=R8", inst: INCQ, dst: RegR8, exp: []byte{0x49, 0xff, 0xc0}}, - {name: "inst=INCQ/reg=R9", inst: INCQ, dst: RegR9, exp: []byte{0x49, 0xff, 0xc1}}, - {name: "inst=INCQ/reg=R13", inst: INCQ, dst: RegR13, exp: []byte{0x49, 0xff, 0xc5}}, - {name: "inst=INCQ/reg=R14", inst: INCQ, dst: RegR14, exp: []byte{0x49, 0xff, 0xc6}}, - {name: "inst=INCQ/reg=R15", inst: INCQ, dst: RegR15, exp: []byte{0x49, 0xff, 0xc7}}, - {name: "inst=DECQ/reg=AX", inst: DECQ, dst: RegAX, exp: []byte{0x48, 0xff, 0xc8}}, - {name: "inst=DECQ/reg=BX", inst: DECQ, dst: RegBX, exp: []byte{0x48, 0xff, 0xcb}}, - {name: "inst=DECQ/reg=SP", inst: DECQ, dst: RegSP, exp: []byte{0x48, 0xff, 0xcc}}, - {name: "inst=DECQ/reg=BP", inst: DECQ, dst: RegBP, exp: []byte{0x48, 0xff, 0xcd}}, - {name: "inst=DECQ/reg=SI", inst: DECQ, dst: RegSI, exp: []byte{0x48, 0xff, 0xce}}, - {name: "inst=DECQ/reg=DI", inst: DECQ, dst: RegDI, exp: []byte{0x48, 0xff, 0xcf}}, - {name: "inst=DECQ/reg=R8", inst: DECQ, dst: RegR8, exp: []byte{0x49, 0xff, 0xc8}}, - {name: "inst=DECQ/reg=R9", inst: DECQ, dst: RegR9, exp: []byte{0x49, 0xff, 0xc9}}, - {name: "inst=DECQ/reg=R13", inst: DECQ, dst: RegR13, exp: []byte{0x49, 0xff, 0xcd}}, - {name: "inst=DECQ/reg=R14", inst: DECQ, dst: RegR14, exp: []byte{0x49, 0xff, 0xce}}, - {name: "inst=DECQ/reg=R15", inst: DECQ, dst: RegR15, exp: []byte{0x49, 0xff, 0xcf}}, - } - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - a := NewAssembler() - buf := code.NextCodeSection() - err := a.encodeNoneToRegister(buf, &nodeImpl{instruction: tc.inst, dstReg: tc.dst}) - require.NoError(t, err, tc.name) - require.Equal(t, tc.exp, buf.Bytes(), tc.name) - }) - } -} - -func TestAssemblerImpl_EncodeNoneToMemory(t *testing.T) { - t.Run("error", func(t *testing.T) { - tests := []struct { - n *nodeImpl - expErr string - }{ - { - n: &nodeImpl{instruction: ADDL, types: operandTypesNoneToMemory, dstReg: RegAX}, - expErr: "ADDL is unsupported for NoneToMemory type", - }, - } - - for _, tt := range tests { - tc := tt - t.Run(tc.expErr, func(t *testing.T) { - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - tc := tc - a := NewAssembler() - buf := code.NextCodeSection() - err := a.encodeNoneToMemory(buf, tc.n) - require.EqualError(t, err, tc.expErr) - }) - } - }) - - tests := []struct { - name string - inst asm.Instruction - dst asm.Register - dstOffset int64 - exp []byte - }{ - {name: "inst=DECQ/reg=AX/offset=0", inst: DECQ, dst: RegAX, dstOffset: 0, exp: []byte{0x48, 0xff, 0x8}}, - {name: "inst=DECQ/reg=AX/offset=1", inst: DECQ, dst: RegAX, dstOffset: 1, exp: []byte{0x48, 0xff, 0x48, 0x1}}, - {name: "inst=DECQ/reg=AX/offset=-1", inst: DECQ, dst: RegAX, dstOffset: -1, exp: []byte{0x48, 0xff, 0x48, 0xff}}, - {name: "inst=DECQ/reg=AX/offset=1243", inst: DECQ, dst: RegAX, dstOffset: 1243, exp: []byte{0x48, 0xff, 0x88, 0xdb, 0x4, 0x0, 0x0}}, - {name: "inst=DECQ/reg=AX/offset=2147483647", inst: DECQ, dst: RegAX, dstOffset: 2147483647, exp: []byte{0x48, 0xff, 0x88, 0xff, 0xff, 0xff, 0x7f}}, - {name: "inst=DECQ/reg=AX/offset=-32768", inst: DECQ, dst: RegAX, dstOffset: -32768, exp: []byte{0x48, 0xff, 0x88, 0x0, 0x80, 0xff, 0xff}}, - {name: "inst=DECQ/reg=BX/offset=0", inst: DECQ, dst: RegBX, dstOffset: 0, exp: []byte{0x48, 0xff, 0xb}}, - {name: "inst=DECQ/reg=BX/offset=1", inst: DECQ, dst: RegBX, dstOffset: 1, exp: []byte{0x48, 0xff, 0x4b, 0x1}}, - {name: "inst=DECQ/reg=BX/offset=-1", inst: DECQ, dst: RegBX, dstOffset: -1, exp: []byte{0x48, 0xff, 0x4b, 0xff}}, - {name: "inst=DECQ/reg=BX/offset=1243", inst: DECQ, dst: RegBX, dstOffset: 1243, exp: []byte{0x48, 0xff, 0x8b, 0xdb, 0x4, 0x0, 0x0}}, - {name: "inst=DECQ/reg=BX/offset=2147483647", inst: DECQ, dst: RegBX, dstOffset: 2147483647, exp: []byte{0x48, 0xff, 0x8b, 0xff, 0xff, 0xff, 0x7f}}, - {name: "inst=DECQ/reg=BX/offset=-32768", inst: DECQ, dst: RegBX, dstOffset: -32768, exp: []byte{0x48, 0xff, 0x8b, 0x0, 0x80, 0xff, 0xff}}, - {name: "inst=DECQ/reg=SP/offset=0", inst: DECQ, dst: RegSP, dstOffset: 0, exp: []byte{0x48, 0xff, 0xc, 0x24}}, - {name: "inst=DECQ/reg=SP/offset=1", inst: DECQ, dst: RegSP, dstOffset: 1, exp: []byte{0x48, 0xff, 0x4c, 0x24, 0x1}}, - {name: "inst=DECQ/reg=SP/offset=-1", inst: DECQ, dst: RegSP, dstOffset: -1, exp: []byte{0x48, 0xff, 0x4c, 0x24, 0xff}}, - {name: "inst=DECQ/reg=SP/offset=1243", inst: DECQ, dst: RegSP, dstOffset: 1243, exp: []byte{0x48, 0xff, 0x8c, 0x24, 0xdb, 0x4, 0x0, 0x0}}, - {name: "inst=DECQ/reg=SP/offset=2147483647", inst: DECQ, dst: RegSP, dstOffset: 2147483647, exp: []byte{0x48, 0xff, 0x8c, 0x24, 0xff, 0xff, 0xff, 0x7f}}, - {name: "inst=DECQ/reg=SP/offset=-32768", inst: DECQ, dst: RegSP, dstOffset: -32768, exp: []byte{0x48, 0xff, 0x8c, 0x24, 0x0, 0x80, 0xff, 0xff}}, - {name: "inst=DECQ/reg=BP/offset=0", inst: DECQ, dst: RegBP, dstOffset: 0, exp: []byte{0x48, 0xff, 0x4d, 0x0}}, - {name: "inst=DECQ/reg=BP/offset=1", inst: DECQ, dst: RegBP, dstOffset: 1, exp: []byte{0x48, 0xff, 0x4d, 0x1}}, - {name: "inst=DECQ/reg=BP/offset=-1", inst: DECQ, dst: RegBP, dstOffset: -1, exp: []byte{0x48, 0xff, 0x4d, 0xff}}, - {name: "inst=DECQ/reg=BP/offset=1243", inst: DECQ, dst: RegBP, dstOffset: 1243, exp: []byte{0x48, 0xff, 0x8d, 0xdb, 0x4, 0x0, 0x0}}, - {name: "inst=DECQ/reg=BP/offset=2147483647", inst: DECQ, dst: RegBP, dstOffset: 2147483647, exp: []byte{0x48, 0xff, 0x8d, 0xff, 0xff, 0xff, 0x7f}}, - {name: "inst=DECQ/reg=BP/offset=-32768", inst: DECQ, dst: RegBP, dstOffset: -32768, exp: []byte{0x48, 0xff, 0x8d, 0x0, 0x80, 0xff, 0xff}}, - {name: "inst=DECQ/reg=SI/offset=0", inst: DECQ, dst: RegSI, dstOffset: 0, exp: []byte{0x48, 0xff, 0xe}}, - {name: "inst=DECQ/reg=SI/offset=1", inst: DECQ, dst: RegSI, dstOffset: 1, exp: []byte{0x48, 0xff, 0x4e, 0x1}}, - {name: "inst=DECQ/reg=SI/offset=-1", inst: DECQ, dst: RegSI, dstOffset: -1, exp: []byte{0x48, 0xff, 0x4e, 0xff}}, - {name: "inst=DECQ/reg=SI/offset=1243", inst: DECQ, dst: RegSI, dstOffset: 1243, exp: []byte{0x48, 0xff, 0x8e, 0xdb, 0x4, 0x0, 0x0}}, - {name: "inst=DECQ/reg=SI/offset=2147483647", inst: DECQ, dst: RegSI, dstOffset: 2147483647, exp: []byte{0x48, 0xff, 0x8e, 0xff, 0xff, 0xff, 0x7f}}, - {name: "inst=DECQ/reg=SI/offset=-32768", inst: DECQ, dst: RegSI, dstOffset: -32768, exp: []byte{0x48, 0xff, 0x8e, 0x0, 0x80, 0xff, 0xff}}, - {name: "inst=DECQ/reg=DI/offset=0", inst: DECQ, dst: RegDI, dstOffset: 0, exp: []byte{0x48, 0xff, 0xf}}, - {name: "inst=DECQ/reg=DI/offset=1", inst: DECQ, dst: RegDI, dstOffset: 1, exp: []byte{0x48, 0xff, 0x4f, 0x1}}, - {name: "inst=DECQ/reg=DI/offset=-1", inst: DECQ, dst: RegDI, dstOffset: -1, exp: []byte{0x48, 0xff, 0x4f, 0xff}}, - {name: "inst=DECQ/reg=DI/offset=1243", inst: DECQ, dst: RegDI, dstOffset: 1243, exp: []byte{0x48, 0xff, 0x8f, 0xdb, 0x4, 0x0, 0x0}}, - {name: "inst=DECQ/reg=DI/offset=2147483647", inst: DECQ, dst: RegDI, dstOffset: 2147483647, exp: []byte{0x48, 0xff, 0x8f, 0xff, 0xff, 0xff, 0x7f}}, - {name: "inst=DECQ/reg=DI/offset=-32768", inst: DECQ, dst: RegDI, dstOffset: -32768, exp: []byte{0x48, 0xff, 0x8f, 0x0, 0x80, 0xff, 0xff}}, - {name: "inst=DECQ/reg=R8/offset=0", inst: DECQ, dst: RegR8, dstOffset: 0, exp: []byte{0x49, 0xff, 0x8}}, - {name: "inst=DECQ/reg=R8/offset=1", inst: DECQ, dst: RegR8, dstOffset: 1, exp: []byte{0x49, 0xff, 0x48, 0x1}}, - {name: "inst=DECQ/reg=R8/offset=-1", inst: DECQ, dst: RegR8, dstOffset: -1, exp: []byte{0x49, 0xff, 0x48, 0xff}}, - {name: "inst=DECQ/reg=R8/offset=1243", inst: DECQ, dst: RegR8, dstOffset: 1243, exp: []byte{0x49, 0xff, 0x88, 0xdb, 0x4, 0x0, 0x0}}, - {name: "inst=DECQ/reg=R8/offset=2147483647", inst: DECQ, dst: RegR8, dstOffset: 2147483647, exp: []byte{0x49, 0xff, 0x88, 0xff, 0xff, 0xff, 0x7f}}, - {name: "inst=DECQ/reg=R8/offset=-32768", inst: DECQ, dst: RegR8, dstOffset: -32768, exp: []byte{0x49, 0xff, 0x88, 0x0, 0x80, 0xff, 0xff}}, - {name: "inst=DECQ/reg=R9/offset=0", inst: DECQ, dst: RegR9, dstOffset: 0, exp: []byte{0x49, 0xff, 0x9}}, - {name: "inst=DECQ/reg=R9/offset=1", inst: DECQ, dst: RegR9, dstOffset: 1, exp: []byte{0x49, 0xff, 0x49, 0x1}}, - {name: "inst=DECQ/reg=R9/offset=-1", inst: DECQ, dst: RegR9, dstOffset: -1, exp: []byte{0x49, 0xff, 0x49, 0xff}}, - {name: "inst=DECQ/reg=R9/offset=1243", inst: DECQ, dst: RegR9, dstOffset: 1243, exp: []byte{0x49, 0xff, 0x89, 0xdb, 0x4, 0x0, 0x0}}, - {name: "inst=DECQ/reg=R9/offset=2147483647", inst: DECQ, dst: RegR9, dstOffset: 2147483647, exp: []byte{0x49, 0xff, 0x89, 0xff, 0xff, 0xff, 0x7f}}, - {name: "inst=DECQ/reg=R9/offset=-32768", inst: DECQ, dst: RegR9, dstOffset: -32768, exp: []byte{0x49, 0xff, 0x89, 0x0, 0x80, 0xff, 0xff}}, - {name: "inst=DECQ/reg=R13/offset=0", inst: DECQ, dst: RegR13, dstOffset: 0, exp: []byte{0x49, 0xff, 0x4d, 0x0}}, - {name: "inst=DECQ/reg=R13/offset=1", inst: DECQ, dst: RegR13, dstOffset: 1, exp: []byte{0x49, 0xff, 0x4d, 0x1}}, - {name: "inst=DECQ/reg=R13/offset=-1", inst: DECQ, dst: RegR13, dstOffset: -1, exp: []byte{0x49, 0xff, 0x4d, 0xff}}, - {name: "inst=DECQ/reg=R13/offset=1243", inst: DECQ, dst: RegR13, dstOffset: 1243, exp: []byte{0x49, 0xff, 0x8d, 0xdb, 0x4, 0x0, 0x0}}, - {name: "inst=DECQ/reg=R13/offset=2147483647", inst: DECQ, dst: RegR13, dstOffset: 2147483647, exp: []byte{0x49, 0xff, 0x8d, 0xff, 0xff, 0xff, 0x7f}}, - {name: "inst=DECQ/reg=R13/offset=-32768", inst: DECQ, dst: RegR13, dstOffset: -32768, exp: []byte{0x49, 0xff, 0x8d, 0x0, 0x80, 0xff, 0xff}}, - {name: "inst=DECQ/reg=R14/offset=0", inst: DECQ, dst: RegR14, dstOffset: 0, exp: []byte{0x49, 0xff, 0xe}}, - {name: "inst=DECQ/reg=R14/offset=1", inst: DECQ, dst: RegR14, dstOffset: 1, exp: []byte{0x49, 0xff, 0x4e, 0x1}}, - {name: "inst=DECQ/reg=R14/offset=-1", inst: DECQ, dst: RegR14, dstOffset: -1, exp: []byte{0x49, 0xff, 0x4e, 0xff}}, - {name: "inst=DECQ/reg=R14/offset=1243", inst: DECQ, dst: RegR14, dstOffset: 1243, exp: []byte{0x49, 0xff, 0x8e, 0xdb, 0x4, 0x0, 0x0}}, - {name: "inst=DECQ/reg=R14/offset=2147483647", inst: DECQ, dst: RegR14, dstOffset: 2147483647, exp: []byte{0x49, 0xff, 0x8e, 0xff, 0xff, 0xff, 0x7f}}, - {name: "inst=DECQ/reg=R14/offset=-32768", inst: DECQ, dst: RegR14, dstOffset: -32768, exp: []byte{0x49, 0xff, 0x8e, 0x0, 0x80, 0xff, 0xff}}, - {name: "inst=DECQ/reg=R15/offset=0", inst: DECQ, dst: RegR15, dstOffset: 0, exp: []byte{0x49, 0xff, 0xf}}, - {name: "inst=DECQ/reg=R15/offset=1", inst: DECQ, dst: RegR15, dstOffset: 1, exp: []byte{0x49, 0xff, 0x4f, 0x1}}, - {name: "inst=DECQ/reg=R15/offset=-1", inst: DECQ, dst: RegR15, dstOffset: -1, exp: []byte{0x49, 0xff, 0x4f, 0xff}}, - {name: "inst=DECQ/reg=R15/offset=1243", inst: DECQ, dst: RegR15, dstOffset: 1243, exp: []byte{0x49, 0xff, 0x8f, 0xdb, 0x4, 0x0, 0x0}}, - {name: "inst=DECQ/reg=R15/offset=2147483647", inst: DECQ, dst: RegR15, dstOffset: 2147483647, exp: []byte{0x49, 0xff, 0x8f, 0xff, 0xff, 0xff, 0x7f}}, - {name: "inst=DECQ/reg=R15/offset=-32768", inst: DECQ, dst: RegR15, dstOffset: -32768, exp: []byte{0x49, 0xff, 0x8f, 0x0, 0x80, 0xff, 0xff}}, - {name: "inst=INCQ/reg=AX/offset=0", inst: INCQ, dst: RegAX, dstOffset: 0, exp: []byte{0x48, 0xff, 0x0}}, - {name: "inst=INCQ/reg=AX/offset=1", inst: INCQ, dst: RegAX, dstOffset: 1, exp: []byte{0x48, 0xff, 0x40, 0x1}}, - {name: "inst=INCQ/reg=AX/offset=-1", inst: INCQ, dst: RegAX, dstOffset: -1, exp: []byte{0x48, 0xff, 0x40, 0xff}}, - {name: "inst=INCQ/reg=AX/offset=1243", inst: INCQ, dst: RegAX, dstOffset: 1243, exp: []byte{0x48, 0xff, 0x80, 0xdb, 0x4, 0x0, 0x0}}, - {name: "inst=INCQ/reg=AX/offset=2147483647", inst: INCQ, dst: RegAX, dstOffset: 2147483647, exp: []byte{0x48, 0xff, 0x80, 0xff, 0xff, 0xff, 0x7f}}, - {name: "inst=INCQ/reg=AX/offset=-32768", inst: INCQ, dst: RegAX, dstOffset: -32768, exp: []byte{0x48, 0xff, 0x80, 0x0, 0x80, 0xff, 0xff}}, - {name: "inst=INCQ/reg=BX/offset=0", inst: INCQ, dst: RegBX, dstOffset: 0, exp: []byte{0x48, 0xff, 0x3}}, - {name: "inst=INCQ/reg=BX/offset=1", inst: INCQ, dst: RegBX, dstOffset: 1, exp: []byte{0x48, 0xff, 0x43, 0x1}}, - {name: "inst=INCQ/reg=BX/offset=-1", inst: INCQ, dst: RegBX, dstOffset: -1, exp: []byte{0x48, 0xff, 0x43, 0xff}}, - {name: "inst=INCQ/reg=BX/offset=1243", inst: INCQ, dst: RegBX, dstOffset: 1243, exp: []byte{0x48, 0xff, 0x83, 0xdb, 0x4, 0x0, 0x0}}, - {name: "inst=INCQ/reg=BX/offset=2147483647", inst: INCQ, dst: RegBX, dstOffset: 2147483647, exp: []byte{0x48, 0xff, 0x83, 0xff, 0xff, 0xff, 0x7f}}, - {name: "inst=INCQ/reg=BX/offset=-32768", inst: INCQ, dst: RegBX, dstOffset: -32768, exp: []byte{0x48, 0xff, 0x83, 0x0, 0x80, 0xff, 0xff}}, - {name: "inst=INCQ/reg=SP/offset=0", inst: INCQ, dst: RegSP, dstOffset: 0, exp: []byte{0x48, 0xff, 0x4, 0x24}}, - {name: "inst=INCQ/reg=SP/offset=1", inst: INCQ, dst: RegSP, dstOffset: 1, exp: []byte{0x48, 0xff, 0x44, 0x24, 0x1}}, - {name: "inst=INCQ/reg=SP/offset=-1", inst: INCQ, dst: RegSP, dstOffset: -1, exp: []byte{0x48, 0xff, 0x44, 0x24, 0xff}}, - {name: "inst=INCQ/reg=SP/offset=1243", inst: INCQ, dst: RegSP, dstOffset: 1243, exp: []byte{0x48, 0xff, 0x84, 0x24, 0xdb, 0x4, 0x0, 0x0}}, - {name: "inst=INCQ/reg=SP/offset=2147483647", inst: INCQ, dst: RegSP, dstOffset: 2147483647, exp: []byte{0x48, 0xff, 0x84, 0x24, 0xff, 0xff, 0xff, 0x7f}}, - {name: "inst=INCQ/reg=SP/offset=-32768", inst: INCQ, dst: RegSP, dstOffset: -32768, exp: []byte{0x48, 0xff, 0x84, 0x24, 0x0, 0x80, 0xff, 0xff}}, - {name: "inst=INCQ/reg=BP/offset=0", inst: INCQ, dst: RegBP, dstOffset: 0, exp: []byte{0x48, 0xff, 0x45, 0x0}}, - {name: "inst=INCQ/reg=BP/offset=1", inst: INCQ, dst: RegBP, dstOffset: 1, exp: []byte{0x48, 0xff, 0x45, 0x1}}, - {name: "inst=INCQ/reg=BP/offset=-1", inst: INCQ, dst: RegBP, dstOffset: -1, exp: []byte{0x48, 0xff, 0x45, 0xff}}, - {name: "inst=INCQ/reg=BP/offset=1243", inst: INCQ, dst: RegBP, dstOffset: 1243, exp: []byte{0x48, 0xff, 0x85, 0xdb, 0x4, 0x0, 0x0}}, - {name: "inst=INCQ/reg=BP/offset=2147483647", inst: INCQ, dst: RegBP, dstOffset: 2147483647, exp: []byte{0x48, 0xff, 0x85, 0xff, 0xff, 0xff, 0x7f}}, - {name: "inst=INCQ/reg=BP/offset=-32768", inst: INCQ, dst: RegBP, dstOffset: -32768, exp: []byte{0x48, 0xff, 0x85, 0x0, 0x80, 0xff, 0xff}}, - {name: "inst=INCQ/reg=SI/offset=0", inst: INCQ, dst: RegSI, dstOffset: 0, exp: []byte{0x48, 0xff, 0x6}}, - {name: "inst=INCQ/reg=SI/offset=1", inst: INCQ, dst: RegSI, dstOffset: 1, exp: []byte{0x48, 0xff, 0x46, 0x1}}, - {name: "inst=INCQ/reg=SI/offset=-1", inst: INCQ, dst: RegSI, dstOffset: -1, exp: []byte{0x48, 0xff, 0x46, 0xff}}, - {name: "inst=INCQ/reg=SI/offset=1243", inst: INCQ, dst: RegSI, dstOffset: 1243, exp: []byte{0x48, 0xff, 0x86, 0xdb, 0x4, 0x0, 0x0}}, - {name: "inst=INCQ/reg=SI/offset=2147483647", inst: INCQ, dst: RegSI, dstOffset: 2147483647, exp: []byte{0x48, 0xff, 0x86, 0xff, 0xff, 0xff, 0x7f}}, - {name: "inst=INCQ/reg=SI/offset=-32768", inst: INCQ, dst: RegSI, dstOffset: -32768, exp: []byte{0x48, 0xff, 0x86, 0x0, 0x80, 0xff, 0xff}}, - {name: "inst=INCQ/reg=DI/offset=0", inst: INCQ, dst: RegDI, dstOffset: 0, exp: []byte{0x48, 0xff, 0x7}}, - {name: "inst=INCQ/reg=DI/offset=1", inst: INCQ, dst: RegDI, dstOffset: 1, exp: []byte{0x48, 0xff, 0x47, 0x1}}, - {name: "inst=INCQ/reg=DI/offset=-1", inst: INCQ, dst: RegDI, dstOffset: -1, exp: []byte{0x48, 0xff, 0x47, 0xff}}, - {name: "inst=INCQ/reg=DI/offset=1243", inst: INCQ, dst: RegDI, dstOffset: 1243, exp: []byte{0x48, 0xff, 0x87, 0xdb, 0x4, 0x0, 0x0}}, - {name: "inst=INCQ/reg=DI/offset=2147483647", inst: INCQ, dst: RegDI, dstOffset: 2147483647, exp: []byte{0x48, 0xff, 0x87, 0xff, 0xff, 0xff, 0x7f}}, - {name: "inst=INCQ/reg=DI/offset=-32768", inst: INCQ, dst: RegDI, dstOffset: -32768, exp: []byte{0x48, 0xff, 0x87, 0x0, 0x80, 0xff, 0xff}}, - {name: "inst=INCQ/reg=R8/offset=0", inst: INCQ, dst: RegR8, dstOffset: 0, exp: []byte{0x49, 0xff, 0x0}}, - {name: "inst=INCQ/reg=R8/offset=1", inst: INCQ, dst: RegR8, dstOffset: 1, exp: []byte{0x49, 0xff, 0x40, 0x1}}, - {name: "inst=INCQ/reg=R8/offset=-1", inst: INCQ, dst: RegR8, dstOffset: -1, exp: []byte{0x49, 0xff, 0x40, 0xff}}, - {name: "inst=INCQ/reg=R8/offset=1243", inst: INCQ, dst: RegR8, dstOffset: 1243, exp: []byte{0x49, 0xff, 0x80, 0xdb, 0x4, 0x0, 0x0}}, - {name: "inst=INCQ/reg=R8/offset=2147483647", inst: INCQ, dst: RegR8, dstOffset: 2147483647, exp: []byte{0x49, 0xff, 0x80, 0xff, 0xff, 0xff, 0x7f}}, - {name: "inst=INCQ/reg=R8/offset=-32768", inst: INCQ, dst: RegR8, dstOffset: -32768, exp: []byte{0x49, 0xff, 0x80, 0x0, 0x80, 0xff, 0xff}}, - {name: "inst=INCQ/reg=R9/offset=0", inst: INCQ, dst: RegR9, dstOffset: 0, exp: []byte{0x49, 0xff, 0x1}}, - {name: "inst=INCQ/reg=R9/offset=1", inst: INCQ, dst: RegR9, dstOffset: 1, exp: []byte{0x49, 0xff, 0x41, 0x1}}, - {name: "inst=INCQ/reg=R9/offset=-1", inst: INCQ, dst: RegR9, dstOffset: -1, exp: []byte{0x49, 0xff, 0x41, 0xff}}, - {name: "inst=INCQ/reg=R9/offset=1243", inst: INCQ, dst: RegR9, dstOffset: 1243, exp: []byte{0x49, 0xff, 0x81, 0xdb, 0x4, 0x0, 0x0}}, - {name: "inst=INCQ/reg=R9/offset=2147483647", inst: INCQ, dst: RegR9, dstOffset: 2147483647, exp: []byte{0x49, 0xff, 0x81, 0xff, 0xff, 0xff, 0x7f}}, - {name: "inst=INCQ/reg=R9/offset=-32768", inst: INCQ, dst: RegR9, dstOffset: -32768, exp: []byte{0x49, 0xff, 0x81, 0x0, 0x80, 0xff, 0xff}}, - {name: "inst=INCQ/reg=R13/offset=0", inst: INCQ, dst: RegR13, dstOffset: 0, exp: []byte{0x49, 0xff, 0x45, 0x0}}, - {name: "inst=INCQ/reg=R13/offset=1", inst: INCQ, dst: RegR13, dstOffset: 1, exp: []byte{0x49, 0xff, 0x45, 0x1}}, - {name: "inst=INCQ/reg=R13/offset=-1", inst: INCQ, dst: RegR13, dstOffset: -1, exp: []byte{0x49, 0xff, 0x45, 0xff}}, - {name: "inst=INCQ/reg=R13/offset=1243", inst: INCQ, dst: RegR13, dstOffset: 1243, exp: []byte{0x49, 0xff, 0x85, 0xdb, 0x4, 0x0, 0x0}}, - {name: "inst=INCQ/reg=R13/offset=2147483647", inst: INCQ, dst: RegR13, dstOffset: 2147483647, exp: []byte{0x49, 0xff, 0x85, 0xff, 0xff, 0xff, 0x7f}}, - {name: "inst=INCQ/reg=R13/offset=-32768", inst: INCQ, dst: RegR13, dstOffset: -32768, exp: []byte{0x49, 0xff, 0x85, 0x0, 0x80, 0xff, 0xff}}, - {name: "inst=INCQ/reg=R14/offset=0", inst: INCQ, dst: RegR14, dstOffset: 0, exp: []byte{0x49, 0xff, 0x6}}, - {name: "inst=INCQ/reg=R14/offset=1", inst: INCQ, dst: RegR14, dstOffset: 1, exp: []byte{0x49, 0xff, 0x46, 0x1}}, - {name: "inst=INCQ/reg=R14/offset=-1", inst: INCQ, dst: RegR14, dstOffset: -1, exp: []byte{0x49, 0xff, 0x46, 0xff}}, - {name: "inst=INCQ/reg=R14/offset=1243", inst: INCQ, dst: RegR14, dstOffset: 1243, exp: []byte{0x49, 0xff, 0x86, 0xdb, 0x4, 0x0, 0x0}}, - {name: "inst=INCQ/reg=R14/offset=2147483647", inst: INCQ, dst: RegR14, dstOffset: 2147483647, exp: []byte{0x49, 0xff, 0x86, 0xff, 0xff, 0xff, 0x7f}}, - {name: "inst=INCQ/reg=R14/offset=-32768", inst: INCQ, dst: RegR14, dstOffset: -32768, exp: []byte{0x49, 0xff, 0x86, 0x0, 0x80, 0xff, 0xff}}, - {name: "inst=INCQ/reg=R15/offset=0", inst: INCQ, dst: RegR15, dstOffset: 0, exp: []byte{0x49, 0xff, 0x7}}, - {name: "inst=INCQ/reg=R15/offset=1", inst: INCQ, dst: RegR15, dstOffset: 1, exp: []byte{0x49, 0xff, 0x47, 0x1}}, - {name: "inst=INCQ/reg=R15/offset=-1", inst: INCQ, dst: RegR15, dstOffset: -1, exp: []byte{0x49, 0xff, 0x47, 0xff}}, - {name: "inst=INCQ/reg=R15/offset=1243", inst: INCQ, dst: RegR15, dstOffset: 1243, exp: []byte{0x49, 0xff, 0x87, 0xdb, 0x4, 0x0, 0x0}}, - {name: "inst=INCQ/reg=R15/offset=2147483647", inst: INCQ, dst: RegR15, dstOffset: 2147483647, exp: []byte{0x49, 0xff, 0x87, 0xff, 0xff, 0xff, 0x7f}}, - {name: "inst=INCQ/reg=R15/offset=-32768", inst: INCQ, dst: RegR15, dstOffset: -32768, exp: []byte{0x49, 0xff, 0x87, 0x0, 0x80, 0xff, 0xff}}, - {name: "inst=JMP/reg=AX/offset=0", inst: JMP, dst: RegAX, dstOffset: 0, exp: []byte{0xff, 0x20}}, - {name: "inst=JMP/reg=AX/offset=1", inst: JMP, dst: RegAX, dstOffset: 1, exp: []byte{0xff, 0x60, 0x1}}, - {name: "inst=JMP/reg=AX/offset=-1", inst: JMP, dst: RegAX, dstOffset: -1, exp: []byte{0xff, 0x60, 0xff}}, - {name: "inst=JMP/reg=AX/offset=1243", inst: JMP, dst: RegAX, dstOffset: 1243, exp: []byte{0xff, 0xa0, 0xdb, 0x4, 0x0, 0x0}}, - {name: "inst=JMP/reg=AX/offset=2147483647", inst: JMP, dst: RegAX, dstOffset: 2147483647, exp: []byte{0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "inst=JMP/reg=AX/offset=-32768", inst: JMP, dst: RegAX, dstOffset: -32768, exp: []byte{0xff, 0xa0, 0x0, 0x80, 0xff, 0xff}}, - {name: "inst=JMP/reg=BX/offset=0", inst: JMP, dst: RegBX, dstOffset: 0, exp: []byte{0xff, 0x23}}, - {name: "inst=JMP/reg=BX/offset=1", inst: JMP, dst: RegBX, dstOffset: 1, exp: []byte{0xff, 0x63, 0x1}}, - {name: "inst=JMP/reg=BX/offset=-1", inst: JMP, dst: RegBX, dstOffset: -1, exp: []byte{0xff, 0x63, 0xff}}, - {name: "inst=JMP/reg=BX/offset=1243", inst: JMP, dst: RegBX, dstOffset: 1243, exp: []byte{0xff, 0xa3, 0xdb, 0x4, 0x0, 0x0}}, - {name: "inst=JMP/reg=BX/offset=2147483647", inst: JMP, dst: RegBX, dstOffset: 2147483647, exp: []byte{0xff, 0xa3, 0xff, 0xff, 0xff, 0x7f}}, - {name: "inst=JMP/reg=BX/offset=-32768", inst: JMP, dst: RegBX, dstOffset: -32768, exp: []byte{0xff, 0xa3, 0x0, 0x80, 0xff, 0xff}}, - {name: "inst=JMP/reg=SP/offset=0", inst: JMP, dst: RegSP, dstOffset: 0, exp: []byte{0xff, 0x24, 0x24}}, - {name: "inst=JMP/reg=SP/offset=1", inst: JMP, dst: RegSP, dstOffset: 1, exp: []byte{0xff, 0x64, 0x24, 0x1}}, - {name: "inst=JMP/reg=SP/offset=-1", inst: JMP, dst: RegSP, dstOffset: -1, exp: []byte{0xff, 0x64, 0x24, 0xff}}, - {name: "inst=JMP/reg=SP/offset=1243", inst: JMP, dst: RegSP, dstOffset: 1243, exp: []byte{0xff, 0xa4, 0x24, 0xdb, 0x4, 0x0, 0x0}}, - {name: "inst=JMP/reg=SP/offset=2147483647", inst: JMP, dst: RegSP, dstOffset: 2147483647, exp: []byte{0xff, 0xa4, 0x24, 0xff, 0xff, 0xff, 0x7f}}, - {name: "inst=JMP/reg=SP/offset=-32768", inst: JMP, dst: RegSP, dstOffset: -32768, exp: []byte{0xff, 0xa4, 0x24, 0x0, 0x80, 0xff, 0xff}}, - {name: "inst=JMP/reg=BP/offset=0", inst: JMP, dst: RegBP, dstOffset: 0, exp: []byte{0xff, 0x65, 0x0}}, - {name: "inst=JMP/reg=BP/offset=1", inst: JMP, dst: RegBP, dstOffset: 1, exp: []byte{0xff, 0x65, 0x1}}, - {name: "inst=JMP/reg=BP/offset=-1", inst: JMP, dst: RegBP, dstOffset: -1, exp: []byte{0xff, 0x65, 0xff}}, - {name: "inst=JMP/reg=BP/offset=1243", inst: JMP, dst: RegBP, dstOffset: 1243, exp: []byte{0xff, 0xa5, 0xdb, 0x4, 0x0, 0x0}}, - {name: "inst=JMP/reg=BP/offset=2147483647", inst: JMP, dst: RegBP, dstOffset: 2147483647, exp: []byte{0xff, 0xa5, 0xff, 0xff, 0xff, 0x7f}}, - {name: "inst=JMP/reg=BP/offset=-32768", inst: JMP, dst: RegBP, dstOffset: -32768, exp: []byte{0xff, 0xa5, 0x0, 0x80, 0xff, 0xff}}, - {name: "inst=JMP/reg=SI/offset=0", inst: JMP, dst: RegSI, dstOffset: 0, exp: []byte{0xff, 0x26}}, - {name: "inst=JMP/reg=SI/offset=1", inst: JMP, dst: RegSI, dstOffset: 1, exp: []byte{0xff, 0x66, 0x1}}, - {name: "inst=JMP/reg=SI/offset=-1", inst: JMP, dst: RegSI, dstOffset: -1, exp: []byte{0xff, 0x66, 0xff}}, - {name: "inst=JMP/reg=SI/offset=1243", inst: JMP, dst: RegSI, dstOffset: 1243, exp: []byte{0xff, 0xa6, 0xdb, 0x4, 0x0, 0x0}}, - {name: "inst=JMP/reg=SI/offset=2147483647", inst: JMP, dst: RegSI, dstOffset: 2147483647, exp: []byte{0xff, 0xa6, 0xff, 0xff, 0xff, 0x7f}}, - {name: "inst=JMP/reg=SI/offset=-32768", inst: JMP, dst: RegSI, dstOffset: -32768, exp: []byte{0xff, 0xa6, 0x0, 0x80, 0xff, 0xff}}, - {name: "inst=JMP/reg=DI/offset=0", inst: JMP, dst: RegDI, dstOffset: 0, exp: []byte{0xff, 0x27}}, - {name: "inst=JMP/reg=DI/offset=1", inst: JMP, dst: RegDI, dstOffset: 1, exp: []byte{0xff, 0x67, 0x1}}, - {name: "inst=JMP/reg=DI/offset=-1", inst: JMP, dst: RegDI, dstOffset: -1, exp: []byte{0xff, 0x67, 0xff}}, - {name: "inst=JMP/reg=DI/offset=1243", inst: JMP, dst: RegDI, dstOffset: 1243, exp: []byte{0xff, 0xa7, 0xdb, 0x4, 0x0, 0x0}}, - {name: "inst=JMP/reg=DI/offset=2147483647", inst: JMP, dst: RegDI, dstOffset: 2147483647, exp: []byte{0xff, 0xa7, 0xff, 0xff, 0xff, 0x7f}}, - {name: "inst=JMP/reg=DI/offset=-32768", inst: JMP, dst: RegDI, dstOffset: -32768, exp: []byte{0xff, 0xa7, 0x0, 0x80, 0xff, 0xff}}, - {name: "inst=JMP/reg=R8/offset=0", inst: JMP, dst: RegR8, dstOffset: 0, exp: []byte{0x41, 0xff, 0x20}}, - {name: "inst=JMP/reg=R8/offset=1", inst: JMP, dst: RegR8, dstOffset: 1, exp: []byte{0x41, 0xff, 0x60, 0x1}}, - {name: "inst=JMP/reg=R8/offset=-1", inst: JMP, dst: RegR8, dstOffset: -1, exp: []byte{0x41, 0xff, 0x60, 0xff}}, - {name: "inst=JMP/reg=R8/offset=1243", inst: JMP, dst: RegR8, dstOffset: 1243, exp: []byte{0x41, 0xff, 0xa0, 0xdb, 0x4, 0x0, 0x0}}, - {name: "inst=JMP/reg=R8/offset=2147483647", inst: JMP, dst: RegR8, dstOffset: 2147483647, exp: []byte{0x41, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "inst=JMP/reg=R8/offset=-32768", inst: JMP, dst: RegR8, dstOffset: -32768, exp: []byte{0x41, 0xff, 0xa0, 0x0, 0x80, 0xff, 0xff}}, - {name: "inst=JMP/reg=R9/offset=0", inst: JMP, dst: RegR9, dstOffset: 0, exp: []byte{0x41, 0xff, 0x21}}, - {name: "inst=JMP/reg=R9/offset=1", inst: JMP, dst: RegR9, dstOffset: 1, exp: []byte{0x41, 0xff, 0x61, 0x1}}, - {name: "inst=JMP/reg=R9/offset=-1", inst: JMP, dst: RegR9, dstOffset: -1, exp: []byte{0x41, 0xff, 0x61, 0xff}}, - {name: "inst=JMP/reg=R9/offset=1243", inst: JMP, dst: RegR9, dstOffset: 1243, exp: []byte{0x41, 0xff, 0xa1, 0xdb, 0x4, 0x0, 0x0}}, - {name: "inst=JMP/reg=R9/offset=2147483647", inst: JMP, dst: RegR9, dstOffset: 2147483647, exp: []byte{0x41, 0xff, 0xa1, 0xff, 0xff, 0xff, 0x7f}}, - {name: "inst=JMP/reg=R9/offset=-32768", inst: JMP, dst: RegR9, dstOffset: -32768, exp: []byte{0x41, 0xff, 0xa1, 0x0, 0x80, 0xff, 0xff}}, - {name: "inst=JMP/reg=R13/offset=0", inst: JMP, dst: RegR13, dstOffset: 0, exp: []byte{0x41, 0xff, 0x65, 0x0}}, - {name: "inst=JMP/reg=R13/offset=1", inst: JMP, dst: RegR13, dstOffset: 1, exp: []byte{0x41, 0xff, 0x65, 0x1}}, - {name: "inst=JMP/reg=R13/offset=-1", inst: JMP, dst: RegR13, dstOffset: -1, exp: []byte{0x41, 0xff, 0x65, 0xff}}, - {name: "inst=JMP/reg=R13/offset=1243", inst: JMP, dst: RegR13, dstOffset: 1243, exp: []byte{0x41, 0xff, 0xa5, 0xdb, 0x4, 0x0, 0x0}}, - {name: "inst=JMP/reg=R13/offset=2147483647", inst: JMP, dst: RegR13, dstOffset: 2147483647, exp: []byte{0x41, 0xff, 0xa5, 0xff, 0xff, 0xff, 0x7f}}, - {name: "inst=JMP/reg=R13/offset=-32768", inst: JMP, dst: RegR13, dstOffset: -32768, exp: []byte{0x41, 0xff, 0xa5, 0x0, 0x80, 0xff, 0xff}}, - {name: "inst=JMP/reg=R14/offset=0", inst: JMP, dst: RegR14, dstOffset: 0, exp: []byte{0x41, 0xff, 0x26}}, - {name: "inst=JMP/reg=R14/offset=1", inst: JMP, dst: RegR14, dstOffset: 1, exp: []byte{0x41, 0xff, 0x66, 0x1}}, - {name: "inst=JMP/reg=R14/offset=-1", inst: JMP, dst: RegR14, dstOffset: -1, exp: []byte{0x41, 0xff, 0x66, 0xff}}, - {name: "inst=JMP/reg=R14/offset=1243", inst: JMP, dst: RegR14, dstOffset: 1243, exp: []byte{0x41, 0xff, 0xa6, 0xdb, 0x4, 0x0, 0x0}}, - {name: "inst=JMP/reg=R14/offset=2147483647", inst: JMP, dst: RegR14, dstOffset: 2147483647, exp: []byte{0x41, 0xff, 0xa6, 0xff, 0xff, 0xff, 0x7f}}, - {name: "inst=JMP/reg=R14/offset=-32768", inst: JMP, dst: RegR14, dstOffset: -32768, exp: []byte{0x41, 0xff, 0xa6, 0x0, 0x80, 0xff, 0xff}}, - {name: "inst=JMP/reg=R15/offset=0", inst: JMP, dst: RegR15, dstOffset: 0, exp: []byte{0x41, 0xff, 0x27}}, - {name: "inst=JMP/reg=R15/offset=1", inst: JMP, dst: RegR15, dstOffset: 1, exp: []byte{0x41, 0xff, 0x67, 0x1}}, - {name: "inst=JMP/reg=R15/offset=-1", inst: JMP, dst: RegR15, dstOffset: -1, exp: []byte{0x41, 0xff, 0x67, 0xff}}, - {name: "inst=JMP/reg=R15/offset=1243", inst: JMP, dst: RegR15, dstOffset: 1243, exp: []byte{0x41, 0xff, 0xa7, 0xdb, 0x4, 0x0, 0x0}}, - {name: "inst=JMP/reg=R15/offset=2147483647", inst: JMP, dst: RegR15, dstOffset: 2147483647, exp: []byte{0x41, 0xff, 0xa7, 0xff, 0xff, 0xff, 0x7f}}, - {name: "inst=JMP/reg=R15/offset=-32768", inst: JMP, dst: RegR15, dstOffset: -32768, exp: []byte{0x41, 0xff, 0xa7, 0x0, 0x80, 0xff, 0xff}}, - } - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - for _, tc := range tests { - tc := tc - a := NewAssembler() - buf := code.NextCodeSection() - err := a.encodeNoneToMemory(buf, &nodeImpl{ - types: operandTypesNoneToMemory, - instruction: tc.inst, dstReg: tc.dst, dstConst: tc.dstOffset, - }) - require.NoError(t, err, tc.name) - require.Equal(t, tc.exp, buf.Bytes(), tc.name) - } -} - -func TestAssemblerImpl_EncodeRegisterToNone(t *testing.T) { - t.Run("error", func(t *testing.T) { - tests := []struct { - n *nodeImpl - expErr string - }{ - { - n: &nodeImpl{instruction: ADDL, types: operandTypesRegisterToNone, srcReg: RegAX}, - expErr: "ADDL is unsupported for RegisterToNone type", - }, - } - - for _, tc := range tests { - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - a := NewAssembler() - buf := code.NextCodeSection() - err := a.encodeRegisterToNone(buf, tc.n) - require.EqualError(t, err, tc.expErr, tc, tc.expErr) - } - }) - - tests := []struct { - name string - inst asm.Instruction - reg asm.Register - exp []byte - }{ - {name: "DIVL/reg=AX/", reg: RegAX, inst: DIVL, exp: []byte{0xf7, 0xf0}}, - {name: "DIVL/reg=BX/", reg: RegBX, inst: DIVL, exp: []byte{0xf7, 0xf3}}, - {name: "DIVL/reg=SP/", reg: RegSP, inst: DIVL, exp: []byte{0xf7, 0xf4}}, - {name: "DIVL/reg=BP/", reg: RegBP, inst: DIVL, exp: []byte{0xf7, 0xf5}}, - {name: "DIVL/reg=SI/", reg: RegSI, inst: DIVL, exp: []byte{0xf7, 0xf6}}, - {name: "DIVL/reg=DI/", reg: RegDI, inst: DIVL, exp: []byte{0xf7, 0xf7}}, - {name: "DIVL/reg=R8/", reg: RegR8, inst: DIVL, exp: []byte{0x41, 0xf7, 0xf0}}, - {name: "DIVL/reg=R9/", reg: RegR9, inst: DIVL, exp: []byte{0x41, 0xf7, 0xf1}}, - {name: "DIVL/reg=R13/", reg: RegR13, inst: DIVL, exp: []byte{0x41, 0xf7, 0xf5}}, - {name: "DIVL/reg=R14/", reg: RegR14, inst: DIVL, exp: []byte{0x41, 0xf7, 0xf6}}, - {name: "DIVL/reg=R15/", reg: RegR15, inst: DIVL, exp: []byte{0x41, 0xf7, 0xf7}}, - {name: "DIVQ/reg=AX/", reg: RegAX, inst: DIVQ, exp: []byte{0x48, 0xf7, 0xf0}}, - {name: "DIVQ/reg=BX/", reg: RegBX, inst: DIVQ, exp: []byte{0x48, 0xf7, 0xf3}}, - {name: "DIVQ/reg=SP/", reg: RegSP, inst: DIVQ, exp: []byte{0x48, 0xf7, 0xf4}}, - {name: "DIVQ/reg=BP/", reg: RegBP, inst: DIVQ, exp: []byte{0x48, 0xf7, 0xf5}}, - {name: "DIVQ/reg=SI/", reg: RegSI, inst: DIVQ, exp: []byte{0x48, 0xf7, 0xf6}}, - {name: "DIVQ/reg=DI/", reg: RegDI, inst: DIVQ, exp: []byte{0x48, 0xf7, 0xf7}}, - {name: "DIVQ/reg=R8/", reg: RegR8, inst: DIVQ, exp: []byte{0x49, 0xf7, 0xf0}}, - {name: "DIVQ/reg=R9/", reg: RegR9, inst: DIVQ, exp: []byte{0x49, 0xf7, 0xf1}}, - {name: "DIVQ/reg=R13/", reg: RegR13, inst: DIVQ, exp: []byte{0x49, 0xf7, 0xf5}}, - {name: "DIVQ/reg=R14/", reg: RegR14, inst: DIVQ, exp: []byte{0x49, 0xf7, 0xf6}}, - {name: "DIVQ/reg=R15/", reg: RegR15, inst: DIVQ, exp: []byte{0x49, 0xf7, 0xf7}}, - {name: "IDIVL/reg=AX/", reg: RegAX, inst: IDIVL, exp: []byte{0xf7, 0xf8}}, - {name: "IDIVL/reg=BX/", reg: RegBX, inst: IDIVL, exp: []byte{0xf7, 0xfb}}, - {name: "IDIVL/reg=SP/", reg: RegSP, inst: IDIVL, exp: []byte{0xf7, 0xfc}}, - {name: "IDIVL/reg=BP/", reg: RegBP, inst: IDIVL, exp: []byte{0xf7, 0xfd}}, - {name: "IDIVL/reg=SI/", reg: RegSI, inst: IDIVL, exp: []byte{0xf7, 0xfe}}, - {name: "IDIVL/reg=DI/", reg: RegDI, inst: IDIVL, exp: []byte{0xf7, 0xff}}, - {name: "IDIVL/reg=R8/", reg: RegR8, inst: IDIVL, exp: []byte{0x41, 0xf7, 0xf8}}, - {name: "IDIVL/reg=R9/", reg: RegR9, inst: IDIVL, exp: []byte{0x41, 0xf7, 0xf9}}, - {name: "IDIVL/reg=R13/", reg: RegR13, inst: IDIVL, exp: []byte{0x41, 0xf7, 0xfd}}, - {name: "IDIVL/reg=R14/", reg: RegR14, inst: IDIVL, exp: []byte{0x41, 0xf7, 0xfe}}, - {name: "IDIVL/reg=R15/", reg: RegR15, inst: IDIVL, exp: []byte{0x41, 0xf7, 0xff}}, - {name: "IDIVQ/reg=AX/", reg: RegAX, inst: IDIVQ, exp: []byte{0x48, 0xf7, 0xf8}}, - {name: "IDIVQ/reg=BX/", reg: RegBX, inst: IDIVQ, exp: []byte{0x48, 0xf7, 0xfb}}, - {name: "IDIVQ/reg=SP/", reg: RegSP, inst: IDIVQ, exp: []byte{0x48, 0xf7, 0xfc}}, - {name: "IDIVQ/reg=BP/", reg: RegBP, inst: IDIVQ, exp: []byte{0x48, 0xf7, 0xfd}}, - {name: "IDIVQ/reg=SI/", reg: RegSI, inst: IDIVQ, exp: []byte{0x48, 0xf7, 0xfe}}, - {name: "IDIVQ/reg=DI/", reg: RegDI, inst: IDIVQ, exp: []byte{0x48, 0xf7, 0xff}}, - {name: "IDIVQ/reg=R8/", reg: RegR8, inst: IDIVQ, exp: []byte{0x49, 0xf7, 0xf8}}, - {name: "IDIVQ/reg=R9/", reg: RegR9, inst: IDIVQ, exp: []byte{0x49, 0xf7, 0xf9}}, - {name: "IDIVQ/reg=R13/", reg: RegR13, inst: IDIVQ, exp: []byte{0x49, 0xf7, 0xfd}}, - {name: "IDIVQ/reg=R14/", reg: RegR14, inst: IDIVQ, exp: []byte{0x49, 0xf7, 0xfe}}, - {name: "IDIVQ/reg=R15/", reg: RegR15, inst: IDIVQ, exp: []byte{0x49, 0xf7, 0xff}}, - {name: "MULL/reg=AX/", reg: RegAX, inst: MULL, exp: []byte{0xf7, 0xe0}}, - {name: "MULL/reg=BX/", reg: RegBX, inst: MULL, exp: []byte{0xf7, 0xe3}}, - {name: "MULL/reg=SP/", reg: RegSP, inst: MULL, exp: []byte{0xf7, 0xe4}}, - {name: "MULL/reg=BP/", reg: RegBP, inst: MULL, exp: []byte{0xf7, 0xe5}}, - {name: "MULL/reg=SI/", reg: RegSI, inst: MULL, exp: []byte{0xf7, 0xe6}}, - {name: "MULL/reg=DI/", reg: RegDI, inst: MULL, exp: []byte{0xf7, 0xe7}}, - {name: "MULL/reg=R8/", reg: RegR8, inst: MULL, exp: []byte{0x41, 0xf7, 0xe0}}, - {name: "MULL/reg=R9/", reg: RegR9, inst: MULL, exp: []byte{0x41, 0xf7, 0xe1}}, - {name: "MULL/reg=R13/", reg: RegR13, inst: MULL, exp: []byte{0x41, 0xf7, 0xe5}}, - {name: "MULL/reg=R14/", reg: RegR14, inst: MULL, exp: []byte{0x41, 0xf7, 0xe6}}, - {name: "MULL/reg=R15/", reg: RegR15, inst: MULL, exp: []byte{0x41, 0xf7, 0xe7}}, - {name: "MULQ/reg=AX/", reg: RegAX, inst: MULQ, exp: []byte{0x48, 0xf7, 0xe0}}, - {name: "MULQ/reg=BX/", reg: RegBX, inst: MULQ, exp: []byte{0x48, 0xf7, 0xe3}}, - {name: "MULQ/reg=SP/", reg: RegSP, inst: MULQ, exp: []byte{0x48, 0xf7, 0xe4}}, - {name: "MULQ/reg=BP/", reg: RegBP, inst: MULQ, exp: []byte{0x48, 0xf7, 0xe5}}, - {name: "MULQ/reg=SI/", reg: RegSI, inst: MULQ, exp: []byte{0x48, 0xf7, 0xe6}}, - {name: "MULQ/reg=DI/", reg: RegDI, inst: MULQ, exp: []byte{0x48, 0xf7, 0xe7}}, - {name: "MULQ/reg=R8/", reg: RegR8, inst: MULQ, exp: []byte{0x49, 0xf7, 0xe0}}, - {name: "MULQ/reg=R9/", reg: RegR9, inst: MULQ, exp: []byte{0x49, 0xf7, 0xe1}}, - {name: "MULQ/reg=R13/", reg: RegR13, inst: MULQ, exp: []byte{0x49, 0xf7, 0xe5}}, - {name: "MULQ/reg=R14/", reg: RegR14, inst: MULQ, exp: []byte{0x49, 0xf7, 0xe6}}, - {name: "MULQ/reg=R15/", reg: RegR15, inst: MULQ, exp: []byte{0x49, 0xf7, 0xe7}}, - } - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - for _, tc := range tests { - a := NewAssembler() - buf := code.NextCodeSection() - err := a.encodeRegisterToNone(buf, &nodeImpl{ - instruction: tc.inst, - types: operandTypesRegisterToNone, srcReg: tc.reg, - }) - require.NoError(t, err, tc.name) - require.Equal(t, tc.exp, buf.Bytes(), tc.name) - } -} - -func TestAssemblerImpl_EncodeRegisterToRegister(t *testing.T) { - t.Run("error", func(t *testing.T) { - tests := []struct { - n *nodeImpl - expErr string - }{ - { - n: &nodeImpl{instruction: JMP, types: operandTypesRegisterToRegister, srcReg: RegAX, dstReg: RegAX}, - expErr: "JMP is unsupported for RegisterToRegister type", - }, - } - - for _, tc := range tests { - t.Run(tc.expErr, func(t *testing.T) { - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - a := NewAssembler() - buf := code.NextCodeSection() - err := a.encodeRegisterToRegister(buf, tc.n) - require.EqualError(t, err, tc.expErr) - }) - } - }) - - tests := []struct { - name string - n *nodeImpl - exp []byte - }{ - {name: "MOVDQU", n: &nodeImpl{instruction: MOVDQU, srcReg: RegX3, dstReg: RegX10}, exp: []byte{0xf3, 0x44, 0xf, 0x6f, 0xd3}}, - {name: "MOVDQU", n: &nodeImpl{instruction: MOVDQU, srcReg: RegX10, dstReg: RegX3}, exp: []byte{0xf3, 0x41, 0xf, 0x6f, 0xda}}, - {name: "MOVDQU", n: &nodeImpl{instruction: MOVDQU, srcReg: RegX10, dstReg: RegX15}, exp: []byte{0xf3, 0x45, 0xf, 0x6f, 0xfa}}, - {name: "MOVDQA", n: &nodeImpl{instruction: MOVDQA, srcReg: RegX3, dstReg: RegX10}, exp: []byte{0x66, 0x44, 0xf, 0x6f, 0xd3}}, - {name: "MOVDQA", n: &nodeImpl{instruction: MOVDQA, srcReg: RegX10, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x6f, 0xda}}, - {name: "MOVDQA", n: &nodeImpl{instruction: MOVDQA, srcReg: RegX10, dstReg: RegX15}, exp: []byte{0x66, 0x45, 0xf, 0x6f, 0xfa}}, - {name: "PACKSSWB", n: &nodeImpl{instruction: PACKSSWB, srcReg: RegX10, dstReg: RegX15}, exp: []byte{0x66, 0x45, 0xf, 0x63, 0xfa}}, - {name: "pmovmskb r15d, xmm10", n: &nodeImpl{instruction: PMOVMSKB, srcReg: RegX10, dstReg: RegR15}, exp: []byte{0x66, 0x45, 0xf, 0xd7, 0xfa}}, - {name: "movmskps eax, xmm10", n: &nodeImpl{instruction: MOVMSKPS, srcReg: RegX10, dstReg: RegAX}, exp: []byte{0x41, 0xf, 0x50, 0xc2}}, - {name: "movmskps r13d, xmm1", n: &nodeImpl{instruction: MOVMSKPS, srcReg: RegX1, dstReg: RegR13}, exp: []byte{0x44, 0xf, 0x50, 0xe9}}, - {name: "movmskpd eax, xmm10", n: &nodeImpl{instruction: MOVMSKPD, srcReg: RegX10, dstReg: RegAX}, exp: []byte{0x66, 0x41, 0xf, 0x50, 0xc2}}, - {name: "movmskpd r15d, xmm1", n: &nodeImpl{instruction: MOVMSKPD, srcReg: RegX1, dstReg: RegR15}, exp: []byte{0x66, 0x44, 0xf, 0x50, 0xf9}}, - {name: "pand xmm15, xmm1", n: &nodeImpl{instruction: PAND, srcReg: RegX1, dstReg: RegX15}, exp: []byte{0x66, 0x44, 0xf, 0xdb, 0xf9}}, - {name: "por xmm1, xmm15", n: &nodeImpl{instruction: POR, srcReg: RegX15, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0xeb, 0xcf}}, - {name: "pandn xmm13, xmm15", n: &nodeImpl{instruction: PANDN, srcReg: RegX15, dstReg: RegX13}, exp: []byte{0x66, 0x45, 0xf, 0xdf, 0xef}}, - {name: "psrad xmm13, xmm15", n: &nodeImpl{instruction: PSRAD, srcReg: RegX15, dstReg: RegX13}, exp: []byte{0x66, 0x45, 0xf, 0xe2, 0xef}}, - {name: "psraw xmm1, xmm1", n: &nodeImpl{instruction: PSRAW, srcReg: RegX1, dstReg: RegX1}, exp: []byte{0x66, 0xf, 0xe1, 0xc9}}, - {name: "psrlq xmm14, xmm14", n: &nodeImpl{instruction: PSRLQ, srcReg: RegX14, dstReg: RegX14}, exp: []byte{0x66, 0x45, 0xf, 0xd3, 0xf6}}, - {name: "psrld xmm3, xmm3", n: &nodeImpl{instruction: PSRLD, srcReg: RegX3, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0xd2, 0xdb}}, - {name: "psrlw xmm15, xmm1", n: &nodeImpl{instruction: PSRLW, srcReg: RegX1, dstReg: RegX15}, exp: []byte{0x66, 0x44, 0xf, 0xd1, 0xf9}}, - {name: "psllw xmm1, xmm15", n: &nodeImpl{instruction: PSLLW, srcReg: RegX15, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0xf1, 0xcf}}, - {name: "punpcklbw xmm1, xmm15", n: &nodeImpl{instruction: PUNPCKLBW, srcReg: RegX15, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0x60, 0xcf}}, - {name: "punpckhbw xmm11, xmm1", n: &nodeImpl{instruction: PUNPCKHBW, srcReg: RegX1, dstReg: RegX11}, exp: []byte{0x66, 0x44, 0xf, 0x68, 0xd9}}, - {name: "pslld xmm11, xmm1", n: &nodeImpl{instruction: PSLLD, srcReg: RegX1, dstReg: RegX11}, exp: []byte{0x66, 0x44, 0xf, 0xf2, 0xd9}}, - {name: "psllq xmm11, xmm15", n: &nodeImpl{instruction: PSLLQ, srcReg: RegX15, dstReg: RegX11}, exp: []byte{0x66, 0x45, 0xf, 0xf3, 0xdf}}, - { - name: "cmpeqps xmm11, xmm15", n: &nodeImpl{instruction: CMPPS, srcReg: RegX15, dstReg: RegX11, arg: 0}, // CMPPS with arg=0 == Pseudo-Op CMPEQPS. - exp: []byte{0x45, 0xf, 0xc2, 0xdf, 0x0}, - }, - { - name: "cmpordps xmm1, xmm5", n: &nodeImpl{instruction: CMPPS, srcReg: RegX5, dstReg: RegX1, arg: 7}, // CMPPS with arg=7 == Pseudo-Op CMPORDPS. - exp: []byte{0xf, 0xc2, 0xcd, 0x7}, - }, - {name: "cmplepd xmm11, xmm15", n: &nodeImpl{instruction: CMPPD, srcReg: RegX15, dstReg: RegX11, arg: 2}, // CMPPD with arg=2 == Pseudo-Op CMPLEPD. - exp: []byte{0x66, 0x45, 0xf, 0xc2, 0xdf, 0x2}}, - { - name: "cmpneqpd xmm1, xmm5", n: &nodeImpl{instruction: CMPPD, srcReg: RegX5, dstReg: RegX1, arg: 4}, // CMPPD with arg=4 == Pseudo-Op CMPNEQPD. - exp: []byte{0x66, 0xf, 0xc2, 0xcd, 0x4}, - }, - {name: "pcmpgtq xmm10, xmm3", n: &nodeImpl{instruction: PCMPGTQ, srcReg: RegX3, dstReg: RegX10}, exp: []byte{0x66, 0x44, 0xf, 0x38, 0x37, 0xd3}}, - {name: "pcmpgtd xmm10, xmm3", n: &nodeImpl{instruction: PCMPGTD, srcReg: RegX3, dstReg: RegX10}, exp: []byte{0x66, 0x44, 0xf, 0x66, 0xd3}}, - {name: "pminsd xmm10, xmm3", n: &nodeImpl{instruction: PMINSD, srcReg: RegX3, dstReg: RegX10}, exp: []byte{0x66, 0x44, 0xf, 0x38, 0x39, 0xd3}}, - {name: "pmaxsd xmm1, xmm12", n: &nodeImpl{instruction: PMAXSD, srcReg: RegX12, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x3d, 0xcc}}, - {name: "pmaxsw xmm1, xmm12", n: &nodeImpl{instruction: PMAXSW, srcReg: RegX12, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0xee, 0xcc}}, - {name: "pminsw xmm1, xmm12", n: &nodeImpl{instruction: PMINSW, srcReg: RegX12, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0xea, 0xcc}}, - {name: "pcmpgtb xmm1, xmm12", n: &nodeImpl{instruction: PCMPGTB, srcReg: RegX12, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0x64, 0xcc}}, - {name: "pminsb xmm1, xmm12", n: &nodeImpl{instruction: PMINSB, srcReg: RegX12, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x38, 0xcc}}, - {name: "pmaxsb xmm1, xmm2", n: &nodeImpl{instruction: PMAXSB, srcReg: RegX2, dstReg: RegX1}, exp: []byte{0x66, 0xf, 0x38, 0x3c, 0xca}}, - {name: "pminud xmm1, xmm2", n: &nodeImpl{instruction: PMINUD, srcReg: RegX2, dstReg: RegX1}, exp: []byte{0x66, 0xf, 0x38, 0x3b, 0xca}}, - {name: "pminuw xmm1, xmm2", n: &nodeImpl{instruction: PMINUW, srcReg: RegX2, dstReg: RegX1}, exp: []byte{0x66, 0xf, 0x38, 0x3a, 0xca}}, - {name: "pminub xmm1, xmm2", n: &nodeImpl{instruction: PMINUB, srcReg: RegX2, dstReg: RegX1}, exp: []byte{0x66, 0xf, 0xda, 0xca}}, - {name: "pmaxud xmm1, xmm2", n: &nodeImpl{instruction: PMAXUD, srcReg: RegX2, dstReg: RegX1}, exp: []byte{0x66, 0xf, 0x38, 0x3f, 0xca}}, - {name: "pmaxuw xmm1, xmm2", n: &nodeImpl{instruction: PMAXUW, srcReg: RegX2, dstReg: RegX1}, exp: []byte{0x66, 0xf, 0x38, 0x3e, 0xca}}, - {name: "pmaxub xmm1, xmm2", n: &nodeImpl{instruction: PMAXUB, srcReg: RegX2, dstReg: RegX1}, exp: []byte{0x66, 0xf, 0xde, 0xca}}, - {name: "pcmpgtw xmm1, xmm2", n: &nodeImpl{instruction: PCMPGTW, srcReg: RegX2, dstReg: RegX1}, exp: []byte{0x66, 0xf, 0x65, 0xca}}, - {name: "pmullw xmm13, xmm1", n: &nodeImpl{instruction: PMULLW, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0xd5, 0xe9}}, - {name: "pmulld xmm1, xmm11", n: &nodeImpl{instruction: PMULLD, srcReg: RegX11, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x40, 0xcb}}, - {name: "pmuludq xmm13, xmm1", n: &nodeImpl{instruction: PMULUDQ, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0xf4, 0xe9}}, - {name: "psubsb xmm13, xmm1", n: &nodeImpl{instruction: PSUBSB, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0xe8, 0xe9}}, - {name: "psubsw xmm13, xmm1", n: &nodeImpl{instruction: PSUBSW, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0xe9, 0xe9}}, - {name: "psubusb xmm13, xmm1", n: &nodeImpl{instruction: PSUBUSB, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0xd8, 0xe9}}, - {name: "psubusw xmm13, xmm1", n: &nodeImpl{instruction: PSUBUSW, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0xd9, 0xe9}}, - {name: "paddsw xmm13, xmm1", n: &nodeImpl{instruction: PADDSW, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0xed, 0xe9}}, - {name: "paddsb xmm13, xmm1", n: &nodeImpl{instruction: PADDSB, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0xec, 0xe9}}, - {name: "paddusw xmm13, xmm1", n: &nodeImpl{instruction: PADDUSW, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0xdd, 0xe9}}, - {name: "pavgb xmm13, xmm1", n: &nodeImpl{instruction: PAVGB, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0xe0, 0xe9}}, - {name: "pavgw xmm13, xmm1", n: &nodeImpl{instruction: PAVGW, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0xe3, 0xe9}}, - {name: "pabsb xmm13, xmm1", n: &nodeImpl{instruction: PABSB, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x38, 0x1c, 0xe9}}, - {name: "pabsw xmm13, xmm1", n: &nodeImpl{instruction: PABSW, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x38, 0x1d, 0xe9}}, - {name: "pabsd xmm13, xmm1", n: &nodeImpl{instruction: PABSD, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x38, 0x1e, 0xe9}}, - {name: "blendvpd xmm13, xmm1", n: &nodeImpl{instruction: BLENDVPD, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x38, 0x15, 0xe9}}, - {name: "maxpd xmm13, xmm1", n: &nodeImpl{instruction: MAXPD, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x5f, 0xe9}}, - {name: "maxps xmm13, xmm1", n: &nodeImpl{instruction: MAXPS, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x44, 0xf, 0x5f, 0xe9}}, - {name: "minpd xmm13, xmm1", n: &nodeImpl{instruction: MINPD, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x5d, 0xe9}}, - {name: "minps xmm13, xmm1", n: &nodeImpl{instruction: MINPS, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x44, 0xf, 0x5d, 0xe9}}, - {name: "andnpd xmm13, xmm1", n: &nodeImpl{instruction: ANDNPD, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x55, 0xe9}}, - {name: "andnps xmm13, xmm1", n: &nodeImpl{instruction: ANDNPS, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x44, 0xf, 0x55, 0xe9}}, - {name: "mulps xmm13, xmm1", n: &nodeImpl{instruction: MULPS, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x44, 0xf, 0x59, 0xe9}}, - {name: "mulpd xmm13, xmm1", n: &nodeImpl{instruction: MULPD, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x59, 0xe9}}, - {name: "divps xmm13, xmm1", n: &nodeImpl{instruction: DIVPS, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x44, 0xf, 0x5e, 0xe9}}, - {name: "divpd xmm13, xmm1", n: &nodeImpl{instruction: DIVPD, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x5e, 0xe9}}, - {name: "sqrtps xmm13, xmm1", n: &nodeImpl{instruction: SQRTPS, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x44, 0xf, 0x51, 0xe9}}, - {name: "sqrtpd xmm13, xmm1", n: &nodeImpl{instruction: SQRTPD, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x51, 0xe9}}, - {name: "roundps xmm13, xmm1, 0", n: &nodeImpl{instruction: ROUNDPS, srcReg: RegX1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x8, 0xe9, 0x0}}, - {name: "roundps xmm13, xmm1, 1", n: &nodeImpl{instruction: ROUNDPS, srcReg: RegX1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x8, 0xe9, 0x1}}, - {name: "roundps xmm13, xmm1, 3", n: &nodeImpl{instruction: ROUNDPS, srcReg: RegX1, dstReg: RegX13, arg: 3}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x8, 0xe9, 0x3}}, - {name: "roundpd xmm13, xmm1, 0", n: &nodeImpl{instruction: ROUNDPD, srcReg: RegX1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x9, 0xe9, 0x0}}, - {name: "roundpd xmm13, xmm1, 1", n: &nodeImpl{instruction: ROUNDPD, srcReg: RegX1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x9, 0xe9, 0x1}}, - {name: "roundpd xmm13, xmm1, 3", n: &nodeImpl{instruction: ROUNDPD, srcReg: RegX1, dstReg: RegX13, arg: 3}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x9, 0xe9, 0x3}}, - {name: "palignr xmm13, xmm1, 3", n: &nodeImpl{instruction: PALIGNR, srcReg: RegX1, dstReg: RegX13, arg: 3}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0xf, 0xe9, 0x3}}, - {name: "punpcklwd xmm13, xmm1", n: &nodeImpl{instruction: PUNPCKLWD, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x61, 0xe9}}, - {name: "punpckhwd xmm13, xmm1", n: &nodeImpl{instruction: PUNPCKHWD, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x69, 0xe9}}, - {name: "pmulhuw xmm13, xmm1", n: &nodeImpl{instruction: PMULHUW, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0xe4, 0xe9}}, - {name: "pmuldq xmm13, xmm1", n: &nodeImpl{instruction: PMULDQ, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x38, 0x28, 0xe9}}, - {name: "pmulhrsw xmm13, xmm1", n: &nodeImpl{instruction: PMULHRSW, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x38, 0xb, 0xe9}}, - {name: "pmovsxbw xmm5, xmm10", n: &nodeImpl{instruction: PMOVSXBW, srcReg: RegX10, dstReg: RegX5}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x20, 0xea}}, - {name: "pmovsxwd xmm5, xmm10", n: &nodeImpl{instruction: PMOVSXWD, srcReg: RegX10, dstReg: RegX5}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x23, 0xea}}, - {name: "pmovsxdq xmm5, xmm10", n: &nodeImpl{instruction: PMOVSXDQ, srcReg: RegX10, dstReg: RegX5}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x25, 0xea}}, - {name: "pmovzxbw xmm5, xmm10", n: &nodeImpl{instruction: PMOVZXBW, srcReg: RegX10, dstReg: RegX5}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x30, 0xea}}, - {name: "pmovzxwd xmm5, xmm10", n: &nodeImpl{instruction: PMOVZXWD, srcReg: RegX10, dstReg: RegX5}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x33, 0xea}}, - {name: "pmovzxdq xmm5, xmm10", n: &nodeImpl{instruction: PMOVZXDQ, srcReg: RegX10, dstReg: RegX5}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x35, 0xea}}, - {name: "pmulhw xmm2, xmm1", n: &nodeImpl{instruction: PMULHW, srcReg: RegX1, dstReg: RegX2}, exp: []byte{0x66, 0xf, 0xe5, 0xd1}}, - {name: "cmpltps xmm1, xmm14", n: &nodeImpl{instruction: CMPEQPS, srcReg: RegX14, dstReg: RegX1, arg: 1}, exp: []byte{0x41, 0xf, 0xc2, 0xce, 0x1}}, - {name: "cmpunordpd xmm1, xmm14", n: &nodeImpl{instruction: CMPEQPD, srcReg: RegX14, dstReg: RegX1, arg: 3}, exp: []byte{0x66, 0x41, 0xf, 0xc2, 0xce, 0x3}}, - {name: "cvttps2dq xmm1, xmm14", n: &nodeImpl{instruction: CVTTPS2DQ, srcReg: RegX14, dstReg: RegX1}, exp: []byte{0xf3, 0x41, 0xf, 0x5b, 0xce}}, - {name: "cvtdq2ps xmm1, xmm14", n: &nodeImpl{instruction: CVTDQ2PS, srcReg: RegX14, dstReg: RegX1}, exp: []byte{0x41, 0xf, 0x5b, 0xce}}, - {name: "movupd xmm1, xmm14", n: &nodeImpl{instruction: MOVUPD, srcReg: RegX14, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0x10, 0xce}}, - {name: "shufps xmm1, xmm14, 5", n: &nodeImpl{instruction: SHUFPS, srcReg: RegX14, dstReg: RegX1, arg: 5}, exp: []byte{0x41, 0xf, 0xc6, 0xce, 0x5}}, - {name: "pmaddwd xmm1, xmm14", n: &nodeImpl{instruction: PMADDWD, srcReg: RegX14, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0xf5, 0xce}}, - {name: "cvtdq2pd xmm1, xmm14", n: &nodeImpl{instruction: CVTDQ2PD, srcReg: RegX14, dstReg: RegX1}, exp: []byte{0xf3, 0x41, 0xf, 0xe6, 0xce}}, - {name: "unpcklps xmm1, xmm14", n: &nodeImpl{instruction: UNPCKLPS, srcReg: RegX14, dstReg: RegX1}, exp: []byte{0x41, 0xf, 0x14, 0xce}}, - {name: "packuswb xmm1, xmm14", n: &nodeImpl{instruction: PACKUSWB, srcReg: RegX14, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0x67, 0xce}}, - {name: "packssdw xmm1, xmm14", n: &nodeImpl{instruction: PACKSSDW, srcReg: RegX14, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0x6b, 0xce}}, - {name: "packusdw xmm1, xmm14", n: &nodeImpl{instruction: PACKUSDW, srcReg: RegX14, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x2b, 0xce}}, - {name: "cvtps2pd xmm1, xmm14", n: &nodeImpl{instruction: CVTPS2PD, srcReg: RegX14, dstReg: RegX1}, exp: []byte{0x41, 0xf, 0x5a, 0xce}}, - {name: "cvtpd2ps xmm1, xmm14", n: &nodeImpl{instruction: CVTPD2PS, srcReg: RegX14, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0x5a, 0xce}}, - {name: "pmaddubsw xmm1, xmm14", n: &nodeImpl{instruction: PMADDUBSW, srcReg: RegX14, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x4, 0xce}}, - {name: "cvttpd2dq xmm1, xmm14", n: &nodeImpl{instruction: CVTTPD2DQ, srcReg: RegX14, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0xe6, 0xce}}, - {name: "PADDB/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PADDB, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0xfc, 0xc0}}, - {name: "PADDB/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PADDB, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0xfc, 0xc0}}, - {name: "PADDB/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PADDB, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0xfc, 0xc0}}, - {name: "PADDB/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PADDB, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0xfc, 0xc0}}, - {name: "PADDW/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PADDW, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0xfd, 0xc0}}, - {name: "PADDW/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PADDW, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0xfd, 0xc0}}, - {name: "PADDW/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PADDW, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0xfd, 0xc0}}, - {name: "PADDW/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PADDW, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0xfd, 0xc0}}, - {name: "PADDD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PADDD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0xfe, 0xc0}}, - {name: "PADDD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PADDD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0xfe, 0xc0}}, - {name: "PADDD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PADDD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0xfe, 0xc0}}, - {name: "PADDD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PADDD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0xfe, 0xc0}}, - {name: "PADDQ/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PADDQ, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0xd4, 0xc0}}, - {name: "PADDQ/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PADDQ, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0xd4, 0xc0}}, - {name: "PADDQ/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PADDQ, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0xd4, 0xc0}}, - {name: "PADDQ/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PADDQ, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0xd4, 0xc0}}, - {name: "ADDPS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: ADDPS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf, 0x58, 0xc0}}, - {name: "ADDPS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: ADDPS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x44, 0xf, 0x58, 0xc0}}, - {name: "ADDPS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: ADDPS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x41, 0xf, 0x58, 0xc0}}, - {name: "ADDPS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: ADDPS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x45, 0xf, 0x58, 0xc0}}, - {name: "ADDPD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: ADDPD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x58, 0xc0}}, - {name: "ADDPD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: ADDPD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x58, 0xc0}}, - {name: "ADDPD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: ADDPD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x58, 0xc0}}, - {name: "ADDPD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: ADDPD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x58, 0xc0}}, - {name: "PSUBB/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PSUBB, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0xf8, 0xc0}}, - {name: "PSUBB/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PSUBB, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0xf8, 0xc0}}, - {name: "PSUBB/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PSUBB, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0xf8, 0xc0}}, - {name: "PSUBB/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PSUBB, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0xf8, 0xc0}}, - {name: "PSUBW/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PSUBW, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0xf9, 0xc0}}, - {name: "PSUBW/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PSUBW, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0xf9, 0xc0}}, - {name: "PSUBW/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PSUBW, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0xf9, 0xc0}}, - {name: "PSUBW/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PSUBW, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0xf9, 0xc0}}, - {name: "PSUBL/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PSUBD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0xfa, 0xc0}}, - {name: "PSUBL/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PSUBD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0xfa, 0xc0}}, - {name: "PSUBL/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PSUBD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0xfa, 0xc0}}, - {name: "PSUBL/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PSUBD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0xfa, 0xc0}}, - {name: "PSUBQ/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PSUBQ, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0xfb, 0xc0}}, - {name: "PSUBQ/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PSUBQ, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0xfb, 0xc0}}, - {name: "PSUBQ/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PSUBQ, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0xfb, 0xc0}}, - {name: "PSUBQ/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PSUBQ, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0xfb, 0xc0}}, - {name: "SUBPS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: SUBPS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf, 0x5c, 0xc0}}, - {name: "SUBPS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: SUBPS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x44, 0xf, 0x5c, 0xc0}}, - {name: "SUBPS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: SUBPS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x41, 0xf, 0x5c, 0xc0}}, - {name: "SUBPS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: SUBPS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x45, 0xf, 0x5c, 0xc0}}, - {name: "SUBPD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: SUBPD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x5c, 0xc0}}, - {name: "SUBPD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: SUBPD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x5c, 0xc0}}, - {name: "SUBPD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: SUBPD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x5c, 0xc0}}, - {name: "SUBPD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: SUBPD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x5c, 0xc0}}, - {name: "PINSRQ/src=AX/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0xc0, 0x1}}, - {name: "PINSRQ/src=AX/dst=X8/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xc0, 0x1}}, - {name: "PINSRQ/src=R8/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegR8, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0x49, 0xf, 0x3a, 0x22, 0xc0, 0x1}}, - {name: "PINSRQ/src=R8/dst=X8/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegR8, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x4d, 0xf, 0x3a, 0x22, 0xc0, 0x1}}, - {name: "PINSRQ/src=AX/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0xc0, 0x0}}, - {name: "PINSRQ/src=AX/dst=X8/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xc0, 0x0}}, - {name: "PINSRQ/src=R8/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegR8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x49, 0xf, 0x3a, 0x22, 0xc0, 0x0}}, - {name: "PINSRQ/src=R8/dst=X8/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegR8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x4d, 0xf, 0x3a, 0x22, 0xc0, 0x0}}, - {name: "PINSRD/src=AX/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0xc0, 0x1}}, - {name: "PINSRD/src=AX/dst=X8/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xc0, 0x1}}, - {name: "PINSRD/src=R8/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegR8, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0x22, 0xc0, 0x1}}, - {name: "PINSRD/src=R8/dst=X8/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegR8, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0x22, 0xc0, 0x1}}, - {name: "PINSRD/src=AX/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0xc0, 0x0}}, - {name: "PINSRD/src=AX/dst=X8/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xc0, 0x0}}, - {name: "PINSRD/src=R8/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegR8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0x22, 0xc0, 0x0}}, - {name: "PINSRD/src=R8/dst=X8/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegR8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0x22, 0xc0, 0x0}}, - {name: "PINSRW/src=AX/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0xf, 0xc4, 0xc0, 0x1}}, - {name: "PINSRW/src=AX/dst=X8/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xc0, 0x1}}, - {name: "PINSRW/src=R8/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegR8, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0x41, 0xf, 0xc4, 0xc0, 0x1}}, - {name: "PINSRW/src=R8/dst=X8/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegR8, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x45, 0xf, 0xc4, 0xc0, 0x1}}, - {name: "PINSRW/src=AX/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0xc4, 0xc0, 0x0}}, - {name: "PINSRW/src=AX/dst=X8/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xc0, 0x0}}, - {name: "PINSRW/src=R8/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegR8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0xc4, 0xc0, 0x0}}, - {name: "PINSRW/src=R8/dst=X8/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegR8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0xc4, 0xc0, 0x0}}, - {name: "PINSRB/src=AX/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0xc0, 0x1}}, - {name: "PINSRB/src=AX/dst=X8/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xc0, 0x1}}, - {name: "PINSRB/src=R8/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegR8, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0x20, 0xc0, 0x1}}, - {name: "PINSRB/src=R8/dst=X8/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegR8, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0x20, 0xc0, 0x1}}, - {name: "PINSRB/src=AX/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0xc0, 0x0}}, - {name: "PINSRB/src=AX/dst=X8/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xc0, 0x0}}, - {name: "PINSRB/src=R8/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegR8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0x20, 0xc0, 0x0}}, - {name: "PINSRB/src=R8/dst=X8/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegR8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0x20, 0xc0, 0x0}}, - {name: "ADDL/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: ADDL, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x1, 0xc0}}, - {name: "ADDL/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: ADDL, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x41, 0x1, 0xc0}}, - {name: "ADDL/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: ADDL, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x44, 0x1, 0xc0}}, - {name: "ADDL/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: ADDL, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x45, 0x1, 0xc0}}, - {name: "ADDQ/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: ADDQ, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0x1, 0xc0}}, - {name: "ADDQ/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: ADDQ, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x49, 0x1, 0xc0}}, - {name: "ADDQ/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: ADDQ, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x4c, 0x1, 0xc0}}, - {name: "ADDQ/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: ADDQ, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0x1, 0xc0}}, - {name: "ADDSD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: ADDSD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0xf, 0x58, 0xc0}}, - {name: "ADDSD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: ADDSD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x44, 0xf, 0x58, 0xc0}}, - {name: "ADDSD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: ADDSD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0x41, 0xf, 0x58, 0xc0}}, - {name: "ADDSD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: ADDSD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x45, 0xf, 0x58, 0xc0}}, - {name: "ADDSS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: ADDSS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0xf, 0x58, 0xc0}}, - {name: "ADDSS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: ADDSS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0x58, 0xc0}}, - {name: "ADDSS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: ADDSS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0x58, 0xc0}}, - {name: "ADDSS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: ADDSS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0x58, 0xc0}}, - {name: "ANDL/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: ANDL, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x21, 0xc0}}, - {name: "ANDL/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: ANDL, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x41, 0x21, 0xc0}}, - {name: "ANDL/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: ANDL, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x44, 0x21, 0xc0}}, - {name: "ANDL/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: ANDL, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x45, 0x21, 0xc0}}, - {name: "ANDPD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: ANDPD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x54, 0xc0}}, - {name: "ANDPD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: ANDPD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x54, 0xc0}}, - {name: "ANDPD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: ANDPD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x54, 0xc0}}, - {name: "ANDPD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: ANDPD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x54, 0xc0}}, - {name: "ANDPS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: ANDPS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf, 0x54, 0xc0}}, - {name: "ANDPS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: ANDPS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x44, 0xf, 0x54, 0xc0}}, - {name: "ANDPS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: ANDPS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x41, 0xf, 0x54, 0xc0}}, - {name: "ANDPS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: ANDPS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x45, 0xf, 0x54, 0xc0}}, - {name: "ANDQ/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: ANDQ, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0x21, 0xc0}}, - {name: "ANDQ/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: ANDQ, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x49, 0x21, 0xc0}}, - {name: "ANDQ/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: ANDQ, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x4c, 0x21, 0xc0}}, - {name: "ANDQ/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: ANDQ, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0x21, 0xc0}}, - {name: "BSRL/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: BSRL, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf, 0xbd, 0xc0}}, - {name: "BSRL/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: BSRL, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x44, 0xf, 0xbd, 0xc0}}, - {name: "BSRL/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: BSRL, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x41, 0xf, 0xbd, 0xc0}}, - {name: "BSRL/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: BSRL, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x45, 0xf, 0xbd, 0xc0}}, - {name: "BSRQ/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: BSRQ, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0xf, 0xbd, 0xc0}}, - {name: "BSRQ/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: BSRQ, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4c, 0xf, 0xbd, 0xc0}}, - {name: "BSRQ/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: BSRQ, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x49, 0xf, 0xbd, 0xc0}}, - {name: "BSRQ/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: BSRQ, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0xf, 0xbd, 0xc0}}, - {name: "CMOVQCS/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: CMOVQCS, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0xf, 0x42, 0xc0}}, - {name: "CMOVQCS/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: CMOVQCS, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4c, 0xf, 0x42, 0xc0}}, - {name: "CMOVQCS/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: CMOVQCS, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x49, 0xf, 0x42, 0xc0}}, - {name: "CMOVQCS/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: CMOVQCS, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0xf, 0x42, 0xc0}}, - {name: "CMPL/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: CMPL, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x39, 0xc0}}, - {name: "CMPL/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: CMPL, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x44, 0x39, 0xc0}}, - {name: "CMPL/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: CMPL, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x41, 0x39, 0xc0}}, - {name: "CMPL/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: CMPL, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x45, 0x39, 0xc0}}, - {name: "CMPQ/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: CMPQ, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0x39, 0xc0}}, - {name: "CMPQ/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: CMPQ, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4c, 0x39, 0xc0}}, - {name: "CMPQ/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: CMPQ, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x49, 0x39, 0xc0}}, - {name: "CMPQ/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: CMPQ, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0x39, 0xc0}}, - {name: "COMISD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: COMISD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x2f, 0xc0}}, - {name: "COMISD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: COMISD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x2f, 0xc0}}, - {name: "COMISD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: COMISD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x2f, 0xc0}}, - {name: "COMISD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: COMISD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x2f, 0xc0}}, - {name: "COMISS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: COMISS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf, 0x2f, 0xc0}}, - {name: "COMISS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: COMISS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x44, 0xf, 0x2f, 0xc0}}, - {name: "COMISS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: COMISS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x41, 0xf, 0x2f, 0xc0}}, - {name: "COMISS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: COMISS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x45, 0xf, 0x2f, 0xc0}}, - {name: "CVTSD2SS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: CVTSD2SS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0xf, 0x5a, 0xc0}}, - {name: "CVTSD2SS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: CVTSD2SS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x44, 0xf, 0x5a, 0xc0}}, - {name: "CVTSD2SS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: CVTSD2SS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0x41, 0xf, 0x5a, 0xc0}}, - {name: "CVTSD2SS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: CVTSD2SS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x45, 0xf, 0x5a, 0xc0}}, - {name: "CVTSL2SD/src=AX/dst=X0/arg=0", n: &nodeImpl{instruction: CVTSL2SD, srcReg: RegAX, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0xf, 0x2a, 0xc0}}, - {name: "CVTSL2SD/src=AX/dst=X8/arg=0", n: &nodeImpl{instruction: CVTSL2SD, srcReg: RegAX, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x44, 0xf, 0x2a, 0xc0}}, - {name: "CVTSL2SD/src=R8/dst=X0/arg=0", n: &nodeImpl{instruction: CVTSL2SD, srcReg: RegR8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0x41, 0xf, 0x2a, 0xc0}}, - {name: "CVTSL2SD/src=R8/dst=X8/arg=0", n: &nodeImpl{instruction: CVTSL2SD, srcReg: RegR8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x45, 0xf, 0x2a, 0xc0}}, - {name: "CVTSL2SS/src=AX/dst=X0/arg=0", n: &nodeImpl{instruction: CVTSL2SS, srcReg: RegAX, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0xf, 0x2a, 0xc0}}, - {name: "CVTSL2SS/src=AX/dst=X8/arg=0", n: &nodeImpl{instruction: CVTSL2SS, srcReg: RegAX, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0x2a, 0xc0}}, - {name: "CVTSL2SS/src=R8/dst=X0/arg=0", n: &nodeImpl{instruction: CVTSL2SS, srcReg: RegR8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0x2a, 0xc0}}, - {name: "CVTSL2SS/src=R8/dst=X8/arg=0", n: &nodeImpl{instruction: CVTSL2SS, srcReg: RegR8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0x2a, 0xc0}}, - {name: "CVTSQ2SD/src=AX/dst=X0/arg=0", n: &nodeImpl{instruction: CVTSQ2SD, srcReg: RegAX, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0x48, 0xf, 0x2a, 0xc0}}, - {name: "CVTSQ2SD/src=AX/dst=X8/arg=0", n: &nodeImpl{instruction: CVTSQ2SD, srcReg: RegAX, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x4c, 0xf, 0x2a, 0xc0}}, - {name: "CVTSQ2SD/src=R8/dst=X0/arg=0", n: &nodeImpl{instruction: CVTSQ2SD, srcReg: RegR8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0x49, 0xf, 0x2a, 0xc0}}, - {name: "CVTSQ2SD/src=R8/dst=X8/arg=0", n: &nodeImpl{instruction: CVTSQ2SD, srcReg: RegR8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x4d, 0xf, 0x2a, 0xc0}}, - {name: "CVTSQ2SS/src=AX/dst=X0/arg=0", n: &nodeImpl{instruction: CVTSQ2SS, srcReg: RegAX, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0x48, 0xf, 0x2a, 0xc0}}, - {name: "CVTSQ2SS/src=AX/dst=X8/arg=0", n: &nodeImpl{instruction: CVTSQ2SS, srcReg: RegAX, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x4c, 0xf, 0x2a, 0xc0}}, - {name: "CVTSQ2SS/src=R8/dst=X0/arg=0", n: &nodeImpl{instruction: CVTSQ2SS, srcReg: RegR8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0x49, 0xf, 0x2a, 0xc0}}, - {name: "CVTSQ2SS/src=R8/dst=X8/arg=0", n: &nodeImpl{instruction: CVTSQ2SS, srcReg: RegR8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x4d, 0xf, 0x2a, 0xc0}}, - {name: "CVTSS2SD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: CVTSS2SD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0xf, 0x5a, 0xc0}}, - {name: "CVTSS2SD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: CVTSS2SD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0x5a, 0xc0}}, - {name: "CVTSS2SD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: CVTSS2SD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0x5a, 0xc0}}, - {name: "CVTSS2SD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: CVTSS2SD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0x5a, 0xc0}}, - {name: "CVTTSD2SL/src=X0/dst=AX/arg=0", n: &nodeImpl{instruction: CVTTSD2SL, srcReg: RegX0, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf2, 0xf, 0x2c, 0xc0}}, - {name: "CVTTSD2SL/src=X0/dst=R8/arg=0", n: &nodeImpl{instruction: CVTTSD2SL, srcReg: RegX0, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf2, 0x44, 0xf, 0x2c, 0xc0}}, - {name: "CVTTSD2SL/src=X8/dst=AX/arg=0", n: &nodeImpl{instruction: CVTTSD2SL, srcReg: RegX8, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf2, 0x41, 0xf, 0x2c, 0xc0}}, - {name: "CVTTSD2SL/src=X8/dst=R8/arg=0", n: &nodeImpl{instruction: CVTTSD2SL, srcReg: RegX8, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf2, 0x45, 0xf, 0x2c, 0xc0}}, - {name: "CVTTSD2SQ/src=X0/dst=AX/arg=0", n: &nodeImpl{instruction: CVTTSD2SQ, srcReg: RegX0, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf2, 0x48, 0xf, 0x2c, 0xc0}}, - {name: "CVTTSD2SQ/src=X0/dst=R8/arg=0", n: &nodeImpl{instruction: CVTTSD2SQ, srcReg: RegX0, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf2, 0x4c, 0xf, 0x2c, 0xc0}}, - {name: "CVTTSD2SQ/src=X8/dst=AX/arg=0", n: &nodeImpl{instruction: CVTTSD2SQ, srcReg: RegX8, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf2, 0x49, 0xf, 0x2c, 0xc0}}, - {name: "CVTTSD2SQ/src=X8/dst=R8/arg=0", n: &nodeImpl{instruction: CVTTSD2SQ, srcReg: RegX8, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf2, 0x4d, 0xf, 0x2c, 0xc0}}, - {name: "CVTTSS2SL/src=X0/dst=AX/arg=0", n: &nodeImpl{instruction: CVTTSS2SL, srcReg: RegX0, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0xf, 0x2c, 0xc0}}, - {name: "CVTTSS2SL/src=X0/dst=R8/arg=0", n: &nodeImpl{instruction: CVTTSS2SL, srcReg: RegX0, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0x2c, 0xc0}}, - {name: "CVTTSS2SL/src=X8/dst=AX/arg=0", n: &nodeImpl{instruction: CVTTSS2SL, srcReg: RegX8, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0x2c, 0xc0}}, - {name: "CVTTSS2SL/src=X8/dst=R8/arg=0", n: &nodeImpl{instruction: CVTTSS2SL, srcReg: RegX8, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0x2c, 0xc0}}, - {name: "CVTTSS2SQ/src=X0/dst=AX/arg=0", n: &nodeImpl{instruction: CVTTSS2SQ, srcReg: RegX0, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0x48, 0xf, 0x2c, 0xc0}}, - {name: "CVTTSS2SQ/src=X0/dst=R8/arg=0", n: &nodeImpl{instruction: CVTTSS2SQ, srcReg: RegX0, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x4c, 0xf, 0x2c, 0xc0}}, - {name: "CVTTSS2SQ/src=X8/dst=AX/arg=0", n: &nodeImpl{instruction: CVTTSS2SQ, srcReg: RegX8, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0x49, 0xf, 0x2c, 0xc0}}, - {name: "CVTTSS2SQ/src=X8/dst=R8/arg=0", n: &nodeImpl{instruction: CVTTSS2SQ, srcReg: RegX8, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x4d, 0xf, 0x2c, 0xc0}}, - {name: "DIVSD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: DIVSD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0xf, 0x5e, 0xc0}}, - {name: "DIVSD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: DIVSD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x44, 0xf, 0x5e, 0xc0}}, - {name: "DIVSD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: DIVSD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0x41, 0xf, 0x5e, 0xc0}}, - {name: "DIVSD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: DIVSD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x45, 0xf, 0x5e, 0xc0}}, - {name: "DIVSS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: DIVSS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0xf, 0x5e, 0xc0}}, - {name: "DIVSS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: DIVSS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0x5e, 0xc0}}, - {name: "DIVSS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: DIVSS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0x5e, 0xc0}}, - {name: "DIVSS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: DIVSS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0x5e, 0xc0}}, - {name: "LZCNTL/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: LZCNTL, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0xf, 0xbd, 0xc0}}, - {name: "LZCNTL/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: LZCNTL, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0xbd, 0xc0}}, - {name: "LZCNTL/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: LZCNTL, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0xbd, 0xc0}}, - {name: "LZCNTL/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: LZCNTL, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0xbd, 0xc0}}, - {name: "LZCNTQ/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: LZCNTQ, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0x48, 0xf, 0xbd, 0xc0}}, - {name: "LZCNTQ/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: LZCNTQ, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x4c, 0xf, 0xbd, 0xc0}}, - {name: "LZCNTQ/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: LZCNTQ, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0x49, 0xf, 0xbd, 0xc0}}, - {name: "LZCNTQ/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: LZCNTQ, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x4d, 0xf, 0xbd, 0xc0}}, - {name: "MAXSS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: MAXSS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0xf, 0x5f, 0xc0}}, - {name: "MAXSS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: MAXSS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0x5f, 0xc0}}, - {name: "MAXSS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: MAXSS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0x5f, 0xc0}}, - {name: "MAXSS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: MAXSS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0x5f, 0xc0}}, - {name: "MINSD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: MINSD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0xf, 0x5d, 0xc0}}, - {name: "MINSD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: MINSD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x44, 0xf, 0x5d, 0xc0}}, - {name: "MINSD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: MINSD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0x41, 0xf, 0x5d, 0xc0}}, - {name: "MINSD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: MINSD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x45, 0xf, 0x5d, 0xc0}}, - {name: "MAXSS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: MAXSS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0xf, 0x5f, 0xc0}}, - {name: "MAXSS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: MAXSS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0x5f, 0xc0}}, - {name: "MAXSS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: MAXSS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0x5f, 0xc0}}, - {name: "MAXSS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: MAXSS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0x5f, 0xc0}}, - {name: "MINSS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: MINSS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0xf, 0x5d, 0xc0}}, - {name: "MINSS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: MINSS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0x5d, 0xc0}}, - {name: "MINSS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: MINSS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0x5d, 0xc0}}, - {name: "MINSS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: MINSS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0x5d, 0xc0}}, - {name: "MOVBLSX/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: MOVBLSX, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf, 0xbe, 0xc0}}, - {name: "MOVBLSX/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: MOVBLSX, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x44, 0xf, 0xbe, 0xc0}}, - {name: "MOVBLSX/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: MOVBLSX, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x41, 0xf, 0xbe, 0xc0}}, - {name: "MOVBLSX/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: MOVBLSX, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x45, 0xf, 0xbe, 0xc0}}, - {name: "MOVWLZX/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: MOVWLZX, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf, 0xb7, 0xc0}}, - {name: "MOVWLZX/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: MOVWLZX, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x44, 0xf, 0xb7, 0xc0}}, - {name: "MOVWLZX/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: MOVWLZX, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x41, 0xf, 0xb7, 0xc0}}, - {name: "MOVWLZX/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: MOVWLZX, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x45, 0xf, 0xb7, 0xc0}}, - {name: "MOVBLZX/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: MOVBLZX, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf, 0xb6, 0xc0}}, - {name: "MOVBLZX/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: MOVBLZX, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x44, 0xf, 0xb6, 0xc0}}, - {name: "MOVBLZX/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: MOVBLZX, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x41, 0xf, 0xb6, 0xc0}}, - {name: "MOVBLZX/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: MOVBLZX, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x45, 0xf, 0xb6, 0xc0}}, - {name: "MOVBQSX/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: MOVBQSX, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0xf, 0xbe, 0xc0}}, - {name: "MOVBQSX/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: MOVBQSX, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4c, 0xf, 0xbe, 0xc0}}, - {name: "MOVBQSX/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: MOVBQSX, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x49, 0xf, 0xbe, 0xc0}}, - {name: "MOVBQSX/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: MOVBQSX, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0xf, 0xbe, 0xc0}}, - {name: "MOVLQSX/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: MOVLQSX, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0x63, 0xc0}}, - {name: "MOVLQSX/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: MOVLQSX, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4c, 0x63, 0xc0}}, - {name: "MOVLQSX/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: MOVLQSX, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x49, 0x63, 0xc0}}, - {name: "MOVLQSX/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: MOVLQSX, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0x63, 0xc0}}, - {name: "MOVL/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: MOVL, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x89, 0xc0}}, - {name: "MOVL/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: MOVL, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x41, 0x89, 0xc0}}, - {name: "MOVL/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: MOVL, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x44, 0x89, 0xc0}}, - {name: "MOVL/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: MOVL, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x45, 0x89, 0xc0}}, - {name: "MOVL/src=AX/dst=X0/arg=0", n: &nodeImpl{instruction: MOVL, srcReg: RegAX, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x6e, 0xc0}}, - {name: "MOVL/src=AX/dst=X8/arg=0", n: &nodeImpl{instruction: MOVL, srcReg: RegAX, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x6e, 0xc0}}, - {name: "MOVL/src=R8/dst=X0/arg=0", n: &nodeImpl{instruction: MOVL, srcReg: RegR8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x6e, 0xc0}}, - {name: "MOVL/src=R8/dst=X8/arg=0", n: &nodeImpl{instruction: MOVL, srcReg: RegR8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x6e, 0xc0}}, - {name: "MOVL/src=X0/dst=AX/arg=0", n: &nodeImpl{instruction: MOVL, srcReg: RegX0, dstReg: RegAX, arg: 0x0}, exp: []byte{0x66, 0xf, 0x7e, 0xc0}}, - {name: "MOVL/src=X0/dst=R8/arg=0", n: &nodeImpl{instruction: MOVL, srcReg: RegX0, dstReg: RegR8, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x7e, 0xc0}}, - {name: "MOVL/src=X8/dst=AX/arg=0", n: &nodeImpl{instruction: MOVL, srcReg: RegX8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x7e, 0xc0}}, - {name: "MOVL/src=X8/dst=R8/arg=0", n: &nodeImpl{instruction: MOVL, srcReg: RegX8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x7e, 0xc0}}, - {name: "MOVQ/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0x89, 0xc0}}, - {name: "MOVQ/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x49, 0x89, 0xc0}}, - {name: "MOVQ/src=AX/dst=X0/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegAX, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x48, 0xf, 0x6e, 0xc0}}, - {name: "MOVQ/src=AX/dst=X8/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegAX, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x4c, 0xf, 0x6e, 0xc0}}, - {name: "MOVQ/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x4c, 0x89, 0xc0}}, - {name: "MOVQ/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0x89, 0xc0}}, - {name: "MOVQ/src=R8/dst=X0/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegR8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x49, 0xf, 0x6e, 0xc0}}, - {name: "MOVQ/src=R8/dst=X8/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegR8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x4d, 0xf, 0x6e, 0xc0}}, - {name: "MOVQ/src=X0/dst=AX/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegX0, dstReg: RegAX, arg: 0x0}, exp: []byte{0x66, 0x48, 0xf, 0x7e, 0xc0}}, - {name: "MOVQ/src=X0/dst=R8/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegX0, dstReg: RegR8, arg: 0x0}, exp: []byte{0x66, 0x49, 0xf, 0x7e, 0xc0}}, - {name: "MOVQ/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0xf, 0x7e, 0xc0}}, - {name: "MOVQ/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0x7e, 0xc0}}, - {name: "MOVQ/src=X8/dst=AX/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegX8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x66, 0x4c, 0xf, 0x7e, 0xc0}}, - {name: "MOVQ/src=X8/dst=R8/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegX8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x66, 0x4d, 0xf, 0x7e, 0xc0}}, - {name: "MOVQ/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0x7e, 0xc0}}, - {name: "MOVQ/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0x7e, 0xc0}}, - {name: "MOVWLSX/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: MOVWLSX, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf, 0xbf, 0xc0}}, - {name: "MOVWLSX/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: MOVWLSX, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x44, 0xf, 0xbf, 0xc0}}, - {name: "MOVWLSX/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: MOVWLSX, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x41, 0xf, 0xbf, 0xc0}}, - {name: "MOVWLSX/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: MOVWLSX, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x45, 0xf, 0xbf, 0xc0}}, - {name: "MOVWQSX/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: MOVWQSX, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0xf, 0xbf, 0xc0}}, - {name: "MOVWQSX/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: MOVWQSX, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4c, 0xf, 0xbf, 0xc0}}, - {name: "MOVWQSX/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: MOVWQSX, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x49, 0xf, 0xbf, 0xc0}}, - {name: "MOVWQSX/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: MOVWQSX, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0xf, 0xbf, 0xc0}}, - {name: "MULSD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: MULSD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0xf, 0x59, 0xc0}}, - {name: "MULSD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: MULSD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x44, 0xf, 0x59, 0xc0}}, - {name: "MULSD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: MULSD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0x41, 0xf, 0x59, 0xc0}}, - {name: "MULSD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: MULSD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x45, 0xf, 0x59, 0xc0}}, - {name: "MULSS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: MULSS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0xf, 0x59, 0xc0}}, - {name: "MULSS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: MULSS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0x59, 0xc0}}, - {name: "MULSS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: MULSS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0x59, 0xc0}}, - {name: "MULSS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: MULSS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0x59, 0xc0}}, - {name: "IMULQ/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: IMULQ, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0xf, 0xaf, 0xc0}}, - {name: "IMULQ/src=DX/dst=AX/arg=0", n: &nodeImpl{instruction: IMULQ, srcReg: RegDX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0xf, 0xaf, 0xc2}}, - {name: "IMULQ/src=R10/dst=CX/arg=0", n: &nodeImpl{instruction: IMULQ, srcReg: RegR10, dstReg: RegCX, arg: 0x0}, exp: []byte{0x49, 0xf, 0xaf, 0xca}}, - {name: "IMULQ/src=CX/dst=DI/arg=0", n: &nodeImpl{instruction: IMULQ, srcReg: RegCX, dstReg: RegDI, arg: 0x0}, exp: []byte{0x48, 0xf, 0xaf, 0xf9}}, - {name: "ORL/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: ORL, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x9, 0xc0}}, - {name: "ORL/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: ORL, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x41, 0x9, 0xc0}}, - {name: "ORL/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: ORL, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x44, 0x9, 0xc0}}, - {name: "ORL/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: ORL, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x45, 0x9, 0xc0}}, - {name: "ORPD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: ORPD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x56, 0xc0}}, - {name: "ORPD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: ORPD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x56, 0xc0}}, - {name: "ORPD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: ORPD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x56, 0xc0}}, - {name: "ORPD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: ORPD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x56, 0xc0}}, - {name: "ORPS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: ORPS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf, 0x56, 0xc0}}, - {name: "ORPS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: ORPS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x44, 0xf, 0x56, 0xc0}}, - {name: "ORPS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: ORPS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x41, 0xf, 0x56, 0xc0}}, - {name: "ORPS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: ORPS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x45, 0xf, 0x56, 0xc0}}, - {name: "ORQ/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: ORQ, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0x9, 0xc0}}, - {name: "ORQ/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: ORQ, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x49, 0x9, 0xc0}}, - {name: "ORQ/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: ORQ, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x4c, 0x9, 0xc0}}, - {name: "ORQ/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: ORQ, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0x9, 0xc0}}, - {name: "POPCNTL/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: POPCNTL, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0xf, 0xb8, 0xc0}}, - {name: "POPCNTL/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: POPCNTL, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0xb8, 0xc0}}, - {name: "POPCNTL/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: POPCNTL, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0xb8, 0xc0}}, - {name: "POPCNTL/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: POPCNTL, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0xb8, 0xc0}}, - {name: "POPCNTQ/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: POPCNTQ, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0x48, 0xf, 0xb8, 0xc0}}, - {name: "POPCNTQ/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: POPCNTQ, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x4c, 0xf, 0xb8, 0xc0}}, - {name: "POPCNTQ/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: POPCNTQ, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0x49, 0xf, 0xb8, 0xc0}}, - {name: "POPCNTQ/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: POPCNTQ, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x4d, 0xf, 0xb8, 0xc0}}, - {name: "ROLL/src=CX/dst=AX/arg=0", n: &nodeImpl{instruction: ROLL, srcReg: RegCX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xd3, 0xc0}}, - {name: "ROLL/src=CX/dst=R8/arg=0", n: &nodeImpl{instruction: ROLL, srcReg: RegCX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x41, 0xd3, 0xc0}}, - {name: "ROLQ/src=CX/dst=AX/arg=0", n: &nodeImpl{instruction: ROLQ, srcReg: RegCX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0xd3, 0xc0}}, - {name: "ROLQ/src=CX/dst=R8/arg=0", n: &nodeImpl{instruction: ROLQ, srcReg: RegCX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x49, 0xd3, 0xc0}}, - {name: "RORL/src=CX/dst=AX/arg=0", n: &nodeImpl{instruction: RORL, srcReg: RegCX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xd3, 0xc8}}, - {name: "RORL/src=CX/dst=R8/arg=0", n: &nodeImpl{instruction: RORL, srcReg: RegCX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x41, 0xd3, 0xc8}}, - {name: "RORQ/src=CX/dst=AX/arg=0", n: &nodeImpl{instruction: RORQ, srcReg: RegCX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0xd3, 0xc8}}, - {name: "RORQ/src=CX/dst=R8/arg=0", n: &nodeImpl{instruction: RORQ, srcReg: RegCX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x49, 0xd3, 0xc8}}, - {name: "ROUNDSD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x3a, 0xb, 0xc0, 0x0}}, - {name: "ROUNDSD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0xb, 0xc0, 0x0}}, - {name: "ROUNDSD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0xb, 0xc0, 0x0}}, - {name: "ROUNDSD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0xb, 0xc0, 0x0}}, - {name: "ROUNDSS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x3a, 0xa, 0xc0, 0x0}}, - {name: "ROUNDSS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0xa, 0xc0, 0x0}}, - {name: "ROUNDSS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0xa, 0xc0, 0x0}}, - {name: "ROUNDSS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0xa, 0xc0, 0x0}}, - {name: "ROUNDSD/src=X0/dst=X0/arg=1", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX0, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0xf, 0x3a, 0xb, 0xc0, 0x1}}, - {name: "ROUNDSD/src=X0/dst=X8/arg=1", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX0, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0xb, 0xc0, 0x1}}, - {name: "ROUNDSD/src=X8/dst=X0/arg=1", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX8, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0xb, 0xc0, 0x1}}, - {name: "ROUNDSD/src=X8/dst=X8/arg=1", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX8, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0xb, 0xc0, 0x1}}, - {name: "ROUNDSS/src=X0/dst=X0/arg=1", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX0, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0xf, 0x3a, 0xa, 0xc0, 0x1}}, - {name: "ROUNDSS/src=X0/dst=X8/arg=1", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX0, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0xa, 0xc0, 0x1}}, - {name: "ROUNDSS/src=X8/dst=X0/arg=1", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX8, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0xa, 0xc0, 0x1}}, - {name: "ROUNDSS/src=X8/dst=X8/arg=1", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX8, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0xa, 0xc0, 0x1}}, - {name: "ROUNDSD/src=X0/dst=X0/arg=2", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX0, dstReg: RegX0, arg: 0x2}, exp: []byte{0x66, 0xf, 0x3a, 0xb, 0xc0, 0x2}}, - {name: "ROUNDSD/src=X0/dst=X8/arg=2", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX0, dstReg: RegX8, arg: 0x2}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0xb, 0xc0, 0x2}}, - {name: "ROUNDSD/src=X8/dst=X0/arg=2", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX8, dstReg: RegX0, arg: 0x2}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0xb, 0xc0, 0x2}}, - {name: "ROUNDSD/src=X8/dst=X8/arg=2", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX8, dstReg: RegX8, arg: 0x2}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0xb, 0xc0, 0x2}}, - {name: "ROUNDSS/src=X0/dst=X0/arg=2", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX0, dstReg: RegX0, arg: 0x2}, exp: []byte{0x66, 0xf, 0x3a, 0xa, 0xc0, 0x2}}, - {name: "ROUNDSS/src=X0/dst=X8/arg=2", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX0, dstReg: RegX8, arg: 0x2}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0xa, 0xc0, 0x2}}, - {name: "ROUNDSS/src=X8/dst=X0/arg=2", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX8, dstReg: RegX0, arg: 0x2}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0xa, 0xc0, 0x2}}, - {name: "ROUNDSS/src=X8/dst=X8/arg=2", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX8, dstReg: RegX8, arg: 0x2}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0xa, 0xc0, 0x2}}, - {name: "ROUNDSD/src=X0/dst=X0/arg=3", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX0, dstReg: RegX0, arg: 0x3}, exp: []byte{0x66, 0xf, 0x3a, 0xb, 0xc0, 0x3}}, - {name: "ROUNDSD/src=X0/dst=X8/arg=3", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX0, dstReg: RegX8, arg: 0x3}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0xb, 0xc0, 0x3}}, - {name: "ROUNDSD/src=X8/dst=X0/arg=3", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX8, dstReg: RegX0, arg: 0x3}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0xb, 0xc0, 0x3}}, - {name: "ROUNDSD/src=X8/dst=X8/arg=3", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX8, dstReg: RegX8, arg: 0x3}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0xb, 0xc0, 0x3}}, - {name: "ROUNDSS/src=X0/dst=X0/arg=3", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX0, dstReg: RegX0, arg: 0x3}, exp: []byte{0x66, 0xf, 0x3a, 0xa, 0xc0, 0x3}}, - {name: "ROUNDSS/src=X0/dst=X8/arg=3", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX0, dstReg: RegX8, arg: 0x3}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0xa, 0xc0, 0x3}}, - {name: "ROUNDSS/src=X8/dst=X0/arg=3", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX8, dstReg: RegX0, arg: 0x3}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0xa, 0xc0, 0x3}}, - {name: "ROUNDSS/src=X8/dst=X8/arg=3", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX8, dstReg: RegX8, arg: 0x3}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0xa, 0xc0, 0x3}}, - {name: "ROUNDSD/src=X0/dst=X0/arg=4", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX0, dstReg: RegX0, arg: 0x4}, exp: []byte{0x66, 0xf, 0x3a, 0xb, 0xc0, 0x4}}, - {name: "ROUNDSD/src=X0/dst=X8/arg=4", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX0, dstReg: RegX8, arg: 0x4}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0xb, 0xc0, 0x4}}, - {name: "ROUNDSD/src=X8/dst=X0/arg=4", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX8, dstReg: RegX0, arg: 0x4}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0xb, 0xc0, 0x4}}, - {name: "ROUNDSD/src=X8/dst=X8/arg=4", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX8, dstReg: RegX8, arg: 0x4}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0xb, 0xc0, 0x4}}, - {name: "ROUNDSS/src=X0/dst=X0/arg=4", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX0, dstReg: RegX0, arg: 0x4}, exp: []byte{0x66, 0xf, 0x3a, 0xa, 0xc0, 0x4}}, - {name: "ROUNDSS/src=X0/dst=X8/arg=4", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX0, dstReg: RegX8, arg: 0x4}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0xa, 0xc0, 0x4}}, - {name: "ROUNDSS/src=X8/dst=X0/arg=4", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX8, dstReg: RegX0, arg: 0x4}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0xa, 0xc0, 0x4}}, - {name: "ROUNDSS/src=X8/dst=X8/arg=4", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX8, dstReg: RegX8, arg: 0x4}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0xa, 0xc0, 0x4}}, - {name: "SARL/src=CX/dst=AX/arg=0", n: &nodeImpl{instruction: SARL, srcReg: RegCX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xd3, 0xf8}}, - {name: "SARL/src=CX/dst=R8/arg=0", n: &nodeImpl{instruction: SARL, srcReg: RegCX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x41, 0xd3, 0xf8}}, - {name: "SARQ/src=CX/dst=AX/arg=0", n: &nodeImpl{instruction: SARQ, srcReg: RegCX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0xd3, 0xf8}}, - {name: "SARQ/src=CX/dst=R8/arg=0", n: &nodeImpl{instruction: SARQ, srcReg: RegCX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x49, 0xd3, 0xf8}}, - {name: "SHLL/src=CX/dst=AX/arg=0", n: &nodeImpl{instruction: SHLL, srcReg: RegCX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xd3, 0xe0}}, - {name: "SHLL/src=CX/dst=R8/arg=0", n: &nodeImpl{instruction: SHLL, srcReg: RegCX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x41, 0xd3, 0xe0}}, - {name: "SHLQ/src=CX/dst=AX/arg=0", n: &nodeImpl{instruction: SHLQ, srcReg: RegCX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0xd3, 0xe0}}, - {name: "SHLQ/src=CX/dst=R8/arg=0", n: &nodeImpl{instruction: SHLQ, srcReg: RegCX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x49, 0xd3, 0xe0}}, - {name: "SHRL/src=CX/dst=AX/arg=0", n: &nodeImpl{instruction: SHRL, srcReg: RegCX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xd3, 0xe8}}, - {name: "SHRL/src=CX/dst=R8/arg=0", n: &nodeImpl{instruction: SHRL, srcReg: RegCX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x41, 0xd3, 0xe8}}, - {name: "SHRQ/src=CX/dst=AX/arg=0", n: &nodeImpl{instruction: SHRQ, srcReg: RegCX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0xd3, 0xe8}}, - {name: "SHRQ/src=CX/dst=R8/arg=0", n: &nodeImpl{instruction: SHRQ, srcReg: RegCX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x49, 0xd3, 0xe8}}, - {name: "SQRTSD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: SQRTSD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0xf, 0x51, 0xc0}}, - {name: "SQRTSD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: SQRTSD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x44, 0xf, 0x51, 0xc0}}, - {name: "SQRTSD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: SQRTSD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0x41, 0xf, 0x51, 0xc0}}, - {name: "SQRTSD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: SQRTSD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x45, 0xf, 0x51, 0xc0}}, - {name: "SQRTSS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: SQRTSS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0xf, 0x51, 0xc0}}, - {name: "SQRTSS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: SQRTSS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0x51, 0xc0}}, - {name: "SQRTSS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: SQRTSS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0x51, 0xc0}}, - {name: "SQRTSS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: SQRTSS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0x51, 0xc0}}, - {name: "SUBL/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: SUBL, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x29, 0xc0}}, - {name: "SUBL/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: SUBL, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x41, 0x29, 0xc0}}, - {name: "SUBL/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: SUBL, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x44, 0x29, 0xc0}}, - {name: "SUBL/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: SUBL, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x45, 0x29, 0xc0}}, - {name: "SUBQ/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: SUBQ, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0x29, 0xc0}}, - {name: "SUBQ/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: SUBQ, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x49, 0x29, 0xc0}}, - {name: "SUBQ/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: SUBQ, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x4c, 0x29, 0xc0}}, - {name: "SUBQ/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: SUBQ, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0x29, 0xc0}}, - {name: "SUBSD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: SUBSD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0xf, 0x5c, 0xc0}}, - {name: "SUBSD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: SUBSD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x44, 0xf, 0x5c, 0xc0}}, - {name: "SUBSD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: SUBSD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0x41, 0xf, 0x5c, 0xc0}}, - {name: "SUBSD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: SUBSD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x45, 0xf, 0x5c, 0xc0}}, - {name: "SUBSS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: SUBSS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0xf, 0x5c, 0xc0}}, - {name: "SUBSS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: SUBSS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0x5c, 0xc0}}, - {name: "SUBSS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: SUBSS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0x5c, 0xc0}}, - {name: "SUBSS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: SUBSS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0x5c, 0xc0}}, - {name: "TESTL/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: TESTL, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x85, 0xc0}}, - {name: "TESTL/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: TESTL, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x41, 0x85, 0xc0}}, - {name: "TESTL/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: TESTL, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x44, 0x85, 0xc0}}, - {name: "TESTL/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: TESTL, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x45, 0x85, 0xc0}}, - {name: "TESTQ/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: TESTQ, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0x85, 0xc0}}, - {name: "TESTQ/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: TESTQ, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x49, 0x85, 0xc0}}, - {name: "TESTQ/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: TESTQ, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x4c, 0x85, 0xc0}}, - {name: "TESTQ/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: TESTQ, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0x85, 0xc0}}, - {name: "TZCNTL/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: TZCNTL, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0xf, 0xbc, 0xc0}}, - {name: "TZCNTL/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: TZCNTL, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0xbc, 0xc0}}, - {name: "TZCNTL/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: TZCNTL, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0xbc, 0xc0}}, - {name: "TZCNTL/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: TZCNTL, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0xbc, 0xc0}}, - {name: "TZCNTQ/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: TZCNTQ, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0x48, 0xf, 0xbc, 0xc0}}, - {name: "TZCNTQ/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: TZCNTQ, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x4c, 0xf, 0xbc, 0xc0}}, - {name: "TZCNTQ/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: TZCNTQ, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0x49, 0xf, 0xbc, 0xc0}}, - {name: "TZCNTQ/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: TZCNTQ, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x4d, 0xf, 0xbc, 0xc0}}, - {name: "UCOMISD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: UCOMISD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x2e, 0xc0}}, - {name: "UCOMISD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: UCOMISD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x2e, 0xc0}}, - {name: "UCOMISD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: UCOMISD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x2e, 0xc0}}, - {name: "UCOMISD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: UCOMISD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x2e, 0xc0}}, - {name: "UCOMISS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: UCOMISS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf, 0x2e, 0xc0}}, - {name: "UCOMISS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: UCOMISS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x44, 0xf, 0x2e, 0xc0}}, - {name: "UCOMISS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: UCOMISS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x41, 0xf, 0x2e, 0xc0}}, - {name: "UCOMISS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: UCOMISS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x45, 0xf, 0x2e, 0xc0}}, - {name: "XORL/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: XORL, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x31, 0xc0}}, - {name: "XORL/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: XORL, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x41, 0x31, 0xc0}}, - {name: "XORL/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: XORL, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x44, 0x31, 0xc0}}, - {name: "XORL/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: XORL, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x45, 0x31, 0xc0}}, - {name: "XORPD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: XORPD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x57, 0xc0}}, - {name: "XORPD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: XORPD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x57, 0xc0}}, - {name: "XORPD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: XORPD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x57, 0xc0}}, - {name: "XORPD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: XORPD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x57, 0xc0}}, - {name: "XORPS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: XORPS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf, 0x57, 0xc0}}, - {name: "XORPS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: XORPS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x44, 0xf, 0x57, 0xc0}}, - {name: "XORPS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: XORPS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x41, 0xf, 0x57, 0xc0}}, - {name: "XORPS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: XORPS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x45, 0xf, 0x57, 0xc0}}, - {name: "XORQ/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: XORQ, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0x31, 0xc0}}, - {name: "XORQ/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: XORQ, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x49, 0x31, 0xc0}}, - {name: "XORQ/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: XORQ, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x4c, 0x31, 0xc0}}, - {name: "XORQ/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: XORQ, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0x31, 0xc0}}, - {name: "XCHGQ/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: XCHGQ, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x4c, 0x87, 0xc0}}, - {name: "XCHGQ/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: XCHGQ, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x49, 0x87, 0xc0}}, - {name: "XCHGQ/src=R8/dst=R9/arg=0", n: &nodeImpl{instruction: XCHGQ, srcReg: RegR9, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0x87, 0xc8}}, - {name: "PXOR/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PXOR, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0xef, 0xc0}}, - {name: "PXOR/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PXOR, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0xef, 0xc0}}, - {name: "PXOR/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PXOR, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0xef, 0xc0}}, - {name: "PSHUFB/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PSHUFB, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x38, 0x0, 0xc0}}, - {name: "PSHUFB/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PSHUFB, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x38, 0x0, 0xc0}}, - {name: "PSHUFB/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PSHUFB, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x0, 0xc0}}, - {name: "PSHUFB/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PSHUFB, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x38, 0x0, 0xc0}}, - {name: "PSHUFD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PSHUFD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x70, 0xc0, 0x0}}, - {name: "PSHUFD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PSHUFD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x70, 0xc0, 0x0}}, - {name: "PSHUFD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PSHUFD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x70, 0xc0, 0x0}}, - {name: "PSHUFD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PSHUFD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x70, 0xc0, 0x0}}, - {name: "PSHUFD/src=X0/dst=X0/arg=1", n: &nodeImpl{instruction: PSHUFD, srcReg: RegX0, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0xf, 0x70, 0xc0, 0x1}}, - {name: "PSHUFD/src=X0/dst=X8/arg=1", n: &nodeImpl{instruction: PSHUFD, srcReg: RegX0, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x44, 0xf, 0x70, 0xc0, 0x1}}, - {name: "PSHUFD/src=X8/dst=X0/arg=1", n: &nodeImpl{instruction: PSHUFD, srcReg: RegX8, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0x41, 0xf, 0x70, 0xc0, 0x1}}, - {name: "PSHUFD/src=X8/dst=X8/arg=1", n: &nodeImpl{instruction: PSHUFD, srcReg: RegX8, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x45, 0xf, 0x70, 0xc0, 0x1}}, - {name: "PEXTRB/src=X0/dst=AX/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegAX, arg: 0x0}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0xc0, 0x0}}, - {name: "PEXTRB/src=X0/dst=R8/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegR8, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0x14, 0xc0, 0x0}}, - {name: "PEXTRB/src=X8/dst=AX/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0xc0, 0x0}}, - {name: "PEXTRB/src=X8/dst=R8/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0x14, 0xc0, 0x0}}, - {name: "PEXTRW/src=X0/dst=AX/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegAX, arg: 0x1}, exp: []byte{0x66, 0xf, 0xc5, 0xc0, 0x1}}, - {name: "PEXTRW/src=X0/dst=R8/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegR8, arg: 0x1}, exp: []byte{0x66, 0x44, 0xf, 0xc5, 0xc0, 0x1}}, - {name: "PEXTRW/src=X8/dst=AX/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX8, dstReg: RegAX, arg: 0x1}, exp: []byte{0x66, 0x41, 0xf, 0xc5, 0xc0, 0x1}}, - {name: "PEXTRW/src=X8/dst=R8/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX8, dstReg: RegR8, arg: 0x1}, exp: []byte{0x66, 0x45, 0xf, 0xc5, 0xc0, 0x1}}, - {name: "PEXTRD/src=X0/dst=AX/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegAX, arg: 0x1}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0xc0, 0x1}}, - {name: "PEXTRD/src=X0/dst=R8/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegR8, arg: 0x1}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0x16, 0xc0, 0x1}}, - {name: "PEXTRD/src=X8/dst=AX/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX8, dstReg: RegAX, arg: 0x1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0xc0, 0x1}}, - {name: "PEXTRD/src=X8/dst=R8/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX8, dstReg: RegR8, arg: 0x1}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0x16, 0xc0, 0x1}}, - {name: "PEXTRQ/src=X0/dst=AX/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegAX, arg: 0x1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0xc0, 0x1}}, - {name: "PEXTRQ/src=X0/dst=R8/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegR8, arg: 0x1}, exp: []byte{0x66, 0x49, 0xf, 0x3a, 0x16, 0xc0, 0x1}}, - {name: "PEXTRQ/src=X8/dst=AX/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX8, dstReg: RegAX, arg: 0x1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0xc0, 0x1}}, - {name: "PEXTRQ/src=X8/dst=R8/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX8, dstReg: RegR8, arg: 0x1}, exp: []byte{0x66, 0x4d, 0xf, 0x3a, 0x16, 0xc0, 0x1}}, - {name: "MOVLHPS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: MOVLHPS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf, 0x16, 0xc0}}, - {name: "MOVLHPS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: MOVLHPS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x44, 0xf, 0x16, 0xc0}}, - {name: "MOVLHPS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: MOVLHPS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x41, 0xf, 0x16, 0xc0}}, - {name: "MOVLHPS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: MOVLHPS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x45, 0xf, 0x16, 0xc0}}, - {name: "INSERTPS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: INSERTPS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x3a, 0x21, 0xc0, 0x0}}, - {name: "INSERTPS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: INSERTPS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x21, 0xc0, 0x0}}, - {name: "INSERTPS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: INSERTPS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0x21, 0xc0, 0x0}}, - {name: "INSERTPS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: INSERTPS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0x21, 0xc0, 0x0}}, - {name: "INSERTPS/src=X0/dst=X0/arg=1", n: &nodeImpl{instruction: INSERTPS, srcReg: RegX0, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0xf, 0x3a, 0x21, 0xc0, 0x1}}, - {name: "INSERTPS/src=X0/dst=X8/arg=1", n: &nodeImpl{instruction: INSERTPS, srcReg: RegX0, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x21, 0xc0, 0x1}}, - {name: "INSERTPS/src=X8/dst=X0/arg=1", n: &nodeImpl{instruction: INSERTPS, srcReg: RegX8, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0x21, 0xc0, 0x1}}, - {name: "INSERTPS/src=X8/dst=X8/arg=1", n: &nodeImpl{instruction: INSERTPS, srcReg: RegX8, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0x21, 0xc0, 0x1}}, - {name: "PTEST/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PTEST, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x38, 0x17, 0xc0}}, - {name: "PTEST/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PTEST, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x38, 0x17, 0xc0}}, - {name: "PTEST/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PTEST, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x17, 0xc0}}, - {name: "PTEST/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PTEST, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x38, 0x17, 0xc0}}, - {name: "PCMPEQB/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PCMPEQB, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x74, 0xc0}}, - {name: "PCMPEQB/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PCMPEQB, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x74, 0xc0}}, - {name: "PCMPEQB/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PCMPEQB, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x74, 0xc0}}, - {name: "PCMPEQB/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PCMPEQB, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x74, 0xc0}}, - {name: "PCMPEQW/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PCMPEQW, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x75, 0xc0}}, - {name: "PCMPEQW/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PCMPEQW, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x75, 0xc0}}, - {name: "PCMPEQW/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PCMPEQW, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x75, 0xc0}}, - {name: "PCMPEQW/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PCMPEQW, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x75, 0xc0}}, - {name: "PCMPEQD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PCMPEQD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x76, 0xc0}}, - {name: "PCMPEQD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PCMPEQD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x76, 0xc0}}, - {name: "PCMPEQD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PCMPEQD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x76, 0xc0}}, - {name: "PCMPEQD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PCMPEQD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x76, 0xc0}}, - {name: "PCMPEQQ/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PCMPEQQ, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x38, 0x29, 0xc0}}, - {name: "PCMPEQQ/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PCMPEQQ, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x38, 0x29, 0xc0}}, - {name: "PCMPEQQ/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PCMPEQQ, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x29, 0xc0}}, - {name: "PCMPEQQ/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PCMPEQQ, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x38, 0x29, 0xc0}}, - {name: "PADDUSB/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PADDUSB, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0xdc, 0xc0}}, - {name: "PADDUSB/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PADDUSB, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0xdc, 0xc0}}, - {name: "PADDUSB/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PADDUSB, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0xdc, 0xc0}}, - {name: "PADDUSB/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PADDUSB, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0xdc, 0xc0}}, - {name: "MOVSD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: MOVSD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0xf, 0x10, 0xc0}}, - {name: "MOVSD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: MOVSD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x44, 0xf, 0x10, 0xc0}}, - {name: "MOVSD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: MOVSD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0x41, 0xf, 0x10, 0xc0}}, - {name: "MOVSD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: MOVSD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x45, 0xf, 0x10, 0xc0}}, - } - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - for _, tt := range tests { - tc := tt - a := NewAssembler() - buf := code.NextCodeSection() - err := a.encodeRegisterToRegister(buf, tc.n) - require.NoError(t, err, tc.name) - - err = a.Assemble(buf) - require.NoError(t, err, tc.name) - - actual := buf.Bytes() - require.Equal(t, tc.exp, actual, tc.name) - } -} diff --git a/internal/asm/amd64/impl_3_test.go b/internal/asm/amd64/impl_3_test.go deleted file mode 100644 index 0a7b0ab9ff..0000000000 --- a/internal/asm/amd64/impl_3_test.go +++ /dev/null @@ -1,1115 +0,0 @@ -package amd64 - -import ( - "testing" - - "github.com/tetratelabs/wazero/internal/asm" - "github.com/tetratelabs/wazero/internal/testing/require" -) - -func TestAssemblerImpl_EncodeRegisterToMemory(t *testing.T) { - t.Run("error", func(t *testing.T) { - tests := []struct { - n *nodeImpl - expErr string - }{ - { - n: &nodeImpl{ - instruction: JMP, - types: operandTypesRegisterToMemory, - srcReg: RegAX, dstReg: RegAX, - }, - expErr: "JMP is unsupported for RegisterToMemory type", - }, - { - n: &nodeImpl{ - instruction: SHLQ, - types: operandTypesRegisterToMemory, - srcReg: RegAX, dstReg: RegAX, - }, - expErr: "shifting instruction SHLQ require CX register as src but got AX", - }, - } - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - for _, tc := range tests { - a := NewAssembler() - b := code.NextCodeSection() - require.EqualError(t, a.encodeRegisterToMemory(b, tc.n), tc.expErr) - } - }) - - tests := []struct { - name string - n *nodeImpl - exp []byte - }{ - {name: "CMPL/baseReg=R12/offset=0x0/dstReg=R8", n: &nodeImpl{instruction: CMPL, srcReg: RegR12, dstConst: 0x0, dstReg: RegR8}, exp: []byte{0x45, 0x3b, 0x20}}, - {name: "CMPL/srcReg=R12/baseReg=R8/offset=0x0/index=R11/scale=4", n: &nodeImpl{instruction: CMPL, srcReg: RegR12, dstConst: 0x0, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x47, 0x3b, 0x24, 0x98}}, - {name: "CMPL/baseReg=R12/offset=0x1/dstReg=R8", n: &nodeImpl{instruction: CMPL, srcReg: RegR12, dstConst: 0x1, dstReg: RegR8}, exp: []byte{0x45, 0x3b, 0x60, 0x1}}, - {name: "CMPL/srcReg=R12/baseReg=R8/offset=0x1/index=R11/scale=4", n: &nodeImpl{instruction: CMPL, srcReg: RegR12, dstConst: 0x1, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x47, 0x3b, 0x64, 0x98, 0x1}}, - {name: "CMPL/baseReg=R12/offset=0x7fffffff/dstReg=R8", n: &nodeImpl{instruction: CMPL, srcReg: RegR12, dstConst: 0x7fffffff, dstReg: RegR8}, exp: []byte{0x45, 0x3b, 0xa0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPL/srcReg=R12/baseReg=R8/offset=0x7fffffff/index=R11/scale=4", n: &nodeImpl{instruction: CMPL, srcReg: RegR12, dstConst: 0x7fffffff, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x47, 0x3b, 0xa4, 0x98, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPL/baseReg=SI/offset=0x0/dstReg=R8", n: &nodeImpl{instruction: CMPL, srcReg: RegSI, dstConst: 0x0, dstReg: RegR8}, exp: []byte{0x41, 0x3b, 0x30}}, - {name: "CMPL/srcReg=SI/baseReg=R8/offset=0x0/index=R11/scale=4", n: &nodeImpl{instruction: CMPL, srcReg: RegSI, dstConst: 0x0, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x43, 0x3b, 0x34, 0x98}}, - {name: "CMPL/baseReg=SI/offset=0x1/dstReg=R8", n: &nodeImpl{instruction: CMPL, srcReg: RegSI, dstConst: 0x1, dstReg: RegR8}, exp: []byte{0x41, 0x3b, 0x70, 0x1}}, - {name: "CMPL/srcReg=SI/baseReg=R8/offset=0x1/index=R11/scale=4", n: &nodeImpl{instruction: CMPL, srcReg: RegSI, dstConst: 0x1, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x43, 0x3b, 0x74, 0x98, 0x1}}, - {name: "CMPL/baseReg=SI/offset=0x7fffffff/dstReg=R8", n: &nodeImpl{instruction: CMPL, srcReg: RegSI, dstConst: 0x7fffffff, dstReg: RegR8}, exp: []byte{0x41, 0x3b, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPL/srcReg=SI/baseReg=R8/offset=0x7fffffff/index=R11/scale=4", n: &nodeImpl{instruction: CMPL, srcReg: RegSI, dstConst: 0x7fffffff, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x43, 0x3b, 0xb4, 0x98, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPQ/baseReg=R12/offset=0x0/dstReg=R8", n: &nodeImpl{instruction: CMPQ, srcReg: RegR12, dstConst: 0x0, dstReg: RegR8}, exp: []byte{0x4d, 0x3b, 0x20}}, - {name: "CMPQ/srcReg=R12/baseReg=R8/offset=0x0/index=R11/scale=4", n: &nodeImpl{instruction: CMPQ, srcReg: RegR12, dstConst: 0x0, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x4f, 0x3b, 0x24, 0x98}}, - {name: "CMPQ/baseReg=R12/offset=0x1/dstReg=R8", n: &nodeImpl{instruction: CMPQ, srcReg: RegR12, dstConst: 0x1, dstReg: RegR8}, exp: []byte{0x4d, 0x3b, 0x60, 0x1}}, - {name: "CMPQ/srcReg=R12/baseReg=R8/offset=0x1/index=R11/scale=4", n: &nodeImpl{instruction: CMPQ, srcReg: RegR12, dstConst: 0x1, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x4f, 0x3b, 0x64, 0x98, 0x1}}, - {name: "CMPQ/baseReg=R12/offset=0x7fffffff/dstReg=R8", n: &nodeImpl{instruction: CMPQ, srcReg: RegR12, dstConst: 0x7fffffff, dstReg: RegR8}, exp: []byte{0x4d, 0x3b, 0xa0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPQ/srcReg=R12/baseReg=R8/offset=0x7fffffff/index=R11/scale=4", n: &nodeImpl{instruction: CMPQ, srcReg: RegR12, dstConst: 0x7fffffff, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x4f, 0x3b, 0xa4, 0x98, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPQ/baseReg=SI/offset=0x0/dstReg=R8", n: &nodeImpl{instruction: CMPQ, srcReg: RegSI, dstConst: 0x0, dstReg: RegR8}, exp: []byte{0x49, 0x3b, 0x30}}, - {name: "CMPQ/srcReg=SI/baseReg=R8/offset=0x0/index=R11/scale=4", n: &nodeImpl{instruction: CMPQ, srcReg: RegSI, dstConst: 0x0, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x4b, 0x3b, 0x34, 0x98}}, - {name: "CMPQ/baseReg=SI/offset=0x1/dstReg=R8", n: &nodeImpl{instruction: CMPQ, srcReg: RegSI, dstConst: 0x1, dstReg: RegR8}, exp: []byte{0x49, 0x3b, 0x70, 0x1}}, - {name: "CMPQ/srcReg=SI/baseReg=R8/offset=0x1/index=R11/scale=4", n: &nodeImpl{instruction: CMPQ, srcReg: RegSI, dstConst: 0x1, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x4b, 0x3b, 0x74, 0x98, 0x1}}, - {name: "CMPQ/baseReg=SI/offset=0x7fffffff/dstReg=R8", n: &nodeImpl{instruction: CMPQ, srcReg: RegSI, dstConst: 0x7fffffff, dstReg: RegR8}, exp: []byte{0x49, 0x3b, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPQ/srcReg=SI/baseReg=R8/offset=0x7fffffff/index=R11/scale=4", n: &nodeImpl{instruction: CMPQ, srcReg: RegSI, dstConst: 0x7fffffff, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x4b, 0x3b, 0xb4, 0x98, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVB/baseReg=R12/offset=0x0/dstReg=R8", n: &nodeImpl{instruction: MOVB, srcReg: RegR12, dstConst: 0x0, dstReg: RegR8}, exp: []byte{0x45, 0x88, 0x20}}, - {name: "MOVB/srcReg=R12/baseReg=R8/offset=0x0/index=R11/scale=4", n: &nodeImpl{instruction: MOVB, srcReg: RegR12, dstConst: 0x0, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x47, 0x88, 0x24, 0x98}}, - {name: "MOVB/baseReg=R12/offset=0x1/dstReg=R8", n: &nodeImpl{instruction: MOVB, srcReg: RegR12, dstConst: 0x1, dstReg: RegR8}, exp: []byte{0x45, 0x88, 0x60, 0x1}}, - {name: "MOVB/srcReg=R12/baseReg=R8/offset=0x1/index=R11/scale=4", n: &nodeImpl{instruction: MOVB, srcReg: RegR12, dstConst: 0x1, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x47, 0x88, 0x64, 0x98, 0x1}}, - {name: "MOVB/baseReg=R12/offset=0x7fffffff/dstReg=R8", n: &nodeImpl{instruction: MOVB, srcReg: RegR12, dstConst: 0x7fffffff, dstReg: RegR8}, exp: []byte{0x45, 0x88, 0xa0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVB/srcReg=R12/baseReg=R8/offset=0x7fffffff/index=R11/scale=4", n: &nodeImpl{instruction: MOVB, srcReg: RegR12, dstConst: 0x7fffffff, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x47, 0x88, 0xa4, 0x98, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVB/baseReg=SI/offset=0x0/dstReg=R8", n: &nodeImpl{instruction: MOVB, srcReg: RegSI, dstConst: 0x0, dstReg: RegR8}, exp: []byte{0x41, 0x88, 0x30}}, - {name: "MOVB/srcReg=SI/baseReg=R8/offset=0x0/index=R11/scale=4", n: &nodeImpl{instruction: MOVB, srcReg: RegSI, dstConst: 0x0, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x43, 0x88, 0x34, 0x98}}, - {name: "MOVB/baseReg=SI/offset=0x1/dstReg=R8", n: &nodeImpl{instruction: MOVB, srcReg: RegSI, dstConst: 0x1, dstReg: RegR8}, exp: []byte{0x41, 0x88, 0x70, 0x1}}, - {name: "MOVB/srcReg=SI/baseReg=R8/offset=0x1/index=R11/scale=4", n: &nodeImpl{instruction: MOVB, srcReg: RegSI, dstConst: 0x1, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x43, 0x88, 0x74, 0x98, 0x1}}, - {name: "MOVB/baseReg=SI/offset=0x7fffffff/dstReg=R8", n: &nodeImpl{instruction: MOVB, srcReg: RegSI, dstConst: 0x7fffffff, dstReg: RegR8}, exp: []byte{0x41, 0x88, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVB/srcReg=SI/baseReg=R8/offset=0x7fffffff/index=R11/scale=4", n: &nodeImpl{instruction: MOVB, srcReg: RegSI, dstConst: 0x7fffffff, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x43, 0x88, 0xb4, 0x98, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVL/baseReg=R12/offset=0x0/dstReg=R8", n: &nodeImpl{instruction: MOVL, srcReg: RegR12, dstConst: 0x0, dstReg: RegR8}, exp: []byte{0x45, 0x89, 0x20}}, - {name: "MOVL/srcReg=R12/baseReg=R8/offset=0x0/index=R11/scale=4", n: &nodeImpl{instruction: MOVL, srcReg: RegR12, dstConst: 0x0, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x47, 0x89, 0x24, 0x98}}, - {name: "MOVL/baseReg=R12/offset=0x1/dstReg=R8", n: &nodeImpl{instruction: MOVL, srcReg: RegR12, dstConst: 0x1, dstReg: RegR8}, exp: []byte{0x45, 0x89, 0x60, 0x1}}, - {name: "MOVL/srcReg=R12/baseReg=R8/offset=0x1/index=R11/scale=4", n: &nodeImpl{instruction: MOVL, srcReg: RegR12, dstConst: 0x1, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x47, 0x89, 0x64, 0x98, 0x1}}, - {name: "MOVL/baseReg=R12/offset=0x7fffffff/dstReg=R8", n: &nodeImpl{instruction: MOVL, srcReg: RegR12, dstConst: 0x7fffffff, dstReg: RegR8}, exp: []byte{0x45, 0x89, 0xa0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVL/srcReg=R12/baseReg=R8/offset=0x7fffffff/index=R11/scale=4", n: &nodeImpl{instruction: MOVL, srcReg: RegR12, dstConst: 0x7fffffff, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x47, 0x89, 0xa4, 0x98, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVL/baseReg=X10/offset=0x0/dstReg=R8", n: &nodeImpl{instruction: MOVL, srcReg: RegX10, dstConst: 0x0, dstReg: RegR8}, exp: []byte{0x66, 0x45, 0xf, 0x7e, 0x10}}, - {name: "MOVL/srcReg=X10/baseReg=R8/offset=0x0/index=R11/scale=4", n: &nodeImpl{instruction: MOVL, srcReg: RegX10, dstConst: 0x0, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x66, 0x47, 0xf, 0x7e, 0x14, 0x98}}, - {name: "MOVL/baseReg=X10/offset=0x1/dstReg=R8", n: &nodeImpl{instruction: MOVL, srcReg: RegX10, dstConst: 0x1, dstReg: RegR8}, exp: []byte{0x66, 0x45, 0xf, 0x7e, 0x50, 0x1}}, - {name: "MOVL/srcReg=X10/baseReg=R8/offset=0x1/index=R11/scale=4", n: &nodeImpl{instruction: MOVL, srcReg: RegX10, dstConst: 0x1, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x66, 0x47, 0xf, 0x7e, 0x54, 0x98, 0x1}}, - {name: "MOVL/baseReg=X10/offset=0x7fffffff/dstReg=R8", n: &nodeImpl{instruction: MOVL, srcReg: RegX10, dstConst: 0x7fffffff, dstReg: RegR8}, exp: []byte{0x66, 0x45, 0xf, 0x7e, 0x90, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVL/srcReg=X10/baseReg=R8/offset=0x7fffffff/index=R11/scale=4", n: &nodeImpl{instruction: MOVL, srcReg: RegX10, dstConst: 0x7fffffff, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x66, 0x47, 0xf, 0x7e, 0x94, 0x98, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVQ/baseReg=R12/offset=0x0/dstReg=R8", n: &nodeImpl{instruction: MOVQ, srcReg: RegR12, dstConst: 0x0, dstReg: RegR8}, exp: []byte{0x4d, 0x89, 0x20}}, - {name: "MOVQ/srcReg=R12/baseReg=R8/offset=0x0/index=R11/scale=4", n: &nodeImpl{instruction: MOVQ, srcReg: RegR12, dstConst: 0x0, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x4f, 0x89, 0x24, 0x98}}, - {name: "MOVQ/baseReg=R12/offset=0x1/dstReg=R8", n: &nodeImpl{instruction: MOVQ, srcReg: RegR12, dstConst: 0x1, dstReg: RegR8}, exp: []byte{0x4d, 0x89, 0x60, 0x1}}, - {name: "MOVQ/srcReg=R12/baseReg=R8/offset=0x1/index=R11/scale=4", n: &nodeImpl{instruction: MOVQ, srcReg: RegR12, dstConst: 0x1, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x4f, 0x89, 0x64, 0x98, 0x1}}, - {name: "MOVQ/baseReg=R12/offset=0x7fffffff/dstReg=R8", n: &nodeImpl{instruction: MOVQ, srcReg: RegR12, dstConst: 0x7fffffff, dstReg: RegR8}, exp: []byte{0x4d, 0x89, 0xa0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVQ/srcReg=R12/baseReg=R8/offset=0x7fffffff/index=R11/scale=4", n: &nodeImpl{instruction: MOVQ, srcReg: RegR12, dstConst: 0x7fffffff, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x4f, 0x89, 0xa4, 0x98, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVQ/baseReg=X10/offset=0x0/dstReg=R8", n: &nodeImpl{instruction: MOVQ, srcReg: RegX10, dstConst: 0x0, dstReg: RegR8}, exp: []byte{0x66, 0x45, 0xf, 0xd6, 0x10}}, - {name: "MOVQ/srcReg=X10/baseReg=R8/offset=0x0/index=R11/scale=4", n: &nodeImpl{instruction: MOVQ, srcReg: RegX10, dstConst: 0x0, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x66, 0x47, 0xf, 0xd6, 0x14, 0x98}}, - {name: "MOVQ/baseReg=X10/offset=0x1/dstReg=R8", n: &nodeImpl{instruction: MOVQ, srcReg: RegX10, dstConst: 0x1, dstReg: RegR8}, exp: []byte{0x66, 0x45, 0xf, 0xd6, 0x50, 0x1}}, - {name: "MOVQ/srcReg=X10/baseReg=R8/offset=0x1/index=R11/scale=4", n: &nodeImpl{instruction: MOVQ, srcReg: RegX10, dstConst: 0x1, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x66, 0x47, 0xf, 0xd6, 0x54, 0x98, 0x1}}, - {name: "MOVQ/baseReg=X10/offset=0x7fffffff/dstReg=R8", n: &nodeImpl{instruction: MOVQ, srcReg: RegX10, dstConst: 0x7fffffff, dstReg: RegR8}, exp: []byte{0x66, 0x45, 0xf, 0xd6, 0x90, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVQ/srcReg=X10/baseReg=R8/offset=0x7fffffff/index=R11/scale=4", n: &nodeImpl{instruction: MOVQ, srcReg: RegX10, dstConst: 0x7fffffff, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x66, 0x47, 0xf, 0xd6, 0x94, 0x98, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVW/baseReg=R12/offset=0x0/dstReg=R8", n: &nodeImpl{instruction: MOVW, srcReg: RegR12, dstConst: 0x0, dstReg: RegR8}, exp: []byte{0x66, 0x45, 0x89, 0x20}}, - {name: "MOVW/srcReg=R12/baseReg=R8/offset=0x0/index=R11/scale=4", n: &nodeImpl{instruction: MOVW, srcReg: RegR12, dstConst: 0x0, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x66, 0x47, 0x89, 0x24, 0x98}}, - {name: "MOVW/baseReg=R12/offset=0x1/dstReg=R8", n: &nodeImpl{instruction: MOVW, srcReg: RegR12, dstConst: 0x1, dstReg: RegR8}, exp: []byte{0x66, 0x45, 0x89, 0x60, 0x1}}, - {name: "MOVW/srcReg=R12/baseReg=R8/offset=0x1/index=R11/scale=4", n: &nodeImpl{instruction: MOVW, srcReg: RegR12, dstConst: 0x1, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x66, 0x47, 0x89, 0x64, 0x98, 0x1}}, - {name: "MOVW/baseReg=R12/offset=0x7fffffff/dstReg=R8", n: &nodeImpl{instruction: MOVW, srcReg: RegR12, dstConst: 0x7fffffff, dstReg: RegR8}, exp: []byte{0x66, 0x45, 0x89, 0xa0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVW/srcReg=R12/baseReg=R8/offset=0x7fffffff/index=R11/scale=4", n: &nodeImpl{instruction: MOVW, srcReg: RegR12, dstConst: 0x7fffffff, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x66, 0x47, 0x89, 0xa4, 0x98, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVW/baseReg=SI/offset=0x0/dstReg=R8", n: &nodeImpl{instruction: MOVW, srcReg: RegSI, dstConst: 0x0, dstReg: RegR8}, exp: []byte{0x66, 0x41, 0x89, 0x30}}, - {name: "MOVW/srcReg=SI/baseReg=R8/offset=0x0/index=R11/scale=4", n: &nodeImpl{instruction: MOVW, srcReg: RegSI, dstConst: 0x0, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x66, 0x43, 0x89, 0x34, 0x98}}, - {name: "MOVW/baseReg=SI/offset=0x1/dstReg=R8", n: &nodeImpl{instruction: MOVW, srcReg: RegSI, dstConst: 0x1, dstReg: RegR8}, exp: []byte{0x66, 0x41, 0x89, 0x70, 0x1}}, - {name: "MOVW/srcReg=SI/baseReg=R8/offset=0x1/index=R11/scale=4", n: &nodeImpl{instruction: MOVW, srcReg: RegSI, dstConst: 0x1, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x66, 0x43, 0x89, 0x74, 0x98, 0x1}}, - {name: "MOVW/baseReg=SI/offset=0x7fffffff/dstReg=R8", n: &nodeImpl{instruction: MOVW, srcReg: RegSI, dstConst: 0x7fffffff, dstReg: RegR8}, exp: []byte{0x66, 0x41, 0x89, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVW/srcReg=SI/baseReg=R8/offset=0x7fffffff/index=R11/scale=4", n: &nodeImpl{instruction: MOVW, srcReg: RegSI, dstConst: 0x7fffffff, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x66, 0x43, 0x89, 0xb4, 0x98, 0xff, 0xff, 0xff, 0x7f}}, - {name: "SARL/baseReg=CX/offset=0x0/dstReg=R13", n: &nodeImpl{instruction: SARL, srcReg: RegCX, dstConst: 0x0, dstReg: RegR13}, exp: []byte{0x41, 0xd3, 0x7d, 0x0}}, - {name: "SARL/srcReg=CX/baseReg=R13/offset=0x0/index=R10/scale=4", n: &nodeImpl{instruction: SARL, srcReg: RegCX, dstConst: 0x0, dstMemIndex: RegR10, dstMemScale: 4, dstReg: RegR13}, exp: []byte{0x43, 0xd3, 0x7c, 0x95, 0x0}}, - {name: "SARL/baseReg=CX/offset=0x1/dstReg=R13", n: &nodeImpl{instruction: SARL, srcReg: RegCX, dstConst: 0x1, dstReg: RegR13}, exp: []byte{0x41, 0xd3, 0x7d, 0x1}}, - {name: "SARL/srcReg=CX/baseReg=R13/offset=0x1/index=R10/scale=4", n: &nodeImpl{instruction: SARL, srcReg: RegCX, dstConst: 0x1, dstMemIndex: RegR10, dstMemScale: 4, dstReg: RegR13}, exp: []byte{0x43, 0xd3, 0x7c, 0x95, 0x1}}, - {name: "SARL/baseReg=CX/offset=0x7fffffff/dstReg=R13", n: &nodeImpl{instruction: SARL, srcReg: RegCX, dstConst: 0x7fffffff, dstReg: RegR13}, exp: []byte{0x41, 0xd3, 0xbd, 0xff, 0xff, 0xff, 0x7f}}, - {name: "SARL/srcReg=CX/baseReg=R13/offset=0x7fffffff/index=R10/scale=4", n: &nodeImpl{instruction: SARL, srcReg: RegCX, dstConst: 0x7fffffff, dstMemIndex: RegR10, dstMemScale: 4, dstReg: RegR13}, exp: []byte{0x43, 0xd3, 0xbc, 0x95, 0xff, 0xff, 0xff, 0x7f}}, - {name: "SARQ/baseReg=CX/offset=0x0/dstReg=R13", n: &nodeImpl{instruction: SARQ, srcReg: RegCX, dstConst: 0x0, dstReg: RegR13}, exp: []byte{0x49, 0xd3, 0x7d, 0x0}}, - {name: "SARQ/srcReg=CX/baseReg=R13/offset=0x0/index=R10/scale=4", n: &nodeImpl{instruction: SARQ, srcReg: RegCX, dstConst: 0x0, dstMemIndex: RegR10, dstMemScale: 4, dstReg: RegR13}, exp: []byte{0x4b, 0xd3, 0x7c, 0x95, 0x0}}, - {name: "SARQ/baseReg=CX/offset=0x1/dstReg=R13", n: &nodeImpl{instruction: SARQ, srcReg: RegCX, dstConst: 0x1, dstReg: RegR13}, exp: []byte{0x49, 0xd3, 0x7d, 0x1}}, - {name: "SARQ/srcReg=CX/baseReg=R13/offset=0x1/index=R10/scale=4", n: &nodeImpl{instruction: SARQ, srcReg: RegCX, dstConst: 0x1, dstMemIndex: RegR10, dstMemScale: 4, dstReg: RegR13}, exp: []byte{0x4b, 0xd3, 0x7c, 0x95, 0x1}}, - {name: "SARQ/baseReg=CX/offset=0x7fffffff/dstReg=R13", n: &nodeImpl{instruction: SARQ, srcReg: RegCX, dstConst: 0x7fffffff, dstReg: RegR13}, exp: []byte{0x49, 0xd3, 0xbd, 0xff, 0xff, 0xff, 0x7f}}, - {name: "SARQ/srcReg=CX/baseReg=R13/offset=0x7fffffff/index=R10/scale=4", n: &nodeImpl{instruction: SARQ, srcReg: RegCX, dstConst: 0x7fffffff, dstMemIndex: RegR10, dstMemScale: 4, dstReg: RegR13}, exp: []byte{0x4b, 0xd3, 0xbc, 0x95, 0xff, 0xff, 0xff, 0x7f}}, - {name: "SHLL/baseReg=CX/offset=0x0/dstReg=R13", n: &nodeImpl{instruction: SHLL, srcReg: RegCX, dstConst: 0x0, dstReg: RegR13}, exp: []byte{0x41, 0xd3, 0x65, 0x0}}, - {name: "SHLL/srcReg=CX/baseReg=R13/offset=0x0/index=R10/scale=4", n: &nodeImpl{instruction: SHLL, srcReg: RegCX, dstConst: 0x0, dstMemIndex: RegR10, dstMemScale: 4, dstReg: RegR13}, exp: []byte{0x43, 0xd3, 0x64, 0x95, 0x0}}, - {name: "SHLL/baseReg=CX/offset=0x1/dstReg=R13", n: &nodeImpl{instruction: SHLL, srcReg: RegCX, dstConst: 0x1, dstReg: RegR13}, exp: []byte{0x41, 0xd3, 0x65, 0x1}}, - {name: "SHLL/srcReg=CX/baseReg=R13/offset=0x1/index=R10/scale=4", n: &nodeImpl{instruction: SHLL, srcReg: RegCX, dstConst: 0x1, dstMemIndex: RegR10, dstMemScale: 4, dstReg: RegR13}, exp: []byte{0x43, 0xd3, 0x64, 0x95, 0x1}}, - {name: "SHLL/baseReg=CX/offset=0x7fffffff/dstReg=R13", n: &nodeImpl{instruction: SHLL, srcReg: RegCX, dstConst: 0x7fffffff, dstReg: RegR13}, exp: []byte{0x41, 0xd3, 0xa5, 0xff, 0xff, 0xff, 0x7f}}, - {name: "SHLL/srcReg=CX/baseReg=R13/offset=0x7fffffff/index=R10/scale=4", n: &nodeImpl{instruction: SHLL, srcReg: RegCX, dstConst: 0x7fffffff, dstMemIndex: RegR10, dstMemScale: 4, dstReg: RegR13}, exp: []byte{0x43, 0xd3, 0xa4, 0x95, 0xff, 0xff, 0xff, 0x7f}}, - {name: "SHLQ/baseReg=CX/offset=0x0/dstReg=R13", n: &nodeImpl{instruction: SHLQ, srcReg: RegCX, dstConst: 0x0, dstReg: RegR13}, exp: []byte{0x49, 0xd3, 0x65, 0x0}}, - {name: "SHLQ/srcReg=CX/baseReg=R13/offset=0x0/index=R10/scale=4", n: &nodeImpl{instruction: SHLQ, srcReg: RegCX, dstConst: 0x0, dstMemIndex: RegR10, dstMemScale: 4, dstReg: RegR13}, exp: []byte{0x4b, 0xd3, 0x64, 0x95, 0x0}}, - {name: "SHLQ/baseReg=CX/offset=0x1/dstReg=R13", n: &nodeImpl{instruction: SHLQ, srcReg: RegCX, dstConst: 0x1, dstReg: RegR13}, exp: []byte{0x49, 0xd3, 0x65, 0x1}}, - {name: "SHLQ/srcReg=CX/baseReg=R13/offset=0x1/index=R10/scale=4", n: &nodeImpl{instruction: SHLQ, srcReg: RegCX, dstConst: 0x1, dstMemIndex: RegR10, dstMemScale: 4, dstReg: RegR13}, exp: []byte{0x4b, 0xd3, 0x64, 0x95, 0x1}}, - {name: "SHLQ/baseReg=CX/offset=0x7fffffff/dstReg=R13", n: &nodeImpl{instruction: SHLQ, srcReg: RegCX, dstConst: 0x7fffffff, dstReg: RegR13}, exp: []byte{0x49, 0xd3, 0xa5, 0xff, 0xff, 0xff, 0x7f}}, - {name: "SHLQ/srcReg=CX/baseReg=R13/offset=0x7fffffff/index=R10/scale=4", n: &nodeImpl{instruction: SHLQ, srcReg: RegCX, dstConst: 0x7fffffff, dstMemIndex: RegR10, dstMemScale: 4, dstReg: RegR13}, exp: []byte{0x4b, 0xd3, 0xa4, 0x95, 0xff, 0xff, 0xff, 0x7f}}, - {name: "SHRL/baseReg=CX/offset=0x0/dstReg=R13", n: &nodeImpl{instruction: SHRL, srcReg: RegCX, dstConst: 0x0, dstReg: RegR13}, exp: []byte{0x41, 0xd3, 0x6d, 0x0}}, - {name: "SHRL/srcReg=CX/baseReg=R13/offset=0x0/index=R10/scale=4", n: &nodeImpl{instruction: SHRL, srcReg: RegCX, dstConst: 0x0, dstMemIndex: RegR10, dstMemScale: 4, dstReg: RegR13}, exp: []byte{0x43, 0xd3, 0x6c, 0x95, 0x0}}, - {name: "SHRL/baseReg=CX/offset=0x1/dstReg=R13", n: &nodeImpl{instruction: SHRL, srcReg: RegCX, dstConst: 0x1, dstReg: RegR13}, exp: []byte{0x41, 0xd3, 0x6d, 0x1}}, - {name: "SHRL/srcReg=CX/baseReg=R13/offset=0x1/index=R10/scale=4", n: &nodeImpl{instruction: SHRL, srcReg: RegCX, dstConst: 0x1, dstMemIndex: RegR10, dstMemScale: 4, dstReg: RegR13}, exp: []byte{0x43, 0xd3, 0x6c, 0x95, 0x1}}, - {name: "SHRL/baseReg=CX/offset=0x7fffffff/dstReg=R13", n: &nodeImpl{instruction: SHRL, srcReg: RegCX, dstConst: 0x7fffffff, dstReg: RegR13}, exp: []byte{0x41, 0xd3, 0xad, 0xff, 0xff, 0xff, 0x7f}}, - {name: "SHRL/srcReg=CX/baseReg=R13/offset=0x7fffffff/index=R10/scale=4", n: &nodeImpl{instruction: SHRL, srcReg: RegCX, dstConst: 0x7fffffff, dstMemIndex: RegR10, dstMemScale: 4, dstReg: RegR13}, exp: []byte{0x43, 0xd3, 0xac, 0x95, 0xff, 0xff, 0xff, 0x7f}}, - {name: "SHRQ/baseReg=CX/offset=0x0/dstReg=R13", n: &nodeImpl{instruction: SHRQ, srcReg: RegCX, dstConst: 0x0, dstReg: RegR13}, exp: []byte{0x49, 0xd3, 0x6d, 0x0}}, - {name: "SHRQ/srcReg=CX/baseReg=R13/offset=0x0/index=R10/scale=4", n: &nodeImpl{instruction: SHRQ, srcReg: RegCX, dstConst: 0x0, dstMemIndex: RegR10, dstMemScale: 4, dstReg: RegR13}, exp: []byte{0x4b, 0xd3, 0x6c, 0x95, 0x0}}, - {name: "SHRQ/baseReg=CX/offset=0x1/dstReg=R13", n: &nodeImpl{instruction: SHRQ, srcReg: RegCX, dstConst: 0x1, dstReg: RegR13}, exp: []byte{0x49, 0xd3, 0x6d, 0x1}}, - {name: "SHRQ/srcReg=CX/baseReg=R13/offset=0x1/index=R10/scale=4", n: &nodeImpl{instruction: SHRQ, srcReg: RegCX, dstConst: 0x1, dstMemIndex: RegR10, dstMemScale: 4, dstReg: RegR13}, exp: []byte{0x4b, 0xd3, 0x6c, 0x95, 0x1}}, - {name: "SHRQ/baseReg=CX/offset=0x7fffffff/dstReg=R13", n: &nodeImpl{instruction: SHRQ, srcReg: RegCX, dstConst: 0x7fffffff, dstReg: RegR13}, exp: []byte{0x49, 0xd3, 0xad, 0xff, 0xff, 0xff, 0x7f}}, - {name: "SHRQ/srcReg=CX/baseReg=R13/offset=0x7fffffff/index=R10/scale=4", n: &nodeImpl{instruction: SHRQ, srcReg: RegCX, dstConst: 0x7fffffff, dstMemIndex: RegR10, dstMemScale: 4, dstReg: RegR13}, exp: []byte{0x4b, 0xd3, 0xac, 0x95, 0xff, 0xff, 0xff, 0x7f}}, - {name: "ROLL/baseReg=CX/offset=0x0/dstReg=R13", n: &nodeImpl{instruction: ROLL, srcReg: RegCX, dstConst: 0x0, dstReg: RegR13}, exp: []byte{0x41, 0xd3, 0x45, 0x0}}, - {name: "ROLL/srcReg=CX/baseReg=R13/offset=0x0/index=R10/scale=4", n: &nodeImpl{instruction: ROLL, srcReg: RegCX, dstConst: 0x0, dstMemIndex: RegR10, dstMemScale: 4, dstReg: RegR13}, exp: []byte{0x43, 0xd3, 0x44, 0x95, 0x0}}, - {name: "ROLL/baseReg=CX/offset=0x1/dstReg=R13", n: &nodeImpl{instruction: ROLL, srcReg: RegCX, dstConst: 0x1, dstReg: RegR13}, exp: []byte{0x41, 0xd3, 0x45, 0x1}}, - {name: "ROLL/srcReg=CX/baseReg=R13/offset=0x1/index=R10/scale=4", n: &nodeImpl{instruction: ROLL, srcReg: RegCX, dstConst: 0x1, dstMemIndex: RegR10, dstMemScale: 4, dstReg: RegR13}, exp: []byte{0x43, 0xd3, 0x44, 0x95, 0x1}}, - {name: "ROLL/baseReg=CX/offset=0x7fffffff/dstReg=R13", n: &nodeImpl{instruction: ROLL, srcReg: RegCX, dstConst: 0x7fffffff, dstReg: RegR13}, exp: []byte{0x41, 0xd3, 0x85, 0xff, 0xff, 0xff, 0x7f}}, - {name: "ROLL/srcReg=CX/baseReg=R13/offset=0x7fffffff/index=R10/scale=4", n: &nodeImpl{instruction: ROLL, srcReg: RegCX, dstConst: 0x7fffffff, dstMemIndex: RegR10, dstMemScale: 4, dstReg: RegR13}, exp: []byte{0x43, 0xd3, 0x84, 0x95, 0xff, 0xff, 0xff, 0x7f}}, - {name: "ROLQ/baseReg=CX/offset=0x0/dstReg=R13", n: &nodeImpl{instruction: ROLQ, srcReg: RegCX, dstConst: 0x0, dstReg: RegR13}, exp: []byte{0x49, 0xd3, 0x45, 0x0}}, - {name: "ROLQ/srcReg=CX/baseReg=R13/offset=0x0/index=R10/scale=4", n: &nodeImpl{instruction: ROLQ, srcReg: RegCX, dstConst: 0x0, dstMemIndex: RegR10, dstMemScale: 4, dstReg: RegR13}, exp: []byte{0x4b, 0xd3, 0x44, 0x95, 0x0}}, - {name: "ROLQ/baseReg=CX/offset=0x1/dstReg=R13", n: &nodeImpl{instruction: ROLQ, srcReg: RegCX, dstConst: 0x1, dstReg: RegR13}, exp: []byte{0x49, 0xd3, 0x45, 0x1}}, - {name: "ROLQ/srcReg=CX/baseReg=R13/offset=0x1/index=R10/scale=4", n: &nodeImpl{instruction: ROLQ, srcReg: RegCX, dstConst: 0x1, dstMemIndex: RegR10, dstMemScale: 4, dstReg: RegR13}, exp: []byte{0x4b, 0xd3, 0x44, 0x95, 0x1}}, - {name: "ROLQ/baseReg=CX/offset=0x7fffffff/dstReg=R13", n: &nodeImpl{instruction: ROLQ, srcReg: RegCX, dstConst: 0x7fffffff, dstReg: RegR13}, exp: []byte{0x49, 0xd3, 0x85, 0xff, 0xff, 0xff, 0x7f}}, - {name: "ROLQ/srcReg=CX/baseReg=R13/offset=0x7fffffff/index=R10/scale=4", n: &nodeImpl{instruction: ROLQ, srcReg: RegCX, dstConst: 0x7fffffff, dstMemIndex: RegR10, dstMemScale: 4, dstReg: RegR13}, exp: []byte{0x4b, 0xd3, 0x84, 0x95, 0xff, 0xff, 0xff, 0x7f}}, - {name: "RORL/baseReg=CX/offset=0x0/dstReg=R13", n: &nodeImpl{instruction: RORL, srcReg: RegCX, dstConst: 0x0, dstReg: RegR13}, exp: []byte{0x41, 0xd3, 0x4d, 0x0}}, - {name: "RORL/srcReg=CX/baseReg=R13/offset=0x0/index=R10/scale=4", n: &nodeImpl{instruction: RORL, srcReg: RegCX, dstConst: 0x0, dstMemIndex: RegR10, dstMemScale: 4, dstReg: RegR13}, exp: []byte{0x43, 0xd3, 0x4c, 0x95, 0x0}}, - {name: "RORL/baseReg=CX/offset=0x1/dstReg=R13", n: &nodeImpl{instruction: RORL, srcReg: RegCX, dstConst: 0x1, dstReg: RegR13}, exp: []byte{0x41, 0xd3, 0x4d, 0x1}}, - {name: "RORL/srcReg=CX/baseReg=R13/offset=0x1/index=R10/scale=4", n: &nodeImpl{instruction: RORL, srcReg: RegCX, dstConst: 0x1, dstMemIndex: RegR10, dstMemScale: 4, dstReg: RegR13}, exp: []byte{0x43, 0xd3, 0x4c, 0x95, 0x1}}, - {name: "RORL/baseReg=CX/offset=0x7fffffff/dstReg=R13", n: &nodeImpl{instruction: RORL, srcReg: RegCX, dstConst: 0x7fffffff, dstReg: RegR13}, exp: []byte{0x41, 0xd3, 0x8d, 0xff, 0xff, 0xff, 0x7f}}, - {name: "RORL/srcReg=CX/baseReg=R13/offset=0x7fffffff/index=R10/scale=4", n: &nodeImpl{instruction: RORL, srcReg: RegCX, dstConst: 0x7fffffff, dstMemIndex: RegR10, dstMemScale: 4, dstReg: RegR13}, exp: []byte{0x43, 0xd3, 0x8c, 0x95, 0xff, 0xff, 0xff, 0x7f}}, - {name: "RORQ/baseReg=CX/offset=0x0/dstReg=R13", n: &nodeImpl{instruction: RORQ, srcReg: RegCX, dstConst: 0x0, dstReg: RegR13}, exp: []byte{0x49, 0xd3, 0x4d, 0x0}}, - {name: "RORQ/srcReg=CX/baseReg=R13/offset=0x0/index=R10/scale=4", n: &nodeImpl{instruction: RORQ, srcReg: RegCX, dstConst: 0x0, dstMemIndex: RegR10, dstMemScale: 4, dstReg: RegR13}, exp: []byte{0x4b, 0xd3, 0x4c, 0x95, 0x0}}, - {name: "RORQ/baseReg=CX/offset=0x1/dstReg=R13", n: &nodeImpl{instruction: RORQ, srcReg: RegCX, dstConst: 0x1, dstReg: RegR13}, exp: []byte{0x49, 0xd3, 0x4d, 0x1}}, - {name: "RORQ/srcReg=CX/baseReg=R13/offset=0x1/index=R10/scale=4", n: &nodeImpl{instruction: RORQ, srcReg: RegCX, dstConst: 0x1, dstMemIndex: RegR10, dstMemScale: 4, dstReg: RegR13}, exp: []byte{0x4b, 0xd3, 0x4c, 0x95, 0x1}}, - {name: "RORQ/baseReg=CX/offset=0x7fffffff/dstReg=R13", n: &nodeImpl{instruction: RORQ, srcReg: RegCX, dstConst: 0x7fffffff, dstReg: RegR13}, exp: []byte{0x49, 0xd3, 0x8d, 0xff, 0xff, 0xff, 0x7f}}, - {name: "RORQ/srcReg=CX/baseReg=R13/offset=0x7fffffff/index=R10/scale=4", n: &nodeImpl{instruction: RORQ, srcReg: RegCX, dstConst: 0x7fffffff, dstMemIndex: RegR10, dstMemScale: 4, dstReg: RegR13}, exp: []byte{0x4b, 0xd3, 0x8c, 0x95, 0xff, 0xff, 0xff, 0x7f}}, - {name: "xchgb %r12b, (%r8)", n: &nodeImpl{instruction: XCHGB, srcReg: RegR12, dstConst: 0x0, dstReg: RegR8}, exp: []byte{0x45, 0x86, 0x20}}, - {name: "xchgb %r12b, (%r8, %r11, 4)", n: &nodeImpl{instruction: XCHGB, srcReg: RegR12, dstConst: 0x0, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x47, 0x86, 0x24, 0x98}}, - {name: "xchgb %r12b, 1(%r8)", n: &nodeImpl{instruction: XCHGB, srcReg: RegR12, dstConst: 0x1, dstReg: RegR8}, exp: []byte{0x45, 0x86, 0x60, 0x1}}, - {name: "xchgb %r12b, 1(%r8, %r11, 4)", n: &nodeImpl{instruction: XCHGB, srcReg: RegR12, dstConst: 0x1, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x47, 0x86, 0x64, 0x98, 0x1}}, - {name: "xchgb %r12b, 0x7fffffff(%r8)", n: &nodeImpl{instruction: XCHGB, srcReg: RegR12, dstConst: 0x7fffffff, dstReg: RegR8}, exp: []byte{0x45, 0x86, 0xa0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "xchgb %r12b, 0x7fffffff(%r8, %r11, 4)", n: &nodeImpl{instruction: XCHGB, srcReg: RegR12, dstConst: 0x7fffffff, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x47, 0x86, 0xa4, 0x98, 0xff, 0xff, 0xff, 0x7f}}, - {name: "xchgb %sil, (%r8)", n: &nodeImpl{instruction: XCHGB, srcReg: RegSI, dstConst: 0x0, dstReg: RegR8}, exp: []byte{0x41, 0x86, 0x30}}, - {name: "xchgb %sil, (%r8, %r11, 4)", n: &nodeImpl{instruction: XCHGB, srcReg: RegSI, dstConst: 0x0, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x43, 0x86, 0x34, 0x98}}, - {name: "xchgb %sil, 1(%r8)", n: &nodeImpl{instruction: XCHGB, srcReg: RegSI, dstConst: 0x1, dstReg: RegR8}, exp: []byte{0x41, 0x86, 0x70, 0x1}}, - {name: "xchgb %sil, 1(%r8, %r11, 4)", n: &nodeImpl{instruction: XCHGB, srcReg: RegSI, dstConst: 0x1, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x43, 0x86, 0x74, 0x98, 0x1}}, - {name: "xchgb %sil, 0x7fffffff(%r8)", n: &nodeImpl{instruction: XCHGB, srcReg: RegSI, dstConst: 0x7fffffff, dstReg: RegR8}, exp: []byte{0x41, 0x86, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "xchgb %sil, 0x7fffffff(%r8, %r11, 4)", n: &nodeImpl{instruction: XCHGB, srcReg: RegSI, dstConst: 0x7fffffff, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x43, 0x86, 0xb4, 0x98, 0xff, 0xff, 0xff, 0x7f}}, - {name: "xchgl %r12d, (%r8)", n: &nodeImpl{instruction: XCHGL, srcReg: RegR12, dstConst: 0x0, dstReg: RegR8}, exp: []byte{0x45, 0x87, 0x20}}, - {name: "xchgl %r12d, (%r8, %r11, 4)", n: &nodeImpl{instruction: XCHGL, srcReg: RegR12, dstConst: 0x0, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x47, 0x87, 0x24, 0x98}}, - {name: "xchgl %r12d, 1(%r8)", n: &nodeImpl{instruction: XCHGL, srcReg: RegR12, dstConst: 0x1, dstReg: RegR8}, exp: []byte{0x45, 0x87, 0x60, 0x1}}, - {name: "xchgl %r12d, 1(%r8, %r11, 4)", n: &nodeImpl{instruction: XCHGL, srcReg: RegR12, dstConst: 0x1, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x47, 0x87, 0x64, 0x98, 0x1}}, - {name: "xchgl %r12d, 0x7fffffff(%r8)", n: &nodeImpl{instruction: XCHGL, srcReg: RegR12, dstConst: 0x7fffffff, dstReg: RegR8}, exp: []byte{0x45, 0x87, 0xa0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "xchgl %r12d, 0x7fffffff(%r8, %r11, 4)", n: &nodeImpl{instruction: XCHGL, srcReg: RegR12, dstConst: 0x7fffffff, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x47, 0x87, 0xa4, 0x98, 0xff, 0xff, 0xff, 0x7f}}, - {name: "xchgl %r10d, (%r8)", n: &nodeImpl{instruction: XCHGL, srcReg: RegX10, dstConst: 0x0, dstReg: RegR8}, exp: []byte{0x45, 0x87, 0x10}}, - {name: "xchgl %r10d, (%r8, %r11, 4)", n: &nodeImpl{instruction: XCHGL, srcReg: RegX10, dstConst: 0x0, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x47, 0x87, 0x14, 0x98}}, - {name: "xchgl %r10d, 1(%r8)", n: &nodeImpl{instruction: XCHGL, srcReg: RegX10, dstConst: 0x1, dstReg: RegR8}, exp: []byte{0x45, 0x87, 0x50, 0x1}}, - {name: "xchgl %r10d, 1(%r8, %r11, 4)", n: &nodeImpl{instruction: XCHGL, srcReg: RegX10, dstConst: 0x1, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x47, 0x87, 0x54, 0x98, 0x1}}, - {name: "xchgl %r10d, 0x7fffffff(%r8)", n: &nodeImpl{instruction: XCHGL, srcReg: RegX10, dstConst: 0x7fffffff, dstReg: RegR8}, exp: []byte{0x45, 0x87, 0x90, 0xff, 0xff, 0xff, 0x7f}}, - {name: "xchgl %r10d, 0x7fffffff(%r8, %r11, 4)", n: &nodeImpl{instruction: XCHGL, srcReg: RegX10, dstConst: 0x7fffffff, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x47, 0x87, 0x94, 0x98, 0xff, 0xff, 0xff, 0x7f}}, - {name: "xchgq %r12, (%r8)", n: &nodeImpl{instruction: XCHGQ, srcReg: RegR12, dstConst: 0x0, dstReg: RegR8}, exp: []byte{0x4d, 0x87, 0x20}}, - {name: "xchgq %r12, (%r8, %r11, 4)", n: &nodeImpl{instruction: XCHGQ, srcReg: RegR12, dstConst: 0x0, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x4f, 0x87, 0x24, 0x98}}, - {name: "xchgq %r12, 1(%r8)", n: &nodeImpl{instruction: XCHGQ, srcReg: RegR12, dstConst: 0x1, dstReg: RegR8}, exp: []byte{0x4d, 0x87, 0x60, 0x1}}, - {name: "xchgq %r12, 1(%r8, %r11, 4)", n: &nodeImpl{instruction: XCHGQ, srcReg: RegR12, dstConst: 0x1, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x4f, 0x87, 0x64, 0x98, 0x1}}, - {name: "xchgq %r12, 0x7fffffff(%r8)", n: &nodeImpl{instruction: XCHGQ, srcReg: RegR12, dstConst: 0x7fffffff, dstReg: RegR8}, exp: []byte{0x4d, 0x87, 0xa0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "xchgq %r12, 0x7fffffff(%r8, %r11, 4)", n: &nodeImpl{instruction: XCHGQ, srcReg: RegR12, dstConst: 0x7fffffff, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x4f, 0x87, 0xa4, 0x98, 0xff, 0xff, 0xff, 0x7f}}, - {name: "xchgq %r10, (%r8)", n: &nodeImpl{instruction: XCHGQ, srcReg: RegX10, dstConst: 0x0, dstReg: RegR8}, exp: []byte{0x4d, 0x87, 0x10}}, - {name: "xchgq %r10, (%r8, %r11, 4)", n: &nodeImpl{instruction: XCHGQ, srcReg: RegX10, dstConst: 0x0, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x4f, 0x87, 0x14, 0x98}}, - {name: "xchgq %r10, 1(%r8)", n: &nodeImpl{instruction: XCHGQ, srcReg: RegX10, dstConst: 0x1, dstReg: RegR8}, exp: []byte{0x4d, 0x87, 0x50, 0x1}}, - {name: "xchgq %r10, 1(%r8, %r11, 4)", n: &nodeImpl{instruction: XCHGQ, srcReg: RegX10, dstConst: 0x1, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x4f, 0x87, 0x54, 0x98, 0x1}}, - {name: "xchgq %r10, 0x7fffffff(%r8)", n: &nodeImpl{instruction: XCHGQ, srcReg: RegX10, dstConst: 0x7fffffff, dstReg: RegR8}, exp: []byte{0x4d, 0x87, 0x90, 0xff, 0xff, 0xff, 0x7f}}, - {name: "xchgq %r10, 0x7fffffff(%r8, %r11, 4)", n: &nodeImpl{instruction: XCHGQ, srcReg: RegX10, dstConst: 0x7fffffff, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x4f, 0x87, 0x94, 0x98, 0xff, 0xff, 0xff, 0x7f}}, - {name: "xchgw %r12w, (%r8)", n: &nodeImpl{instruction: XCHGW, srcReg: RegR12, dstConst: 0x0, dstReg: RegR8}, exp: []byte{0x66, 0x45, 0x87, 0x20}}, - {name: "xchgw %r12w, (%r8, %r11, 4)", n: &nodeImpl{instruction: XCHGW, srcReg: RegR12, dstConst: 0x0, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x66, 0x47, 0x87, 0x24, 0x98}}, - {name: "xchgw %r12w, 1(%r8)", n: &nodeImpl{instruction: XCHGW, srcReg: RegR12, dstConst: 0x1, dstReg: RegR8}, exp: []byte{0x66, 0x45, 0x87, 0x60, 0x1}}, - {name: "xchgw %r12w, 1(%r8, %r11, 4)", n: &nodeImpl{instruction: XCHGW, srcReg: RegR12, dstConst: 0x1, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x66, 0x47, 0x87, 0x64, 0x98, 0x1}}, - {name: "xchgw %r12w, 0x7fffffff(%r8)", n: &nodeImpl{instruction: XCHGW, srcReg: RegR12, dstConst: 0x7fffffff, dstReg: RegR8}, exp: []byte{0x66, 0x45, 0x87, 0xa0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "xchgw %r12w, 0x7fffffff(%r8, %r11, 4)", n: &nodeImpl{instruction: XCHGW, srcReg: RegR12, dstConst: 0x7fffffff, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x66, 0x47, 0x87, 0xa4, 0x98, 0xff, 0xff, 0xff, 0x7f}}, - {name: "xchgw %si, (%r8)", n: &nodeImpl{instruction: XCHGW, srcReg: RegSI, dstConst: 0x0, dstReg: RegR8}, exp: []byte{0x66, 0x41, 0x87, 0x30}}, - {name: "xchgw %si, (%r8, %r11, 4)", n: &nodeImpl{instruction: XCHGW, srcReg: RegSI, dstConst: 0x0, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x66, 0x43, 0x87, 0x34, 0x98}}, - {name: "xchgw %si, 1(%r8)", n: &nodeImpl{instruction: XCHGW, srcReg: RegSI, dstConst: 0x1, dstReg: RegR8}, exp: []byte{0x66, 0x41, 0x87, 0x70, 0x1}}, - {name: "xchgw %si, 1(%r8, %r11, 4)", n: &nodeImpl{instruction: XCHGW, srcReg: RegSI, dstConst: 0x1, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x66, 0x43, 0x87, 0x74, 0x98, 0x1}}, - {name: "xchgw %si, 0x7fffffff(%r8)", n: &nodeImpl{instruction: XCHGW, srcReg: RegSI, dstConst: 0x7fffffff, dstReg: RegR8}, exp: []byte{0x66, 0x41, 0x87, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "xchgw %si, 0x7fffffff(%r8, %r11, 4)", n: &nodeImpl{instruction: XCHGW, srcReg: RegSI, dstConst: 0x7fffffff, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x66, 0x43, 0x87, 0xb4, 0x98, 0xff, 0xff, 0xff, 0x7f}}, - {name: "lock xaddb %r12b, (%r8)", n: &nodeImpl{instruction: XADDB, flag: nodeFlagLock, srcReg: RegR12, dstConst: 0x0, dstReg: RegR8}, exp: []byte{0xf0, 0x45, 0xf, 0xc0, 0x20}}, - {name: "lock xaddb %r12b, (%r8, %r11, 4)", n: &nodeImpl{instruction: XADDB, flag: nodeFlagLock, srcReg: RegR12, dstConst: 0x0, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0xf0, 0x47, 0xf, 0xc0, 0x24, 0x98}}, - {name: "lock xaddb %r12b, 1(%r8)", n: &nodeImpl{instruction: XADDB, flag: nodeFlagLock, srcReg: RegR12, dstConst: 0x1, dstReg: RegR8}, exp: []byte{0xf0, 0x45, 0xf, 0xc0, 0x60, 0x1}}, - {name: "lock xaddb %r12b, 1(%r8, %r11, 4)", n: &nodeImpl{instruction: XADDB, flag: nodeFlagLock, srcReg: RegR12, dstConst: 0x1, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0xf0, 0x47, 0xf, 0xc0, 0x64, 0x98, 0x1}}, - {name: "lock xaddb %r12b, 0x7fffffff(%r8)", n: &nodeImpl{instruction: XADDB, flag: nodeFlagLock, srcReg: RegR12, dstConst: 0x7fffffff, dstReg: RegR8}, exp: []byte{0xf0, 0x45, 0xf, 0xc0, 0xa0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "lock xaddb %r12b, 0x7fffffff(%r8, %r11, 4)", n: &nodeImpl{instruction: XADDB, flag: nodeFlagLock, srcReg: RegR12, dstConst: 0x7fffffff, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0xf0, 0x47, 0xf, 0xc0, 0xa4, 0x98, 0xff, 0xff, 0xff, 0x7f}}, - {name: "lock xaddb %sil, (%r8)", n: &nodeImpl{instruction: XADDB, flag: nodeFlagLock, srcReg: RegSI, dstConst: 0x0, dstReg: RegR8}, exp: []byte{0xf0, 0x41, 0xf, 0xc0, 0x30}}, - {name: "lock xaddb %sil, (%r8, %r11, 4)", n: &nodeImpl{instruction: XADDB, flag: nodeFlagLock, srcReg: RegSI, dstConst: 0x0, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0xf0, 0x43, 0xf, 0xc0, 0x34, 0x98}}, - {name: "lock xaddb %sil, 1(%r8)", n: &nodeImpl{instruction: XADDB, flag: nodeFlagLock, srcReg: RegSI, dstConst: 0x1, dstReg: RegR8}, exp: []byte{0xf0, 0x41, 0xf, 0xc0, 0x70, 0x1}}, - {name: "lock xaddb %sil, 1(%r8, %r11, 4)", n: &nodeImpl{instruction: XADDB, flag: nodeFlagLock, srcReg: RegSI, dstConst: 0x1, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0xf0, 0x43, 0xf, 0xc0, 0x74, 0x98, 0x1}}, - {name: "lock xaddb %sil, 0x7fffffff(%r8)", n: &nodeImpl{instruction: XADDB, flag: nodeFlagLock, srcReg: RegSI, dstConst: 0x7fffffff, dstReg: RegR8}, exp: []byte{0xf0, 0x41, 0xf, 0xc0, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "lock xaddb %sil, 0x7fffffff(%r8, %r11, 4)", n: &nodeImpl{instruction: XADDB, flag: nodeFlagLock, srcReg: RegSI, dstConst: 0x7fffffff, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0xf0, 0x43, 0xf, 0xc0, 0xb4, 0x98, 0xff, 0xff, 0xff, 0x7f}}, - {name: "lock xaddl %r12d, (%r8)", n: &nodeImpl{instruction: XADDL, flag: nodeFlagLock, srcReg: RegR12, dstConst: 0x0, dstReg: RegR8}, exp: []byte{0xf0, 0x45, 0xf, 0xc1, 0x20}}, - {name: "lock xaddl %r12d, (%r8, %r11, 4)", n: &nodeImpl{instruction: XADDL, flag: nodeFlagLock, srcReg: RegR12, dstConst: 0x0, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0xf0, 0x47, 0xf, 0xc1, 0x24, 0x98}}, - {name: "lock xaddl %r12d, 1(%r8)", n: &nodeImpl{instruction: XADDL, flag: nodeFlagLock, srcReg: RegR12, dstConst: 0x1, dstReg: RegR8}, exp: []byte{0xf0, 0x45, 0xf, 0xc1, 0x60, 0x1}}, - {name: "lock xaddl %r12d, 1(%r8, %r11, 4)", n: &nodeImpl{instruction: XADDL, flag: nodeFlagLock, srcReg: RegR12, dstConst: 0x1, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0xf0, 0x47, 0xf, 0xc1, 0x64, 0x98, 0x1}}, - {name: "lock xaddl %r12d, 0x7fffffff(%r8)", n: &nodeImpl{instruction: XADDL, flag: nodeFlagLock, srcReg: RegR12, dstConst: 0x7fffffff, dstReg: RegR8}, exp: []byte{0xf0, 0x45, 0xf, 0xc1, 0xa0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "lock xaddl %r12d, 0x7fffffff(%r8, %r11, 4)", n: &nodeImpl{instruction: XADDL, flag: nodeFlagLock, srcReg: RegR12, dstConst: 0x7fffffff, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0xf0, 0x47, 0xf, 0xc1, 0xa4, 0x98, 0xff, 0xff, 0xff, 0x7f}}, - {name: "lock xaddl %r10d, (%r8)", n: &nodeImpl{instruction: XADDL, flag: nodeFlagLock, srcReg: RegX10, dstConst: 0x0, dstReg: RegR8}, exp: []byte{0xf0, 0x45, 0xf, 0xc1, 0x10}}, - {name: "lock xaddl %r10d, (%r8, %r11, 4)", n: &nodeImpl{instruction: XADDL, flag: nodeFlagLock, srcReg: RegX10, dstConst: 0x0, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0xf0, 0x47, 0xf, 0xc1, 0x14, 0x98}}, - {name: "lock xaddl %r10d, 1(%r8)", n: &nodeImpl{instruction: XADDL, flag: nodeFlagLock, srcReg: RegX10, dstConst: 0x1, dstReg: RegR8}, exp: []byte{0xf0, 0x45, 0xf, 0xc1, 0x50, 0x1}}, - {name: "lock xaddl %r10d, 1(%r8, %r11, 4)", n: &nodeImpl{instruction: XADDL, flag: nodeFlagLock, srcReg: RegX10, dstConst: 0x1, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0xf0, 0x47, 0xf, 0xc1, 0x54, 0x98, 0x1}}, - {name: "lock xaddl %r10d, 0x7fffffff(%r8)", n: &nodeImpl{instruction: XADDL, flag: nodeFlagLock, srcReg: RegX10, dstConst: 0x7fffffff, dstReg: RegR8}, exp: []byte{0xf0, 0x45, 0xf, 0xc1, 0x90, 0xff, 0xff, 0xff, 0x7f}}, - {name: "lock xaddl %r10d, 0x7fffffff(%r8, %r11, 4)", n: &nodeImpl{instruction: XADDL, flag: nodeFlagLock, srcReg: RegX10, dstConst: 0x7fffffff, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0xf0, 0x47, 0xf, 0xc1, 0x94, 0x98, 0xff, 0xff, 0xff, 0x7f}}, - {name: "lock xaddq %r12, (%r8)", n: &nodeImpl{instruction: XADDQ, flag: nodeFlagLock, srcReg: RegR12, dstConst: 0x0, dstReg: RegR8}, exp: []byte{0xf0, 0x4d, 0xf, 0xc1, 0x20}}, - {name: "lock xaddq %r12, (%r8, %r11, 4)", n: &nodeImpl{instruction: XADDQ, flag: nodeFlagLock, srcReg: RegR12, dstConst: 0x0, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0xf0, 0x4f, 0xf, 0xc1, 0x24, 0x98}}, - {name: "lock xaddq %r12, 1(%r8)", n: &nodeImpl{instruction: XADDQ, flag: nodeFlagLock, srcReg: RegR12, dstConst: 0x1, dstReg: RegR8}, exp: []byte{0xf0, 0x4d, 0xf, 0xc1, 0x60, 0x1}}, - {name: "lock xaddq %r12, 1(%r8, %r11, 4)", n: &nodeImpl{instruction: XADDQ, flag: nodeFlagLock, srcReg: RegR12, dstConst: 0x1, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0xf0, 0x4f, 0xf, 0xc1, 0x64, 0x98, 0x1}}, - {name: "lock xaddq %r12, 0x7fffffff(%r8)", n: &nodeImpl{instruction: XADDQ, flag: nodeFlagLock, srcReg: RegR12, dstConst: 0x7fffffff, dstReg: RegR8}, exp: []byte{0xf0, 0x4d, 0xf, 0xc1, 0xa0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "lock xaddq %r12, 0x7fffffff(%r8, %r11, 4)", n: &nodeImpl{instruction: XADDQ, flag: nodeFlagLock, srcReg: RegR12, dstConst: 0x7fffffff, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0xf0, 0x4f, 0xf, 0xc1, 0xa4, 0x98, 0xff, 0xff, 0xff, 0x7f}}, - {name: "lock xaddq %r10, (%r8)", n: &nodeImpl{instruction: XADDQ, flag: nodeFlagLock, srcReg: RegX10, dstConst: 0x0, dstReg: RegR8}, exp: []byte{0xf0, 0x4d, 0xf, 0xc1, 0x10}}, - {name: "lock xaddq %r10, (%r8, %r11, 4)", n: &nodeImpl{instruction: XADDQ, flag: nodeFlagLock, srcReg: RegX10, dstConst: 0x0, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0xf0, 0x4f, 0xf, 0xc1, 0x14, 0x98}}, - {name: "lock xaddq %r10, 1(%r8)", n: &nodeImpl{instruction: XADDQ, flag: nodeFlagLock, srcReg: RegX10, dstConst: 0x1, dstReg: RegR8}, exp: []byte{0xf0, 0x4d, 0xf, 0xc1, 0x50, 0x1}}, - {name: "lock xaddq %r10, 1(%r8, %r11, 4)", n: &nodeImpl{instruction: XADDQ, flag: nodeFlagLock, srcReg: RegX10, dstConst: 0x1, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0xf0, 0x4f, 0xf, 0xc1, 0x54, 0x98, 0x1}}, - {name: "lock xaddq %r10, 0x7fffffff(%r8)", n: &nodeImpl{instruction: XADDQ, flag: nodeFlagLock, srcReg: RegX10, dstConst: 0x7fffffff, dstReg: RegR8}, exp: []byte{0xf0, 0x4d, 0xf, 0xc1, 0x90, 0xff, 0xff, 0xff, 0x7f}}, - {name: "lock xaddq %r10, 0x7fffffff(%r8, %r11, 4)", n: &nodeImpl{instruction: XADDQ, flag: nodeFlagLock, srcReg: RegX10, dstConst: 0x7fffffff, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0xf0, 0x4f, 0xf, 0xc1, 0x94, 0x98, 0xff, 0xff, 0xff, 0x7f}}, - {name: "lock xaddw %r12w, (%r8)", n: &nodeImpl{instruction: XADDW, flag: nodeFlagLock, srcReg: RegR12, dstConst: 0x0, dstReg: RegR8}, exp: []byte{0x66, 0xf0, 0x45, 0xf, 0xc1, 0x20}}, - {name: "lock xaddw %r12w, (%r8, %r11, 4)", n: &nodeImpl{instruction: XADDW, flag: nodeFlagLock, srcReg: RegR12, dstConst: 0x0, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x66, 0xf0, 0x47, 0xf, 0xc1, 0x24, 0x98}}, - {name: "lock xaddw %r12w, 1(%r8)", n: &nodeImpl{instruction: XADDW, flag: nodeFlagLock, srcReg: RegR12, dstConst: 0x1, dstReg: RegR8}, exp: []byte{0x66, 0xf0, 0x45, 0xf, 0xc1, 0x60, 0x1}}, - {name: "lock xaddw %r12w, 1(%r8, %r11, 4)", n: &nodeImpl{instruction: XADDW, flag: nodeFlagLock, srcReg: RegR12, dstConst: 0x1, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x66, 0xf0, 0x47, 0xf, 0xc1, 0x64, 0x98, 0x1}}, - {name: "lock xaddw %r12w, 0x7fffffff(%r8)", n: &nodeImpl{instruction: XADDW, flag: nodeFlagLock, srcReg: RegR12, dstConst: 0x7fffffff, dstReg: RegR8}, exp: []byte{0x66, 0xf0, 0x45, 0xf, 0xc1, 0xa0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "lock xaddw %r12w, 0x7fffffff(%r8, %r11, 4)", n: &nodeImpl{instruction: XADDW, flag: nodeFlagLock, srcReg: RegR12, dstConst: 0x7fffffff, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x66, 0xf0, 0x47, 0xf, 0xc1, 0xa4, 0x98, 0xff, 0xff, 0xff, 0x7f}}, - {name: "lock xaddw %si, (%r8)", n: &nodeImpl{instruction: XADDW, flag: nodeFlagLock, srcReg: RegSI, dstConst: 0x0, dstReg: RegR8}, exp: []byte{0x66, 0xf0, 0x41, 0xf, 0xc1, 0x30}}, - {name: "lock xaddw %si, (%r8, %r11, 4)", n: &nodeImpl{instruction: XADDW, flag: nodeFlagLock, srcReg: RegSI, dstConst: 0x0, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x66, 0xf0, 0x43, 0xf, 0xc1, 0x34, 0x98}}, - {name: "lock xaddw %si, 1(%r8)", n: &nodeImpl{instruction: XADDW, flag: nodeFlagLock, srcReg: RegSI, dstConst: 0x1, dstReg: RegR8}, exp: []byte{0x66, 0xf0, 0x41, 0xf, 0xc1, 0x70, 0x1}}, - {name: "lock xaddw %si, 1(%r8, %r11, 4)", n: &nodeImpl{instruction: XADDW, flag: nodeFlagLock, srcReg: RegSI, dstConst: 0x1, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x66, 0xf0, 0x43, 0xf, 0xc1, 0x74, 0x98, 0x1}}, - {name: "lock xaddw %si, 0x7fffffff(%r8)", n: &nodeImpl{instruction: XADDW, flag: nodeFlagLock, srcReg: RegSI, dstConst: 0x7fffffff, dstReg: RegR8}, exp: []byte{0x66, 0xf0, 0x41, 0xf, 0xc1, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "lock xaddw %si, 0x7fffffff(%r8, %r11, 4)", n: &nodeImpl{instruction: XADDW, flag: nodeFlagLock, srcReg: RegSI, dstConst: 0x7fffffff, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x66, 0xf0, 0x43, 0xf, 0xc1, 0xb4, 0x98, 0xff, 0xff, 0xff, 0x7f}}, - {name: "lock cmpxchgb %r12b, (%r8)", n: &nodeImpl{instruction: CMPXCHGB, flag: nodeFlagLock, srcReg: RegR12, dstConst: 0x0, dstReg: RegR8}, exp: []byte{0xf0, 0x45, 0xf, 0xb0, 0x20}}, - {name: "lock cmpxchgb %r12b, (%r8, %r11, 4)", n: &nodeImpl{instruction: CMPXCHGB, flag: nodeFlagLock, srcReg: RegR12, dstConst: 0x0, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0xf0, 0x47, 0xf, 0xb0, 0x24, 0x98}}, - {name: "lock cmpxchgb %r12b, 1(%r8)", n: &nodeImpl{instruction: CMPXCHGB, flag: nodeFlagLock, srcReg: RegR12, dstConst: 0x1, dstReg: RegR8}, exp: []byte{0xf0, 0x45, 0xf, 0xb0, 0x60, 0x1}}, - {name: "lock cmpxchgb %r12b, 1(%r8, %r11, 4)", n: &nodeImpl{instruction: CMPXCHGB, flag: nodeFlagLock, srcReg: RegR12, dstConst: 0x1, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0xf0, 0x47, 0xf, 0xb0, 0x64, 0x98, 0x1}}, - {name: "lock cmpxchgb %r12b, 0x7fffffff(%r8)", n: &nodeImpl{instruction: CMPXCHGB, flag: nodeFlagLock, srcReg: RegR12, dstConst: 0x7fffffff, dstReg: RegR8}, exp: []byte{0xf0, 0x45, 0xf, 0xb0, 0xa0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "lock cmpxchgb %r12b, 0x7fffffff(%r8, %r11, 4)", n: &nodeImpl{instruction: CMPXCHGB, flag: nodeFlagLock, srcReg: RegR12, dstConst: 0x7fffffff, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0xf0, 0x47, 0xf, 0xb0, 0xa4, 0x98, 0xff, 0xff, 0xff, 0x7f}}, - {name: "lock cmpxchgb %sil, (%r8)", n: &nodeImpl{instruction: CMPXCHGB, flag: nodeFlagLock, srcReg: RegSI, dstConst: 0x0, dstReg: RegR8}, exp: []byte{0xf0, 0x41, 0xf, 0xb0, 0x30}}, - {name: "lock cmpxchgb %sil, (%r8, %r11, 4)", n: &nodeImpl{instruction: CMPXCHGB, flag: nodeFlagLock, srcReg: RegSI, dstConst: 0x0, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0xf0, 0x43, 0xf, 0xb0, 0x34, 0x98}}, - {name: "lock cmpxchgb %sil, 1(%r8)", n: &nodeImpl{instruction: CMPXCHGB, flag: nodeFlagLock, srcReg: RegSI, dstConst: 0x1, dstReg: RegR8}, exp: []byte{0xf0, 0x41, 0xf, 0xb0, 0x70, 0x1}}, - {name: "lock cmpxchgb %sil, 1(%r8, %r11, 4)", n: &nodeImpl{instruction: CMPXCHGB, flag: nodeFlagLock, srcReg: RegSI, dstConst: 0x1, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0xf0, 0x43, 0xf, 0xb0, 0x74, 0x98, 0x1}}, - {name: "lock cmpxchgb %sil, 0x7fffffff(%r8)", n: &nodeImpl{instruction: CMPXCHGB, flag: nodeFlagLock, srcReg: RegSI, dstConst: 0x7fffffff, dstReg: RegR8}, exp: []byte{0xf0, 0x41, 0xf, 0xb0, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "lock cmpxchgb %sil, 0x7fffffff(%r8, %r11, 4)", n: &nodeImpl{instruction: CMPXCHGB, flag: nodeFlagLock, srcReg: RegSI, dstConst: 0x7fffffff, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0xf0, 0x43, 0xf, 0xb0, 0xb4, 0x98, 0xff, 0xff, 0xff, 0x7f}}, - {name: "lock cmpxchgl %r12d, (%r8)", n: &nodeImpl{instruction: CMPXCHGL, flag: nodeFlagLock, srcReg: RegR12, dstConst: 0x0, dstReg: RegR8}, exp: []byte{0xf0, 0x45, 0xf, 0xb1, 0x20}}, - {name: "lock cmpxchgl %r12d, (%r8, %r11, 4)", n: &nodeImpl{instruction: CMPXCHGL, flag: nodeFlagLock, srcReg: RegR12, dstConst: 0x0, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0xf0, 0x47, 0xf, 0xb1, 0x24, 0x98}}, - {name: "lock cmpxchgl %r12d, 1(%r8)", n: &nodeImpl{instruction: CMPXCHGL, flag: nodeFlagLock, srcReg: RegR12, dstConst: 0x1, dstReg: RegR8}, exp: []byte{0xf0, 0x45, 0xf, 0xb1, 0x60, 0x1}}, - {name: "lock cmpxchgl %r12d, 1(%r8, %r11, 4)", n: &nodeImpl{instruction: CMPXCHGL, flag: nodeFlagLock, srcReg: RegR12, dstConst: 0x1, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0xf0, 0x47, 0xf, 0xb1, 0x64, 0x98, 0x1}}, - {name: "lock cmpxchgl %r12d, 0x7fffffff(%r8)", n: &nodeImpl{instruction: CMPXCHGL, flag: nodeFlagLock, srcReg: RegR12, dstConst: 0x7fffffff, dstReg: RegR8}, exp: []byte{0xf0, 0x45, 0xf, 0xb1, 0xa0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "lock cmpxchgl %r12d, 0x7fffffff(%r8, %r11, 4)", n: &nodeImpl{instruction: CMPXCHGL, flag: nodeFlagLock, srcReg: RegR12, dstConst: 0x7fffffff, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0xf0, 0x47, 0xf, 0xb1, 0xa4, 0x98, 0xff, 0xff, 0xff, 0x7f}}, - {name: "lock cmpxchgl %r10d, (%r8)", n: &nodeImpl{instruction: CMPXCHGL, flag: nodeFlagLock, srcReg: RegX10, dstConst: 0x0, dstReg: RegR8}, exp: []byte{0xf0, 0x45, 0xf, 0xb1, 0x10}}, - {name: "lock cmpxchgl %r10d, (%r8, %r11, 4)", n: &nodeImpl{instruction: CMPXCHGL, flag: nodeFlagLock, srcReg: RegX10, dstConst: 0x0, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0xf0, 0x47, 0xf, 0xb1, 0x14, 0x98}}, - {name: "lock cmpxchgl %r10d, 1(%r8)", n: &nodeImpl{instruction: CMPXCHGL, flag: nodeFlagLock, srcReg: RegX10, dstConst: 0x1, dstReg: RegR8}, exp: []byte{0xf0, 0x45, 0xf, 0xb1, 0x50, 0x1}}, - {name: "lock cmpxchgl %r10d, 1(%r8, %r11, 4)", n: &nodeImpl{instruction: CMPXCHGL, flag: nodeFlagLock, srcReg: RegX10, dstConst: 0x1, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0xf0, 0x47, 0xf, 0xb1, 0x54, 0x98, 0x1}}, - {name: "lock cmpxchgl %r10d, 0x7fffffff(%r8)", n: &nodeImpl{instruction: CMPXCHGL, flag: nodeFlagLock, srcReg: RegX10, dstConst: 0x7fffffff, dstReg: RegR8}, exp: []byte{0xf0, 0x45, 0xf, 0xb1, 0x90, 0xff, 0xff, 0xff, 0x7f}}, - {name: "lock cmpxchgl %r10d, 0x7fffffff(%r8, %r11, 4)", n: &nodeImpl{instruction: CMPXCHGL, flag: nodeFlagLock, srcReg: RegX10, dstConst: 0x7fffffff, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0xf0, 0x47, 0xf, 0xb1, 0x94, 0x98, 0xff, 0xff, 0xff, 0x7f}}, - {name: "lock cmpxchgq %r12, (%r8)", n: &nodeImpl{instruction: CMPXCHGQ, flag: nodeFlagLock, srcReg: RegR12, dstConst: 0x0, dstReg: RegR8}, exp: []byte{0xf0, 0x4d, 0xf, 0xb1, 0x20}}, - {name: "lock cmpxchgq %r12, (%r8, %r11, 4)", n: &nodeImpl{instruction: CMPXCHGQ, flag: nodeFlagLock, srcReg: RegR12, dstConst: 0x0, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0xf0, 0x4f, 0xf, 0xb1, 0x24, 0x98}}, - {name: "lock cmpxchgq %r12, 1(%r8)", n: &nodeImpl{instruction: CMPXCHGQ, flag: nodeFlagLock, srcReg: RegR12, dstConst: 0x1, dstReg: RegR8}, exp: []byte{0xf0, 0x4d, 0xf, 0xb1, 0x60, 0x1}}, - {name: "lock cmpxchgq %r12, 1(%r8, %r11, 4)", n: &nodeImpl{instruction: CMPXCHGQ, flag: nodeFlagLock, srcReg: RegR12, dstConst: 0x1, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0xf0, 0x4f, 0xf, 0xb1, 0x64, 0x98, 0x1}}, - {name: "lock cmpxchgq %r12, 0x7fffffff(%r8)", n: &nodeImpl{instruction: CMPXCHGQ, flag: nodeFlagLock, srcReg: RegR12, dstConst: 0x7fffffff, dstReg: RegR8}, exp: []byte{0xf0, 0x4d, 0xf, 0xb1, 0xa0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "lock cmpxchgq %r12, 0x7fffffff(%r8, %r11, 4)", n: &nodeImpl{instruction: CMPXCHGQ, flag: nodeFlagLock, srcReg: RegR12, dstConst: 0x7fffffff, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0xf0, 0x4f, 0xf, 0xb1, 0xa4, 0x98, 0xff, 0xff, 0xff, 0x7f}}, - {name: "lock cmpxchgq %r10, (%r8)", n: &nodeImpl{instruction: CMPXCHGQ, flag: nodeFlagLock, srcReg: RegX10, dstConst: 0x0, dstReg: RegR8}, exp: []byte{0xf0, 0x4d, 0xf, 0xb1, 0x10}}, - {name: "lock cmpxchgq %r10, (%r8, %r11, 4)", n: &nodeImpl{instruction: CMPXCHGQ, flag: nodeFlagLock, srcReg: RegX10, dstConst: 0x0, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0xf0, 0x4f, 0xf, 0xb1, 0x14, 0x98}}, - {name: "lock cmpxchgq %r10, 1(%r8)", n: &nodeImpl{instruction: CMPXCHGQ, flag: nodeFlagLock, srcReg: RegX10, dstConst: 0x1, dstReg: RegR8}, exp: []byte{0xf0, 0x4d, 0xf, 0xb1, 0x50, 0x1}}, - {name: "lock cmpxchgq %r10, 1(%r8, %r11, 4)", n: &nodeImpl{instruction: CMPXCHGQ, flag: nodeFlagLock, srcReg: RegX10, dstConst: 0x1, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0xf0, 0x4f, 0xf, 0xb1, 0x54, 0x98, 0x1}}, - {name: "lock cmpxchgq %r10, 0x7fffffff(%r8)", n: &nodeImpl{instruction: CMPXCHGQ, flag: nodeFlagLock, srcReg: RegX10, dstConst: 0x7fffffff, dstReg: RegR8}, exp: []byte{0xf0, 0x4d, 0xf, 0xb1, 0x90, 0xff, 0xff, 0xff, 0x7f}}, - {name: "lock cmpxchgq %r10, 0x7fffffff(%r8, %r11, 4)", n: &nodeImpl{instruction: CMPXCHGQ, flag: nodeFlagLock, srcReg: RegX10, dstConst: 0x7fffffff, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0xf0, 0x4f, 0xf, 0xb1, 0x94, 0x98, 0xff, 0xff, 0xff, 0x7f}}, - {name: "lock cmpxchgw %r12w, (%r8)", n: &nodeImpl{instruction: CMPXCHGW, flag: nodeFlagLock, srcReg: RegR12, dstConst: 0x0, dstReg: RegR8}, exp: []byte{0x66, 0xf0, 0x45, 0xf, 0xb1, 0x20}}, - {name: "lock cmpxchgw %r12w, (%r8, %r11, 4)", n: &nodeImpl{instruction: CMPXCHGW, flag: nodeFlagLock, srcReg: RegR12, dstConst: 0x0, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x66, 0xf0, 0x47, 0xf, 0xb1, 0x24, 0x98}}, - {name: "lock cmpxchgw %r12w, 1(%r8)", n: &nodeImpl{instruction: CMPXCHGW, flag: nodeFlagLock, srcReg: RegR12, dstConst: 0x1, dstReg: RegR8}, exp: []byte{0x66, 0xf0, 0x45, 0xf, 0xb1, 0x60, 0x1}}, - {name: "lock cmpxchgw %r12w, 1(%r8, %r11, 4)", n: &nodeImpl{instruction: CMPXCHGW, flag: nodeFlagLock, srcReg: RegR12, dstConst: 0x1, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x66, 0xf0, 0x47, 0xf, 0xb1, 0x64, 0x98, 0x1}}, - {name: "lock cmpxchgw %r12w, 0x7fffffff(%r8)", n: &nodeImpl{instruction: CMPXCHGW, flag: nodeFlagLock, srcReg: RegR12, dstConst: 0x7fffffff, dstReg: RegR8}, exp: []byte{0x66, 0xf0, 0x45, 0xf, 0xb1, 0xa0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "lock cmpxchgw %r12w, 0x7fffffff(%r8, %r11, 4)", n: &nodeImpl{instruction: CMPXCHGW, flag: nodeFlagLock, srcReg: RegR12, dstConst: 0x7fffffff, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x66, 0xf0, 0x47, 0xf, 0xb1, 0xa4, 0x98, 0xff, 0xff, 0xff, 0x7f}}, - {name: "lock cmpxchgw %si, (%r8)", n: &nodeImpl{instruction: CMPXCHGW, flag: nodeFlagLock, srcReg: RegSI, dstConst: 0x0, dstReg: RegR8}, exp: []byte{0x66, 0xf0, 0x41, 0xf, 0xb1, 0x30}}, - {name: "lock cmpxchgw %si, (%r8, %r11, 4)", n: &nodeImpl{instruction: CMPXCHGW, flag: nodeFlagLock, srcReg: RegSI, dstConst: 0x0, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x66, 0xf0, 0x43, 0xf, 0xb1, 0x34, 0x98}}, - {name: "lock cmpxchgw %si, 1(%r8)", n: &nodeImpl{instruction: CMPXCHGW, flag: nodeFlagLock, srcReg: RegSI, dstConst: 0x1, dstReg: RegR8}, exp: []byte{0x66, 0xf0, 0x41, 0xf, 0xb1, 0x70, 0x1}}, - {name: "lock cmpxchgw %si, 1(%r8, %r11, 4)", n: &nodeImpl{instruction: CMPXCHGW, flag: nodeFlagLock, srcReg: RegSI, dstConst: 0x1, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x66, 0xf0, 0x43, 0xf, 0xb1, 0x74, 0x98, 0x1}}, - {name: "lock cmpxchgw %si, 0x7fffffff(%r8)", n: &nodeImpl{instruction: CMPXCHGW, flag: nodeFlagLock, srcReg: RegSI, dstConst: 0x7fffffff, dstReg: RegR8}, exp: []byte{0x66, 0xf0, 0x41, 0xf, 0xb1, 0xb0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "lock cmpxchgw %si, 0x7fffffff(%r8, %r11, 4)", n: &nodeImpl{instruction: CMPXCHGW, flag: nodeFlagLock, srcReg: RegSI, dstConst: 0x7fffffff, dstMemIndex: RegR11, dstMemScale: 4, dstReg: RegR8}, exp: []byte{0x66, 0xf0, 0x43, 0xf, 0xb1, 0xb4, 0x98, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVDQU", n: &nodeImpl{instruction: MOVDQU, srcReg: RegX3, dstReg: RegAX, srcConst: 10}, exp: []byte{0xf3, 0xf, 0x7f, 0x18}}, - {name: "MOVDQU", n: &nodeImpl{instruction: MOVDQU, srcReg: RegX3, dstReg: RegR13, srcConst: 10}, exp: []byte{0xf3, 0x41, 0xf, 0x7f, 0x5d, 0x0}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=R12/scale=1/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 1, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x14, 0x4, 0x21, 0x0}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=R12/scale=1/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 1, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x14, 0x4, 0x21, 0x1}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=R12/scale=1/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 1, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x14, 0x44, 0x21, 0x1, 0x0}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=R12/scale=1/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 1, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x14, 0x44, 0x21, 0x1, 0x1}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=R12/scale=1/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 1, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x14, 0x84, 0x21, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=R12/scale=1/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 1, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x14, 0x84, 0x21, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=AX/scale=1/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 1, dstConst: 0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x4, 0x1, 0x0}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=AX/scale=1/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 1, dstConst: 0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x4, 0x1, 0x1}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=AX/scale=1/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 1, dstConst: 1, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x44, 0x1, 0x1, 0x0}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=AX/scale=1/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 1, dstConst: 1, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x44, 0x1, 0x1, 0x1}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=AX/scale=1/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 1, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x84, 0x1, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=AX/scale=1/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 1, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x84, 0x1, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=BP/scale=1/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 1, dstConst: 0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x4, 0x29, 0x0}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=BP/scale=1/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 1, dstConst: 0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x4, 0x29, 0x1}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=BP/scale=1/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 1, dstConst: 1, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x44, 0x29, 0x1, 0x0}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=BP/scale=1/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 1, dstConst: 1, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x44, 0x29, 0x1, 0x1}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=BP/scale=1/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 1, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x84, 0x29, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=BP/scale=1/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 1, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x84, 0x29, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=SI/scale=1/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 1, dstConst: 0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x4, 0x31, 0x0}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=SI/scale=1/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 1, dstConst: 0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x4, 0x31, 0x1}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=SI/scale=1/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 1, dstConst: 1, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x44, 0x31, 0x1, 0x0}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=SI/scale=1/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 1, dstConst: 1, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x44, 0x31, 0x1, 0x1}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=SI/scale=1/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 1, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x84, 0x31, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=SI/scale=1/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 1, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x84, 0x31, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=R12/scale=2/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 2, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x14, 0x4, 0x61, 0x0}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=R12/scale=2/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 2, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x14, 0x4, 0x61, 0x1}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=R12/scale=2/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 2, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x14, 0x44, 0x61, 0x1, 0x0}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=R12/scale=2/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 2, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x14, 0x44, 0x61, 0x1, 0x1}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=R12/scale=2/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 2, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x14, 0x84, 0x61, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=R12/scale=2/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 2, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x14, 0x84, 0x61, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=AX/scale=2/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 2, dstConst: 0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x4, 0x41, 0x0}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=AX/scale=2/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 2, dstConst: 0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x4, 0x41, 0x1}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=AX/scale=2/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 2, dstConst: 1, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x44, 0x41, 0x1, 0x0}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=AX/scale=2/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 2, dstConst: 1, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x44, 0x41, 0x1, 0x1}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=AX/scale=2/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 2, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x84, 0x41, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=AX/scale=2/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 2, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x84, 0x41, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=BP/scale=2/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 2, dstConst: 0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x4, 0x69, 0x0}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=BP/scale=2/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 2, dstConst: 0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x4, 0x69, 0x1}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=BP/scale=2/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 2, dstConst: 1, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x44, 0x69, 0x1, 0x0}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=BP/scale=2/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 2, dstConst: 1, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x44, 0x69, 0x1, 0x1}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=BP/scale=2/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 2, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x84, 0x69, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=BP/scale=2/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 2, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x84, 0x69, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=SI/scale=2/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 2, dstConst: 0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x4, 0x71, 0x0}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=SI/scale=2/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 2, dstConst: 0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x4, 0x71, 0x1}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=SI/scale=2/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 2, dstConst: 1, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x44, 0x71, 0x1, 0x0}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=SI/scale=2/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 2, dstConst: 1, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x44, 0x71, 0x1, 0x1}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=SI/scale=2/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 2, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x84, 0x71, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=SI/scale=2/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 2, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x84, 0x71, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=R12/scale=4/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 4, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x14, 0x4, 0xa1, 0x0}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=R12/scale=4/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 4, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x14, 0x4, 0xa1, 0x1}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=R12/scale=4/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 4, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x14, 0x44, 0xa1, 0x1, 0x0}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=R12/scale=4/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 4, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x14, 0x44, 0xa1, 0x1, 0x1}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=R12/scale=4/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 4, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x14, 0x84, 0xa1, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=R12/scale=4/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 4, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x14, 0x84, 0xa1, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=AX/scale=4/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 4, dstConst: 0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x4, 0x81, 0x0}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=AX/scale=4/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 4, dstConst: 0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x4, 0x81, 0x1}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=AX/scale=4/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 4, dstConst: 1, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x44, 0x81, 0x1, 0x0}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=AX/scale=4/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 4, dstConst: 1, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x44, 0x81, 0x1, 0x1}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=AX/scale=4/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 4, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x84, 0x81, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=AX/scale=4/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 4, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x84, 0x81, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=BP/scale=4/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 4, dstConst: 0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x4, 0xa9, 0x0}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=BP/scale=4/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 4, dstConst: 0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x4, 0xa9, 0x1}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=BP/scale=4/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 4, dstConst: 1, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x44, 0xa9, 0x1, 0x0}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=BP/scale=4/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 4, dstConst: 1, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x44, 0xa9, 0x1, 0x1}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=BP/scale=4/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 4, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x84, 0xa9, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=BP/scale=4/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 4, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x84, 0xa9, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=SI/scale=4/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 4, dstConst: 0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x4, 0xb1, 0x0}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=SI/scale=4/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 4, dstConst: 0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x4, 0xb1, 0x1}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=SI/scale=4/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 4, dstConst: 1, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x44, 0xb1, 0x1, 0x0}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=SI/scale=4/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 4, dstConst: 1, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x44, 0xb1, 0x1, 0x1}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=SI/scale=4/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 4, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x84, 0xb1, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=SI/scale=4/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 4, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x84, 0xb1, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=R12/scale=8/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 8, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x14, 0x4, 0xe1, 0x0}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=R12/scale=8/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 8, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x14, 0x4, 0xe1, 0x1}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=R12/scale=8/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 8, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x14, 0x44, 0xe1, 0x1, 0x0}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=R12/scale=8/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 8, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x14, 0x44, 0xe1, 0x1, 0x1}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=R12/scale=8/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 8, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x14, 0x84, 0xe1, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=R12/scale=8/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 8, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x14, 0x84, 0xe1, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=AX/scale=8/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 8, dstConst: 0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x4, 0xc1, 0x0}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=AX/scale=8/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 8, dstConst: 0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x4, 0xc1, 0x1}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=AX/scale=8/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 8, dstConst: 1, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x44, 0xc1, 0x1, 0x0}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=AX/scale=8/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 8, dstConst: 1, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x44, 0xc1, 0x1, 0x1}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=AX/scale=8/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 8, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x84, 0xc1, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=AX/scale=8/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 8, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x84, 0xc1, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=BP/scale=8/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 8, dstConst: 0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x4, 0xe9, 0x0}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=BP/scale=8/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 8, dstConst: 0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x4, 0xe9, 0x1}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=BP/scale=8/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 8, dstConst: 1, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x44, 0xe9, 0x1, 0x0}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=BP/scale=8/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 8, dstConst: 1, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x44, 0xe9, 0x1, 0x1}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=BP/scale=8/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 8, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x84, 0xe9, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=BP/scale=8/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 8, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x84, 0xe9, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=SI/scale=8/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 8, dstConst: 0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x4, 0xf1, 0x0}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=SI/scale=8/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 8, dstConst: 0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x4, 0xf1, 0x1}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=SI/scale=8/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 8, dstConst: 1, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x44, 0xf1, 0x1, 0x0}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=SI/scale=8/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 8, dstConst: 1, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x44, 0xf1, 0x1, 0x1}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=SI/scale=8/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 8, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x84, 0xf1, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRB/src=X0/dstBase=CX/index=SI/scale=8/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 8, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0x84, 0xf1, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=R12/scale=1/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 1, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x14, 0x2c, 0x21, 0x0}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=R12/scale=1/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 1, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x14, 0x2c, 0x21, 0x1}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=R12/scale=1/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 1, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x14, 0x6c, 0x21, 0x1, 0x0}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=R12/scale=1/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 1, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x14, 0x6c, 0x21, 0x1, 0x1}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=R12/scale=1/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 1, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x14, 0xac, 0x21, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=R12/scale=1/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 1, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x14, 0xac, 0x21, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=AX/scale=1/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 1, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0x2c, 0x1, 0x0}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=AX/scale=1/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 1, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0x2c, 0x1, 0x1}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=AX/scale=1/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 1, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0x6c, 0x1, 0x1, 0x0}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=AX/scale=1/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 1, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0x6c, 0x1, 0x1, 0x1}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=AX/scale=1/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 1, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0xac, 0x1, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=AX/scale=1/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 1, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0xac, 0x1, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=BP/scale=1/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 1, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0x2c, 0x29, 0x0}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=BP/scale=1/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 1, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0x2c, 0x29, 0x1}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=BP/scale=1/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 1, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0x6c, 0x29, 0x1, 0x0}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=BP/scale=1/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 1, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0x6c, 0x29, 0x1, 0x1}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=BP/scale=1/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 1, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0xac, 0x29, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=BP/scale=1/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 1, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0xac, 0x29, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=SI/scale=1/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 1, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0x2c, 0x31, 0x0}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=SI/scale=1/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 1, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0x2c, 0x31, 0x1}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=SI/scale=1/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 1, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0x6c, 0x31, 0x1, 0x0}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=SI/scale=1/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 1, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0x6c, 0x31, 0x1, 0x1}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=SI/scale=1/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 1, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0xac, 0x31, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=SI/scale=1/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 1, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0xac, 0x31, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=R12/scale=2/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 2, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x14, 0x2c, 0x61, 0x0}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=R12/scale=2/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 2, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x14, 0x2c, 0x61, 0x1}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=R12/scale=2/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 2, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x14, 0x6c, 0x61, 0x1, 0x0}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=R12/scale=2/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 2, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x14, 0x6c, 0x61, 0x1, 0x1}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=R12/scale=2/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 2, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x14, 0xac, 0x61, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=R12/scale=2/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 2, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x14, 0xac, 0x61, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=AX/scale=2/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 2, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0x2c, 0x41, 0x0}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=AX/scale=2/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 2, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0x2c, 0x41, 0x1}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=AX/scale=2/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 2, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0x6c, 0x41, 0x1, 0x0}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=AX/scale=2/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 2, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0x6c, 0x41, 0x1, 0x1}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=AX/scale=2/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 2, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0xac, 0x41, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=AX/scale=2/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 2, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0xac, 0x41, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=BP/scale=2/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 2, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0x2c, 0x69, 0x0}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=BP/scale=2/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 2, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0x2c, 0x69, 0x1}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=BP/scale=2/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 2, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0x6c, 0x69, 0x1, 0x0}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=BP/scale=2/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 2, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0x6c, 0x69, 0x1, 0x1}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=BP/scale=2/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 2, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0xac, 0x69, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=BP/scale=2/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 2, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0xac, 0x69, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=SI/scale=2/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 2, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0x2c, 0x71, 0x0}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=SI/scale=2/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 2, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0x2c, 0x71, 0x1}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=SI/scale=2/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 2, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0x6c, 0x71, 0x1, 0x0}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=SI/scale=2/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 2, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0x6c, 0x71, 0x1, 0x1}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=SI/scale=2/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 2, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0xac, 0x71, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=SI/scale=2/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 2, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0xac, 0x71, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=R12/scale=4/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 4, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x14, 0x2c, 0xa1, 0x0}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=R12/scale=4/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 4, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x14, 0x2c, 0xa1, 0x1}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=R12/scale=4/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 4, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x14, 0x6c, 0xa1, 0x1, 0x0}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=R12/scale=4/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 4, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x14, 0x6c, 0xa1, 0x1, 0x1}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=R12/scale=4/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 4, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x14, 0xac, 0xa1, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=R12/scale=4/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 4, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x14, 0xac, 0xa1, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=AX/scale=4/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 4, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0x2c, 0x81, 0x0}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=AX/scale=4/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 4, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0x2c, 0x81, 0x1}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=AX/scale=4/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 4, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0x6c, 0x81, 0x1, 0x0}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=AX/scale=4/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 4, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0x6c, 0x81, 0x1, 0x1}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=AX/scale=4/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 4, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0xac, 0x81, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=AX/scale=4/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 4, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0xac, 0x81, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=BP/scale=4/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 4, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0x2c, 0xa9, 0x0}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=BP/scale=4/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 4, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0x2c, 0xa9, 0x1}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=BP/scale=4/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 4, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0x6c, 0xa9, 0x1, 0x0}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=BP/scale=4/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 4, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0x6c, 0xa9, 0x1, 0x1}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=BP/scale=4/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 4, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0xac, 0xa9, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=BP/scale=4/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 4, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0xac, 0xa9, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=SI/scale=4/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 4, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0x2c, 0xb1, 0x0}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=SI/scale=4/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 4, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0x2c, 0xb1, 0x1}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=SI/scale=4/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 4, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0x6c, 0xb1, 0x1, 0x0}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=SI/scale=4/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 4, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0x6c, 0xb1, 0x1, 0x1}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=SI/scale=4/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 4, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0xac, 0xb1, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=SI/scale=4/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 4, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0xac, 0xb1, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=R12/scale=8/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 8, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x14, 0x2c, 0xe1, 0x0}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=R12/scale=8/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 8, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x14, 0x2c, 0xe1, 0x1}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=R12/scale=8/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 8, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x14, 0x6c, 0xe1, 0x1, 0x0}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=R12/scale=8/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 8, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x14, 0x6c, 0xe1, 0x1, 0x1}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=R12/scale=8/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 8, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x14, 0xac, 0xe1, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=R12/scale=8/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 8, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x14, 0xac, 0xe1, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=AX/scale=8/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 8, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0x2c, 0xc1, 0x0}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=AX/scale=8/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 8, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0x2c, 0xc1, 0x1}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=AX/scale=8/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 8, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0x6c, 0xc1, 0x1, 0x0}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=AX/scale=8/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 8, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0x6c, 0xc1, 0x1, 0x1}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=AX/scale=8/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 8, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0xac, 0xc1, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=AX/scale=8/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 8, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0xac, 0xc1, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=BP/scale=8/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 8, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0x2c, 0xe9, 0x0}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=BP/scale=8/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 8, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0x2c, 0xe9, 0x1}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=BP/scale=8/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 8, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0x6c, 0xe9, 0x1, 0x0}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=BP/scale=8/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 8, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0x6c, 0xe9, 0x1, 0x1}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=BP/scale=8/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 8, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0xac, 0xe9, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=BP/scale=8/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 8, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0xac, 0xe9, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=SI/scale=8/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 8, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0x2c, 0xf1, 0x0}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=SI/scale=8/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 8, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0x2c, 0xf1, 0x1}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=SI/scale=8/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 8, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0x6c, 0xf1, 0x1, 0x0}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=SI/scale=8/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 8, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0x6c, 0xf1, 0x1, 0x1}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=SI/scale=8/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 8, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0xac, 0xf1, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRB/src=X13/dstBase=CX/index=SI/scale=8/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 8, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0xac, 0xf1, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=R12/scale=1/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 1, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x15, 0x4, 0x21, 0x0}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=R12/scale=1/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 1, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x15, 0x4, 0x21, 0x1}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=R12/scale=1/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 1, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x15, 0x44, 0x21, 0x1, 0x0}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=R12/scale=1/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 1, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x15, 0x44, 0x21, 0x1, 0x1}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=R12/scale=1/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 1, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x15, 0x84, 0x21, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=R12/scale=1/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 1, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x15, 0x84, 0x21, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=AX/scale=1/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 1, dstConst: 0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x4, 0x1, 0x0}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=AX/scale=1/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 1, dstConst: 0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x4, 0x1, 0x1}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=AX/scale=1/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 1, dstConst: 1, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x44, 0x1, 0x1, 0x0}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=AX/scale=1/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 1, dstConst: 1, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x44, 0x1, 0x1, 0x1}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=AX/scale=1/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 1, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x84, 0x1, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=AX/scale=1/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 1, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x84, 0x1, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=BP/scale=1/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 1, dstConst: 0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x4, 0x29, 0x0}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=BP/scale=1/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 1, dstConst: 0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x4, 0x29, 0x1}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=BP/scale=1/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 1, dstConst: 1, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x44, 0x29, 0x1, 0x0}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=BP/scale=1/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 1, dstConst: 1, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x44, 0x29, 0x1, 0x1}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=BP/scale=1/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 1, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x84, 0x29, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=BP/scale=1/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 1, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x84, 0x29, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=SI/scale=1/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 1, dstConst: 0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x4, 0x31, 0x0}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=SI/scale=1/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 1, dstConst: 0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x4, 0x31, 0x1}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=SI/scale=1/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 1, dstConst: 1, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x44, 0x31, 0x1, 0x0}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=SI/scale=1/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 1, dstConst: 1, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x44, 0x31, 0x1, 0x1}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=SI/scale=1/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 1, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x84, 0x31, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=SI/scale=1/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 1, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x84, 0x31, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=R12/scale=2/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 2, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x15, 0x4, 0x61, 0x0}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=R12/scale=2/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 2, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x15, 0x4, 0x61, 0x1}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=R12/scale=2/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 2, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x15, 0x44, 0x61, 0x1, 0x0}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=R12/scale=2/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 2, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x15, 0x44, 0x61, 0x1, 0x1}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=R12/scale=2/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 2, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x15, 0x84, 0x61, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=R12/scale=2/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 2, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x15, 0x84, 0x61, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=AX/scale=2/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 2, dstConst: 0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x4, 0x41, 0x0}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=AX/scale=2/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 2, dstConst: 0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x4, 0x41, 0x1}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=AX/scale=2/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 2, dstConst: 1, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x44, 0x41, 0x1, 0x0}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=AX/scale=2/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 2, dstConst: 1, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x44, 0x41, 0x1, 0x1}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=AX/scale=2/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 2, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x84, 0x41, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=AX/scale=2/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 2, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x84, 0x41, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=BP/scale=2/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 2, dstConst: 0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x4, 0x69, 0x0}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=BP/scale=2/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 2, dstConst: 0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x4, 0x69, 0x1}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=BP/scale=2/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 2, dstConst: 1, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x44, 0x69, 0x1, 0x0}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=BP/scale=2/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 2, dstConst: 1, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x44, 0x69, 0x1, 0x1}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=BP/scale=2/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 2, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x84, 0x69, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=BP/scale=2/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 2, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x84, 0x69, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=SI/scale=2/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 2, dstConst: 0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x4, 0x71, 0x0}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=SI/scale=2/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 2, dstConst: 0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x4, 0x71, 0x1}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=SI/scale=2/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 2, dstConst: 1, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x44, 0x71, 0x1, 0x0}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=SI/scale=2/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 2, dstConst: 1, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x44, 0x71, 0x1, 0x1}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=SI/scale=2/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 2, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x84, 0x71, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=SI/scale=2/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 2, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x84, 0x71, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=R12/scale=4/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 4, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x15, 0x4, 0xa1, 0x0}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=R12/scale=4/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 4, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x15, 0x4, 0xa1, 0x1}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=R12/scale=4/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 4, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x15, 0x44, 0xa1, 0x1, 0x0}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=R12/scale=4/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 4, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x15, 0x44, 0xa1, 0x1, 0x1}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=R12/scale=4/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 4, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x15, 0x84, 0xa1, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=R12/scale=4/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 4, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x15, 0x84, 0xa1, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=AX/scale=4/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 4, dstConst: 0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x4, 0x81, 0x0}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=AX/scale=4/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 4, dstConst: 0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x4, 0x81, 0x1}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=AX/scale=4/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 4, dstConst: 1, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x44, 0x81, 0x1, 0x0}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=AX/scale=4/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 4, dstConst: 1, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x44, 0x81, 0x1, 0x1}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=AX/scale=4/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 4, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x84, 0x81, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=AX/scale=4/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 4, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x84, 0x81, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=BP/scale=4/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 4, dstConst: 0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x4, 0xa9, 0x0}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=BP/scale=4/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 4, dstConst: 0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x4, 0xa9, 0x1}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=BP/scale=4/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 4, dstConst: 1, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x44, 0xa9, 0x1, 0x0}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=BP/scale=4/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 4, dstConst: 1, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x44, 0xa9, 0x1, 0x1}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=BP/scale=4/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 4, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x84, 0xa9, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=BP/scale=4/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 4, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x84, 0xa9, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=SI/scale=4/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 4, dstConst: 0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x4, 0xb1, 0x0}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=SI/scale=4/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 4, dstConst: 0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x4, 0xb1, 0x1}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=SI/scale=4/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 4, dstConst: 1, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x44, 0xb1, 0x1, 0x0}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=SI/scale=4/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 4, dstConst: 1, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x44, 0xb1, 0x1, 0x1}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=SI/scale=4/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 4, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x84, 0xb1, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=SI/scale=4/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 4, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x84, 0xb1, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=R12/scale=8/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 8, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x15, 0x4, 0xe1, 0x0}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=R12/scale=8/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 8, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x15, 0x4, 0xe1, 0x1}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=R12/scale=8/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 8, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x15, 0x44, 0xe1, 0x1, 0x0}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=R12/scale=8/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 8, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x15, 0x44, 0xe1, 0x1, 0x1}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=R12/scale=8/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 8, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x15, 0x84, 0xe1, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=R12/scale=8/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 8, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x15, 0x84, 0xe1, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=AX/scale=8/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 8, dstConst: 0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x4, 0xc1, 0x0}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=AX/scale=8/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 8, dstConst: 0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x4, 0xc1, 0x1}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=AX/scale=8/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 8, dstConst: 1, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x44, 0xc1, 0x1, 0x0}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=AX/scale=8/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 8, dstConst: 1, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x44, 0xc1, 0x1, 0x1}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=AX/scale=8/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 8, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x84, 0xc1, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=AX/scale=8/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 8, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x84, 0xc1, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=BP/scale=8/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 8, dstConst: 0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x4, 0xe9, 0x0}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=BP/scale=8/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 8, dstConst: 0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x4, 0xe9, 0x1}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=BP/scale=8/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 8, dstConst: 1, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x44, 0xe9, 0x1, 0x0}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=BP/scale=8/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 8, dstConst: 1, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x44, 0xe9, 0x1, 0x1}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=BP/scale=8/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 8, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x84, 0xe9, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=BP/scale=8/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 8, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x84, 0xe9, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=SI/scale=8/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 8, dstConst: 0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x4, 0xf1, 0x0}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=SI/scale=8/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 8, dstConst: 0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x4, 0xf1, 0x1}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=SI/scale=8/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 8, dstConst: 1, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x44, 0xf1, 0x1, 0x0}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=SI/scale=8/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 8, dstConst: 1, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x44, 0xf1, 0x1, 0x1}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=SI/scale=8/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 8, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x84, 0xf1, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRW/src=X0/dstBase=CX/index=SI/scale=8/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 8, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x15, 0x84, 0xf1, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=R12/scale=1/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 1, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x15, 0x2c, 0x21, 0x0}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=R12/scale=1/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 1, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x15, 0x2c, 0x21, 0x1}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=R12/scale=1/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 1, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x15, 0x6c, 0x21, 0x1, 0x0}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=R12/scale=1/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 1, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x15, 0x6c, 0x21, 0x1, 0x1}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=R12/scale=1/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 1, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x15, 0xac, 0x21, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=R12/scale=1/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 1, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x15, 0xac, 0x21, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=AX/scale=1/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 1, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0x2c, 0x1, 0x0}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=AX/scale=1/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 1, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0x2c, 0x1, 0x1}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=AX/scale=1/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 1, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0x6c, 0x1, 0x1, 0x0}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=AX/scale=1/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 1, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0x6c, 0x1, 0x1, 0x1}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=AX/scale=1/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 1, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0xac, 0x1, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=AX/scale=1/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 1, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0xac, 0x1, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=BP/scale=1/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 1, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0x2c, 0x29, 0x0}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=BP/scale=1/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 1, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0x2c, 0x29, 0x1}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=BP/scale=1/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 1, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0x6c, 0x29, 0x1, 0x0}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=BP/scale=1/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 1, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0x6c, 0x29, 0x1, 0x1}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=BP/scale=1/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 1, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0xac, 0x29, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=BP/scale=1/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 1, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0xac, 0x29, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=SI/scale=1/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 1, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0x2c, 0x31, 0x0}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=SI/scale=1/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 1, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0x2c, 0x31, 0x1}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=SI/scale=1/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 1, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0x6c, 0x31, 0x1, 0x0}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=SI/scale=1/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 1, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0x6c, 0x31, 0x1, 0x1}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=SI/scale=1/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 1, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0xac, 0x31, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=SI/scale=1/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 1, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0xac, 0x31, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=R12/scale=2/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 2, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x15, 0x2c, 0x61, 0x0}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=R12/scale=2/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 2, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x15, 0x2c, 0x61, 0x1}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=R12/scale=2/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 2, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x15, 0x6c, 0x61, 0x1, 0x0}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=R12/scale=2/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 2, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x15, 0x6c, 0x61, 0x1, 0x1}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=R12/scale=2/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 2, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x15, 0xac, 0x61, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=R12/scale=2/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 2, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x15, 0xac, 0x61, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=AX/scale=2/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 2, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0x2c, 0x41, 0x0}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=AX/scale=2/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 2, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0x2c, 0x41, 0x1}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=AX/scale=2/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 2, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0x6c, 0x41, 0x1, 0x0}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=AX/scale=2/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 2, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0x6c, 0x41, 0x1, 0x1}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=AX/scale=2/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 2, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0xac, 0x41, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=AX/scale=2/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 2, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0xac, 0x41, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=BP/scale=2/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 2, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0x2c, 0x69, 0x0}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=BP/scale=2/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 2, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0x2c, 0x69, 0x1}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=BP/scale=2/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 2, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0x6c, 0x69, 0x1, 0x0}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=BP/scale=2/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 2, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0x6c, 0x69, 0x1, 0x1}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=BP/scale=2/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 2, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0xac, 0x69, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=BP/scale=2/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 2, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0xac, 0x69, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=SI/scale=2/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 2, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0x2c, 0x71, 0x0}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=SI/scale=2/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 2, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0x2c, 0x71, 0x1}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=SI/scale=2/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 2, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0x6c, 0x71, 0x1, 0x0}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=SI/scale=2/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 2, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0x6c, 0x71, 0x1, 0x1}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=SI/scale=2/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 2, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0xac, 0x71, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=SI/scale=2/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 2, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0xac, 0x71, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=R12/scale=4/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 4, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x15, 0x2c, 0xa1, 0x0}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=R12/scale=4/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 4, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x15, 0x2c, 0xa1, 0x1}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=R12/scale=4/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 4, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x15, 0x6c, 0xa1, 0x1, 0x0}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=R12/scale=4/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 4, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x15, 0x6c, 0xa1, 0x1, 0x1}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=R12/scale=4/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 4, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x15, 0xac, 0xa1, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=R12/scale=4/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 4, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x15, 0xac, 0xa1, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=AX/scale=4/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 4, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0x2c, 0x81, 0x0}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=AX/scale=4/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 4, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0x2c, 0x81, 0x1}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=AX/scale=4/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 4, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0x6c, 0x81, 0x1, 0x0}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=AX/scale=4/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 4, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0x6c, 0x81, 0x1, 0x1}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=AX/scale=4/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 4, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0xac, 0x81, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=AX/scale=4/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 4, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0xac, 0x81, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=BP/scale=4/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 4, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0x2c, 0xa9, 0x0}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=BP/scale=4/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 4, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0x2c, 0xa9, 0x1}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=BP/scale=4/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 4, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0x6c, 0xa9, 0x1, 0x0}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=BP/scale=4/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 4, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0x6c, 0xa9, 0x1, 0x1}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=BP/scale=4/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 4, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0xac, 0xa9, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=BP/scale=4/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 4, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0xac, 0xa9, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=SI/scale=4/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 4, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0x2c, 0xb1, 0x0}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=SI/scale=4/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 4, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0x2c, 0xb1, 0x1}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=SI/scale=4/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 4, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0x6c, 0xb1, 0x1, 0x0}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=SI/scale=4/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 4, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0x6c, 0xb1, 0x1, 0x1}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=SI/scale=4/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 4, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0xac, 0xb1, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=SI/scale=4/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 4, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0xac, 0xb1, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=R12/scale=8/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 8, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x15, 0x2c, 0xe1, 0x0}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=R12/scale=8/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 8, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x15, 0x2c, 0xe1, 0x1}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=R12/scale=8/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 8, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x15, 0x6c, 0xe1, 0x1, 0x0}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=R12/scale=8/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 8, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x15, 0x6c, 0xe1, 0x1, 0x1}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=R12/scale=8/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 8, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x15, 0xac, 0xe1, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=R12/scale=8/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 8, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x15, 0xac, 0xe1, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=AX/scale=8/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 8, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0x2c, 0xc1, 0x0}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=AX/scale=8/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 8, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0x2c, 0xc1, 0x1}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=AX/scale=8/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 8, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0x6c, 0xc1, 0x1, 0x0}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=AX/scale=8/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 8, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0x6c, 0xc1, 0x1, 0x1}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=AX/scale=8/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 8, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0xac, 0xc1, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=AX/scale=8/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 8, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0xac, 0xc1, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=BP/scale=8/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 8, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0x2c, 0xe9, 0x0}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=BP/scale=8/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 8, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0x2c, 0xe9, 0x1}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=BP/scale=8/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 8, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0x6c, 0xe9, 0x1, 0x0}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=BP/scale=8/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 8, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0x6c, 0xe9, 0x1, 0x1}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=BP/scale=8/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 8, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0xac, 0xe9, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=BP/scale=8/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 8, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0xac, 0xe9, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=SI/scale=8/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 8, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0x2c, 0xf1, 0x0}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=SI/scale=8/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 8, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0x2c, 0xf1, 0x1}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=SI/scale=8/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 8, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0x6c, 0xf1, 0x1, 0x0}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=SI/scale=8/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 8, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0x6c, 0xf1, 0x1, 0x1}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=SI/scale=8/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 8, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0xac, 0xf1, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRW/src=X13/dstBase=CX/index=SI/scale=8/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 8, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x15, 0xac, 0xf1, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=R12/scale=1/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 1, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x16, 0x4, 0x21, 0x0}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=R12/scale=1/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 1, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x16, 0x4, 0x21, 0x1}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=R12/scale=1/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 1, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x16, 0x44, 0x21, 0x1, 0x0}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=R12/scale=1/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 1, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x16, 0x44, 0x21, 0x1, 0x1}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=R12/scale=1/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 1, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x16, 0x84, 0x21, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=R12/scale=1/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 1, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x16, 0x84, 0x21, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=AX/scale=1/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 1, dstConst: 0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x4, 0x1, 0x0}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=AX/scale=1/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 1, dstConst: 0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x4, 0x1, 0x1}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=AX/scale=1/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 1, dstConst: 1, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x44, 0x1, 0x1, 0x0}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=AX/scale=1/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 1, dstConst: 1, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x44, 0x1, 0x1, 0x1}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=AX/scale=1/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 1, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x84, 0x1, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=AX/scale=1/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 1, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x84, 0x1, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=BP/scale=1/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 1, dstConst: 0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x4, 0x29, 0x0}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=BP/scale=1/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 1, dstConst: 0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x4, 0x29, 0x1}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=BP/scale=1/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 1, dstConst: 1, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x44, 0x29, 0x1, 0x0}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=BP/scale=1/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 1, dstConst: 1, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x44, 0x29, 0x1, 0x1}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=BP/scale=1/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 1, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x84, 0x29, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=BP/scale=1/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 1, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x84, 0x29, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=SI/scale=1/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 1, dstConst: 0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x4, 0x31, 0x0}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=SI/scale=1/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 1, dstConst: 0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x4, 0x31, 0x1}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=SI/scale=1/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 1, dstConst: 1, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x44, 0x31, 0x1, 0x0}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=SI/scale=1/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 1, dstConst: 1, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x44, 0x31, 0x1, 0x1}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=SI/scale=1/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 1, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x84, 0x31, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=SI/scale=1/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 1, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x84, 0x31, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=R12/scale=2/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 2, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x16, 0x4, 0x61, 0x0}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=R12/scale=2/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 2, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x16, 0x4, 0x61, 0x1}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=R12/scale=2/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 2, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x16, 0x44, 0x61, 0x1, 0x0}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=R12/scale=2/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 2, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x16, 0x44, 0x61, 0x1, 0x1}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=R12/scale=2/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 2, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x16, 0x84, 0x61, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=R12/scale=2/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 2, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x16, 0x84, 0x61, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=AX/scale=2/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 2, dstConst: 0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x4, 0x41, 0x0}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=AX/scale=2/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 2, dstConst: 0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x4, 0x41, 0x1}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=AX/scale=2/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 2, dstConst: 1, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x44, 0x41, 0x1, 0x0}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=AX/scale=2/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 2, dstConst: 1, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x44, 0x41, 0x1, 0x1}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=AX/scale=2/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 2, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x84, 0x41, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=AX/scale=2/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 2, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x84, 0x41, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=BP/scale=2/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 2, dstConst: 0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x4, 0x69, 0x0}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=BP/scale=2/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 2, dstConst: 0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x4, 0x69, 0x1}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=BP/scale=2/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 2, dstConst: 1, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x44, 0x69, 0x1, 0x0}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=BP/scale=2/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 2, dstConst: 1, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x44, 0x69, 0x1, 0x1}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=BP/scale=2/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 2, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x84, 0x69, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=BP/scale=2/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 2, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x84, 0x69, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=SI/scale=2/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 2, dstConst: 0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x4, 0x71, 0x0}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=SI/scale=2/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 2, dstConst: 0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x4, 0x71, 0x1}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=SI/scale=2/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 2, dstConst: 1, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x44, 0x71, 0x1, 0x0}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=SI/scale=2/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 2, dstConst: 1, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x44, 0x71, 0x1, 0x1}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=SI/scale=2/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 2, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x84, 0x71, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=SI/scale=2/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 2, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x84, 0x71, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=R12/scale=4/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 4, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x16, 0x4, 0xa1, 0x0}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=R12/scale=4/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 4, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x16, 0x4, 0xa1, 0x1}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=R12/scale=4/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 4, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x16, 0x44, 0xa1, 0x1, 0x0}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=R12/scale=4/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 4, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x16, 0x44, 0xa1, 0x1, 0x1}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=R12/scale=4/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 4, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x16, 0x84, 0xa1, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=R12/scale=4/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 4, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x16, 0x84, 0xa1, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=AX/scale=4/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 4, dstConst: 0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x4, 0x81, 0x0}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=AX/scale=4/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 4, dstConst: 0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x4, 0x81, 0x1}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=AX/scale=4/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 4, dstConst: 1, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x44, 0x81, 0x1, 0x0}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=AX/scale=4/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 4, dstConst: 1, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x44, 0x81, 0x1, 0x1}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=AX/scale=4/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 4, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x84, 0x81, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=AX/scale=4/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 4, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x84, 0x81, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=BP/scale=4/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 4, dstConst: 0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x4, 0xa9, 0x0}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=BP/scale=4/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 4, dstConst: 0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x4, 0xa9, 0x1}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=BP/scale=4/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 4, dstConst: 1, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x44, 0xa9, 0x1, 0x0}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=BP/scale=4/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 4, dstConst: 1, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x44, 0xa9, 0x1, 0x1}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=BP/scale=4/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 4, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x84, 0xa9, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=BP/scale=4/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 4, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x84, 0xa9, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=SI/scale=4/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 4, dstConst: 0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x4, 0xb1, 0x0}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=SI/scale=4/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 4, dstConst: 0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x4, 0xb1, 0x1}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=SI/scale=4/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 4, dstConst: 1, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x44, 0xb1, 0x1, 0x0}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=SI/scale=4/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 4, dstConst: 1, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x44, 0xb1, 0x1, 0x1}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=SI/scale=4/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 4, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x84, 0xb1, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=SI/scale=4/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 4, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x84, 0xb1, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=R12/scale=8/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 8, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x16, 0x4, 0xe1, 0x0}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=R12/scale=8/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 8, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x16, 0x4, 0xe1, 0x1}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=R12/scale=8/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 8, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x16, 0x44, 0xe1, 0x1, 0x0}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=R12/scale=8/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 8, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x16, 0x44, 0xe1, 0x1, 0x1}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=R12/scale=8/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 8, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x16, 0x84, 0xe1, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=R12/scale=8/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 8, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x16, 0x84, 0xe1, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=AX/scale=8/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 8, dstConst: 0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x4, 0xc1, 0x0}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=AX/scale=8/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 8, dstConst: 0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x4, 0xc1, 0x1}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=AX/scale=8/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 8, dstConst: 1, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x44, 0xc1, 0x1, 0x0}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=AX/scale=8/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 8, dstConst: 1, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x44, 0xc1, 0x1, 0x1}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=AX/scale=8/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 8, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x84, 0xc1, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=AX/scale=8/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 8, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x84, 0xc1, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=BP/scale=8/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 8, dstConst: 0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x4, 0xe9, 0x0}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=BP/scale=8/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 8, dstConst: 0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x4, 0xe9, 0x1}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=BP/scale=8/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 8, dstConst: 1, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x44, 0xe9, 0x1, 0x0}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=BP/scale=8/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 8, dstConst: 1, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x44, 0xe9, 0x1, 0x1}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=BP/scale=8/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 8, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x84, 0xe9, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=BP/scale=8/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 8, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x84, 0xe9, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=SI/scale=8/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 8, dstConst: 0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x4, 0xf1, 0x0}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=SI/scale=8/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 8, dstConst: 0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x4, 0xf1, 0x1}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=SI/scale=8/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 8, dstConst: 1, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x44, 0xf1, 0x1, 0x0}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=SI/scale=8/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 8, dstConst: 1, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x44, 0xf1, 0x1, 0x1}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=SI/scale=8/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 8, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x84, 0xf1, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRD/src=X0/dstBase=CX/index=SI/scale=8/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 8, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0x84, 0xf1, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=R12/scale=1/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 1, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x16, 0x2c, 0x21, 0x0}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=R12/scale=1/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 1, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x16, 0x2c, 0x21, 0x1}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=R12/scale=1/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 1, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x16, 0x6c, 0x21, 0x1, 0x0}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=R12/scale=1/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 1, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x16, 0x6c, 0x21, 0x1, 0x1}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=R12/scale=1/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 1, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x16, 0xac, 0x21, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=R12/scale=1/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 1, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x16, 0xac, 0x21, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=AX/scale=1/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 1, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0x2c, 0x1, 0x0}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=AX/scale=1/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 1, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0x2c, 0x1, 0x1}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=AX/scale=1/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 1, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0x6c, 0x1, 0x1, 0x0}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=AX/scale=1/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 1, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0x6c, 0x1, 0x1, 0x1}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=AX/scale=1/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 1, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0xac, 0x1, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=AX/scale=1/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 1, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0xac, 0x1, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=BP/scale=1/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 1, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0x2c, 0x29, 0x0}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=BP/scale=1/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 1, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0x2c, 0x29, 0x1}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=BP/scale=1/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 1, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0x6c, 0x29, 0x1, 0x0}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=BP/scale=1/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 1, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0x6c, 0x29, 0x1, 0x1}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=BP/scale=1/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 1, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0xac, 0x29, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=BP/scale=1/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 1, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0xac, 0x29, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=SI/scale=1/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 1, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0x2c, 0x31, 0x0}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=SI/scale=1/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 1, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0x2c, 0x31, 0x1}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=SI/scale=1/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 1, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0x6c, 0x31, 0x1, 0x0}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=SI/scale=1/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 1, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0x6c, 0x31, 0x1, 0x1}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=SI/scale=1/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 1, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0xac, 0x31, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=SI/scale=1/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 1, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0xac, 0x31, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=R12/scale=2/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 2, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x16, 0x2c, 0x61, 0x0}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=R12/scale=2/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 2, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x16, 0x2c, 0x61, 0x1}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=R12/scale=2/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 2, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x16, 0x6c, 0x61, 0x1, 0x0}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=R12/scale=2/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 2, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x16, 0x6c, 0x61, 0x1, 0x1}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=R12/scale=2/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 2, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x16, 0xac, 0x61, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=R12/scale=2/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 2, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x16, 0xac, 0x61, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=AX/scale=2/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 2, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0x2c, 0x41, 0x0}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=AX/scale=2/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 2, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0x2c, 0x41, 0x1}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=AX/scale=2/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 2, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0x6c, 0x41, 0x1, 0x0}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=AX/scale=2/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 2, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0x6c, 0x41, 0x1, 0x1}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=AX/scale=2/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 2, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0xac, 0x41, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=AX/scale=2/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 2, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0xac, 0x41, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=BP/scale=2/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 2, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0x2c, 0x69, 0x0}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=BP/scale=2/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 2, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0x2c, 0x69, 0x1}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=BP/scale=2/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 2, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0x6c, 0x69, 0x1, 0x0}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=BP/scale=2/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 2, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0x6c, 0x69, 0x1, 0x1}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=BP/scale=2/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 2, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0xac, 0x69, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=BP/scale=2/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 2, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0xac, 0x69, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=SI/scale=2/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 2, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0x2c, 0x71, 0x0}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=SI/scale=2/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 2, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0x2c, 0x71, 0x1}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=SI/scale=2/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 2, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0x6c, 0x71, 0x1, 0x0}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=SI/scale=2/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 2, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0x6c, 0x71, 0x1, 0x1}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=SI/scale=2/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 2, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0xac, 0x71, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=SI/scale=2/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 2, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0xac, 0x71, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=R12/scale=4/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 4, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x16, 0x2c, 0xa1, 0x0}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=R12/scale=4/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 4, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x16, 0x2c, 0xa1, 0x1}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=R12/scale=4/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 4, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x16, 0x6c, 0xa1, 0x1, 0x0}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=R12/scale=4/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 4, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x16, 0x6c, 0xa1, 0x1, 0x1}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=R12/scale=4/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 4, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x16, 0xac, 0xa1, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=R12/scale=4/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 4, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x16, 0xac, 0xa1, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=AX/scale=4/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 4, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0x2c, 0x81, 0x0}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=AX/scale=4/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 4, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0x2c, 0x81, 0x1}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=AX/scale=4/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 4, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0x6c, 0x81, 0x1, 0x0}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=AX/scale=4/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 4, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0x6c, 0x81, 0x1, 0x1}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=AX/scale=4/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 4, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0xac, 0x81, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=AX/scale=4/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 4, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0xac, 0x81, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=BP/scale=4/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 4, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0x2c, 0xa9, 0x0}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=BP/scale=4/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 4, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0x2c, 0xa9, 0x1}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=BP/scale=4/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 4, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0x6c, 0xa9, 0x1, 0x0}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=BP/scale=4/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 4, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0x6c, 0xa9, 0x1, 0x1}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=BP/scale=4/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 4, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0xac, 0xa9, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=BP/scale=4/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 4, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0xac, 0xa9, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=SI/scale=4/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 4, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0x2c, 0xb1, 0x0}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=SI/scale=4/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 4, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0x2c, 0xb1, 0x1}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=SI/scale=4/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 4, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0x6c, 0xb1, 0x1, 0x0}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=SI/scale=4/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 4, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0x6c, 0xb1, 0x1, 0x1}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=SI/scale=4/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 4, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0xac, 0xb1, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=SI/scale=4/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 4, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0xac, 0xb1, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=R12/scale=8/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 8, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x16, 0x2c, 0xe1, 0x0}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=R12/scale=8/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 8, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x16, 0x2c, 0xe1, 0x1}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=R12/scale=8/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 8, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x16, 0x6c, 0xe1, 0x1, 0x0}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=R12/scale=8/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 8, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x16, 0x6c, 0xe1, 0x1, 0x1}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=R12/scale=8/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 8, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x16, 0xac, 0xe1, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=R12/scale=8/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 8, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x16, 0xac, 0xe1, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=AX/scale=8/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 8, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0x2c, 0xc1, 0x0}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=AX/scale=8/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 8, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0x2c, 0xc1, 0x1}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=AX/scale=8/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 8, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0x6c, 0xc1, 0x1, 0x0}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=AX/scale=8/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 8, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0x6c, 0xc1, 0x1, 0x1}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=AX/scale=8/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 8, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0xac, 0xc1, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=AX/scale=8/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 8, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0xac, 0xc1, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=BP/scale=8/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 8, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0x2c, 0xe9, 0x0}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=BP/scale=8/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 8, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0x2c, 0xe9, 0x1}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=BP/scale=8/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 8, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0x6c, 0xe9, 0x1, 0x0}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=BP/scale=8/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 8, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0x6c, 0xe9, 0x1, 0x1}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=BP/scale=8/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 8, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0xac, 0xe9, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=BP/scale=8/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 8, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0xac, 0xe9, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=SI/scale=8/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 8, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0x2c, 0xf1, 0x0}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=SI/scale=8/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 8, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0x2c, 0xf1, 0x1}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=SI/scale=8/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 8, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0x6c, 0xf1, 0x1, 0x0}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=SI/scale=8/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 8, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0x6c, 0xf1, 0x1, 0x1}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=SI/scale=8/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 8, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0xac, 0xf1, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRD/src=X13/dstBase=CX/index=SI/scale=8/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 8, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0xac, 0xf1, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=R12/scale=1/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 1, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x16, 0x4, 0x21, 0x0}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=R12/scale=1/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 1, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x16, 0x4, 0x21, 0x1}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=R12/scale=1/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 1, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x16, 0x44, 0x21, 0x1, 0x0}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=R12/scale=1/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 1, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x16, 0x44, 0x21, 0x1, 0x1}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=R12/scale=1/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 1, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x16, 0x84, 0x21, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=R12/scale=1/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 1, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x16, 0x84, 0x21, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=AX/scale=1/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 1, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x4, 0x1, 0x0}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=AX/scale=1/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 1, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x4, 0x1, 0x1}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=AX/scale=1/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 1, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x44, 0x1, 0x1, 0x0}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=AX/scale=1/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 1, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x44, 0x1, 0x1, 0x1}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=AX/scale=1/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 1, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x84, 0x1, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=AX/scale=1/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 1, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x84, 0x1, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=BP/scale=1/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 1, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x4, 0x29, 0x0}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=BP/scale=1/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 1, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x4, 0x29, 0x1}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=BP/scale=1/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 1, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x44, 0x29, 0x1, 0x0}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=BP/scale=1/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 1, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x44, 0x29, 0x1, 0x1}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=BP/scale=1/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 1, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x84, 0x29, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=BP/scale=1/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 1, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x84, 0x29, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=SI/scale=1/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 1, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x4, 0x31, 0x0}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=SI/scale=1/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 1, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x4, 0x31, 0x1}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=SI/scale=1/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 1, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x44, 0x31, 0x1, 0x0}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=SI/scale=1/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 1, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x44, 0x31, 0x1, 0x1}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=SI/scale=1/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 1, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x84, 0x31, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=SI/scale=1/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 1, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x84, 0x31, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=R12/scale=2/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 2, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x16, 0x4, 0x61, 0x0}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=R12/scale=2/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 2, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x16, 0x4, 0x61, 0x1}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=R12/scale=2/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 2, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x16, 0x44, 0x61, 0x1, 0x0}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=R12/scale=2/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 2, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x16, 0x44, 0x61, 0x1, 0x1}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=R12/scale=2/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 2, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x16, 0x84, 0x61, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=R12/scale=2/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 2, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x16, 0x84, 0x61, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=AX/scale=2/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 2, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x4, 0x41, 0x0}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=AX/scale=2/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 2, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x4, 0x41, 0x1}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=AX/scale=2/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 2, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x44, 0x41, 0x1, 0x0}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=AX/scale=2/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 2, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x44, 0x41, 0x1, 0x1}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=AX/scale=2/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 2, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x84, 0x41, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=AX/scale=2/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 2, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x84, 0x41, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=BP/scale=2/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 2, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x4, 0x69, 0x0}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=BP/scale=2/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 2, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x4, 0x69, 0x1}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=BP/scale=2/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 2, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x44, 0x69, 0x1, 0x0}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=BP/scale=2/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 2, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x44, 0x69, 0x1, 0x1}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=BP/scale=2/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 2, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x84, 0x69, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=BP/scale=2/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 2, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x84, 0x69, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=SI/scale=2/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 2, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x4, 0x71, 0x0}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=SI/scale=2/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 2, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x4, 0x71, 0x1}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=SI/scale=2/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 2, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x44, 0x71, 0x1, 0x0}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=SI/scale=2/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 2, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x44, 0x71, 0x1, 0x1}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=SI/scale=2/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 2, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x84, 0x71, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=SI/scale=2/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 2, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x84, 0x71, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=R12/scale=4/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 4, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x16, 0x4, 0xa1, 0x0}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=R12/scale=4/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 4, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x16, 0x4, 0xa1, 0x1}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=R12/scale=4/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 4, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x16, 0x44, 0xa1, 0x1, 0x0}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=R12/scale=4/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 4, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x16, 0x44, 0xa1, 0x1, 0x1}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=R12/scale=4/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 4, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x16, 0x84, 0xa1, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=R12/scale=4/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 4, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x16, 0x84, 0xa1, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=AX/scale=4/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 4, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x4, 0x81, 0x0}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=AX/scale=4/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 4, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x4, 0x81, 0x1}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=AX/scale=4/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 4, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x44, 0x81, 0x1, 0x0}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=AX/scale=4/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 4, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x44, 0x81, 0x1, 0x1}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=AX/scale=4/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 4, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x84, 0x81, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=AX/scale=4/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 4, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x84, 0x81, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=BP/scale=4/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 4, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x4, 0xa9, 0x0}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=BP/scale=4/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 4, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x4, 0xa9, 0x1}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=BP/scale=4/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 4, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x44, 0xa9, 0x1, 0x0}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=BP/scale=4/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 4, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x44, 0xa9, 0x1, 0x1}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=BP/scale=4/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 4, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x84, 0xa9, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=BP/scale=4/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 4, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x84, 0xa9, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=SI/scale=4/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 4, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x4, 0xb1, 0x0}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=SI/scale=4/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 4, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x4, 0xb1, 0x1}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=SI/scale=4/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 4, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x44, 0xb1, 0x1, 0x0}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=SI/scale=4/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 4, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x44, 0xb1, 0x1, 0x1}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=SI/scale=4/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 4, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x84, 0xb1, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=SI/scale=4/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 4, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x84, 0xb1, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=R12/scale=8/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 8, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x16, 0x4, 0xe1, 0x0}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=R12/scale=8/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 8, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x16, 0x4, 0xe1, 0x1}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=R12/scale=8/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 8, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x16, 0x44, 0xe1, 0x1, 0x0}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=R12/scale=8/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 8, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x16, 0x44, 0xe1, 0x1, 0x1}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=R12/scale=8/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 8, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x16, 0x84, 0xe1, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=R12/scale=8/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 8, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x16, 0x84, 0xe1, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=AX/scale=8/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 8, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x4, 0xc1, 0x0}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=AX/scale=8/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 8, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x4, 0xc1, 0x1}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=AX/scale=8/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 8, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x44, 0xc1, 0x1, 0x0}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=AX/scale=8/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 8, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x44, 0xc1, 0x1, 0x1}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=AX/scale=8/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 8, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x84, 0xc1, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=AX/scale=8/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 8, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x84, 0xc1, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=BP/scale=8/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 8, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x4, 0xe9, 0x0}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=BP/scale=8/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 8, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x4, 0xe9, 0x1}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=BP/scale=8/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 8, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x44, 0xe9, 0x1, 0x0}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=BP/scale=8/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 8, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x44, 0xe9, 0x1, 0x1}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=BP/scale=8/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 8, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x84, 0xe9, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=BP/scale=8/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 8, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x84, 0xe9, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=SI/scale=8/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 8, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x4, 0xf1, 0x0}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=SI/scale=8/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 8, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x4, 0xf1, 0x1}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=SI/scale=8/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 8, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x44, 0xf1, 0x1, 0x0}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=SI/scale=8/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 8, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x44, 0xf1, 0x1, 0x1}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=SI/scale=8/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 8, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x84, 0xf1, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRQ/src=X0/dstBase=CX/index=SI/scale=8/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 8, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0x84, 0xf1, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=R12/scale=1/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 1, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x16, 0x2c, 0x21, 0x0}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=R12/scale=1/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 1, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x16, 0x2c, 0x21, 0x1}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=R12/scale=1/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 1, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x16, 0x6c, 0x21, 0x1, 0x0}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=R12/scale=1/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 1, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x16, 0x6c, 0x21, 0x1, 0x1}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=R12/scale=1/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 1, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x16, 0xac, 0x21, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=R12/scale=1/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 1, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x16, 0xac, 0x21, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=AX/scale=1/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 1, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0x2c, 0x1, 0x0}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=AX/scale=1/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 1, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0x2c, 0x1, 0x1}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=AX/scale=1/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 1, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0x6c, 0x1, 0x1, 0x0}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=AX/scale=1/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 1, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0x6c, 0x1, 0x1, 0x1}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=AX/scale=1/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 1, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0xac, 0x1, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=AX/scale=1/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 1, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0xac, 0x1, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=BP/scale=1/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 1, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0x2c, 0x29, 0x0}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=BP/scale=1/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 1, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0x2c, 0x29, 0x1}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=BP/scale=1/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 1, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0x6c, 0x29, 0x1, 0x0}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=BP/scale=1/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 1, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0x6c, 0x29, 0x1, 0x1}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=BP/scale=1/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 1, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0xac, 0x29, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=BP/scale=1/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 1, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0xac, 0x29, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=SI/scale=1/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 1, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0x2c, 0x31, 0x0}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=SI/scale=1/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 1, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0x2c, 0x31, 0x1}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=SI/scale=1/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 1, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0x6c, 0x31, 0x1, 0x0}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=SI/scale=1/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 1, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0x6c, 0x31, 0x1, 0x1}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=SI/scale=1/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 1, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0xac, 0x31, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=SI/scale=1/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 1, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0xac, 0x31, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=R12/scale=2/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 2, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x16, 0x2c, 0x61, 0x0}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=R12/scale=2/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 2, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x16, 0x2c, 0x61, 0x1}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=R12/scale=2/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 2, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x16, 0x6c, 0x61, 0x1, 0x0}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=R12/scale=2/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 2, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x16, 0x6c, 0x61, 0x1, 0x1}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=R12/scale=2/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 2, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x16, 0xac, 0x61, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=R12/scale=2/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 2, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x16, 0xac, 0x61, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=AX/scale=2/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 2, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0x2c, 0x41, 0x0}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=AX/scale=2/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 2, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0x2c, 0x41, 0x1}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=AX/scale=2/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 2, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0x6c, 0x41, 0x1, 0x0}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=AX/scale=2/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 2, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0x6c, 0x41, 0x1, 0x1}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=AX/scale=2/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 2, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0xac, 0x41, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=AX/scale=2/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 2, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0xac, 0x41, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=BP/scale=2/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 2, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0x2c, 0x69, 0x0}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=BP/scale=2/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 2, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0x2c, 0x69, 0x1}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=BP/scale=2/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 2, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0x6c, 0x69, 0x1, 0x0}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=BP/scale=2/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 2, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0x6c, 0x69, 0x1, 0x1}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=BP/scale=2/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 2, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0xac, 0x69, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=BP/scale=2/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 2, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0xac, 0x69, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=SI/scale=2/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 2, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0x2c, 0x71, 0x0}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=SI/scale=2/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 2, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0x2c, 0x71, 0x1}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=SI/scale=2/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 2, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0x6c, 0x71, 0x1, 0x0}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=SI/scale=2/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 2, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0x6c, 0x71, 0x1, 0x1}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=SI/scale=2/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 2, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0xac, 0x71, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=SI/scale=2/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 2, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0xac, 0x71, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=R12/scale=4/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 4, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x16, 0x2c, 0xa1, 0x0}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=R12/scale=4/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 4, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x16, 0x2c, 0xa1, 0x1}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=R12/scale=4/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 4, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x16, 0x6c, 0xa1, 0x1, 0x0}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=R12/scale=4/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 4, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x16, 0x6c, 0xa1, 0x1, 0x1}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=R12/scale=4/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 4, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x16, 0xac, 0xa1, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=R12/scale=4/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 4, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x16, 0xac, 0xa1, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=AX/scale=4/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 4, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0x2c, 0x81, 0x0}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=AX/scale=4/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 4, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0x2c, 0x81, 0x1}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=AX/scale=4/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 4, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0x6c, 0x81, 0x1, 0x0}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=AX/scale=4/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 4, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0x6c, 0x81, 0x1, 0x1}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=AX/scale=4/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 4, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0xac, 0x81, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=AX/scale=4/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 4, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0xac, 0x81, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=BP/scale=4/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 4, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0x2c, 0xa9, 0x0}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=BP/scale=4/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 4, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0x2c, 0xa9, 0x1}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=BP/scale=4/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 4, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0x6c, 0xa9, 0x1, 0x0}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=BP/scale=4/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 4, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0x6c, 0xa9, 0x1, 0x1}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=BP/scale=4/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 4, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0xac, 0xa9, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=BP/scale=4/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 4, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0xac, 0xa9, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=SI/scale=4/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 4, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0x2c, 0xb1, 0x0}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=SI/scale=4/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 4, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0x2c, 0xb1, 0x1}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=SI/scale=4/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 4, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0x6c, 0xb1, 0x1, 0x0}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=SI/scale=4/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 4, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0x6c, 0xb1, 0x1, 0x1}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=SI/scale=4/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 4, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0xac, 0xb1, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=SI/scale=4/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 4, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0xac, 0xb1, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=R12/scale=8/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 8, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x16, 0x2c, 0xe1, 0x0}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=R12/scale=8/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 8, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x16, 0x2c, 0xe1, 0x1}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=R12/scale=8/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 8, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x16, 0x6c, 0xe1, 0x1, 0x0}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=R12/scale=8/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 8, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x16, 0x6c, 0xe1, 0x1, 0x1}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=R12/scale=8/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 8, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x16, 0xac, 0xe1, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=R12/scale=8/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegR12, dstMemScale: 8, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x16, 0xac, 0xe1, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=AX/scale=8/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 8, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0x2c, 0xc1, 0x0}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=AX/scale=8/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 8, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0x2c, 0xc1, 0x1}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=AX/scale=8/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 8, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0x6c, 0xc1, 0x1, 0x0}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=AX/scale=8/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 8, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0x6c, 0xc1, 0x1, 0x1}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=AX/scale=8/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 8, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0xac, 0xc1, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=AX/scale=8/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegAX, dstMemScale: 8, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0xac, 0xc1, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=BP/scale=8/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 8, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0x2c, 0xe9, 0x0}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=BP/scale=8/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 8, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0x2c, 0xe9, 0x1}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=BP/scale=8/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 8, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0x6c, 0xe9, 0x1, 0x0}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=BP/scale=8/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 8, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0x6c, 0xe9, 0x1, 0x1}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=BP/scale=8/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 8, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0xac, 0xe9, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=BP/scale=8/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegBP, dstMemScale: 8, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0xac, 0xe9, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=SI/scale=8/offset=0/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 8, dstConst: 0, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0x2c, 0xf1, 0x0}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=SI/scale=8/offset=0/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 8, dstConst: 0, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0x2c, 0xf1, 0x1}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=SI/scale=8/offset=1/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 8, dstConst: 1, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0x6c, 0xf1, 0x1, 0x0}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=SI/scale=8/offset=1/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 8, dstConst: 1, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0x6c, 0xf1, 0x1, 0x1}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=SI/scale=8/offset=2147483647/arg=0", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 8, dstConst: 2147483647, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0xac, 0xf1, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "PEXTRQ/src=X13/dstBase=CX/index=SI/scale=8/offset=2147483647/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX13, dstReg: RegCX, dstMemIndex: RegSI, dstMemScale: 8, dstConst: 2147483647, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0xac, 0xf1, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - } - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - for _, tc := range tests { - t.Run(tc.name, func(t *testing.T) { - tc.n.types = operandTypesRegisterToMemory - a := NewAssembler() - buf := code.NextCodeSection() - err := a.encodeRegisterToMemory(buf, tc.n) - require.NoError(t, err, tc.name) - - err = a.Assemble(buf) - require.NoError(t, err, tc.name) - - actual := buf.Bytes() - require.Equal(t, tc.exp, actual, tc.name) - }) - } -} diff --git a/internal/asm/amd64/impl_4_test.go b/internal/asm/amd64/impl_4_test.go deleted file mode 100644 index a056e4c31f..0000000000 --- a/internal/asm/amd64/impl_4_test.go +++ /dev/null @@ -1,1481 +0,0 @@ -package amd64 - -import ( - "math" - "testing" - - "github.com/tetratelabs/wazero/internal/asm" - "github.com/tetratelabs/wazero/internal/testing/require" -) - -func TestAssemblerImpl_encodeConstToRegister(t *testing.T) { - t.Run("error", func(t *testing.T) { - tests := []struct { - n *nodeImpl - expErr string - }{ - { - n: &nodeImpl{instruction: RET, types: operandTypesConstToRegister, dstReg: RegAX}, - expErr: "RET is unsupported for ConstToRegister type", - }, - { - n: &nodeImpl{instruction: PSLLD, types: operandTypesConstToRegister}, - expErr: "PSLLD needs float register but got nil", - }, - { - n: &nodeImpl{instruction: PSLLD, types: operandTypesConstToRegister, dstReg: RegAX}, - expErr: "PSLLD needs float register but got AX", - }, - { - n: &nodeImpl{instruction: ADDQ, types: operandTypesConstToRegister, dstReg: RegX0}, - expErr: "ADDQ needs int register but got X0", - }, - { - n: &nodeImpl{instruction: PSLLD, types: operandTypesConstToRegister, dstReg: RegX0, srcConst: 2199023255552}, - expErr: "constant must fit in 32-bit integer for PSLLD, but got 2199023255552", - }, - { - n: &nodeImpl{instruction: SHLQ, types: operandTypesConstToRegister, dstReg: RegR10, srcConst: 32768}, - expErr: "constant must fit in positive 8-bit integer for SHLQ, but got 32768", - }, - { - n: &nodeImpl{instruction: PSRLQ, types: operandTypesConstToRegister, dstReg: RegX0, srcConst: 32768}, - expErr: "constant must fit in signed 8-bit integer for PSRLQ, but got 32768", - }, - } - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - for _, tc := range tests { - a := NewAssembler() - buf := code.NextCodeSection() - err := a.encodeConstToRegister(buf, tc.n) - require.EqualError(t, err, tc.expErr) - } - }) - - tests := []struct { - name string - c int64 - inst asm.Instruction - dstReg asm.Register - exp []byte - }{ - {name: "ADDQ/c=0/dst=BX", inst: ADDQ, c: 0x0, dstReg: RegBX, exp: []byte{0x48, 0x83, 0xc3, 0x0}}, - {name: "ADDQ/c=1/dst=BX", inst: ADDQ, c: 0x1, dstReg: RegBX, exp: []byte{0x48, 0x83, 0xc3, 0x1}}, - {name: "ADDQ/c=-1/dst=BX", inst: ADDQ, c: -0x1, dstReg: RegBX, exp: []byte{0x48, 0x83, 0xc3, 0xff}}, - {name: "ADDQ/c=11/dst=BX", inst: ADDQ, c: 0xb, dstReg: RegBX, exp: []byte{0x48, 0x83, 0xc3, 0xb}}, - {name: "ADDQ/c=-11/dst=BX", inst: ADDQ, c: -0xb, dstReg: RegBX, exp: []byte{0x48, 0x83, 0xc3, 0xf5}}, - {name: "ADDQ/c=1243/dst=BX", inst: ADDQ, c: 0x4db, dstReg: RegBX, exp: []byte{0x48, 0x81, 0xc3, 0xdb, 0x4, 0x0, 0x0}}, - {name: "ADDQ/c=-1234/dst=BX", inst: ADDQ, c: -0x4d2, dstReg: RegBX, exp: []byte{0x48, 0x81, 0xc3, 0x2e, 0xfb, 0xff, 0xff}}, - {name: "ADDQ/c=255/dst=BX", inst: ADDQ, c: 0xff, dstReg: RegBX, exp: []byte{0x48, 0x81, 0xc3, 0xff, 0x0, 0x0, 0x0}}, - {name: "ADDQ/c=2147483647/dst=BX", inst: ADDQ, c: 0x7fffffff, dstReg: RegBX, exp: []byte{0x48, 0x81, 0xc3, 0xff, 0xff, 0xff, 0x7f}}, - {name: "ADDQ/c=-2147483648/dst=BX", inst: ADDQ, c: -0x80000000, dstReg: RegBX, exp: []byte{0x48, 0x81, 0xc3, 0x0, 0x0, 0x0, 0x80}}, - {name: "ADDQ/c=32767/dst=BX", inst: ADDQ, c: 0x7fff, dstReg: RegBX, exp: []byte{0x48, 0x81, 0xc3, 0xff, 0x7f, 0x0, 0x0}}, - {name: "ADDQ/c=4294967295/dst=BX", inst: ADDQ, c: 0xffffffff, dstReg: RegBX, exp: []byte{0x48, 0x81, 0xc3, 0xff, 0xff, 0xff, 0xff}}, - {name: "ADDQ/c=-32768/dst=BX", inst: ADDQ, c: -0x8000, dstReg: RegBX, exp: []byte{0x48, 0x81, 0xc3, 0x0, 0x80, 0xff, 0xff}}, - {name: "ADDQ/c=0/dst=R15", inst: ADDQ, c: 0x0, dstReg: RegR15, exp: []byte{0x49, 0x83, 0xc7, 0x0}}, - {name: "ADDQ/c=1/dst=R15", inst: ADDQ, c: 0x1, dstReg: RegR15, exp: []byte{0x49, 0x83, 0xc7, 0x1}}, - {name: "ADDQ/c=-1/dst=R15", inst: ADDQ, c: -0x1, dstReg: RegR15, exp: []byte{0x49, 0x83, 0xc7, 0xff}}, - {name: "ADDQ/c=11/dst=R15", inst: ADDQ, c: 0xb, dstReg: RegR15, exp: []byte{0x49, 0x83, 0xc7, 0xb}}, - {name: "ADDQ/c=-11/dst=R15", inst: ADDQ, c: -0xb, dstReg: RegR15, exp: []byte{0x49, 0x83, 0xc7, 0xf5}}, - {name: "ADDQ/c=1243/dst=R15", inst: ADDQ, c: 0x4db, dstReg: RegR15, exp: []byte{0x49, 0x81, 0xc7, 0xdb, 0x4, 0x0, 0x0}}, - {name: "ADDQ/c=-1234/dst=R15", inst: ADDQ, c: -0x4d2, dstReg: RegR15, exp: []byte{0x49, 0x81, 0xc7, 0x2e, 0xfb, 0xff, 0xff}}, - {name: "ADDQ/c=255/dst=R15", inst: ADDQ, c: 0xff, dstReg: RegR15, exp: []byte{0x49, 0x81, 0xc7, 0xff, 0x0, 0x0, 0x0}}, - {name: "ADDQ/c=2147483647/dst=R15", inst: ADDQ, c: 0x7fffffff, dstReg: RegR15, exp: []byte{0x49, 0x81, 0xc7, 0xff, 0xff, 0xff, 0x7f}}, - {name: "ADDQ/c=-2147483648/dst=R15", inst: ADDQ, c: -0x80000000, dstReg: RegR15, exp: []byte{0x49, 0x81, 0xc7, 0x0, 0x0, 0x0, 0x80}}, - {name: "ADDQ/c=32767/dst=R15", inst: ADDQ, c: 0x7fff, dstReg: RegR15, exp: []byte{0x49, 0x81, 0xc7, 0xff, 0x7f, 0x0, 0x0}}, - {name: "ADDQ/c=4294967295/dst=R15", inst: ADDQ, c: 0xffffffff, dstReg: RegR15, exp: []byte{0x49, 0x81, 0xc7, 0xff, 0xff, 0xff, 0xff}}, - {name: "ADDQ/c=-32768/dst=R15", inst: ADDQ, c: -0x8000, dstReg: RegR15, exp: []byte{0x49, 0x81, 0xc7, 0x0, 0x80, 0xff, 0xff}}, - {name: "ANDQ/c=0/dst=BX", inst: ANDQ, c: 0x0, dstReg: RegBX, exp: []byte{0x48, 0x83, 0xe3, 0x0}}, - {name: "ANDQ/c=1/dst=BX", inst: ANDQ, c: 0x1, dstReg: RegBX, exp: []byte{0x48, 0x83, 0xe3, 0x1}}, - {name: "ANDQ/c=-1/dst=BX", inst: ANDQ, c: -0x1, dstReg: RegBX, exp: []byte{0x48, 0x83, 0xe3, 0xff}}, - {name: "ANDQ/c=11/dst=BX", inst: ANDQ, c: 0xb, dstReg: RegBX, exp: []byte{0x48, 0x83, 0xe3, 0xb}}, - {name: "ANDQ/c=-11/dst=BX", inst: ANDQ, c: -0xb, dstReg: RegBX, exp: []byte{0x48, 0x83, 0xe3, 0xf5}}, - {name: "ANDQ/c=1243/dst=BX", inst: ANDQ, c: 0x4db, dstReg: RegBX, exp: []byte{0x48, 0x81, 0xe3, 0xdb, 0x4, 0x0, 0x0}}, - {name: "ANDQ/c=-1234/dst=BX", inst: ANDQ, c: -0x4d2, dstReg: RegBX, exp: []byte{0x48, 0x81, 0xe3, 0x2e, 0xfb, 0xff, 0xff}}, - {name: "ANDQ/c=255/dst=BX", inst: ANDQ, c: 0xff, dstReg: RegBX, exp: []byte{0x48, 0x81, 0xe3, 0xff, 0x0, 0x0, 0x0}}, - {name: "ANDQ/c=2147483647/dst=BX", inst: ANDQ, c: 0x7fffffff, dstReg: RegBX, exp: []byte{0x48, 0x81, 0xe3, 0xff, 0xff, 0xff, 0x7f}}, - {name: "ANDQ/c=-2147483648/dst=BX", inst: ANDQ, c: -0x80000000, dstReg: RegBX, exp: []byte{0x48, 0x81, 0xe3, 0x0, 0x0, 0x0, 0x80}}, - {name: "ANDQ/c=32767/dst=BX", inst: ANDQ, c: 0x7fff, dstReg: RegBX, exp: []byte{0x48, 0x81, 0xe3, 0xff, 0x7f, 0x0, 0x0}}, - {name: "ANDQ/c=4294967295/dst=BX", inst: ANDQ, c: 0xffffffff, dstReg: RegBX, exp: []byte{0x48, 0x81, 0xe3, 0xff, 0xff, 0xff, 0xff}}, - {name: "ANDQ/c=-32768/dst=BX", inst: ANDQ, c: -0x8000, dstReg: RegBX, exp: []byte{0x48, 0x81, 0xe3, 0x0, 0x80, 0xff, 0xff}}, - {name: "ANDQ/c=0/dst=R15", inst: ANDQ, c: 0x0, dstReg: RegR15, exp: []byte{0x49, 0x83, 0xe7, 0x0}}, - {name: "ANDQ/c=1/dst=R15", inst: ANDQ, c: 0x1, dstReg: RegR15, exp: []byte{0x49, 0x83, 0xe7, 0x1}}, - {name: "ANDQ/c=-1/dst=R15", inst: ANDQ, c: -0x1, dstReg: RegR15, exp: []byte{0x49, 0x83, 0xe7, 0xff}}, - {name: "ANDQ/c=11/dst=R15", inst: ANDQ, c: 0xb, dstReg: RegR15, exp: []byte{0x49, 0x83, 0xe7, 0xb}}, - {name: "ANDQ/c=-11/dst=R15", inst: ANDQ, c: -0xb, dstReg: RegR15, exp: []byte{0x49, 0x83, 0xe7, 0xf5}}, - {name: "ANDQ/c=1243/dst=R15", inst: ANDQ, c: 0x4db, dstReg: RegR15, exp: []byte{0x49, 0x81, 0xe7, 0xdb, 0x4, 0x0, 0x0}}, - {name: "ANDQ/c=-1234/dst=R15", inst: ANDQ, c: -0x4d2, dstReg: RegR15, exp: []byte{0x49, 0x81, 0xe7, 0x2e, 0xfb, 0xff, 0xff}}, - {name: "ANDQ/c=255/dst=R15", inst: ANDQ, c: 0xff, dstReg: RegR15, exp: []byte{0x49, 0x81, 0xe7, 0xff, 0x0, 0x0, 0x0}}, - {name: "ANDQ/c=2147483647/dst=R15", inst: ANDQ, c: 0x7fffffff, dstReg: RegR15, exp: []byte{0x49, 0x81, 0xe7, 0xff, 0xff, 0xff, 0x7f}}, - {name: "ANDQ/c=-2147483648/dst=R15", inst: ANDQ, c: -0x80000000, dstReg: RegR15, exp: []byte{0x49, 0x81, 0xe7, 0x0, 0x0, 0x0, 0x80}}, - {name: "ANDQ/c=32767/dst=R15", inst: ANDQ, c: 0x7fff, dstReg: RegR15, exp: []byte{0x49, 0x81, 0xe7, 0xff, 0x7f, 0x0, 0x0}}, - {name: "ANDQ/c=4294967295/dst=R15", inst: ANDQ, c: 0xffffffff, dstReg: RegR15, exp: []byte{0x49, 0x81, 0xe7, 0xff, 0xff, 0xff, 0xff}}, - {name: "ANDQ/c=-32768/dst=R15", inst: ANDQ, c: -0x8000, dstReg: RegR15, exp: []byte{0x49, 0x81, 0xe7, 0x0, 0x80, 0xff, 0xff}}, - {name: "MOVL/c=0/dst=BX", inst: MOVL, c: 0x0, dstReg: RegBX, exp: []byte{0xbb, 0x0, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=1/dst=BX", inst: MOVL, c: 0x1, dstReg: RegBX, exp: []byte{0xbb, 0x1, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-1/dst=BX", inst: MOVL, c: -0x1, dstReg: RegBX, exp: []byte{0xbb, 0xff, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=11/dst=BX", inst: MOVL, c: 0xb, dstReg: RegBX, exp: []byte{0xbb, 0xb, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-11/dst=BX", inst: MOVL, c: -0xb, dstReg: RegBX, exp: []byte{0xbb, 0xf5, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=1243/dst=BX", inst: MOVL, c: 0x4db, dstReg: RegBX, exp: []byte{0xbb, 0xdb, 0x4, 0x0, 0x0}}, - {name: "MOVL/c=-1234/dst=BX", inst: MOVL, c: -0x4d2, dstReg: RegBX, exp: []byte{0xbb, 0x2e, 0xfb, 0xff, 0xff}}, - {name: "MOVL/c=255/dst=BX", inst: MOVL, c: 0xff, dstReg: RegBX, exp: []byte{0xbb, 0xff, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=2147483647/dst=BX", inst: MOVL, c: 0x7fffffff, dstReg: RegBX, exp: []byte{0xbb, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVL/c=-2147483648/dst=BX", inst: MOVL, c: -0x80000000, dstReg: RegBX, exp: []byte{0xbb, 0x0, 0x0, 0x0, 0x80}}, - {name: "MOVL/c=32767/dst=BX", inst: MOVL, c: 0x7fff, dstReg: RegBX, exp: []byte{0xbb, 0xff, 0x7f, 0x0, 0x0}}, - {name: "MOVL/c=4294967295/dst=BX", inst: MOVL, c: 0xffffffff, dstReg: RegBX, exp: []byte{0xbb, 0xff, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=-32768/dst=BX", inst: MOVL, c: -0x8000, dstReg: RegBX, exp: []byte{0xbb, 0x0, 0x80, 0xff, 0xff}}, - {name: "MOVL/c=0/dst=R15", inst: MOVL, c: 0x0, dstReg: RegR15, exp: []byte{0x41, 0xbf, 0x0, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=1/dst=R15", inst: MOVL, c: 0x1, dstReg: RegR15, exp: []byte{0x41, 0xbf, 0x1, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-1/dst=R15", inst: MOVL, c: -0x1, dstReg: RegR15, exp: []byte{0x41, 0xbf, 0xff, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=11/dst=R15", inst: MOVL, c: 0xb, dstReg: RegR15, exp: []byte{0x41, 0xbf, 0xb, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-11/dst=R15", inst: MOVL, c: -0xb, dstReg: RegR15, exp: []byte{0x41, 0xbf, 0xf5, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=1243/dst=R15", inst: MOVL, c: 0x4db, dstReg: RegR15, exp: []byte{0x41, 0xbf, 0xdb, 0x4, 0x0, 0x0}}, - {name: "MOVL/c=-1234/dst=R15", inst: MOVL, c: -0x4d2, dstReg: RegR15, exp: []byte{0x41, 0xbf, 0x2e, 0xfb, 0xff, 0xff}}, - {name: "MOVL/c=255/dst=R15", inst: MOVL, c: 0xff, dstReg: RegR15, exp: []byte{0x41, 0xbf, 0xff, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=2147483647/dst=R15", inst: MOVL, c: 0x7fffffff, dstReg: RegR15, exp: []byte{0x41, 0xbf, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVL/c=-2147483648/dst=R15", inst: MOVL, c: -0x80000000, dstReg: RegR15, exp: []byte{0x41, 0xbf, 0x0, 0x0, 0x0, 0x80}}, - {name: "MOVL/c=32767/dst=R15", inst: MOVL, c: 0x7fff, dstReg: RegR15, exp: []byte{0x41, 0xbf, 0xff, 0x7f, 0x0, 0x0}}, - {name: "MOVL/c=4294967295/dst=R15", inst: MOVL, c: 0xffffffff, dstReg: RegR15, exp: []byte{0x41, 0xbf, 0xff, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=-32768/dst=R15", inst: MOVL, c: -0x8000, dstReg: RegR15, exp: []byte{0x41, 0xbf, 0x0, 0x80, 0xff, 0xff}}, - {name: "MOVQ/c=0/dst=BX", inst: MOVQ, c: 0x0, dstReg: RegBX, exp: []byte{0x48, 0xc7, 0xc3, 0x0, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=1/dst=BX", inst: MOVQ, c: 0x1, dstReg: RegBX, exp: []byte{0x48, 0xc7, 0xc3, 0x1, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-1/dst=BX", inst: MOVQ, c: -0x1, dstReg: RegBX, exp: []byte{0x48, 0xc7, 0xc3, 0xff, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=11/dst=BX", inst: MOVQ, c: 0xb, dstReg: RegBX, exp: []byte{0x48, 0xc7, 0xc3, 0xb, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-11/dst=BX", inst: MOVQ, c: -0xb, dstReg: RegBX, exp: []byte{0x48, 0xc7, 0xc3, 0xf5, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=1243/dst=BX", inst: MOVQ, c: 0x4db, dstReg: RegBX, exp: []byte{0x48, 0xc7, 0xc3, 0xdb, 0x4, 0x0, 0x0}}, - {name: "MOVQ/c=-1234/dst=BX", inst: MOVQ, c: -0x4d2, dstReg: RegBX, exp: []byte{0x48, 0xc7, 0xc3, 0x2e, 0xfb, 0xff, 0xff}}, - {name: "MOVQ/c=255/dst=BX", inst: MOVQ, c: 0xff, dstReg: RegBX, exp: []byte{0x48, 0xc7, 0xc3, 0xff, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=2147483647/dst=BX", inst: MOVQ, c: 0x7fffffff, dstReg: RegBX, exp: []byte{0x48, 0xc7, 0xc3, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVQ/c=-2147483648/dst=BX", inst: MOVQ, c: -0x80000000, dstReg: RegBX, exp: []byte{0x48, 0xc7, 0xc3, 0x0, 0x0, 0x0, 0x80}}, - {name: "MOVQ/c=32767/dst=BX", inst: MOVQ, c: 0x7fff, dstReg: RegBX, exp: []byte{0x48, 0xc7, 0xc3, 0xff, 0x7f, 0x0, 0x0}}, - {name: "MOVQ/c=4294967295/dst=BX", inst: MOVQ, c: 0xffffffff, dstReg: RegBX, exp: []byte{0xbb, 0xff, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=-32768/dst=BX", inst: MOVQ, c: -0x8000, dstReg: RegBX, exp: []byte{0x48, 0xc7, 0xc3, 0x0, 0x80, 0xff, 0xff}}, - {name: "MOVQ/c=9223372036854775807/dst=BX", inst: MOVQ, c: 0x7fffffffffffffff, dstReg: RegBX, exp: []byte{0x48, 0xbb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVQ/c=-9223372036854775808/dst=BX", inst: MOVQ, c: -0x8000000000000000, dstReg: RegBX, exp: []byte{0x48, 0xbb, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80}}, - {name: "MOVQ/c=0/dst=R15", inst: MOVQ, c: 0x0, dstReg: RegR15, exp: []byte{0x49, 0xc7, 0xc7, 0x0, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=1/dst=R15", inst: MOVQ, c: 0x1, dstReg: RegR15, exp: []byte{0x49, 0xc7, 0xc7, 0x1, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-1/dst=R15", inst: MOVQ, c: -0x1, dstReg: RegR15, exp: []byte{0x49, 0xc7, 0xc7, 0xff, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=11/dst=R15", inst: MOVQ, c: 0xb, dstReg: RegR15, exp: []byte{0x49, 0xc7, 0xc7, 0xb, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-11/dst=R15", inst: MOVQ, c: -0xb, dstReg: RegR15, exp: []byte{0x49, 0xc7, 0xc7, 0xf5, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=1243/dst=R15", inst: MOVQ, c: 0x4db, dstReg: RegR15, exp: []byte{0x49, 0xc7, 0xc7, 0xdb, 0x4, 0x0, 0x0}}, - {name: "MOVQ/c=-1234/dst=R15", inst: MOVQ, c: -0x4d2, dstReg: RegR15, exp: []byte{0x49, 0xc7, 0xc7, 0x2e, 0xfb, 0xff, 0xff}}, - {name: "MOVQ/c=255/dst=R15", inst: MOVQ, c: 0xff, dstReg: RegR15, exp: []byte{0x49, 0xc7, 0xc7, 0xff, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=2147483647/dst=R15", inst: MOVQ, c: 0x7fffffff, dstReg: RegR15, exp: []byte{0x49, 0xc7, 0xc7, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVQ/c=-2147483648/dst=R15", inst: MOVQ, c: -0x80000000, dstReg: RegR15, exp: []byte{0x49, 0xc7, 0xc7, 0x0, 0x0, 0x0, 0x80}}, - {name: "MOVQ/c=32767/dst=R15", inst: MOVQ, c: 0x7fff, dstReg: RegR15, exp: []byte{0x49, 0xc7, 0xc7, 0xff, 0x7f, 0x0, 0x0}}, - {name: "MOVQ/c=4294967295/dst=R15", inst: MOVQ, c: 0xffffffff, dstReg: RegR15, exp: []byte{0x41, 0xbf, 0xff, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=-32768/dst=R15", inst: MOVQ, c: -0x8000, dstReg: RegR15, exp: []byte{0x49, 0xc7, 0xc7, 0x0, 0x80, 0xff, 0xff}}, - {name: "MOVQ/c=9223372036854775807/dst=R15", inst: MOVQ, c: 0x7fffffffffffffff, dstReg: RegR15, exp: []byte{0x49, 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVQ/c=-9223372036854775808/dst=R15", inst: MOVQ, c: -0x8000000000000000, dstReg: RegR15, exp: []byte{0x49, 0xbf, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80}}, - {name: "SHLQ/c=0/dst=BX", inst: SHLQ, c: 0x0, dstReg: RegBX, exp: []byte{0x48, 0xc1, 0xe3, 0x0}}, - {name: "SHLQ/c=1/dst=BX", inst: SHLQ, c: 0x1, dstReg: RegBX, exp: []byte{0x48, 0xd1, 0xe3}}, - {name: "SHLQ/c=11/dst=BX", inst: SHLQ, c: 0xb, dstReg: RegBX, exp: []byte{0x48, 0xc1, 0xe3, 0xb}}, - {name: "SHLQ/c=255/dst=BX", inst: SHLQ, c: 0xff, dstReg: RegBX, exp: []byte{0x48, 0xc1, 0xe3, 0xff}}, - {name: "SHLQ/c=0/dst=R15", inst: SHLQ, c: 0x0, dstReg: RegR15, exp: []byte{0x49, 0xc1, 0xe7, 0x0}}, - {name: "SHLQ/c=1/dst=R15", inst: SHLQ, c: 0x1, dstReg: RegR15, exp: []byte{0x49, 0xd1, 0xe7}}, - {name: "SHLQ/c=11/dst=R15", inst: SHLQ, c: 0xb, dstReg: RegR15, exp: []byte{0x49, 0xc1, 0xe7, 0xb}}, - {name: "SHLQ/c=255/dst=R15", inst: SHLQ, c: 0xff, dstReg: RegR15, exp: []byte{0x49, 0xc1, 0xe7, 0xff}}, - {name: "SHRQ/c=0/dst=BX", inst: SHRQ, c: 0x0, dstReg: RegBX, exp: []byte{0x48, 0xc1, 0xeb, 0x0}}, - {name: "SHRQ/c=1/dst=BX", inst: SHRQ, c: 0x1, dstReg: RegBX, exp: []byte{0x48, 0xd1, 0xeb}}, - {name: "SHRQ/c=11/dst=BX", inst: SHRQ, c: 0xb, dstReg: RegBX, exp: []byte{0x48, 0xc1, 0xeb, 0xb}}, - {name: "SHRQ/c=255/dst=BX", inst: SHRQ, c: 0xff, dstReg: RegBX, exp: []byte{0x48, 0xc1, 0xeb, 0xff}}, - {name: "SHRQ/c=0/dst=R15", inst: SHRQ, c: 0x0, dstReg: RegR15, exp: []byte{0x49, 0xc1, 0xef, 0x0}}, - {name: "SHRQ/c=1/dst=R15", inst: SHRQ, c: 0x1, dstReg: RegR15, exp: []byte{0x49, 0xd1, 0xef}}, - {name: "SHRQ/c=11/dst=R15", inst: SHRQ, c: 0xb, dstReg: RegR15, exp: []byte{0x49, 0xc1, 0xef, 0xb}}, - {name: "SHRQ/c=255/dst=R15", inst: SHRQ, c: 0xff, dstReg: RegR15, exp: []byte{0x49, 0xc1, 0xef, 0xff}}, - {name: "XORL/c=0/dst=BX", inst: XORL, c: 0x0, dstReg: RegBX, exp: []byte{0x83, 0xf3, 0x0}}, - {name: "XORL/c=1/dst=BX", inst: XORL, c: 0x1, dstReg: RegBX, exp: []byte{0x83, 0xf3, 0x1}}, - {name: "XORL/c=-1/dst=BX", inst: XORL, c: -0x1, dstReg: RegBX, exp: []byte{0x83, 0xf3, 0xff}}, - {name: "XORL/c=11/dst=BX", inst: XORL, c: 0xb, dstReg: RegBX, exp: []byte{0x83, 0xf3, 0xb}}, - {name: "XORL/c=-11/dst=BX", inst: XORL, c: -0xb, dstReg: RegBX, exp: []byte{0x83, 0xf3, 0xf5}}, - {name: "XORL/c=1243/dst=BX", inst: XORL, c: 0x4db, dstReg: RegBX, exp: []byte{0x81, 0xf3, 0xdb, 0x4, 0x0, 0x0}}, - {name: "XORL/c=-1234/dst=BX", inst: XORL, c: -0x4d2, dstReg: RegBX, exp: []byte{0x81, 0xf3, 0x2e, 0xfb, 0xff, 0xff}}, - {name: "XORL/c=255/dst=BX", inst: XORL, c: 0xff, dstReg: RegBX, exp: []byte{0x81, 0xf3, 0xff, 0x0, 0x0, 0x0}}, - {name: "XORL/c=2147483647/dst=BX", inst: XORL, c: 0x7fffffff, dstReg: RegBX, exp: []byte{0x81, 0xf3, 0xff, 0xff, 0xff, 0x7f}}, - {name: "XORL/c=-2147483648/dst=BX", inst: XORL, c: -0x80000000, dstReg: RegBX, exp: []byte{0x81, 0xf3, 0x0, 0x0, 0x0, 0x80}}, - {name: "XORL/c=32767/dst=BX", inst: XORL, c: 0x7fff, dstReg: RegBX, exp: []byte{0x81, 0xf3, 0xff, 0x7f, 0x0, 0x0}}, - {name: "XORL/c=4294967295/dst=BX", inst: XORL, c: 0xffffffff, dstReg: RegBX, exp: []byte{0x81, 0xf3, 0xff, 0xff, 0xff, 0xff}}, - {name: "XORL/c=-32768/dst=BX", inst: XORL, c: -0x8000, dstReg: RegBX, exp: []byte{0x81, 0xf3, 0x0, 0x80, 0xff, 0xff}}, - {name: "XORL/c=0/dst=R15", inst: XORL, c: 0x0, dstReg: RegR15, exp: []byte{0x41, 0x83, 0xf7, 0x0}}, - {name: "XORL/c=1/dst=R15", inst: XORL, c: 0x1, dstReg: RegR15, exp: []byte{0x41, 0x83, 0xf7, 0x1}}, - {name: "XORL/c=-1/dst=R15", inst: XORL, c: -0x1, dstReg: RegR15, exp: []byte{0x41, 0x83, 0xf7, 0xff}}, - {name: "XORL/c=11/dst=R15", inst: XORL, c: 0xb, dstReg: RegR15, exp: []byte{0x41, 0x83, 0xf7, 0xb}}, - {name: "XORL/c=-11/dst=R15", inst: XORL, c: -0xb, dstReg: RegR15, exp: []byte{0x41, 0x83, 0xf7, 0xf5}}, - {name: "XORL/c=1243/dst=R15", inst: XORL, c: 0x4db, dstReg: RegR15, exp: []byte{0x41, 0x81, 0xf7, 0xdb, 0x4, 0x0, 0x0}}, - {name: "XORL/c=-1234/dst=R15", inst: XORL, c: -0x4d2, dstReg: RegR15, exp: []byte{0x41, 0x81, 0xf7, 0x2e, 0xfb, 0xff, 0xff}}, - {name: "XORL/c=255/dst=R15", inst: XORL, c: 0xff, dstReg: RegR15, exp: []byte{0x41, 0x81, 0xf7, 0xff, 0x0, 0x0, 0x0}}, - {name: "XORL/c=2147483647/dst=R15", inst: XORL, c: 0x7fffffff, dstReg: RegR15, exp: []byte{0x41, 0x81, 0xf7, 0xff, 0xff, 0xff, 0x7f}}, - {name: "XORL/c=-2147483648/dst=R15", inst: XORL, c: -0x80000000, dstReg: RegR15, exp: []byte{0x41, 0x81, 0xf7, 0x0, 0x0, 0x0, 0x80}}, - {name: "XORL/c=32767/dst=R15", inst: XORL, c: 0x7fff, dstReg: RegR15, exp: []byte{0x41, 0x81, 0xf7, 0xff, 0x7f, 0x0, 0x0}}, - {name: "XORL/c=4294967295/dst=R15", inst: XORL, c: 0xffffffff, dstReg: RegR15, exp: []byte{0x41, 0x81, 0xf7, 0xff, 0xff, 0xff, 0xff}}, - {name: "XORL/c=-32768/dst=R15", inst: XORL, c: -0x8000, dstReg: RegR15, exp: []byte{0x41, 0x81, 0xf7, 0x0, 0x80, 0xff, 0xff}}, - {name: "XORQ/c=0/dst=BX", inst: XORQ, c: 0x0, dstReg: RegBX, exp: []byte{0x48, 0x83, 0xf3, 0x0}}, - {name: "XORQ/c=1/dst=BX", inst: XORQ, c: 0x1, dstReg: RegBX, exp: []byte{0x48, 0x83, 0xf3, 0x1}}, - {name: "XORQ/c=-1/dst=BX", inst: XORQ, c: -0x1, dstReg: RegBX, exp: []byte{0x48, 0x83, 0xf3, 0xff}}, - {name: "XORQ/c=11/dst=BX", inst: XORQ, c: 0xb, dstReg: RegBX, exp: []byte{0x48, 0x83, 0xf3, 0xb}}, - {name: "XORQ/c=-11/dst=BX", inst: XORQ, c: -0xb, dstReg: RegBX, exp: []byte{0x48, 0x83, 0xf3, 0xf5}}, - {name: "XORQ/c=1243/dst=BX", inst: XORQ, c: 0x4db, dstReg: RegBX, exp: []byte{0x48, 0x81, 0xf3, 0xdb, 0x4, 0x0, 0x0}}, - {name: "XORQ/c=-1234/dst=BX", inst: XORQ, c: -0x4d2, dstReg: RegBX, exp: []byte{0x48, 0x81, 0xf3, 0x2e, 0xfb, 0xff, 0xff}}, - {name: "XORQ/c=255/dst=BX", inst: XORQ, c: 0xff, dstReg: RegBX, exp: []byte{0x48, 0x81, 0xf3, 0xff, 0x0, 0x0, 0x0}}, - {name: "XORQ/c=2147483647/dst=BX", inst: XORQ, c: 0x7fffffff, dstReg: RegBX, exp: []byte{0x48, 0x81, 0xf3, 0xff, 0xff, 0xff, 0x7f}}, - {name: "XORQ/c=-2147483648/dst=BX", inst: XORQ, c: -0x80000000, dstReg: RegBX, exp: []byte{0x48, 0x81, 0xf3, 0x0, 0x0, 0x0, 0x80}}, - {name: "XORQ/c=32767/dst=BX", inst: XORQ, c: 0x7fff, dstReg: RegBX, exp: []byte{0x48, 0x81, 0xf3, 0xff, 0x7f, 0x0, 0x0}}, - {name: "XORQ/c=4294967295/dst=BX", inst: XORQ, c: 0xffffffff, dstReg: RegBX, exp: []byte{0x48, 0x81, 0xf3, 0xff, 0xff, 0xff, 0xff}}, - {name: "XORQ/c=-32768/dst=BX", inst: XORQ, c: -0x8000, dstReg: RegBX, exp: []byte{0x48, 0x81, 0xf3, 0x0, 0x80, 0xff, 0xff}}, - {name: "XORQ/c=0/dst=R15", inst: XORQ, c: 0x0, dstReg: RegR15, exp: []byte{0x49, 0x83, 0xf7, 0x0}}, - {name: "XORQ/c=1/dst=R15", inst: XORQ, c: 0x1, dstReg: RegR15, exp: []byte{0x49, 0x83, 0xf7, 0x1}}, - {name: "XORQ/c=-1/dst=R15", inst: XORQ, c: -0x1, dstReg: RegR15, exp: []byte{0x49, 0x83, 0xf7, 0xff}}, - {name: "XORQ/c=11/dst=R15", inst: XORQ, c: 0xb, dstReg: RegR15, exp: []byte{0x49, 0x83, 0xf7, 0xb}}, - {name: "XORQ/c=-11/dst=R15", inst: XORQ, c: -0xb, dstReg: RegR15, exp: []byte{0x49, 0x83, 0xf7, 0xf5}}, - {name: "XORQ/c=1243/dst=R15", inst: XORQ, c: 0x4db, dstReg: RegR15, exp: []byte{0x49, 0x81, 0xf7, 0xdb, 0x4, 0x0, 0x0}}, - {name: "XORQ/c=-1234/dst=R15", inst: XORQ, c: -0x4d2, dstReg: RegR15, exp: []byte{0x49, 0x81, 0xf7, 0x2e, 0xfb, 0xff, 0xff}}, - {name: "XORQ/c=255/dst=R15", inst: XORQ, c: 0xff, dstReg: RegR15, exp: []byte{0x49, 0x81, 0xf7, 0xff, 0x0, 0x0, 0x0}}, - {name: "XORQ/c=2147483647/dst=R15", inst: XORQ, c: 0x7fffffff, dstReg: RegR15, exp: []byte{0x49, 0x81, 0xf7, 0xff, 0xff, 0xff, 0x7f}}, - {name: "XORQ/c=-2147483648/dst=R15", inst: XORQ, c: -0x80000000, dstReg: RegR15, exp: []byte{0x49, 0x81, 0xf7, 0x0, 0x0, 0x0, 0x80}}, - {name: "XORQ/c=32767/dst=R15", inst: XORQ, c: 0x7fff, dstReg: RegR15, exp: []byte{0x49, 0x81, 0xf7, 0xff, 0x7f, 0x0, 0x0}}, - {name: "XORQ/c=4294967295/dst=R15", inst: XORQ, c: 0xffffffff, dstReg: RegR15, exp: []byte{0x49, 0x81, 0xf7, 0xff, 0xff, 0xff, 0xff}}, - {name: "XORQ/c=-32768/dst=R15", inst: XORQ, c: -0x8000, dstReg: RegR15, exp: []byte{0x49, 0x81, 0xf7, 0x0, 0x80, 0xff, 0xff}}, - {name: "PSLLD/c=0/dst=X3", inst: PSLLD, c: 0x0, dstReg: RegX3, exp: []byte{0x66, 0xf, 0x72, 0xf3, 0x0}}, - {name: "PSLLD/c=1/dst=X3", inst: PSLLD, c: 0x1, dstReg: RegX3, exp: []byte{0x66, 0xf, 0x72, 0xf3, 0x1}}, - {name: "PSLLD/c=-1/dst=X3", inst: PSLLD, c: -0x1, dstReg: RegX3, exp: []byte{0x66, 0xf, 0x72, 0xf3, 0xff}}, - {name: "PSLLD/c=127/dst=X3", inst: PSLLD, c: 0x7f, dstReg: RegX3, exp: []byte{0x66, 0xf, 0x72, 0xf3, 0x7f}}, - {name: "PSLLD/c=-128/dst=X3", inst: PSLLD, c: -0x80, dstReg: RegX3, exp: []byte{0x66, 0xf, 0x72, 0xf3, 0x80}}, - {name: "PSLLD/c=0/dst=X15", inst: PSLLD, c: 0x0, dstReg: RegX15, exp: []byte{0x66, 0x41, 0xf, 0x72, 0xf7, 0x0}}, - {name: "PSLLD/c=1/dst=X15", inst: PSLLD, c: 0x1, dstReg: RegX15, exp: []byte{0x66, 0x41, 0xf, 0x72, 0xf7, 0x1}}, - {name: "PSLLD/c=-1/dst=X15", inst: PSLLD, c: -0x1, dstReg: RegX15, exp: []byte{0x66, 0x41, 0xf, 0x72, 0xf7, 0xff}}, - {name: "PSLLD/c=127/dst=X15", inst: PSLLD, c: 0x7f, dstReg: RegX15, exp: []byte{0x66, 0x41, 0xf, 0x72, 0xf7, 0x7f}}, - {name: "PSLLD/c=-128/dst=X15", inst: PSLLD, c: -0x80, dstReg: RegX15, exp: []byte{0x66, 0x41, 0xf, 0x72, 0xf7, 0x80}}, - {name: "PSLLQ/c=0/dst=X3", inst: PSLLQ, c: 0x0, dstReg: RegX3, exp: []byte{0x66, 0xf, 0x73, 0xf3, 0x0}}, - {name: "PSLLQ/c=1/dst=X3", inst: PSLLQ, c: 0x1, dstReg: RegX3, exp: []byte{0x66, 0xf, 0x73, 0xf3, 0x1}}, - {name: "PSLLQ/c=-1/dst=X3", inst: PSLLQ, c: -0x1, dstReg: RegX3, exp: []byte{0x66, 0xf, 0x73, 0xf3, 0xff}}, - {name: "PSLLQ/c=127/dst=X3", inst: PSLLQ, c: 0x7f, dstReg: RegX3, exp: []byte{0x66, 0xf, 0x73, 0xf3, 0x7f}}, - {name: "PSLLQ/c=-128/dst=X3", inst: PSLLQ, c: -0x80, dstReg: RegX3, exp: []byte{0x66, 0xf, 0x73, 0xf3, 0x80}}, - {name: "PSLLQ/c=0/dst=X15", inst: PSLLQ, c: 0x0, dstReg: RegX15, exp: []byte{0x66, 0x41, 0xf, 0x73, 0xf7, 0x0}}, - {name: "PSLLQ/c=1/dst=X15", inst: PSLLQ, c: 0x1, dstReg: RegX15, exp: []byte{0x66, 0x41, 0xf, 0x73, 0xf7, 0x1}}, - {name: "PSLLQ/c=-1/dst=X15", inst: PSLLQ, c: -0x1, dstReg: RegX15, exp: []byte{0x66, 0x41, 0xf, 0x73, 0xf7, 0xff}}, - {name: "PSLLQ/c=127/dst=X15", inst: PSLLQ, c: 0x7f, dstReg: RegX15, exp: []byte{0x66, 0x41, 0xf, 0x73, 0xf7, 0x7f}}, - {name: "PSLLQ/c=-128/dst=X15", inst: PSLLQ, c: -0x80, dstReg: RegX15, exp: []byte{0x66, 0x41, 0xf, 0x73, 0xf7, 0x80}}, - {name: "PSLLD/c=0/dst=X3", inst: PSLLD, c: 0x0, dstReg: RegX3, exp: []byte{0x66, 0xf, 0x72, 0xf3, 0x0}}, - {name: "PSLLD/c=1/dst=X3", inst: PSLLD, c: 0x1, dstReg: RegX3, exp: []byte{0x66, 0xf, 0x72, 0xf3, 0x1}}, - {name: "PSLLD/c=-1/dst=X3", inst: PSLLD, c: -0x1, dstReg: RegX3, exp: []byte{0x66, 0xf, 0x72, 0xf3, 0xff}}, - {name: "PSLLD/c=127/dst=X3", inst: PSLLD, c: 0x7f, dstReg: RegX3, exp: []byte{0x66, 0xf, 0x72, 0xf3, 0x7f}}, - {name: "PSLLD/c=-128/dst=X3", inst: PSLLD, c: -0x80, dstReg: RegX3, exp: []byte{0x66, 0xf, 0x72, 0xf3, 0x80}}, - {name: "PSLLD/c=0/dst=X15", inst: PSLLD, c: 0x0, dstReg: RegX15, exp: []byte{0x66, 0x41, 0xf, 0x72, 0xf7, 0x0}}, - {name: "PSLLD/c=1/dst=X15", inst: PSLLD, c: 0x1, dstReg: RegX15, exp: []byte{0x66, 0x41, 0xf, 0x72, 0xf7, 0x1}}, - {name: "PSLLD/c=-1/dst=X15", inst: PSLLD, c: -0x1, dstReg: RegX15, exp: []byte{0x66, 0x41, 0xf, 0x72, 0xf7, 0xff}}, - {name: "PSLLD/c=127/dst=X15", inst: PSLLD, c: 0x7f, dstReg: RegX15, exp: []byte{0x66, 0x41, 0xf, 0x72, 0xf7, 0x7f}}, - {name: "PSLLD/c=-128/dst=X15", inst: PSLLD, c: -0x80, dstReg: RegX15, exp: []byte{0x66, 0x41, 0xf, 0x72, 0xf7, 0x80}}, - {name: "PSRLQ/c=0/dst=X3", inst: PSRLQ, c: 0x0, dstReg: RegX3, exp: []byte{0x66, 0xf, 0x73, 0xd3, 0x0}}, - {name: "PSRLQ/c=1/dst=X3", inst: PSRLQ, c: 0x1, dstReg: RegX3, exp: []byte{0x66, 0xf, 0x73, 0xd3, 0x1}}, - {name: "PSRLQ/c=-1/dst=X3", inst: PSRLQ, c: -0x1, dstReg: RegX3, exp: []byte{0x66, 0xf, 0x73, 0xd3, 0xff}}, - {name: "PSRLQ/c=127/dst=X3", inst: PSRLQ, c: 0x7f, dstReg: RegX3, exp: []byte{0x66, 0xf, 0x73, 0xd3, 0x7f}}, - {name: "PSRLQ/c=-128/dst=X3", inst: PSRLQ, c: -0x80, dstReg: RegX3, exp: []byte{0x66, 0xf, 0x73, 0xd3, 0x80}}, - {name: "PSRLQ/c=0/dst=X15", inst: PSRLQ, c: 0x0, dstReg: RegX15, exp: []byte{0x66, 0x41, 0xf, 0x73, 0xd7, 0x0}}, - {name: "PSRLQ/c=1/dst=X15", inst: PSRLQ, c: 0x1, dstReg: RegX15, exp: []byte{0x66, 0x41, 0xf, 0x73, 0xd7, 0x1}}, - {name: "PSRLQ/c=-1/dst=X15", inst: PSRLQ, c: -0x1, dstReg: RegX15, exp: []byte{0x66, 0x41, 0xf, 0x73, 0xd7, 0xff}}, - {name: "PSRLQ/c=127/dst=X15", inst: PSRLQ, c: 0x7f, dstReg: RegX15, exp: []byte{0x66, 0x41, 0xf, 0x73, 0xd7, 0x7f}}, - {name: "PSRLQ/c=-128/dst=X15", inst: PSRLQ, c: -0x80, dstReg: RegX15, exp: []byte{0x66, 0x41, 0xf, 0x73, 0xd7, 0x80}}, - {name: "TESTQ/c=7/dst=R8", inst: TESTQ, c: 0x7, dstReg: RegR8, exp: []byte{0x49, 0xf7, 0xc0, 0x07, 0x00, 0x00, 0x00}}, - {name: "TESTQ/c=17/dst=BX", inst: TESTQ, c: 0x11, dstReg: RegBX, exp: []byte{0x48, 0xf7, 0xc3, 0x11, 0x00, 0x00, 0x00}}, - } - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - for _, tc := range tests { - a := NewAssembler() - buf := code.NextCodeSection() - err := a.encodeConstToRegister(buf, &nodeImpl{ - instruction: tc.inst, - types: operandTypesConstToRegister, srcConst: tc.c, dstReg: tc.dstReg, - }) - require.NoError(t, err, tc.name) - require.Equal(t, tc.exp, buf.Bytes(), tc.name) - } -} - -func TestAssemblerImpl_encodeReadInstructionAddress(t *testing.T) { - t.Run("ok", func(t *testing.T) { - const targetBeforeInstruction = RET - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - for _, tc := range []struct { - name string - dst asm.Register - exp []byte - }{ - {name: "AX", dst: RegAX, exp: []byte{0x48, 0x8d, 0x5, 0x2, 0x0, 0x0, 0x0, 0x99, 0xc3, 0x99}}, - {name: "R8", dst: RegR8, exp: []byte{0x4c, 0x8d, 0x5, 0x2, 0x0, 0x0, 0x0, 0x99, 0xc3, 0x99}}, - } { - a := NewAssembler() - - // Setup target. - a.CompileReadInstructionAddress(tc.dst, targetBeforeInstruction) - a.CompileStandAlone(CDQ) // Dummy. - a.CompileStandAlone(targetBeforeInstruction) - a.CompileStandAlone(CDQ) // Target. - - buf := code.NextCodeSection() - err := a.Assemble(buf) - require.NoError(t, err, tc.name) - - actual := buf.Bytes() - require.Equal(t, tc.exp, actual, tc.name) - } - }) - t.Run("not found", func(t *testing.T) { - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - a := NewAssembler() - a.CompileReadInstructionAddress(RegR10, NOP) - a.CompileStandAlone(CDQ) - - buf := code.NextCodeSection() - err := a.Assemble(buf) - require.EqualError(t, err, "BUG: target instruction not found for read instruction address") - }) - t.Run("offset too large", func(t *testing.T) { - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - a := NewAssembler() - a.CompileReadInstructionAddress(RegR10, RET) - a.CompileStandAlone(RET) - a.CompileStandAlone(CDQ) - - buf := code.NextCodeSection() - - for n := a.root; n != nil; n = n.next { - n.offsetInBinary = uint64(buf.Len()) - - err := a.encodeNode(buf, n) - require.NoError(t, err) - } - - targetNode := a.current - targetNode.offsetInBinary = uint64(math.MaxInt64) - - n := a.readInstructionAddressNodes[0] - err := a.finalizeReadInstructionAddressNode(nil, n) - require.EqualError(t, err, "BUG: too large offset for LEAQ instruction") - }) -} - -func TestAssemblerImpl_encodeRegisterToConst(t *testing.T) { - t.Run("error", func(t *testing.T) { - tests := []struct { - n *nodeImpl - expErr string - }{ - { - n: &nodeImpl{instruction: ADDL, types: operandTypesRegisterToConst, srcReg: RegAX}, - expErr: "ADDL is unsupported for RegisterToConst type", - }, - } - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - for _, tc := range tests { - a := NewAssembler() - buf := code.NextCodeSection() - err := a.encodeRegisterToNone(buf, tc.n) - require.EqualError(t, err, tc.expErr) - } - }) - - tests := []struct { - name string - c int64 - inst asm.Instruction - srcReg asm.Register - exp []byte - }{ - {name: "CMPL/src=AX/c=0x0", inst: CMPL, srcReg: RegAX, c: 0x0, exp: []byte{0x83, 0xf8, 0x0}}, - {name: "CMPL/src=AX/c=0x1", inst: CMPL, srcReg: RegAX, c: 0x1, exp: []byte{0x83, 0xf8, 0x1}}, - {name: "CMPL/src=AX/c=-0x1", inst: CMPL, srcReg: RegAX, c: -0x1, exp: []byte{0x83, 0xf8, 0xff}}, - {name: "CMPL/src=AX/c=0x4db", inst: CMPL, srcReg: RegAX, c: 0x4db, exp: []byte{0x3d, 0xdb, 0x4, 0x0, 0x0}}, - {name: "CMPL/src=AX/c=-0x4d2", inst: CMPL, srcReg: RegAX, c: -0x4d2, exp: []byte{0x3d, 0x2e, 0xfb, 0xff, 0xff}}, - {name: "CMPL/src=AX/c=0x7fffffff", inst: CMPL, srcReg: RegAX, c: 0x7fffffff, exp: []byte{0x3d, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPL/src=AX/c=-0x80000000", inst: CMPL, srcReg: RegAX, c: -0x80000000, exp: []byte{0x3d, 0x0, 0x0, 0x0, 0x80}}, - {name: "CMPL/src=AX/c=0x7fff", inst: CMPL, srcReg: RegAX, c: 0x7fff, exp: []byte{0x3d, 0xff, 0x7f, 0x0, 0x0}}, - {name: "CMPL/src=AX/c=-0x8000", inst: CMPL, srcReg: RegAX, c: -0x8000, exp: []byte{0x3d, 0x0, 0x80, 0xff, 0xff}}, - {name: "CMPL/src=BX/c=0x0", inst: CMPL, srcReg: RegBX, c: 0x0, exp: []byte{0x83, 0xfb, 0x0}}, - {name: "CMPL/src=BX/c=0x1", inst: CMPL, srcReg: RegBX, c: 0x1, exp: []byte{0x83, 0xfb, 0x1}}, - {name: "CMPL/src=BX/c=-0x1", inst: CMPL, srcReg: RegBX, c: -0x1, exp: []byte{0x83, 0xfb, 0xff}}, - {name: "CMPL/src=BX/c=0x4db", inst: CMPL, srcReg: RegBX, c: 0x4db, exp: []byte{0x81, 0xfb, 0xdb, 0x4, 0x0, 0x0}}, - {name: "CMPL/src=BX/c=-0x4d2", inst: CMPL, srcReg: RegBX, c: -0x4d2, exp: []byte{0x81, 0xfb, 0x2e, 0xfb, 0xff, 0xff}}, - {name: "CMPL/src=BX/c=0x7fffffff", inst: CMPL, srcReg: RegBX, c: 0x7fffffff, exp: []byte{0x81, 0xfb, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPL/src=BX/c=-0x80000000", inst: CMPL, srcReg: RegBX, c: -0x80000000, exp: []byte{0x81, 0xfb, 0x0, 0x0, 0x0, 0x80}}, - {name: "CMPL/src=BX/c=0x7fff", inst: CMPL, srcReg: RegBX, c: 0x7fff, exp: []byte{0x81, 0xfb, 0xff, 0x7f, 0x0, 0x0}}, - {name: "CMPL/src=BX/c=-0x8000", inst: CMPL, srcReg: RegBX, c: -0x8000, exp: []byte{0x81, 0xfb, 0x0, 0x80, 0xff, 0xff}}, - {name: "CMPL/src=SP/c=0x0", inst: CMPL, srcReg: RegSP, c: 0x0, exp: []byte{0x83, 0xfc, 0x0}}, - {name: "CMPL/src=SP/c=0x1", inst: CMPL, srcReg: RegSP, c: 0x1, exp: []byte{0x83, 0xfc, 0x1}}, - {name: "CMPL/src=SP/c=-0x1", inst: CMPL, srcReg: RegSP, c: -0x1, exp: []byte{0x83, 0xfc, 0xff}}, - {name: "CMPL/src=SP/c=0x4db", inst: CMPL, srcReg: RegSP, c: 0x4db, exp: []byte{0x81, 0xfc, 0xdb, 0x4, 0x0, 0x0}}, - {name: "CMPL/src=SP/c=-0x4d2", inst: CMPL, srcReg: RegSP, c: -0x4d2, exp: []byte{0x81, 0xfc, 0x2e, 0xfb, 0xff, 0xff}}, - {name: "CMPL/src=SP/c=0x7fffffff", inst: CMPL, srcReg: RegSP, c: 0x7fffffff, exp: []byte{0x81, 0xfc, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPL/src=SP/c=-0x80000000", inst: CMPL, srcReg: RegSP, c: -0x80000000, exp: []byte{0x81, 0xfc, 0x0, 0x0, 0x0, 0x80}}, - {name: "CMPL/src=SP/c=0x7fff", inst: CMPL, srcReg: RegSP, c: 0x7fff, exp: []byte{0x81, 0xfc, 0xff, 0x7f, 0x0, 0x0}}, - {name: "CMPL/src=SP/c=-0x8000", inst: CMPL, srcReg: RegSP, c: -0x8000, exp: []byte{0x81, 0xfc, 0x0, 0x80, 0xff, 0xff}}, - {name: "CMPL/src=BP/c=0x0", inst: CMPL, srcReg: RegBP, c: 0x0, exp: []byte{0x83, 0xfd, 0x0}}, - {name: "CMPL/src=BP/c=0x1", inst: CMPL, srcReg: RegBP, c: 0x1, exp: []byte{0x83, 0xfd, 0x1}}, - {name: "CMPL/src=BP/c=-0x1", inst: CMPL, srcReg: RegBP, c: -0x1, exp: []byte{0x83, 0xfd, 0xff}}, - {name: "CMPL/src=BP/c=0x4db", inst: CMPL, srcReg: RegBP, c: 0x4db, exp: []byte{0x81, 0xfd, 0xdb, 0x4, 0x0, 0x0}}, - {name: "CMPL/src=BP/c=-0x4d2", inst: CMPL, srcReg: RegBP, c: -0x4d2, exp: []byte{0x81, 0xfd, 0x2e, 0xfb, 0xff, 0xff}}, - {name: "CMPL/src=BP/c=0x7fffffff", inst: CMPL, srcReg: RegBP, c: 0x7fffffff, exp: []byte{0x81, 0xfd, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPL/src=BP/c=-0x80000000", inst: CMPL, srcReg: RegBP, c: -0x80000000, exp: []byte{0x81, 0xfd, 0x0, 0x0, 0x0, 0x80}}, - {name: "CMPL/src=BP/c=0x7fff", inst: CMPL, srcReg: RegBP, c: 0x7fff, exp: []byte{0x81, 0xfd, 0xff, 0x7f, 0x0, 0x0}}, - {name: "CMPL/src=BP/c=-0x8000", inst: CMPL, srcReg: RegBP, c: -0x8000, exp: []byte{0x81, 0xfd, 0x0, 0x80, 0xff, 0xff}}, - {name: "CMPL/src=SI/c=0x0", inst: CMPL, srcReg: RegSI, c: 0x0, exp: []byte{0x83, 0xfe, 0x0}}, - {name: "CMPL/src=SI/c=0x1", inst: CMPL, srcReg: RegSI, c: 0x1, exp: []byte{0x83, 0xfe, 0x1}}, - {name: "CMPL/src=SI/c=-0x1", inst: CMPL, srcReg: RegSI, c: -0x1, exp: []byte{0x83, 0xfe, 0xff}}, - {name: "CMPL/src=SI/c=0x4db", inst: CMPL, srcReg: RegSI, c: 0x4db, exp: []byte{0x81, 0xfe, 0xdb, 0x4, 0x0, 0x0}}, - {name: "CMPL/src=SI/c=-0x4d2", inst: CMPL, srcReg: RegSI, c: -0x4d2, exp: []byte{0x81, 0xfe, 0x2e, 0xfb, 0xff, 0xff}}, - {name: "CMPL/src=SI/c=0x7fffffff", inst: CMPL, srcReg: RegSI, c: 0x7fffffff, exp: []byte{0x81, 0xfe, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPL/src=SI/c=-0x80000000", inst: CMPL, srcReg: RegSI, c: -0x80000000, exp: []byte{0x81, 0xfe, 0x0, 0x0, 0x0, 0x80}}, - {name: "CMPL/src=SI/c=0x7fff", inst: CMPL, srcReg: RegSI, c: 0x7fff, exp: []byte{0x81, 0xfe, 0xff, 0x7f, 0x0, 0x0}}, - {name: "CMPL/src=SI/c=-0x8000", inst: CMPL, srcReg: RegSI, c: -0x8000, exp: []byte{0x81, 0xfe, 0x0, 0x80, 0xff, 0xff}}, - {name: "CMPL/src=DI/c=0x0", inst: CMPL, srcReg: RegDI, c: 0x0, exp: []byte{0x83, 0xff, 0x0}}, - {name: "CMPL/src=DI/c=0x1", inst: CMPL, srcReg: RegDI, c: 0x1, exp: []byte{0x83, 0xff, 0x1}}, - {name: "CMPL/src=DI/c=-0x1", inst: CMPL, srcReg: RegDI, c: -0x1, exp: []byte{0x83, 0xff, 0xff}}, - {name: "CMPL/src=DI/c=0x4db", inst: CMPL, srcReg: RegDI, c: 0x4db, exp: []byte{0x81, 0xff, 0xdb, 0x4, 0x0, 0x0}}, - {name: "CMPL/src=DI/c=-0x4d2", inst: CMPL, srcReg: RegDI, c: -0x4d2, exp: []byte{0x81, 0xff, 0x2e, 0xfb, 0xff, 0xff}}, - {name: "CMPL/src=DI/c=0x7fffffff", inst: CMPL, srcReg: RegDI, c: 0x7fffffff, exp: []byte{0x81, 0xff, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPL/src=DI/c=-0x80000000", inst: CMPL, srcReg: RegDI, c: -0x80000000, exp: []byte{0x81, 0xff, 0x0, 0x0, 0x0, 0x80}}, - {name: "CMPL/src=DI/c=0x7fff", inst: CMPL, srcReg: RegDI, c: 0x7fff, exp: []byte{0x81, 0xff, 0xff, 0x7f, 0x0, 0x0}}, - {name: "CMPL/src=DI/c=-0x8000", inst: CMPL, srcReg: RegDI, c: -0x8000, exp: []byte{0x81, 0xff, 0x0, 0x80, 0xff, 0xff}}, - {name: "CMPL/src=R8/c=0x0", inst: CMPL, srcReg: RegR8, c: 0x0, exp: []byte{0x41, 0x83, 0xf8, 0x0}}, - {name: "CMPL/src=R8/c=0x1", inst: CMPL, srcReg: RegR8, c: 0x1, exp: []byte{0x41, 0x83, 0xf8, 0x1}}, - {name: "CMPL/src=R8/c=-0x1", inst: CMPL, srcReg: RegR8, c: -0x1, exp: []byte{0x41, 0x83, 0xf8, 0xff}}, - {name: "CMPL/src=R8/c=0x4db", inst: CMPL, srcReg: RegR8, c: 0x4db, exp: []byte{0x41, 0x81, 0xf8, 0xdb, 0x4, 0x0, 0x0}}, - {name: "CMPL/src=R8/c=-0x4d2", inst: CMPL, srcReg: RegR8, c: -0x4d2, exp: []byte{0x41, 0x81, 0xf8, 0x2e, 0xfb, 0xff, 0xff}}, - {name: "CMPL/src=R8/c=0x7fffffff", inst: CMPL, srcReg: RegR8, c: 0x7fffffff, exp: []byte{0x41, 0x81, 0xf8, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPL/src=R8/c=-0x80000000", inst: CMPL, srcReg: RegR8, c: -0x80000000, exp: []byte{0x41, 0x81, 0xf8, 0x0, 0x0, 0x0, 0x80}}, - {name: "CMPL/src=R8/c=0x7fff", inst: CMPL, srcReg: RegR8, c: 0x7fff, exp: []byte{0x41, 0x81, 0xf8, 0xff, 0x7f, 0x0, 0x0}}, - {name: "CMPL/src=R8/c=-0x8000", inst: CMPL, srcReg: RegR8, c: -0x8000, exp: []byte{0x41, 0x81, 0xf8, 0x0, 0x80, 0xff, 0xff}}, - {name: "CMPL/src=R9/c=0x0", inst: CMPL, srcReg: RegR9, c: 0x0, exp: []byte{0x41, 0x83, 0xf9, 0x0}}, - {name: "CMPL/src=R9/c=0x1", inst: CMPL, srcReg: RegR9, c: 0x1, exp: []byte{0x41, 0x83, 0xf9, 0x1}}, - {name: "CMPL/src=R9/c=-0x1", inst: CMPL, srcReg: RegR9, c: -0x1, exp: []byte{0x41, 0x83, 0xf9, 0xff}}, - {name: "CMPL/src=R9/c=0x4db", inst: CMPL, srcReg: RegR9, c: 0x4db, exp: []byte{0x41, 0x81, 0xf9, 0xdb, 0x4, 0x0, 0x0}}, - {name: "CMPL/src=R9/c=-0x4d2", inst: CMPL, srcReg: RegR9, c: -0x4d2, exp: []byte{0x41, 0x81, 0xf9, 0x2e, 0xfb, 0xff, 0xff}}, - {name: "CMPL/src=R9/c=0x7fffffff", inst: CMPL, srcReg: RegR9, c: 0x7fffffff, exp: []byte{0x41, 0x81, 0xf9, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPL/src=R9/c=-0x80000000", inst: CMPL, srcReg: RegR9, c: -0x80000000, exp: []byte{0x41, 0x81, 0xf9, 0x0, 0x0, 0x0, 0x80}}, - {name: "CMPL/src=R9/c=0x7fff", inst: CMPL, srcReg: RegR9, c: 0x7fff, exp: []byte{0x41, 0x81, 0xf9, 0xff, 0x7f, 0x0, 0x0}}, - {name: "CMPL/src=R9/c=-0x8000", inst: CMPL, srcReg: RegR9, c: -0x8000, exp: []byte{0x41, 0x81, 0xf9, 0x0, 0x80, 0xff, 0xff}}, - {name: "CMPL/src=R13/c=0x0", inst: CMPL, srcReg: RegR13, c: 0x0, exp: []byte{0x41, 0x83, 0xfd, 0x0}}, - {name: "CMPL/src=R13/c=0x1", inst: CMPL, srcReg: RegR13, c: 0x1, exp: []byte{0x41, 0x83, 0xfd, 0x1}}, - {name: "CMPL/src=R13/c=-0x1", inst: CMPL, srcReg: RegR13, c: -0x1, exp: []byte{0x41, 0x83, 0xfd, 0xff}}, - {name: "CMPL/src=R13/c=0x4db", inst: CMPL, srcReg: RegR13, c: 0x4db, exp: []byte{0x41, 0x81, 0xfd, 0xdb, 0x4, 0x0, 0x0}}, - {name: "CMPL/src=R13/c=-0x4d2", inst: CMPL, srcReg: RegR13, c: -0x4d2, exp: []byte{0x41, 0x81, 0xfd, 0x2e, 0xfb, 0xff, 0xff}}, - {name: "CMPL/src=R13/c=0x7fffffff", inst: CMPL, srcReg: RegR13, c: 0x7fffffff, exp: []byte{0x41, 0x81, 0xfd, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPL/src=R13/c=-0x80000000", inst: CMPL, srcReg: RegR13, c: -0x80000000, exp: []byte{0x41, 0x81, 0xfd, 0x0, 0x0, 0x0, 0x80}}, - {name: "CMPL/src=R13/c=0x7fff", inst: CMPL, srcReg: RegR13, c: 0x7fff, exp: []byte{0x41, 0x81, 0xfd, 0xff, 0x7f, 0x0, 0x0}}, - {name: "CMPL/src=R13/c=-0x8000", inst: CMPL, srcReg: RegR13, c: -0x8000, exp: []byte{0x41, 0x81, 0xfd, 0x0, 0x80, 0xff, 0xff}}, - {name: "CMPL/src=R14/c=0x0", inst: CMPL, srcReg: RegR14, c: 0x0, exp: []byte{0x41, 0x83, 0xfe, 0x0}}, - {name: "CMPL/src=R14/c=0x1", inst: CMPL, srcReg: RegR14, c: 0x1, exp: []byte{0x41, 0x83, 0xfe, 0x1}}, - {name: "CMPL/src=R14/c=-0x1", inst: CMPL, srcReg: RegR14, c: -0x1, exp: []byte{0x41, 0x83, 0xfe, 0xff}}, - {name: "CMPL/src=R14/c=0x4db", inst: CMPL, srcReg: RegR14, c: 0x4db, exp: []byte{0x41, 0x81, 0xfe, 0xdb, 0x4, 0x0, 0x0}}, - {name: "CMPL/src=R14/c=-0x4d2", inst: CMPL, srcReg: RegR14, c: -0x4d2, exp: []byte{0x41, 0x81, 0xfe, 0x2e, 0xfb, 0xff, 0xff}}, - {name: "CMPL/src=R14/c=0x7fffffff", inst: CMPL, srcReg: RegR14, c: 0x7fffffff, exp: []byte{0x41, 0x81, 0xfe, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPL/src=R14/c=-0x80000000", inst: CMPL, srcReg: RegR14, c: -0x80000000, exp: []byte{0x41, 0x81, 0xfe, 0x0, 0x0, 0x0, 0x80}}, - {name: "CMPL/src=R14/c=0x7fff", inst: CMPL, srcReg: RegR14, c: 0x7fff, exp: []byte{0x41, 0x81, 0xfe, 0xff, 0x7f, 0x0, 0x0}}, - {name: "CMPL/src=R14/c=-0x8000", inst: CMPL, srcReg: RegR14, c: -0x8000, exp: []byte{0x41, 0x81, 0xfe, 0x0, 0x80, 0xff, 0xff}}, - {name: "CMPL/src=R15/c=0x0", inst: CMPL, srcReg: RegR15, c: 0x0, exp: []byte{0x41, 0x83, 0xff, 0x0}}, - {name: "CMPL/src=R15/c=0x1", inst: CMPL, srcReg: RegR15, c: 0x1, exp: []byte{0x41, 0x83, 0xff, 0x1}}, - {name: "CMPL/src=R15/c=-0x1", inst: CMPL, srcReg: RegR15, c: -0x1, exp: []byte{0x41, 0x83, 0xff, 0xff}}, - {name: "CMPL/src=R15/c=0x4db", inst: CMPL, srcReg: RegR15, c: 0x4db, exp: []byte{0x41, 0x81, 0xff, 0xdb, 0x4, 0x0, 0x0}}, - {name: "CMPL/src=R15/c=-0x4d2", inst: CMPL, srcReg: RegR15, c: -0x4d2, exp: []byte{0x41, 0x81, 0xff, 0x2e, 0xfb, 0xff, 0xff}}, - {name: "CMPL/src=R15/c=0x7fffffff", inst: CMPL, srcReg: RegR15, c: 0x7fffffff, exp: []byte{0x41, 0x81, 0xff, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPL/src=R15/c=-0x80000000", inst: CMPL, srcReg: RegR15, c: -0x80000000, exp: []byte{0x41, 0x81, 0xff, 0x0, 0x0, 0x0, 0x80}}, - {name: "CMPL/src=R15/c=0x7fff", inst: CMPL, srcReg: RegR15, c: 0x7fff, exp: []byte{0x41, 0x81, 0xff, 0xff, 0x7f, 0x0, 0x0}}, - {name: "CMPL/src=R15/c=-0x8000", inst: CMPL, srcReg: RegR15, c: -0x8000, exp: []byte{0x41, 0x81, 0xff, 0x0, 0x80, 0xff, 0xff}}, - {name: "CMPQ/src=AX/c=0x0", inst: CMPQ, srcReg: RegAX, c: 0x0, exp: []byte{0x48, 0x83, 0xf8, 0x0}}, - {name: "CMPQ/src=AX/c=0x1", inst: CMPQ, srcReg: RegAX, c: 0x1, exp: []byte{0x48, 0x83, 0xf8, 0x1}}, - {name: "CMPQ/src=AX/c=-0x1", inst: CMPQ, srcReg: RegAX, c: -0x1, exp: []byte{0x48, 0x83, 0xf8, 0xff}}, - {name: "CMPQ/src=AX/c=0x4db", inst: CMPQ, srcReg: RegAX, c: 0x4db, exp: []byte{0x48, 0x3d, 0xdb, 0x4, 0x0, 0x0}}, - {name: "CMPQ/src=AX/c=-0x4d2", inst: CMPQ, srcReg: RegAX, c: -0x4d2, exp: []byte{0x48, 0x3d, 0x2e, 0xfb, 0xff, 0xff}}, - {name: "CMPQ/src=AX/c=0x7fffffff", inst: CMPQ, srcReg: RegAX, c: 0x7fffffff, exp: []byte{0x48, 0x3d, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPQ/src=AX/c=-0x80000000", inst: CMPQ, srcReg: RegAX, c: -0x80000000, exp: []byte{0x48, 0x3d, 0x0, 0x0, 0x0, 0x80}}, - {name: "CMPQ/src=AX/c=0x7fff", inst: CMPQ, srcReg: RegAX, c: 0x7fff, exp: []byte{0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0}}, - {name: "CMPQ/src=AX/c=-0x8000", inst: CMPQ, srcReg: RegAX, c: -0x8000, exp: []byte{0x48, 0x3d, 0x0, 0x80, 0xff, 0xff}}, - {name: "CMPQ/src=BX/c=0x0", inst: CMPQ, srcReg: RegBX, c: 0x0, exp: []byte{0x48, 0x83, 0xfb, 0x0}}, - {name: "CMPQ/src=BX/c=0x1", inst: CMPQ, srcReg: RegBX, c: 0x1, exp: []byte{0x48, 0x83, 0xfb, 0x1}}, - {name: "CMPQ/src=BX/c=-0x1", inst: CMPQ, srcReg: RegBX, c: -0x1, exp: []byte{0x48, 0x83, 0xfb, 0xff}}, - {name: "CMPQ/src=BX/c=0x4db", inst: CMPQ, srcReg: RegBX, c: 0x4db, exp: []byte{0x48, 0x81, 0xfb, 0xdb, 0x4, 0x0, 0x0}}, - {name: "CMPQ/src=BX/c=-0x4d2", inst: CMPQ, srcReg: RegBX, c: -0x4d2, exp: []byte{0x48, 0x81, 0xfb, 0x2e, 0xfb, 0xff, 0xff}}, - {name: "CMPQ/src=BX/c=0x7fffffff", inst: CMPQ, srcReg: RegBX, c: 0x7fffffff, exp: []byte{0x48, 0x81, 0xfb, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPQ/src=BX/c=-0x80000000", inst: CMPQ, srcReg: RegBX, c: -0x80000000, exp: []byte{0x48, 0x81, 0xfb, 0x0, 0x0, 0x0, 0x80}}, - {name: "CMPQ/src=BX/c=0x7fff", inst: CMPQ, srcReg: RegBX, c: 0x7fff, exp: []byte{0x48, 0x81, 0xfb, 0xff, 0x7f, 0x0, 0x0}}, - {name: "CMPQ/src=BX/c=-0x8000", inst: CMPQ, srcReg: RegBX, c: -0x8000, exp: []byte{0x48, 0x81, 0xfb, 0x0, 0x80, 0xff, 0xff}}, - {name: "CMPQ/src=SP/c=0x0", inst: CMPQ, srcReg: RegSP, c: 0x0, exp: []byte{0x48, 0x83, 0xfc, 0x0}}, - {name: "CMPQ/src=SP/c=0x1", inst: CMPQ, srcReg: RegSP, c: 0x1, exp: []byte{0x48, 0x83, 0xfc, 0x1}}, - {name: "CMPQ/src=SP/c=-0x1", inst: CMPQ, srcReg: RegSP, c: -0x1, exp: []byte{0x48, 0x83, 0xfc, 0xff}}, - {name: "CMPQ/src=SP/c=0x4db", inst: CMPQ, srcReg: RegSP, c: 0x4db, exp: []byte{0x48, 0x81, 0xfc, 0xdb, 0x4, 0x0, 0x0}}, - {name: "CMPQ/src=SP/c=-0x4d2", inst: CMPQ, srcReg: RegSP, c: -0x4d2, exp: []byte{0x48, 0x81, 0xfc, 0x2e, 0xfb, 0xff, 0xff}}, - {name: "CMPQ/src=SP/c=0x7fffffff", inst: CMPQ, srcReg: RegSP, c: 0x7fffffff, exp: []byte{0x48, 0x81, 0xfc, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPQ/src=SP/c=-0x80000000", inst: CMPQ, srcReg: RegSP, c: -0x80000000, exp: []byte{0x48, 0x81, 0xfc, 0x0, 0x0, 0x0, 0x80}}, - {name: "CMPQ/src=SP/c=0x7fff", inst: CMPQ, srcReg: RegSP, c: 0x7fff, exp: []byte{0x48, 0x81, 0xfc, 0xff, 0x7f, 0x0, 0x0}}, - {name: "CMPQ/src=SP/c=-0x8000", inst: CMPQ, srcReg: RegSP, c: -0x8000, exp: []byte{0x48, 0x81, 0xfc, 0x0, 0x80, 0xff, 0xff}}, - {name: "CMPQ/src=BP/c=0x0", inst: CMPQ, srcReg: RegBP, c: 0x0, exp: []byte{0x48, 0x83, 0xfd, 0x0}}, - {name: "CMPQ/src=BP/c=0x1", inst: CMPQ, srcReg: RegBP, c: 0x1, exp: []byte{0x48, 0x83, 0xfd, 0x1}}, - {name: "CMPQ/src=BP/c=-0x1", inst: CMPQ, srcReg: RegBP, c: -0x1, exp: []byte{0x48, 0x83, 0xfd, 0xff}}, - {name: "CMPQ/src=BP/c=0x4db", inst: CMPQ, srcReg: RegBP, c: 0x4db, exp: []byte{0x48, 0x81, 0xfd, 0xdb, 0x4, 0x0, 0x0}}, - {name: "CMPQ/src=BP/c=-0x4d2", inst: CMPQ, srcReg: RegBP, c: -0x4d2, exp: []byte{0x48, 0x81, 0xfd, 0x2e, 0xfb, 0xff, 0xff}}, - {name: "CMPQ/src=BP/c=0x7fffffff", inst: CMPQ, srcReg: RegBP, c: 0x7fffffff, exp: []byte{0x48, 0x81, 0xfd, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPQ/src=BP/c=-0x80000000", inst: CMPQ, srcReg: RegBP, c: -0x80000000, exp: []byte{0x48, 0x81, 0xfd, 0x0, 0x0, 0x0, 0x80}}, - {name: "CMPQ/src=BP/c=0x7fff", inst: CMPQ, srcReg: RegBP, c: 0x7fff, exp: []byte{0x48, 0x81, 0xfd, 0xff, 0x7f, 0x0, 0x0}}, - {name: "CMPQ/src=BP/c=-0x8000", inst: CMPQ, srcReg: RegBP, c: -0x8000, exp: []byte{0x48, 0x81, 0xfd, 0x0, 0x80, 0xff, 0xff}}, - {name: "CMPQ/src=SI/c=0x0", inst: CMPQ, srcReg: RegSI, c: 0x0, exp: []byte{0x48, 0x83, 0xfe, 0x0}}, - {name: "CMPQ/src=SI/c=0x1", inst: CMPQ, srcReg: RegSI, c: 0x1, exp: []byte{0x48, 0x83, 0xfe, 0x1}}, - {name: "CMPQ/src=SI/c=-0x1", inst: CMPQ, srcReg: RegSI, c: -0x1, exp: []byte{0x48, 0x83, 0xfe, 0xff}}, - {name: "CMPQ/src=SI/c=0x4db", inst: CMPQ, srcReg: RegSI, c: 0x4db, exp: []byte{0x48, 0x81, 0xfe, 0xdb, 0x4, 0x0, 0x0}}, - {name: "CMPQ/src=SI/c=-0x4d2", inst: CMPQ, srcReg: RegSI, c: -0x4d2, exp: []byte{0x48, 0x81, 0xfe, 0x2e, 0xfb, 0xff, 0xff}}, - {name: "CMPQ/src=SI/c=0x7fffffff", inst: CMPQ, srcReg: RegSI, c: 0x7fffffff, exp: []byte{0x48, 0x81, 0xfe, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPQ/src=SI/c=-0x80000000", inst: CMPQ, srcReg: RegSI, c: -0x80000000, exp: []byte{0x48, 0x81, 0xfe, 0x0, 0x0, 0x0, 0x80}}, - {name: "CMPQ/src=SI/c=0x7fff", inst: CMPQ, srcReg: RegSI, c: 0x7fff, exp: []byte{0x48, 0x81, 0xfe, 0xff, 0x7f, 0x0, 0x0}}, - {name: "CMPQ/src=SI/c=-0x8000", inst: CMPQ, srcReg: RegSI, c: -0x8000, exp: []byte{0x48, 0x81, 0xfe, 0x0, 0x80, 0xff, 0xff}}, - {name: "CMPQ/src=DI/c=0x0", inst: CMPQ, srcReg: RegDI, c: 0x0, exp: []byte{0x48, 0x83, 0xff, 0x0}}, - {name: "CMPQ/src=DI/c=0x1", inst: CMPQ, srcReg: RegDI, c: 0x1, exp: []byte{0x48, 0x83, 0xff, 0x1}}, - {name: "CMPQ/src=DI/c=-0x1", inst: CMPQ, srcReg: RegDI, c: -0x1, exp: []byte{0x48, 0x83, 0xff, 0xff}}, - {name: "CMPQ/src=DI/c=0x4db", inst: CMPQ, srcReg: RegDI, c: 0x4db, exp: []byte{0x48, 0x81, 0xff, 0xdb, 0x4, 0x0, 0x0}}, - {name: "CMPQ/src=DI/c=-0x4d2", inst: CMPQ, srcReg: RegDI, c: -0x4d2, exp: []byte{0x48, 0x81, 0xff, 0x2e, 0xfb, 0xff, 0xff}}, - {name: "CMPQ/src=DI/c=0x7fffffff", inst: CMPQ, srcReg: RegDI, c: 0x7fffffff, exp: []byte{0x48, 0x81, 0xff, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPQ/src=DI/c=-0x80000000", inst: CMPQ, srcReg: RegDI, c: -0x80000000, exp: []byte{0x48, 0x81, 0xff, 0x0, 0x0, 0x0, 0x80}}, - {name: "CMPQ/src=DI/c=0x7fff", inst: CMPQ, srcReg: RegDI, c: 0x7fff, exp: []byte{0x48, 0x81, 0xff, 0xff, 0x7f, 0x0, 0x0}}, - {name: "CMPQ/src=DI/c=-0x8000", inst: CMPQ, srcReg: RegDI, c: -0x8000, exp: []byte{0x48, 0x81, 0xff, 0x0, 0x80, 0xff, 0xff}}, - {name: "CMPQ/src=R8/c=0x0", inst: CMPQ, srcReg: RegR8, c: 0x0, exp: []byte{0x49, 0x83, 0xf8, 0x0}}, - {name: "CMPQ/src=R8/c=0x1", inst: CMPQ, srcReg: RegR8, c: 0x1, exp: []byte{0x49, 0x83, 0xf8, 0x1}}, - {name: "CMPQ/src=R8/c=-0x1", inst: CMPQ, srcReg: RegR8, c: -0x1, exp: []byte{0x49, 0x83, 0xf8, 0xff}}, - {name: "CMPQ/src=R8/c=0x4db", inst: CMPQ, srcReg: RegR8, c: 0x4db, exp: []byte{0x49, 0x81, 0xf8, 0xdb, 0x4, 0x0, 0x0}}, - {name: "CMPQ/src=R8/c=-0x4d2", inst: CMPQ, srcReg: RegR8, c: -0x4d2, exp: []byte{0x49, 0x81, 0xf8, 0x2e, 0xfb, 0xff, 0xff}}, - {name: "CMPQ/src=R8/c=0x7fffffff", inst: CMPQ, srcReg: RegR8, c: 0x7fffffff, exp: []byte{0x49, 0x81, 0xf8, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPQ/src=R8/c=-0x80000000", inst: CMPQ, srcReg: RegR8, c: -0x80000000, exp: []byte{0x49, 0x81, 0xf8, 0x0, 0x0, 0x0, 0x80}}, - {name: "CMPQ/src=R8/c=0x7fff", inst: CMPQ, srcReg: RegR8, c: 0x7fff, exp: []byte{0x49, 0x81, 0xf8, 0xff, 0x7f, 0x0, 0x0}}, - {name: "CMPQ/src=R8/c=-0x8000", inst: CMPQ, srcReg: RegR8, c: -0x8000, exp: []byte{0x49, 0x81, 0xf8, 0x0, 0x80, 0xff, 0xff}}, - {name: "CMPQ/src=R9/c=0x0", inst: CMPQ, srcReg: RegR9, c: 0x0, exp: []byte{0x49, 0x83, 0xf9, 0x0}}, - {name: "CMPQ/src=R9/c=0x1", inst: CMPQ, srcReg: RegR9, c: 0x1, exp: []byte{0x49, 0x83, 0xf9, 0x1}}, - {name: "CMPQ/src=R9/c=-0x1", inst: CMPQ, srcReg: RegR9, c: -0x1, exp: []byte{0x49, 0x83, 0xf9, 0xff}}, - {name: "CMPQ/src=R9/c=0x4db", inst: CMPQ, srcReg: RegR9, c: 0x4db, exp: []byte{0x49, 0x81, 0xf9, 0xdb, 0x4, 0x0, 0x0}}, - {name: "CMPQ/src=R9/c=-0x4d2", inst: CMPQ, srcReg: RegR9, c: -0x4d2, exp: []byte{0x49, 0x81, 0xf9, 0x2e, 0xfb, 0xff, 0xff}}, - {name: "CMPQ/src=R9/c=0x7fffffff", inst: CMPQ, srcReg: RegR9, c: 0x7fffffff, exp: []byte{0x49, 0x81, 0xf9, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPQ/src=R9/c=-0x80000000", inst: CMPQ, srcReg: RegR9, c: -0x80000000, exp: []byte{0x49, 0x81, 0xf9, 0x0, 0x0, 0x0, 0x80}}, - {name: "CMPQ/src=R9/c=0x7fff", inst: CMPQ, srcReg: RegR9, c: 0x7fff, exp: []byte{0x49, 0x81, 0xf9, 0xff, 0x7f, 0x0, 0x0}}, - {name: "CMPQ/src=R9/c=-0x8000", inst: CMPQ, srcReg: RegR9, c: -0x8000, exp: []byte{0x49, 0x81, 0xf9, 0x0, 0x80, 0xff, 0xff}}, - {name: "CMPQ/src=R13/c=0x0", inst: CMPQ, srcReg: RegR13, c: 0x0, exp: []byte{0x49, 0x83, 0xfd, 0x0}}, - {name: "CMPQ/src=R13/c=0x1", inst: CMPQ, srcReg: RegR13, c: 0x1, exp: []byte{0x49, 0x83, 0xfd, 0x1}}, - {name: "CMPQ/src=R13/c=-0x1", inst: CMPQ, srcReg: RegR13, c: -0x1, exp: []byte{0x49, 0x83, 0xfd, 0xff}}, - {name: "CMPQ/src=R13/c=0x4db", inst: CMPQ, srcReg: RegR13, c: 0x4db, exp: []byte{0x49, 0x81, 0xfd, 0xdb, 0x4, 0x0, 0x0}}, - {name: "CMPQ/src=R13/c=-0x4d2", inst: CMPQ, srcReg: RegR13, c: -0x4d2, exp: []byte{0x49, 0x81, 0xfd, 0x2e, 0xfb, 0xff, 0xff}}, - {name: "CMPQ/src=R13/c=0x7fffffff", inst: CMPQ, srcReg: RegR13, c: 0x7fffffff, exp: []byte{0x49, 0x81, 0xfd, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPQ/src=R13/c=-0x80000000", inst: CMPQ, srcReg: RegR13, c: -0x80000000, exp: []byte{0x49, 0x81, 0xfd, 0x0, 0x0, 0x0, 0x80}}, - {name: "CMPQ/src=R13/c=0x7fff", inst: CMPQ, srcReg: RegR13, c: 0x7fff, exp: []byte{0x49, 0x81, 0xfd, 0xff, 0x7f, 0x0, 0x0}}, - {name: "CMPQ/src=R13/c=-0x8000", inst: CMPQ, srcReg: RegR13, c: -0x8000, exp: []byte{0x49, 0x81, 0xfd, 0x0, 0x80, 0xff, 0xff}}, - {name: "CMPQ/src=R14/c=0x0", inst: CMPQ, srcReg: RegR14, c: 0x0, exp: []byte{0x49, 0x83, 0xfe, 0x0}}, - {name: "CMPQ/src=R14/c=0x1", inst: CMPQ, srcReg: RegR14, c: 0x1, exp: []byte{0x49, 0x83, 0xfe, 0x1}}, - {name: "CMPQ/src=R14/c=-0x1", inst: CMPQ, srcReg: RegR14, c: -0x1, exp: []byte{0x49, 0x83, 0xfe, 0xff}}, - {name: "CMPQ/src=R14/c=0x4db", inst: CMPQ, srcReg: RegR14, c: 0x4db, exp: []byte{0x49, 0x81, 0xfe, 0xdb, 0x4, 0x0, 0x0}}, - {name: "CMPQ/src=R14/c=-0x4d2", inst: CMPQ, srcReg: RegR14, c: -0x4d2, exp: []byte{0x49, 0x81, 0xfe, 0x2e, 0xfb, 0xff, 0xff}}, - {name: "CMPQ/src=R14/c=0x7fffffff", inst: CMPQ, srcReg: RegR14, c: 0x7fffffff, exp: []byte{0x49, 0x81, 0xfe, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPQ/src=R14/c=-0x80000000", inst: CMPQ, srcReg: RegR14, c: -0x80000000, exp: []byte{0x49, 0x81, 0xfe, 0x0, 0x0, 0x0, 0x80}}, - {name: "CMPQ/src=R14/c=0x7fff", inst: CMPQ, srcReg: RegR14, c: 0x7fff, exp: []byte{0x49, 0x81, 0xfe, 0xff, 0x7f, 0x0, 0x0}}, - {name: "CMPQ/src=R14/c=-0x8000", inst: CMPQ, srcReg: RegR14, c: -0x8000, exp: []byte{0x49, 0x81, 0xfe, 0x0, 0x80, 0xff, 0xff}}, - {name: "CMPQ/src=R15/c=0x0", inst: CMPQ, srcReg: RegR15, c: 0x0, exp: []byte{0x49, 0x83, 0xff, 0x0}}, - {name: "CMPQ/src=R15/c=0x1", inst: CMPQ, srcReg: RegR15, c: 0x1, exp: []byte{0x49, 0x83, 0xff, 0x1}}, - {name: "CMPQ/src=R15/c=-0x1", inst: CMPQ, srcReg: RegR15, c: -0x1, exp: []byte{0x49, 0x83, 0xff, 0xff}}, - {name: "CMPQ/src=R15/c=0x4db", inst: CMPQ, srcReg: RegR15, c: 0x4db, exp: []byte{0x49, 0x81, 0xff, 0xdb, 0x4, 0x0, 0x0}}, - {name: "CMPQ/src=R15/c=-0x4d2", inst: CMPQ, srcReg: RegR15, c: -0x4d2, exp: []byte{0x49, 0x81, 0xff, 0x2e, 0xfb, 0xff, 0xff}}, - {name: "CMPQ/src=R15/c=0x7fffffff", inst: CMPQ, srcReg: RegR15, c: 0x7fffffff, exp: []byte{0x49, 0x81, 0xff, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPQ/src=R15/c=-0x80000000", inst: CMPQ, srcReg: RegR15, c: -0x80000000, exp: []byte{0x49, 0x81, 0xff, 0x0, 0x0, 0x0, 0x80}}, - {name: "CMPQ/src=R15/c=0x7fff", inst: CMPQ, srcReg: RegR15, c: 0x7fff, exp: []byte{0x49, 0x81, 0xff, 0xff, 0x7f, 0x0, 0x0}}, - {name: "CMPQ/src=R15/c=-0x8000", inst: CMPQ, srcReg: RegR15, c: -0x8000, exp: []byte{0x49, 0x81, 0xff, 0x0, 0x80, 0xff, 0xff}}, - } - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - for _, tc := range tests { - a := NewAssembler() - buf := code.NextCodeSection() - err := a.encodeRegisterToConst(buf, &nodeImpl{ - instruction: tc.inst, - types: operandTypesRegisterToConst, srcReg: tc.srcReg, dstConst: tc.c, - }) - require.NoError(t, err, tc.name) - require.Equal(t, tc.exp, buf.Bytes(), tc.name) - } -} - -func TestNodeImpl_GetRegisterToRegisterModRM(t *testing.T) { - tests := []struct { - name string - srcReg, dstReg asm.Register - srcOnModRMReg bool - expRexPrefix, expModRM byte - }{ - {name: "src=AX/dst=AX/srcOnModRMReg=true", srcReg: RegAX, dstReg: RegAX, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xc0}, - {name: "src=AX/dst=BX/srcOnModRMReg=true", srcReg: RegAX, dstReg: RegBX, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xc3}, - {name: "src=AX/dst=SP/srcOnModRMReg=true", srcReg: RegAX, dstReg: RegSP, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xc4}, - {name: "src=AX/dst=BP/srcOnModRMReg=true", srcReg: RegAX, dstReg: RegBP, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xc5}, - {name: "src=AX/dst=SI/srcOnModRMReg=true", srcReg: RegAX, dstReg: RegSI, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xc6}, - {name: "src=AX/dst=DI/srcOnModRMReg=true", srcReg: RegAX, dstReg: RegDI, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xc7}, - {name: "src=AX/dst=R8/srcOnModRMReg=true", srcReg: RegAX, dstReg: RegR8, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xc0}, - {name: "src=AX/dst=R9/srcOnModRMReg=true", srcReg: RegAX, dstReg: RegR9, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xc1}, - {name: "src=AX/dst=R13/srcOnModRMReg=true", srcReg: RegAX, dstReg: RegR13, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xc5}, - {name: "src=AX/dst=R14/srcOnModRMReg=true", srcReg: RegAX, dstReg: RegR14, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xc6}, - {name: "src=AX/dst=R15/srcOnModRMReg=true", srcReg: RegAX, dstReg: RegR15, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xc7}, - {name: "src=BX/dst=AX/srcOnModRMReg=true", srcReg: RegBX, dstReg: RegAX, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xd8}, - {name: "src=BX/dst=BX/srcOnModRMReg=true", srcReg: RegBX, dstReg: RegBX, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xdb}, - {name: "src=BX/dst=SP/srcOnModRMReg=true", srcReg: RegBX, dstReg: RegSP, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xdc}, - {name: "src=BX/dst=BP/srcOnModRMReg=true", srcReg: RegBX, dstReg: RegBP, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xdd}, - {name: "src=BX/dst=SI/srcOnModRMReg=true", srcReg: RegBX, dstReg: RegSI, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xde}, - {name: "src=BX/dst=DI/srcOnModRMReg=true", srcReg: RegBX, dstReg: RegDI, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xdf}, - {name: "src=BX/dst=R8/srcOnModRMReg=true", srcReg: RegBX, dstReg: RegR8, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xd8}, - {name: "src=BX/dst=R9/srcOnModRMReg=true", srcReg: RegBX, dstReg: RegR9, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xd9}, - {name: "src=BX/dst=R13/srcOnModRMReg=true", srcReg: RegBX, dstReg: RegR13, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xdd}, - {name: "src=BX/dst=R14/srcOnModRMReg=true", srcReg: RegBX, dstReg: RegR14, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xde}, - {name: "src=BX/dst=R15/srcOnModRMReg=true", srcReg: RegBX, dstReg: RegR15, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xdf}, - {name: "src=SP/dst=AX/srcOnModRMReg=true", srcReg: RegSP, dstReg: RegAX, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xe0}, - {name: "src=SP/dst=BX/srcOnModRMReg=true", srcReg: RegSP, dstReg: RegBX, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xe3}, - {name: "src=SP/dst=SP/srcOnModRMReg=true", srcReg: RegSP, dstReg: RegSP, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xe4}, - {name: "src=SP/dst=BP/srcOnModRMReg=true", srcReg: RegSP, dstReg: RegBP, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xe5}, - {name: "src=SP/dst=SI/srcOnModRMReg=true", srcReg: RegSP, dstReg: RegSI, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xe6}, - {name: "src=SP/dst=DI/srcOnModRMReg=true", srcReg: RegSP, dstReg: RegDI, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xe7}, - {name: "src=SP/dst=R8/srcOnModRMReg=true", srcReg: RegSP, dstReg: RegR8, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xe0}, - {name: "src=SP/dst=R9/srcOnModRMReg=true", srcReg: RegSP, dstReg: RegR9, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xe1}, - {name: "src=SP/dst=R13/srcOnModRMReg=true", srcReg: RegSP, dstReg: RegR13, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xe5}, - {name: "src=SP/dst=R14/srcOnModRMReg=true", srcReg: RegSP, dstReg: RegR14, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xe6}, - {name: "src=SP/dst=R15/srcOnModRMReg=true", srcReg: RegSP, dstReg: RegR15, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xe7}, - {name: "src=BP/dst=AX/srcOnModRMReg=true", srcReg: RegBP, dstReg: RegAX, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xe8}, - {name: "src=BP/dst=BX/srcOnModRMReg=true", srcReg: RegBP, dstReg: RegBX, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xeb}, - {name: "src=BP/dst=SP/srcOnModRMReg=true", srcReg: RegBP, dstReg: RegSP, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xec}, - {name: "src=BP/dst=BP/srcOnModRMReg=true", srcReg: RegBP, dstReg: RegBP, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xed}, - {name: "src=BP/dst=SI/srcOnModRMReg=true", srcReg: RegBP, dstReg: RegSI, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xee}, - {name: "src=BP/dst=DI/srcOnModRMReg=true", srcReg: RegBP, dstReg: RegDI, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xef}, - {name: "src=BP/dst=R8/srcOnModRMReg=true", srcReg: RegBP, dstReg: RegR8, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xe8}, - {name: "src=BP/dst=R9/srcOnModRMReg=true", srcReg: RegBP, dstReg: RegR9, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xe9}, - {name: "src=BP/dst=R13/srcOnModRMReg=true", srcReg: RegBP, dstReg: RegR13, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xed}, - {name: "src=BP/dst=R14/srcOnModRMReg=true", srcReg: RegBP, dstReg: RegR14, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xee}, - {name: "src=BP/dst=R15/srcOnModRMReg=true", srcReg: RegBP, dstReg: RegR15, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xef}, - {name: "src=SI/dst=AX/srcOnModRMReg=true", srcReg: RegSI, dstReg: RegAX, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xf0}, - {name: "src=SI/dst=BX/srcOnModRMReg=true", srcReg: RegSI, dstReg: RegBX, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xf3}, - {name: "src=SI/dst=SP/srcOnModRMReg=true", srcReg: RegSI, dstReg: RegSP, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xf4}, - {name: "src=SI/dst=BP/srcOnModRMReg=true", srcReg: RegSI, dstReg: RegBP, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xf5}, - {name: "src=SI/dst=SI/srcOnModRMReg=true", srcReg: RegSI, dstReg: RegSI, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xf6}, - {name: "src=SI/dst=DI/srcOnModRMReg=true", srcReg: RegSI, dstReg: RegDI, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xf7}, - {name: "src=SI/dst=R8/srcOnModRMReg=true", srcReg: RegSI, dstReg: RegR8, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xf0}, - {name: "src=SI/dst=R9/srcOnModRMReg=true", srcReg: RegSI, dstReg: RegR9, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xf1}, - {name: "src=SI/dst=R13/srcOnModRMReg=true", srcReg: RegSI, dstReg: RegR13, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xf5}, - {name: "src=SI/dst=R14/srcOnModRMReg=true", srcReg: RegSI, dstReg: RegR14, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xf6}, - {name: "src=SI/dst=R15/srcOnModRMReg=true", srcReg: RegSI, dstReg: RegR15, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xf7}, - {name: "src=DI/dst=AX/srcOnModRMReg=true", srcReg: RegDI, dstReg: RegAX, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xf8}, - {name: "src=DI/dst=BX/srcOnModRMReg=true", srcReg: RegDI, dstReg: RegBX, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xfb}, - {name: "src=DI/dst=SP/srcOnModRMReg=true", srcReg: RegDI, dstReg: RegSP, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xfc}, - {name: "src=DI/dst=BP/srcOnModRMReg=true", srcReg: RegDI, dstReg: RegBP, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xfd}, - {name: "src=DI/dst=SI/srcOnModRMReg=true", srcReg: RegDI, dstReg: RegSI, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xfe}, - {name: "src=DI/dst=DI/srcOnModRMReg=true", srcReg: RegDI, dstReg: RegDI, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xff}, - {name: "src=DI/dst=R8/srcOnModRMReg=true", srcReg: RegDI, dstReg: RegR8, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xf8}, - {name: "src=DI/dst=R9/srcOnModRMReg=true", srcReg: RegDI, dstReg: RegR9, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xf9}, - {name: "src=DI/dst=R13/srcOnModRMReg=true", srcReg: RegDI, dstReg: RegR13, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xfd}, - {name: "src=DI/dst=R14/srcOnModRMReg=true", srcReg: RegDI, dstReg: RegR14, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xfe}, - {name: "src=DI/dst=R15/srcOnModRMReg=true", srcReg: RegDI, dstReg: RegR15, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xff}, - {name: "src=R8/dst=AX/srcOnModRMReg=true", srcReg: RegR8, dstReg: RegAX, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xc0}, - {name: "src=R8/dst=BX/srcOnModRMReg=true", srcReg: RegR8, dstReg: RegBX, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xc3}, - {name: "src=R8/dst=SP/srcOnModRMReg=true", srcReg: RegR8, dstReg: RegSP, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xc4}, - {name: "src=R8/dst=BP/srcOnModRMReg=true", srcReg: RegR8, dstReg: RegBP, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xc5}, - {name: "src=R8/dst=SI/srcOnModRMReg=true", srcReg: RegR8, dstReg: RegSI, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xc6}, - {name: "src=R8/dst=DI/srcOnModRMReg=true", srcReg: RegR8, dstReg: RegDI, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xc7}, - {name: "src=R8/dst=R8/srcOnModRMReg=true", srcReg: RegR8, dstReg: RegR8, srcOnModRMReg: true, expRexPrefix: 0x45, expModRM: 0xc0}, - {name: "src=R8/dst=R9/srcOnModRMReg=true", srcReg: RegR8, dstReg: RegR9, srcOnModRMReg: true, expRexPrefix: 0x45, expModRM: 0xc1}, - {name: "src=R8/dst=R13/srcOnModRMReg=true", srcReg: RegR8, dstReg: RegR13, srcOnModRMReg: true, expRexPrefix: 0x45, expModRM: 0xc5}, - {name: "src=R8/dst=R14/srcOnModRMReg=true", srcReg: RegR8, dstReg: RegR14, srcOnModRMReg: true, expRexPrefix: 0x45, expModRM: 0xc6}, - {name: "src=R8/dst=R15/srcOnModRMReg=true", srcReg: RegR8, dstReg: RegR15, srcOnModRMReg: true, expRexPrefix: 0x45, expModRM: 0xc7}, - {name: "src=R9/dst=AX/srcOnModRMReg=true", srcReg: RegR9, dstReg: RegAX, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xc8}, - {name: "src=R9/dst=BX/srcOnModRMReg=true", srcReg: RegR9, dstReg: RegBX, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xcb}, - {name: "src=R9/dst=SP/srcOnModRMReg=true", srcReg: RegR9, dstReg: RegSP, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xcc}, - {name: "src=R9/dst=BP/srcOnModRMReg=true", srcReg: RegR9, dstReg: RegBP, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xcd}, - {name: "src=R9/dst=SI/srcOnModRMReg=true", srcReg: RegR9, dstReg: RegSI, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xce}, - {name: "src=R9/dst=DI/srcOnModRMReg=true", srcReg: RegR9, dstReg: RegDI, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xcf}, - {name: "src=R9/dst=R8/srcOnModRMReg=true", srcReg: RegR9, dstReg: RegR8, srcOnModRMReg: true, expRexPrefix: 0x45, expModRM: 0xc8}, - {name: "src=R9/dst=R9/srcOnModRMReg=true", srcReg: RegR9, dstReg: RegR9, srcOnModRMReg: true, expRexPrefix: 0x45, expModRM: 0xc9}, - {name: "src=R9/dst=R13/srcOnModRMReg=true", srcReg: RegR9, dstReg: RegR13, srcOnModRMReg: true, expRexPrefix: 0x45, expModRM: 0xcd}, - {name: "src=R9/dst=R14/srcOnModRMReg=true", srcReg: RegR9, dstReg: RegR14, srcOnModRMReg: true, expRexPrefix: 0x45, expModRM: 0xce}, - {name: "src=R9/dst=R15/srcOnModRMReg=true", srcReg: RegR9, dstReg: RegR15, srcOnModRMReg: true, expRexPrefix: 0x45, expModRM: 0xcf}, - {name: "src=R13/dst=AX/srcOnModRMReg=true", srcReg: RegR13, dstReg: RegAX, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xe8}, - {name: "src=R13/dst=BX/srcOnModRMReg=true", srcReg: RegR13, dstReg: RegBX, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xeb}, - {name: "src=R13/dst=SP/srcOnModRMReg=true", srcReg: RegR13, dstReg: RegSP, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xec}, - {name: "src=R13/dst=BP/srcOnModRMReg=true", srcReg: RegR13, dstReg: RegBP, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xed}, - {name: "src=R13/dst=SI/srcOnModRMReg=true", srcReg: RegR13, dstReg: RegSI, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xee}, - {name: "src=R13/dst=DI/srcOnModRMReg=true", srcReg: RegR13, dstReg: RegDI, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xef}, - {name: "src=R13/dst=R8/srcOnModRMReg=true", srcReg: RegR13, dstReg: RegR8, srcOnModRMReg: true, expRexPrefix: 0x45, expModRM: 0xe8}, - {name: "src=R13/dst=R9/srcOnModRMReg=true", srcReg: RegR13, dstReg: RegR9, srcOnModRMReg: true, expRexPrefix: 0x45, expModRM: 0xe9}, - {name: "src=R13/dst=R13/srcOnModRMReg=true", srcReg: RegR13, dstReg: RegR13, srcOnModRMReg: true, expRexPrefix: 0x45, expModRM: 0xed}, - {name: "src=R13/dst=R14/srcOnModRMReg=true", srcReg: RegR13, dstReg: RegR14, srcOnModRMReg: true, expRexPrefix: 0x45, expModRM: 0xee}, - {name: "src=R13/dst=R15/srcOnModRMReg=true", srcReg: RegR13, dstReg: RegR15, srcOnModRMReg: true, expRexPrefix: 0x45, expModRM: 0xef}, - {name: "src=R14/dst=AX/srcOnModRMReg=true", srcReg: RegR14, dstReg: RegAX, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xf0}, - {name: "src=R14/dst=BX/srcOnModRMReg=true", srcReg: RegR14, dstReg: RegBX, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xf3}, - {name: "src=R14/dst=SP/srcOnModRMReg=true", srcReg: RegR14, dstReg: RegSP, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xf4}, - {name: "src=R14/dst=BP/srcOnModRMReg=true", srcReg: RegR14, dstReg: RegBP, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xf5}, - {name: "src=R14/dst=SI/srcOnModRMReg=true", srcReg: RegR14, dstReg: RegSI, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xf6}, - {name: "src=R14/dst=DI/srcOnModRMReg=true", srcReg: RegR14, dstReg: RegDI, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xf7}, - {name: "src=R14/dst=R8/srcOnModRMReg=true", srcReg: RegR14, dstReg: RegR8, srcOnModRMReg: true, expRexPrefix: 0x45, expModRM: 0xf0}, - {name: "src=R14/dst=R9/srcOnModRMReg=true", srcReg: RegR14, dstReg: RegR9, srcOnModRMReg: true, expRexPrefix: 0x45, expModRM: 0xf1}, - {name: "src=R14/dst=R13/srcOnModRMReg=true", srcReg: RegR14, dstReg: RegR13, srcOnModRMReg: true, expRexPrefix: 0x45, expModRM: 0xf5}, - {name: "src=R14/dst=R14/srcOnModRMReg=true", srcReg: RegR14, dstReg: RegR14, srcOnModRMReg: true, expRexPrefix: 0x45, expModRM: 0xf6}, - {name: "src=R14/dst=R15/srcOnModRMReg=true", srcReg: RegR14, dstReg: RegR15, srcOnModRMReg: true, expRexPrefix: 0x45, expModRM: 0xf7}, - {name: "src=R15/dst=AX/srcOnModRMReg=true", srcReg: RegR15, dstReg: RegAX, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xf8}, - {name: "src=R15/dst=BX/srcOnModRMReg=true", srcReg: RegR15, dstReg: RegBX, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xfb}, - {name: "src=R15/dst=SP/srcOnModRMReg=true", srcReg: RegR15, dstReg: RegSP, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xfc}, - {name: "src=R15/dst=BP/srcOnModRMReg=true", srcReg: RegR15, dstReg: RegBP, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xfd}, - {name: "src=R15/dst=SI/srcOnModRMReg=true", srcReg: RegR15, dstReg: RegSI, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xfe}, - {name: "src=R15/dst=DI/srcOnModRMReg=true", srcReg: RegR15, dstReg: RegDI, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xff}, - {name: "src=R15/dst=R8/srcOnModRMReg=true", srcReg: RegR15, dstReg: RegR8, srcOnModRMReg: true, expRexPrefix: 0x45, expModRM: 0xf8}, - {name: "src=R15/dst=R9/srcOnModRMReg=true", srcReg: RegR15, dstReg: RegR9, srcOnModRMReg: true, expRexPrefix: 0x45, expModRM: 0xf9}, - {name: "src=R15/dst=R13/srcOnModRMReg=true", srcReg: RegR15, dstReg: RegR13, srcOnModRMReg: true, expRexPrefix: 0x45, expModRM: 0xfd}, - {name: "src=R15/dst=R14/srcOnModRMReg=true", srcReg: RegR15, dstReg: RegR14, srcOnModRMReg: true, expRexPrefix: 0x45, expModRM: 0xfe}, - {name: "src=R15/dst=R15/srcOnModRMReg=true", srcReg: RegR15, dstReg: RegR15, srcOnModRMReg: true, expRexPrefix: 0x45, expModRM: 0xff}, - {name: "src=AX/dst=AX/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc0}, - {name: "src=AX/dst=BX/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xd8}, - {name: "src=AX/dst=SP/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe0}, - {name: "src=AX/dst=BP/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe8}, - {name: "src=AX/dst=SI/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf0}, - {name: "src=AX/dst=DI/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf8}, - {name: "src=AX/dst=R8/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc0}, - {name: "src=AX/dst=R9/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc8}, - {name: "src=AX/dst=R13/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xe8}, - {name: "src=AX/dst=R14/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf0}, - {name: "src=AX/dst=R15/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf8}, - {name: "src=BX/dst=AX/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc3}, - {name: "src=BX/dst=BX/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xdb}, - {name: "src=BX/dst=SP/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe3}, - {name: "src=BX/dst=BP/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xeb}, - {name: "src=BX/dst=SI/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf3}, - {name: "src=BX/dst=DI/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xfb}, - {name: "src=BX/dst=R8/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc3}, - {name: "src=BX/dst=R9/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xcb}, - {name: "src=BX/dst=R13/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xeb}, - {name: "src=BX/dst=R14/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf3}, - {name: "src=BX/dst=R15/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xfb}, - {name: "src=SP/dst=AX/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc4}, - {name: "src=SP/dst=BX/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xdc}, - {name: "src=SP/dst=SP/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe4}, - {name: "src=SP/dst=BP/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xec}, - {name: "src=SP/dst=SI/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf4}, - {name: "src=SP/dst=DI/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xfc}, - {name: "src=SP/dst=R8/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc4}, - {name: "src=SP/dst=R9/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xcc}, - {name: "src=SP/dst=R13/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xec}, - {name: "src=SP/dst=R14/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf4}, - {name: "src=SP/dst=R15/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xfc}, - {name: "src=BP/dst=AX/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc5}, - {name: "src=BP/dst=BX/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xdd}, - {name: "src=BP/dst=SP/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe5}, - {name: "src=BP/dst=BP/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xed}, - {name: "src=BP/dst=SI/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf5}, - {name: "src=BP/dst=DI/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xfd}, - {name: "src=BP/dst=R8/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc5}, - {name: "src=BP/dst=R9/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xcd}, - {name: "src=BP/dst=R13/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xed}, - {name: "src=BP/dst=R14/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf5}, - {name: "src=BP/dst=R15/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xfd}, - {name: "src=SI/dst=AX/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc6}, - {name: "src=SI/dst=BX/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xde}, - {name: "src=SI/dst=SP/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe6}, - {name: "src=SI/dst=BP/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xee}, - {name: "src=SI/dst=SI/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf6}, - {name: "src=SI/dst=DI/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xfe}, - {name: "src=SI/dst=R8/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc6}, - {name: "src=SI/dst=R9/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xce}, - {name: "src=SI/dst=R13/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xee}, - {name: "src=SI/dst=R14/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf6}, - {name: "src=SI/dst=R15/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xfe}, - {name: "src=DI/dst=AX/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc7}, - {name: "src=DI/dst=BX/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xdf}, - {name: "src=DI/dst=SP/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe7}, - {name: "src=DI/dst=BP/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xef}, - {name: "src=DI/dst=SI/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf7}, - {name: "src=DI/dst=DI/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xff}, - {name: "src=DI/dst=R8/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc7}, - {name: "src=DI/dst=R9/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xcf}, - {name: "src=DI/dst=R13/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xef}, - {name: "src=DI/dst=R14/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf7}, - {name: "src=DI/dst=R15/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xff}, - {name: "src=R8/dst=AX/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc0}, - {name: "src=R8/dst=BX/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xd8}, - {name: "src=R8/dst=SP/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe0}, - {name: "src=R8/dst=BP/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe8}, - {name: "src=R8/dst=SI/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf0}, - {name: "src=R8/dst=DI/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf8}, - {name: "src=R8/dst=R8/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc0}, - {name: "src=R8/dst=R9/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc8}, - {name: "src=R8/dst=R13/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xe8}, - {name: "src=R8/dst=R14/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf0}, - {name: "src=R8/dst=R15/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf8}, - {name: "src=R9/dst=AX/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc1}, - {name: "src=R9/dst=BX/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xd9}, - {name: "src=R9/dst=SP/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe1}, - {name: "src=R9/dst=BP/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe9}, - {name: "src=R9/dst=SI/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf1}, - {name: "src=R9/dst=DI/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf9}, - {name: "src=R9/dst=R8/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc1}, - {name: "src=R9/dst=R9/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc9}, - {name: "src=R9/dst=R13/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xe9}, - {name: "src=R9/dst=R14/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf1}, - {name: "src=R9/dst=R15/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf9}, - {name: "src=R13/dst=AX/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc5}, - {name: "src=R13/dst=BX/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xdd}, - {name: "src=R13/dst=SP/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe5}, - {name: "src=R13/dst=BP/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xed}, - {name: "src=R13/dst=SI/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf5}, - {name: "src=R13/dst=DI/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xfd}, - {name: "src=R13/dst=R8/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc5}, - {name: "src=R13/dst=R9/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xcd}, - {name: "src=R13/dst=R13/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xed}, - {name: "src=R13/dst=R14/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf5}, - {name: "src=R13/dst=R15/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xfd}, - {name: "src=R14/dst=AX/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc6}, - {name: "src=R14/dst=BX/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xde}, - {name: "src=R14/dst=SP/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe6}, - {name: "src=R14/dst=BP/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xee}, - {name: "src=R14/dst=SI/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf6}, - {name: "src=R14/dst=DI/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xfe}, - {name: "src=R14/dst=R8/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc6}, - {name: "src=R14/dst=R9/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xce}, - {name: "src=R14/dst=R13/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xee}, - {name: "src=R14/dst=R14/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf6}, - {name: "src=R14/dst=R15/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xfe}, - {name: "src=R15/dst=AX/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc7}, - {name: "src=R15/dst=BX/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xdf}, - {name: "src=R15/dst=SP/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe7}, - {name: "src=R15/dst=BP/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xef}, - {name: "src=R15/dst=SI/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf7}, - {name: "src=R15/dst=DI/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xff}, - {name: "src=R15/dst=R8/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc7}, - {name: "src=R15/dst=R9/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xcf}, - {name: "src=R15/dst=R13/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xef}, - {name: "src=R15/dst=R14/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf7}, - {name: "src=R15/dst=R15/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xff}, - {name: "src=X0/dst=X0/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc0}, - {name: "src=X0/dst=X1/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc8}, - {name: "src=X0/dst=X2/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xd0}, - {name: "src=X0/dst=X3/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xd8}, - {name: "src=X0/dst=X4/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe0}, - {name: "src=X0/dst=X5/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe8}, - {name: "src=X0/dst=X6/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf0}, - {name: "src=X0/dst=X7/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf8}, - {name: "src=X0/dst=X8/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc0}, - {name: "src=X0/dst=X9/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc8}, - {name: "src=X0/dst=X10/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xd0}, - {name: "src=X0/dst=X11/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xd8}, - {name: "src=X0/dst=X12/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xe0}, - {name: "src=X0/dst=X13/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xe8}, - {name: "src=X0/dst=X14/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf0}, - {name: "src=X0/dst=X15/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf8}, - {name: "src=X1/dst=X0/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc1}, - {name: "src=X1/dst=X1/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc9}, - {name: "src=X1/dst=X2/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xd1}, - {name: "src=X1/dst=X3/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xd9}, - {name: "src=X1/dst=X4/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe1}, - {name: "src=X1/dst=X5/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe9}, - {name: "src=X1/dst=X6/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf1}, - {name: "src=X1/dst=X7/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf9}, - {name: "src=X1/dst=X8/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc1}, - {name: "src=X1/dst=X9/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc9}, - {name: "src=X1/dst=X10/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xd1}, - {name: "src=X1/dst=X11/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xd9}, - {name: "src=X1/dst=X12/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xe1}, - {name: "src=X1/dst=X13/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xe9}, - {name: "src=X1/dst=X14/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf1}, - {name: "src=X1/dst=X15/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf9}, - {name: "src=X2/dst=X0/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc2}, - {name: "src=X2/dst=X1/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xca}, - {name: "src=X2/dst=X2/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xd2}, - {name: "src=X2/dst=X3/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xda}, - {name: "src=X2/dst=X4/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe2}, - {name: "src=X2/dst=X5/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xea}, - {name: "src=X2/dst=X6/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf2}, - {name: "src=X2/dst=X7/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xfa}, - {name: "src=X2/dst=X8/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc2}, - {name: "src=X2/dst=X9/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xca}, - {name: "src=X2/dst=X10/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xd2}, - {name: "src=X2/dst=X11/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xda}, - {name: "src=X2/dst=X12/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xe2}, - {name: "src=X2/dst=X13/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xea}, - {name: "src=X2/dst=X14/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf2}, - {name: "src=X2/dst=X15/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xfa}, - {name: "src=X3/dst=X0/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc3}, - {name: "src=X3/dst=X1/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xcb}, - {name: "src=X3/dst=X2/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xd3}, - {name: "src=X3/dst=X3/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xdb}, - {name: "src=X3/dst=X4/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe3}, - {name: "src=X3/dst=X5/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xeb}, - {name: "src=X3/dst=X6/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf3}, - {name: "src=X3/dst=X7/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xfb}, - {name: "src=X3/dst=X8/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc3}, - {name: "src=X3/dst=X9/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xcb}, - {name: "src=X3/dst=X10/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xd3}, - {name: "src=X3/dst=X11/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xdb}, - {name: "src=X3/dst=X12/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xe3}, - {name: "src=X3/dst=X13/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xeb}, - {name: "src=X3/dst=X14/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf3}, - {name: "src=X3/dst=X15/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xfb}, - {name: "src=X4/dst=X0/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc4}, - {name: "src=X4/dst=X1/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xcc}, - {name: "src=X4/dst=X2/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xd4}, - {name: "src=X4/dst=X3/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xdc}, - {name: "src=X4/dst=X4/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe4}, - {name: "src=X4/dst=X5/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xec}, - {name: "src=X4/dst=X6/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf4}, - {name: "src=X4/dst=X7/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xfc}, - {name: "src=X4/dst=X8/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc4}, - {name: "src=X4/dst=X9/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xcc}, - {name: "src=X4/dst=X10/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xd4}, - {name: "src=X4/dst=X11/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xdc}, - {name: "src=X4/dst=X12/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xe4}, - {name: "src=X4/dst=X13/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xec}, - {name: "src=X4/dst=X14/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf4}, - {name: "src=X4/dst=X15/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xfc}, - {name: "src=X5/dst=X0/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc5}, - {name: "src=X5/dst=X1/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xcd}, - {name: "src=X5/dst=X2/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xd5}, - {name: "src=X5/dst=X3/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xdd}, - {name: "src=X5/dst=X4/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe5}, - {name: "src=X5/dst=X5/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xed}, - {name: "src=X5/dst=X6/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf5}, - {name: "src=X5/dst=X7/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xfd}, - {name: "src=X5/dst=X8/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc5}, - {name: "src=X5/dst=X9/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xcd}, - {name: "src=X5/dst=X10/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xd5}, - {name: "src=X5/dst=X11/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xdd}, - {name: "src=X5/dst=X12/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xe5}, - {name: "src=X5/dst=X13/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xed}, - {name: "src=X5/dst=X14/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf5}, - {name: "src=X5/dst=X15/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xfd}, - {name: "src=X6/dst=X0/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc6}, - {name: "src=X6/dst=X1/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xce}, - {name: "src=X6/dst=X2/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xd6}, - {name: "src=X6/dst=X3/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xde}, - {name: "src=X6/dst=X4/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe6}, - {name: "src=X6/dst=X5/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xee}, - {name: "src=X6/dst=X6/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf6}, - {name: "src=X6/dst=X7/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xfe}, - {name: "src=X6/dst=X8/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc6}, - {name: "src=X6/dst=X9/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xce}, - {name: "src=X6/dst=X10/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xd6}, - {name: "src=X6/dst=X11/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xde}, - {name: "src=X6/dst=X12/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xe6}, - {name: "src=X6/dst=X13/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xee}, - {name: "src=X6/dst=X14/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf6}, - {name: "src=X6/dst=X15/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xfe}, - {name: "src=X7/dst=X0/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc7}, - {name: "src=X7/dst=X1/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xcf}, - {name: "src=X7/dst=X2/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xd7}, - {name: "src=X7/dst=X3/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xdf}, - {name: "src=X7/dst=X4/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe7}, - {name: "src=X7/dst=X5/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xef}, - {name: "src=X7/dst=X6/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf7}, - {name: "src=X7/dst=X7/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xff}, - {name: "src=X7/dst=X8/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc7}, - {name: "src=X7/dst=X9/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xcf}, - {name: "src=X7/dst=X10/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xd7}, - {name: "src=X7/dst=X11/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xdf}, - {name: "src=X7/dst=X12/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xe7}, - {name: "src=X7/dst=X13/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xef}, - {name: "src=X7/dst=X14/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf7}, - {name: "src=X7/dst=X15/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xff}, - {name: "src=X8/dst=X0/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc0}, - {name: "src=X8/dst=X1/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc8}, - {name: "src=X8/dst=X2/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xd0}, - {name: "src=X8/dst=X3/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xd8}, - {name: "src=X8/dst=X4/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe0}, - {name: "src=X8/dst=X5/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe8}, - {name: "src=X8/dst=X6/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf0}, - {name: "src=X8/dst=X7/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf8}, - {name: "src=X8/dst=X8/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc0}, - {name: "src=X8/dst=X9/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc8}, - {name: "src=X8/dst=X10/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xd0}, - {name: "src=X8/dst=X11/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xd8}, - {name: "src=X8/dst=X12/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xe0}, - {name: "src=X8/dst=X13/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xe8}, - {name: "src=X8/dst=X14/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf0}, - {name: "src=X8/dst=X15/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf8}, - {name: "src=X9/dst=X0/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc1}, - {name: "src=X9/dst=X1/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc9}, - {name: "src=X9/dst=X2/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xd1}, - {name: "src=X9/dst=X3/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xd9}, - {name: "src=X9/dst=X4/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe1}, - {name: "src=X9/dst=X5/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe9}, - {name: "src=X9/dst=X6/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf1}, - {name: "src=X9/dst=X7/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf9}, - {name: "src=X9/dst=X8/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc1}, - {name: "src=X9/dst=X9/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc9}, - {name: "src=X9/dst=X10/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xd1}, - {name: "src=X9/dst=X11/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xd9}, - {name: "src=X9/dst=X12/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xe1}, - {name: "src=X9/dst=X13/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xe9}, - {name: "src=X9/dst=X14/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf1}, - {name: "src=X9/dst=X15/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf9}, - {name: "src=X10/dst=X0/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc2}, - {name: "src=X10/dst=X1/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xca}, - {name: "src=X10/dst=X2/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xd2}, - {name: "src=X10/dst=X3/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xda}, - {name: "src=X10/dst=X4/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe2}, - {name: "src=X10/dst=X5/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xea}, - {name: "src=X10/dst=X6/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf2}, - {name: "src=X10/dst=X7/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xfa}, - {name: "src=X10/dst=X8/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc2}, - {name: "src=X10/dst=X9/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xca}, - {name: "src=X10/dst=X10/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xd2}, - {name: "src=X10/dst=X11/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xda}, - {name: "src=X10/dst=X12/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xe2}, - {name: "src=X10/dst=X13/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xea}, - {name: "src=X10/dst=X14/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf2}, - {name: "src=X10/dst=X15/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xfa}, - {name: "src=X11/dst=X0/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc3}, - {name: "src=X11/dst=X1/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xcb}, - {name: "src=X11/dst=X2/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xd3}, - {name: "src=X11/dst=X3/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xdb}, - {name: "src=X11/dst=X4/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe3}, - {name: "src=X11/dst=X5/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xeb}, - {name: "src=X11/dst=X6/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf3}, - {name: "src=X11/dst=X7/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xfb}, - {name: "src=X11/dst=X8/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc3}, - {name: "src=X11/dst=X9/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xcb}, - {name: "src=X11/dst=X10/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xd3}, - {name: "src=X11/dst=X11/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xdb}, - {name: "src=X11/dst=X12/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xe3}, - {name: "src=X11/dst=X13/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xeb}, - {name: "src=X11/dst=X14/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf3}, - {name: "src=X11/dst=X15/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xfb}, - {name: "src=X12/dst=X0/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc4}, - {name: "src=X12/dst=X1/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xcc}, - {name: "src=X12/dst=X2/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xd4}, - {name: "src=X12/dst=X3/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xdc}, - {name: "src=X12/dst=X4/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe4}, - {name: "src=X12/dst=X5/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xec}, - {name: "src=X12/dst=X6/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf4}, - {name: "src=X12/dst=X7/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xfc}, - {name: "src=X12/dst=X8/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc4}, - {name: "src=X12/dst=X9/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xcc}, - {name: "src=X12/dst=X10/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xd4}, - {name: "src=X12/dst=X11/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xdc}, - {name: "src=X12/dst=X12/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xe4}, - {name: "src=X12/dst=X13/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xec}, - {name: "src=X12/dst=X14/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf4}, - {name: "src=X12/dst=X15/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xfc}, - {name: "src=X13/dst=X0/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc5}, - {name: "src=X13/dst=X1/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xcd}, - {name: "src=X13/dst=X2/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xd5}, - {name: "src=X13/dst=X3/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xdd}, - {name: "src=X13/dst=X4/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe5}, - {name: "src=X13/dst=X5/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xed}, - {name: "src=X13/dst=X6/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf5}, - {name: "src=X13/dst=X7/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xfd}, - {name: "src=X13/dst=X8/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc5}, - {name: "src=X13/dst=X9/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xcd}, - {name: "src=X13/dst=X10/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xd5}, - {name: "src=X13/dst=X11/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xdd}, - {name: "src=X13/dst=X12/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xe5}, - {name: "src=X13/dst=X13/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xed}, - {name: "src=X13/dst=X14/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf5}, - {name: "src=X13/dst=X15/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xfd}, - {name: "src=X14/dst=X0/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc6}, - {name: "src=X14/dst=X1/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xce}, - {name: "src=X14/dst=X2/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xd6}, - {name: "src=X14/dst=X3/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xde}, - {name: "src=X14/dst=X4/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe6}, - {name: "src=X14/dst=X5/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xee}, - {name: "src=X14/dst=X6/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf6}, - {name: "src=X14/dst=X7/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xfe}, - {name: "src=X14/dst=X8/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc6}, - {name: "src=X14/dst=X9/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xce}, - {name: "src=X14/dst=X10/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xd6}, - {name: "src=X14/dst=X11/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xde}, - {name: "src=X14/dst=X12/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xe6}, - {name: "src=X14/dst=X13/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xee}, - {name: "src=X14/dst=X14/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf6}, - {name: "src=X14/dst=X15/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xfe}, - {name: "src=X15/dst=X0/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc7}, - {name: "src=X15/dst=X1/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xcf}, - {name: "src=X15/dst=X2/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xd7}, - {name: "src=X15/dst=X3/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xdf}, - {name: "src=X15/dst=X4/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe7}, - {name: "src=X15/dst=X5/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xef}, - {name: "src=X15/dst=X6/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf7}, - {name: "src=X15/dst=X7/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xff}, - {name: "src=X15/dst=X8/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc7}, - {name: "src=X15/dst=X9/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xcf}, - {name: "src=X15/dst=X10/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xd7}, - {name: "src=X15/dst=X11/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xdf}, - {name: "src=X15/dst=X12/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xe7}, - {name: "src=X15/dst=X13/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xef}, - {name: "src=X15/dst=X14/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf7}, - {name: "src=X15/dst=X15/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xff}, - {name: "src=X0/dst=AX/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc0}, - {name: "src=X0/dst=BX/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xd8}, - {name: "src=X0/dst=SP/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe0}, - {name: "src=X0/dst=BP/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe8}, - {name: "src=X0/dst=SI/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf0}, - {name: "src=X0/dst=DI/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf8}, - {name: "src=X0/dst=R8/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc0}, - {name: "src=X0/dst=R9/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc8}, - {name: "src=X0/dst=R13/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xe8}, - {name: "src=X0/dst=R14/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf0}, - {name: "src=X0/dst=R15/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf8}, - {name: "src=X1/dst=AX/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc1}, - {name: "src=X1/dst=BX/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xd9}, - {name: "src=X1/dst=SP/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe1}, - {name: "src=X1/dst=BP/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe9}, - {name: "src=X1/dst=SI/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf1}, - {name: "src=X1/dst=DI/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf9}, - {name: "src=X1/dst=R8/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc1}, - {name: "src=X1/dst=R9/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc9}, - {name: "src=X1/dst=R13/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xe9}, - {name: "src=X1/dst=R14/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf1}, - {name: "src=X1/dst=R15/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf9}, - {name: "src=X2/dst=AX/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc2}, - {name: "src=X2/dst=BX/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xda}, - {name: "src=X2/dst=SP/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe2}, - {name: "src=X2/dst=BP/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xea}, - {name: "src=X2/dst=SI/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf2}, - {name: "src=X2/dst=DI/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xfa}, - {name: "src=X2/dst=R8/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc2}, - {name: "src=X2/dst=R9/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xca}, - {name: "src=X2/dst=R13/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xea}, - {name: "src=X2/dst=R14/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf2}, - {name: "src=X2/dst=R15/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xfa}, - {name: "src=X3/dst=AX/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc3}, - {name: "src=X3/dst=BX/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xdb}, - {name: "src=X3/dst=SP/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe3}, - {name: "src=X3/dst=BP/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xeb}, - {name: "src=X3/dst=SI/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf3}, - {name: "src=X3/dst=DI/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xfb}, - {name: "src=X3/dst=R8/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc3}, - {name: "src=X3/dst=R9/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xcb}, - {name: "src=X3/dst=R13/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xeb}, - {name: "src=X3/dst=R14/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf3}, - {name: "src=X3/dst=R15/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xfb}, - {name: "src=X4/dst=AX/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc4}, - {name: "src=X4/dst=BX/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xdc}, - {name: "src=X4/dst=SP/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe4}, - {name: "src=X4/dst=BP/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xec}, - {name: "src=X4/dst=SI/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf4}, - {name: "src=X4/dst=DI/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xfc}, - {name: "src=X4/dst=R8/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc4}, - {name: "src=X4/dst=R9/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xcc}, - {name: "src=X4/dst=R13/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xec}, - {name: "src=X4/dst=R14/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf4}, - {name: "src=X4/dst=R15/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xfc}, - {name: "src=X5/dst=AX/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc5}, - {name: "src=X5/dst=BX/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xdd}, - {name: "src=X5/dst=SP/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe5}, - {name: "src=X5/dst=BP/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xed}, - {name: "src=X5/dst=SI/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf5}, - {name: "src=X5/dst=DI/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xfd}, - {name: "src=X5/dst=R8/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc5}, - {name: "src=X5/dst=R9/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xcd}, - {name: "src=X5/dst=R13/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xed}, - {name: "src=X5/dst=R14/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf5}, - {name: "src=X5/dst=R15/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xfd}, - {name: "src=X6/dst=AX/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc6}, - {name: "src=X6/dst=BX/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xde}, - {name: "src=X6/dst=SP/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe6}, - {name: "src=X6/dst=BP/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xee}, - {name: "src=X6/dst=SI/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf6}, - {name: "src=X6/dst=DI/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xfe}, - {name: "src=X6/dst=R8/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc6}, - {name: "src=X6/dst=R9/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xce}, - {name: "src=X6/dst=R13/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xee}, - {name: "src=X6/dst=R14/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf6}, - {name: "src=X6/dst=R15/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xfe}, - {name: "src=X7/dst=AX/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc7}, - {name: "src=X7/dst=BX/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xdf}, - {name: "src=X7/dst=SP/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe7}, - {name: "src=X7/dst=BP/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xef}, - {name: "src=X7/dst=SI/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf7}, - {name: "src=X7/dst=DI/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xff}, - {name: "src=X7/dst=R8/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc7}, - {name: "src=X7/dst=R9/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xcf}, - {name: "src=X7/dst=R13/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xef}, - {name: "src=X7/dst=R14/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf7}, - {name: "src=X7/dst=R15/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xff}, - {name: "src=X8/dst=AX/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc0}, - {name: "src=X8/dst=BX/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xd8}, - {name: "src=X8/dst=SP/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe0}, - {name: "src=X8/dst=BP/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe8}, - {name: "src=X8/dst=SI/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf0}, - {name: "src=X8/dst=DI/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf8}, - {name: "src=X8/dst=R8/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc0}, - {name: "src=X8/dst=R9/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc8}, - {name: "src=X8/dst=R13/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xe8}, - {name: "src=X8/dst=R14/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf0}, - {name: "src=X8/dst=R15/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf8}, - {name: "src=X9/dst=AX/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc1}, - {name: "src=X9/dst=BX/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xd9}, - {name: "src=X9/dst=SP/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe1}, - {name: "src=X9/dst=BP/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe9}, - {name: "src=X9/dst=SI/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf1}, - {name: "src=X9/dst=DI/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf9}, - {name: "src=X9/dst=R8/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc1}, - {name: "src=X9/dst=R9/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc9}, - {name: "src=X9/dst=R13/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xe9}, - {name: "src=X9/dst=R14/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf1}, - {name: "src=X9/dst=R15/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf9}, - {name: "src=X10/dst=AX/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc2}, - {name: "src=X10/dst=BX/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xda}, - {name: "src=X10/dst=SP/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe2}, - {name: "src=X10/dst=BP/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xea}, - {name: "src=X10/dst=SI/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf2}, - {name: "src=X10/dst=DI/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xfa}, - {name: "src=X10/dst=R8/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc2}, - {name: "src=X10/dst=R9/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xca}, - {name: "src=X10/dst=R13/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xea}, - {name: "src=X10/dst=R14/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf2}, - {name: "src=X10/dst=R15/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xfa}, - {name: "src=X11/dst=AX/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc3}, - {name: "src=X11/dst=BX/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xdb}, - {name: "src=X11/dst=SP/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe3}, - {name: "src=X11/dst=BP/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xeb}, - {name: "src=X11/dst=SI/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf3}, - {name: "src=X11/dst=DI/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xfb}, - {name: "src=X11/dst=R8/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc3}, - {name: "src=X11/dst=R9/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xcb}, - {name: "src=X11/dst=R13/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xeb}, - {name: "src=X11/dst=R14/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf3}, - {name: "src=X11/dst=R15/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xfb}, - {name: "src=X12/dst=AX/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc4}, - {name: "src=X12/dst=BX/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xdc}, - {name: "src=X12/dst=SP/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe4}, - {name: "src=X12/dst=BP/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xec}, - {name: "src=X12/dst=SI/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf4}, - {name: "src=X12/dst=DI/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xfc}, - {name: "src=X12/dst=R8/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc4}, - {name: "src=X12/dst=R9/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xcc}, - {name: "src=X12/dst=R13/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xec}, - {name: "src=X12/dst=R14/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf4}, - {name: "src=X12/dst=R15/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xfc}, - {name: "src=X13/dst=AX/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc5}, - {name: "src=X13/dst=BX/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xdd}, - {name: "src=X13/dst=SP/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe5}, - {name: "src=X13/dst=BP/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xed}, - {name: "src=X13/dst=SI/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf5}, - {name: "src=X13/dst=DI/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xfd}, - {name: "src=X13/dst=R8/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc5}, - {name: "src=X13/dst=R9/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xcd}, - {name: "src=X13/dst=R13/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xed}, - {name: "src=X13/dst=R14/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf5}, - {name: "src=X13/dst=R15/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xfd}, - {name: "src=X14/dst=AX/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc6}, - {name: "src=X14/dst=BX/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xde}, - {name: "src=X14/dst=SP/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe6}, - {name: "src=X14/dst=BP/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xee}, - {name: "src=X14/dst=SI/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf6}, - {name: "src=X14/dst=DI/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xfe}, - {name: "src=X14/dst=R8/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc6}, - {name: "src=X14/dst=R9/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xce}, - {name: "src=X14/dst=R13/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xee}, - {name: "src=X14/dst=R14/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf6}, - {name: "src=X14/dst=R15/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xfe}, - {name: "src=X15/dst=AX/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc7}, - {name: "src=X15/dst=BX/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xdf}, - {name: "src=X15/dst=SP/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe7}, - {name: "src=X15/dst=BP/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xef}, - {name: "src=X15/dst=SI/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf7}, - {name: "src=X15/dst=DI/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xff}, - {name: "src=X15/dst=R8/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc7}, - {name: "src=X15/dst=R9/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xcf}, - {name: "src=X15/dst=R13/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xef}, - {name: "src=X15/dst=R14/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf7}, - {name: "src=X15/dst=R15/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xff}, - {name: "src=AX/dst=X0/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc0}, - {name: "src=AX/dst=X1/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc8}, - {name: "src=AX/dst=X2/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xd0}, - {name: "src=AX/dst=X3/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xd8}, - {name: "src=AX/dst=X4/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe0}, - {name: "src=AX/dst=X5/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe8}, - {name: "src=AX/dst=X6/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf0}, - {name: "src=AX/dst=X7/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf8}, - {name: "src=AX/dst=X8/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc0}, - {name: "src=AX/dst=X9/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc8}, - {name: "src=AX/dst=X10/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xd0}, - {name: "src=AX/dst=X11/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xd8}, - {name: "src=AX/dst=X12/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xe0}, - {name: "src=AX/dst=X13/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xe8}, - {name: "src=AX/dst=X14/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf0}, - {name: "src=AX/dst=X15/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf8}, - {name: "src=BX/dst=X0/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc3}, - {name: "src=BX/dst=X1/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xcb}, - {name: "src=BX/dst=X2/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xd3}, - {name: "src=BX/dst=X3/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xdb}, - {name: "src=BX/dst=X4/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe3}, - {name: "src=BX/dst=X5/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xeb}, - {name: "src=BX/dst=X6/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf3}, - {name: "src=BX/dst=X7/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xfb}, - {name: "src=BX/dst=X8/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc3}, - {name: "src=BX/dst=X9/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xcb}, - {name: "src=BX/dst=X10/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xd3}, - {name: "src=BX/dst=X11/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xdb}, - {name: "src=BX/dst=X12/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xe3}, - {name: "src=BX/dst=X13/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xeb}, - {name: "src=BX/dst=X14/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf3}, - {name: "src=BX/dst=X15/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xfb}, - {name: "src=SP/dst=X0/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc4}, - {name: "src=SP/dst=X1/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xcc}, - {name: "src=SP/dst=X2/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xd4}, - {name: "src=SP/dst=X3/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xdc}, - {name: "src=SP/dst=X4/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe4}, - {name: "src=SP/dst=X5/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xec}, - {name: "src=SP/dst=X6/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf4}, - {name: "src=SP/dst=X7/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xfc}, - {name: "src=SP/dst=X8/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc4}, - {name: "src=SP/dst=X9/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xcc}, - {name: "src=SP/dst=X10/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xd4}, - {name: "src=SP/dst=X11/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xdc}, - {name: "src=SP/dst=X12/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xe4}, - {name: "src=SP/dst=X13/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xec}, - {name: "src=SP/dst=X14/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf4}, - {name: "src=SP/dst=X15/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xfc}, - {name: "src=BP/dst=X0/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc5}, - {name: "src=BP/dst=X1/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xcd}, - {name: "src=BP/dst=X2/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xd5}, - {name: "src=BP/dst=X3/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xdd}, - {name: "src=BP/dst=X4/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe5}, - {name: "src=BP/dst=X5/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xed}, - {name: "src=BP/dst=X6/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf5}, - {name: "src=BP/dst=X7/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xfd}, - {name: "src=BP/dst=X8/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc5}, - {name: "src=BP/dst=X9/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xcd}, - {name: "src=BP/dst=X10/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xd5}, - {name: "src=BP/dst=X11/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xdd}, - {name: "src=BP/dst=X12/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xe5}, - {name: "src=BP/dst=X13/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xed}, - {name: "src=BP/dst=X14/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf5}, - {name: "src=BP/dst=X15/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xfd}, - {name: "src=SI/dst=X0/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc6}, - {name: "src=SI/dst=X1/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xce}, - {name: "src=SI/dst=X2/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xd6}, - {name: "src=SI/dst=X3/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xde}, - {name: "src=SI/dst=X4/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe6}, - {name: "src=SI/dst=X5/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xee}, - {name: "src=SI/dst=X6/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf6}, - {name: "src=SI/dst=X7/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xfe}, - {name: "src=SI/dst=X8/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc6}, - {name: "src=SI/dst=X9/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xce}, - {name: "src=SI/dst=X10/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xd6}, - {name: "src=SI/dst=X11/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xde}, - {name: "src=SI/dst=X12/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xe6}, - {name: "src=SI/dst=X13/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xee}, - {name: "src=SI/dst=X14/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf6}, - {name: "src=SI/dst=X15/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xfe}, - {name: "src=DI/dst=X0/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc7}, - {name: "src=DI/dst=X1/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xcf}, - {name: "src=DI/dst=X2/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xd7}, - {name: "src=DI/dst=X3/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xdf}, - {name: "src=DI/dst=X4/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe7}, - {name: "src=DI/dst=X5/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xef}, - {name: "src=DI/dst=X6/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf7}, - {name: "src=DI/dst=X7/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xff}, - {name: "src=DI/dst=X8/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc7}, - {name: "src=DI/dst=X9/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xcf}, - {name: "src=DI/dst=X10/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xd7}, - {name: "src=DI/dst=X11/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xdf}, - {name: "src=DI/dst=X12/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xe7}, - {name: "src=DI/dst=X13/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xef}, - {name: "src=DI/dst=X14/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf7}, - {name: "src=DI/dst=X15/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xff}, - {name: "src=R8/dst=X0/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc0}, - {name: "src=R8/dst=X1/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc8}, - {name: "src=R8/dst=X2/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xd0}, - {name: "src=R8/dst=X3/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xd8}, - {name: "src=R8/dst=X4/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe0}, - {name: "src=R8/dst=X5/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe8}, - {name: "src=R8/dst=X6/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf0}, - {name: "src=R8/dst=X7/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf8}, - {name: "src=R8/dst=X8/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc0}, - {name: "src=R8/dst=X9/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc8}, - {name: "src=R8/dst=X10/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xd0}, - {name: "src=R8/dst=X11/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xd8}, - {name: "src=R8/dst=X12/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xe0}, - {name: "src=R8/dst=X13/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xe8}, - {name: "src=R8/dst=X14/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf0}, - {name: "src=R8/dst=X15/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf8}, - {name: "src=R9/dst=X0/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc1}, - {name: "src=R9/dst=X1/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc9}, - {name: "src=R9/dst=X2/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xd1}, - {name: "src=R9/dst=X3/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xd9}, - {name: "src=R9/dst=X4/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe1}, - {name: "src=R9/dst=X5/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe9}, - {name: "src=R9/dst=X6/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf1}, - {name: "src=R9/dst=X7/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf9}, - {name: "src=R9/dst=X8/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc1}, - {name: "src=R9/dst=X9/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc9}, - {name: "src=R9/dst=X10/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xd1}, - {name: "src=R9/dst=X11/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xd9}, - {name: "src=R9/dst=X12/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xe1}, - {name: "src=R9/dst=X13/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xe9}, - {name: "src=R9/dst=X14/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf1}, - {name: "src=R9/dst=X15/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf9}, - {name: "src=R13/dst=X0/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc5}, - {name: "src=R13/dst=X1/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xcd}, - {name: "src=R13/dst=X2/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xd5}, - {name: "src=R13/dst=X3/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xdd}, - {name: "src=R13/dst=X4/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe5}, - {name: "src=R13/dst=X5/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xed}, - {name: "src=R13/dst=X6/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf5}, - {name: "src=R13/dst=X7/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xfd}, - {name: "src=R13/dst=X8/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc5}, - {name: "src=R13/dst=X9/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xcd}, - {name: "src=R13/dst=X10/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xd5}, - {name: "src=R13/dst=X11/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xdd}, - {name: "src=R13/dst=X12/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xe5}, - {name: "src=R13/dst=X13/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xed}, - {name: "src=R13/dst=X14/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf5}, - {name: "src=R13/dst=X15/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xfd}, - {name: "src=R14/dst=X0/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc6}, - {name: "src=R14/dst=X1/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xce}, - {name: "src=R14/dst=X2/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xd6}, - {name: "src=R14/dst=X3/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xde}, - {name: "src=R14/dst=X4/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe6}, - {name: "src=R14/dst=X5/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xee}, - {name: "src=R14/dst=X6/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf6}, - {name: "src=R14/dst=X7/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xfe}, - {name: "src=R14/dst=X8/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc6}, - {name: "src=R14/dst=X9/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xce}, - {name: "src=R14/dst=X10/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xd6}, - {name: "src=R14/dst=X11/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xde}, - {name: "src=R14/dst=X12/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xe6}, - {name: "src=R14/dst=X13/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xee}, - {name: "src=R14/dst=X14/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf6}, - {name: "src=R14/dst=X15/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xfe}, - {name: "src=R15/dst=X0/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc7}, - {name: "src=R15/dst=X1/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xcf}, - {name: "src=R15/dst=X2/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xd7}, - {name: "src=R15/dst=X3/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xdf}, - {name: "src=R15/dst=X4/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe7}, - {name: "src=R15/dst=X5/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xef}, - {name: "src=R15/dst=X6/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf7}, - {name: "src=R15/dst=X7/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xff}, - {name: "src=R15/dst=X8/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc7}, - {name: "src=R15/dst=X9/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xcf}, - {name: "src=R15/dst=X10/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xd7}, - {name: "src=R15/dst=X11/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xdf}, - {name: "src=R15/dst=X12/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xe7}, - {name: "src=R15/dst=X13/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xef}, - {name: "src=R15/dst=X14/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf7}, - {name: "src=R15/dst=X15/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xff}, - } - - for _, tc := range tests { - n := nodeImpl{srcReg: tc.srcReg, dstReg: tc.dstReg} - rexPrefix, modRM, err := n.getRegisterToRegisterModRM(tc.srcOnModRMReg) - require.NoError(t, err, tc.name) - require.Equal(t, tc.expRexPrefix, rexPrefix, tc.name) - require.Equal(t, tc.expModRM, modRM, tc.name) - } -} diff --git a/internal/asm/amd64/impl_5_test.go b/internal/asm/amd64/impl_5_test.go deleted file mode 100644 index bac9875341..0000000000 --- a/internal/asm/amd64/impl_5_test.go +++ /dev/null @@ -1,1090 +0,0 @@ -package amd64 - -import ( - "encoding/binary" - "math" - "testing" - - "github.com/tetratelabs/wazero/internal/asm" - "github.com/tetratelabs/wazero/internal/testing/require" -) - -func TestAssemblerImpl_EncodeConstToMemory(t *testing.T) { - t.Run("error", func(t *testing.T) { - tests := []struct { - n *nodeImpl - expErr string - }{ - { - n: &nodeImpl{instruction: ADDL, types: operandTypesConstToMemory, dstReg: RegAX}, - expErr: "ADDL is unsupported for ConstToMemory type", - }, - { - n: &nodeImpl{ - instruction: MOVB, types: operandTypesConstToMemory, - srcConst: math.MaxInt16, - dstReg: RegAX, dstConst: 0xff_ff, - }, - expErr: "too large load target const 32767 for MOVB", - }, - { - n: &nodeImpl{ - instruction: MOVL, types: operandTypesConstToMemory, - srcConst: math.MaxInt64, - dstReg: RegAX, dstConst: 0xff_ff, - }, - expErr: "too large load target const 9223372036854775807 for MOVL", - }, - } - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - for _, tc := range tests { - a := NewAssembler() - buf := code.NextCodeSection() - err := a.encodeConstToMemory(buf, tc.n) - require.EqualError(t, err, tc.expErr) - } - }) - - tests := []struct { - name string - inst asm.Instruction - baseReg asm.Register - c, offset int64 - exp []byte - }{ - {name: "MOVB/c=0/base=AX/offset=0x0", inst: MOVB, c: 0, baseReg: RegAX, offset: 0x0, exp: []byte{0xc6, 0x0, 0x0}}, - {name: "MOVB/c=1/base=AX/offset=0x0", inst: MOVB, c: 1, baseReg: RegAX, offset: 0x0, exp: []byte{0xc6, 0x0, 0x1}}, - {name: "MOVB/c=-1/base=AX/offset=0x0", inst: MOVB, c: -1, baseReg: RegAX, offset: 0x0, exp: []byte{0xc6, 0x0, 0xff}}, - {name: "MOVB/c=100/base=AX/offset=0x0", inst: MOVB, c: 100, baseReg: RegAX, offset: 0x0, exp: []byte{0xc6, 0x0, 0x64}}, - {name: "MOVB/c=-100/base=AX/offset=0x0", inst: MOVB, c: -100, baseReg: RegAX, offset: 0x0, exp: []byte{0xc6, 0x0, 0x9c}}, - {name: "MOVB/c=127/base=AX/offset=0x0", inst: MOVB, c: 127, baseReg: RegAX, offset: 0x0, exp: []byte{0xc6, 0x0, 0x7f}}, - {name: "MOVB/c=-128/base=AX/offset=0x0", inst: MOVB, c: -128, baseReg: RegAX, offset: 0x0, exp: []byte{0xc6, 0x0, 0x80}}, - {name: "MOVB/c=0/base=AX/offset=0x1", inst: MOVB, c: 0, baseReg: RegAX, offset: 0x1, exp: []byte{0xc6, 0x40, 0x1, 0x0}}, - {name: "MOVB/c=1/base=AX/offset=0x1", inst: MOVB, c: 1, baseReg: RegAX, offset: 0x1, exp: []byte{0xc6, 0x40, 0x1, 0x1}}, - {name: "MOVB/c=-1/base=AX/offset=0x1", inst: MOVB, c: -1, baseReg: RegAX, offset: 0x1, exp: []byte{0xc6, 0x40, 0x1, 0xff}}, - {name: "MOVB/c=100/base=AX/offset=0x1", inst: MOVB, c: 100, baseReg: RegAX, offset: 0x1, exp: []byte{0xc6, 0x40, 0x1, 0x64}}, - {name: "MOVB/c=-100/base=AX/offset=0x1", inst: MOVB, c: -100, baseReg: RegAX, offset: 0x1, exp: []byte{0xc6, 0x40, 0x1, 0x9c}}, - {name: "MOVB/c=127/base=AX/offset=0x1", inst: MOVB, c: 127, baseReg: RegAX, offset: 0x1, exp: []byte{0xc6, 0x40, 0x1, 0x7f}}, - {name: "MOVB/c=-128/base=AX/offset=0x1", inst: MOVB, c: -128, baseReg: RegAX, offset: 0x1, exp: []byte{0xc6, 0x40, 0x1, 0x80}}, - {name: "MOVB/c=0/base=AX/offset=-0x1", inst: MOVB, c: 0, baseReg: RegAX, offset: -0x1, exp: []byte{0xc6, 0x40, 0xff, 0x0}}, - {name: "MOVB/c=1/base=AX/offset=-0x1", inst: MOVB, c: 1, baseReg: RegAX, offset: -0x1, exp: []byte{0xc6, 0x40, 0xff, 0x1}}, - {name: "MOVB/c=-1/base=AX/offset=-0x1", inst: MOVB, c: -1, baseReg: RegAX, offset: -0x1, exp: []byte{0xc6, 0x40, 0xff, 0xff}}, - {name: "MOVB/c=100/base=AX/offset=-0x1", inst: MOVB, c: 100, baseReg: RegAX, offset: -0x1, exp: []byte{0xc6, 0x40, 0xff, 0x64}}, - {name: "MOVB/c=-100/base=AX/offset=-0x1", inst: MOVB, c: -100, baseReg: RegAX, offset: -0x1, exp: []byte{0xc6, 0x40, 0xff, 0x9c}}, - {name: "MOVB/c=127/base=AX/offset=-0x1", inst: MOVB, c: 127, baseReg: RegAX, offset: -0x1, exp: []byte{0xc6, 0x40, 0xff, 0x7f}}, - {name: "MOVB/c=-128/base=AX/offset=-0x1", inst: MOVB, c: -128, baseReg: RegAX, offset: -0x1, exp: []byte{0xc6, 0x40, 0xff, 0x80}}, - {name: "MOVB/c=0/base=AX/offset=0x4db", inst: MOVB, c: 0, baseReg: RegAX, offset: 0x4db, exp: []byte{0xc6, 0x80, 0xdb, 0x4, 0x0, 0x0, 0x0}}, - {name: "MOVB/c=1/base=AX/offset=0x4db", inst: MOVB, c: 1, baseReg: RegAX, offset: 0x4db, exp: []byte{0xc6, 0x80, 0xdb, 0x4, 0x0, 0x0, 0x1}}, - {name: "MOVB/c=-1/base=AX/offset=0x4db", inst: MOVB, c: -1, baseReg: RegAX, offset: 0x4db, exp: []byte{0xc6, 0x80, 0xdb, 0x4, 0x0, 0x0, 0xff}}, - {name: "MOVB/c=100/base=AX/offset=0x4db", inst: MOVB, c: 100, baseReg: RegAX, offset: 0x4db, exp: []byte{0xc6, 0x80, 0xdb, 0x4, 0x0, 0x0, 0x64}}, - {name: "MOVB/c=-100/base=AX/offset=0x4db", inst: MOVB, c: -100, baseReg: RegAX, offset: 0x4db, exp: []byte{0xc6, 0x80, 0xdb, 0x4, 0x0, 0x0, 0x9c}}, - {name: "MOVB/c=127/base=AX/offset=0x4db", inst: MOVB, c: 127, baseReg: RegAX, offset: 0x4db, exp: []byte{0xc6, 0x80, 0xdb, 0x4, 0x0, 0x0, 0x7f}}, - {name: "MOVB/c=-128/base=AX/offset=0x4db", inst: MOVB, c: -128, baseReg: RegAX, offset: 0x4db, exp: []byte{0xc6, 0x80, 0xdb, 0x4, 0x0, 0x0, 0x80}}, - {name: "MOVB/c=0/base=AX/offset=-0x4d2", inst: MOVB, c: 0, baseReg: RegAX, offset: -0x4d2, exp: []byte{0xc6, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0x0}}, - {name: "MOVB/c=1/base=AX/offset=-0x4d2", inst: MOVB, c: 1, baseReg: RegAX, offset: -0x4d2, exp: []byte{0xc6, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0x1}}, - {name: "MOVB/c=-1/base=AX/offset=-0x4d2", inst: MOVB, c: -1, baseReg: RegAX, offset: -0x4d2, exp: []byte{0xc6, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0xff}}, - {name: "MOVB/c=100/base=AX/offset=-0x4d2", inst: MOVB, c: 100, baseReg: RegAX, offset: -0x4d2, exp: []byte{0xc6, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0x64}}, - {name: "MOVB/c=-100/base=AX/offset=-0x4d2", inst: MOVB, c: -100, baseReg: RegAX, offset: -0x4d2, exp: []byte{0xc6, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0x9c}}, - {name: "MOVB/c=127/base=AX/offset=-0x4d2", inst: MOVB, c: 127, baseReg: RegAX, offset: -0x4d2, exp: []byte{0xc6, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0x7f}}, - {name: "MOVB/c=-128/base=AX/offset=-0x4d2", inst: MOVB, c: -128, baseReg: RegAX, offset: -0x4d2, exp: []byte{0xc6, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0x80}}, - {name: "MOVB/c=0/base=AX/offset=0x7fffffff", inst: MOVB, c: 0, baseReg: RegAX, offset: 0x7fffffff, exp: []byte{0xc6, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "MOVB/c=1/base=AX/offset=0x7fffffff", inst: MOVB, c: 1, baseReg: RegAX, offset: 0x7fffffff, exp: []byte{0xc6, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "MOVB/c=-1/base=AX/offset=0x7fffffff", inst: MOVB, c: -1, baseReg: RegAX, offset: 0x7fffffff, exp: []byte{0xc6, 0x80, 0xff, 0xff, 0xff, 0x7f, 0xff}}, - {name: "MOVB/c=100/base=AX/offset=0x7fffffff", inst: MOVB, c: 100, baseReg: RegAX, offset: 0x7fffffff, exp: []byte{0xc6, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x64}}, - {name: "MOVB/c=-100/base=AX/offset=0x7fffffff", inst: MOVB, c: -100, baseReg: RegAX, offset: 0x7fffffff, exp: []byte{0xc6, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x9c}}, - {name: "MOVB/c=127/base=AX/offset=0x7fffffff", inst: MOVB, c: 127, baseReg: RegAX, offset: 0x7fffffff, exp: []byte{0xc6, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x7f}}, - {name: "MOVB/c=-128/base=AX/offset=0x7fffffff", inst: MOVB, c: -128, baseReg: RegAX, offset: 0x7fffffff, exp: []byte{0xc6, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x80}}, - {name: "MOVB/c=0/base=AX/offset=-0x80000000", inst: MOVB, c: 0, baseReg: RegAX, offset: -0x80000000, exp: []byte{0xc6, 0x80, 0x0, 0x0, 0x0, 0x80, 0x0}}, - {name: "MOVB/c=1/base=AX/offset=-0x80000000", inst: MOVB, c: 1, baseReg: RegAX, offset: -0x80000000, exp: []byte{0xc6, 0x80, 0x0, 0x0, 0x0, 0x80, 0x1}}, - {name: "MOVB/c=-1/base=AX/offset=-0x80000000", inst: MOVB, c: -1, baseReg: RegAX, offset: -0x80000000, exp: []byte{0xc6, 0x80, 0x0, 0x0, 0x0, 0x80, 0xff}}, - {name: "MOVB/c=100/base=AX/offset=-0x80000000", inst: MOVB, c: 100, baseReg: RegAX, offset: -0x80000000, exp: []byte{0xc6, 0x80, 0x0, 0x0, 0x0, 0x80, 0x64}}, - {name: "MOVB/c=-100/base=AX/offset=-0x80000000", inst: MOVB, c: -100, baseReg: RegAX, offset: -0x80000000, exp: []byte{0xc6, 0x80, 0x0, 0x0, 0x0, 0x80, 0x9c}}, - {name: "MOVB/c=127/base=AX/offset=-0x80000000", inst: MOVB, c: 127, baseReg: RegAX, offset: -0x80000000, exp: []byte{0xc6, 0x80, 0x0, 0x0, 0x0, 0x80, 0x7f}}, - {name: "MOVB/c=-128/base=AX/offset=-0x80000000", inst: MOVB, c: -128, baseReg: RegAX, offset: -0x80000000, exp: []byte{0xc6, 0x80, 0x0, 0x0, 0x0, 0x80, 0x80}}, - {name: "MOVB/c=0/base=AX/offset=0x7fff", inst: MOVB, c: 0, baseReg: RegAX, offset: 0x7fff, exp: []byte{0xc6, 0x80, 0xff, 0x7f, 0x0, 0x0, 0x0}}, - {name: "MOVB/c=1/base=AX/offset=0x7fff", inst: MOVB, c: 1, baseReg: RegAX, offset: 0x7fff, exp: []byte{0xc6, 0x80, 0xff, 0x7f, 0x0, 0x0, 0x1}}, - {name: "MOVB/c=-1/base=AX/offset=0x7fff", inst: MOVB, c: -1, baseReg: RegAX, offset: 0x7fff, exp: []byte{0xc6, 0x80, 0xff, 0x7f, 0x0, 0x0, 0xff}}, - {name: "MOVB/c=100/base=AX/offset=0x7fff", inst: MOVB, c: 100, baseReg: RegAX, offset: 0x7fff, exp: []byte{0xc6, 0x80, 0xff, 0x7f, 0x0, 0x0, 0x64}}, - {name: "MOVB/c=-100/base=AX/offset=0x7fff", inst: MOVB, c: -100, baseReg: RegAX, offset: 0x7fff, exp: []byte{0xc6, 0x80, 0xff, 0x7f, 0x0, 0x0, 0x9c}}, - {name: "MOVB/c=127/base=AX/offset=0x7fff", inst: MOVB, c: 127, baseReg: RegAX, offset: 0x7fff, exp: []byte{0xc6, 0x80, 0xff, 0x7f, 0x0, 0x0, 0x7f}}, - {name: "MOVB/c=-128/base=AX/offset=0x7fff", inst: MOVB, c: -128, baseReg: RegAX, offset: 0x7fff, exp: []byte{0xc6, 0x80, 0xff, 0x7f, 0x0, 0x0, 0x80}}, - {name: "MOVB/c=0/base=AX/offset=-0x8000", inst: MOVB, c: 0, baseReg: RegAX, offset: -0x8000, exp: []byte{0xc6, 0x80, 0x0, 0x80, 0xff, 0xff, 0x0}}, - {name: "MOVB/c=1/base=AX/offset=-0x8000", inst: MOVB, c: 1, baseReg: RegAX, offset: -0x8000, exp: []byte{0xc6, 0x80, 0x0, 0x80, 0xff, 0xff, 0x1}}, - {name: "MOVB/c=-1/base=AX/offset=-0x8000", inst: MOVB, c: -1, baseReg: RegAX, offset: -0x8000, exp: []byte{0xc6, 0x80, 0x0, 0x80, 0xff, 0xff, 0xff}}, - {name: "MOVB/c=100/base=AX/offset=-0x8000", inst: MOVB, c: 100, baseReg: RegAX, offset: -0x8000, exp: []byte{0xc6, 0x80, 0x0, 0x80, 0xff, 0xff, 0x64}}, - {name: "MOVB/c=-100/base=AX/offset=-0x8000", inst: MOVB, c: -100, baseReg: RegAX, offset: -0x8000, exp: []byte{0xc6, 0x80, 0x0, 0x80, 0xff, 0xff, 0x9c}}, - {name: "MOVB/c=127/base=AX/offset=-0x8000", inst: MOVB, c: 127, baseReg: RegAX, offset: -0x8000, exp: []byte{0xc6, 0x80, 0x0, 0x80, 0xff, 0xff, 0x7f}}, - {name: "MOVB/c=-128/base=AX/offset=-0x8000", inst: MOVB, c: -128, baseReg: RegAX, offset: -0x8000, exp: []byte{0xc6, 0x80, 0x0, 0x80, 0xff, 0xff, 0x80}}, - {name: "MOVB/c=0/base=R8/offset=0x0", inst: MOVB, c: 0, baseReg: RegR8, offset: 0x0, exp: []byte{0x41, 0xc6, 0x0, 0x0}}, - {name: "MOVB/c=1/base=R8/offset=0x0", inst: MOVB, c: 1, baseReg: RegR8, offset: 0x0, exp: []byte{0x41, 0xc6, 0x0, 0x1}}, - {name: "MOVB/c=-1/base=R8/offset=0x0", inst: MOVB, c: -1, baseReg: RegR8, offset: 0x0, exp: []byte{0x41, 0xc6, 0x0, 0xff}}, - {name: "MOVB/c=100/base=R8/offset=0x0", inst: MOVB, c: 100, baseReg: RegR8, offset: 0x0, exp: []byte{0x41, 0xc6, 0x0, 0x64}}, - {name: "MOVB/c=-100/base=R8/offset=0x0", inst: MOVB, c: -100, baseReg: RegR8, offset: 0x0, exp: []byte{0x41, 0xc6, 0x0, 0x9c}}, - {name: "MOVB/c=127/base=R8/offset=0x0", inst: MOVB, c: 127, baseReg: RegR8, offset: 0x0, exp: []byte{0x41, 0xc6, 0x0, 0x7f}}, - {name: "MOVB/c=-128/base=R8/offset=0x0", inst: MOVB, c: -128, baseReg: RegR8, offset: 0x0, exp: []byte{0x41, 0xc6, 0x0, 0x80}}, - {name: "MOVB/c=0/base=R8/offset=0x1", inst: MOVB, c: 0, baseReg: RegR8, offset: 0x1, exp: []byte{0x41, 0xc6, 0x40, 0x1, 0x0}}, - {name: "MOVB/c=1/base=R8/offset=0x1", inst: MOVB, c: 1, baseReg: RegR8, offset: 0x1, exp: []byte{0x41, 0xc6, 0x40, 0x1, 0x1}}, - {name: "MOVB/c=-1/base=R8/offset=0x1", inst: MOVB, c: -1, baseReg: RegR8, offset: 0x1, exp: []byte{0x41, 0xc6, 0x40, 0x1, 0xff}}, - {name: "MOVB/c=100/base=R8/offset=0x1", inst: MOVB, c: 100, baseReg: RegR8, offset: 0x1, exp: []byte{0x41, 0xc6, 0x40, 0x1, 0x64}}, - {name: "MOVB/c=-100/base=R8/offset=0x1", inst: MOVB, c: -100, baseReg: RegR8, offset: 0x1, exp: []byte{0x41, 0xc6, 0x40, 0x1, 0x9c}}, - {name: "MOVB/c=127/base=R8/offset=0x1", inst: MOVB, c: 127, baseReg: RegR8, offset: 0x1, exp: []byte{0x41, 0xc6, 0x40, 0x1, 0x7f}}, - {name: "MOVB/c=-128/base=R8/offset=0x1", inst: MOVB, c: -128, baseReg: RegR8, offset: 0x1, exp: []byte{0x41, 0xc6, 0x40, 0x1, 0x80}}, - {name: "MOVB/c=0/base=R8/offset=-0x1", inst: MOVB, c: 0, baseReg: RegR8, offset: -0x1, exp: []byte{0x41, 0xc6, 0x40, 0xff, 0x0}}, - {name: "MOVB/c=1/base=R8/offset=-0x1", inst: MOVB, c: 1, baseReg: RegR8, offset: -0x1, exp: []byte{0x41, 0xc6, 0x40, 0xff, 0x1}}, - {name: "MOVB/c=-1/base=R8/offset=-0x1", inst: MOVB, c: -1, baseReg: RegR8, offset: -0x1, exp: []byte{0x41, 0xc6, 0x40, 0xff, 0xff}}, - {name: "MOVB/c=100/base=R8/offset=-0x1", inst: MOVB, c: 100, baseReg: RegR8, offset: -0x1, exp: []byte{0x41, 0xc6, 0x40, 0xff, 0x64}}, - {name: "MOVB/c=-100/base=R8/offset=-0x1", inst: MOVB, c: -100, baseReg: RegR8, offset: -0x1, exp: []byte{0x41, 0xc6, 0x40, 0xff, 0x9c}}, - {name: "MOVB/c=127/base=R8/offset=-0x1", inst: MOVB, c: 127, baseReg: RegR8, offset: -0x1, exp: []byte{0x41, 0xc6, 0x40, 0xff, 0x7f}}, - {name: "MOVB/c=-128/base=R8/offset=-0x1", inst: MOVB, c: -128, baseReg: RegR8, offset: -0x1, exp: []byte{0x41, 0xc6, 0x40, 0xff, 0x80}}, - {name: "MOVB/c=0/base=R8/offset=0x4db", inst: MOVB, c: 0, baseReg: RegR8, offset: 0x4db, exp: []byte{0x41, 0xc6, 0x80, 0xdb, 0x4, 0x0, 0x0, 0x0}}, - {name: "MOVB/c=1/base=R8/offset=0x4db", inst: MOVB, c: 1, baseReg: RegR8, offset: 0x4db, exp: []byte{0x41, 0xc6, 0x80, 0xdb, 0x4, 0x0, 0x0, 0x1}}, - {name: "MOVB/c=-1/base=R8/offset=0x4db", inst: MOVB, c: -1, baseReg: RegR8, offset: 0x4db, exp: []byte{0x41, 0xc6, 0x80, 0xdb, 0x4, 0x0, 0x0, 0xff}}, - {name: "MOVB/c=100/base=R8/offset=0x4db", inst: MOVB, c: 100, baseReg: RegR8, offset: 0x4db, exp: []byte{0x41, 0xc6, 0x80, 0xdb, 0x4, 0x0, 0x0, 0x64}}, - {name: "MOVB/c=-100/base=R8/offset=0x4db", inst: MOVB, c: -100, baseReg: RegR8, offset: 0x4db, exp: []byte{0x41, 0xc6, 0x80, 0xdb, 0x4, 0x0, 0x0, 0x9c}}, - {name: "MOVB/c=127/base=R8/offset=0x4db", inst: MOVB, c: 127, baseReg: RegR8, offset: 0x4db, exp: []byte{0x41, 0xc6, 0x80, 0xdb, 0x4, 0x0, 0x0, 0x7f}}, - {name: "MOVB/c=-128/base=R8/offset=0x4db", inst: MOVB, c: -128, baseReg: RegR8, offset: 0x4db, exp: []byte{0x41, 0xc6, 0x80, 0xdb, 0x4, 0x0, 0x0, 0x80}}, - {name: "MOVB/c=0/base=R8/offset=-0x4d2", inst: MOVB, c: 0, baseReg: RegR8, offset: -0x4d2, exp: []byte{0x41, 0xc6, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0x0}}, - {name: "MOVB/c=1/base=R8/offset=-0x4d2", inst: MOVB, c: 1, baseReg: RegR8, offset: -0x4d2, exp: []byte{0x41, 0xc6, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0x1}}, - {name: "MOVB/c=-1/base=R8/offset=-0x4d2", inst: MOVB, c: -1, baseReg: RegR8, offset: -0x4d2, exp: []byte{0x41, 0xc6, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0xff}}, - {name: "MOVB/c=100/base=R8/offset=-0x4d2", inst: MOVB, c: 100, baseReg: RegR8, offset: -0x4d2, exp: []byte{0x41, 0xc6, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0x64}}, - {name: "MOVB/c=-100/base=R8/offset=-0x4d2", inst: MOVB, c: -100, baseReg: RegR8, offset: -0x4d2, exp: []byte{0x41, 0xc6, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0x9c}}, - {name: "MOVB/c=127/base=R8/offset=-0x4d2", inst: MOVB, c: 127, baseReg: RegR8, offset: -0x4d2, exp: []byte{0x41, 0xc6, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0x7f}}, - {name: "MOVB/c=-128/base=R8/offset=-0x4d2", inst: MOVB, c: -128, baseReg: RegR8, offset: -0x4d2, exp: []byte{0x41, 0xc6, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0x80}}, - {name: "MOVB/c=0/base=R8/offset=0x7fffffff", inst: MOVB, c: 0, baseReg: RegR8, offset: 0x7fffffff, exp: []byte{0x41, 0xc6, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "MOVB/c=1/base=R8/offset=0x7fffffff", inst: MOVB, c: 1, baseReg: RegR8, offset: 0x7fffffff, exp: []byte{0x41, 0xc6, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "MOVB/c=-1/base=R8/offset=0x7fffffff", inst: MOVB, c: -1, baseReg: RegR8, offset: 0x7fffffff, exp: []byte{0x41, 0xc6, 0x80, 0xff, 0xff, 0xff, 0x7f, 0xff}}, - {name: "MOVB/c=100/base=R8/offset=0x7fffffff", inst: MOVB, c: 100, baseReg: RegR8, offset: 0x7fffffff, exp: []byte{0x41, 0xc6, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x64}}, - {name: "MOVB/c=-100/base=R8/offset=0x7fffffff", inst: MOVB, c: -100, baseReg: RegR8, offset: 0x7fffffff, exp: []byte{0x41, 0xc6, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x9c}}, - {name: "MOVB/c=127/base=R8/offset=0x7fffffff", inst: MOVB, c: 127, baseReg: RegR8, offset: 0x7fffffff, exp: []byte{0x41, 0xc6, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x7f}}, - {name: "MOVB/c=-128/base=R8/offset=0x7fffffff", inst: MOVB, c: -128, baseReg: RegR8, offset: 0x7fffffff, exp: []byte{0x41, 0xc6, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x80}}, - {name: "MOVB/c=0/base=R8/offset=-0x80000000", inst: MOVB, c: 0, baseReg: RegR8, offset: -0x80000000, exp: []byte{0x41, 0xc6, 0x80, 0x0, 0x0, 0x0, 0x80, 0x0}}, - {name: "MOVB/c=1/base=R8/offset=-0x80000000", inst: MOVB, c: 1, baseReg: RegR8, offset: -0x80000000, exp: []byte{0x41, 0xc6, 0x80, 0x0, 0x0, 0x0, 0x80, 0x1}}, - {name: "MOVB/c=-1/base=R8/offset=-0x80000000", inst: MOVB, c: -1, baseReg: RegR8, offset: -0x80000000, exp: []byte{0x41, 0xc6, 0x80, 0x0, 0x0, 0x0, 0x80, 0xff}}, - {name: "MOVB/c=100/base=R8/offset=-0x80000000", inst: MOVB, c: 100, baseReg: RegR8, offset: -0x80000000, exp: []byte{0x41, 0xc6, 0x80, 0x0, 0x0, 0x0, 0x80, 0x64}}, - {name: "MOVB/c=-100/base=R8/offset=-0x80000000", inst: MOVB, c: -100, baseReg: RegR8, offset: -0x80000000, exp: []byte{0x41, 0xc6, 0x80, 0x0, 0x0, 0x0, 0x80, 0x9c}}, - {name: "MOVB/c=127/base=R8/offset=-0x80000000", inst: MOVB, c: 127, baseReg: RegR8, offset: -0x80000000, exp: []byte{0x41, 0xc6, 0x80, 0x0, 0x0, 0x0, 0x80, 0x7f}}, - {name: "MOVB/c=-128/base=R8/offset=-0x80000000", inst: MOVB, c: -128, baseReg: RegR8, offset: -0x80000000, exp: []byte{0x41, 0xc6, 0x80, 0x0, 0x0, 0x0, 0x80, 0x80}}, - {name: "MOVB/c=0/base=R8/offset=0x7fff", inst: MOVB, c: 0, baseReg: RegR8, offset: 0x7fff, exp: []byte{0x41, 0xc6, 0x80, 0xff, 0x7f, 0x0, 0x0, 0x0}}, - {name: "MOVB/c=1/base=R8/offset=0x7fff", inst: MOVB, c: 1, baseReg: RegR8, offset: 0x7fff, exp: []byte{0x41, 0xc6, 0x80, 0xff, 0x7f, 0x0, 0x0, 0x1}}, - {name: "MOVB/c=-1/base=R8/offset=0x7fff", inst: MOVB, c: -1, baseReg: RegR8, offset: 0x7fff, exp: []byte{0x41, 0xc6, 0x80, 0xff, 0x7f, 0x0, 0x0, 0xff}}, - {name: "MOVB/c=100/base=R8/offset=0x7fff", inst: MOVB, c: 100, baseReg: RegR8, offset: 0x7fff, exp: []byte{0x41, 0xc6, 0x80, 0xff, 0x7f, 0x0, 0x0, 0x64}}, - {name: "MOVB/c=-100/base=R8/offset=0x7fff", inst: MOVB, c: -100, baseReg: RegR8, offset: 0x7fff, exp: []byte{0x41, 0xc6, 0x80, 0xff, 0x7f, 0x0, 0x0, 0x9c}}, - {name: "MOVB/c=127/base=R8/offset=0x7fff", inst: MOVB, c: 127, baseReg: RegR8, offset: 0x7fff, exp: []byte{0x41, 0xc6, 0x80, 0xff, 0x7f, 0x0, 0x0, 0x7f}}, - {name: "MOVB/c=-128/base=R8/offset=0x7fff", inst: MOVB, c: -128, baseReg: RegR8, offset: 0x7fff, exp: []byte{0x41, 0xc6, 0x80, 0xff, 0x7f, 0x0, 0x0, 0x80}}, - {name: "MOVB/c=0/base=R8/offset=-0x8000", inst: MOVB, c: 0, baseReg: RegR8, offset: -0x8000, exp: []byte{0x41, 0xc6, 0x80, 0x0, 0x80, 0xff, 0xff, 0x0}}, - {name: "MOVB/c=1/base=R8/offset=-0x8000", inst: MOVB, c: 1, baseReg: RegR8, offset: -0x8000, exp: []byte{0x41, 0xc6, 0x80, 0x0, 0x80, 0xff, 0xff, 0x1}}, - {name: "MOVB/c=-1/base=R8/offset=-0x8000", inst: MOVB, c: -1, baseReg: RegR8, offset: -0x8000, exp: []byte{0x41, 0xc6, 0x80, 0x0, 0x80, 0xff, 0xff, 0xff}}, - {name: "MOVB/c=100/base=R8/offset=-0x8000", inst: MOVB, c: 100, baseReg: RegR8, offset: -0x8000, exp: []byte{0x41, 0xc6, 0x80, 0x0, 0x80, 0xff, 0xff, 0x64}}, - {name: "MOVB/c=-100/base=R8/offset=-0x8000", inst: MOVB, c: -100, baseReg: RegR8, offset: -0x8000, exp: []byte{0x41, 0xc6, 0x80, 0x0, 0x80, 0xff, 0xff, 0x9c}}, - {name: "MOVB/c=127/base=R8/offset=-0x8000", inst: MOVB, c: 127, baseReg: RegR8, offset: -0x8000, exp: []byte{0x41, 0xc6, 0x80, 0x0, 0x80, 0xff, 0xff, 0x7f}}, - {name: "MOVB/c=-128/base=R8/offset=-0x8000", inst: MOVB, c: -128, baseReg: RegR8, offset: -0x8000, exp: []byte{0x41, 0xc6, 0x80, 0x0, 0x80, 0xff, 0xff, 0x80}}, - {name: "MOVL/c=0/base=AX/offset=0x0", inst: MOVL, c: 0, baseReg: RegAX, offset: 0x0, exp: []byte{0xc7, 0x0, 0x0, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=1/base=AX/offset=0x0", inst: MOVL, c: 1, baseReg: RegAX, offset: 0x0, exp: []byte{0xc7, 0x0, 0x1, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-1/base=AX/offset=0x0", inst: MOVL, c: -1, baseReg: RegAX, offset: 0x0, exp: []byte{0xc7, 0x0, 0xff, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=100/base=AX/offset=0x0", inst: MOVL, c: 100, baseReg: RegAX, offset: 0x0, exp: []byte{0xc7, 0x0, 0x64, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-100/base=AX/offset=0x0", inst: MOVL, c: -100, baseReg: RegAX, offset: 0x0, exp: []byte{0xc7, 0x0, 0x9c, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=127/base=AX/offset=0x0", inst: MOVL, c: 127, baseReg: RegAX, offset: 0x0, exp: []byte{0xc7, 0x0, 0x7f, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-128/base=AX/offset=0x0", inst: MOVL, c: -128, baseReg: RegAX, offset: 0x0, exp: []byte{0xc7, 0x0, 0x80, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=32767/base=AX/offset=0x0", inst: MOVL, c: 32767, baseReg: RegAX, offset: 0x0, exp: []byte{0xc7, 0x0, 0xff, 0x7f, 0x0, 0x0}}, - {name: "MOVL/c=-32768/base=AX/offset=0x0", inst: MOVL, c: -32768, baseReg: RegAX, offset: 0x0, exp: []byte{0xc7, 0x0, 0x0, 0x80, 0xff, 0xff}}, - {name: "MOVL/c=1048576/base=AX/offset=0x0", inst: MOVL, c: 1048576, baseReg: RegAX, offset: 0x0, exp: []byte{0xc7, 0x0, 0x0, 0x0, 0x10, 0x0}}, - {name: "MOVL/c=-1048576/base=AX/offset=0x0", inst: MOVL, c: -1048576, baseReg: RegAX, offset: 0x0, exp: []byte{0xc7, 0x0, 0x0, 0x0, 0xf0, 0xff}}, - {name: "MOVL/c=2147483647/base=AX/offset=0x0", inst: MOVL, c: 2147483647, baseReg: RegAX, offset: 0x0, exp: []byte{0xc7, 0x0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVL/c=-2147483648/base=AX/offset=0x0", inst: MOVL, c: -2147483648, baseReg: RegAX, offset: 0x0, exp: []byte{0xc7, 0x0, 0x0, 0x0, 0x0, 0x80}}, - {name: "MOVL/c=0/base=AX/offset=0x1", inst: MOVL, c: 0, baseReg: RegAX, offset: 0x1, exp: []byte{0xc7, 0x40, 0x1, 0x0, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=1/base=AX/offset=0x1", inst: MOVL, c: 1, baseReg: RegAX, offset: 0x1, exp: []byte{0xc7, 0x40, 0x1, 0x1, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-1/base=AX/offset=0x1", inst: MOVL, c: -1, baseReg: RegAX, offset: 0x1, exp: []byte{0xc7, 0x40, 0x1, 0xff, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=100/base=AX/offset=0x1", inst: MOVL, c: 100, baseReg: RegAX, offset: 0x1, exp: []byte{0xc7, 0x40, 0x1, 0x64, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-100/base=AX/offset=0x1", inst: MOVL, c: -100, baseReg: RegAX, offset: 0x1, exp: []byte{0xc7, 0x40, 0x1, 0x9c, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=127/base=AX/offset=0x1", inst: MOVL, c: 127, baseReg: RegAX, offset: 0x1, exp: []byte{0xc7, 0x40, 0x1, 0x7f, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-128/base=AX/offset=0x1", inst: MOVL, c: -128, baseReg: RegAX, offset: 0x1, exp: []byte{0xc7, 0x40, 0x1, 0x80, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=32767/base=AX/offset=0x1", inst: MOVL, c: 32767, baseReg: RegAX, offset: 0x1, exp: []byte{0xc7, 0x40, 0x1, 0xff, 0x7f, 0x0, 0x0}}, - {name: "MOVL/c=-32768/base=AX/offset=0x1", inst: MOVL, c: -32768, baseReg: RegAX, offset: 0x1, exp: []byte{0xc7, 0x40, 0x1, 0x0, 0x80, 0xff, 0xff}}, - {name: "MOVL/c=1048576/base=AX/offset=0x1", inst: MOVL, c: 1048576, baseReg: RegAX, offset: 0x1, exp: []byte{0xc7, 0x40, 0x1, 0x0, 0x0, 0x10, 0x0}}, - {name: "MOVL/c=-1048576/base=AX/offset=0x1", inst: MOVL, c: -1048576, baseReg: RegAX, offset: 0x1, exp: []byte{0xc7, 0x40, 0x1, 0x0, 0x0, 0xf0, 0xff}}, - {name: "MOVL/c=2147483647/base=AX/offset=0x1", inst: MOVL, c: 2147483647, baseReg: RegAX, offset: 0x1, exp: []byte{0xc7, 0x40, 0x1, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVL/c=-2147483648/base=AX/offset=0x1", inst: MOVL, c: -2147483648, baseReg: RegAX, offset: 0x1, exp: []byte{0xc7, 0x40, 0x1, 0x0, 0x0, 0x0, 0x80}}, - {name: "MOVL/c=0/base=AX/offset=-0x1", inst: MOVL, c: 0, baseReg: RegAX, offset: -0x1, exp: []byte{0xc7, 0x40, 0xff, 0x0, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=1/base=AX/offset=-0x1", inst: MOVL, c: 1, baseReg: RegAX, offset: -0x1, exp: []byte{0xc7, 0x40, 0xff, 0x1, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-1/base=AX/offset=-0x1", inst: MOVL, c: -1, baseReg: RegAX, offset: -0x1, exp: []byte{0xc7, 0x40, 0xff, 0xff, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=100/base=AX/offset=-0x1", inst: MOVL, c: 100, baseReg: RegAX, offset: -0x1, exp: []byte{0xc7, 0x40, 0xff, 0x64, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-100/base=AX/offset=-0x1", inst: MOVL, c: -100, baseReg: RegAX, offset: -0x1, exp: []byte{0xc7, 0x40, 0xff, 0x9c, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=127/base=AX/offset=-0x1", inst: MOVL, c: 127, baseReg: RegAX, offset: -0x1, exp: []byte{0xc7, 0x40, 0xff, 0x7f, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-128/base=AX/offset=-0x1", inst: MOVL, c: -128, baseReg: RegAX, offset: -0x1, exp: []byte{0xc7, 0x40, 0xff, 0x80, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=32767/base=AX/offset=-0x1", inst: MOVL, c: 32767, baseReg: RegAX, offset: -0x1, exp: []byte{0xc7, 0x40, 0xff, 0xff, 0x7f, 0x0, 0x0}}, - {name: "MOVL/c=-32768/base=AX/offset=-0x1", inst: MOVL, c: -32768, baseReg: RegAX, offset: -0x1, exp: []byte{0xc7, 0x40, 0xff, 0x0, 0x80, 0xff, 0xff}}, - {name: "MOVL/c=1048576/base=AX/offset=-0x1", inst: MOVL, c: 1048576, baseReg: RegAX, offset: -0x1, exp: []byte{0xc7, 0x40, 0xff, 0x0, 0x0, 0x10, 0x0}}, - {name: "MOVL/c=-1048576/base=AX/offset=-0x1", inst: MOVL, c: -1048576, baseReg: RegAX, offset: -0x1, exp: []byte{0xc7, 0x40, 0xff, 0x0, 0x0, 0xf0, 0xff}}, - {name: "MOVL/c=2147483647/base=AX/offset=-0x1", inst: MOVL, c: 2147483647, baseReg: RegAX, offset: -0x1, exp: []byte{0xc7, 0x40, 0xff, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVL/c=-2147483648/base=AX/offset=-0x1", inst: MOVL, c: -2147483648, baseReg: RegAX, offset: -0x1, exp: []byte{0xc7, 0x40, 0xff, 0x0, 0x0, 0x0, 0x80}}, - {name: "MOVL/c=0/base=AX/offset=0x4db", inst: MOVL, c: 0, baseReg: RegAX, offset: 0x4db, exp: []byte{0xc7, 0x80, 0xdb, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=1/base=AX/offset=0x4db", inst: MOVL, c: 1, baseReg: RegAX, offset: 0x4db, exp: []byte{0xc7, 0x80, 0xdb, 0x4, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-1/base=AX/offset=0x4db", inst: MOVL, c: -1, baseReg: RegAX, offset: 0x4db, exp: []byte{0xc7, 0x80, 0xdb, 0x4, 0x0, 0x0, 0xff, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=100/base=AX/offset=0x4db", inst: MOVL, c: 100, baseReg: RegAX, offset: 0x4db, exp: []byte{0xc7, 0x80, 0xdb, 0x4, 0x0, 0x0, 0x64, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-100/base=AX/offset=0x4db", inst: MOVL, c: -100, baseReg: RegAX, offset: 0x4db, exp: []byte{0xc7, 0x80, 0xdb, 0x4, 0x0, 0x0, 0x9c, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=127/base=AX/offset=0x4db", inst: MOVL, c: 127, baseReg: RegAX, offset: 0x4db, exp: []byte{0xc7, 0x80, 0xdb, 0x4, 0x0, 0x0, 0x7f, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-128/base=AX/offset=0x4db", inst: MOVL, c: -128, baseReg: RegAX, offset: 0x4db, exp: []byte{0xc7, 0x80, 0xdb, 0x4, 0x0, 0x0, 0x80, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=32767/base=AX/offset=0x4db", inst: MOVL, c: 32767, baseReg: RegAX, offset: 0x4db, exp: []byte{0xc7, 0x80, 0xdb, 0x4, 0x0, 0x0, 0xff, 0x7f, 0x0, 0x0}}, - {name: "MOVL/c=-32768/base=AX/offset=0x4db", inst: MOVL, c: -32768, baseReg: RegAX, offset: 0x4db, exp: []byte{0xc7, 0x80, 0xdb, 0x4, 0x0, 0x0, 0x0, 0x80, 0xff, 0xff}}, - {name: "MOVL/c=1048576/base=AX/offset=0x4db", inst: MOVL, c: 1048576, baseReg: RegAX, offset: 0x4db, exp: []byte{0xc7, 0x80, 0xdb, 0x4, 0x0, 0x0, 0x0, 0x0, 0x10, 0x0}}, - {name: "MOVL/c=-1048576/base=AX/offset=0x4db", inst: MOVL, c: -1048576, baseReg: RegAX, offset: 0x4db, exp: []byte{0xc7, 0x80, 0xdb, 0x4, 0x0, 0x0, 0x0, 0x0, 0xf0, 0xff}}, - {name: "MOVL/c=2147483647/base=AX/offset=0x4db", inst: MOVL, c: 2147483647, baseReg: RegAX, offset: 0x4db, exp: []byte{0xc7, 0x80, 0xdb, 0x4, 0x0, 0x0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVL/c=-2147483648/base=AX/offset=0x4db", inst: MOVL, c: -2147483648, baseReg: RegAX, offset: 0x4db, exp: []byte{0xc7, 0x80, 0xdb, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80}}, - {name: "MOVL/c=0/base=AX/offset=-0x4d2", inst: MOVL, c: 0, baseReg: RegAX, offset: -0x4d2, exp: []byte{0xc7, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0x0, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=1/base=AX/offset=-0x4d2", inst: MOVL, c: 1, baseReg: RegAX, offset: -0x4d2, exp: []byte{0xc7, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0x1, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-1/base=AX/offset=-0x4d2", inst: MOVL, c: -1, baseReg: RegAX, offset: -0x4d2, exp: []byte{0xc7, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=100/base=AX/offset=-0x4d2", inst: MOVL, c: 100, baseReg: RegAX, offset: -0x4d2, exp: []byte{0xc7, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0x64, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-100/base=AX/offset=-0x4d2", inst: MOVL, c: -100, baseReg: RegAX, offset: -0x4d2, exp: []byte{0xc7, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0x9c, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=127/base=AX/offset=-0x4d2", inst: MOVL, c: 127, baseReg: RegAX, offset: -0x4d2, exp: []byte{0xc7, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0x7f, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-128/base=AX/offset=-0x4d2", inst: MOVL, c: -128, baseReg: RegAX, offset: -0x4d2, exp: []byte{0xc7, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0x80, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=32767/base=AX/offset=-0x4d2", inst: MOVL, c: 32767, baseReg: RegAX, offset: -0x4d2, exp: []byte{0xc7, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0xff, 0x7f, 0x0, 0x0}}, - {name: "MOVL/c=-32768/base=AX/offset=-0x4d2", inst: MOVL, c: -32768, baseReg: RegAX, offset: -0x4d2, exp: []byte{0xc7, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0x0, 0x80, 0xff, 0xff}}, - {name: "MOVL/c=1048576/base=AX/offset=-0x4d2", inst: MOVL, c: 1048576, baseReg: RegAX, offset: -0x4d2, exp: []byte{0xc7, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0x0, 0x0, 0x10, 0x0}}, - {name: "MOVL/c=-1048576/base=AX/offset=-0x4d2", inst: MOVL, c: -1048576, baseReg: RegAX, offset: -0x4d2, exp: []byte{0xc7, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0x0, 0x0, 0xf0, 0xff}}, - {name: "MOVL/c=2147483647/base=AX/offset=-0x4d2", inst: MOVL, c: 2147483647, baseReg: RegAX, offset: -0x4d2, exp: []byte{0xc7, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVL/c=-2147483648/base=AX/offset=-0x4d2", inst: MOVL, c: -2147483648, baseReg: RegAX, offset: -0x4d2, exp: []byte{0xc7, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0x0, 0x0, 0x0, 0x80}}, - {name: "MOVL/c=0/base=AX/offset=0x7fffffff", inst: MOVL, c: 0, baseReg: RegAX, offset: 0x7fffffff, exp: []byte{0xc7, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x0, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=1/base=AX/offset=0x7fffffff", inst: MOVL, c: 1, baseReg: RegAX, offset: 0x7fffffff, exp: []byte{0xc7, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x1, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-1/base=AX/offset=0x7fffffff", inst: MOVL, c: -1, baseReg: RegAX, offset: 0x7fffffff, exp: []byte{0xc7, 0x80, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=100/base=AX/offset=0x7fffffff", inst: MOVL, c: 100, baseReg: RegAX, offset: 0x7fffffff, exp: []byte{0xc7, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x64, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-100/base=AX/offset=0x7fffffff", inst: MOVL, c: -100, baseReg: RegAX, offset: 0x7fffffff, exp: []byte{0xc7, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x9c, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=127/base=AX/offset=0x7fffffff", inst: MOVL, c: 127, baseReg: RegAX, offset: 0x7fffffff, exp: []byte{0xc7, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x7f, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-128/base=AX/offset=0x7fffffff", inst: MOVL, c: -128, baseReg: RegAX, offset: 0x7fffffff, exp: []byte{0xc7, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x80, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=32767/base=AX/offset=0x7fffffff", inst: MOVL, c: 32767, baseReg: RegAX, offset: 0x7fffffff, exp: []byte{0xc7, 0x80, 0xff, 0xff, 0xff, 0x7f, 0xff, 0x7f, 0x0, 0x0}}, - {name: "MOVL/c=-32768/base=AX/offset=0x7fffffff", inst: MOVL, c: -32768, baseReg: RegAX, offset: 0x7fffffff, exp: []byte{0xc7, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x0, 0x80, 0xff, 0xff}}, - {name: "MOVL/c=1048576/base=AX/offset=0x7fffffff", inst: MOVL, c: 1048576, baseReg: RegAX, offset: 0x7fffffff, exp: []byte{0xc7, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x0, 0x0, 0x10, 0x0}}, - {name: "MOVL/c=-1048576/base=AX/offset=0x7fffffff", inst: MOVL, c: -1048576, baseReg: RegAX, offset: 0x7fffffff, exp: []byte{0xc7, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x0, 0x0, 0xf0, 0xff}}, - {name: "MOVL/c=2147483647/base=AX/offset=0x7fffffff", inst: MOVL, c: 2147483647, baseReg: RegAX, offset: 0x7fffffff, exp: []byte{0xc7, 0x80, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVL/c=-2147483648/base=AX/offset=0x7fffffff", inst: MOVL, c: -2147483648, baseReg: RegAX, offset: 0x7fffffff, exp: []byte{0xc7, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x0, 0x0, 0x0, 0x80}}, - {name: "MOVL/c=0/base=AX/offset=-0x80000000", inst: MOVL, c: 0, baseReg: RegAX, offset: -0x80000000, exp: []byte{0xc7, 0x80, 0x0, 0x0, 0x0, 0x80, 0x0, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=1/base=AX/offset=-0x80000000", inst: MOVL, c: 1, baseReg: RegAX, offset: -0x80000000, exp: []byte{0xc7, 0x80, 0x0, 0x0, 0x0, 0x80, 0x1, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-1/base=AX/offset=-0x80000000", inst: MOVL, c: -1, baseReg: RegAX, offset: -0x80000000, exp: []byte{0xc7, 0x80, 0x0, 0x0, 0x0, 0x80, 0xff, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=100/base=AX/offset=-0x80000000", inst: MOVL, c: 100, baseReg: RegAX, offset: -0x80000000, exp: []byte{0xc7, 0x80, 0x0, 0x0, 0x0, 0x80, 0x64, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-100/base=AX/offset=-0x80000000", inst: MOVL, c: -100, baseReg: RegAX, offset: -0x80000000, exp: []byte{0xc7, 0x80, 0x0, 0x0, 0x0, 0x80, 0x9c, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=127/base=AX/offset=-0x80000000", inst: MOVL, c: 127, baseReg: RegAX, offset: -0x80000000, exp: []byte{0xc7, 0x80, 0x0, 0x0, 0x0, 0x80, 0x7f, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-128/base=AX/offset=-0x80000000", inst: MOVL, c: -128, baseReg: RegAX, offset: -0x80000000, exp: []byte{0xc7, 0x80, 0x0, 0x0, 0x0, 0x80, 0x80, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=32767/base=AX/offset=-0x80000000", inst: MOVL, c: 32767, baseReg: RegAX, offset: -0x80000000, exp: []byte{0xc7, 0x80, 0x0, 0x0, 0x0, 0x80, 0xff, 0x7f, 0x0, 0x0}}, - {name: "MOVL/c=-32768/base=AX/offset=-0x80000000", inst: MOVL, c: -32768, baseReg: RegAX, offset: -0x80000000, exp: []byte{0xc7, 0x80, 0x0, 0x0, 0x0, 0x80, 0x0, 0x80, 0xff, 0xff}}, - {name: "MOVL/c=1048576/base=AX/offset=-0x80000000", inst: MOVL, c: 1048576, baseReg: RegAX, offset: -0x80000000, exp: []byte{0xc7, 0x80, 0x0, 0x0, 0x0, 0x80, 0x0, 0x0, 0x10, 0x0}}, - {name: "MOVL/c=-1048576/base=AX/offset=-0x80000000", inst: MOVL, c: -1048576, baseReg: RegAX, offset: -0x80000000, exp: []byte{0xc7, 0x80, 0x0, 0x0, 0x0, 0x80, 0x0, 0x0, 0xf0, 0xff}}, - {name: "MOVL/c=2147483647/base=AX/offset=-0x80000000", inst: MOVL, c: 2147483647, baseReg: RegAX, offset: -0x80000000, exp: []byte{0xc7, 0x80, 0x0, 0x0, 0x0, 0x80, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVL/c=-2147483648/base=AX/offset=-0x80000000", inst: MOVL, c: -2147483648, baseReg: RegAX, offset: -0x80000000, exp: []byte{0xc7, 0x80, 0x0, 0x0, 0x0, 0x80, 0x0, 0x0, 0x0, 0x80}}, - {name: "MOVL/c=0/base=AX/offset=0x7fff", inst: MOVL, c: 0, baseReg: RegAX, offset: 0x7fff, exp: []byte{0xc7, 0x80, 0xff, 0x7f, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=1/base=AX/offset=0x7fff", inst: MOVL, c: 1, baseReg: RegAX, offset: 0x7fff, exp: []byte{0xc7, 0x80, 0xff, 0x7f, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-1/base=AX/offset=0x7fff", inst: MOVL, c: -1, baseReg: RegAX, offset: 0x7fff, exp: []byte{0xc7, 0x80, 0xff, 0x7f, 0x0, 0x0, 0xff, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=100/base=AX/offset=0x7fff", inst: MOVL, c: 100, baseReg: RegAX, offset: 0x7fff, exp: []byte{0xc7, 0x80, 0xff, 0x7f, 0x0, 0x0, 0x64, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-100/base=AX/offset=0x7fff", inst: MOVL, c: -100, baseReg: RegAX, offset: 0x7fff, exp: []byte{0xc7, 0x80, 0xff, 0x7f, 0x0, 0x0, 0x9c, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=127/base=AX/offset=0x7fff", inst: MOVL, c: 127, baseReg: RegAX, offset: 0x7fff, exp: []byte{0xc7, 0x80, 0xff, 0x7f, 0x0, 0x0, 0x7f, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-128/base=AX/offset=0x7fff", inst: MOVL, c: -128, baseReg: RegAX, offset: 0x7fff, exp: []byte{0xc7, 0x80, 0xff, 0x7f, 0x0, 0x0, 0x80, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=32767/base=AX/offset=0x7fff", inst: MOVL, c: 32767, baseReg: RegAX, offset: 0x7fff, exp: []byte{0xc7, 0x80, 0xff, 0x7f, 0x0, 0x0, 0xff, 0x7f, 0x0, 0x0}}, - {name: "MOVL/c=-32768/base=AX/offset=0x7fff", inst: MOVL, c: -32768, baseReg: RegAX, offset: 0x7fff, exp: []byte{0xc7, 0x80, 0xff, 0x7f, 0x0, 0x0, 0x0, 0x80, 0xff, 0xff}}, - {name: "MOVL/c=1048576/base=AX/offset=0x7fff", inst: MOVL, c: 1048576, baseReg: RegAX, offset: 0x7fff, exp: []byte{0xc7, 0x80, 0xff, 0x7f, 0x0, 0x0, 0x0, 0x0, 0x10, 0x0}}, - {name: "MOVL/c=-1048576/base=AX/offset=0x7fff", inst: MOVL, c: -1048576, baseReg: RegAX, offset: 0x7fff, exp: []byte{0xc7, 0x80, 0xff, 0x7f, 0x0, 0x0, 0x0, 0x0, 0xf0, 0xff}}, - {name: "MOVL/c=2147483647/base=AX/offset=0x7fff", inst: MOVL, c: 2147483647, baseReg: RegAX, offset: 0x7fff, exp: []byte{0xc7, 0x80, 0xff, 0x7f, 0x0, 0x0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVL/c=-2147483648/base=AX/offset=0x7fff", inst: MOVL, c: -2147483648, baseReg: RegAX, offset: 0x7fff, exp: []byte{0xc7, 0x80, 0xff, 0x7f, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80}}, - {name: "MOVL/c=0/base=AX/offset=-0x8000", inst: MOVL, c: 0, baseReg: RegAX, offset: -0x8000, exp: []byte{0xc7, 0x80, 0x0, 0x80, 0xff, 0xff, 0x0, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=1/base=AX/offset=-0x8000", inst: MOVL, c: 1, baseReg: RegAX, offset: -0x8000, exp: []byte{0xc7, 0x80, 0x0, 0x80, 0xff, 0xff, 0x1, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-1/base=AX/offset=-0x8000", inst: MOVL, c: -1, baseReg: RegAX, offset: -0x8000, exp: []byte{0xc7, 0x80, 0x0, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=100/base=AX/offset=-0x8000", inst: MOVL, c: 100, baseReg: RegAX, offset: -0x8000, exp: []byte{0xc7, 0x80, 0x0, 0x80, 0xff, 0xff, 0x64, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-100/base=AX/offset=-0x8000", inst: MOVL, c: -100, baseReg: RegAX, offset: -0x8000, exp: []byte{0xc7, 0x80, 0x0, 0x80, 0xff, 0xff, 0x9c, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=127/base=AX/offset=-0x8000", inst: MOVL, c: 127, baseReg: RegAX, offset: -0x8000, exp: []byte{0xc7, 0x80, 0x0, 0x80, 0xff, 0xff, 0x7f, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-128/base=AX/offset=-0x8000", inst: MOVL, c: -128, baseReg: RegAX, offset: -0x8000, exp: []byte{0xc7, 0x80, 0x0, 0x80, 0xff, 0xff, 0x80, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=32767/base=AX/offset=-0x8000", inst: MOVL, c: 32767, baseReg: RegAX, offset: -0x8000, exp: []byte{0xc7, 0x80, 0x0, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x0, 0x0}}, - {name: "MOVL/c=-32768/base=AX/offset=-0x8000", inst: MOVL, c: -32768, baseReg: RegAX, offset: -0x8000, exp: []byte{0xc7, 0x80, 0x0, 0x80, 0xff, 0xff, 0x0, 0x80, 0xff, 0xff}}, - {name: "MOVL/c=1048576/base=AX/offset=-0x8000", inst: MOVL, c: 1048576, baseReg: RegAX, offset: -0x8000, exp: []byte{0xc7, 0x80, 0x0, 0x80, 0xff, 0xff, 0x0, 0x0, 0x10, 0x0}}, - {name: "MOVL/c=-1048576/base=AX/offset=-0x8000", inst: MOVL, c: -1048576, baseReg: RegAX, offset: -0x8000, exp: []byte{0xc7, 0x80, 0x0, 0x80, 0xff, 0xff, 0x0, 0x0, 0xf0, 0xff}}, - {name: "MOVL/c=2147483647/base=AX/offset=-0x8000", inst: MOVL, c: 2147483647, baseReg: RegAX, offset: -0x8000, exp: []byte{0xc7, 0x80, 0x0, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVL/c=-2147483648/base=AX/offset=-0x8000", inst: MOVL, c: -2147483648, baseReg: RegAX, offset: -0x8000, exp: []byte{0xc7, 0x80, 0x0, 0x80, 0xff, 0xff, 0x0, 0x0, 0x0, 0x80}}, - {name: "MOVL/c=0/base=R8/offset=0x0", inst: MOVL, c: 0, baseReg: RegR8, offset: 0x0, exp: []byte{0x41, 0xc7, 0x0, 0x0, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=1/base=R8/offset=0x0", inst: MOVL, c: 1, baseReg: RegR8, offset: 0x0, exp: []byte{0x41, 0xc7, 0x0, 0x1, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-1/base=R8/offset=0x0", inst: MOVL, c: -1, baseReg: RegR8, offset: 0x0, exp: []byte{0x41, 0xc7, 0x0, 0xff, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=100/base=R8/offset=0x0", inst: MOVL, c: 100, baseReg: RegR8, offset: 0x0, exp: []byte{0x41, 0xc7, 0x0, 0x64, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-100/base=R8/offset=0x0", inst: MOVL, c: -100, baseReg: RegR8, offset: 0x0, exp: []byte{0x41, 0xc7, 0x0, 0x9c, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=127/base=R8/offset=0x0", inst: MOVL, c: 127, baseReg: RegR8, offset: 0x0, exp: []byte{0x41, 0xc7, 0x0, 0x7f, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-128/base=R8/offset=0x0", inst: MOVL, c: -128, baseReg: RegR8, offset: 0x0, exp: []byte{0x41, 0xc7, 0x0, 0x80, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=32767/base=R8/offset=0x0", inst: MOVL, c: 32767, baseReg: RegR8, offset: 0x0, exp: []byte{0x41, 0xc7, 0x0, 0xff, 0x7f, 0x0, 0x0}}, - {name: "MOVL/c=-32768/base=R8/offset=0x0", inst: MOVL, c: -32768, baseReg: RegR8, offset: 0x0, exp: []byte{0x41, 0xc7, 0x0, 0x0, 0x80, 0xff, 0xff}}, - {name: "MOVL/c=1048576/base=R8/offset=0x0", inst: MOVL, c: 1048576, baseReg: RegR8, offset: 0x0, exp: []byte{0x41, 0xc7, 0x0, 0x0, 0x0, 0x10, 0x0}}, - {name: "MOVL/c=-1048576/base=R8/offset=0x0", inst: MOVL, c: -1048576, baseReg: RegR8, offset: 0x0, exp: []byte{0x41, 0xc7, 0x0, 0x0, 0x0, 0xf0, 0xff}}, - {name: "MOVL/c=2147483647/base=R8/offset=0x0", inst: MOVL, c: 2147483647, baseReg: RegR8, offset: 0x0, exp: []byte{0x41, 0xc7, 0x0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVL/c=-2147483648/base=R8/offset=0x0", inst: MOVL, c: -2147483648, baseReg: RegR8, offset: 0x0, exp: []byte{0x41, 0xc7, 0x0, 0x0, 0x0, 0x0, 0x80}}, - {name: "MOVL/c=0/base=R8/offset=0x1", inst: MOVL, c: 0, baseReg: RegR8, offset: 0x1, exp: []byte{0x41, 0xc7, 0x40, 0x1, 0x0, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=1/base=R8/offset=0x1", inst: MOVL, c: 1, baseReg: RegR8, offset: 0x1, exp: []byte{0x41, 0xc7, 0x40, 0x1, 0x1, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-1/base=R8/offset=0x1", inst: MOVL, c: -1, baseReg: RegR8, offset: 0x1, exp: []byte{0x41, 0xc7, 0x40, 0x1, 0xff, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=100/base=R8/offset=0x1", inst: MOVL, c: 100, baseReg: RegR8, offset: 0x1, exp: []byte{0x41, 0xc7, 0x40, 0x1, 0x64, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-100/base=R8/offset=0x1", inst: MOVL, c: -100, baseReg: RegR8, offset: 0x1, exp: []byte{0x41, 0xc7, 0x40, 0x1, 0x9c, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=127/base=R8/offset=0x1", inst: MOVL, c: 127, baseReg: RegR8, offset: 0x1, exp: []byte{0x41, 0xc7, 0x40, 0x1, 0x7f, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-128/base=R8/offset=0x1", inst: MOVL, c: -128, baseReg: RegR8, offset: 0x1, exp: []byte{0x41, 0xc7, 0x40, 0x1, 0x80, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=32767/base=R8/offset=0x1", inst: MOVL, c: 32767, baseReg: RegR8, offset: 0x1, exp: []byte{0x41, 0xc7, 0x40, 0x1, 0xff, 0x7f, 0x0, 0x0}}, - {name: "MOVL/c=-32768/base=R8/offset=0x1", inst: MOVL, c: -32768, baseReg: RegR8, offset: 0x1, exp: []byte{0x41, 0xc7, 0x40, 0x1, 0x0, 0x80, 0xff, 0xff}}, - {name: "MOVL/c=1048576/base=R8/offset=0x1", inst: MOVL, c: 1048576, baseReg: RegR8, offset: 0x1, exp: []byte{0x41, 0xc7, 0x40, 0x1, 0x0, 0x0, 0x10, 0x0}}, - {name: "MOVL/c=-1048576/base=R8/offset=0x1", inst: MOVL, c: -1048576, baseReg: RegR8, offset: 0x1, exp: []byte{0x41, 0xc7, 0x40, 0x1, 0x0, 0x0, 0xf0, 0xff}}, - {name: "MOVL/c=2147483647/base=R8/offset=0x1", inst: MOVL, c: 2147483647, baseReg: RegR8, offset: 0x1, exp: []byte{0x41, 0xc7, 0x40, 0x1, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVL/c=-2147483648/base=R8/offset=0x1", inst: MOVL, c: -2147483648, baseReg: RegR8, offset: 0x1, exp: []byte{0x41, 0xc7, 0x40, 0x1, 0x0, 0x0, 0x0, 0x80}}, - {name: "MOVL/c=0/base=R8/offset=-0x1", inst: MOVL, c: 0, baseReg: RegR8, offset: -0x1, exp: []byte{0x41, 0xc7, 0x40, 0xff, 0x0, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=1/base=R8/offset=-0x1", inst: MOVL, c: 1, baseReg: RegR8, offset: -0x1, exp: []byte{0x41, 0xc7, 0x40, 0xff, 0x1, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-1/base=R8/offset=-0x1", inst: MOVL, c: -1, baseReg: RegR8, offset: -0x1, exp: []byte{0x41, 0xc7, 0x40, 0xff, 0xff, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=100/base=R8/offset=-0x1", inst: MOVL, c: 100, baseReg: RegR8, offset: -0x1, exp: []byte{0x41, 0xc7, 0x40, 0xff, 0x64, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-100/base=R8/offset=-0x1", inst: MOVL, c: -100, baseReg: RegR8, offset: -0x1, exp: []byte{0x41, 0xc7, 0x40, 0xff, 0x9c, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=127/base=R8/offset=-0x1", inst: MOVL, c: 127, baseReg: RegR8, offset: -0x1, exp: []byte{0x41, 0xc7, 0x40, 0xff, 0x7f, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-128/base=R8/offset=-0x1", inst: MOVL, c: -128, baseReg: RegR8, offset: -0x1, exp: []byte{0x41, 0xc7, 0x40, 0xff, 0x80, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=32767/base=R8/offset=-0x1", inst: MOVL, c: 32767, baseReg: RegR8, offset: -0x1, exp: []byte{0x41, 0xc7, 0x40, 0xff, 0xff, 0x7f, 0x0, 0x0}}, - {name: "MOVL/c=-32768/base=R8/offset=-0x1", inst: MOVL, c: -32768, baseReg: RegR8, offset: -0x1, exp: []byte{0x41, 0xc7, 0x40, 0xff, 0x0, 0x80, 0xff, 0xff}}, - {name: "MOVL/c=1048576/base=R8/offset=-0x1", inst: MOVL, c: 1048576, baseReg: RegR8, offset: -0x1, exp: []byte{0x41, 0xc7, 0x40, 0xff, 0x0, 0x0, 0x10, 0x0}}, - {name: "MOVL/c=-1048576/base=R8/offset=-0x1", inst: MOVL, c: -1048576, baseReg: RegR8, offset: -0x1, exp: []byte{0x41, 0xc7, 0x40, 0xff, 0x0, 0x0, 0xf0, 0xff}}, - {name: "MOVL/c=2147483647/base=R8/offset=-0x1", inst: MOVL, c: 2147483647, baseReg: RegR8, offset: -0x1, exp: []byte{0x41, 0xc7, 0x40, 0xff, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVL/c=-2147483648/base=R8/offset=-0x1", inst: MOVL, c: -2147483648, baseReg: RegR8, offset: -0x1, exp: []byte{0x41, 0xc7, 0x40, 0xff, 0x0, 0x0, 0x0, 0x80}}, - {name: "MOVL/c=0/base=R8/offset=0x4db", inst: MOVL, c: 0, baseReg: RegR8, offset: 0x4db, exp: []byte{0x41, 0xc7, 0x80, 0xdb, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=1/base=R8/offset=0x4db", inst: MOVL, c: 1, baseReg: RegR8, offset: 0x4db, exp: []byte{0x41, 0xc7, 0x80, 0xdb, 0x4, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-1/base=R8/offset=0x4db", inst: MOVL, c: -1, baseReg: RegR8, offset: 0x4db, exp: []byte{0x41, 0xc7, 0x80, 0xdb, 0x4, 0x0, 0x0, 0xff, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=100/base=R8/offset=0x4db", inst: MOVL, c: 100, baseReg: RegR8, offset: 0x4db, exp: []byte{0x41, 0xc7, 0x80, 0xdb, 0x4, 0x0, 0x0, 0x64, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-100/base=R8/offset=0x4db", inst: MOVL, c: -100, baseReg: RegR8, offset: 0x4db, exp: []byte{0x41, 0xc7, 0x80, 0xdb, 0x4, 0x0, 0x0, 0x9c, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=127/base=R8/offset=0x4db", inst: MOVL, c: 127, baseReg: RegR8, offset: 0x4db, exp: []byte{0x41, 0xc7, 0x80, 0xdb, 0x4, 0x0, 0x0, 0x7f, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-128/base=R8/offset=0x4db", inst: MOVL, c: -128, baseReg: RegR8, offset: 0x4db, exp: []byte{0x41, 0xc7, 0x80, 0xdb, 0x4, 0x0, 0x0, 0x80, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=32767/base=R8/offset=0x4db", inst: MOVL, c: 32767, baseReg: RegR8, offset: 0x4db, exp: []byte{0x41, 0xc7, 0x80, 0xdb, 0x4, 0x0, 0x0, 0xff, 0x7f, 0x0, 0x0}}, - {name: "MOVL/c=-32768/base=R8/offset=0x4db", inst: MOVL, c: -32768, baseReg: RegR8, offset: 0x4db, exp: []byte{0x41, 0xc7, 0x80, 0xdb, 0x4, 0x0, 0x0, 0x0, 0x80, 0xff, 0xff}}, - {name: "MOVL/c=1048576/base=R8/offset=0x4db", inst: MOVL, c: 1048576, baseReg: RegR8, offset: 0x4db, exp: []byte{0x41, 0xc7, 0x80, 0xdb, 0x4, 0x0, 0x0, 0x0, 0x0, 0x10, 0x0}}, - {name: "MOVL/c=-1048576/base=R8/offset=0x4db", inst: MOVL, c: -1048576, baseReg: RegR8, offset: 0x4db, exp: []byte{0x41, 0xc7, 0x80, 0xdb, 0x4, 0x0, 0x0, 0x0, 0x0, 0xf0, 0xff}}, - {name: "MOVL/c=2147483647/base=R8/offset=0x4db", inst: MOVL, c: 2147483647, baseReg: RegR8, offset: 0x4db, exp: []byte{0x41, 0xc7, 0x80, 0xdb, 0x4, 0x0, 0x0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVL/c=-2147483648/base=R8/offset=0x4db", inst: MOVL, c: -2147483648, baseReg: RegR8, offset: 0x4db, exp: []byte{0x41, 0xc7, 0x80, 0xdb, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80}}, - {name: "MOVL/c=0/base=R8/offset=-0x4d2", inst: MOVL, c: 0, baseReg: RegR8, offset: -0x4d2, exp: []byte{0x41, 0xc7, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0x0, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=1/base=R8/offset=-0x4d2", inst: MOVL, c: 1, baseReg: RegR8, offset: -0x4d2, exp: []byte{0x41, 0xc7, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0x1, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-1/base=R8/offset=-0x4d2", inst: MOVL, c: -1, baseReg: RegR8, offset: -0x4d2, exp: []byte{0x41, 0xc7, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=100/base=R8/offset=-0x4d2", inst: MOVL, c: 100, baseReg: RegR8, offset: -0x4d2, exp: []byte{0x41, 0xc7, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0x64, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-100/base=R8/offset=-0x4d2", inst: MOVL, c: -100, baseReg: RegR8, offset: -0x4d2, exp: []byte{0x41, 0xc7, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0x9c, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=127/base=R8/offset=-0x4d2", inst: MOVL, c: 127, baseReg: RegR8, offset: -0x4d2, exp: []byte{0x41, 0xc7, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0x7f, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-128/base=R8/offset=-0x4d2", inst: MOVL, c: -128, baseReg: RegR8, offset: -0x4d2, exp: []byte{0x41, 0xc7, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0x80, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=32767/base=R8/offset=-0x4d2", inst: MOVL, c: 32767, baseReg: RegR8, offset: -0x4d2, exp: []byte{0x41, 0xc7, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0xff, 0x7f, 0x0, 0x0}}, - {name: "MOVL/c=-32768/base=R8/offset=-0x4d2", inst: MOVL, c: -32768, baseReg: RegR8, offset: -0x4d2, exp: []byte{0x41, 0xc7, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0x0, 0x80, 0xff, 0xff}}, - {name: "MOVL/c=1048576/base=R8/offset=-0x4d2", inst: MOVL, c: 1048576, baseReg: RegR8, offset: -0x4d2, exp: []byte{0x41, 0xc7, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0x0, 0x0, 0x10, 0x0}}, - {name: "MOVL/c=-1048576/base=R8/offset=-0x4d2", inst: MOVL, c: -1048576, baseReg: RegR8, offset: -0x4d2, exp: []byte{0x41, 0xc7, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0x0, 0x0, 0xf0, 0xff}}, - {name: "MOVL/c=2147483647/base=R8/offset=-0x4d2", inst: MOVL, c: 2147483647, baseReg: RegR8, offset: -0x4d2, exp: []byte{0x41, 0xc7, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVL/c=-2147483648/base=R8/offset=-0x4d2", inst: MOVL, c: -2147483648, baseReg: RegR8, offset: -0x4d2, exp: []byte{0x41, 0xc7, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0x0, 0x0, 0x0, 0x80}}, - {name: "MOVL/c=0/base=R8/offset=0x7fffffff", inst: MOVL, c: 0, baseReg: RegR8, offset: 0x7fffffff, exp: []byte{0x41, 0xc7, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x0, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=1/base=R8/offset=0x7fffffff", inst: MOVL, c: 1, baseReg: RegR8, offset: 0x7fffffff, exp: []byte{0x41, 0xc7, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x1, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-1/base=R8/offset=0x7fffffff", inst: MOVL, c: -1, baseReg: RegR8, offset: 0x7fffffff, exp: []byte{0x41, 0xc7, 0x80, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=100/base=R8/offset=0x7fffffff", inst: MOVL, c: 100, baseReg: RegR8, offset: 0x7fffffff, exp: []byte{0x41, 0xc7, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x64, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-100/base=R8/offset=0x7fffffff", inst: MOVL, c: -100, baseReg: RegR8, offset: 0x7fffffff, exp: []byte{0x41, 0xc7, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x9c, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=127/base=R8/offset=0x7fffffff", inst: MOVL, c: 127, baseReg: RegR8, offset: 0x7fffffff, exp: []byte{0x41, 0xc7, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x7f, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-128/base=R8/offset=0x7fffffff", inst: MOVL, c: -128, baseReg: RegR8, offset: 0x7fffffff, exp: []byte{0x41, 0xc7, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x80, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=32767/base=R8/offset=0x7fffffff", inst: MOVL, c: 32767, baseReg: RegR8, offset: 0x7fffffff, exp: []byte{0x41, 0xc7, 0x80, 0xff, 0xff, 0xff, 0x7f, 0xff, 0x7f, 0x0, 0x0}}, - {name: "MOVL/c=-32768/base=R8/offset=0x7fffffff", inst: MOVL, c: -32768, baseReg: RegR8, offset: 0x7fffffff, exp: []byte{0x41, 0xc7, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x0, 0x80, 0xff, 0xff}}, - {name: "MOVL/c=1048576/base=R8/offset=0x7fffffff", inst: MOVL, c: 1048576, baseReg: RegR8, offset: 0x7fffffff, exp: []byte{0x41, 0xc7, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x0, 0x0, 0x10, 0x0}}, - {name: "MOVL/c=-1048576/base=R8/offset=0x7fffffff", inst: MOVL, c: -1048576, baseReg: RegR8, offset: 0x7fffffff, exp: []byte{0x41, 0xc7, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x0, 0x0, 0xf0, 0xff}}, - {name: "MOVL/c=2147483647/base=R8/offset=0x7fffffff", inst: MOVL, c: 2147483647, baseReg: RegR8, offset: 0x7fffffff, exp: []byte{0x41, 0xc7, 0x80, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVL/c=-2147483648/base=R8/offset=0x7fffffff", inst: MOVL, c: -2147483648, baseReg: RegR8, offset: 0x7fffffff, exp: []byte{0x41, 0xc7, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x0, 0x0, 0x0, 0x80}}, - {name: "MOVL/c=0/base=R8/offset=-0x80000000", inst: MOVL, c: 0, baseReg: RegR8, offset: -0x80000000, exp: []byte{0x41, 0xc7, 0x80, 0x0, 0x0, 0x0, 0x80, 0x0, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=1/base=R8/offset=-0x80000000", inst: MOVL, c: 1, baseReg: RegR8, offset: -0x80000000, exp: []byte{0x41, 0xc7, 0x80, 0x0, 0x0, 0x0, 0x80, 0x1, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-1/base=R8/offset=-0x80000000", inst: MOVL, c: -1, baseReg: RegR8, offset: -0x80000000, exp: []byte{0x41, 0xc7, 0x80, 0x0, 0x0, 0x0, 0x80, 0xff, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=100/base=R8/offset=-0x80000000", inst: MOVL, c: 100, baseReg: RegR8, offset: -0x80000000, exp: []byte{0x41, 0xc7, 0x80, 0x0, 0x0, 0x0, 0x80, 0x64, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-100/base=R8/offset=-0x80000000", inst: MOVL, c: -100, baseReg: RegR8, offset: -0x80000000, exp: []byte{0x41, 0xc7, 0x80, 0x0, 0x0, 0x0, 0x80, 0x9c, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=127/base=R8/offset=-0x80000000", inst: MOVL, c: 127, baseReg: RegR8, offset: -0x80000000, exp: []byte{0x41, 0xc7, 0x80, 0x0, 0x0, 0x0, 0x80, 0x7f, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-128/base=R8/offset=-0x80000000", inst: MOVL, c: -128, baseReg: RegR8, offset: -0x80000000, exp: []byte{0x41, 0xc7, 0x80, 0x0, 0x0, 0x0, 0x80, 0x80, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=32767/base=R8/offset=-0x80000000", inst: MOVL, c: 32767, baseReg: RegR8, offset: -0x80000000, exp: []byte{0x41, 0xc7, 0x80, 0x0, 0x0, 0x0, 0x80, 0xff, 0x7f, 0x0, 0x0}}, - {name: "MOVL/c=-32768/base=R8/offset=-0x80000000", inst: MOVL, c: -32768, baseReg: RegR8, offset: -0x80000000, exp: []byte{0x41, 0xc7, 0x80, 0x0, 0x0, 0x0, 0x80, 0x0, 0x80, 0xff, 0xff}}, - {name: "MOVL/c=1048576/base=R8/offset=-0x80000000", inst: MOVL, c: 1048576, baseReg: RegR8, offset: -0x80000000, exp: []byte{0x41, 0xc7, 0x80, 0x0, 0x0, 0x0, 0x80, 0x0, 0x0, 0x10, 0x0}}, - {name: "MOVL/c=-1048576/base=R8/offset=-0x80000000", inst: MOVL, c: -1048576, baseReg: RegR8, offset: -0x80000000, exp: []byte{0x41, 0xc7, 0x80, 0x0, 0x0, 0x0, 0x80, 0x0, 0x0, 0xf0, 0xff}}, - {name: "MOVL/c=2147483647/base=R8/offset=-0x80000000", inst: MOVL, c: 2147483647, baseReg: RegR8, offset: -0x80000000, exp: []byte{0x41, 0xc7, 0x80, 0x0, 0x0, 0x0, 0x80, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVL/c=-2147483648/base=R8/offset=-0x80000000", inst: MOVL, c: -2147483648, baseReg: RegR8, offset: -0x80000000, exp: []byte{0x41, 0xc7, 0x80, 0x0, 0x0, 0x0, 0x80, 0x0, 0x0, 0x0, 0x80}}, - {name: "MOVL/c=0/base=R8/offset=0x7fff", inst: MOVL, c: 0, baseReg: RegR8, offset: 0x7fff, exp: []byte{0x41, 0xc7, 0x80, 0xff, 0x7f, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=1/base=R8/offset=0x7fff", inst: MOVL, c: 1, baseReg: RegR8, offset: 0x7fff, exp: []byte{0x41, 0xc7, 0x80, 0xff, 0x7f, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-1/base=R8/offset=0x7fff", inst: MOVL, c: -1, baseReg: RegR8, offset: 0x7fff, exp: []byte{0x41, 0xc7, 0x80, 0xff, 0x7f, 0x0, 0x0, 0xff, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=100/base=R8/offset=0x7fff", inst: MOVL, c: 100, baseReg: RegR8, offset: 0x7fff, exp: []byte{0x41, 0xc7, 0x80, 0xff, 0x7f, 0x0, 0x0, 0x64, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-100/base=R8/offset=0x7fff", inst: MOVL, c: -100, baseReg: RegR8, offset: 0x7fff, exp: []byte{0x41, 0xc7, 0x80, 0xff, 0x7f, 0x0, 0x0, 0x9c, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=127/base=R8/offset=0x7fff", inst: MOVL, c: 127, baseReg: RegR8, offset: 0x7fff, exp: []byte{0x41, 0xc7, 0x80, 0xff, 0x7f, 0x0, 0x0, 0x7f, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-128/base=R8/offset=0x7fff", inst: MOVL, c: -128, baseReg: RegR8, offset: 0x7fff, exp: []byte{0x41, 0xc7, 0x80, 0xff, 0x7f, 0x0, 0x0, 0x80, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=32767/base=R8/offset=0x7fff", inst: MOVL, c: 32767, baseReg: RegR8, offset: 0x7fff, exp: []byte{0x41, 0xc7, 0x80, 0xff, 0x7f, 0x0, 0x0, 0xff, 0x7f, 0x0, 0x0}}, - {name: "MOVL/c=-32768/base=R8/offset=0x7fff", inst: MOVL, c: -32768, baseReg: RegR8, offset: 0x7fff, exp: []byte{0x41, 0xc7, 0x80, 0xff, 0x7f, 0x0, 0x0, 0x0, 0x80, 0xff, 0xff}}, - {name: "MOVL/c=1048576/base=R8/offset=0x7fff", inst: MOVL, c: 1048576, baseReg: RegR8, offset: 0x7fff, exp: []byte{0x41, 0xc7, 0x80, 0xff, 0x7f, 0x0, 0x0, 0x0, 0x0, 0x10, 0x0}}, - {name: "MOVL/c=-1048576/base=R8/offset=0x7fff", inst: MOVL, c: -1048576, baseReg: RegR8, offset: 0x7fff, exp: []byte{0x41, 0xc7, 0x80, 0xff, 0x7f, 0x0, 0x0, 0x0, 0x0, 0xf0, 0xff}}, - {name: "MOVL/c=2147483647/base=R8/offset=0x7fff", inst: MOVL, c: 2147483647, baseReg: RegR8, offset: 0x7fff, exp: []byte{0x41, 0xc7, 0x80, 0xff, 0x7f, 0x0, 0x0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVL/c=-2147483648/base=R8/offset=0x7fff", inst: MOVL, c: -2147483648, baseReg: RegR8, offset: 0x7fff, exp: []byte{0x41, 0xc7, 0x80, 0xff, 0x7f, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80}}, - {name: "MOVL/c=0/base=R8/offset=-0x8000", inst: MOVL, c: 0, baseReg: RegR8, offset: -0x8000, exp: []byte{0x41, 0xc7, 0x80, 0x0, 0x80, 0xff, 0xff, 0x0, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=1/base=R8/offset=-0x8000", inst: MOVL, c: 1, baseReg: RegR8, offset: -0x8000, exp: []byte{0x41, 0xc7, 0x80, 0x0, 0x80, 0xff, 0xff, 0x1, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-1/base=R8/offset=-0x8000", inst: MOVL, c: -1, baseReg: RegR8, offset: -0x8000, exp: []byte{0x41, 0xc7, 0x80, 0x0, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=100/base=R8/offset=-0x8000", inst: MOVL, c: 100, baseReg: RegR8, offset: -0x8000, exp: []byte{0x41, 0xc7, 0x80, 0x0, 0x80, 0xff, 0xff, 0x64, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-100/base=R8/offset=-0x8000", inst: MOVL, c: -100, baseReg: RegR8, offset: -0x8000, exp: []byte{0x41, 0xc7, 0x80, 0x0, 0x80, 0xff, 0xff, 0x9c, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=127/base=R8/offset=-0x8000", inst: MOVL, c: 127, baseReg: RegR8, offset: -0x8000, exp: []byte{0x41, 0xc7, 0x80, 0x0, 0x80, 0xff, 0xff, 0x7f, 0x0, 0x0, 0x0}}, - {name: "MOVL/c=-128/base=R8/offset=-0x8000", inst: MOVL, c: -128, baseReg: RegR8, offset: -0x8000, exp: []byte{0x41, 0xc7, 0x80, 0x0, 0x80, 0xff, 0xff, 0x80, 0xff, 0xff, 0xff}}, - {name: "MOVL/c=32767/base=R8/offset=-0x8000", inst: MOVL, c: 32767, baseReg: RegR8, offset: -0x8000, exp: []byte{0x41, 0xc7, 0x80, 0x0, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x0, 0x0}}, - {name: "MOVL/c=-32768/base=R8/offset=-0x8000", inst: MOVL, c: -32768, baseReg: RegR8, offset: -0x8000, exp: []byte{0x41, 0xc7, 0x80, 0x0, 0x80, 0xff, 0xff, 0x0, 0x80, 0xff, 0xff}}, - {name: "MOVL/c=1048576/base=R8/offset=-0x8000", inst: MOVL, c: 1048576, baseReg: RegR8, offset: -0x8000, exp: []byte{0x41, 0xc7, 0x80, 0x0, 0x80, 0xff, 0xff, 0x0, 0x0, 0x10, 0x0}}, - {name: "MOVL/c=-1048576/base=R8/offset=-0x8000", inst: MOVL, c: -1048576, baseReg: RegR8, offset: -0x8000, exp: []byte{0x41, 0xc7, 0x80, 0x0, 0x80, 0xff, 0xff, 0x0, 0x0, 0xf0, 0xff}}, - {name: "MOVL/c=2147483647/base=R8/offset=-0x8000", inst: MOVL, c: 2147483647, baseReg: RegR8, offset: -0x8000, exp: []byte{0x41, 0xc7, 0x80, 0x0, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVL/c=-2147483648/base=R8/offset=-0x8000", inst: MOVL, c: -2147483648, baseReg: RegR8, offset: -0x8000, exp: []byte{0x41, 0xc7, 0x80, 0x0, 0x80, 0xff, 0xff, 0x0, 0x0, 0x0, 0x80}}, - {name: "MOVQ/c=0/base=AX/offset=0x0", inst: MOVQ, c: 0, baseReg: RegAX, offset: 0x0, exp: []byte{0x48, 0xc7, 0x0, 0x0, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=1/base=AX/offset=0x0", inst: MOVQ, c: 1, baseReg: RegAX, offset: 0x0, exp: []byte{0x48, 0xc7, 0x0, 0x1, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-1/base=AX/offset=0x0", inst: MOVQ, c: -1, baseReg: RegAX, offset: 0x0, exp: []byte{0x48, 0xc7, 0x0, 0xff, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=100/base=AX/offset=0x0", inst: MOVQ, c: 100, baseReg: RegAX, offset: 0x0, exp: []byte{0x48, 0xc7, 0x0, 0x64, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-100/base=AX/offset=0x0", inst: MOVQ, c: -100, baseReg: RegAX, offset: 0x0, exp: []byte{0x48, 0xc7, 0x0, 0x9c, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=127/base=AX/offset=0x0", inst: MOVQ, c: 127, baseReg: RegAX, offset: 0x0, exp: []byte{0x48, 0xc7, 0x0, 0x7f, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-128/base=AX/offset=0x0", inst: MOVQ, c: -128, baseReg: RegAX, offset: 0x0, exp: []byte{0x48, 0xc7, 0x0, 0x80, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=32767/base=AX/offset=0x0", inst: MOVQ, c: 32767, baseReg: RegAX, offset: 0x0, exp: []byte{0x48, 0xc7, 0x0, 0xff, 0x7f, 0x0, 0x0}}, - {name: "MOVQ/c=-32768/base=AX/offset=0x0", inst: MOVQ, c: -32768, baseReg: RegAX, offset: 0x0, exp: []byte{0x48, 0xc7, 0x0, 0x0, 0x80, 0xff, 0xff}}, - {name: "MOVQ/c=1048576/base=AX/offset=0x0", inst: MOVQ, c: 1048576, baseReg: RegAX, offset: 0x0, exp: []byte{0x48, 0xc7, 0x0, 0x0, 0x0, 0x10, 0x0}}, - {name: "MOVQ/c=-1048576/base=AX/offset=0x0", inst: MOVQ, c: -1048576, baseReg: RegAX, offset: 0x0, exp: []byte{0x48, 0xc7, 0x0, 0x0, 0x0, 0xf0, 0xff}}, - {name: "MOVQ/c=2147483647/base=AX/offset=0x0", inst: MOVQ, c: 2147483647, baseReg: RegAX, offset: 0x0, exp: []byte{0x48, 0xc7, 0x0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVQ/c=-2147483648/base=AX/offset=0x0", inst: MOVQ, c: -2147483648, baseReg: RegAX, offset: 0x0, exp: []byte{0x48, 0xc7, 0x0, 0x0, 0x0, 0x0, 0x80}}, - {name: "MOVQ/c=0/base=AX/offset=0x1", inst: MOVQ, c: 0, baseReg: RegAX, offset: 0x1, exp: []byte{0x48, 0xc7, 0x40, 0x1, 0x0, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=1/base=AX/offset=0x1", inst: MOVQ, c: 1, baseReg: RegAX, offset: 0x1, exp: []byte{0x48, 0xc7, 0x40, 0x1, 0x1, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-1/base=AX/offset=0x1", inst: MOVQ, c: -1, baseReg: RegAX, offset: 0x1, exp: []byte{0x48, 0xc7, 0x40, 0x1, 0xff, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=100/base=AX/offset=0x1", inst: MOVQ, c: 100, baseReg: RegAX, offset: 0x1, exp: []byte{0x48, 0xc7, 0x40, 0x1, 0x64, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-100/base=AX/offset=0x1", inst: MOVQ, c: -100, baseReg: RegAX, offset: 0x1, exp: []byte{0x48, 0xc7, 0x40, 0x1, 0x9c, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=127/base=AX/offset=0x1", inst: MOVQ, c: 127, baseReg: RegAX, offset: 0x1, exp: []byte{0x48, 0xc7, 0x40, 0x1, 0x7f, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-128/base=AX/offset=0x1", inst: MOVQ, c: -128, baseReg: RegAX, offset: 0x1, exp: []byte{0x48, 0xc7, 0x40, 0x1, 0x80, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=32767/base=AX/offset=0x1", inst: MOVQ, c: 32767, baseReg: RegAX, offset: 0x1, exp: []byte{0x48, 0xc7, 0x40, 0x1, 0xff, 0x7f, 0x0, 0x0}}, - {name: "MOVQ/c=-32768/base=AX/offset=0x1", inst: MOVQ, c: -32768, baseReg: RegAX, offset: 0x1, exp: []byte{0x48, 0xc7, 0x40, 0x1, 0x0, 0x80, 0xff, 0xff}}, - {name: "MOVQ/c=1048576/base=AX/offset=0x1", inst: MOVQ, c: 1048576, baseReg: RegAX, offset: 0x1, exp: []byte{0x48, 0xc7, 0x40, 0x1, 0x0, 0x0, 0x10, 0x0}}, - {name: "MOVQ/c=-1048576/base=AX/offset=0x1", inst: MOVQ, c: -1048576, baseReg: RegAX, offset: 0x1, exp: []byte{0x48, 0xc7, 0x40, 0x1, 0x0, 0x0, 0xf0, 0xff}}, - {name: "MOVQ/c=2147483647/base=AX/offset=0x1", inst: MOVQ, c: 2147483647, baseReg: RegAX, offset: 0x1, exp: []byte{0x48, 0xc7, 0x40, 0x1, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVQ/c=-2147483648/base=AX/offset=0x1", inst: MOVQ, c: -2147483648, baseReg: RegAX, offset: 0x1, exp: []byte{0x48, 0xc7, 0x40, 0x1, 0x0, 0x0, 0x0, 0x80}}, - {name: "MOVQ/c=0/base=AX/offset=-0x1", inst: MOVQ, c: 0, baseReg: RegAX, offset: -0x1, exp: []byte{0x48, 0xc7, 0x40, 0xff, 0x0, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=1/base=AX/offset=-0x1", inst: MOVQ, c: 1, baseReg: RegAX, offset: -0x1, exp: []byte{0x48, 0xc7, 0x40, 0xff, 0x1, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-1/base=AX/offset=-0x1", inst: MOVQ, c: -1, baseReg: RegAX, offset: -0x1, exp: []byte{0x48, 0xc7, 0x40, 0xff, 0xff, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=100/base=AX/offset=-0x1", inst: MOVQ, c: 100, baseReg: RegAX, offset: -0x1, exp: []byte{0x48, 0xc7, 0x40, 0xff, 0x64, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-100/base=AX/offset=-0x1", inst: MOVQ, c: -100, baseReg: RegAX, offset: -0x1, exp: []byte{0x48, 0xc7, 0x40, 0xff, 0x9c, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=127/base=AX/offset=-0x1", inst: MOVQ, c: 127, baseReg: RegAX, offset: -0x1, exp: []byte{0x48, 0xc7, 0x40, 0xff, 0x7f, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-128/base=AX/offset=-0x1", inst: MOVQ, c: -128, baseReg: RegAX, offset: -0x1, exp: []byte{0x48, 0xc7, 0x40, 0xff, 0x80, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=32767/base=AX/offset=-0x1", inst: MOVQ, c: 32767, baseReg: RegAX, offset: -0x1, exp: []byte{0x48, 0xc7, 0x40, 0xff, 0xff, 0x7f, 0x0, 0x0}}, - {name: "MOVQ/c=-32768/base=AX/offset=-0x1", inst: MOVQ, c: -32768, baseReg: RegAX, offset: -0x1, exp: []byte{0x48, 0xc7, 0x40, 0xff, 0x0, 0x80, 0xff, 0xff}}, - {name: "MOVQ/c=1048576/base=AX/offset=-0x1", inst: MOVQ, c: 1048576, baseReg: RegAX, offset: -0x1, exp: []byte{0x48, 0xc7, 0x40, 0xff, 0x0, 0x0, 0x10, 0x0}}, - {name: "MOVQ/c=-1048576/base=AX/offset=-0x1", inst: MOVQ, c: -1048576, baseReg: RegAX, offset: -0x1, exp: []byte{0x48, 0xc7, 0x40, 0xff, 0x0, 0x0, 0xf0, 0xff}}, - {name: "MOVQ/c=2147483647/base=AX/offset=-0x1", inst: MOVQ, c: 2147483647, baseReg: RegAX, offset: -0x1, exp: []byte{0x48, 0xc7, 0x40, 0xff, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVQ/c=-2147483648/base=AX/offset=-0x1", inst: MOVQ, c: -2147483648, baseReg: RegAX, offset: -0x1, exp: []byte{0x48, 0xc7, 0x40, 0xff, 0x0, 0x0, 0x0, 0x80}}, - {name: "MOVQ/c=0/base=AX/offset=0x4db", inst: MOVQ, c: 0, baseReg: RegAX, offset: 0x4db, exp: []byte{0x48, 0xc7, 0x80, 0xdb, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=1/base=AX/offset=0x4db", inst: MOVQ, c: 1, baseReg: RegAX, offset: 0x4db, exp: []byte{0x48, 0xc7, 0x80, 0xdb, 0x4, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-1/base=AX/offset=0x4db", inst: MOVQ, c: -1, baseReg: RegAX, offset: 0x4db, exp: []byte{0x48, 0xc7, 0x80, 0xdb, 0x4, 0x0, 0x0, 0xff, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=100/base=AX/offset=0x4db", inst: MOVQ, c: 100, baseReg: RegAX, offset: 0x4db, exp: []byte{0x48, 0xc7, 0x80, 0xdb, 0x4, 0x0, 0x0, 0x64, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-100/base=AX/offset=0x4db", inst: MOVQ, c: -100, baseReg: RegAX, offset: 0x4db, exp: []byte{0x48, 0xc7, 0x80, 0xdb, 0x4, 0x0, 0x0, 0x9c, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=127/base=AX/offset=0x4db", inst: MOVQ, c: 127, baseReg: RegAX, offset: 0x4db, exp: []byte{0x48, 0xc7, 0x80, 0xdb, 0x4, 0x0, 0x0, 0x7f, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-128/base=AX/offset=0x4db", inst: MOVQ, c: -128, baseReg: RegAX, offset: 0x4db, exp: []byte{0x48, 0xc7, 0x80, 0xdb, 0x4, 0x0, 0x0, 0x80, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=32767/base=AX/offset=0x4db", inst: MOVQ, c: 32767, baseReg: RegAX, offset: 0x4db, exp: []byte{0x48, 0xc7, 0x80, 0xdb, 0x4, 0x0, 0x0, 0xff, 0x7f, 0x0, 0x0}}, - {name: "MOVQ/c=-32768/base=AX/offset=0x4db", inst: MOVQ, c: -32768, baseReg: RegAX, offset: 0x4db, exp: []byte{0x48, 0xc7, 0x80, 0xdb, 0x4, 0x0, 0x0, 0x0, 0x80, 0xff, 0xff}}, - {name: "MOVQ/c=1048576/base=AX/offset=0x4db", inst: MOVQ, c: 1048576, baseReg: RegAX, offset: 0x4db, exp: []byte{0x48, 0xc7, 0x80, 0xdb, 0x4, 0x0, 0x0, 0x0, 0x0, 0x10, 0x0}}, - {name: "MOVQ/c=-1048576/base=AX/offset=0x4db", inst: MOVQ, c: -1048576, baseReg: RegAX, offset: 0x4db, exp: []byte{0x48, 0xc7, 0x80, 0xdb, 0x4, 0x0, 0x0, 0x0, 0x0, 0xf0, 0xff}}, - {name: "MOVQ/c=2147483647/base=AX/offset=0x4db", inst: MOVQ, c: 2147483647, baseReg: RegAX, offset: 0x4db, exp: []byte{0x48, 0xc7, 0x80, 0xdb, 0x4, 0x0, 0x0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVQ/c=-2147483648/base=AX/offset=0x4db", inst: MOVQ, c: -2147483648, baseReg: RegAX, offset: 0x4db, exp: []byte{0x48, 0xc7, 0x80, 0xdb, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80}}, - {name: "MOVQ/c=0/base=AX/offset=-0x4d2", inst: MOVQ, c: 0, baseReg: RegAX, offset: -0x4d2, exp: []byte{0x48, 0xc7, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0x0, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=1/base=AX/offset=-0x4d2", inst: MOVQ, c: 1, baseReg: RegAX, offset: -0x4d2, exp: []byte{0x48, 0xc7, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0x1, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-1/base=AX/offset=-0x4d2", inst: MOVQ, c: -1, baseReg: RegAX, offset: -0x4d2, exp: []byte{0x48, 0xc7, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=100/base=AX/offset=-0x4d2", inst: MOVQ, c: 100, baseReg: RegAX, offset: -0x4d2, exp: []byte{0x48, 0xc7, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0x64, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-100/base=AX/offset=-0x4d2", inst: MOVQ, c: -100, baseReg: RegAX, offset: -0x4d2, exp: []byte{0x48, 0xc7, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0x9c, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=127/base=AX/offset=-0x4d2", inst: MOVQ, c: 127, baseReg: RegAX, offset: -0x4d2, exp: []byte{0x48, 0xc7, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0x7f, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-128/base=AX/offset=-0x4d2", inst: MOVQ, c: -128, baseReg: RegAX, offset: -0x4d2, exp: []byte{0x48, 0xc7, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0x80, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=32767/base=AX/offset=-0x4d2", inst: MOVQ, c: 32767, baseReg: RegAX, offset: -0x4d2, exp: []byte{0x48, 0xc7, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0xff, 0x7f, 0x0, 0x0}}, - {name: "MOVQ/c=-32768/base=AX/offset=-0x4d2", inst: MOVQ, c: -32768, baseReg: RegAX, offset: -0x4d2, exp: []byte{0x48, 0xc7, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0x0, 0x80, 0xff, 0xff}}, - {name: "MOVQ/c=1048576/base=AX/offset=-0x4d2", inst: MOVQ, c: 1048576, baseReg: RegAX, offset: -0x4d2, exp: []byte{0x48, 0xc7, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0x0, 0x0, 0x10, 0x0}}, - {name: "MOVQ/c=-1048576/base=AX/offset=-0x4d2", inst: MOVQ, c: -1048576, baseReg: RegAX, offset: -0x4d2, exp: []byte{0x48, 0xc7, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0x0, 0x0, 0xf0, 0xff}}, - {name: "MOVQ/c=2147483647/base=AX/offset=-0x4d2", inst: MOVQ, c: 2147483647, baseReg: RegAX, offset: -0x4d2, exp: []byte{0x48, 0xc7, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVQ/c=-2147483648/base=AX/offset=-0x4d2", inst: MOVQ, c: -2147483648, baseReg: RegAX, offset: -0x4d2, exp: []byte{0x48, 0xc7, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0x0, 0x0, 0x0, 0x80}}, - {name: "MOVQ/c=0/base=AX/offset=0x7fffffff", inst: MOVQ, c: 0, baseReg: RegAX, offset: 0x7fffffff, exp: []byte{0x48, 0xc7, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x0, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=1/base=AX/offset=0x7fffffff", inst: MOVQ, c: 1, baseReg: RegAX, offset: 0x7fffffff, exp: []byte{0x48, 0xc7, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x1, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-1/base=AX/offset=0x7fffffff", inst: MOVQ, c: -1, baseReg: RegAX, offset: 0x7fffffff, exp: []byte{0x48, 0xc7, 0x80, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=100/base=AX/offset=0x7fffffff", inst: MOVQ, c: 100, baseReg: RegAX, offset: 0x7fffffff, exp: []byte{0x48, 0xc7, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x64, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-100/base=AX/offset=0x7fffffff", inst: MOVQ, c: -100, baseReg: RegAX, offset: 0x7fffffff, exp: []byte{0x48, 0xc7, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x9c, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=127/base=AX/offset=0x7fffffff", inst: MOVQ, c: 127, baseReg: RegAX, offset: 0x7fffffff, exp: []byte{0x48, 0xc7, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x7f, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-128/base=AX/offset=0x7fffffff", inst: MOVQ, c: -128, baseReg: RegAX, offset: 0x7fffffff, exp: []byte{0x48, 0xc7, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x80, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=32767/base=AX/offset=0x7fffffff", inst: MOVQ, c: 32767, baseReg: RegAX, offset: 0x7fffffff, exp: []byte{0x48, 0xc7, 0x80, 0xff, 0xff, 0xff, 0x7f, 0xff, 0x7f, 0x0, 0x0}}, - {name: "MOVQ/c=-32768/base=AX/offset=0x7fffffff", inst: MOVQ, c: -32768, baseReg: RegAX, offset: 0x7fffffff, exp: []byte{0x48, 0xc7, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x0, 0x80, 0xff, 0xff}}, - {name: "MOVQ/c=1048576/base=AX/offset=0x7fffffff", inst: MOVQ, c: 1048576, baseReg: RegAX, offset: 0x7fffffff, exp: []byte{0x48, 0xc7, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x0, 0x0, 0x10, 0x0}}, - {name: "MOVQ/c=-1048576/base=AX/offset=0x7fffffff", inst: MOVQ, c: -1048576, baseReg: RegAX, offset: 0x7fffffff, exp: []byte{0x48, 0xc7, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x0, 0x0, 0xf0, 0xff}}, - {name: "MOVQ/c=2147483647/base=AX/offset=0x7fffffff", inst: MOVQ, c: 2147483647, baseReg: RegAX, offset: 0x7fffffff, exp: []byte{0x48, 0xc7, 0x80, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVQ/c=-2147483648/base=AX/offset=0x7fffffff", inst: MOVQ, c: -2147483648, baseReg: RegAX, offset: 0x7fffffff, exp: []byte{0x48, 0xc7, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x0, 0x0, 0x0, 0x80}}, - {name: "MOVQ/c=0/base=AX/offset=-0x80000000", inst: MOVQ, c: 0, baseReg: RegAX, offset: -0x80000000, exp: []byte{0x48, 0xc7, 0x80, 0x0, 0x0, 0x0, 0x80, 0x0, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=1/base=AX/offset=-0x80000000", inst: MOVQ, c: 1, baseReg: RegAX, offset: -0x80000000, exp: []byte{0x48, 0xc7, 0x80, 0x0, 0x0, 0x0, 0x80, 0x1, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-1/base=AX/offset=-0x80000000", inst: MOVQ, c: -1, baseReg: RegAX, offset: -0x80000000, exp: []byte{0x48, 0xc7, 0x80, 0x0, 0x0, 0x0, 0x80, 0xff, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=100/base=AX/offset=-0x80000000", inst: MOVQ, c: 100, baseReg: RegAX, offset: -0x80000000, exp: []byte{0x48, 0xc7, 0x80, 0x0, 0x0, 0x0, 0x80, 0x64, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-100/base=AX/offset=-0x80000000", inst: MOVQ, c: -100, baseReg: RegAX, offset: -0x80000000, exp: []byte{0x48, 0xc7, 0x80, 0x0, 0x0, 0x0, 0x80, 0x9c, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=127/base=AX/offset=-0x80000000", inst: MOVQ, c: 127, baseReg: RegAX, offset: -0x80000000, exp: []byte{0x48, 0xc7, 0x80, 0x0, 0x0, 0x0, 0x80, 0x7f, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-128/base=AX/offset=-0x80000000", inst: MOVQ, c: -128, baseReg: RegAX, offset: -0x80000000, exp: []byte{0x48, 0xc7, 0x80, 0x0, 0x0, 0x0, 0x80, 0x80, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=32767/base=AX/offset=-0x80000000", inst: MOVQ, c: 32767, baseReg: RegAX, offset: -0x80000000, exp: []byte{0x48, 0xc7, 0x80, 0x0, 0x0, 0x0, 0x80, 0xff, 0x7f, 0x0, 0x0}}, - {name: "MOVQ/c=-32768/base=AX/offset=-0x80000000", inst: MOVQ, c: -32768, baseReg: RegAX, offset: -0x80000000, exp: []byte{0x48, 0xc7, 0x80, 0x0, 0x0, 0x0, 0x80, 0x0, 0x80, 0xff, 0xff}}, - {name: "MOVQ/c=1048576/base=AX/offset=-0x80000000", inst: MOVQ, c: 1048576, baseReg: RegAX, offset: -0x80000000, exp: []byte{0x48, 0xc7, 0x80, 0x0, 0x0, 0x0, 0x80, 0x0, 0x0, 0x10, 0x0}}, - {name: "MOVQ/c=-1048576/base=AX/offset=-0x80000000", inst: MOVQ, c: -1048576, baseReg: RegAX, offset: -0x80000000, exp: []byte{0x48, 0xc7, 0x80, 0x0, 0x0, 0x0, 0x80, 0x0, 0x0, 0xf0, 0xff}}, - {name: "MOVQ/c=2147483647/base=AX/offset=-0x80000000", inst: MOVQ, c: 2147483647, baseReg: RegAX, offset: -0x80000000, exp: []byte{0x48, 0xc7, 0x80, 0x0, 0x0, 0x0, 0x80, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVQ/c=-2147483648/base=AX/offset=-0x80000000", inst: MOVQ, c: -2147483648, baseReg: RegAX, offset: -0x80000000, exp: []byte{0x48, 0xc7, 0x80, 0x0, 0x0, 0x0, 0x80, 0x0, 0x0, 0x0, 0x80}}, - {name: "MOVQ/c=0/base=AX/offset=0x7fff", inst: MOVQ, c: 0, baseReg: RegAX, offset: 0x7fff, exp: []byte{0x48, 0xc7, 0x80, 0xff, 0x7f, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=1/base=AX/offset=0x7fff", inst: MOVQ, c: 1, baseReg: RegAX, offset: 0x7fff, exp: []byte{0x48, 0xc7, 0x80, 0xff, 0x7f, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-1/base=AX/offset=0x7fff", inst: MOVQ, c: -1, baseReg: RegAX, offset: 0x7fff, exp: []byte{0x48, 0xc7, 0x80, 0xff, 0x7f, 0x0, 0x0, 0xff, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=100/base=AX/offset=0x7fff", inst: MOVQ, c: 100, baseReg: RegAX, offset: 0x7fff, exp: []byte{0x48, 0xc7, 0x80, 0xff, 0x7f, 0x0, 0x0, 0x64, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-100/base=AX/offset=0x7fff", inst: MOVQ, c: -100, baseReg: RegAX, offset: 0x7fff, exp: []byte{0x48, 0xc7, 0x80, 0xff, 0x7f, 0x0, 0x0, 0x9c, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=127/base=AX/offset=0x7fff", inst: MOVQ, c: 127, baseReg: RegAX, offset: 0x7fff, exp: []byte{0x48, 0xc7, 0x80, 0xff, 0x7f, 0x0, 0x0, 0x7f, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-128/base=AX/offset=0x7fff", inst: MOVQ, c: -128, baseReg: RegAX, offset: 0x7fff, exp: []byte{0x48, 0xc7, 0x80, 0xff, 0x7f, 0x0, 0x0, 0x80, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=32767/base=AX/offset=0x7fff", inst: MOVQ, c: 32767, baseReg: RegAX, offset: 0x7fff, exp: []byte{0x48, 0xc7, 0x80, 0xff, 0x7f, 0x0, 0x0, 0xff, 0x7f, 0x0, 0x0}}, - {name: "MOVQ/c=-32768/base=AX/offset=0x7fff", inst: MOVQ, c: -32768, baseReg: RegAX, offset: 0x7fff, exp: []byte{0x48, 0xc7, 0x80, 0xff, 0x7f, 0x0, 0x0, 0x0, 0x80, 0xff, 0xff}}, - {name: "MOVQ/c=1048576/base=AX/offset=0x7fff", inst: MOVQ, c: 1048576, baseReg: RegAX, offset: 0x7fff, exp: []byte{0x48, 0xc7, 0x80, 0xff, 0x7f, 0x0, 0x0, 0x0, 0x0, 0x10, 0x0}}, - {name: "MOVQ/c=-1048576/base=AX/offset=0x7fff", inst: MOVQ, c: -1048576, baseReg: RegAX, offset: 0x7fff, exp: []byte{0x48, 0xc7, 0x80, 0xff, 0x7f, 0x0, 0x0, 0x0, 0x0, 0xf0, 0xff}}, - {name: "MOVQ/c=2147483647/base=AX/offset=0x7fff", inst: MOVQ, c: 2147483647, baseReg: RegAX, offset: 0x7fff, exp: []byte{0x48, 0xc7, 0x80, 0xff, 0x7f, 0x0, 0x0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVQ/c=-2147483648/base=AX/offset=0x7fff", inst: MOVQ, c: -2147483648, baseReg: RegAX, offset: 0x7fff, exp: []byte{0x48, 0xc7, 0x80, 0xff, 0x7f, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80}}, - {name: "MOVQ/c=0/base=AX/offset=-0x8000", inst: MOVQ, c: 0, baseReg: RegAX, offset: -0x8000, exp: []byte{0x48, 0xc7, 0x80, 0x0, 0x80, 0xff, 0xff, 0x0, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=1/base=AX/offset=-0x8000", inst: MOVQ, c: 1, baseReg: RegAX, offset: -0x8000, exp: []byte{0x48, 0xc7, 0x80, 0x0, 0x80, 0xff, 0xff, 0x1, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-1/base=AX/offset=-0x8000", inst: MOVQ, c: -1, baseReg: RegAX, offset: -0x8000, exp: []byte{0x48, 0xc7, 0x80, 0x0, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=100/base=AX/offset=-0x8000", inst: MOVQ, c: 100, baseReg: RegAX, offset: -0x8000, exp: []byte{0x48, 0xc7, 0x80, 0x0, 0x80, 0xff, 0xff, 0x64, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-100/base=AX/offset=-0x8000", inst: MOVQ, c: -100, baseReg: RegAX, offset: -0x8000, exp: []byte{0x48, 0xc7, 0x80, 0x0, 0x80, 0xff, 0xff, 0x9c, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=127/base=AX/offset=-0x8000", inst: MOVQ, c: 127, baseReg: RegAX, offset: -0x8000, exp: []byte{0x48, 0xc7, 0x80, 0x0, 0x80, 0xff, 0xff, 0x7f, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-128/base=AX/offset=-0x8000", inst: MOVQ, c: -128, baseReg: RegAX, offset: -0x8000, exp: []byte{0x48, 0xc7, 0x80, 0x0, 0x80, 0xff, 0xff, 0x80, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=32767/base=AX/offset=-0x8000", inst: MOVQ, c: 32767, baseReg: RegAX, offset: -0x8000, exp: []byte{0x48, 0xc7, 0x80, 0x0, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x0, 0x0}}, - {name: "MOVQ/c=-32768/base=AX/offset=-0x8000", inst: MOVQ, c: -32768, baseReg: RegAX, offset: -0x8000, exp: []byte{0x48, 0xc7, 0x80, 0x0, 0x80, 0xff, 0xff, 0x0, 0x80, 0xff, 0xff}}, - {name: "MOVQ/c=1048576/base=AX/offset=-0x8000", inst: MOVQ, c: 1048576, baseReg: RegAX, offset: -0x8000, exp: []byte{0x48, 0xc7, 0x80, 0x0, 0x80, 0xff, 0xff, 0x0, 0x0, 0x10, 0x0}}, - {name: "MOVQ/c=-1048576/base=AX/offset=-0x8000", inst: MOVQ, c: -1048576, baseReg: RegAX, offset: -0x8000, exp: []byte{0x48, 0xc7, 0x80, 0x0, 0x80, 0xff, 0xff, 0x0, 0x0, 0xf0, 0xff}}, - {name: "MOVQ/c=2147483647/base=AX/offset=-0x8000", inst: MOVQ, c: 2147483647, baseReg: RegAX, offset: -0x8000, exp: []byte{0x48, 0xc7, 0x80, 0x0, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVQ/c=-2147483648/base=AX/offset=-0x8000", inst: MOVQ, c: -2147483648, baseReg: RegAX, offset: -0x8000, exp: []byte{0x48, 0xc7, 0x80, 0x0, 0x80, 0xff, 0xff, 0x0, 0x0, 0x0, 0x80}}, - {name: "MOVQ/c=0/base=R8/offset=0x0", inst: MOVQ, c: 0, baseReg: RegR8, offset: 0x0, exp: []byte{0x49, 0xc7, 0x0, 0x0, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=1/base=R8/offset=0x0", inst: MOVQ, c: 1, baseReg: RegR8, offset: 0x0, exp: []byte{0x49, 0xc7, 0x0, 0x1, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-1/base=R8/offset=0x0", inst: MOVQ, c: -1, baseReg: RegR8, offset: 0x0, exp: []byte{0x49, 0xc7, 0x0, 0xff, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=100/base=R8/offset=0x0", inst: MOVQ, c: 100, baseReg: RegR8, offset: 0x0, exp: []byte{0x49, 0xc7, 0x0, 0x64, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-100/base=R8/offset=0x0", inst: MOVQ, c: -100, baseReg: RegR8, offset: 0x0, exp: []byte{0x49, 0xc7, 0x0, 0x9c, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=127/base=R8/offset=0x0", inst: MOVQ, c: 127, baseReg: RegR8, offset: 0x0, exp: []byte{0x49, 0xc7, 0x0, 0x7f, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-128/base=R8/offset=0x0", inst: MOVQ, c: -128, baseReg: RegR8, offset: 0x0, exp: []byte{0x49, 0xc7, 0x0, 0x80, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=32767/base=R8/offset=0x0", inst: MOVQ, c: 32767, baseReg: RegR8, offset: 0x0, exp: []byte{0x49, 0xc7, 0x0, 0xff, 0x7f, 0x0, 0x0}}, - {name: "MOVQ/c=-32768/base=R8/offset=0x0", inst: MOVQ, c: -32768, baseReg: RegR8, offset: 0x0, exp: []byte{0x49, 0xc7, 0x0, 0x0, 0x80, 0xff, 0xff}}, - {name: "MOVQ/c=1048576/base=R8/offset=0x0", inst: MOVQ, c: 1048576, baseReg: RegR8, offset: 0x0, exp: []byte{0x49, 0xc7, 0x0, 0x0, 0x0, 0x10, 0x0}}, - {name: "MOVQ/c=-1048576/base=R8/offset=0x0", inst: MOVQ, c: -1048576, baseReg: RegR8, offset: 0x0, exp: []byte{0x49, 0xc7, 0x0, 0x0, 0x0, 0xf0, 0xff}}, - {name: "MOVQ/c=2147483647/base=R8/offset=0x0", inst: MOVQ, c: 2147483647, baseReg: RegR8, offset: 0x0, exp: []byte{0x49, 0xc7, 0x0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVQ/c=-2147483648/base=R8/offset=0x0", inst: MOVQ, c: -2147483648, baseReg: RegR8, offset: 0x0, exp: []byte{0x49, 0xc7, 0x0, 0x0, 0x0, 0x0, 0x80}}, - {name: "MOVQ/c=0/base=R8/offset=0x1", inst: MOVQ, c: 0, baseReg: RegR8, offset: 0x1, exp: []byte{0x49, 0xc7, 0x40, 0x1, 0x0, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=1/base=R8/offset=0x1", inst: MOVQ, c: 1, baseReg: RegR8, offset: 0x1, exp: []byte{0x49, 0xc7, 0x40, 0x1, 0x1, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-1/base=R8/offset=0x1", inst: MOVQ, c: -1, baseReg: RegR8, offset: 0x1, exp: []byte{0x49, 0xc7, 0x40, 0x1, 0xff, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=100/base=R8/offset=0x1", inst: MOVQ, c: 100, baseReg: RegR8, offset: 0x1, exp: []byte{0x49, 0xc7, 0x40, 0x1, 0x64, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-100/base=R8/offset=0x1", inst: MOVQ, c: -100, baseReg: RegR8, offset: 0x1, exp: []byte{0x49, 0xc7, 0x40, 0x1, 0x9c, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=127/base=R8/offset=0x1", inst: MOVQ, c: 127, baseReg: RegR8, offset: 0x1, exp: []byte{0x49, 0xc7, 0x40, 0x1, 0x7f, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-128/base=R8/offset=0x1", inst: MOVQ, c: -128, baseReg: RegR8, offset: 0x1, exp: []byte{0x49, 0xc7, 0x40, 0x1, 0x80, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=32767/base=R8/offset=0x1", inst: MOVQ, c: 32767, baseReg: RegR8, offset: 0x1, exp: []byte{0x49, 0xc7, 0x40, 0x1, 0xff, 0x7f, 0x0, 0x0}}, - {name: "MOVQ/c=-32768/base=R8/offset=0x1", inst: MOVQ, c: -32768, baseReg: RegR8, offset: 0x1, exp: []byte{0x49, 0xc7, 0x40, 0x1, 0x0, 0x80, 0xff, 0xff}}, - {name: "MOVQ/c=1048576/base=R8/offset=0x1", inst: MOVQ, c: 1048576, baseReg: RegR8, offset: 0x1, exp: []byte{0x49, 0xc7, 0x40, 0x1, 0x0, 0x0, 0x10, 0x0}}, - {name: "MOVQ/c=-1048576/base=R8/offset=0x1", inst: MOVQ, c: -1048576, baseReg: RegR8, offset: 0x1, exp: []byte{0x49, 0xc7, 0x40, 0x1, 0x0, 0x0, 0xf0, 0xff}}, - {name: "MOVQ/c=2147483647/base=R8/offset=0x1", inst: MOVQ, c: 2147483647, baseReg: RegR8, offset: 0x1, exp: []byte{0x49, 0xc7, 0x40, 0x1, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVQ/c=-2147483648/base=R8/offset=0x1", inst: MOVQ, c: -2147483648, baseReg: RegR8, offset: 0x1, exp: []byte{0x49, 0xc7, 0x40, 0x1, 0x0, 0x0, 0x0, 0x80}}, - {name: "MOVQ/c=0/base=R8/offset=-0x1", inst: MOVQ, c: 0, baseReg: RegR8, offset: -0x1, exp: []byte{0x49, 0xc7, 0x40, 0xff, 0x0, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=1/base=R8/offset=-0x1", inst: MOVQ, c: 1, baseReg: RegR8, offset: -0x1, exp: []byte{0x49, 0xc7, 0x40, 0xff, 0x1, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-1/base=R8/offset=-0x1", inst: MOVQ, c: -1, baseReg: RegR8, offset: -0x1, exp: []byte{0x49, 0xc7, 0x40, 0xff, 0xff, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=100/base=R8/offset=-0x1", inst: MOVQ, c: 100, baseReg: RegR8, offset: -0x1, exp: []byte{0x49, 0xc7, 0x40, 0xff, 0x64, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-100/base=R8/offset=-0x1", inst: MOVQ, c: -100, baseReg: RegR8, offset: -0x1, exp: []byte{0x49, 0xc7, 0x40, 0xff, 0x9c, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=127/base=R8/offset=-0x1", inst: MOVQ, c: 127, baseReg: RegR8, offset: -0x1, exp: []byte{0x49, 0xc7, 0x40, 0xff, 0x7f, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-128/base=R8/offset=-0x1", inst: MOVQ, c: -128, baseReg: RegR8, offset: -0x1, exp: []byte{0x49, 0xc7, 0x40, 0xff, 0x80, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=32767/base=R8/offset=-0x1", inst: MOVQ, c: 32767, baseReg: RegR8, offset: -0x1, exp: []byte{0x49, 0xc7, 0x40, 0xff, 0xff, 0x7f, 0x0, 0x0}}, - {name: "MOVQ/c=-32768/base=R8/offset=-0x1", inst: MOVQ, c: -32768, baseReg: RegR8, offset: -0x1, exp: []byte{0x49, 0xc7, 0x40, 0xff, 0x0, 0x80, 0xff, 0xff}}, - {name: "MOVQ/c=1048576/base=R8/offset=-0x1", inst: MOVQ, c: 1048576, baseReg: RegR8, offset: -0x1, exp: []byte{0x49, 0xc7, 0x40, 0xff, 0x0, 0x0, 0x10, 0x0}}, - {name: "MOVQ/c=-1048576/base=R8/offset=-0x1", inst: MOVQ, c: -1048576, baseReg: RegR8, offset: -0x1, exp: []byte{0x49, 0xc7, 0x40, 0xff, 0x0, 0x0, 0xf0, 0xff}}, - {name: "MOVQ/c=2147483647/base=R8/offset=-0x1", inst: MOVQ, c: 2147483647, baseReg: RegR8, offset: -0x1, exp: []byte{0x49, 0xc7, 0x40, 0xff, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVQ/c=-2147483648/base=R8/offset=-0x1", inst: MOVQ, c: -2147483648, baseReg: RegR8, offset: -0x1, exp: []byte{0x49, 0xc7, 0x40, 0xff, 0x0, 0x0, 0x0, 0x80}}, - {name: "MOVQ/c=0/base=R8/offset=0x4db", inst: MOVQ, c: 0, baseReg: RegR8, offset: 0x4db, exp: []byte{0x49, 0xc7, 0x80, 0xdb, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=1/base=R8/offset=0x4db", inst: MOVQ, c: 1, baseReg: RegR8, offset: 0x4db, exp: []byte{0x49, 0xc7, 0x80, 0xdb, 0x4, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-1/base=R8/offset=0x4db", inst: MOVQ, c: -1, baseReg: RegR8, offset: 0x4db, exp: []byte{0x49, 0xc7, 0x80, 0xdb, 0x4, 0x0, 0x0, 0xff, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=100/base=R8/offset=0x4db", inst: MOVQ, c: 100, baseReg: RegR8, offset: 0x4db, exp: []byte{0x49, 0xc7, 0x80, 0xdb, 0x4, 0x0, 0x0, 0x64, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-100/base=R8/offset=0x4db", inst: MOVQ, c: -100, baseReg: RegR8, offset: 0x4db, exp: []byte{0x49, 0xc7, 0x80, 0xdb, 0x4, 0x0, 0x0, 0x9c, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=127/base=R8/offset=0x4db", inst: MOVQ, c: 127, baseReg: RegR8, offset: 0x4db, exp: []byte{0x49, 0xc7, 0x80, 0xdb, 0x4, 0x0, 0x0, 0x7f, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-128/base=R8/offset=0x4db", inst: MOVQ, c: -128, baseReg: RegR8, offset: 0x4db, exp: []byte{0x49, 0xc7, 0x80, 0xdb, 0x4, 0x0, 0x0, 0x80, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=32767/base=R8/offset=0x4db", inst: MOVQ, c: 32767, baseReg: RegR8, offset: 0x4db, exp: []byte{0x49, 0xc7, 0x80, 0xdb, 0x4, 0x0, 0x0, 0xff, 0x7f, 0x0, 0x0}}, - {name: "MOVQ/c=-32768/base=R8/offset=0x4db", inst: MOVQ, c: -32768, baseReg: RegR8, offset: 0x4db, exp: []byte{0x49, 0xc7, 0x80, 0xdb, 0x4, 0x0, 0x0, 0x0, 0x80, 0xff, 0xff}}, - {name: "MOVQ/c=1048576/base=R8/offset=0x4db", inst: MOVQ, c: 1048576, baseReg: RegR8, offset: 0x4db, exp: []byte{0x49, 0xc7, 0x80, 0xdb, 0x4, 0x0, 0x0, 0x0, 0x0, 0x10, 0x0}}, - {name: "MOVQ/c=-1048576/base=R8/offset=0x4db", inst: MOVQ, c: -1048576, baseReg: RegR8, offset: 0x4db, exp: []byte{0x49, 0xc7, 0x80, 0xdb, 0x4, 0x0, 0x0, 0x0, 0x0, 0xf0, 0xff}}, - {name: "MOVQ/c=2147483647/base=R8/offset=0x4db", inst: MOVQ, c: 2147483647, baseReg: RegR8, offset: 0x4db, exp: []byte{0x49, 0xc7, 0x80, 0xdb, 0x4, 0x0, 0x0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVQ/c=-2147483648/base=R8/offset=0x4db", inst: MOVQ, c: -2147483648, baseReg: RegR8, offset: 0x4db, exp: []byte{0x49, 0xc7, 0x80, 0xdb, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80}}, - {name: "MOVQ/c=0/base=R8/offset=-0x4d2", inst: MOVQ, c: 0, baseReg: RegR8, offset: -0x4d2, exp: []byte{0x49, 0xc7, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0x0, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=1/base=R8/offset=-0x4d2", inst: MOVQ, c: 1, baseReg: RegR8, offset: -0x4d2, exp: []byte{0x49, 0xc7, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0x1, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-1/base=R8/offset=-0x4d2", inst: MOVQ, c: -1, baseReg: RegR8, offset: -0x4d2, exp: []byte{0x49, 0xc7, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=100/base=R8/offset=-0x4d2", inst: MOVQ, c: 100, baseReg: RegR8, offset: -0x4d2, exp: []byte{0x49, 0xc7, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0x64, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-100/base=R8/offset=-0x4d2", inst: MOVQ, c: -100, baseReg: RegR8, offset: -0x4d2, exp: []byte{0x49, 0xc7, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0x9c, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=127/base=R8/offset=-0x4d2", inst: MOVQ, c: 127, baseReg: RegR8, offset: -0x4d2, exp: []byte{0x49, 0xc7, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0x7f, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-128/base=R8/offset=-0x4d2", inst: MOVQ, c: -128, baseReg: RegR8, offset: -0x4d2, exp: []byte{0x49, 0xc7, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0x80, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=32767/base=R8/offset=-0x4d2", inst: MOVQ, c: 32767, baseReg: RegR8, offset: -0x4d2, exp: []byte{0x49, 0xc7, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0xff, 0x7f, 0x0, 0x0}}, - {name: "MOVQ/c=-32768/base=R8/offset=-0x4d2", inst: MOVQ, c: -32768, baseReg: RegR8, offset: -0x4d2, exp: []byte{0x49, 0xc7, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0x0, 0x80, 0xff, 0xff}}, - {name: "MOVQ/c=1048576/base=R8/offset=-0x4d2", inst: MOVQ, c: 1048576, baseReg: RegR8, offset: -0x4d2, exp: []byte{0x49, 0xc7, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0x0, 0x0, 0x10, 0x0}}, - {name: "MOVQ/c=-1048576/base=R8/offset=-0x4d2", inst: MOVQ, c: -1048576, baseReg: RegR8, offset: -0x4d2, exp: []byte{0x49, 0xc7, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0x0, 0x0, 0xf0, 0xff}}, - {name: "MOVQ/c=2147483647/base=R8/offset=-0x4d2", inst: MOVQ, c: 2147483647, baseReg: RegR8, offset: -0x4d2, exp: []byte{0x49, 0xc7, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVQ/c=-2147483648/base=R8/offset=-0x4d2", inst: MOVQ, c: -2147483648, baseReg: RegR8, offset: -0x4d2, exp: []byte{0x49, 0xc7, 0x80, 0x2e, 0xfb, 0xff, 0xff, 0x0, 0x0, 0x0, 0x80}}, - {name: "MOVQ/c=0/base=R8/offset=0x7fffffff", inst: MOVQ, c: 0, baseReg: RegR8, offset: 0x7fffffff, exp: []byte{0x49, 0xc7, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x0, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=1/base=R8/offset=0x7fffffff", inst: MOVQ, c: 1, baseReg: RegR8, offset: 0x7fffffff, exp: []byte{0x49, 0xc7, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x1, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-1/base=R8/offset=0x7fffffff", inst: MOVQ, c: -1, baseReg: RegR8, offset: 0x7fffffff, exp: []byte{0x49, 0xc7, 0x80, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=100/base=R8/offset=0x7fffffff", inst: MOVQ, c: 100, baseReg: RegR8, offset: 0x7fffffff, exp: []byte{0x49, 0xc7, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x64, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-100/base=R8/offset=0x7fffffff", inst: MOVQ, c: -100, baseReg: RegR8, offset: 0x7fffffff, exp: []byte{0x49, 0xc7, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x9c, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=127/base=R8/offset=0x7fffffff", inst: MOVQ, c: 127, baseReg: RegR8, offset: 0x7fffffff, exp: []byte{0x49, 0xc7, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x7f, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-128/base=R8/offset=0x7fffffff", inst: MOVQ, c: -128, baseReg: RegR8, offset: 0x7fffffff, exp: []byte{0x49, 0xc7, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x80, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=32767/base=R8/offset=0x7fffffff", inst: MOVQ, c: 32767, baseReg: RegR8, offset: 0x7fffffff, exp: []byte{0x49, 0xc7, 0x80, 0xff, 0xff, 0xff, 0x7f, 0xff, 0x7f, 0x0, 0x0}}, - {name: "MOVQ/c=-32768/base=R8/offset=0x7fffffff", inst: MOVQ, c: -32768, baseReg: RegR8, offset: 0x7fffffff, exp: []byte{0x49, 0xc7, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x0, 0x80, 0xff, 0xff}}, - {name: "MOVQ/c=1048576/base=R8/offset=0x7fffffff", inst: MOVQ, c: 1048576, baseReg: RegR8, offset: 0x7fffffff, exp: []byte{0x49, 0xc7, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x0, 0x0, 0x10, 0x0}}, - {name: "MOVQ/c=-1048576/base=R8/offset=0x7fffffff", inst: MOVQ, c: -1048576, baseReg: RegR8, offset: 0x7fffffff, exp: []byte{0x49, 0xc7, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x0, 0x0, 0xf0, 0xff}}, - {name: "MOVQ/c=2147483647/base=R8/offset=0x7fffffff", inst: MOVQ, c: 2147483647, baseReg: RegR8, offset: 0x7fffffff, exp: []byte{0x49, 0xc7, 0x80, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVQ/c=-2147483648/base=R8/offset=0x7fffffff", inst: MOVQ, c: -2147483648, baseReg: RegR8, offset: 0x7fffffff, exp: []byte{0x49, 0xc7, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x0, 0x0, 0x0, 0x80}}, - {name: "MOVQ/c=0/base=R8/offset=-0x80000000", inst: MOVQ, c: 0, baseReg: RegR8, offset: -0x80000000, exp: []byte{0x49, 0xc7, 0x80, 0x0, 0x0, 0x0, 0x80, 0x0, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=1/base=R8/offset=-0x80000000", inst: MOVQ, c: 1, baseReg: RegR8, offset: -0x80000000, exp: []byte{0x49, 0xc7, 0x80, 0x0, 0x0, 0x0, 0x80, 0x1, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-1/base=R8/offset=-0x80000000", inst: MOVQ, c: -1, baseReg: RegR8, offset: -0x80000000, exp: []byte{0x49, 0xc7, 0x80, 0x0, 0x0, 0x0, 0x80, 0xff, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=100/base=R8/offset=-0x80000000", inst: MOVQ, c: 100, baseReg: RegR8, offset: -0x80000000, exp: []byte{0x49, 0xc7, 0x80, 0x0, 0x0, 0x0, 0x80, 0x64, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-100/base=R8/offset=-0x80000000", inst: MOVQ, c: -100, baseReg: RegR8, offset: -0x80000000, exp: []byte{0x49, 0xc7, 0x80, 0x0, 0x0, 0x0, 0x80, 0x9c, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=127/base=R8/offset=-0x80000000", inst: MOVQ, c: 127, baseReg: RegR8, offset: -0x80000000, exp: []byte{0x49, 0xc7, 0x80, 0x0, 0x0, 0x0, 0x80, 0x7f, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-128/base=R8/offset=-0x80000000", inst: MOVQ, c: -128, baseReg: RegR8, offset: -0x80000000, exp: []byte{0x49, 0xc7, 0x80, 0x0, 0x0, 0x0, 0x80, 0x80, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=32767/base=R8/offset=-0x80000000", inst: MOVQ, c: 32767, baseReg: RegR8, offset: -0x80000000, exp: []byte{0x49, 0xc7, 0x80, 0x0, 0x0, 0x0, 0x80, 0xff, 0x7f, 0x0, 0x0}}, - {name: "MOVQ/c=-32768/base=R8/offset=-0x80000000", inst: MOVQ, c: -32768, baseReg: RegR8, offset: -0x80000000, exp: []byte{0x49, 0xc7, 0x80, 0x0, 0x0, 0x0, 0x80, 0x0, 0x80, 0xff, 0xff}}, - {name: "MOVQ/c=1048576/base=R8/offset=-0x80000000", inst: MOVQ, c: 1048576, baseReg: RegR8, offset: -0x80000000, exp: []byte{0x49, 0xc7, 0x80, 0x0, 0x0, 0x0, 0x80, 0x0, 0x0, 0x10, 0x0}}, - {name: "MOVQ/c=-1048576/base=R8/offset=-0x80000000", inst: MOVQ, c: -1048576, baseReg: RegR8, offset: -0x80000000, exp: []byte{0x49, 0xc7, 0x80, 0x0, 0x0, 0x0, 0x80, 0x0, 0x0, 0xf0, 0xff}}, - {name: "MOVQ/c=2147483647/base=R8/offset=-0x80000000", inst: MOVQ, c: 2147483647, baseReg: RegR8, offset: -0x80000000, exp: []byte{0x49, 0xc7, 0x80, 0x0, 0x0, 0x0, 0x80, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVQ/c=-2147483648/base=R8/offset=-0x80000000", inst: MOVQ, c: -2147483648, baseReg: RegR8, offset: -0x80000000, exp: []byte{0x49, 0xc7, 0x80, 0x0, 0x0, 0x0, 0x80, 0x0, 0x0, 0x0, 0x80}}, - {name: "MOVQ/c=0/base=R8/offset=0x7fff", inst: MOVQ, c: 0, baseReg: RegR8, offset: 0x7fff, exp: []byte{0x49, 0xc7, 0x80, 0xff, 0x7f, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=1/base=R8/offset=0x7fff", inst: MOVQ, c: 1, baseReg: RegR8, offset: 0x7fff, exp: []byte{0x49, 0xc7, 0x80, 0xff, 0x7f, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-1/base=R8/offset=0x7fff", inst: MOVQ, c: -1, baseReg: RegR8, offset: 0x7fff, exp: []byte{0x49, 0xc7, 0x80, 0xff, 0x7f, 0x0, 0x0, 0xff, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=100/base=R8/offset=0x7fff", inst: MOVQ, c: 100, baseReg: RegR8, offset: 0x7fff, exp: []byte{0x49, 0xc7, 0x80, 0xff, 0x7f, 0x0, 0x0, 0x64, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-100/base=R8/offset=0x7fff", inst: MOVQ, c: -100, baseReg: RegR8, offset: 0x7fff, exp: []byte{0x49, 0xc7, 0x80, 0xff, 0x7f, 0x0, 0x0, 0x9c, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=127/base=R8/offset=0x7fff", inst: MOVQ, c: 127, baseReg: RegR8, offset: 0x7fff, exp: []byte{0x49, 0xc7, 0x80, 0xff, 0x7f, 0x0, 0x0, 0x7f, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-128/base=R8/offset=0x7fff", inst: MOVQ, c: -128, baseReg: RegR8, offset: 0x7fff, exp: []byte{0x49, 0xc7, 0x80, 0xff, 0x7f, 0x0, 0x0, 0x80, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=32767/base=R8/offset=0x7fff", inst: MOVQ, c: 32767, baseReg: RegR8, offset: 0x7fff, exp: []byte{0x49, 0xc7, 0x80, 0xff, 0x7f, 0x0, 0x0, 0xff, 0x7f, 0x0, 0x0}}, - {name: "MOVQ/c=-32768/base=R8/offset=0x7fff", inst: MOVQ, c: -32768, baseReg: RegR8, offset: 0x7fff, exp: []byte{0x49, 0xc7, 0x80, 0xff, 0x7f, 0x0, 0x0, 0x0, 0x80, 0xff, 0xff}}, - {name: "MOVQ/c=1048576/base=R8/offset=0x7fff", inst: MOVQ, c: 1048576, baseReg: RegR8, offset: 0x7fff, exp: []byte{0x49, 0xc7, 0x80, 0xff, 0x7f, 0x0, 0x0, 0x0, 0x0, 0x10, 0x0}}, - {name: "MOVQ/c=-1048576/base=R8/offset=0x7fff", inst: MOVQ, c: -1048576, baseReg: RegR8, offset: 0x7fff, exp: []byte{0x49, 0xc7, 0x80, 0xff, 0x7f, 0x0, 0x0, 0x0, 0x0, 0xf0, 0xff}}, - {name: "MOVQ/c=2147483647/base=R8/offset=0x7fff", inst: MOVQ, c: 2147483647, baseReg: RegR8, offset: 0x7fff, exp: []byte{0x49, 0xc7, 0x80, 0xff, 0x7f, 0x0, 0x0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVQ/c=-2147483648/base=R8/offset=0x7fff", inst: MOVQ, c: -2147483648, baseReg: RegR8, offset: 0x7fff, exp: []byte{0x49, 0xc7, 0x80, 0xff, 0x7f, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80}}, - {name: "MOVQ/c=0/base=R8/offset=-0x8000", inst: MOVQ, c: 0, baseReg: RegR8, offset: -0x8000, exp: []byte{0x49, 0xc7, 0x80, 0x0, 0x80, 0xff, 0xff, 0x0, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=1/base=R8/offset=-0x8000", inst: MOVQ, c: 1, baseReg: RegR8, offset: -0x8000, exp: []byte{0x49, 0xc7, 0x80, 0x0, 0x80, 0xff, 0xff, 0x1, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-1/base=R8/offset=-0x8000", inst: MOVQ, c: -1, baseReg: RegR8, offset: -0x8000, exp: []byte{0x49, 0xc7, 0x80, 0x0, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=100/base=R8/offset=-0x8000", inst: MOVQ, c: 100, baseReg: RegR8, offset: -0x8000, exp: []byte{0x49, 0xc7, 0x80, 0x0, 0x80, 0xff, 0xff, 0x64, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-100/base=R8/offset=-0x8000", inst: MOVQ, c: -100, baseReg: RegR8, offset: -0x8000, exp: []byte{0x49, 0xc7, 0x80, 0x0, 0x80, 0xff, 0xff, 0x9c, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=127/base=R8/offset=-0x8000", inst: MOVQ, c: 127, baseReg: RegR8, offset: -0x8000, exp: []byte{0x49, 0xc7, 0x80, 0x0, 0x80, 0xff, 0xff, 0x7f, 0x0, 0x0, 0x0}}, - {name: "MOVQ/c=-128/base=R8/offset=-0x8000", inst: MOVQ, c: -128, baseReg: RegR8, offset: -0x8000, exp: []byte{0x49, 0xc7, 0x80, 0x0, 0x80, 0xff, 0xff, 0x80, 0xff, 0xff, 0xff}}, - {name: "MOVQ/c=32767/base=R8/offset=-0x8000", inst: MOVQ, c: 32767, baseReg: RegR8, offset: -0x8000, exp: []byte{0x49, 0xc7, 0x80, 0x0, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x0, 0x0}}, - {name: "MOVQ/c=-32768/base=R8/offset=-0x8000", inst: MOVQ, c: -32768, baseReg: RegR8, offset: -0x8000, exp: []byte{0x49, 0xc7, 0x80, 0x0, 0x80, 0xff, 0xff, 0x0, 0x80, 0xff, 0xff}}, - {name: "MOVQ/c=1048576/base=R8/offset=-0x8000", inst: MOVQ, c: 1048576, baseReg: RegR8, offset: -0x8000, exp: []byte{0x49, 0xc7, 0x80, 0x0, 0x80, 0xff, 0xff, 0x0, 0x0, 0x10, 0x0}}, - {name: "MOVQ/c=-1048576/base=R8/offset=-0x8000", inst: MOVQ, c: -1048576, baseReg: RegR8, offset: -0x8000, exp: []byte{0x49, 0xc7, 0x80, 0x0, 0x80, 0xff, 0xff, 0x0, 0x0, 0xf0, 0xff}}, - {name: "MOVQ/c=2147483647/base=R8/offset=-0x8000", inst: MOVQ, c: 2147483647, baseReg: RegR8, offset: -0x8000, exp: []byte{0x49, 0xc7, 0x80, 0x0, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f}}, - {name: "MOVQ/c=-2147483648/base=R8/offset=-0x8000", inst: MOVQ, c: -2147483648, baseReg: RegR8, offset: -0x8000, exp: []byte{0x49, 0xc7, 0x80, 0x0, 0x80, 0xff, 0xff, 0x0, 0x0, 0x0, 0x80}}, - } - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - for _, tc := range tests { - a := NewAssembler() - buf := code.NextCodeSection() - err := a.encodeConstToMemory(buf, &nodeImpl{ - instruction: tc.inst, - types: operandTypesConstToMemory, srcConst: tc.c, dstReg: tc.baseReg, dstConst: int64(tc.offset), - }) - require.NoError(t, err) - } -} - -func TestAssemblerImpl_EncodeMemoryToConst(t *testing.T) { - t.Run("error", func(t *testing.T) { - tests := []struct { - n *nodeImpl - expErr string - }{ - { - n: &nodeImpl{instruction: ADDL, types: operandTypesMemoryToConst, dstReg: RegAX}, - expErr: "ADDL is unsupported for MemoryToConst type", - }, - } - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - for _, tc := range tests { - a := NewAssembler() - buf := code.NextCodeSection() - err := a.encodeMemoryToConst(buf, tc.n) - require.EqualError(t, err, tc.expErr) - } - }) - - tests := []struct { - name string - inst asm.Instruction - baseReg asm.Register - offset, c int64 - exp []byte - }{ - {name: "CMPL/base=AX/offset=0x0/c=0", inst: CMPL, baseReg: RegAX, offset: 0x0, c: 0, exp: []byte{0x83, 0x38, 0x0}}, - {name: "CMPL/base=AX/offset=0x0/c=1", inst: CMPL, baseReg: RegAX, offset: 0x0, c: 1, exp: []byte{0x83, 0x38, 0x1}}, - {name: "CMPL/base=AX/offset=0x0/c=-1", inst: CMPL, baseReg: RegAX, offset: 0x0, c: -1, exp: []byte{0x83, 0x38, 0xff}}, - {name: "CMPL/base=AX/offset=0x0/c=100", inst: CMPL, baseReg: RegAX, offset: 0x0, c: 100, exp: []byte{0x83, 0x38, 0x64}}, - {name: "CMPL/base=AX/offset=0x0/c=-100", inst: CMPL, baseReg: RegAX, offset: 0x0, c: -100, exp: []byte{0x83, 0x38, 0x9c}}, - {name: "CMPL/base=AX/offset=0x0/c=127", inst: CMPL, baseReg: RegAX, offset: 0x0, c: 127, exp: []byte{0x83, 0x38, 0x7f}}, - {name: "CMPL/base=AX/offset=0x0/c=-128", inst: CMPL, baseReg: RegAX, offset: 0x0, c: -128, exp: []byte{0x83, 0x38, 0x80}}, - {name: "CMPL/base=AX/offset=0x0/c=32767", inst: CMPL, baseReg: RegAX, offset: 0x0, c: 32767, exp: []byte{0x81, 0x38, 0xff, 0x7f, 0x0, 0x0}}, - {name: "CMPL/base=AX/offset=0x0/c=-32768", inst: CMPL, baseReg: RegAX, offset: 0x0, c: -32768, exp: []byte{0x81, 0x38, 0x0, 0x80, 0xff, 0xff}}, - {name: "CMPL/base=AX/offset=0x0/c=1048576", inst: CMPL, baseReg: RegAX, offset: 0x0, c: 1048576, exp: []byte{0x81, 0x38, 0x0, 0x0, 0x10, 0x0}}, - {name: "CMPL/base=AX/offset=0x0/c=-1048576", inst: CMPL, baseReg: RegAX, offset: 0x0, c: -1048576, exp: []byte{0x81, 0x38, 0x0, 0x0, 0xf0, 0xff}}, - {name: "CMPL/base=AX/offset=0x0/c=2147483647", inst: CMPL, baseReg: RegAX, offset: 0x0, c: 2147483647, exp: []byte{0x81, 0x38, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPL/base=AX/offset=0x0/c=-2147483648", inst: CMPL, baseReg: RegAX, offset: 0x0, c: -2147483648, exp: []byte{0x81, 0x38, 0x0, 0x0, 0x0, 0x80}}, - {name: "CMPL/base=AX/offset=0x1/c=0", inst: CMPL, baseReg: RegAX, offset: 0x1, c: 0, exp: []byte{0x83, 0x78, 0x1, 0x0}}, - {name: "CMPL/base=AX/offset=0x1/c=1", inst: CMPL, baseReg: RegAX, offset: 0x1, c: 1, exp: []byte{0x83, 0x78, 0x1, 0x1}}, - {name: "CMPL/base=AX/offset=0x1/c=-1", inst: CMPL, baseReg: RegAX, offset: 0x1, c: -1, exp: []byte{0x83, 0x78, 0x1, 0xff}}, - {name: "CMPL/base=AX/offset=0x1/c=100", inst: CMPL, baseReg: RegAX, offset: 0x1, c: 100, exp: []byte{0x83, 0x78, 0x1, 0x64}}, - {name: "CMPL/base=AX/offset=0x1/c=-100", inst: CMPL, baseReg: RegAX, offset: 0x1, c: -100, exp: []byte{0x83, 0x78, 0x1, 0x9c}}, - {name: "CMPL/base=AX/offset=0x1/c=127", inst: CMPL, baseReg: RegAX, offset: 0x1, c: 127, exp: []byte{0x83, 0x78, 0x1, 0x7f}}, - {name: "CMPL/base=AX/offset=0x1/c=-128", inst: CMPL, baseReg: RegAX, offset: 0x1, c: -128, exp: []byte{0x83, 0x78, 0x1, 0x80}}, - {name: "CMPL/base=AX/offset=0x1/c=32767", inst: CMPL, baseReg: RegAX, offset: 0x1, c: 32767, exp: []byte{0x81, 0x78, 0x1, 0xff, 0x7f, 0x0, 0x0}}, - {name: "CMPL/base=AX/offset=0x1/c=-32768", inst: CMPL, baseReg: RegAX, offset: 0x1, c: -32768, exp: []byte{0x81, 0x78, 0x1, 0x0, 0x80, 0xff, 0xff}}, - {name: "CMPL/base=AX/offset=0x1/c=1048576", inst: CMPL, baseReg: RegAX, offset: 0x1, c: 1048576, exp: []byte{0x81, 0x78, 0x1, 0x0, 0x0, 0x10, 0x0}}, - {name: "CMPL/base=AX/offset=0x1/c=-1048576", inst: CMPL, baseReg: RegAX, offset: 0x1, c: -1048576, exp: []byte{0x81, 0x78, 0x1, 0x0, 0x0, 0xf0, 0xff}}, - {name: "CMPL/base=AX/offset=0x1/c=2147483647", inst: CMPL, baseReg: RegAX, offset: 0x1, c: 2147483647, exp: []byte{0x81, 0x78, 0x1, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPL/base=AX/offset=0x1/c=-2147483648", inst: CMPL, baseReg: RegAX, offset: 0x1, c: -2147483648, exp: []byte{0x81, 0x78, 0x1, 0x0, 0x0, 0x0, 0x80}}, - {name: "CMPL/base=AX/offset=-0x1/c=0", inst: CMPL, baseReg: RegAX, offset: -0x1, c: 0, exp: []byte{0x83, 0x78, 0xff, 0x0}}, - {name: "CMPL/base=AX/offset=-0x1/c=1", inst: CMPL, baseReg: RegAX, offset: -0x1, c: 1, exp: []byte{0x83, 0x78, 0xff, 0x1}}, - {name: "CMPL/base=AX/offset=-0x1/c=-1", inst: CMPL, baseReg: RegAX, offset: -0x1, c: -1, exp: []byte{0x83, 0x78, 0xff, 0xff}}, - {name: "CMPL/base=AX/offset=-0x1/c=100", inst: CMPL, baseReg: RegAX, offset: -0x1, c: 100, exp: []byte{0x83, 0x78, 0xff, 0x64}}, - {name: "CMPL/base=AX/offset=-0x1/c=-100", inst: CMPL, baseReg: RegAX, offset: -0x1, c: -100, exp: []byte{0x83, 0x78, 0xff, 0x9c}}, - {name: "CMPL/base=AX/offset=-0x1/c=127", inst: CMPL, baseReg: RegAX, offset: -0x1, c: 127, exp: []byte{0x83, 0x78, 0xff, 0x7f}}, - {name: "CMPL/base=AX/offset=-0x1/c=-128", inst: CMPL, baseReg: RegAX, offset: -0x1, c: -128, exp: []byte{0x83, 0x78, 0xff, 0x80}}, - {name: "CMPL/base=AX/offset=-0x1/c=32767", inst: CMPL, baseReg: RegAX, offset: -0x1, c: 32767, exp: []byte{0x81, 0x78, 0xff, 0xff, 0x7f, 0x0, 0x0}}, - {name: "CMPL/base=AX/offset=-0x1/c=-32768", inst: CMPL, baseReg: RegAX, offset: -0x1, c: -32768, exp: []byte{0x81, 0x78, 0xff, 0x0, 0x80, 0xff, 0xff}}, - {name: "CMPL/base=AX/offset=-0x1/c=1048576", inst: CMPL, baseReg: RegAX, offset: -0x1, c: 1048576, exp: []byte{0x81, 0x78, 0xff, 0x0, 0x0, 0x10, 0x0}}, - {name: "CMPL/base=AX/offset=-0x1/c=-1048576", inst: CMPL, baseReg: RegAX, offset: -0x1, c: -1048576, exp: []byte{0x81, 0x78, 0xff, 0x0, 0x0, 0xf0, 0xff}}, - {name: "CMPL/base=AX/offset=-0x1/c=2147483647", inst: CMPL, baseReg: RegAX, offset: -0x1, c: 2147483647, exp: []byte{0x81, 0x78, 0xff, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPL/base=AX/offset=-0x1/c=-2147483648", inst: CMPL, baseReg: RegAX, offset: -0x1, c: -2147483648, exp: []byte{0x81, 0x78, 0xff, 0x0, 0x0, 0x0, 0x80}}, - {name: "CMPL/base=AX/offset=0x4db/c=0", inst: CMPL, baseReg: RegAX, offset: 0x4db, c: 0, exp: []byte{0x83, 0xb8, 0xdb, 0x4, 0x0, 0x0, 0x0}}, - {name: "CMPL/base=AX/offset=0x4db/c=1", inst: CMPL, baseReg: RegAX, offset: 0x4db, c: 1, exp: []byte{0x83, 0xb8, 0xdb, 0x4, 0x0, 0x0, 0x1}}, - {name: "CMPL/base=AX/offset=0x4db/c=-1", inst: CMPL, baseReg: RegAX, offset: 0x4db, c: -1, exp: []byte{0x83, 0xb8, 0xdb, 0x4, 0x0, 0x0, 0xff}}, - {name: "CMPL/base=AX/offset=0x4db/c=100", inst: CMPL, baseReg: RegAX, offset: 0x4db, c: 100, exp: []byte{0x83, 0xb8, 0xdb, 0x4, 0x0, 0x0, 0x64}}, - {name: "CMPL/base=AX/offset=0x4db/c=-100", inst: CMPL, baseReg: RegAX, offset: 0x4db, c: -100, exp: []byte{0x83, 0xb8, 0xdb, 0x4, 0x0, 0x0, 0x9c}}, - {name: "CMPL/base=AX/offset=0x4db/c=127", inst: CMPL, baseReg: RegAX, offset: 0x4db, c: 127, exp: []byte{0x83, 0xb8, 0xdb, 0x4, 0x0, 0x0, 0x7f}}, - {name: "CMPL/base=AX/offset=0x4db/c=-128", inst: CMPL, baseReg: RegAX, offset: 0x4db, c: -128, exp: []byte{0x83, 0xb8, 0xdb, 0x4, 0x0, 0x0, 0x80}}, - {name: "CMPL/base=AX/offset=0x4db/c=32767", inst: CMPL, baseReg: RegAX, offset: 0x4db, c: 32767, exp: []byte{0x81, 0xb8, 0xdb, 0x4, 0x0, 0x0, 0xff, 0x7f, 0x0, 0x0}}, - {name: "CMPL/base=AX/offset=0x4db/c=-32768", inst: CMPL, baseReg: RegAX, offset: 0x4db, c: -32768, exp: []byte{0x81, 0xb8, 0xdb, 0x4, 0x0, 0x0, 0x0, 0x80, 0xff, 0xff}}, - {name: "CMPL/base=AX/offset=0x4db/c=1048576", inst: CMPL, baseReg: RegAX, offset: 0x4db, c: 1048576, exp: []byte{0x81, 0xb8, 0xdb, 0x4, 0x0, 0x0, 0x0, 0x0, 0x10, 0x0}}, - {name: "CMPL/base=AX/offset=0x4db/c=-1048576", inst: CMPL, baseReg: RegAX, offset: 0x4db, c: -1048576, exp: []byte{0x81, 0xb8, 0xdb, 0x4, 0x0, 0x0, 0x0, 0x0, 0xf0, 0xff}}, - {name: "CMPL/base=AX/offset=0x4db/c=2147483647", inst: CMPL, baseReg: RegAX, offset: 0x4db, c: 2147483647, exp: []byte{0x81, 0xb8, 0xdb, 0x4, 0x0, 0x0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPL/base=AX/offset=0x4db/c=-2147483648", inst: CMPL, baseReg: RegAX, offset: 0x4db, c: -2147483648, exp: []byte{0x81, 0xb8, 0xdb, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80}}, - {name: "CMPL/base=AX/offset=-0x4d2/c=0", inst: CMPL, baseReg: RegAX, offset: -0x4d2, c: 0, exp: []byte{0x83, 0xb8, 0x2e, 0xfb, 0xff, 0xff, 0x0}}, - {name: "CMPL/base=AX/offset=-0x4d2/c=1", inst: CMPL, baseReg: RegAX, offset: -0x4d2, c: 1, exp: []byte{0x83, 0xb8, 0x2e, 0xfb, 0xff, 0xff, 0x1}}, - {name: "CMPL/base=AX/offset=-0x4d2/c=-1", inst: CMPL, baseReg: RegAX, offset: -0x4d2, c: -1, exp: []byte{0x83, 0xb8, 0x2e, 0xfb, 0xff, 0xff, 0xff}}, - {name: "CMPL/base=AX/offset=-0x4d2/c=100", inst: CMPL, baseReg: RegAX, offset: -0x4d2, c: 100, exp: []byte{0x83, 0xb8, 0x2e, 0xfb, 0xff, 0xff, 0x64}}, - {name: "CMPL/base=AX/offset=-0x4d2/c=-100", inst: CMPL, baseReg: RegAX, offset: -0x4d2, c: -100, exp: []byte{0x83, 0xb8, 0x2e, 0xfb, 0xff, 0xff, 0x9c}}, - {name: "CMPL/base=AX/offset=-0x4d2/c=127", inst: CMPL, baseReg: RegAX, offset: -0x4d2, c: 127, exp: []byte{0x83, 0xb8, 0x2e, 0xfb, 0xff, 0xff, 0x7f}}, - {name: "CMPL/base=AX/offset=-0x4d2/c=-128", inst: CMPL, baseReg: RegAX, offset: -0x4d2, c: -128, exp: []byte{0x83, 0xb8, 0x2e, 0xfb, 0xff, 0xff, 0x80}}, - {name: "CMPL/base=AX/offset=-0x4d2/c=32767", inst: CMPL, baseReg: RegAX, offset: -0x4d2, c: 32767, exp: []byte{0x81, 0xb8, 0x2e, 0xfb, 0xff, 0xff, 0xff, 0x7f, 0x0, 0x0}}, - {name: "CMPL/base=AX/offset=-0x4d2/c=-32768", inst: CMPL, baseReg: RegAX, offset: -0x4d2, c: -32768, exp: []byte{0x81, 0xb8, 0x2e, 0xfb, 0xff, 0xff, 0x0, 0x80, 0xff, 0xff}}, - {name: "CMPL/base=AX/offset=-0x4d2/c=1048576", inst: CMPL, baseReg: RegAX, offset: -0x4d2, c: 1048576, exp: []byte{0x81, 0xb8, 0x2e, 0xfb, 0xff, 0xff, 0x0, 0x0, 0x10, 0x0}}, - {name: "CMPL/base=AX/offset=-0x4d2/c=-1048576", inst: CMPL, baseReg: RegAX, offset: -0x4d2, c: -1048576, exp: []byte{0x81, 0xb8, 0x2e, 0xfb, 0xff, 0xff, 0x0, 0x0, 0xf0, 0xff}}, - {name: "CMPL/base=AX/offset=-0x4d2/c=2147483647", inst: CMPL, baseReg: RegAX, offset: -0x4d2, c: 2147483647, exp: []byte{0x81, 0xb8, 0x2e, 0xfb, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPL/base=AX/offset=-0x4d2/c=-2147483648", inst: CMPL, baseReg: RegAX, offset: -0x4d2, c: -2147483648, exp: []byte{0x81, 0xb8, 0x2e, 0xfb, 0xff, 0xff, 0x0, 0x0, 0x0, 0x80}}, - {name: "CMPL/base=AX/offset=0x7fffffff/c=0", inst: CMPL, baseReg: RegAX, offset: 0x7fffffff, c: 0, exp: []byte{0x83, 0xb8, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "CMPL/base=AX/offset=0x7fffffff/c=1", inst: CMPL, baseReg: RegAX, offset: 0x7fffffff, c: 1, exp: []byte{0x83, 0xb8, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "CMPL/base=AX/offset=0x7fffffff/c=-1", inst: CMPL, baseReg: RegAX, offset: 0x7fffffff, c: -1, exp: []byte{0x83, 0xb8, 0xff, 0xff, 0xff, 0x7f, 0xff}}, - {name: "CMPL/base=AX/offset=0x7fffffff/c=100", inst: CMPL, baseReg: RegAX, offset: 0x7fffffff, c: 100, exp: []byte{0x83, 0xb8, 0xff, 0xff, 0xff, 0x7f, 0x64}}, - {name: "CMPL/base=AX/offset=0x7fffffff/c=-100", inst: CMPL, baseReg: RegAX, offset: 0x7fffffff, c: -100, exp: []byte{0x83, 0xb8, 0xff, 0xff, 0xff, 0x7f, 0x9c}}, - {name: "CMPL/base=AX/offset=0x7fffffff/c=127", inst: CMPL, baseReg: RegAX, offset: 0x7fffffff, c: 127, exp: []byte{0x83, 0xb8, 0xff, 0xff, 0xff, 0x7f, 0x7f}}, - {name: "CMPL/base=AX/offset=0x7fffffff/c=-128", inst: CMPL, baseReg: RegAX, offset: 0x7fffffff, c: -128, exp: []byte{0x83, 0xb8, 0xff, 0xff, 0xff, 0x7f, 0x80}}, - {name: "CMPL/base=AX/offset=0x7fffffff/c=32767", inst: CMPL, baseReg: RegAX, offset: 0x7fffffff, c: 32767, exp: []byte{0x81, 0xb8, 0xff, 0xff, 0xff, 0x7f, 0xff, 0x7f, 0x0, 0x0}}, - {name: "CMPL/base=AX/offset=0x7fffffff/c=-32768", inst: CMPL, baseReg: RegAX, offset: 0x7fffffff, c: -32768, exp: []byte{0x81, 0xb8, 0xff, 0xff, 0xff, 0x7f, 0x0, 0x80, 0xff, 0xff}}, - {name: "CMPL/base=AX/offset=0x7fffffff/c=1048576", inst: CMPL, baseReg: RegAX, offset: 0x7fffffff, c: 1048576, exp: []byte{0x81, 0xb8, 0xff, 0xff, 0xff, 0x7f, 0x0, 0x0, 0x10, 0x0}}, - {name: "CMPL/base=AX/offset=0x7fffffff/c=-1048576", inst: CMPL, baseReg: RegAX, offset: 0x7fffffff, c: -1048576, exp: []byte{0x81, 0xb8, 0xff, 0xff, 0xff, 0x7f, 0x0, 0x0, 0xf0, 0xff}}, - {name: "CMPL/base=AX/offset=0x7fffffff/c=2147483647", inst: CMPL, baseReg: RegAX, offset: 0x7fffffff, c: 2147483647, exp: []byte{0x81, 0xb8, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPL/base=AX/offset=0x7fffffff/c=-2147483648", inst: CMPL, baseReg: RegAX, offset: 0x7fffffff, c: -2147483648, exp: []byte{0x81, 0xb8, 0xff, 0xff, 0xff, 0x7f, 0x0, 0x0, 0x0, 0x80}}, - {name: "CMPL/base=AX/offset=-0x80000000/c=0", inst: CMPL, baseReg: RegAX, offset: -0x80000000, c: 0, exp: []byte{0x83, 0xb8, 0x0, 0x0, 0x0, 0x80, 0x0}}, - {name: "CMPL/base=AX/offset=-0x80000000/c=1", inst: CMPL, baseReg: RegAX, offset: -0x80000000, c: 1, exp: []byte{0x83, 0xb8, 0x0, 0x0, 0x0, 0x80, 0x1}}, - {name: "CMPL/base=AX/offset=-0x80000000/c=-1", inst: CMPL, baseReg: RegAX, offset: -0x80000000, c: -1, exp: []byte{0x83, 0xb8, 0x0, 0x0, 0x0, 0x80, 0xff}}, - {name: "CMPL/base=AX/offset=-0x80000000/c=100", inst: CMPL, baseReg: RegAX, offset: -0x80000000, c: 100, exp: []byte{0x83, 0xb8, 0x0, 0x0, 0x0, 0x80, 0x64}}, - {name: "CMPL/base=AX/offset=-0x80000000/c=-100", inst: CMPL, baseReg: RegAX, offset: -0x80000000, c: -100, exp: []byte{0x83, 0xb8, 0x0, 0x0, 0x0, 0x80, 0x9c}}, - {name: "CMPL/base=AX/offset=-0x80000000/c=127", inst: CMPL, baseReg: RegAX, offset: -0x80000000, c: 127, exp: []byte{0x83, 0xb8, 0x0, 0x0, 0x0, 0x80, 0x7f}}, - {name: "CMPL/base=AX/offset=-0x80000000/c=-128", inst: CMPL, baseReg: RegAX, offset: -0x80000000, c: -128, exp: []byte{0x83, 0xb8, 0x0, 0x0, 0x0, 0x80, 0x80}}, - {name: "CMPL/base=AX/offset=-0x80000000/c=32767", inst: CMPL, baseReg: RegAX, offset: -0x80000000, c: 32767, exp: []byte{0x81, 0xb8, 0x0, 0x0, 0x0, 0x80, 0xff, 0x7f, 0x0, 0x0}}, - {name: "CMPL/base=AX/offset=-0x80000000/c=-32768", inst: CMPL, baseReg: RegAX, offset: -0x80000000, c: -32768, exp: []byte{0x81, 0xb8, 0x0, 0x0, 0x0, 0x80, 0x0, 0x80, 0xff, 0xff}}, - {name: "CMPL/base=AX/offset=-0x80000000/c=1048576", inst: CMPL, baseReg: RegAX, offset: -0x80000000, c: 1048576, exp: []byte{0x81, 0xb8, 0x0, 0x0, 0x0, 0x80, 0x0, 0x0, 0x10, 0x0}}, - {name: "CMPL/base=AX/offset=-0x80000000/c=-1048576", inst: CMPL, baseReg: RegAX, offset: -0x80000000, c: -1048576, exp: []byte{0x81, 0xb8, 0x0, 0x0, 0x0, 0x80, 0x0, 0x0, 0xf0, 0xff}}, - {name: "CMPL/base=AX/offset=-0x80000000/c=2147483647", inst: CMPL, baseReg: RegAX, offset: -0x80000000, c: 2147483647, exp: []byte{0x81, 0xb8, 0x0, 0x0, 0x0, 0x80, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPL/base=AX/offset=-0x80000000/c=-2147483648", inst: CMPL, baseReg: RegAX, offset: -0x80000000, c: -2147483648, exp: []byte{0x81, 0xb8, 0x0, 0x0, 0x0, 0x80, 0x0, 0x0, 0x0, 0x80}}, - {name: "CMPL/base=AX/offset=0x7fff/c=0", inst: CMPL, baseReg: RegAX, offset: 0x7fff, c: 0, exp: []byte{0x83, 0xb8, 0xff, 0x7f, 0x0, 0x0, 0x0}}, - {name: "CMPL/base=AX/offset=0x7fff/c=1", inst: CMPL, baseReg: RegAX, offset: 0x7fff, c: 1, exp: []byte{0x83, 0xb8, 0xff, 0x7f, 0x0, 0x0, 0x1}}, - {name: "CMPL/base=AX/offset=0x7fff/c=-1", inst: CMPL, baseReg: RegAX, offset: 0x7fff, c: -1, exp: []byte{0x83, 0xb8, 0xff, 0x7f, 0x0, 0x0, 0xff}}, - {name: "CMPL/base=AX/offset=0x7fff/c=100", inst: CMPL, baseReg: RegAX, offset: 0x7fff, c: 100, exp: []byte{0x83, 0xb8, 0xff, 0x7f, 0x0, 0x0, 0x64}}, - {name: "CMPL/base=AX/offset=0x7fff/c=-100", inst: CMPL, baseReg: RegAX, offset: 0x7fff, c: -100, exp: []byte{0x83, 0xb8, 0xff, 0x7f, 0x0, 0x0, 0x9c}}, - {name: "CMPL/base=AX/offset=0x7fff/c=127", inst: CMPL, baseReg: RegAX, offset: 0x7fff, c: 127, exp: []byte{0x83, 0xb8, 0xff, 0x7f, 0x0, 0x0, 0x7f}}, - {name: "CMPL/base=AX/offset=0x7fff/c=-128", inst: CMPL, baseReg: RegAX, offset: 0x7fff, c: -128, exp: []byte{0x83, 0xb8, 0xff, 0x7f, 0x0, 0x0, 0x80}}, - {name: "CMPL/base=AX/offset=0x7fff/c=32767", inst: CMPL, baseReg: RegAX, offset: 0x7fff, c: 32767, exp: []byte{0x81, 0xb8, 0xff, 0x7f, 0x0, 0x0, 0xff, 0x7f, 0x0, 0x0}}, - {name: "CMPL/base=AX/offset=0x7fff/c=-32768", inst: CMPL, baseReg: RegAX, offset: 0x7fff, c: -32768, exp: []byte{0x81, 0xb8, 0xff, 0x7f, 0x0, 0x0, 0x0, 0x80, 0xff, 0xff}}, - {name: "CMPL/base=AX/offset=0x7fff/c=1048576", inst: CMPL, baseReg: RegAX, offset: 0x7fff, c: 1048576, exp: []byte{0x81, 0xb8, 0xff, 0x7f, 0x0, 0x0, 0x0, 0x0, 0x10, 0x0}}, - {name: "CMPL/base=AX/offset=0x7fff/c=-1048576", inst: CMPL, baseReg: RegAX, offset: 0x7fff, c: -1048576, exp: []byte{0x81, 0xb8, 0xff, 0x7f, 0x0, 0x0, 0x0, 0x0, 0xf0, 0xff}}, - {name: "CMPL/base=AX/offset=0x7fff/c=2147483647", inst: CMPL, baseReg: RegAX, offset: 0x7fff, c: 2147483647, exp: []byte{0x81, 0xb8, 0xff, 0x7f, 0x0, 0x0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPL/base=AX/offset=0x7fff/c=-2147483648", inst: CMPL, baseReg: RegAX, offset: 0x7fff, c: -2147483648, exp: []byte{0x81, 0xb8, 0xff, 0x7f, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80}}, - {name: "CMPL/base=AX/offset=-0x8000/c=0", inst: CMPL, baseReg: RegAX, offset: -0x8000, c: 0, exp: []byte{0x83, 0xb8, 0x0, 0x80, 0xff, 0xff, 0x0}}, - {name: "CMPL/base=AX/offset=-0x8000/c=1", inst: CMPL, baseReg: RegAX, offset: -0x8000, c: 1, exp: []byte{0x83, 0xb8, 0x0, 0x80, 0xff, 0xff, 0x1}}, - {name: "CMPL/base=AX/offset=-0x8000/c=-1", inst: CMPL, baseReg: RegAX, offset: -0x8000, c: -1, exp: []byte{0x83, 0xb8, 0x0, 0x80, 0xff, 0xff, 0xff}}, - {name: "CMPL/base=AX/offset=-0x8000/c=100", inst: CMPL, baseReg: RegAX, offset: -0x8000, c: 100, exp: []byte{0x83, 0xb8, 0x0, 0x80, 0xff, 0xff, 0x64}}, - {name: "CMPL/base=AX/offset=-0x8000/c=-100", inst: CMPL, baseReg: RegAX, offset: -0x8000, c: -100, exp: []byte{0x83, 0xb8, 0x0, 0x80, 0xff, 0xff, 0x9c}}, - {name: "CMPL/base=AX/offset=-0x8000/c=127", inst: CMPL, baseReg: RegAX, offset: -0x8000, c: 127, exp: []byte{0x83, 0xb8, 0x0, 0x80, 0xff, 0xff, 0x7f}}, - {name: "CMPL/base=AX/offset=-0x8000/c=-128", inst: CMPL, baseReg: RegAX, offset: -0x8000, c: -128, exp: []byte{0x83, 0xb8, 0x0, 0x80, 0xff, 0xff, 0x80}}, - {name: "CMPL/base=AX/offset=-0x8000/c=32767", inst: CMPL, baseReg: RegAX, offset: -0x8000, c: 32767, exp: []byte{0x81, 0xb8, 0x0, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x0, 0x0}}, - {name: "CMPL/base=AX/offset=-0x8000/c=-32768", inst: CMPL, baseReg: RegAX, offset: -0x8000, c: -32768, exp: []byte{0x81, 0xb8, 0x0, 0x80, 0xff, 0xff, 0x0, 0x80, 0xff, 0xff}}, - {name: "CMPL/base=AX/offset=-0x8000/c=1048576", inst: CMPL, baseReg: RegAX, offset: -0x8000, c: 1048576, exp: []byte{0x81, 0xb8, 0x0, 0x80, 0xff, 0xff, 0x0, 0x0, 0x10, 0x0}}, - {name: "CMPL/base=AX/offset=-0x8000/c=-1048576", inst: CMPL, baseReg: RegAX, offset: -0x8000, c: -1048576, exp: []byte{0x81, 0xb8, 0x0, 0x80, 0xff, 0xff, 0x0, 0x0, 0xf0, 0xff}}, - {name: "CMPL/base=AX/offset=-0x8000/c=2147483647", inst: CMPL, baseReg: RegAX, offset: -0x8000, c: 2147483647, exp: []byte{0x81, 0xb8, 0x0, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPL/base=AX/offset=-0x8000/c=-2147483648", inst: CMPL, baseReg: RegAX, offset: -0x8000, c: -2147483648, exp: []byte{0x81, 0xb8, 0x0, 0x80, 0xff, 0xff, 0x0, 0x0, 0x0, 0x80}}, - {name: "CMPL/base=R8/offset=0x0/c=0", inst: CMPL, baseReg: RegR8, offset: 0x0, c: 0, exp: []byte{0x41, 0x83, 0x38, 0x0}}, - {name: "CMPL/base=R8/offset=0x0/c=1", inst: CMPL, baseReg: RegR8, offset: 0x0, c: 1, exp: []byte{0x41, 0x83, 0x38, 0x1}}, - {name: "CMPL/base=R8/offset=0x0/c=-1", inst: CMPL, baseReg: RegR8, offset: 0x0, c: -1, exp: []byte{0x41, 0x83, 0x38, 0xff}}, - {name: "CMPL/base=R8/offset=0x0/c=100", inst: CMPL, baseReg: RegR8, offset: 0x0, c: 100, exp: []byte{0x41, 0x83, 0x38, 0x64}}, - {name: "CMPL/base=R8/offset=0x0/c=-100", inst: CMPL, baseReg: RegR8, offset: 0x0, c: -100, exp: []byte{0x41, 0x83, 0x38, 0x9c}}, - {name: "CMPL/base=R8/offset=0x0/c=127", inst: CMPL, baseReg: RegR8, offset: 0x0, c: 127, exp: []byte{0x41, 0x83, 0x38, 0x7f}}, - {name: "CMPL/base=R8/offset=0x0/c=-128", inst: CMPL, baseReg: RegR8, offset: 0x0, c: -128, exp: []byte{0x41, 0x83, 0x38, 0x80}}, - {name: "CMPL/base=R8/offset=0x0/c=32767", inst: CMPL, baseReg: RegR8, offset: 0x0, c: 32767, exp: []byte{0x41, 0x81, 0x38, 0xff, 0x7f, 0x0, 0x0}}, - {name: "CMPL/base=R8/offset=0x0/c=-32768", inst: CMPL, baseReg: RegR8, offset: 0x0, c: -32768, exp: []byte{0x41, 0x81, 0x38, 0x0, 0x80, 0xff, 0xff}}, - {name: "CMPL/base=R8/offset=0x0/c=1048576", inst: CMPL, baseReg: RegR8, offset: 0x0, c: 1048576, exp: []byte{0x41, 0x81, 0x38, 0x0, 0x0, 0x10, 0x0}}, - {name: "CMPL/base=R8/offset=0x0/c=-1048576", inst: CMPL, baseReg: RegR8, offset: 0x0, c: -1048576, exp: []byte{0x41, 0x81, 0x38, 0x0, 0x0, 0xf0, 0xff}}, - {name: "CMPL/base=R8/offset=0x0/c=2147483647", inst: CMPL, baseReg: RegR8, offset: 0x0, c: 2147483647, exp: []byte{0x41, 0x81, 0x38, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPL/base=R8/offset=0x0/c=-2147483648", inst: CMPL, baseReg: RegR8, offset: 0x0, c: -2147483648, exp: []byte{0x41, 0x81, 0x38, 0x0, 0x0, 0x0, 0x80}}, - {name: "CMPL/base=R8/offset=0x1/c=0", inst: CMPL, baseReg: RegR8, offset: 0x1, c: 0, exp: []byte{0x41, 0x83, 0x78, 0x1, 0x0}}, - {name: "CMPL/base=R8/offset=0x1/c=1", inst: CMPL, baseReg: RegR8, offset: 0x1, c: 1, exp: []byte{0x41, 0x83, 0x78, 0x1, 0x1}}, - {name: "CMPL/base=R8/offset=0x1/c=-1", inst: CMPL, baseReg: RegR8, offset: 0x1, c: -1, exp: []byte{0x41, 0x83, 0x78, 0x1, 0xff}}, - {name: "CMPL/base=R8/offset=0x1/c=100", inst: CMPL, baseReg: RegR8, offset: 0x1, c: 100, exp: []byte{0x41, 0x83, 0x78, 0x1, 0x64}}, - {name: "CMPL/base=R8/offset=0x1/c=-100", inst: CMPL, baseReg: RegR8, offset: 0x1, c: -100, exp: []byte{0x41, 0x83, 0x78, 0x1, 0x9c}}, - {name: "CMPL/base=R8/offset=0x1/c=127", inst: CMPL, baseReg: RegR8, offset: 0x1, c: 127, exp: []byte{0x41, 0x83, 0x78, 0x1, 0x7f}}, - {name: "CMPL/base=R8/offset=0x1/c=-128", inst: CMPL, baseReg: RegR8, offset: 0x1, c: -128, exp: []byte{0x41, 0x83, 0x78, 0x1, 0x80}}, - {name: "CMPL/base=R8/offset=0x1/c=32767", inst: CMPL, baseReg: RegR8, offset: 0x1, c: 32767, exp: []byte{0x41, 0x81, 0x78, 0x1, 0xff, 0x7f, 0x0, 0x0}}, - {name: "CMPL/base=R8/offset=0x1/c=-32768", inst: CMPL, baseReg: RegR8, offset: 0x1, c: -32768, exp: []byte{0x41, 0x81, 0x78, 0x1, 0x0, 0x80, 0xff, 0xff}}, - {name: "CMPL/base=R8/offset=0x1/c=1048576", inst: CMPL, baseReg: RegR8, offset: 0x1, c: 1048576, exp: []byte{0x41, 0x81, 0x78, 0x1, 0x0, 0x0, 0x10, 0x0}}, - {name: "CMPL/base=R8/offset=0x1/c=-1048576", inst: CMPL, baseReg: RegR8, offset: 0x1, c: -1048576, exp: []byte{0x41, 0x81, 0x78, 0x1, 0x0, 0x0, 0xf0, 0xff}}, - {name: "CMPL/base=R8/offset=0x1/c=2147483647", inst: CMPL, baseReg: RegR8, offset: 0x1, c: 2147483647, exp: []byte{0x41, 0x81, 0x78, 0x1, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPL/base=R8/offset=0x1/c=-2147483648", inst: CMPL, baseReg: RegR8, offset: 0x1, c: -2147483648, exp: []byte{0x41, 0x81, 0x78, 0x1, 0x0, 0x0, 0x0, 0x80}}, - {name: "CMPL/base=R8/offset=-0x1/c=0", inst: CMPL, baseReg: RegR8, offset: -0x1, c: 0, exp: []byte{0x41, 0x83, 0x78, 0xff, 0x0}}, - {name: "CMPL/base=R8/offset=-0x1/c=1", inst: CMPL, baseReg: RegR8, offset: -0x1, c: 1, exp: []byte{0x41, 0x83, 0x78, 0xff, 0x1}}, - {name: "CMPL/base=R8/offset=-0x1/c=-1", inst: CMPL, baseReg: RegR8, offset: -0x1, c: -1, exp: []byte{0x41, 0x83, 0x78, 0xff, 0xff}}, - {name: "CMPL/base=R8/offset=-0x1/c=100", inst: CMPL, baseReg: RegR8, offset: -0x1, c: 100, exp: []byte{0x41, 0x83, 0x78, 0xff, 0x64}}, - {name: "CMPL/base=R8/offset=-0x1/c=-100", inst: CMPL, baseReg: RegR8, offset: -0x1, c: -100, exp: []byte{0x41, 0x83, 0x78, 0xff, 0x9c}}, - {name: "CMPL/base=R8/offset=-0x1/c=127", inst: CMPL, baseReg: RegR8, offset: -0x1, c: 127, exp: []byte{0x41, 0x83, 0x78, 0xff, 0x7f}}, - {name: "CMPL/base=R8/offset=-0x1/c=-128", inst: CMPL, baseReg: RegR8, offset: -0x1, c: -128, exp: []byte{0x41, 0x83, 0x78, 0xff, 0x80}}, - {name: "CMPL/base=R8/offset=-0x1/c=32767", inst: CMPL, baseReg: RegR8, offset: -0x1, c: 32767, exp: []byte{0x41, 0x81, 0x78, 0xff, 0xff, 0x7f, 0x0, 0x0}}, - {name: "CMPL/base=R8/offset=-0x1/c=-32768", inst: CMPL, baseReg: RegR8, offset: -0x1, c: -32768, exp: []byte{0x41, 0x81, 0x78, 0xff, 0x0, 0x80, 0xff, 0xff}}, - {name: "CMPL/base=R8/offset=-0x1/c=1048576", inst: CMPL, baseReg: RegR8, offset: -0x1, c: 1048576, exp: []byte{0x41, 0x81, 0x78, 0xff, 0x0, 0x0, 0x10, 0x0}}, - {name: "CMPL/base=R8/offset=-0x1/c=-1048576", inst: CMPL, baseReg: RegR8, offset: -0x1, c: -1048576, exp: []byte{0x41, 0x81, 0x78, 0xff, 0x0, 0x0, 0xf0, 0xff}}, - {name: "CMPL/base=R8/offset=-0x1/c=2147483647", inst: CMPL, baseReg: RegR8, offset: -0x1, c: 2147483647, exp: []byte{0x41, 0x81, 0x78, 0xff, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPL/base=R8/offset=-0x1/c=-2147483648", inst: CMPL, baseReg: RegR8, offset: -0x1, c: -2147483648, exp: []byte{0x41, 0x81, 0x78, 0xff, 0x0, 0x0, 0x0, 0x80}}, - {name: "CMPL/base=R8/offset=0x4db/c=0", inst: CMPL, baseReg: RegR8, offset: 0x4db, c: 0, exp: []byte{0x41, 0x83, 0xb8, 0xdb, 0x4, 0x0, 0x0, 0x0}}, - {name: "CMPL/base=R8/offset=0x4db/c=1", inst: CMPL, baseReg: RegR8, offset: 0x4db, c: 1, exp: []byte{0x41, 0x83, 0xb8, 0xdb, 0x4, 0x0, 0x0, 0x1}}, - {name: "CMPL/base=R8/offset=0x4db/c=-1", inst: CMPL, baseReg: RegR8, offset: 0x4db, c: -1, exp: []byte{0x41, 0x83, 0xb8, 0xdb, 0x4, 0x0, 0x0, 0xff}}, - {name: "CMPL/base=R8/offset=0x4db/c=100", inst: CMPL, baseReg: RegR8, offset: 0x4db, c: 100, exp: []byte{0x41, 0x83, 0xb8, 0xdb, 0x4, 0x0, 0x0, 0x64}}, - {name: "CMPL/base=R8/offset=0x4db/c=-100", inst: CMPL, baseReg: RegR8, offset: 0x4db, c: -100, exp: []byte{0x41, 0x83, 0xb8, 0xdb, 0x4, 0x0, 0x0, 0x9c}}, - {name: "CMPL/base=R8/offset=0x4db/c=127", inst: CMPL, baseReg: RegR8, offset: 0x4db, c: 127, exp: []byte{0x41, 0x83, 0xb8, 0xdb, 0x4, 0x0, 0x0, 0x7f}}, - {name: "CMPL/base=R8/offset=0x4db/c=-128", inst: CMPL, baseReg: RegR8, offset: 0x4db, c: -128, exp: []byte{0x41, 0x83, 0xb8, 0xdb, 0x4, 0x0, 0x0, 0x80}}, - {name: "CMPL/base=R8/offset=0x4db/c=32767", inst: CMPL, baseReg: RegR8, offset: 0x4db, c: 32767, exp: []byte{0x41, 0x81, 0xb8, 0xdb, 0x4, 0x0, 0x0, 0xff, 0x7f, 0x0, 0x0}}, - {name: "CMPL/base=R8/offset=0x4db/c=-32768", inst: CMPL, baseReg: RegR8, offset: 0x4db, c: -32768, exp: []byte{0x41, 0x81, 0xb8, 0xdb, 0x4, 0x0, 0x0, 0x0, 0x80, 0xff, 0xff}}, - {name: "CMPL/base=R8/offset=0x4db/c=1048576", inst: CMPL, baseReg: RegR8, offset: 0x4db, c: 1048576, exp: []byte{0x41, 0x81, 0xb8, 0xdb, 0x4, 0x0, 0x0, 0x0, 0x0, 0x10, 0x0}}, - {name: "CMPL/base=R8/offset=0x4db/c=-1048576", inst: CMPL, baseReg: RegR8, offset: 0x4db, c: -1048576, exp: []byte{0x41, 0x81, 0xb8, 0xdb, 0x4, 0x0, 0x0, 0x0, 0x0, 0xf0, 0xff}}, - {name: "CMPL/base=R8/offset=0x4db/c=2147483647", inst: CMPL, baseReg: RegR8, offset: 0x4db, c: 2147483647, exp: []byte{0x41, 0x81, 0xb8, 0xdb, 0x4, 0x0, 0x0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPL/base=R8/offset=0x4db/c=-2147483648", inst: CMPL, baseReg: RegR8, offset: 0x4db, c: -2147483648, exp: []byte{0x41, 0x81, 0xb8, 0xdb, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80}}, - {name: "CMPL/base=R8/offset=-0x4d2/c=0", inst: CMPL, baseReg: RegR8, offset: -0x4d2, c: 0, exp: []byte{0x41, 0x83, 0xb8, 0x2e, 0xfb, 0xff, 0xff, 0x0}}, - {name: "CMPL/base=R8/offset=-0x4d2/c=1", inst: CMPL, baseReg: RegR8, offset: -0x4d2, c: 1, exp: []byte{0x41, 0x83, 0xb8, 0x2e, 0xfb, 0xff, 0xff, 0x1}}, - {name: "CMPL/base=R8/offset=-0x4d2/c=-1", inst: CMPL, baseReg: RegR8, offset: -0x4d2, c: -1, exp: []byte{0x41, 0x83, 0xb8, 0x2e, 0xfb, 0xff, 0xff, 0xff}}, - {name: "CMPL/base=R8/offset=-0x4d2/c=100", inst: CMPL, baseReg: RegR8, offset: -0x4d2, c: 100, exp: []byte{0x41, 0x83, 0xb8, 0x2e, 0xfb, 0xff, 0xff, 0x64}}, - {name: "CMPL/base=R8/offset=-0x4d2/c=-100", inst: CMPL, baseReg: RegR8, offset: -0x4d2, c: -100, exp: []byte{0x41, 0x83, 0xb8, 0x2e, 0xfb, 0xff, 0xff, 0x9c}}, - {name: "CMPL/base=R8/offset=-0x4d2/c=127", inst: CMPL, baseReg: RegR8, offset: -0x4d2, c: 127, exp: []byte{0x41, 0x83, 0xb8, 0x2e, 0xfb, 0xff, 0xff, 0x7f}}, - {name: "CMPL/base=R8/offset=-0x4d2/c=-128", inst: CMPL, baseReg: RegR8, offset: -0x4d2, c: -128, exp: []byte{0x41, 0x83, 0xb8, 0x2e, 0xfb, 0xff, 0xff, 0x80}}, - {name: "CMPL/base=R8/offset=-0x4d2/c=32767", inst: CMPL, baseReg: RegR8, offset: -0x4d2, c: 32767, exp: []byte{0x41, 0x81, 0xb8, 0x2e, 0xfb, 0xff, 0xff, 0xff, 0x7f, 0x0, 0x0}}, - {name: "CMPL/base=R8/offset=-0x4d2/c=-32768", inst: CMPL, baseReg: RegR8, offset: -0x4d2, c: -32768, exp: []byte{0x41, 0x81, 0xb8, 0x2e, 0xfb, 0xff, 0xff, 0x0, 0x80, 0xff, 0xff}}, - {name: "CMPL/base=R8/offset=-0x4d2/c=1048576", inst: CMPL, baseReg: RegR8, offset: -0x4d2, c: 1048576, exp: []byte{0x41, 0x81, 0xb8, 0x2e, 0xfb, 0xff, 0xff, 0x0, 0x0, 0x10, 0x0}}, - {name: "CMPL/base=R8/offset=-0x4d2/c=-1048576", inst: CMPL, baseReg: RegR8, offset: -0x4d2, c: -1048576, exp: []byte{0x41, 0x81, 0xb8, 0x2e, 0xfb, 0xff, 0xff, 0x0, 0x0, 0xf0, 0xff}}, - {name: "CMPL/base=R8/offset=-0x4d2/c=2147483647", inst: CMPL, baseReg: RegR8, offset: -0x4d2, c: 2147483647, exp: []byte{0x41, 0x81, 0xb8, 0x2e, 0xfb, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPL/base=R8/offset=-0x4d2/c=-2147483648", inst: CMPL, baseReg: RegR8, offset: -0x4d2, c: -2147483648, exp: []byte{0x41, 0x81, 0xb8, 0x2e, 0xfb, 0xff, 0xff, 0x0, 0x0, 0x0, 0x80}}, - {name: "CMPL/base=R8/offset=0x7fffffff/c=0", inst: CMPL, baseReg: RegR8, offset: 0x7fffffff, c: 0, exp: []byte{0x41, 0x83, 0xb8, 0xff, 0xff, 0xff, 0x7f, 0x0}}, - {name: "CMPL/base=R8/offset=0x7fffffff/c=1", inst: CMPL, baseReg: RegR8, offset: 0x7fffffff, c: 1, exp: []byte{0x41, 0x83, 0xb8, 0xff, 0xff, 0xff, 0x7f, 0x1}}, - {name: "CMPL/base=R8/offset=0x7fffffff/c=-1", inst: CMPL, baseReg: RegR8, offset: 0x7fffffff, c: -1, exp: []byte{0x41, 0x83, 0xb8, 0xff, 0xff, 0xff, 0x7f, 0xff}}, - {name: "CMPL/base=R8/offset=0x7fffffff/c=100", inst: CMPL, baseReg: RegR8, offset: 0x7fffffff, c: 100, exp: []byte{0x41, 0x83, 0xb8, 0xff, 0xff, 0xff, 0x7f, 0x64}}, - {name: "CMPL/base=R8/offset=0x7fffffff/c=-100", inst: CMPL, baseReg: RegR8, offset: 0x7fffffff, c: -100, exp: []byte{0x41, 0x83, 0xb8, 0xff, 0xff, 0xff, 0x7f, 0x9c}}, - {name: "CMPL/base=R8/offset=0x7fffffff/c=127", inst: CMPL, baseReg: RegR8, offset: 0x7fffffff, c: 127, exp: []byte{0x41, 0x83, 0xb8, 0xff, 0xff, 0xff, 0x7f, 0x7f}}, - {name: "CMPL/base=R8/offset=0x7fffffff/c=-128", inst: CMPL, baseReg: RegR8, offset: 0x7fffffff, c: -128, exp: []byte{0x41, 0x83, 0xb8, 0xff, 0xff, 0xff, 0x7f, 0x80}}, - {name: "CMPL/base=R8/offset=0x7fffffff/c=32767", inst: CMPL, baseReg: RegR8, offset: 0x7fffffff, c: 32767, exp: []byte{0x41, 0x81, 0xb8, 0xff, 0xff, 0xff, 0x7f, 0xff, 0x7f, 0x0, 0x0}}, - {name: "CMPL/base=R8/offset=0x7fffffff/c=-32768", inst: CMPL, baseReg: RegR8, offset: 0x7fffffff, c: -32768, exp: []byte{0x41, 0x81, 0xb8, 0xff, 0xff, 0xff, 0x7f, 0x0, 0x80, 0xff, 0xff}}, - {name: "CMPL/base=R8/offset=0x7fffffff/c=1048576", inst: CMPL, baseReg: RegR8, offset: 0x7fffffff, c: 1048576, exp: []byte{0x41, 0x81, 0xb8, 0xff, 0xff, 0xff, 0x7f, 0x0, 0x0, 0x10, 0x0}}, - {name: "CMPL/base=R8/offset=0x7fffffff/c=-1048576", inst: CMPL, baseReg: RegR8, offset: 0x7fffffff, c: -1048576, exp: []byte{0x41, 0x81, 0xb8, 0xff, 0xff, 0xff, 0x7f, 0x0, 0x0, 0xf0, 0xff}}, - {name: "CMPL/base=R8/offset=0x7fffffff/c=2147483647", inst: CMPL, baseReg: RegR8, offset: 0x7fffffff, c: 2147483647, exp: []byte{0x41, 0x81, 0xb8, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPL/base=R8/offset=0x7fffffff/c=-2147483648", inst: CMPL, baseReg: RegR8, offset: 0x7fffffff, c: -2147483648, exp: []byte{0x41, 0x81, 0xb8, 0xff, 0xff, 0xff, 0x7f, 0x0, 0x0, 0x0, 0x80}}, - {name: "CMPL/base=R8/offset=-0x80000000/c=0", inst: CMPL, baseReg: RegR8, offset: -0x80000000, c: 0, exp: []byte{0x41, 0x83, 0xb8, 0x0, 0x0, 0x0, 0x80, 0x0}}, - {name: "CMPL/base=R8/offset=-0x80000000/c=1", inst: CMPL, baseReg: RegR8, offset: -0x80000000, c: 1, exp: []byte{0x41, 0x83, 0xb8, 0x0, 0x0, 0x0, 0x80, 0x1}}, - {name: "CMPL/base=R8/offset=-0x80000000/c=-1", inst: CMPL, baseReg: RegR8, offset: -0x80000000, c: -1, exp: []byte{0x41, 0x83, 0xb8, 0x0, 0x0, 0x0, 0x80, 0xff}}, - {name: "CMPL/base=R8/offset=-0x80000000/c=100", inst: CMPL, baseReg: RegR8, offset: -0x80000000, c: 100, exp: []byte{0x41, 0x83, 0xb8, 0x0, 0x0, 0x0, 0x80, 0x64}}, - {name: "CMPL/base=R8/offset=-0x80000000/c=-100", inst: CMPL, baseReg: RegR8, offset: -0x80000000, c: -100, exp: []byte{0x41, 0x83, 0xb8, 0x0, 0x0, 0x0, 0x80, 0x9c}}, - {name: "CMPL/base=R8/offset=-0x80000000/c=127", inst: CMPL, baseReg: RegR8, offset: -0x80000000, c: 127, exp: []byte{0x41, 0x83, 0xb8, 0x0, 0x0, 0x0, 0x80, 0x7f}}, - {name: "CMPL/base=R8/offset=-0x80000000/c=-128", inst: CMPL, baseReg: RegR8, offset: -0x80000000, c: -128, exp: []byte{0x41, 0x83, 0xb8, 0x0, 0x0, 0x0, 0x80, 0x80}}, - {name: "CMPL/base=R8/offset=-0x80000000/c=32767", inst: CMPL, baseReg: RegR8, offset: -0x80000000, c: 32767, exp: []byte{0x41, 0x81, 0xb8, 0x0, 0x0, 0x0, 0x80, 0xff, 0x7f, 0x0, 0x0}}, - {name: "CMPL/base=R8/offset=-0x80000000/c=-32768", inst: CMPL, baseReg: RegR8, offset: -0x80000000, c: -32768, exp: []byte{0x41, 0x81, 0xb8, 0x0, 0x0, 0x0, 0x80, 0x0, 0x80, 0xff, 0xff}}, - {name: "CMPL/base=R8/offset=-0x80000000/c=1048576", inst: CMPL, baseReg: RegR8, offset: -0x80000000, c: 1048576, exp: []byte{0x41, 0x81, 0xb8, 0x0, 0x0, 0x0, 0x80, 0x0, 0x0, 0x10, 0x0}}, - {name: "CMPL/base=R8/offset=-0x80000000/c=-1048576", inst: CMPL, baseReg: RegR8, offset: -0x80000000, c: -1048576, exp: []byte{0x41, 0x81, 0xb8, 0x0, 0x0, 0x0, 0x80, 0x0, 0x0, 0xf0, 0xff}}, - {name: "CMPL/base=R8/offset=-0x80000000/c=2147483647", inst: CMPL, baseReg: RegR8, offset: -0x80000000, c: 2147483647, exp: []byte{0x41, 0x81, 0xb8, 0x0, 0x0, 0x0, 0x80, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPL/base=R8/offset=-0x80000000/c=-2147483648", inst: CMPL, baseReg: RegR8, offset: -0x80000000, c: -2147483648, exp: []byte{0x41, 0x81, 0xb8, 0x0, 0x0, 0x0, 0x80, 0x0, 0x0, 0x0, 0x80}}, - {name: "CMPL/base=R8/offset=0x7fff/c=0", inst: CMPL, baseReg: RegR8, offset: 0x7fff, c: 0, exp: []byte{0x41, 0x83, 0xb8, 0xff, 0x7f, 0x0, 0x0, 0x0}}, - {name: "CMPL/base=R8/offset=0x7fff/c=1", inst: CMPL, baseReg: RegR8, offset: 0x7fff, c: 1, exp: []byte{0x41, 0x83, 0xb8, 0xff, 0x7f, 0x0, 0x0, 0x1}}, - {name: "CMPL/base=R8/offset=0x7fff/c=-1", inst: CMPL, baseReg: RegR8, offset: 0x7fff, c: -1, exp: []byte{0x41, 0x83, 0xb8, 0xff, 0x7f, 0x0, 0x0, 0xff}}, - {name: "CMPL/base=R8/offset=0x7fff/c=100", inst: CMPL, baseReg: RegR8, offset: 0x7fff, c: 100, exp: []byte{0x41, 0x83, 0xb8, 0xff, 0x7f, 0x0, 0x0, 0x64}}, - {name: "CMPL/base=R8/offset=0x7fff/c=-100", inst: CMPL, baseReg: RegR8, offset: 0x7fff, c: -100, exp: []byte{0x41, 0x83, 0xb8, 0xff, 0x7f, 0x0, 0x0, 0x9c}}, - {name: "CMPL/base=R8/offset=0x7fff/c=127", inst: CMPL, baseReg: RegR8, offset: 0x7fff, c: 127, exp: []byte{0x41, 0x83, 0xb8, 0xff, 0x7f, 0x0, 0x0, 0x7f}}, - {name: "CMPL/base=R8/offset=0x7fff/c=-128", inst: CMPL, baseReg: RegR8, offset: 0x7fff, c: -128, exp: []byte{0x41, 0x83, 0xb8, 0xff, 0x7f, 0x0, 0x0, 0x80}}, - {name: "CMPL/base=R8/offset=0x7fff/c=32767", inst: CMPL, baseReg: RegR8, offset: 0x7fff, c: 32767, exp: []byte{0x41, 0x81, 0xb8, 0xff, 0x7f, 0x0, 0x0, 0xff, 0x7f, 0x0, 0x0}}, - {name: "CMPL/base=R8/offset=0x7fff/c=-32768", inst: CMPL, baseReg: RegR8, offset: 0x7fff, c: -32768, exp: []byte{0x41, 0x81, 0xb8, 0xff, 0x7f, 0x0, 0x0, 0x0, 0x80, 0xff, 0xff}}, - {name: "CMPL/base=R8/offset=0x7fff/c=1048576", inst: CMPL, baseReg: RegR8, offset: 0x7fff, c: 1048576, exp: []byte{0x41, 0x81, 0xb8, 0xff, 0x7f, 0x0, 0x0, 0x0, 0x0, 0x10, 0x0}}, - {name: "CMPL/base=R8/offset=0x7fff/c=-1048576", inst: CMPL, baseReg: RegR8, offset: 0x7fff, c: -1048576, exp: []byte{0x41, 0x81, 0xb8, 0xff, 0x7f, 0x0, 0x0, 0x0, 0x0, 0xf0, 0xff}}, - {name: "CMPL/base=R8/offset=0x7fff/c=2147483647", inst: CMPL, baseReg: RegR8, offset: 0x7fff, c: 2147483647, exp: []byte{0x41, 0x81, 0xb8, 0xff, 0x7f, 0x0, 0x0, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPL/base=R8/offset=0x7fff/c=-2147483648", inst: CMPL, baseReg: RegR8, offset: 0x7fff, c: -2147483648, exp: []byte{0x41, 0x81, 0xb8, 0xff, 0x7f, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80}}, - {name: "CMPL/base=R8/offset=-0x8000/c=0", inst: CMPL, baseReg: RegR8, offset: -0x8000, c: 0, exp: []byte{0x41, 0x83, 0xb8, 0x0, 0x80, 0xff, 0xff, 0x0}}, - {name: "CMPL/base=R8/offset=-0x8000/c=1", inst: CMPL, baseReg: RegR8, offset: -0x8000, c: 1, exp: []byte{0x41, 0x83, 0xb8, 0x0, 0x80, 0xff, 0xff, 0x1}}, - {name: "CMPL/base=R8/offset=-0x8000/c=-1", inst: CMPL, baseReg: RegR8, offset: -0x8000, c: -1, exp: []byte{0x41, 0x83, 0xb8, 0x0, 0x80, 0xff, 0xff, 0xff}}, - {name: "CMPL/base=R8/offset=-0x8000/c=100", inst: CMPL, baseReg: RegR8, offset: -0x8000, c: 100, exp: []byte{0x41, 0x83, 0xb8, 0x0, 0x80, 0xff, 0xff, 0x64}}, - {name: "CMPL/base=R8/offset=-0x8000/c=-100", inst: CMPL, baseReg: RegR8, offset: -0x8000, c: -100, exp: []byte{0x41, 0x83, 0xb8, 0x0, 0x80, 0xff, 0xff, 0x9c}}, - {name: "CMPL/base=R8/offset=-0x8000/c=127", inst: CMPL, baseReg: RegR8, offset: -0x8000, c: 127, exp: []byte{0x41, 0x83, 0xb8, 0x0, 0x80, 0xff, 0xff, 0x7f}}, - {name: "CMPL/base=R8/offset=-0x8000/c=-128", inst: CMPL, baseReg: RegR8, offset: -0x8000, c: -128, exp: []byte{0x41, 0x83, 0xb8, 0x0, 0x80, 0xff, 0xff, 0x80}}, - {name: "CMPL/base=R8/offset=-0x8000/c=32767", inst: CMPL, baseReg: RegR8, offset: -0x8000, c: 32767, exp: []byte{0x41, 0x81, 0xb8, 0x0, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x0, 0x0}}, - {name: "CMPL/base=R8/offset=-0x8000/c=-32768", inst: CMPL, baseReg: RegR8, offset: -0x8000, c: -32768, exp: []byte{0x41, 0x81, 0xb8, 0x0, 0x80, 0xff, 0xff, 0x0, 0x80, 0xff, 0xff}}, - {name: "CMPL/base=R8/offset=-0x8000/c=1048576", inst: CMPL, baseReg: RegR8, offset: -0x8000, c: 1048576, exp: []byte{0x41, 0x81, 0xb8, 0x0, 0x80, 0xff, 0xff, 0x0, 0x0, 0x10, 0x0}}, - {name: "CMPL/base=R8/offset=-0x8000/c=-1048576", inst: CMPL, baseReg: RegR8, offset: -0x8000, c: -1048576, exp: []byte{0x41, 0x81, 0xb8, 0x0, 0x80, 0xff, 0xff, 0x0, 0x0, 0xf0, 0xff}}, - {name: "CMPL/base=R8/offset=-0x8000/c=2147483647", inst: CMPL, baseReg: RegR8, offset: -0x8000, c: 2147483647, exp: []byte{0x41, 0x81, 0xb8, 0x0, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f}}, - {name: "CMPL/base=R8/offset=-0x8000/c=-2147483648", inst: CMPL, baseReg: RegR8, offset: -0x8000, c: -2147483648, exp: []byte{0x41, 0x81, 0xb8, 0x0, 0x80, 0xff, 0xff, 0x0, 0x0, 0x0, 0x80}}, - } - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - for _, tc := range tests { - a := NewAssembler() - buf := code.NextCodeSection() - err := a.encodeMemoryToConst(buf, &nodeImpl{ - instruction: tc.inst, - types: operandTypesMemoryToConst, srcReg: tc.baseReg, srcConst: tc.offset, dstConst: tc.c, - }) - require.NoError(t, err, tc.name) - require.Equal(t, tc.exp, buf.Bytes(), tc.name) - } -} - -func TestAssemblerImpl_ResolveForwardRelativeJumps(t *testing.T) { - t.Run("long jump", func(t *testing.T) { - t.Run("error", func(t *testing.T) { - originOffset, targetOffset := uint64(0), uint64(math.MaxInt64) - origin := &nodeImpl{instruction: JMP, offsetInBinary: originOffset} - target := &nodeImpl{offsetInBinary: targetOffset, forwardJumpOrigins: origin} - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - a := NewAssembler() - buf := code.NextCodeSection() - err := a.resolveForwardRelativeJumps(buf, target) - require.EqualError(t, err, "too large jump offset 9223372036854775802 for encoding JMP") - }) - t.Run("ok", func(t *testing.T) { - originOffset := uint64(0) - tests := []struct { - instruction asm.Instruction - targetOffset uint64 - expectedOffsetFromEIP int32 - writtenOffsetIndexInBinary int - }{ - { - instruction: JMP, targetOffset: 1234, - writtenOffsetIndexInBinary: 1, // JMP has one opcode byte for long jump. - expectedOffsetFromEIP: 1234 - 5, // the instruction length of long relative jmp. - }, - { - instruction: JCC, targetOffset: 1234, - writtenOffsetIndexInBinary: 2, // Conditional jumps has two opcode for long jump. - expectedOffsetFromEIP: 1234 - 6, // the instruction length of long relative JCC - }, - } - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - for _, tt := range tests { - tc := tt - origin := &nodeImpl{instruction: tc.instruction, offsetInBinary: originOffset} - target := &nodeImpl{offsetInBinary: tc.targetOffset, forwardJumpOrigins: origin} - a := NewAssembler() - - // Grow the capacity of buffer so that we could put the offset. - buf := code.NextCodeSection() - buf.AppendBytes([]byte{0, 0, 0, 0, 0, 0}) // Relative long jumps are at most 6 bytes. - - err := a.resolveForwardRelativeJumps(buf, target) - require.NoError(t, err) - - actual := binary.LittleEndian.Uint32(buf.Bytes()[tc.writtenOffsetIndexInBinary:]) - require.Equal(t, tc.expectedOffsetFromEIP, int32(actual)) - } - }) - }) - t.Run("short jump", func(t *testing.T) { - t.Run("reassemble", func(t *testing.T) { - originOffset := uint64(0) - tests := []struct { - instruction asm.Instruction - targetOffset uint64 - }{ - { - instruction: JMP, - targetOffset: 10000, - }, - { - instruction: JMP, - // Relative jump offset = 130 - len(JMP instruction bytes) = 130 - 2 = 128 > math.MaxInt8. - targetOffset: 130, - }, - { - instruction: JCC, - targetOffset: 10000, - }, - { - instruction: JCC, - // Relative jump offset = 130 - len(JCC instruction bytes) = 130 -2 = 128 > math.MaxInt8. - targetOffset: 130, - }, - } - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - for _, tt := range tests { - tc := tt - origin := &nodeImpl{instruction: tc.instruction, offsetInBinary: originOffset, flag: nodeFlagShortForwardJump} - target := &nodeImpl{offsetInBinary: tc.targetOffset, forwardJumpOrigins: origin} - origin.jumpTarget = target - - a := NewAssembler() - buf := code.NextCodeSection() - err := a.resolveForwardRelativeJumps(buf, target) - require.NoError(t, err) - - require.True(t, a.forceReAssemble) - require.True(t, origin.flag&nodeFlagShortForwardJump == 0) - } - }) - t.Run("ok", func(t *testing.T) { - originOffset := uint64(0) - tests := []struct { - instruction asm.Instruction - targetOffset uint64 - expectedOffsetFromEIP byte - }{ - { - instruction: JMP, targetOffset: 129, - expectedOffsetFromEIP: 129 - 2, // short jumps are of 2 bytes. - }, - { - instruction: JCC, targetOffset: 129, - expectedOffsetFromEIP: 129 - 2, // short jumps are of 2 bytes. - }, - } - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - for _, tt := range tests { - tc := tt - origin := &nodeImpl{instruction: tc.instruction, offsetInBinary: originOffset, flag: nodeFlagShortForwardJump} - target := &nodeImpl{offsetInBinary: tc.targetOffset, forwardJumpOrigins: origin} - origin.jumpTarget = target - - a := NewAssembler() - - // Grow the capacity of buffer so that we could put the offset. - buf := code.NextCodeSection() - buf.AppendBytes([]byte{0, 0}) // Relative short jumps are of 2 bytes. - - err := a.resolveForwardRelativeJumps(buf, target) - require.NoError(t, err) - - actual := buf.Bytes()[1] // For short jumps, the opcode has one opcode so the offset is writte at 2nd byte. - require.Equal(t, tc.expectedOffsetFromEIP, actual) - } - }) - }) -} diff --git a/internal/asm/amd64/impl_6_test.go b/internal/asm/amd64/impl_6_test.go deleted file mode 100644 index 97dd049a03..0000000000 --- a/internal/asm/amd64/impl_6_test.go +++ /dev/null @@ -1,712 +0,0 @@ -package amd64 - -import ( - "fmt" - "math" - "testing" - - "github.com/tetratelabs/wazero/internal/asm" - "github.com/tetratelabs/wazero/internal/testing/require" -) - -func TestAssemblerImpl_Assemble_NOPPadding(t *testing.T) { - t.Run("non relative jumps", func(t *testing.T) { - tests := []struct { - name string - setupFn func(assembler Assembler) - expected []byte - }{ - { - name: "RET", - setupFn: func(assembler Assembler) { - for i := 0; i < 128; i++ { - assembler.CompileStandAlone(RET) - } - }, - expected: []byte{ - 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, - 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0x90, - 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, - 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0x90, 0xc3, 0xc3, - 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, - 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0x90, 0xc3, 0xc3, 0xc3, 0xc3, - 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, - 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0xc3, 0x90, 0xc3, 0xc3, 0xc3, 0xc3, - }, - }, - { - name: "JMP to register", - setupFn: func(assembler Assembler) { - for i := 0; i < 128; i++ { - assembler.CompileJumpToRegister(JMP, RegAX) - } - }, - expected: []byte{ - 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, - 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, - 0x66, 0x90, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, - 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, - 0xff, 0xe0, 0x66, 0x90, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, - 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, - 0xff, 0xe0, 0xff, 0xe0, 0x66, 0x90, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, - 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, - 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0x66, 0x90, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, - 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, - 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0x66, 0x90, 0xff, 0xe0, 0xff, 0xe0, 0xff, - 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, - 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0x66, 0x90, 0xff, 0xe0, 0xff, - 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, - 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0x66, 0x90, 0xff, - 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, - 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0x66, - 0x90, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, 0xff, 0xe0, - 0xff, 0xe0, - }, - }, - { - name: "JMP to memory", - setupFn: func(assembler Assembler) { - for i := 0; i < 128; i++ { - assembler.CompileJumpToMemory(JMP, RegAX, 10) - } - }, - expected: []byte{ - 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, - 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, - 0x66, 0x90, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, - 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, - 0xff, 0x60, 0xa, 0x66, 0x90, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, - 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, - 0x60, 0xa, 0xff, 0x60, 0xa, 0x66, 0x90, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, - 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, - 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0x66, 0x90, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, - 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, - 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0x66, 0x90, 0xff, 0x60, 0xa, 0xff, - 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, - 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0x66, 0x90, 0xff, 0x60, - 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, - 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0x66, 0x90, - 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, - 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, - 0x66, 0x90, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, - 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, - 0x60, 0xa, 0x66, 0x90, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, - 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, - 0xa, 0xff, 0x60, 0xa, 0x66, 0x90, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, - 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, - 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0x66, 0x90, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, - 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, - 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0x66, 0x90, 0xff, 0x60, 0xa, 0xff, 0x60, - 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, 0xa, 0xff, 0x60, - 0xa, 0xff, 0x60, 0xa, - }, - }, - { - name: "JMP to memory large offset", - setupFn: func(assembler Assembler) { - for i := 0; i < 128; i++ { - assembler.CompileJumpToMemory(JMP, RegAX, math.MaxInt32) - } - }, - expected: []byte{ - 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, - 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x66, 0x90, - 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, - 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x66, 0x90, - 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, - 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x66, 0x90, - 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, - 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x66, 0x90, - 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, - 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x66, 0x90, - 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, - 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x66, 0x90, - 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, - 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x66, 0x90, - 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, - 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x66, 0x90, - 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, - 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x66, 0x90, - 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, - 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x66, 0x90, - 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, - 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x66, 0x90, - 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, - 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x66, 0x90, - 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, - 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x66, 0x90, - 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, - 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x66, 0x90, - 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, - 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x66, 0x90, - 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, - 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x66, 0x90, - 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, - 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x66, 0x90, - 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, - 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x66, 0x90, - 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, - 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x66, 0x90, - 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, - 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x66, 0x90, - 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, - 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x66, 0x90, - 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, - 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x66, 0x90, - 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, - 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x66, 0x90, - 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, - 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x66, 0x90, - 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, - 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x66, 0x90, - 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xa0, 0xff, 0xff, - 0xff, 0x7f, - }, - }, - } - - for _, tt := range tests { - tc := tt - t.Run(tc.name, func(t *testing.T) { - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - a := NewAssembler() - tc.setupFn(a) - - buf := code.NextCodeSection() - err := a.Assemble(buf) - require.NoError(t, err) - - actual := buf.Bytes() - require.Equal(t, tc.expected, actual) - }) - } - }) - - t.Run("relative jumps", func(t *testing.T) { - tests := []struct { - jmpInst asm.Instruction - backward bool - exp []byte - }{ - { - backward: false, jmpInst: JMP, exp: []byte{ - 0xc3, 0xe9, 0xe4, 0x1, 0x0, 0x0, 0xe9, 0xdf, 0x1, 0x0, 0x0, 0xe9, 0xda, 0x1, 0x0, 0x0, 0xe9, 0xd5, - 0x1, 0x0, 0x0, 0xe9, 0xd0, 0x1, 0x0, 0x0, 0xe9, 0xcb, 0x1, 0x0, 0x0, 0x90, 0xe9, 0xc5, 0x1, 0x0, - 0x0, 0xe9, 0xc0, 0x1, 0x0, 0x0, 0xe9, 0xbb, 0x1, 0x0, 0x0, 0xe9, 0xb6, 0x1, 0x0, 0x0, 0xe9, 0xb1, - 0x1, 0x0, 0x0, 0xe9, 0xac, 0x1, 0x0, 0x0, 0x66, 0x90, 0xe9, 0xa5, 0x1, 0x0, 0x0, 0xe9, 0xa0, 0x1, - 0x0, 0x0, 0xe9, 0x9b, 0x1, 0x0, 0x0, 0xe9, 0x96, 0x1, 0x0, 0x0, 0xe9, 0x91, 0x1, 0x0, 0x0, 0xe9, - 0x8c, 0x1, 0x0, 0x0, 0x66, 0x90, 0xe9, 0x85, 0x1, 0x0, 0x0, 0xe9, 0x80, 0x1, 0x0, 0x0, 0xe9, 0x7b, - 0x1, 0x0, 0x0, 0xe9, 0x76, 0x1, 0x0, 0x0, 0xe9, 0x71, 0x1, 0x0, 0x0, 0xe9, 0x6c, 0x1, 0x0, 0x0, - 0x66, 0x90, 0xe9, 0x65, 0x1, 0x0, 0x0, 0xe9, 0x60, 0x1, 0x0, 0x0, 0xe9, 0x5b, 0x1, 0x0, 0x0, 0xe9, - 0x56, 0x1, 0x0, 0x0, 0xe9, 0x51, 0x1, 0x0, 0x0, 0xe9, 0x4c, 0x1, 0x0, 0x0, 0x66, 0x90, 0xe9, 0x45, - 0x1, 0x0, 0x0, 0xe9, 0x40, 0x1, 0x0, 0x0, 0xe9, 0x3b, 0x1, 0x0, 0x0, 0xe9, 0x36, 0x1, 0x0, 0x0, 0xe9, - 0x31, 0x1, 0x0, 0x0, 0xe9, 0x2c, 0x1, 0x0, 0x0, 0x66, 0x90, 0xe9, 0x25, 0x1, 0x0, 0x0, 0xe9, 0x20, 0x1, - 0x0, 0x0, 0xe9, 0x1b, 0x1, 0x0, 0x0, 0xe9, 0x16, 0x1, 0x0, 0x0, 0xe9, 0x11, 0x1, 0x0, 0x0, 0xe9, 0xc, - 0x1, 0x0, 0x0, 0x66, 0x90, 0xe9, 0x5, 0x1, 0x0, 0x0, 0xe9, 0x0, 0x1, 0x0, 0x0, 0xe9, 0xfb, 0x0, 0x0, - 0x0, 0xe9, 0xf6, 0x0, 0x0, 0x0, 0xe9, 0xf1, 0x0, 0x0, 0x0, 0xe9, 0xec, 0x0, 0x0, 0x0, 0x66, 0x90, 0xe9, - 0xe5, 0x0, 0x0, 0x0, 0xe9, 0xe0, 0x0, 0x0, 0x0, 0xe9, 0xdb, 0x0, 0x0, 0x0, 0xe9, 0xd6, 0x0, 0x0, 0x0, - 0xe9, 0xd1, 0x0, 0x0, 0x0, 0xe9, 0xcc, 0x0, 0x0, 0x0, 0x66, 0x90, 0xe9, 0xc5, 0x0, 0x0, 0x0, 0xe9, 0xc0, - 0x0, 0x0, 0x0, 0xe9, 0xbb, 0x0, 0x0, 0x0, 0xe9, 0xb6, 0x0, 0x0, 0x0, 0xe9, 0xb1, 0x0, 0x0, 0x0, 0xe9, - 0xac, 0x0, 0x0, 0x0, 0x66, 0x90, 0xe9, 0xa5, 0x0, 0x0, 0x0, 0xe9, 0xa0, 0x0, 0x0, 0x0, 0xe9, 0x9b, 0x0, - 0x0, 0x0, 0xe9, 0x96, 0x0, 0x0, 0x0, 0xe9, 0x91, 0x0, 0x0, 0x0, 0xe9, 0x8c, 0x0, 0x0, 0x0, 0x66, 0x90, - 0xe9, 0x85, 0x0, 0x0, 0x0, 0xe9, 0x80, 0x0, 0x0, 0x0, 0xeb, 0x7e, 0xeb, 0x7c, 0xeb, 0x7a, 0xeb, 0x78, 0xeb, - 0x76, 0xeb, 0x74, 0xeb, 0x72, 0xeb, 0x70, 0xeb, 0x6e, 0xeb, 0x6c, 0x66, 0x90, 0xeb, 0x68, 0xeb, 0x66, 0xeb, 0x64, - 0xeb, 0x62, 0xeb, 0x60, 0xeb, 0x5e, 0xeb, 0x5c, 0xeb, 0x5a, 0xeb, 0x58, 0xeb, 0x56, 0xeb, 0x54, 0xeb, 0x52, 0xeb, - 0x50, 0xeb, 0x4e, 0xeb, 0x4c, 0x66, 0x90, 0xeb, 0x48, 0xeb, 0x46, 0xeb, 0x44, 0xeb, 0x42, 0xeb, 0x40, 0xeb, 0x3e, - 0xeb, 0x3c, 0xeb, 0x3a, 0xeb, 0x38, 0xeb, 0x36, 0xeb, 0x34, 0xeb, 0x32, 0xeb, 0x30, 0xeb, 0x2e, 0xeb, 0x2c, - 0x66, 0x90, 0xeb, 0x28, 0xeb, 0x26, 0xeb, 0x24, 0xeb, 0x22, 0xeb, 0x20, 0xeb, 0x1e, 0xeb, 0x1c, 0xeb, - 0x1a, 0xeb, 0x18, 0xeb, 0x16, 0xeb, 0x14, 0xeb, 0x12, 0xeb, 0x10, 0xeb, 0xe, 0xeb, 0xc, 0x66, 0x90, - 0xeb, 0x8, 0xeb, 0x6, 0xeb, 0x4, 0xeb, 0x2, 0xeb, 0x0, 0xc3, - }, - }, - { - backward: false, jmpInst: JCC, exp: []byte{ - 0xc3, 0xf, 0x83, 0x2b, 0x2, 0x0, 0x0, 0xf, 0x83, 0x25, 0x2, 0x0, 0x0, 0xf, 0x83, 0x1f, 0x2, 0x0, - 0x0, 0xf, 0x83, 0x19, 0x2, 0x0, 0x0, 0xf, 0x83, 0x13, 0x2, 0x0, 0x0, 0x90, 0xf, 0x83, 0xc, 0x2, - 0x0, 0x0, 0xf, 0x83, 0x6, 0x2, 0x0, 0x0, 0xf, 0x83, 0x0, 0x2, 0x0, 0x0, 0xf, 0x83, 0xfa, 0x1, - 0x0, 0x0, 0xf, 0x83, 0xf4, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x83, 0xec, 0x1, 0x0, 0x0, 0xf, 0x83, - 0xe6, 0x1, 0x0, 0x0, 0xf, 0x83, 0xe0, 0x1, 0x0, 0x0, 0xf, 0x83, 0xda, 0x1, 0x0, 0x0, 0xf, 0x83, - 0xd4, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x83, 0xcc, 0x1, 0x0, 0x0, 0xf, 0x83, 0xc6, 0x1, 0x0, 0x0, - 0xf, 0x83, 0xc0, 0x1, 0x0, 0x0, 0xf, 0x83, 0xba, 0x1, 0x0, 0x0, 0xf, 0x83, 0xb4, 0x1, 0x0, 0x0, - 0x66, 0x90, 0xf, 0x83, 0xac, 0x1, 0x0, 0x0, 0xf, 0x83, 0xa6, 0x1, 0x0, 0x0, 0xf, 0x83, 0xa0, 0x1, - 0x0, 0x0, 0xf, 0x83, 0x9a, 0x1, 0x0, 0x0, 0xf, 0x83, 0x94, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x83, - 0x8c, 0x1, 0x0, 0x0, 0xf, 0x83, 0x86, 0x1, 0x0, 0x0, 0xf, 0x83, 0x80, 0x1, 0x0, 0x0, 0xf, 0x83, 0x7a, - 0x1, 0x0, 0x0, 0xf, 0x83, 0x74, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x83, 0x6c, 0x1, 0x0, 0x0, 0xf, 0x83, - 0x66, 0x1, 0x0, 0x0, 0xf, 0x83, 0x60, 0x1, 0x0, 0x0, 0xf, 0x83, 0x5a, 0x1, 0x0, 0x0, 0xf, 0x83, 0x54, - 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x83, 0x4c, 0x1, 0x0, 0x0, 0xf, 0x83, 0x46, 0x1, 0x0, 0x0, 0xf, 0x83, - 0x40, 0x1, 0x0, 0x0, 0xf, 0x83, 0x3a, 0x1, 0x0, 0x0, 0xf, 0x83, 0x34, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, - 0x83, 0x2c, 0x1, 0x0, 0x0, 0xf, 0x83, 0x26, 0x1, 0x0, 0x0, 0xf, 0x83, 0x20, 0x1, 0x0, 0x0, 0xf, 0x83, - 0x1a, 0x1, 0x0, 0x0, 0xf, 0x83, 0x14, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x83, 0xc, 0x1, 0x0, 0x0, 0xf, - 0x83, 0x6, 0x1, 0x0, 0x0, 0xf, 0x83, 0x0, 0x1, 0x0, 0x0, 0xf, 0x83, 0xfa, 0x0, 0x0, 0x0, 0xf, 0x83, - 0xf4, 0x0, 0x0, 0x0, 0x66, 0x90, 0xf, 0x83, 0xec, 0x0, 0x0, 0x0, 0xf, 0x83, 0xe6, 0x0, 0x0, 0x0, 0xf, - 0x83, 0xe0, 0x0, 0x0, 0x0, 0xf, 0x83, 0xda, 0x0, 0x0, 0x0, 0xf, 0x83, 0xd4, 0x0, 0x0, 0x0, 0x66, 0x90, - 0xf, 0x83, 0xcc, 0x0, 0x0, 0x0, 0xf, 0x83, 0xc6, 0x0, 0x0, 0x0, 0xf, 0x83, 0xc0, 0x0, 0x0, 0x0, 0xf, - 0x83, 0xba, 0x0, 0x0, 0x0, 0xf, 0x83, 0xb4, 0x0, 0x0, 0x0, 0x66, 0x90, 0xf, 0x83, 0xac, 0x0, 0x0, 0x0, - 0xf, 0x83, 0xa6, 0x0, 0x0, 0x0, 0xf, 0x83, 0xa0, 0x0, 0x0, 0x0, 0xf, 0x83, 0x9a, 0x0, 0x0, 0x0, 0xf, - 0x83, 0x94, 0x0, 0x0, 0x0, 0x66, 0x90, 0xf, 0x83, 0x8c, 0x0, 0x0, 0x0, 0xf, 0x83, 0x86, 0x0, 0x0, 0x0, - 0xf, 0x83, 0x80, 0x0, 0x0, 0x0, 0x73, 0x7e, 0x73, 0x7c, 0x73, 0x7a, 0x73, 0x78, 0x73, 0x76, 0x73, 0x74, - 0x66, 0x90, 0x73, 0x70, 0x73, 0x6e, 0x73, 0x6c, 0x73, 0x6a, 0x73, 0x68, 0x73, 0x66, 0x73, 0x64, 0x73, - 0x62, 0x73, 0x60, 0x73, 0x5e, 0x73, 0x5c, 0x73, 0x5a, 0x73, 0x58, 0x73, 0x56, 0x73, 0x54, 0x66, 0x90, - 0x73, 0x50, 0x73, 0x4e, 0x73, 0x4c, 0x73, 0x4a, 0x73, 0x48, 0x73, 0x46, 0x73, 0x44, 0x73, 0x42, 0x73, - 0x40, 0x73, 0x3e, 0x73, 0x3c, 0x73, 0x3a, 0x73, 0x38, 0x73, 0x36, 0x73, 0x34, 0x66, 0x90, 0x73, 0x30, - 0x73, 0x2e, 0x73, 0x2c, 0x73, 0x2a, 0x73, 0x28, 0x73, 0x26, 0x73, 0x24, 0x73, 0x22, 0x73, 0x20, 0x73, - 0x1e, 0x73, 0x1c, 0x73, 0x1a, 0x73, 0x18, 0x73, 0x16, 0x73, 0x14, 0x66, 0x90, 0x73, 0x10, 0x73, 0xe, - 0x73, 0xc, 0x73, 0xa, 0x73, 0x8, 0x73, 0x6, 0x73, 0x4, 0x73, 0x2, 0x73, 0x0, 0xc3, - }, - }, - { - backward: false, jmpInst: JCS, exp: []byte{ - 0xc3, 0xf, 0x82, 0x2b, 0x2, 0x0, 0x0, 0xf, 0x82, 0x25, 0x2, 0x0, 0x0, 0xf, 0x82, 0x1f, 0x2, 0x0, - 0x0, 0xf, 0x82, 0x19, 0x2, 0x0, 0x0, 0xf, 0x82, 0x13, 0x2, 0x0, 0x0, 0x90, 0xf, 0x82, 0xc, 0x2, - 0x0, 0x0, 0xf, 0x82, 0x6, 0x2, 0x0, 0x0, 0xf, 0x82, 0x0, 0x2, 0x0, 0x0, 0xf, 0x82, 0xfa, 0x1, - 0x0, 0x0, 0xf, 0x82, 0xf4, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x82, 0xec, 0x1, 0x0, 0x0, 0xf, 0x82, - 0xe6, 0x1, 0x0, 0x0, 0xf, 0x82, 0xe0, 0x1, 0x0, 0x0, 0xf, 0x82, 0xda, 0x1, 0x0, 0x0, 0xf, 0x82, - 0xd4, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x82, 0xcc, 0x1, 0x0, 0x0, 0xf, 0x82, 0xc6, 0x1, 0x0, 0x0, - 0xf, 0x82, 0xc0, 0x1, 0x0, 0x0, 0xf, 0x82, 0xba, 0x1, 0x0, 0x0, 0xf, 0x82, 0xb4, 0x1, 0x0, 0x0, - 0x66, 0x90, 0xf, 0x82, 0xac, 0x1, 0x0, 0x0, 0xf, 0x82, 0xa6, 0x1, 0x0, 0x0, 0xf, 0x82, 0xa0, 0x1, - 0x0, 0x0, 0xf, 0x82, 0x9a, 0x1, 0x0, 0x0, 0xf, 0x82, 0x94, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x82, - 0x8c, 0x1, 0x0, 0x0, 0xf, 0x82, 0x86, 0x1, 0x0, 0x0, 0xf, 0x82, 0x80, 0x1, 0x0, 0x0, 0xf, 0x82, 0x7a, - 0x1, 0x0, 0x0, 0xf, 0x82, 0x74, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x82, 0x6c, 0x1, 0x0, 0x0, 0xf, 0x82, - 0x66, 0x1, 0x0, 0x0, 0xf, 0x82, 0x60, 0x1, 0x0, 0x0, 0xf, 0x82, 0x5a, 0x1, 0x0, 0x0, 0xf, 0x82, 0x54, - 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x82, 0x4c, 0x1, 0x0, 0x0, 0xf, 0x82, 0x46, 0x1, 0x0, 0x0, 0xf, 0x82, - 0x40, 0x1, 0x0, 0x0, 0xf, 0x82, 0x3a, 0x1, 0x0, 0x0, 0xf, 0x82, 0x34, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, - 0x82, 0x2c, 0x1, 0x0, 0x0, 0xf, 0x82, 0x26, 0x1, 0x0, 0x0, 0xf, 0x82, 0x20, 0x1, 0x0, 0x0, 0xf, 0x82, - 0x1a, 0x1, 0x0, 0x0, 0xf, 0x82, 0x14, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x82, 0xc, 0x1, 0x0, 0x0, 0xf, - 0x82, 0x6, 0x1, 0x0, 0x0, 0xf, 0x82, 0x0, 0x1, 0x0, 0x0, 0xf, 0x82, 0xfa, 0x0, 0x0, 0x0, 0xf, 0x82, - 0xf4, 0x0, 0x0, 0x0, 0x66, 0x90, 0xf, 0x82, 0xec, 0x0, 0x0, 0x0, 0xf, 0x82, 0xe6, 0x0, 0x0, 0x0, 0xf, - 0x82, 0xe0, 0x0, 0x0, 0x0, 0xf, 0x82, 0xda, 0x0, 0x0, 0x0, 0xf, 0x82, 0xd4, 0x0, 0x0, 0x0, 0x66, 0x90, - 0xf, 0x82, 0xcc, 0x0, 0x0, 0x0, 0xf, 0x82, 0xc6, 0x0, 0x0, 0x0, 0xf, 0x82, 0xc0, 0x0, 0x0, 0x0, 0xf, - 0x82, 0xba, 0x0, 0x0, 0x0, 0xf, 0x82, 0xb4, 0x0, 0x0, 0x0, 0x66, 0x90, 0xf, 0x82, 0xac, 0x0, 0x0, 0x0, - 0xf, 0x82, 0xa6, 0x0, 0x0, 0x0, 0xf, 0x82, 0xa0, 0x0, 0x0, 0x0, 0xf, 0x82, 0x9a, 0x0, 0x0, 0x0, 0xf, - 0x82, 0x94, 0x0, 0x0, 0x0, 0x66, 0x90, 0xf, 0x82, 0x8c, 0x0, 0x0, 0x0, 0xf, 0x82, 0x86, 0x0, 0x0, 0x0, - 0xf, 0x82, 0x80, 0x0, 0x0, 0x0, 0x72, 0x7e, 0x72, 0x7c, 0x72, 0x7a, 0x72, 0x78, 0x72, 0x76, 0x72, 0x74, - 0x66, 0x90, 0x72, 0x70, 0x72, 0x6e, 0x72, 0x6c, 0x72, 0x6a, 0x72, 0x68, 0x72, 0x66, 0x72, 0x64, 0x72, - 0x62, 0x72, 0x60, 0x72, 0x5e, 0x72, 0x5c, 0x72, 0x5a, 0x72, 0x58, 0x72, 0x56, 0x72, 0x54, 0x66, 0x90, - 0x72, 0x50, 0x72, 0x4e, 0x72, 0x4c, 0x72, 0x4a, 0x72, 0x48, 0x72, 0x46, 0x72, 0x44, 0x72, 0x42, 0x72, - 0x40, 0x72, 0x3e, 0x72, 0x3c, 0x72, 0x3a, 0x72, 0x38, 0x72, 0x36, 0x72, 0x34, 0x66, 0x90, 0x72, 0x30, - 0x72, 0x2e, 0x72, 0x2c, 0x72, 0x2a, 0x72, 0x28, 0x72, 0x26, 0x72, 0x24, 0x72, 0x22, 0x72, 0x20, 0x72, - 0x1e, 0x72, 0x1c, 0x72, 0x1a, 0x72, 0x18, 0x72, 0x16, 0x72, 0x14, 0x66, 0x90, 0x72, 0x10, 0x72, 0xe, - 0x72, 0xc, 0x72, 0xa, 0x72, 0x8, 0x72, 0x6, 0x72, 0x4, 0x72, 0x2, 0x72, 0x0, 0xc3, - }, - }, - { - backward: false, jmpInst: JEQ, exp: []byte{ - 0xc3, 0xf, 0x84, 0x2b, 0x2, 0x0, 0x0, 0xf, 0x84, 0x25, 0x2, 0x0, 0x0, 0xf, 0x84, 0x1f, 0x2, 0x0, - 0x0, 0xf, 0x84, 0x19, 0x2, 0x0, 0x0, 0xf, 0x84, 0x13, 0x2, 0x0, 0x0, 0x90, 0xf, 0x84, 0xc, 0x2, - 0x0, 0x0, 0xf, 0x84, 0x6, 0x2, 0x0, 0x0, 0xf, 0x84, 0x0, 0x2, 0x0, 0x0, 0xf, 0x84, 0xfa, 0x1, - 0x0, 0x0, 0xf, 0x84, 0xf4, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x84, 0xec, 0x1, 0x0, 0x0, 0xf, 0x84, - 0xe6, 0x1, 0x0, 0x0, 0xf, 0x84, 0xe0, 0x1, 0x0, 0x0, 0xf, 0x84, 0xda, 0x1, 0x0, 0x0, 0xf, 0x84, - 0xd4, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x84, 0xcc, 0x1, 0x0, 0x0, 0xf, 0x84, 0xc6, 0x1, 0x0, 0x0, - 0xf, 0x84, 0xc0, 0x1, 0x0, 0x0, 0xf, 0x84, 0xba, 0x1, 0x0, 0x0, 0xf, 0x84, 0xb4, 0x1, 0x0, 0x0, - 0x66, 0x90, 0xf, 0x84, 0xac, 0x1, 0x0, 0x0, 0xf, 0x84, 0xa6, 0x1, 0x0, 0x0, 0xf, 0x84, 0xa0, 0x1, - 0x0, 0x0, 0xf, 0x84, 0x9a, 0x1, 0x0, 0x0, 0xf, 0x84, 0x94, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x84, - 0x8c, 0x1, 0x0, 0x0, 0xf, 0x84, 0x86, 0x1, 0x0, 0x0, 0xf, 0x84, 0x80, 0x1, 0x0, 0x0, 0xf, 0x84, 0x7a, - 0x1, 0x0, 0x0, 0xf, 0x84, 0x74, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x84, 0x6c, 0x1, 0x0, 0x0, 0xf, 0x84, - 0x66, 0x1, 0x0, 0x0, 0xf, 0x84, 0x60, 0x1, 0x0, 0x0, 0xf, 0x84, 0x5a, 0x1, 0x0, 0x0, 0xf, 0x84, 0x54, - 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x84, 0x4c, 0x1, 0x0, 0x0, 0xf, 0x84, 0x46, 0x1, 0x0, 0x0, 0xf, 0x84, - 0x40, 0x1, 0x0, 0x0, 0xf, 0x84, 0x3a, 0x1, 0x0, 0x0, 0xf, 0x84, 0x34, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, - 0x84, 0x2c, 0x1, 0x0, 0x0, 0xf, 0x84, 0x26, 0x1, 0x0, 0x0, 0xf, 0x84, 0x20, 0x1, 0x0, 0x0, 0xf, 0x84, - 0x1a, 0x1, 0x0, 0x0, 0xf, 0x84, 0x14, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x84, 0xc, 0x1, 0x0, 0x0, 0xf, - 0x84, 0x6, 0x1, 0x0, 0x0, 0xf, 0x84, 0x0, 0x1, 0x0, 0x0, 0xf, 0x84, 0xfa, 0x0, 0x0, 0x0, 0xf, 0x84, - 0xf4, 0x0, 0x0, 0x0, 0x66, 0x90, 0xf, 0x84, 0xec, 0x0, 0x0, 0x0, 0xf, 0x84, 0xe6, 0x0, 0x0, 0x0, 0xf, - 0x84, 0xe0, 0x0, 0x0, 0x0, 0xf, 0x84, 0xda, 0x0, 0x0, 0x0, 0xf, 0x84, 0xd4, 0x0, 0x0, 0x0, 0x66, 0x90, - 0xf, 0x84, 0xcc, 0x0, 0x0, 0x0, 0xf, 0x84, 0xc6, 0x0, 0x0, 0x0, 0xf, 0x84, 0xc0, 0x0, 0x0, 0x0, 0xf, - 0x84, 0xba, 0x0, 0x0, 0x0, 0xf, 0x84, 0xb4, 0x0, 0x0, 0x0, 0x66, 0x90, 0xf, 0x84, 0xac, 0x0, 0x0, 0x0, - 0xf, 0x84, 0xa6, 0x0, 0x0, 0x0, 0xf, 0x84, 0xa0, 0x0, 0x0, 0x0, 0xf, 0x84, 0x9a, 0x0, 0x0, 0x0, 0xf, - 0x84, 0x94, 0x0, 0x0, 0x0, 0x66, 0x90, 0xf, 0x84, 0x8c, 0x0, 0x0, 0x0, 0xf, 0x84, 0x86, 0x0, 0x0, 0x0, - 0xf, 0x84, 0x80, 0x0, 0x0, 0x0, 0x74, 0x7e, 0x74, 0x7c, 0x74, 0x7a, 0x74, 0x78, 0x74, 0x76, 0x74, 0x74, - 0x66, 0x90, 0x74, 0x70, 0x74, 0x6e, 0x74, 0x6c, 0x74, 0x6a, 0x74, 0x68, 0x74, 0x66, 0x74, 0x64, 0x74, - 0x62, 0x74, 0x60, 0x74, 0x5e, 0x74, 0x5c, 0x74, 0x5a, 0x74, 0x58, 0x74, 0x56, 0x74, 0x54, 0x66, 0x90, - 0x74, 0x50, 0x74, 0x4e, 0x74, 0x4c, 0x74, 0x4a, 0x74, 0x48, 0x74, 0x46, 0x74, 0x44, 0x74, 0x42, 0x74, - 0x40, 0x74, 0x3e, 0x74, 0x3c, 0x74, 0x3a, 0x74, 0x38, 0x74, 0x36, 0x74, 0x34, 0x66, 0x90, 0x74, 0x30, - 0x74, 0x2e, 0x74, 0x2c, 0x74, 0x2a, 0x74, 0x28, 0x74, 0x26, 0x74, 0x24, 0x74, 0x22, 0x74, 0x20, 0x74, - 0x1e, 0x74, 0x1c, 0x74, 0x1a, 0x74, 0x18, 0x74, 0x16, 0x74, 0x14, 0x66, 0x90, 0x74, 0x10, 0x74, 0xe, - 0x74, 0xc, 0x74, 0xa, 0x74, 0x8, 0x74, 0x6, 0x74, 0x4, 0x74, 0x2, 0x74, 0x0, 0xc3, - }, - }, - { - backward: false, jmpInst: JGE, exp: []byte{ - 0xc3, 0xf, 0x8d, 0x2b, 0x2, 0x0, 0x0, 0xf, 0x8d, 0x25, 0x2, 0x0, 0x0, 0xf, 0x8d, 0x1f, 0x2, 0x0, - 0x0, 0xf, 0x8d, 0x19, 0x2, 0x0, 0x0, 0xf, 0x8d, 0x13, 0x2, 0x0, 0x0, 0x90, 0xf, 0x8d, 0xc, 0x2, - 0x0, 0x0, 0xf, 0x8d, 0x6, 0x2, 0x0, 0x0, 0xf, 0x8d, 0x0, 0x2, 0x0, 0x0, 0xf, 0x8d, 0xfa, 0x1, - 0x0, 0x0, 0xf, 0x8d, 0xf4, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8d, 0xec, 0x1, 0x0, 0x0, 0xf, 0x8d, - 0xe6, 0x1, 0x0, 0x0, 0xf, 0x8d, 0xe0, 0x1, 0x0, 0x0, 0xf, 0x8d, 0xda, 0x1, 0x0, 0x0, 0xf, 0x8d, - 0xd4, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8d, 0xcc, 0x1, 0x0, 0x0, 0xf, 0x8d, 0xc6, 0x1, 0x0, 0x0, - 0xf, 0x8d, 0xc0, 0x1, 0x0, 0x0, 0xf, 0x8d, 0xba, 0x1, 0x0, 0x0, 0xf, 0x8d, 0xb4, 0x1, 0x0, 0x0, - 0x66, 0x90, 0xf, 0x8d, 0xac, 0x1, 0x0, 0x0, 0xf, 0x8d, 0xa6, 0x1, 0x0, 0x0, 0xf, 0x8d, 0xa0, 0x1, - 0x0, 0x0, 0xf, 0x8d, 0x9a, 0x1, 0x0, 0x0, 0xf, 0x8d, 0x94, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8d, - 0x8c, 0x1, 0x0, 0x0, 0xf, 0x8d, 0x86, 0x1, 0x0, 0x0, 0xf, 0x8d, 0x80, 0x1, 0x0, 0x0, 0xf, 0x8d, 0x7a, - 0x1, 0x0, 0x0, 0xf, 0x8d, 0x74, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8d, 0x6c, 0x1, 0x0, 0x0, 0xf, 0x8d, - 0x66, 0x1, 0x0, 0x0, 0xf, 0x8d, 0x60, 0x1, 0x0, 0x0, 0xf, 0x8d, 0x5a, 0x1, 0x0, 0x0, 0xf, 0x8d, 0x54, - 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8d, 0x4c, 0x1, 0x0, 0x0, 0xf, 0x8d, 0x46, 0x1, 0x0, 0x0, 0xf, 0x8d, - 0x40, 0x1, 0x0, 0x0, 0xf, 0x8d, 0x3a, 0x1, 0x0, 0x0, 0xf, 0x8d, 0x34, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, - 0x8d, 0x2c, 0x1, 0x0, 0x0, 0xf, 0x8d, 0x26, 0x1, 0x0, 0x0, 0xf, 0x8d, 0x20, 0x1, 0x0, 0x0, 0xf, 0x8d, - 0x1a, 0x1, 0x0, 0x0, 0xf, 0x8d, 0x14, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8d, 0xc, 0x1, 0x0, 0x0, 0xf, - 0x8d, 0x6, 0x1, 0x0, 0x0, 0xf, 0x8d, 0x0, 0x1, 0x0, 0x0, 0xf, 0x8d, 0xfa, 0x0, 0x0, 0x0, 0xf, 0x8d, - 0xf4, 0x0, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8d, 0xec, 0x0, 0x0, 0x0, 0xf, 0x8d, 0xe6, 0x0, 0x0, 0x0, 0xf, - 0x8d, 0xe0, 0x0, 0x0, 0x0, 0xf, 0x8d, 0xda, 0x0, 0x0, 0x0, 0xf, 0x8d, 0xd4, 0x0, 0x0, 0x0, 0x66, 0x90, - 0xf, 0x8d, 0xcc, 0x0, 0x0, 0x0, 0xf, 0x8d, 0xc6, 0x0, 0x0, 0x0, 0xf, 0x8d, 0xc0, 0x0, 0x0, 0x0, 0xf, - 0x8d, 0xba, 0x0, 0x0, 0x0, 0xf, 0x8d, 0xb4, 0x0, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8d, 0xac, 0x0, 0x0, 0x0, - 0xf, 0x8d, 0xa6, 0x0, 0x0, 0x0, 0xf, 0x8d, 0xa0, 0x0, 0x0, 0x0, 0xf, 0x8d, 0x9a, 0x0, 0x0, 0x0, 0xf, - 0x8d, 0x94, 0x0, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8d, 0x8c, 0x0, 0x0, 0x0, 0xf, 0x8d, 0x86, 0x0, 0x0, 0x0, - 0xf, 0x8d, 0x80, 0x0, 0x0, 0x0, 0x7d, 0x7e, 0x7d, 0x7c, 0x7d, 0x7a, 0x7d, 0x78, 0x7d, 0x76, 0x7d, 0x74, - 0x66, 0x90, 0x7d, 0x70, 0x7d, 0x6e, 0x7d, 0x6c, 0x7d, 0x6a, 0x7d, 0x68, 0x7d, 0x66, 0x7d, 0x64, 0x7d, - 0x62, 0x7d, 0x60, 0x7d, 0x5e, 0x7d, 0x5c, 0x7d, 0x5a, 0x7d, 0x58, 0x7d, 0x56, 0x7d, 0x54, 0x66, 0x90, - 0x7d, 0x50, 0x7d, 0x4e, 0x7d, 0x4c, 0x7d, 0x4a, 0x7d, 0x48, 0x7d, 0x46, 0x7d, 0x44, 0x7d, 0x42, 0x7d, - 0x40, 0x7d, 0x3e, 0x7d, 0x3c, 0x7d, 0x3a, 0x7d, 0x38, 0x7d, 0x36, 0x7d, 0x34, 0x66, 0x90, 0x7d, 0x30, - 0x7d, 0x2e, 0x7d, 0x2c, 0x7d, 0x2a, 0x7d, 0x28, 0x7d, 0x26, 0x7d, 0x24, 0x7d, 0x22, 0x7d, 0x20, 0x7d, - 0x1e, 0x7d, 0x1c, 0x7d, 0x1a, 0x7d, 0x18, 0x7d, 0x16, 0x7d, 0x14, 0x66, 0x90, 0x7d, 0x10, 0x7d, 0xe, - 0x7d, 0xc, 0x7d, 0xa, 0x7d, 0x8, 0x7d, 0x6, 0x7d, 0x4, 0x7d, 0x2, 0x7d, 0x0, 0xc3, - }, - }, - { - backward: false, jmpInst: JGT, exp: []byte{ - 0xc3, 0xf, 0x8f, 0x2b, 0x2, 0x0, 0x0, 0xf, 0x8f, 0x25, 0x2, 0x0, 0x0, 0xf, 0x8f, 0x1f, 0x2, 0x0, - 0x0, 0xf, 0x8f, 0x19, 0x2, 0x0, 0x0, 0xf, 0x8f, 0x13, 0x2, 0x0, 0x0, 0x90, 0xf, 0x8f, 0xc, 0x2, - 0x0, 0x0, 0xf, 0x8f, 0x6, 0x2, 0x0, 0x0, 0xf, 0x8f, 0x0, 0x2, 0x0, 0x0, 0xf, 0x8f, 0xfa, 0x1, - 0x0, 0x0, 0xf, 0x8f, 0xf4, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8f, 0xec, 0x1, 0x0, 0x0, 0xf, 0x8f, - 0xe6, 0x1, 0x0, 0x0, 0xf, 0x8f, 0xe0, 0x1, 0x0, 0x0, 0xf, 0x8f, 0xda, 0x1, 0x0, 0x0, 0xf, 0x8f, - 0xd4, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8f, 0xcc, 0x1, 0x0, 0x0, 0xf, 0x8f, 0xc6, 0x1, 0x0, 0x0, - 0xf, 0x8f, 0xc0, 0x1, 0x0, 0x0, 0xf, 0x8f, 0xba, 0x1, 0x0, 0x0, 0xf, 0x8f, 0xb4, 0x1, 0x0, 0x0, - 0x66, 0x90, 0xf, 0x8f, 0xac, 0x1, 0x0, 0x0, 0xf, 0x8f, 0xa6, 0x1, 0x0, 0x0, 0xf, 0x8f, 0xa0, 0x1, - 0x0, 0x0, 0xf, 0x8f, 0x9a, 0x1, 0x0, 0x0, 0xf, 0x8f, 0x94, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8f, - 0x8c, 0x1, 0x0, 0x0, 0xf, 0x8f, 0x86, 0x1, 0x0, 0x0, 0xf, 0x8f, 0x80, 0x1, 0x0, 0x0, 0xf, 0x8f, 0x7a, - 0x1, 0x0, 0x0, 0xf, 0x8f, 0x74, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8f, 0x6c, 0x1, 0x0, 0x0, 0xf, 0x8f, - 0x66, 0x1, 0x0, 0x0, 0xf, 0x8f, 0x60, 0x1, 0x0, 0x0, 0xf, 0x8f, 0x5a, 0x1, 0x0, 0x0, 0xf, 0x8f, 0x54, - 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8f, 0x4c, 0x1, 0x0, 0x0, 0xf, 0x8f, 0x46, 0x1, 0x0, 0x0, 0xf, 0x8f, - 0x40, 0x1, 0x0, 0x0, 0xf, 0x8f, 0x3a, 0x1, 0x0, 0x0, 0xf, 0x8f, 0x34, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, - 0x8f, 0x2c, 0x1, 0x0, 0x0, 0xf, 0x8f, 0x26, 0x1, 0x0, 0x0, 0xf, 0x8f, 0x20, 0x1, 0x0, 0x0, 0xf, 0x8f, - 0x1a, 0x1, 0x0, 0x0, 0xf, 0x8f, 0x14, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8f, 0xc, 0x1, 0x0, 0x0, 0xf, - 0x8f, 0x6, 0x1, 0x0, 0x0, 0xf, 0x8f, 0x0, 0x1, 0x0, 0x0, 0xf, 0x8f, 0xfa, 0x0, 0x0, 0x0, 0xf, 0x8f, - 0xf4, 0x0, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8f, 0xec, 0x0, 0x0, 0x0, 0xf, 0x8f, 0xe6, 0x0, 0x0, 0x0, 0xf, - 0x8f, 0xe0, 0x0, 0x0, 0x0, 0xf, 0x8f, 0xda, 0x0, 0x0, 0x0, 0xf, 0x8f, 0xd4, 0x0, 0x0, 0x0, 0x66, 0x90, - 0xf, 0x8f, 0xcc, 0x0, 0x0, 0x0, 0xf, 0x8f, 0xc6, 0x0, 0x0, 0x0, 0xf, 0x8f, 0xc0, 0x0, 0x0, 0x0, 0xf, - 0x8f, 0xba, 0x0, 0x0, 0x0, 0xf, 0x8f, 0xb4, 0x0, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8f, 0xac, 0x0, 0x0, 0x0, - 0xf, 0x8f, 0xa6, 0x0, 0x0, 0x0, 0xf, 0x8f, 0xa0, 0x0, 0x0, 0x0, 0xf, 0x8f, 0x9a, 0x0, 0x0, 0x0, 0xf, - 0x8f, 0x94, 0x0, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8f, 0x8c, 0x0, 0x0, 0x0, 0xf, 0x8f, 0x86, 0x0, 0x0, 0x0, - 0xf, 0x8f, 0x80, 0x0, 0x0, 0x0, 0x7f, 0x7e, 0x7f, 0x7c, 0x7f, 0x7a, 0x7f, 0x78, 0x7f, 0x76, 0x7f, 0x74, - 0x66, 0x90, 0x7f, 0x70, 0x7f, 0x6e, 0x7f, 0x6c, 0x7f, 0x6a, 0x7f, 0x68, 0x7f, 0x66, 0x7f, 0x64, 0x7f, - 0x62, 0x7f, 0x60, 0x7f, 0x5e, 0x7f, 0x5c, 0x7f, 0x5a, 0x7f, 0x58, 0x7f, 0x56, 0x7f, 0x54, 0x66, 0x90, - 0x7f, 0x50, 0x7f, 0x4e, 0x7f, 0x4c, 0x7f, 0x4a, 0x7f, 0x48, 0x7f, 0x46, 0x7f, 0x44, 0x7f, 0x42, 0x7f, - 0x40, 0x7f, 0x3e, 0x7f, 0x3c, 0x7f, 0x3a, 0x7f, 0x38, 0x7f, 0x36, 0x7f, 0x34, 0x66, 0x90, 0x7f, 0x30, - 0x7f, 0x2e, 0x7f, 0x2c, 0x7f, 0x2a, 0x7f, 0x28, 0x7f, 0x26, 0x7f, 0x24, 0x7f, 0x22, 0x7f, 0x20, 0x7f, - 0x1e, 0x7f, 0x1c, 0x7f, 0x1a, 0x7f, 0x18, 0x7f, 0x16, 0x7f, 0x14, 0x66, 0x90, 0x7f, 0x10, 0x7f, 0xe, - 0x7f, 0xc, 0x7f, 0xa, 0x7f, 0x8, 0x7f, 0x6, 0x7f, 0x4, 0x7f, 0x2, 0x7f, 0x0, 0xc3, - }, - }, - { - backward: false, jmpInst: JHI, exp: []byte{ - 0xc3, 0xf, 0x87, 0x2b, 0x2, 0x0, 0x0, 0xf, 0x87, 0x25, 0x2, 0x0, 0x0, 0xf, 0x87, 0x1f, 0x2, 0x0, - 0x0, 0xf, 0x87, 0x19, 0x2, 0x0, 0x0, 0xf, 0x87, 0x13, 0x2, 0x0, 0x0, 0x90, 0xf, 0x87, 0xc, 0x2, - 0x0, 0x0, 0xf, 0x87, 0x6, 0x2, 0x0, 0x0, 0xf, 0x87, 0x0, 0x2, 0x0, 0x0, 0xf, 0x87, 0xfa, 0x1, - 0x0, 0x0, 0xf, 0x87, 0xf4, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x87, 0xec, 0x1, 0x0, 0x0, 0xf, 0x87, - 0xe6, 0x1, 0x0, 0x0, 0xf, 0x87, 0xe0, 0x1, 0x0, 0x0, 0xf, 0x87, 0xda, 0x1, 0x0, 0x0, 0xf, 0x87, - 0xd4, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x87, 0xcc, 0x1, 0x0, 0x0, 0xf, 0x87, 0xc6, 0x1, 0x0, 0x0, - 0xf, 0x87, 0xc0, 0x1, 0x0, 0x0, 0xf, 0x87, 0xba, 0x1, 0x0, 0x0, 0xf, 0x87, 0xb4, 0x1, 0x0, 0x0, - 0x66, 0x90, 0xf, 0x87, 0xac, 0x1, 0x0, 0x0, 0xf, 0x87, 0xa6, 0x1, 0x0, 0x0, 0xf, 0x87, 0xa0, 0x1, - 0x0, 0x0, 0xf, 0x87, 0x9a, 0x1, 0x0, 0x0, 0xf, 0x87, 0x94, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x87, - 0x8c, 0x1, 0x0, 0x0, 0xf, 0x87, 0x86, 0x1, 0x0, 0x0, 0xf, 0x87, 0x80, 0x1, 0x0, 0x0, 0xf, 0x87, 0x7a, - 0x1, 0x0, 0x0, 0xf, 0x87, 0x74, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x87, 0x6c, 0x1, 0x0, 0x0, 0xf, 0x87, - 0x66, 0x1, 0x0, 0x0, 0xf, 0x87, 0x60, 0x1, 0x0, 0x0, 0xf, 0x87, 0x5a, 0x1, 0x0, 0x0, 0xf, 0x87, 0x54, - 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x87, 0x4c, 0x1, 0x0, 0x0, 0xf, 0x87, 0x46, 0x1, 0x0, 0x0, 0xf, 0x87, - 0x40, 0x1, 0x0, 0x0, 0xf, 0x87, 0x3a, 0x1, 0x0, 0x0, 0xf, 0x87, 0x34, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, - 0x87, 0x2c, 0x1, 0x0, 0x0, 0xf, 0x87, 0x26, 0x1, 0x0, 0x0, 0xf, 0x87, 0x20, 0x1, 0x0, 0x0, 0xf, 0x87, - 0x1a, 0x1, 0x0, 0x0, 0xf, 0x87, 0x14, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x87, 0xc, 0x1, 0x0, 0x0, 0xf, - 0x87, 0x6, 0x1, 0x0, 0x0, 0xf, 0x87, 0x0, 0x1, 0x0, 0x0, 0xf, 0x87, 0xfa, 0x0, 0x0, 0x0, 0xf, 0x87, - 0xf4, 0x0, 0x0, 0x0, 0x66, 0x90, 0xf, 0x87, 0xec, 0x0, 0x0, 0x0, 0xf, 0x87, 0xe6, 0x0, 0x0, 0x0, 0xf, - 0x87, 0xe0, 0x0, 0x0, 0x0, 0xf, 0x87, 0xda, 0x0, 0x0, 0x0, 0xf, 0x87, 0xd4, 0x0, 0x0, 0x0, 0x66, 0x90, - 0xf, 0x87, 0xcc, 0x0, 0x0, 0x0, 0xf, 0x87, 0xc6, 0x0, 0x0, 0x0, 0xf, 0x87, 0xc0, 0x0, 0x0, 0x0, 0xf, - 0x87, 0xba, 0x0, 0x0, 0x0, 0xf, 0x87, 0xb4, 0x0, 0x0, 0x0, 0x66, 0x90, 0xf, 0x87, 0xac, 0x0, 0x0, 0x0, - 0xf, 0x87, 0xa6, 0x0, 0x0, 0x0, 0xf, 0x87, 0xa0, 0x0, 0x0, 0x0, 0xf, 0x87, 0x9a, 0x0, 0x0, 0x0, 0xf, - 0x87, 0x94, 0x0, 0x0, 0x0, 0x66, 0x90, 0xf, 0x87, 0x8c, 0x0, 0x0, 0x0, 0xf, 0x87, 0x86, 0x0, 0x0, 0x0, - 0xf, 0x87, 0x80, 0x0, 0x0, 0x0, 0x77, 0x7e, 0x77, 0x7c, 0x77, 0x7a, 0x77, 0x78, 0x77, 0x76, 0x77, 0x74, - 0x66, 0x90, 0x77, 0x70, 0x77, 0x6e, 0x77, 0x6c, 0x77, 0x6a, 0x77, 0x68, 0x77, 0x66, 0x77, 0x64, 0x77, - 0x62, 0x77, 0x60, 0x77, 0x5e, 0x77, 0x5c, 0x77, 0x5a, 0x77, 0x58, 0x77, 0x56, 0x77, 0x54, 0x66, 0x90, - 0x77, 0x50, 0x77, 0x4e, 0x77, 0x4c, 0x77, 0x4a, 0x77, 0x48, 0x77, 0x46, 0x77, 0x44, 0x77, 0x42, 0x77, - 0x40, 0x77, 0x3e, 0x77, 0x3c, 0x77, 0x3a, 0x77, 0x38, 0x77, 0x36, 0x77, 0x34, 0x66, 0x90, 0x77, 0x30, - 0x77, 0x2e, 0x77, 0x2c, 0x77, 0x2a, 0x77, 0x28, 0x77, 0x26, 0x77, 0x24, 0x77, 0x22, 0x77, 0x20, 0x77, - 0x1e, 0x77, 0x1c, 0x77, 0x1a, 0x77, 0x18, 0x77, 0x16, 0x77, 0x14, 0x66, 0x90, 0x77, 0x10, 0x77, 0xe, - 0x77, 0xc, 0x77, 0xa, 0x77, 0x8, 0x77, 0x6, 0x77, 0x4, 0x77, 0x2, 0x77, 0x0, 0xc3, - }, - }, - { - backward: false, jmpInst: JLE, exp: []byte{ - 0xc3, 0xf, 0x8e, 0x2b, 0x2, 0x0, 0x0, 0xf, 0x8e, 0x25, 0x2, 0x0, 0x0, 0xf, 0x8e, 0x1f, 0x2, 0x0, - 0x0, 0xf, 0x8e, 0x19, 0x2, 0x0, 0x0, 0xf, 0x8e, 0x13, 0x2, 0x0, 0x0, 0x90, 0xf, 0x8e, 0xc, 0x2, - 0x0, 0x0, 0xf, 0x8e, 0x6, 0x2, 0x0, 0x0, 0xf, 0x8e, 0x0, 0x2, 0x0, 0x0, 0xf, 0x8e, 0xfa, 0x1, - 0x0, 0x0, 0xf, 0x8e, 0xf4, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8e, 0xec, 0x1, 0x0, 0x0, 0xf, 0x8e, - 0xe6, 0x1, 0x0, 0x0, 0xf, 0x8e, 0xe0, 0x1, 0x0, 0x0, 0xf, 0x8e, 0xda, 0x1, 0x0, 0x0, 0xf, 0x8e, - 0xd4, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8e, 0xcc, 0x1, 0x0, 0x0, 0xf, 0x8e, 0xc6, 0x1, 0x0, 0x0, - 0xf, 0x8e, 0xc0, 0x1, 0x0, 0x0, 0xf, 0x8e, 0xba, 0x1, 0x0, 0x0, 0xf, 0x8e, 0xb4, 0x1, 0x0, 0x0, - 0x66, 0x90, 0xf, 0x8e, 0xac, 0x1, 0x0, 0x0, 0xf, 0x8e, 0xa6, 0x1, 0x0, 0x0, 0xf, 0x8e, 0xa0, 0x1, - 0x0, 0x0, 0xf, 0x8e, 0x9a, 0x1, 0x0, 0x0, 0xf, 0x8e, 0x94, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8e, - 0x8c, 0x1, 0x0, 0x0, 0xf, 0x8e, 0x86, 0x1, 0x0, 0x0, 0xf, 0x8e, 0x80, 0x1, 0x0, 0x0, 0xf, 0x8e, 0x7a, - 0x1, 0x0, 0x0, 0xf, 0x8e, 0x74, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8e, 0x6c, 0x1, 0x0, 0x0, 0xf, 0x8e, - 0x66, 0x1, 0x0, 0x0, 0xf, 0x8e, 0x60, 0x1, 0x0, 0x0, 0xf, 0x8e, 0x5a, 0x1, 0x0, 0x0, 0xf, 0x8e, 0x54, - 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8e, 0x4c, 0x1, 0x0, 0x0, 0xf, 0x8e, 0x46, 0x1, 0x0, 0x0, 0xf, 0x8e, - 0x40, 0x1, 0x0, 0x0, 0xf, 0x8e, 0x3a, 0x1, 0x0, 0x0, 0xf, 0x8e, 0x34, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, - 0x8e, 0x2c, 0x1, 0x0, 0x0, 0xf, 0x8e, 0x26, 0x1, 0x0, 0x0, 0xf, 0x8e, 0x20, 0x1, 0x0, 0x0, 0xf, 0x8e, - 0x1a, 0x1, 0x0, 0x0, 0xf, 0x8e, 0x14, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8e, 0xc, 0x1, 0x0, 0x0, 0xf, - 0x8e, 0x6, 0x1, 0x0, 0x0, 0xf, 0x8e, 0x0, 0x1, 0x0, 0x0, 0xf, 0x8e, 0xfa, 0x0, 0x0, 0x0, 0xf, 0x8e, - 0xf4, 0x0, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8e, 0xec, 0x0, 0x0, 0x0, 0xf, 0x8e, 0xe6, 0x0, 0x0, 0x0, 0xf, - 0x8e, 0xe0, 0x0, 0x0, 0x0, 0xf, 0x8e, 0xda, 0x0, 0x0, 0x0, 0xf, 0x8e, 0xd4, 0x0, 0x0, 0x0, 0x66, 0x90, - 0xf, 0x8e, 0xcc, 0x0, 0x0, 0x0, 0xf, 0x8e, 0xc6, 0x0, 0x0, 0x0, 0xf, 0x8e, 0xc0, 0x0, 0x0, 0x0, 0xf, - 0x8e, 0xba, 0x0, 0x0, 0x0, 0xf, 0x8e, 0xb4, 0x0, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8e, 0xac, 0x0, 0x0, 0x0, - 0xf, 0x8e, 0xa6, 0x0, 0x0, 0x0, 0xf, 0x8e, 0xa0, 0x0, 0x0, 0x0, 0xf, 0x8e, 0x9a, 0x0, 0x0, 0x0, 0xf, - 0x8e, 0x94, 0x0, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8e, 0x8c, 0x0, 0x0, 0x0, 0xf, 0x8e, 0x86, 0x0, 0x0, 0x0, - 0xf, 0x8e, 0x80, 0x0, 0x0, 0x0, 0x7e, 0x7e, 0x7e, 0x7c, 0x7e, 0x7a, 0x7e, 0x78, 0x7e, 0x76, 0x7e, 0x74, - 0x66, 0x90, 0x7e, 0x70, 0x7e, 0x6e, 0x7e, 0x6c, 0x7e, 0x6a, 0x7e, 0x68, 0x7e, 0x66, 0x7e, 0x64, 0x7e, - 0x62, 0x7e, 0x60, 0x7e, 0x5e, 0x7e, 0x5c, 0x7e, 0x5a, 0x7e, 0x58, 0x7e, 0x56, 0x7e, 0x54, 0x66, 0x90, - 0x7e, 0x50, 0x7e, 0x4e, 0x7e, 0x4c, 0x7e, 0x4a, 0x7e, 0x48, 0x7e, 0x46, 0x7e, 0x44, 0x7e, 0x42, 0x7e, - 0x40, 0x7e, 0x3e, 0x7e, 0x3c, 0x7e, 0x3a, 0x7e, 0x38, 0x7e, 0x36, 0x7e, 0x34, 0x66, 0x90, 0x7e, 0x30, - 0x7e, 0x2e, 0x7e, 0x2c, 0x7e, 0x2a, 0x7e, 0x28, 0x7e, 0x26, 0x7e, 0x24, 0x7e, 0x22, 0x7e, 0x20, 0x7e, - 0x1e, 0x7e, 0x1c, 0x7e, 0x1a, 0x7e, 0x18, 0x7e, 0x16, 0x7e, 0x14, 0x66, 0x90, 0x7e, 0x10, 0x7e, 0xe, - 0x7e, 0xc, 0x7e, 0xa, 0x7e, 0x8, 0x7e, 0x6, 0x7e, 0x4, 0x7e, 0x2, 0x7e, 0x0, 0xc3, - }, - }, - { - backward: false, jmpInst: JLS, exp: []byte{ - 0xc3, 0xf, 0x86, 0x2b, 0x2, 0x0, 0x0, 0xf, 0x86, 0x25, 0x2, 0x0, 0x0, 0xf, 0x86, 0x1f, 0x2, 0x0, - 0x0, 0xf, 0x86, 0x19, 0x2, 0x0, 0x0, 0xf, 0x86, 0x13, 0x2, 0x0, 0x0, 0x90, 0xf, 0x86, 0xc, 0x2, - 0x0, 0x0, 0xf, 0x86, 0x6, 0x2, 0x0, 0x0, 0xf, 0x86, 0x0, 0x2, 0x0, 0x0, 0xf, 0x86, 0xfa, 0x1, - 0x0, 0x0, 0xf, 0x86, 0xf4, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x86, 0xec, 0x1, 0x0, 0x0, 0xf, 0x86, - 0xe6, 0x1, 0x0, 0x0, 0xf, 0x86, 0xe0, 0x1, 0x0, 0x0, 0xf, 0x86, 0xda, 0x1, 0x0, 0x0, 0xf, 0x86, - 0xd4, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x86, 0xcc, 0x1, 0x0, 0x0, 0xf, 0x86, 0xc6, 0x1, 0x0, 0x0, - 0xf, 0x86, 0xc0, 0x1, 0x0, 0x0, 0xf, 0x86, 0xba, 0x1, 0x0, 0x0, 0xf, 0x86, 0xb4, 0x1, 0x0, 0x0, - 0x66, 0x90, 0xf, 0x86, 0xac, 0x1, 0x0, 0x0, 0xf, 0x86, 0xa6, 0x1, 0x0, 0x0, 0xf, 0x86, 0xa0, 0x1, - 0x0, 0x0, 0xf, 0x86, 0x9a, 0x1, 0x0, 0x0, 0xf, 0x86, 0x94, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x86, - 0x8c, 0x1, 0x0, 0x0, 0xf, 0x86, 0x86, 0x1, 0x0, 0x0, 0xf, 0x86, 0x80, 0x1, 0x0, 0x0, 0xf, 0x86, 0x7a, - 0x1, 0x0, 0x0, 0xf, 0x86, 0x74, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x86, 0x6c, 0x1, 0x0, 0x0, 0xf, 0x86, - 0x66, 0x1, 0x0, 0x0, 0xf, 0x86, 0x60, 0x1, 0x0, 0x0, 0xf, 0x86, 0x5a, 0x1, 0x0, 0x0, 0xf, 0x86, 0x54, - 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x86, 0x4c, 0x1, 0x0, 0x0, 0xf, 0x86, 0x46, 0x1, 0x0, 0x0, 0xf, 0x86, - 0x40, 0x1, 0x0, 0x0, 0xf, 0x86, 0x3a, 0x1, 0x0, 0x0, 0xf, 0x86, 0x34, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, - 0x86, 0x2c, 0x1, 0x0, 0x0, 0xf, 0x86, 0x26, 0x1, 0x0, 0x0, 0xf, 0x86, 0x20, 0x1, 0x0, 0x0, 0xf, 0x86, - 0x1a, 0x1, 0x0, 0x0, 0xf, 0x86, 0x14, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x86, 0xc, 0x1, 0x0, 0x0, 0xf, - 0x86, 0x6, 0x1, 0x0, 0x0, 0xf, 0x86, 0x0, 0x1, 0x0, 0x0, 0xf, 0x86, 0xfa, 0x0, 0x0, 0x0, 0xf, 0x86, - 0xf4, 0x0, 0x0, 0x0, 0x66, 0x90, 0xf, 0x86, 0xec, 0x0, 0x0, 0x0, 0xf, 0x86, 0xe6, 0x0, 0x0, 0x0, 0xf, - 0x86, 0xe0, 0x0, 0x0, 0x0, 0xf, 0x86, 0xda, 0x0, 0x0, 0x0, 0xf, 0x86, 0xd4, 0x0, 0x0, 0x0, 0x66, 0x90, - 0xf, 0x86, 0xcc, 0x0, 0x0, 0x0, 0xf, 0x86, 0xc6, 0x0, 0x0, 0x0, 0xf, 0x86, 0xc0, 0x0, 0x0, 0x0, 0xf, - 0x86, 0xba, 0x0, 0x0, 0x0, 0xf, 0x86, 0xb4, 0x0, 0x0, 0x0, 0x66, 0x90, 0xf, 0x86, 0xac, 0x0, 0x0, 0x0, - 0xf, 0x86, 0xa6, 0x0, 0x0, 0x0, 0xf, 0x86, 0xa0, 0x0, 0x0, 0x0, 0xf, 0x86, 0x9a, 0x0, 0x0, 0x0, 0xf, - 0x86, 0x94, 0x0, 0x0, 0x0, 0x66, 0x90, 0xf, 0x86, 0x8c, 0x0, 0x0, 0x0, 0xf, 0x86, 0x86, 0x0, 0x0, 0x0, - 0xf, 0x86, 0x80, 0x0, 0x0, 0x0, 0x76, 0x7e, 0x76, 0x7c, 0x76, 0x7a, 0x76, 0x78, 0x76, 0x76, 0x76, 0x74, - 0x66, 0x90, 0x76, 0x70, 0x76, 0x6e, 0x76, 0x6c, 0x76, 0x6a, 0x76, 0x68, 0x76, 0x66, 0x76, 0x64, 0x76, - 0x62, 0x76, 0x60, 0x76, 0x5e, 0x76, 0x5c, 0x76, 0x5a, 0x76, 0x58, 0x76, 0x56, 0x76, 0x54, 0x66, 0x90, - 0x76, 0x50, 0x76, 0x4e, 0x76, 0x4c, 0x76, 0x4a, 0x76, 0x48, 0x76, 0x46, 0x76, 0x44, 0x76, 0x42, 0x76, - 0x40, 0x76, 0x3e, 0x76, 0x3c, 0x76, 0x3a, 0x76, 0x38, 0x76, 0x36, 0x76, 0x34, 0x66, 0x90, 0x76, 0x30, - 0x76, 0x2e, 0x76, 0x2c, 0x76, 0x2a, 0x76, 0x28, 0x76, 0x26, 0x76, 0x24, 0x76, 0x22, 0x76, 0x20, 0x76, - 0x1e, 0x76, 0x1c, 0x76, 0x1a, 0x76, 0x18, 0x76, 0x16, 0x76, 0x14, 0x66, 0x90, 0x76, 0x10, 0x76, 0xe, - 0x76, 0xc, 0x76, 0xa, 0x76, 0x8, 0x76, 0x6, 0x76, 0x4, 0x76, 0x2, 0x76, 0x0, 0xc3, - }, - }, - { - backward: false, jmpInst: JLT, exp: []byte{ - 0xc3, 0xf, 0x8c, 0x2b, 0x2, 0x0, 0x0, 0xf, 0x8c, 0x25, 0x2, 0x0, 0x0, 0xf, 0x8c, 0x1f, 0x2, 0x0, - 0x0, 0xf, 0x8c, 0x19, 0x2, 0x0, 0x0, 0xf, 0x8c, 0x13, 0x2, 0x0, 0x0, 0x90, 0xf, 0x8c, 0xc, 0x2, - 0x0, 0x0, 0xf, 0x8c, 0x6, 0x2, 0x0, 0x0, 0xf, 0x8c, 0x0, 0x2, 0x0, 0x0, 0xf, 0x8c, 0xfa, 0x1, - 0x0, 0x0, 0xf, 0x8c, 0xf4, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8c, 0xec, 0x1, 0x0, 0x0, 0xf, 0x8c, - 0xe6, 0x1, 0x0, 0x0, 0xf, 0x8c, 0xe0, 0x1, 0x0, 0x0, 0xf, 0x8c, 0xda, 0x1, 0x0, 0x0, 0xf, 0x8c, - 0xd4, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8c, 0xcc, 0x1, 0x0, 0x0, 0xf, 0x8c, 0xc6, 0x1, 0x0, 0x0, - 0xf, 0x8c, 0xc0, 0x1, 0x0, 0x0, 0xf, 0x8c, 0xba, 0x1, 0x0, 0x0, 0xf, 0x8c, 0xb4, 0x1, 0x0, 0x0, - 0x66, 0x90, 0xf, 0x8c, 0xac, 0x1, 0x0, 0x0, 0xf, 0x8c, 0xa6, 0x1, 0x0, 0x0, 0xf, 0x8c, 0xa0, 0x1, - 0x0, 0x0, 0xf, 0x8c, 0x9a, 0x1, 0x0, 0x0, 0xf, 0x8c, 0x94, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8c, - 0x8c, 0x1, 0x0, 0x0, 0xf, 0x8c, 0x86, 0x1, 0x0, 0x0, 0xf, 0x8c, 0x80, 0x1, 0x0, 0x0, 0xf, 0x8c, 0x7a, - 0x1, 0x0, 0x0, 0xf, 0x8c, 0x74, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8c, 0x6c, 0x1, 0x0, 0x0, 0xf, 0x8c, - 0x66, 0x1, 0x0, 0x0, 0xf, 0x8c, 0x60, 0x1, 0x0, 0x0, 0xf, 0x8c, 0x5a, 0x1, 0x0, 0x0, 0xf, 0x8c, 0x54, - 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8c, 0x4c, 0x1, 0x0, 0x0, 0xf, 0x8c, 0x46, 0x1, 0x0, 0x0, 0xf, 0x8c, - 0x40, 0x1, 0x0, 0x0, 0xf, 0x8c, 0x3a, 0x1, 0x0, 0x0, 0xf, 0x8c, 0x34, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, - 0x8c, 0x2c, 0x1, 0x0, 0x0, 0xf, 0x8c, 0x26, 0x1, 0x0, 0x0, 0xf, 0x8c, 0x20, 0x1, 0x0, 0x0, 0xf, 0x8c, - 0x1a, 0x1, 0x0, 0x0, 0xf, 0x8c, 0x14, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8c, 0xc, 0x1, 0x0, 0x0, 0xf, - 0x8c, 0x6, 0x1, 0x0, 0x0, 0xf, 0x8c, 0x0, 0x1, 0x0, 0x0, 0xf, 0x8c, 0xfa, 0x0, 0x0, 0x0, 0xf, 0x8c, - 0xf4, 0x0, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8c, 0xec, 0x0, 0x0, 0x0, 0xf, 0x8c, 0xe6, 0x0, 0x0, 0x0, 0xf, - 0x8c, 0xe0, 0x0, 0x0, 0x0, 0xf, 0x8c, 0xda, 0x0, 0x0, 0x0, 0xf, 0x8c, 0xd4, 0x0, 0x0, 0x0, 0x66, 0x90, - 0xf, 0x8c, 0xcc, 0x0, 0x0, 0x0, 0xf, 0x8c, 0xc6, 0x0, 0x0, 0x0, 0xf, 0x8c, 0xc0, 0x0, 0x0, 0x0, 0xf, - 0x8c, 0xba, 0x0, 0x0, 0x0, 0xf, 0x8c, 0xb4, 0x0, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8c, 0xac, 0x0, 0x0, 0x0, - 0xf, 0x8c, 0xa6, 0x0, 0x0, 0x0, 0xf, 0x8c, 0xa0, 0x0, 0x0, 0x0, 0xf, 0x8c, 0x9a, 0x0, 0x0, 0x0, 0xf, - 0x8c, 0x94, 0x0, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8c, 0x8c, 0x0, 0x0, 0x0, 0xf, 0x8c, 0x86, 0x0, 0x0, 0x0, - 0xf, 0x8c, 0x80, 0x0, 0x0, 0x0, 0x7c, 0x7e, 0x7c, 0x7c, 0x7c, 0x7a, 0x7c, 0x78, 0x7c, 0x76, 0x7c, 0x74, - 0x66, 0x90, 0x7c, 0x70, 0x7c, 0x6e, 0x7c, 0x6c, 0x7c, 0x6a, 0x7c, 0x68, 0x7c, 0x66, 0x7c, 0x64, 0x7c, - 0x62, 0x7c, 0x60, 0x7c, 0x5e, 0x7c, 0x5c, 0x7c, 0x5a, 0x7c, 0x58, 0x7c, 0x56, 0x7c, 0x54, 0x66, 0x90, - 0x7c, 0x50, 0x7c, 0x4e, 0x7c, 0x4c, 0x7c, 0x4a, 0x7c, 0x48, 0x7c, 0x46, 0x7c, 0x44, 0x7c, 0x42, 0x7c, - 0x40, 0x7c, 0x3e, 0x7c, 0x3c, 0x7c, 0x3a, 0x7c, 0x38, 0x7c, 0x36, 0x7c, 0x34, 0x66, 0x90, 0x7c, 0x30, - 0x7c, 0x2e, 0x7c, 0x2c, 0x7c, 0x2a, 0x7c, 0x28, 0x7c, 0x26, 0x7c, 0x24, 0x7c, 0x22, 0x7c, 0x20, 0x7c, - 0x1e, 0x7c, 0x1c, 0x7c, 0x1a, 0x7c, 0x18, 0x7c, 0x16, 0x7c, 0x14, 0x66, 0x90, 0x7c, 0x10, 0x7c, 0xe, - 0x7c, 0xc, 0x7c, 0xa, 0x7c, 0x8, 0x7c, 0x6, 0x7c, 0x4, 0x7c, 0x2, 0x7c, 0x0, 0xc3, - }, - }, - { - backward: false, jmpInst: JMI, exp: []byte{ - 0xc3, 0xf, 0x88, 0x2b, 0x2, 0x0, 0x0, 0xf, 0x88, 0x25, 0x2, 0x0, 0x0, 0xf, 0x88, 0x1f, 0x2, 0x0, - 0x0, 0xf, 0x88, 0x19, 0x2, 0x0, 0x0, 0xf, 0x88, 0x13, 0x2, 0x0, 0x0, 0x90, 0xf, 0x88, 0xc, 0x2, - 0x0, 0x0, 0xf, 0x88, 0x6, 0x2, 0x0, 0x0, 0xf, 0x88, 0x0, 0x2, 0x0, 0x0, 0xf, 0x88, 0xfa, 0x1, - 0x0, 0x0, 0xf, 0x88, 0xf4, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x88, 0xec, 0x1, 0x0, 0x0, 0xf, 0x88, - 0xe6, 0x1, 0x0, 0x0, 0xf, 0x88, 0xe0, 0x1, 0x0, 0x0, 0xf, 0x88, 0xda, 0x1, 0x0, 0x0, 0xf, 0x88, - 0xd4, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x88, 0xcc, 0x1, 0x0, 0x0, 0xf, 0x88, 0xc6, 0x1, 0x0, 0x0, - 0xf, 0x88, 0xc0, 0x1, 0x0, 0x0, 0xf, 0x88, 0xba, 0x1, 0x0, 0x0, 0xf, 0x88, 0xb4, 0x1, 0x0, 0x0, - 0x66, 0x90, 0xf, 0x88, 0xac, 0x1, 0x0, 0x0, 0xf, 0x88, 0xa6, 0x1, 0x0, 0x0, 0xf, 0x88, 0xa0, 0x1, - 0x0, 0x0, 0xf, 0x88, 0x9a, 0x1, 0x0, 0x0, 0xf, 0x88, 0x94, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x88, - 0x8c, 0x1, 0x0, 0x0, 0xf, 0x88, 0x86, 0x1, 0x0, 0x0, 0xf, 0x88, 0x80, 0x1, 0x0, 0x0, 0xf, 0x88, 0x7a, - 0x1, 0x0, 0x0, 0xf, 0x88, 0x74, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x88, 0x6c, 0x1, 0x0, 0x0, 0xf, 0x88, - 0x66, 0x1, 0x0, 0x0, 0xf, 0x88, 0x60, 0x1, 0x0, 0x0, 0xf, 0x88, 0x5a, 0x1, 0x0, 0x0, 0xf, 0x88, 0x54, - 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x88, 0x4c, 0x1, 0x0, 0x0, 0xf, 0x88, 0x46, 0x1, 0x0, 0x0, 0xf, 0x88, - 0x40, 0x1, 0x0, 0x0, 0xf, 0x88, 0x3a, 0x1, 0x0, 0x0, 0xf, 0x88, 0x34, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, - 0x88, 0x2c, 0x1, 0x0, 0x0, 0xf, 0x88, 0x26, 0x1, 0x0, 0x0, 0xf, 0x88, 0x20, 0x1, 0x0, 0x0, 0xf, 0x88, - 0x1a, 0x1, 0x0, 0x0, 0xf, 0x88, 0x14, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x88, 0xc, 0x1, 0x0, 0x0, 0xf, - 0x88, 0x6, 0x1, 0x0, 0x0, 0xf, 0x88, 0x0, 0x1, 0x0, 0x0, 0xf, 0x88, 0xfa, 0x0, 0x0, 0x0, 0xf, 0x88, - 0xf4, 0x0, 0x0, 0x0, 0x66, 0x90, 0xf, 0x88, 0xec, 0x0, 0x0, 0x0, 0xf, 0x88, 0xe6, 0x0, 0x0, 0x0, 0xf, - 0x88, 0xe0, 0x0, 0x0, 0x0, 0xf, 0x88, 0xda, 0x0, 0x0, 0x0, 0xf, 0x88, 0xd4, 0x0, 0x0, 0x0, 0x66, 0x90, - 0xf, 0x88, 0xcc, 0x0, 0x0, 0x0, 0xf, 0x88, 0xc6, 0x0, 0x0, 0x0, 0xf, 0x88, 0xc0, 0x0, 0x0, 0x0, 0xf, - 0x88, 0xba, 0x0, 0x0, 0x0, 0xf, 0x88, 0xb4, 0x0, 0x0, 0x0, 0x66, 0x90, 0xf, 0x88, 0xac, 0x0, 0x0, 0x0, - 0xf, 0x88, 0xa6, 0x0, 0x0, 0x0, 0xf, 0x88, 0xa0, 0x0, 0x0, 0x0, 0xf, 0x88, 0x9a, 0x0, 0x0, 0x0, 0xf, - 0x88, 0x94, 0x0, 0x0, 0x0, 0x66, 0x90, 0xf, 0x88, 0x8c, 0x0, 0x0, 0x0, 0xf, 0x88, 0x86, 0x0, 0x0, 0x0, - 0xf, 0x88, 0x80, 0x0, 0x0, 0x0, 0x78, 0x7e, 0x78, 0x7c, 0x78, 0x7a, 0x78, 0x78, 0x78, 0x76, 0x78, 0x74, - 0x66, 0x90, 0x78, 0x70, 0x78, 0x6e, 0x78, 0x6c, 0x78, 0x6a, 0x78, 0x68, 0x78, 0x66, 0x78, 0x64, 0x78, - 0x62, 0x78, 0x60, 0x78, 0x5e, 0x78, 0x5c, 0x78, 0x5a, 0x78, 0x58, 0x78, 0x56, 0x78, 0x54, 0x66, 0x90, - 0x78, 0x50, 0x78, 0x4e, 0x78, 0x4c, 0x78, 0x4a, 0x78, 0x48, 0x78, 0x46, 0x78, 0x44, 0x78, 0x42, 0x78, - 0x40, 0x78, 0x3e, 0x78, 0x3c, 0x78, 0x3a, 0x78, 0x38, 0x78, 0x36, 0x78, 0x34, 0x66, 0x90, 0x78, 0x30, - 0x78, 0x2e, 0x78, 0x2c, 0x78, 0x2a, 0x78, 0x28, 0x78, 0x26, 0x78, 0x24, 0x78, 0x22, 0x78, 0x20, 0x78, - 0x1e, 0x78, 0x1c, 0x78, 0x1a, 0x78, 0x18, 0x78, 0x16, 0x78, 0x14, 0x66, 0x90, 0x78, 0x10, 0x78, 0xe, - 0x78, 0xc, 0x78, 0xa, 0x78, 0x8, 0x78, 0x6, 0x78, 0x4, 0x78, 0x2, 0x78, 0x0, 0xc3, - }, - }, - { - backward: false, jmpInst: JNE, exp: []byte{ - 0xc3, 0xf, 0x85, 0x2b, 0x2, 0x0, 0x0, 0xf, 0x85, 0x25, 0x2, 0x0, 0x0, 0xf, 0x85, 0x1f, 0x2, 0x0, - 0x0, 0xf, 0x85, 0x19, 0x2, 0x0, 0x0, 0xf, 0x85, 0x13, 0x2, 0x0, 0x0, 0x90, 0xf, 0x85, 0xc, 0x2, - 0x0, 0x0, 0xf, 0x85, 0x6, 0x2, 0x0, 0x0, 0xf, 0x85, 0x0, 0x2, 0x0, 0x0, 0xf, 0x85, 0xfa, 0x1, - 0x0, 0x0, 0xf, 0x85, 0xf4, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x85, 0xec, 0x1, 0x0, 0x0, 0xf, 0x85, - 0xe6, 0x1, 0x0, 0x0, 0xf, 0x85, 0xe0, 0x1, 0x0, 0x0, 0xf, 0x85, 0xda, 0x1, 0x0, 0x0, 0xf, 0x85, - 0xd4, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x85, 0xcc, 0x1, 0x0, 0x0, 0xf, 0x85, 0xc6, 0x1, 0x0, 0x0, - 0xf, 0x85, 0xc0, 0x1, 0x0, 0x0, 0xf, 0x85, 0xba, 0x1, 0x0, 0x0, 0xf, 0x85, 0xb4, 0x1, 0x0, 0x0, - 0x66, 0x90, 0xf, 0x85, 0xac, 0x1, 0x0, 0x0, 0xf, 0x85, 0xa6, 0x1, 0x0, 0x0, 0xf, 0x85, 0xa0, 0x1, - 0x0, 0x0, 0xf, 0x85, 0x9a, 0x1, 0x0, 0x0, 0xf, 0x85, 0x94, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x85, - 0x8c, 0x1, 0x0, 0x0, 0xf, 0x85, 0x86, 0x1, 0x0, 0x0, 0xf, 0x85, 0x80, 0x1, 0x0, 0x0, 0xf, 0x85, 0x7a, - 0x1, 0x0, 0x0, 0xf, 0x85, 0x74, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x85, 0x6c, 0x1, 0x0, 0x0, 0xf, 0x85, - 0x66, 0x1, 0x0, 0x0, 0xf, 0x85, 0x60, 0x1, 0x0, 0x0, 0xf, 0x85, 0x5a, 0x1, 0x0, 0x0, 0xf, 0x85, 0x54, - 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x85, 0x4c, 0x1, 0x0, 0x0, 0xf, 0x85, 0x46, 0x1, 0x0, 0x0, 0xf, 0x85, - 0x40, 0x1, 0x0, 0x0, 0xf, 0x85, 0x3a, 0x1, 0x0, 0x0, 0xf, 0x85, 0x34, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, - 0x85, 0x2c, 0x1, 0x0, 0x0, 0xf, 0x85, 0x26, 0x1, 0x0, 0x0, 0xf, 0x85, 0x20, 0x1, 0x0, 0x0, 0xf, 0x85, - 0x1a, 0x1, 0x0, 0x0, 0xf, 0x85, 0x14, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x85, 0xc, 0x1, 0x0, 0x0, 0xf, - 0x85, 0x6, 0x1, 0x0, 0x0, 0xf, 0x85, 0x0, 0x1, 0x0, 0x0, 0xf, 0x85, 0xfa, 0x0, 0x0, 0x0, 0xf, 0x85, - 0xf4, 0x0, 0x0, 0x0, 0x66, 0x90, 0xf, 0x85, 0xec, 0x0, 0x0, 0x0, 0xf, 0x85, 0xe6, 0x0, 0x0, 0x0, 0xf, - 0x85, 0xe0, 0x0, 0x0, 0x0, 0xf, 0x85, 0xda, 0x0, 0x0, 0x0, 0xf, 0x85, 0xd4, 0x0, 0x0, 0x0, 0x66, 0x90, - 0xf, 0x85, 0xcc, 0x0, 0x0, 0x0, 0xf, 0x85, 0xc6, 0x0, 0x0, 0x0, 0xf, 0x85, 0xc0, 0x0, 0x0, 0x0, 0xf, - 0x85, 0xba, 0x0, 0x0, 0x0, 0xf, 0x85, 0xb4, 0x0, 0x0, 0x0, 0x66, 0x90, 0xf, 0x85, 0xac, 0x0, 0x0, 0x0, - 0xf, 0x85, 0xa6, 0x0, 0x0, 0x0, 0xf, 0x85, 0xa0, 0x0, 0x0, 0x0, 0xf, 0x85, 0x9a, 0x0, 0x0, 0x0, 0xf, - 0x85, 0x94, 0x0, 0x0, 0x0, 0x66, 0x90, 0xf, 0x85, 0x8c, 0x0, 0x0, 0x0, 0xf, 0x85, 0x86, 0x0, 0x0, 0x0, - 0xf, 0x85, 0x80, 0x0, 0x0, 0x0, 0x75, 0x7e, 0x75, 0x7c, 0x75, 0x7a, 0x75, 0x78, 0x75, 0x76, 0x75, 0x74, - 0x66, 0x90, 0x75, 0x70, 0x75, 0x6e, 0x75, 0x6c, 0x75, 0x6a, 0x75, 0x68, 0x75, 0x66, 0x75, 0x64, 0x75, - 0x62, 0x75, 0x60, 0x75, 0x5e, 0x75, 0x5c, 0x75, 0x5a, 0x75, 0x58, 0x75, 0x56, 0x75, 0x54, 0x66, 0x90, - 0x75, 0x50, 0x75, 0x4e, 0x75, 0x4c, 0x75, 0x4a, 0x75, 0x48, 0x75, 0x46, 0x75, 0x44, 0x75, 0x42, 0x75, - 0x40, 0x75, 0x3e, 0x75, 0x3c, 0x75, 0x3a, 0x75, 0x38, 0x75, 0x36, 0x75, 0x34, 0x66, 0x90, 0x75, 0x30, - 0x75, 0x2e, 0x75, 0x2c, 0x75, 0x2a, 0x75, 0x28, 0x75, 0x26, 0x75, 0x24, 0x75, 0x22, 0x75, 0x20, 0x75, - 0x1e, 0x75, 0x1c, 0x75, 0x1a, 0x75, 0x18, 0x75, 0x16, 0x75, 0x14, 0x66, 0x90, 0x75, 0x10, 0x75, 0xe, - 0x75, 0xc, 0x75, 0xa, 0x75, 0x8, 0x75, 0x6, 0x75, 0x4, 0x75, 0x2, 0x75, 0x0, 0xc3, - }, - }, - { - backward: false, jmpInst: JPC, exp: []byte{ - 0xc3, 0xf, 0x8b, 0x2b, 0x2, 0x0, 0x0, 0xf, 0x8b, 0x25, 0x2, 0x0, 0x0, 0xf, 0x8b, 0x1f, 0x2, 0x0, - 0x0, 0xf, 0x8b, 0x19, 0x2, 0x0, 0x0, 0xf, 0x8b, 0x13, 0x2, 0x0, 0x0, 0x90, 0xf, 0x8b, 0xc, 0x2, - 0x0, 0x0, 0xf, 0x8b, 0x6, 0x2, 0x0, 0x0, 0xf, 0x8b, 0x0, 0x2, 0x0, 0x0, 0xf, 0x8b, 0xfa, 0x1, - 0x0, 0x0, 0xf, 0x8b, 0xf4, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8b, 0xec, 0x1, 0x0, 0x0, 0xf, 0x8b, - 0xe6, 0x1, 0x0, 0x0, 0xf, 0x8b, 0xe0, 0x1, 0x0, 0x0, 0xf, 0x8b, 0xda, 0x1, 0x0, 0x0, 0xf, 0x8b, - 0xd4, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8b, 0xcc, 0x1, 0x0, 0x0, 0xf, 0x8b, 0xc6, 0x1, 0x0, 0x0, - 0xf, 0x8b, 0xc0, 0x1, 0x0, 0x0, 0xf, 0x8b, 0xba, 0x1, 0x0, 0x0, 0xf, 0x8b, 0xb4, 0x1, 0x0, 0x0, - 0x66, 0x90, 0xf, 0x8b, 0xac, 0x1, 0x0, 0x0, 0xf, 0x8b, 0xa6, 0x1, 0x0, 0x0, 0xf, 0x8b, 0xa0, 0x1, - 0x0, 0x0, 0xf, 0x8b, 0x9a, 0x1, 0x0, 0x0, 0xf, 0x8b, 0x94, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8b, - 0x8c, 0x1, 0x0, 0x0, 0xf, 0x8b, 0x86, 0x1, 0x0, 0x0, 0xf, 0x8b, 0x80, 0x1, 0x0, 0x0, 0xf, 0x8b, 0x7a, - 0x1, 0x0, 0x0, 0xf, 0x8b, 0x74, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8b, 0x6c, 0x1, 0x0, 0x0, 0xf, 0x8b, - 0x66, 0x1, 0x0, 0x0, 0xf, 0x8b, 0x60, 0x1, 0x0, 0x0, 0xf, 0x8b, 0x5a, 0x1, 0x0, 0x0, 0xf, 0x8b, 0x54, - 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8b, 0x4c, 0x1, 0x0, 0x0, 0xf, 0x8b, 0x46, 0x1, 0x0, 0x0, 0xf, 0x8b, - 0x40, 0x1, 0x0, 0x0, 0xf, 0x8b, 0x3a, 0x1, 0x0, 0x0, 0xf, 0x8b, 0x34, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, - 0x8b, 0x2c, 0x1, 0x0, 0x0, 0xf, 0x8b, 0x26, 0x1, 0x0, 0x0, 0xf, 0x8b, 0x20, 0x1, 0x0, 0x0, 0xf, 0x8b, - 0x1a, 0x1, 0x0, 0x0, 0xf, 0x8b, 0x14, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8b, 0xc, 0x1, 0x0, 0x0, 0xf, - 0x8b, 0x6, 0x1, 0x0, 0x0, 0xf, 0x8b, 0x0, 0x1, 0x0, 0x0, 0xf, 0x8b, 0xfa, 0x0, 0x0, 0x0, 0xf, 0x8b, - 0xf4, 0x0, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8b, 0xec, 0x0, 0x0, 0x0, 0xf, 0x8b, 0xe6, 0x0, 0x0, 0x0, 0xf, - 0x8b, 0xe0, 0x0, 0x0, 0x0, 0xf, 0x8b, 0xda, 0x0, 0x0, 0x0, 0xf, 0x8b, 0xd4, 0x0, 0x0, 0x0, 0x66, 0x90, - 0xf, 0x8b, 0xcc, 0x0, 0x0, 0x0, 0xf, 0x8b, 0xc6, 0x0, 0x0, 0x0, 0xf, 0x8b, 0xc0, 0x0, 0x0, 0x0, 0xf, - 0x8b, 0xba, 0x0, 0x0, 0x0, 0xf, 0x8b, 0xb4, 0x0, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8b, 0xac, 0x0, 0x0, 0x0, - 0xf, 0x8b, 0xa6, 0x0, 0x0, 0x0, 0xf, 0x8b, 0xa0, 0x0, 0x0, 0x0, 0xf, 0x8b, 0x9a, 0x0, 0x0, 0x0, 0xf, - 0x8b, 0x94, 0x0, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8b, 0x8c, 0x0, 0x0, 0x0, 0xf, 0x8b, 0x86, 0x0, 0x0, 0x0, - 0xf, 0x8b, 0x80, 0x0, 0x0, 0x0, 0x7b, 0x7e, 0x7b, 0x7c, 0x7b, 0x7a, 0x7b, 0x78, 0x7b, 0x76, 0x7b, 0x74, - 0x66, 0x90, 0x7b, 0x70, 0x7b, 0x6e, 0x7b, 0x6c, 0x7b, 0x6a, 0x7b, 0x68, 0x7b, 0x66, 0x7b, 0x64, 0x7b, - 0x62, 0x7b, 0x60, 0x7b, 0x5e, 0x7b, 0x5c, 0x7b, 0x5a, 0x7b, 0x58, 0x7b, 0x56, 0x7b, 0x54, 0x66, 0x90, - 0x7b, 0x50, 0x7b, 0x4e, 0x7b, 0x4c, 0x7b, 0x4a, 0x7b, 0x48, 0x7b, 0x46, 0x7b, 0x44, 0x7b, 0x42, 0x7b, - 0x40, 0x7b, 0x3e, 0x7b, 0x3c, 0x7b, 0x3a, 0x7b, 0x38, 0x7b, 0x36, 0x7b, 0x34, 0x66, 0x90, 0x7b, 0x30, - 0x7b, 0x2e, 0x7b, 0x2c, 0x7b, 0x2a, 0x7b, 0x28, 0x7b, 0x26, 0x7b, 0x24, 0x7b, 0x22, 0x7b, 0x20, 0x7b, - 0x1e, 0x7b, 0x1c, 0x7b, 0x1a, 0x7b, 0x18, 0x7b, 0x16, 0x7b, 0x14, 0x66, 0x90, 0x7b, 0x10, 0x7b, 0xe, - 0x7b, 0xc, 0x7b, 0xa, 0x7b, 0x8, 0x7b, 0x6, 0x7b, 0x4, 0x7b, 0x2, 0x7b, 0x0, 0xc3, - }, - }, - { - backward: false, jmpInst: JPS, exp: []byte{ - 0xc3, 0xf, 0x8a, 0x2b, 0x2, 0x0, 0x0, 0xf, 0x8a, 0x25, 0x2, 0x0, 0x0, 0xf, 0x8a, 0x1f, 0x2, 0x0, - 0x0, 0xf, 0x8a, 0x19, 0x2, 0x0, 0x0, 0xf, 0x8a, 0x13, 0x2, 0x0, 0x0, 0x90, 0xf, 0x8a, 0xc, 0x2, - 0x0, 0x0, 0xf, 0x8a, 0x6, 0x2, 0x0, 0x0, 0xf, 0x8a, 0x0, 0x2, 0x0, 0x0, 0xf, 0x8a, 0xfa, 0x1, - 0x0, 0x0, 0xf, 0x8a, 0xf4, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8a, 0xec, 0x1, 0x0, 0x0, 0xf, 0x8a, - 0xe6, 0x1, 0x0, 0x0, 0xf, 0x8a, 0xe0, 0x1, 0x0, 0x0, 0xf, 0x8a, 0xda, 0x1, 0x0, 0x0, 0xf, 0x8a, - 0xd4, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8a, 0xcc, 0x1, 0x0, 0x0, 0xf, 0x8a, 0xc6, 0x1, 0x0, 0x0, - 0xf, 0x8a, 0xc0, 0x1, 0x0, 0x0, 0xf, 0x8a, 0xba, 0x1, 0x0, 0x0, 0xf, 0x8a, 0xb4, 0x1, 0x0, 0x0, - 0x66, 0x90, 0xf, 0x8a, 0xac, 0x1, 0x0, 0x0, 0xf, 0x8a, 0xa6, 0x1, 0x0, 0x0, 0xf, 0x8a, 0xa0, 0x1, - 0x0, 0x0, 0xf, 0x8a, 0x9a, 0x1, 0x0, 0x0, 0xf, 0x8a, 0x94, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8a, - 0x8c, 0x1, 0x0, 0x0, 0xf, 0x8a, 0x86, 0x1, 0x0, 0x0, 0xf, 0x8a, 0x80, 0x1, 0x0, 0x0, 0xf, 0x8a, 0x7a, - 0x1, 0x0, 0x0, 0xf, 0x8a, 0x74, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8a, 0x6c, 0x1, 0x0, 0x0, 0xf, 0x8a, - 0x66, 0x1, 0x0, 0x0, 0xf, 0x8a, 0x60, 0x1, 0x0, 0x0, 0xf, 0x8a, 0x5a, 0x1, 0x0, 0x0, 0xf, 0x8a, 0x54, - 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8a, 0x4c, 0x1, 0x0, 0x0, 0xf, 0x8a, 0x46, 0x1, 0x0, 0x0, 0xf, 0x8a, - 0x40, 0x1, 0x0, 0x0, 0xf, 0x8a, 0x3a, 0x1, 0x0, 0x0, 0xf, 0x8a, 0x34, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, - 0x8a, 0x2c, 0x1, 0x0, 0x0, 0xf, 0x8a, 0x26, 0x1, 0x0, 0x0, 0xf, 0x8a, 0x20, 0x1, 0x0, 0x0, 0xf, 0x8a, - 0x1a, 0x1, 0x0, 0x0, 0xf, 0x8a, 0x14, 0x1, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8a, 0xc, 0x1, 0x0, 0x0, 0xf, - 0x8a, 0x6, 0x1, 0x0, 0x0, 0xf, 0x8a, 0x0, 0x1, 0x0, 0x0, 0xf, 0x8a, 0xfa, 0x0, 0x0, 0x0, 0xf, 0x8a, - 0xf4, 0x0, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8a, 0xec, 0x0, 0x0, 0x0, 0xf, 0x8a, 0xe6, 0x0, 0x0, 0x0, 0xf, - 0x8a, 0xe0, 0x0, 0x0, 0x0, 0xf, 0x8a, 0xda, 0x0, 0x0, 0x0, 0xf, 0x8a, 0xd4, 0x0, 0x0, 0x0, 0x66, 0x90, - 0xf, 0x8a, 0xcc, 0x0, 0x0, 0x0, 0xf, 0x8a, 0xc6, 0x0, 0x0, 0x0, 0xf, 0x8a, 0xc0, 0x0, 0x0, 0x0, 0xf, - 0x8a, 0xba, 0x0, 0x0, 0x0, 0xf, 0x8a, 0xb4, 0x0, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8a, 0xac, 0x0, 0x0, 0x0, - 0xf, 0x8a, 0xa6, 0x0, 0x0, 0x0, 0xf, 0x8a, 0xa0, 0x0, 0x0, 0x0, 0xf, 0x8a, 0x9a, 0x0, 0x0, 0x0, 0xf, - 0x8a, 0x94, 0x0, 0x0, 0x0, 0x66, 0x90, 0xf, 0x8a, 0x8c, 0x0, 0x0, 0x0, 0xf, 0x8a, 0x86, 0x0, 0x0, 0x0, - 0xf, 0x8a, 0x80, 0x0, 0x0, 0x0, 0x7a, 0x7e, 0x7a, 0x7c, 0x7a, 0x7a, 0x7a, 0x78, 0x7a, 0x76, 0x7a, 0x74, - 0x66, 0x90, 0x7a, 0x70, 0x7a, 0x6e, 0x7a, 0x6c, 0x7a, 0x6a, 0x7a, 0x68, 0x7a, 0x66, 0x7a, 0x64, 0x7a, - 0x62, 0x7a, 0x60, 0x7a, 0x5e, 0x7a, 0x5c, 0x7a, 0x5a, 0x7a, 0x58, 0x7a, 0x56, 0x7a, 0x54, 0x66, 0x90, - 0x7a, 0x50, 0x7a, 0x4e, 0x7a, 0x4c, 0x7a, 0x4a, 0x7a, 0x48, 0x7a, 0x46, 0x7a, 0x44, 0x7a, 0x42, 0x7a, - 0x40, 0x7a, 0x3e, 0x7a, 0x3c, 0x7a, 0x3a, 0x7a, 0x38, 0x7a, 0x36, 0x7a, 0x34, 0x66, 0x90, 0x7a, 0x30, - 0x7a, 0x2e, 0x7a, 0x2c, 0x7a, 0x2a, 0x7a, 0x28, 0x7a, 0x26, 0x7a, 0x24, 0x7a, 0x22, 0x7a, 0x20, 0x7a, - 0x1e, 0x7a, 0x1c, 0x7a, 0x1a, 0x7a, 0x18, 0x7a, 0x16, 0x7a, 0x14, 0x66, 0x90, 0x7a, 0x10, 0x7a, 0xe, - 0x7a, 0xc, 0x7a, 0xa, 0x7a, 0x8, 0x7a, 0x6, 0x7a, 0x4, 0x7a, 0x2, 0x7a, 0x0, 0xc3, - }, - }, - } - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - for _, tc := range tests { - t.Run(fmt.Sprintf("%s/backward=%v", InstructionName(tc.jmpInst), tc.backward), func(t *testing.T) { - a := NewAssembler() - - head := a.CompileStandAlone(RET) - var jmps []asm.Node - for i := 0; i < 128; i++ { // Large enough so that this includes long jump. - jmps = append(jmps, a.CompileJump(tc.jmpInst)) - } - tail := a.CompileStandAlone(RET) - - for _, jmp := range jmps { - if tc.backward { - jmp.AssignJumpTarget(head) - } else { - jmp.AssignJumpTarget(tail) - } - } - - buf := code.NextCodeSection() - err := a.Assemble(buf) - require.NoError(t, err) - - actual := buf.Bytes() - require.Equal(t, tc.exp, actual) - }) - } - }) -} diff --git a/internal/asm/amd64/impl_7_test.go b/internal/asm/amd64/impl_7_test.go deleted file mode 100644 index ed012fcb79..0000000000 --- a/internal/asm/amd64/impl_7_test.go +++ /dev/null @@ -1,633 +0,0 @@ -package amd64 - -import ( - "fmt" - "math" - "testing" - - "github.com/tetratelabs/wazero/internal/asm" - "github.com/tetratelabs/wazero/internal/testing/require" -) - -func TestAssemblerImpl_Assemble_NOPPadding_fusedJumps(t *testing.T) { - tests := []struct { - name string - setupFn func(assembler Assembler) - jmpInstToExpectedBytes map[string][]byte - }{ - { - name: "CMPL(register to const)", - setupFn: func(assembler Assembler) { - assembler.CompileRegisterToConst(CMPL, RegAX, math.MaxInt16) - }, - jmpInstToExpectedBytes: map[string][]uint8{ - "JCC": {0x3d, 0xff, 0x7f, 0x0, 0x0, 0x73, 0x55, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x73, 0x4e, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x73, 0x47, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x73, 0x40, 0xf, 0x1f, 0x40, 0x0, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x73, 0x35, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x73, 0x2e, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x73, 0x27, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x73, 0x20, 0xf, 0x1f, 0x40, 0x0, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x73, 0x15, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x73, 0xe, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x73, 0x7, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x73, 0x0, 0xc3}, - "JCS": {0x3d, 0xff, 0x7f, 0x0, 0x0, 0x72, 0x55, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x72, 0x4e, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x72, 0x47, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x72, 0x40, 0xf, 0x1f, 0x40, 0x0, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x72, 0x35, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x72, 0x2e, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x72, 0x27, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x72, 0x20, 0xf, 0x1f, 0x40, 0x0, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x72, 0x15, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x72, 0xe, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x72, 0x7, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x72, 0x0, 0xc3}, - "JEQ": {0x3d, 0xff, 0x7f, 0x0, 0x0, 0x74, 0x55, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x74, 0x4e, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x74, 0x47, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x74, 0x40, 0xf, 0x1f, 0x40, 0x0, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x74, 0x35, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x74, 0x2e, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x74, 0x27, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x74, 0x20, 0xf, 0x1f, 0x40, 0x0, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x74, 0x15, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x74, 0xe, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x74, 0x7, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x74, 0x0, 0xc3}, - "JGE": {0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7d, 0x55, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7d, 0x4e, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7d, 0x47, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7d, 0x40, 0xf, 0x1f, 0x40, 0x0, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7d, 0x35, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7d, 0x2e, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7d, 0x27, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7d, 0x20, 0xf, 0x1f, 0x40, 0x0, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7d, 0x15, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7d, 0xe, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7d, 0x7, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7d, 0x0, 0xc3}, - "JGT": {0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7f, 0x55, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7f, 0x4e, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7f, 0x47, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7f, 0x40, 0xf, 0x1f, 0x40, 0x0, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7f, 0x35, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7f, 0x2e, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7f, 0x27, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7f, 0x20, 0xf, 0x1f, 0x40, 0x0, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7f, 0x15, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7f, 0xe, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7f, 0x7, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7f, 0x0, 0xc3}, - "JHI": {0x3d, 0xff, 0x7f, 0x0, 0x0, 0x77, 0x55, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x77, 0x4e, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x77, 0x47, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x77, 0x40, 0xf, 0x1f, 0x40, 0x0, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x77, 0x35, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x77, 0x2e, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x77, 0x27, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x77, 0x20, 0xf, 0x1f, 0x40, 0x0, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x77, 0x15, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x77, 0xe, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x77, 0x7, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x77, 0x0, 0xc3}, - "JLE": {0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7e, 0x55, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7e, 0x4e, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7e, 0x47, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7e, 0x40, 0xf, 0x1f, 0x40, 0x0, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7e, 0x35, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7e, 0x2e, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7e, 0x27, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7e, 0x20, 0xf, 0x1f, 0x40, 0x0, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7e, 0x15, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7e, 0xe, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7e, 0x7, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7e, 0x0, 0xc3}, - "JLS": {0x3d, 0xff, 0x7f, 0x0, 0x0, 0x76, 0x55, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x76, 0x4e, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x76, 0x47, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x76, 0x40, 0xf, 0x1f, 0x40, 0x0, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x76, 0x35, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x76, 0x2e, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x76, 0x27, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x76, 0x20, 0xf, 0x1f, 0x40, 0x0, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x76, 0x15, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x76, 0xe, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x76, 0x7, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x76, 0x0, 0xc3}, - "JLT": {0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7c, 0x55, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7c, 0x4e, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7c, 0x47, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7c, 0x40, 0xf, 0x1f, 0x40, 0x0, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7c, 0x35, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7c, 0x2e, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7c, 0x27, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7c, 0x20, 0xf, 0x1f, 0x40, 0x0, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7c, 0x15, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7c, 0xe, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7c, 0x7, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7c, 0x0, 0xc3}, - "JMI": {0x3d, 0xff, 0x7f, 0x0, 0x0, 0x78, 0x4d, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x78, 0x46, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x78, 0x3f, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x78, 0x38, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x78, 0x31, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x78, 0x2a, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x78, 0x23, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x78, 0x1c, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x78, 0x15, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x78, 0xe, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x78, 0x7, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x78, 0x0, 0xc3}, - "JNE": {0x3d, 0xff, 0x7f, 0x0, 0x0, 0x75, 0x55, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x75, 0x4e, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x75, 0x47, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x75, 0x40, 0xf, 0x1f, 0x40, 0x0, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x75, 0x35, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x75, 0x2e, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x75, 0x27, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x75, 0x20, 0xf, 0x1f, 0x40, 0x0, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x75, 0x15, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x75, 0xe, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x75, 0x7, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x75, 0x0, 0xc3}, - "JPC": {0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7b, 0x4d, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7b, 0x46, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7b, 0x3f, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7b, 0x38, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7b, 0x31, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7b, 0x2a, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7b, 0x23, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7b, 0x1c, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7b, 0x15, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7b, 0xe, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7b, 0x7, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7b, 0x0, 0xc3}, - "JPS": {0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7a, 0x4d, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7a, 0x46, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7a, 0x3f, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7a, 0x38, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7a, 0x31, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7a, 0x2a, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7a, 0x23, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7a, 0x1c, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7a, 0x15, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7a, 0xe, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7a, 0x7, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7a, 0x0, 0xc3}, - }, - }, - { - name: "CMPL(memory to const)", - setupFn: func(assembler Assembler) { - assembler.CompileMemoryToConst(CMPL, RegAX, 1, 10) - }, - jmpInstToExpectedBytes: map[string][]uint8{ - "JCC": {0x83, 0x78, 0x1, 0xa, 0x73, 0x42, 0x83, 0x78, 0x1, 0xa, 0x73, 0x3c, 0x83, 0x78, 0x1, 0xa, 0x73, 0x36, 0x83, 0x78, 0x1, 0xa, 0x73, 0x30, 0x83, 0x78, 0x1, 0xa, 0x73, 0x2a, 0x83, 0x78, 0x1, 0xa, 0x73, 0x24, 0x83, 0x78, 0x1, 0xa, 0x73, 0x1e, 0x83, 0x78, 0x1, 0xa, 0x73, 0x18, 0x83, 0x78, 0x1, 0xa, 0x73, 0x12, 0x83, 0x78, 0x1, 0xa, 0x73, 0xc, 0x83, 0x78, 0x1, 0xa, 0x73, 0x6, 0x83, 0x78, 0x1, 0xa, 0x73, 0x0, 0xc3}, - "JCS": {0x83, 0x78, 0x1, 0xa, 0x72, 0x42, 0x83, 0x78, 0x1, 0xa, 0x72, 0x3c, 0x83, 0x78, 0x1, 0xa, 0x72, 0x36, 0x83, 0x78, 0x1, 0xa, 0x72, 0x30, 0x83, 0x78, 0x1, 0xa, 0x72, 0x2a, 0x83, 0x78, 0x1, 0xa, 0x72, 0x24, 0x83, 0x78, 0x1, 0xa, 0x72, 0x1e, 0x83, 0x78, 0x1, 0xa, 0x72, 0x18, 0x83, 0x78, 0x1, 0xa, 0x72, 0x12, 0x83, 0x78, 0x1, 0xa, 0x72, 0xc, 0x83, 0x78, 0x1, 0xa, 0x72, 0x6, 0x83, 0x78, 0x1, 0xa, 0x72, 0x0, 0xc3}, - "JEQ": {0x83, 0x78, 0x1, 0xa, 0x74, 0x42, 0x83, 0x78, 0x1, 0xa, 0x74, 0x3c, 0x83, 0x78, 0x1, 0xa, 0x74, 0x36, 0x83, 0x78, 0x1, 0xa, 0x74, 0x30, 0x83, 0x78, 0x1, 0xa, 0x74, 0x2a, 0x83, 0x78, 0x1, 0xa, 0x74, 0x24, 0x83, 0x78, 0x1, 0xa, 0x74, 0x1e, 0x83, 0x78, 0x1, 0xa, 0x74, 0x18, 0x83, 0x78, 0x1, 0xa, 0x74, 0x12, 0x83, 0x78, 0x1, 0xa, 0x74, 0xc, 0x83, 0x78, 0x1, 0xa, 0x74, 0x6, 0x83, 0x78, 0x1, 0xa, 0x74, 0x0, 0xc3}, - "JGE": {0x83, 0x78, 0x1, 0xa, 0x7d, 0x42, 0x83, 0x78, 0x1, 0xa, 0x7d, 0x3c, 0x83, 0x78, 0x1, 0xa, 0x7d, 0x36, 0x83, 0x78, 0x1, 0xa, 0x7d, 0x30, 0x83, 0x78, 0x1, 0xa, 0x7d, 0x2a, 0x83, 0x78, 0x1, 0xa, 0x7d, 0x24, 0x83, 0x78, 0x1, 0xa, 0x7d, 0x1e, 0x83, 0x78, 0x1, 0xa, 0x7d, 0x18, 0x83, 0x78, 0x1, 0xa, 0x7d, 0x12, 0x83, 0x78, 0x1, 0xa, 0x7d, 0xc, 0x83, 0x78, 0x1, 0xa, 0x7d, 0x6, 0x83, 0x78, 0x1, 0xa, 0x7d, 0x0, 0xc3}, - "JGT": {0x83, 0x78, 0x1, 0xa, 0x7f, 0x42, 0x83, 0x78, 0x1, 0xa, 0x7f, 0x3c, 0x83, 0x78, 0x1, 0xa, 0x7f, 0x36, 0x83, 0x78, 0x1, 0xa, 0x7f, 0x30, 0x83, 0x78, 0x1, 0xa, 0x7f, 0x2a, 0x83, 0x78, 0x1, 0xa, 0x7f, 0x24, 0x83, 0x78, 0x1, 0xa, 0x7f, 0x1e, 0x83, 0x78, 0x1, 0xa, 0x7f, 0x18, 0x83, 0x78, 0x1, 0xa, 0x7f, 0x12, 0x83, 0x78, 0x1, 0xa, 0x7f, 0xc, 0x83, 0x78, 0x1, 0xa, 0x7f, 0x6, 0x83, 0x78, 0x1, 0xa, 0x7f, 0x0, 0xc3}, - "JHI": {0x83, 0x78, 0x1, 0xa, 0x77, 0x42, 0x83, 0x78, 0x1, 0xa, 0x77, 0x3c, 0x83, 0x78, 0x1, 0xa, 0x77, 0x36, 0x83, 0x78, 0x1, 0xa, 0x77, 0x30, 0x83, 0x78, 0x1, 0xa, 0x77, 0x2a, 0x83, 0x78, 0x1, 0xa, 0x77, 0x24, 0x83, 0x78, 0x1, 0xa, 0x77, 0x1e, 0x83, 0x78, 0x1, 0xa, 0x77, 0x18, 0x83, 0x78, 0x1, 0xa, 0x77, 0x12, 0x83, 0x78, 0x1, 0xa, 0x77, 0xc, 0x83, 0x78, 0x1, 0xa, 0x77, 0x6, 0x83, 0x78, 0x1, 0xa, 0x77, 0x0, 0xc3}, - "JLE": {0x83, 0x78, 0x1, 0xa, 0x7e, 0x42, 0x83, 0x78, 0x1, 0xa, 0x7e, 0x3c, 0x83, 0x78, 0x1, 0xa, 0x7e, 0x36, 0x83, 0x78, 0x1, 0xa, 0x7e, 0x30, 0x83, 0x78, 0x1, 0xa, 0x7e, 0x2a, 0x83, 0x78, 0x1, 0xa, 0x7e, 0x24, 0x83, 0x78, 0x1, 0xa, 0x7e, 0x1e, 0x83, 0x78, 0x1, 0xa, 0x7e, 0x18, 0x83, 0x78, 0x1, 0xa, 0x7e, 0x12, 0x83, 0x78, 0x1, 0xa, 0x7e, 0xc, 0x83, 0x78, 0x1, 0xa, 0x7e, 0x6, 0x83, 0x78, 0x1, 0xa, 0x7e, 0x0, 0xc3}, - "JLS": {0x83, 0x78, 0x1, 0xa, 0x76, 0x42, 0x83, 0x78, 0x1, 0xa, 0x76, 0x3c, 0x83, 0x78, 0x1, 0xa, 0x76, 0x36, 0x83, 0x78, 0x1, 0xa, 0x76, 0x30, 0x83, 0x78, 0x1, 0xa, 0x76, 0x2a, 0x83, 0x78, 0x1, 0xa, 0x76, 0x24, 0x83, 0x78, 0x1, 0xa, 0x76, 0x1e, 0x83, 0x78, 0x1, 0xa, 0x76, 0x18, 0x83, 0x78, 0x1, 0xa, 0x76, 0x12, 0x83, 0x78, 0x1, 0xa, 0x76, 0xc, 0x83, 0x78, 0x1, 0xa, 0x76, 0x6, 0x83, 0x78, 0x1, 0xa, 0x76, 0x0, 0xc3}, - "JLT": {0x83, 0x78, 0x1, 0xa, 0x7c, 0x42, 0x83, 0x78, 0x1, 0xa, 0x7c, 0x3c, 0x83, 0x78, 0x1, 0xa, 0x7c, 0x36, 0x83, 0x78, 0x1, 0xa, 0x7c, 0x30, 0x83, 0x78, 0x1, 0xa, 0x7c, 0x2a, 0x83, 0x78, 0x1, 0xa, 0x7c, 0x24, 0x83, 0x78, 0x1, 0xa, 0x7c, 0x1e, 0x83, 0x78, 0x1, 0xa, 0x7c, 0x18, 0x83, 0x78, 0x1, 0xa, 0x7c, 0x12, 0x83, 0x78, 0x1, 0xa, 0x7c, 0xc, 0x83, 0x78, 0x1, 0xa, 0x7c, 0x6, 0x83, 0x78, 0x1, 0xa, 0x7c, 0x0, 0xc3}, - "JMI": {0x83, 0x78, 0x1, 0xa, 0x78, 0x42, 0x83, 0x78, 0x1, 0xa, 0x78, 0x3c, 0x83, 0x78, 0x1, 0xa, 0x78, 0x36, 0x83, 0x78, 0x1, 0xa, 0x78, 0x30, 0x83, 0x78, 0x1, 0xa, 0x78, 0x2a, 0x83, 0x78, 0x1, 0xa, 0x78, 0x24, 0x83, 0x78, 0x1, 0xa, 0x78, 0x1e, 0x83, 0x78, 0x1, 0xa, 0x78, 0x18, 0x83, 0x78, 0x1, 0xa, 0x78, 0x12, 0x83, 0x78, 0x1, 0xa, 0x78, 0xc, 0x83, 0x78, 0x1, 0xa, 0x78, 0x6, 0x83, 0x78, 0x1, 0xa, 0x78, 0x0, 0xc3}, - "JNE": {0x83, 0x78, 0x1, 0xa, 0x75, 0x42, 0x83, 0x78, 0x1, 0xa, 0x75, 0x3c, 0x83, 0x78, 0x1, 0xa, 0x75, 0x36, 0x83, 0x78, 0x1, 0xa, 0x75, 0x30, 0x83, 0x78, 0x1, 0xa, 0x75, 0x2a, 0x83, 0x78, 0x1, 0xa, 0x75, 0x24, 0x83, 0x78, 0x1, 0xa, 0x75, 0x1e, 0x83, 0x78, 0x1, 0xa, 0x75, 0x18, 0x83, 0x78, 0x1, 0xa, 0x75, 0x12, 0x83, 0x78, 0x1, 0xa, 0x75, 0xc, 0x83, 0x78, 0x1, 0xa, 0x75, 0x6, 0x83, 0x78, 0x1, 0xa, 0x75, 0x0, 0xc3}, - "JPC": {0x83, 0x78, 0x1, 0xa, 0x7b, 0x42, 0x83, 0x78, 0x1, 0xa, 0x7b, 0x3c, 0x83, 0x78, 0x1, 0xa, 0x7b, 0x36, 0x83, 0x78, 0x1, 0xa, 0x7b, 0x30, 0x83, 0x78, 0x1, 0xa, 0x7b, 0x2a, 0x83, 0x78, 0x1, 0xa, 0x7b, 0x24, 0x83, 0x78, 0x1, 0xa, 0x7b, 0x1e, 0x83, 0x78, 0x1, 0xa, 0x7b, 0x18, 0x83, 0x78, 0x1, 0xa, 0x7b, 0x12, 0x83, 0x78, 0x1, 0xa, 0x7b, 0xc, 0x83, 0x78, 0x1, 0xa, 0x7b, 0x6, 0x83, 0x78, 0x1, 0xa, 0x7b, 0x0, 0xc3}, - "JPS": {0x83, 0x78, 0x1, 0xa, 0x7a, 0x42, 0x83, 0x78, 0x1, 0xa, 0x7a, 0x3c, 0x83, 0x78, 0x1, 0xa, 0x7a, 0x36, 0x83, 0x78, 0x1, 0xa, 0x7a, 0x30, 0x83, 0x78, 0x1, 0xa, 0x7a, 0x2a, 0x83, 0x78, 0x1, 0xa, 0x7a, 0x24, 0x83, 0x78, 0x1, 0xa, 0x7a, 0x1e, 0x83, 0x78, 0x1, 0xa, 0x7a, 0x18, 0x83, 0x78, 0x1, 0xa, 0x7a, 0x12, 0x83, 0x78, 0x1, 0xa, 0x7a, 0xc, 0x83, 0x78, 0x1, 0xa, 0x7a, 0x6, 0x83, 0x78, 0x1, 0xa, 0x7a, 0x0, 0xc3}, - }, - }, - { - name: "CMPL(register to register)", - setupFn: func(assembler Assembler) { - assembler.CompileRegisterToRegister(CMPL, RegR14, RegR10) - }, - jmpInstToExpectedBytes: map[string][]uint8{ - "JCC": {0x45, 0x39, 0xd6, 0x73, 0x39, 0x45, 0x39, 0xd6, 0x73, 0x34, 0x45, 0x39, 0xd6, 0x73, 0x2f, 0x45, 0x39, 0xd6, 0x73, 0x2a, 0x45, 0x39, 0xd6, 0x73, 0x25, 0x45, 0x39, 0xd6, 0x73, 0x20, 0x66, 0x90, 0x45, 0x39, 0xd6, 0x73, 0x19, 0x45, 0x39, 0xd6, 0x73, 0x14, 0x45, 0x39, 0xd6, 0x73, 0xf, 0x45, 0x39, 0xd6, 0x73, 0xa, 0x45, 0x39, 0xd6, 0x73, 0x5, 0x45, 0x39, 0xd6, 0x73, 0x0, 0xc3}, - "JCS": {0x45, 0x39, 0xd6, 0x72, 0x39, 0x45, 0x39, 0xd6, 0x72, 0x34, 0x45, 0x39, 0xd6, 0x72, 0x2f, 0x45, 0x39, 0xd6, 0x72, 0x2a, 0x45, 0x39, 0xd6, 0x72, 0x25, 0x45, 0x39, 0xd6, 0x72, 0x20, 0x66, 0x90, 0x45, 0x39, 0xd6, 0x72, 0x19, 0x45, 0x39, 0xd6, 0x72, 0x14, 0x45, 0x39, 0xd6, 0x72, 0xf, 0x45, 0x39, 0xd6, 0x72, 0xa, 0x45, 0x39, 0xd6, 0x72, 0x5, 0x45, 0x39, 0xd6, 0x72, 0x0, 0xc3}, - "JEQ": {0x45, 0x39, 0xd6, 0x74, 0x39, 0x45, 0x39, 0xd6, 0x74, 0x34, 0x45, 0x39, 0xd6, 0x74, 0x2f, 0x45, 0x39, 0xd6, 0x74, 0x2a, 0x45, 0x39, 0xd6, 0x74, 0x25, 0x45, 0x39, 0xd6, 0x74, 0x20, 0x66, 0x90, 0x45, 0x39, 0xd6, 0x74, 0x19, 0x45, 0x39, 0xd6, 0x74, 0x14, 0x45, 0x39, 0xd6, 0x74, 0xf, 0x45, 0x39, 0xd6, 0x74, 0xa, 0x45, 0x39, 0xd6, 0x74, 0x5, 0x45, 0x39, 0xd6, 0x74, 0x0, 0xc3}, - "JGE": {0x45, 0x39, 0xd6, 0x7d, 0x39, 0x45, 0x39, 0xd6, 0x7d, 0x34, 0x45, 0x39, 0xd6, 0x7d, 0x2f, 0x45, 0x39, 0xd6, 0x7d, 0x2a, 0x45, 0x39, 0xd6, 0x7d, 0x25, 0x45, 0x39, 0xd6, 0x7d, 0x20, 0x66, 0x90, 0x45, 0x39, 0xd6, 0x7d, 0x19, 0x45, 0x39, 0xd6, 0x7d, 0x14, 0x45, 0x39, 0xd6, 0x7d, 0xf, 0x45, 0x39, 0xd6, 0x7d, 0xa, 0x45, 0x39, 0xd6, 0x7d, 0x5, 0x45, 0x39, 0xd6, 0x7d, 0x0, 0xc3}, - "JGT": {0x45, 0x39, 0xd6, 0x7f, 0x39, 0x45, 0x39, 0xd6, 0x7f, 0x34, 0x45, 0x39, 0xd6, 0x7f, 0x2f, 0x45, 0x39, 0xd6, 0x7f, 0x2a, 0x45, 0x39, 0xd6, 0x7f, 0x25, 0x45, 0x39, 0xd6, 0x7f, 0x20, 0x66, 0x90, 0x45, 0x39, 0xd6, 0x7f, 0x19, 0x45, 0x39, 0xd6, 0x7f, 0x14, 0x45, 0x39, 0xd6, 0x7f, 0xf, 0x45, 0x39, 0xd6, 0x7f, 0xa, 0x45, 0x39, 0xd6, 0x7f, 0x5, 0x45, 0x39, 0xd6, 0x7f, 0x0, 0xc3}, - "JHI": {0x45, 0x39, 0xd6, 0x77, 0x39, 0x45, 0x39, 0xd6, 0x77, 0x34, 0x45, 0x39, 0xd6, 0x77, 0x2f, 0x45, 0x39, 0xd6, 0x77, 0x2a, 0x45, 0x39, 0xd6, 0x77, 0x25, 0x45, 0x39, 0xd6, 0x77, 0x20, 0x66, 0x90, 0x45, 0x39, 0xd6, 0x77, 0x19, 0x45, 0x39, 0xd6, 0x77, 0x14, 0x45, 0x39, 0xd6, 0x77, 0xf, 0x45, 0x39, 0xd6, 0x77, 0xa, 0x45, 0x39, 0xd6, 0x77, 0x5, 0x45, 0x39, 0xd6, 0x77, 0x0, 0xc3}, - "JLE": {0x45, 0x39, 0xd6, 0x7e, 0x39, 0x45, 0x39, 0xd6, 0x7e, 0x34, 0x45, 0x39, 0xd6, 0x7e, 0x2f, 0x45, 0x39, 0xd6, 0x7e, 0x2a, 0x45, 0x39, 0xd6, 0x7e, 0x25, 0x45, 0x39, 0xd6, 0x7e, 0x20, 0x66, 0x90, 0x45, 0x39, 0xd6, 0x7e, 0x19, 0x45, 0x39, 0xd6, 0x7e, 0x14, 0x45, 0x39, 0xd6, 0x7e, 0xf, 0x45, 0x39, 0xd6, 0x7e, 0xa, 0x45, 0x39, 0xd6, 0x7e, 0x5, 0x45, 0x39, 0xd6, 0x7e, 0x0, 0xc3}, - "JLS": {0x45, 0x39, 0xd6, 0x76, 0x39, 0x45, 0x39, 0xd6, 0x76, 0x34, 0x45, 0x39, 0xd6, 0x76, 0x2f, 0x45, 0x39, 0xd6, 0x76, 0x2a, 0x45, 0x39, 0xd6, 0x76, 0x25, 0x45, 0x39, 0xd6, 0x76, 0x20, 0x66, 0x90, 0x45, 0x39, 0xd6, 0x76, 0x19, 0x45, 0x39, 0xd6, 0x76, 0x14, 0x45, 0x39, 0xd6, 0x76, 0xf, 0x45, 0x39, 0xd6, 0x76, 0xa, 0x45, 0x39, 0xd6, 0x76, 0x5, 0x45, 0x39, 0xd6, 0x76, 0x0, 0xc3}, - "JLT": {0x45, 0x39, 0xd6, 0x7c, 0x39, 0x45, 0x39, 0xd6, 0x7c, 0x34, 0x45, 0x39, 0xd6, 0x7c, 0x2f, 0x45, 0x39, 0xd6, 0x7c, 0x2a, 0x45, 0x39, 0xd6, 0x7c, 0x25, 0x45, 0x39, 0xd6, 0x7c, 0x20, 0x66, 0x90, 0x45, 0x39, 0xd6, 0x7c, 0x19, 0x45, 0x39, 0xd6, 0x7c, 0x14, 0x45, 0x39, 0xd6, 0x7c, 0xf, 0x45, 0x39, 0xd6, 0x7c, 0xa, 0x45, 0x39, 0xd6, 0x7c, 0x5, 0x45, 0x39, 0xd6, 0x7c, 0x0, 0xc3}, - "JMI": {0x45, 0x39, 0xd6, 0x78, 0x37, 0x45, 0x39, 0xd6, 0x78, 0x32, 0x45, 0x39, 0xd6, 0x78, 0x2d, 0x45, 0x39, 0xd6, 0x78, 0x28, 0x45, 0x39, 0xd6, 0x78, 0x23, 0x45, 0x39, 0xd6, 0x78, 0x1e, 0x45, 0x39, 0xd6, 0x78, 0x19, 0x45, 0x39, 0xd6, 0x78, 0x14, 0x45, 0x39, 0xd6, 0x78, 0xf, 0x45, 0x39, 0xd6, 0x78, 0xa, 0x45, 0x39, 0xd6, 0x78, 0x5, 0x45, 0x39, 0xd6, 0x78, 0x0, 0xc3}, - "JNE": {0x45, 0x39, 0xd6, 0x75, 0x39, 0x45, 0x39, 0xd6, 0x75, 0x34, 0x45, 0x39, 0xd6, 0x75, 0x2f, 0x45, 0x39, 0xd6, 0x75, 0x2a, 0x45, 0x39, 0xd6, 0x75, 0x25, 0x45, 0x39, 0xd6, 0x75, 0x20, 0x66, 0x90, 0x45, 0x39, 0xd6, 0x75, 0x19, 0x45, 0x39, 0xd6, 0x75, 0x14, 0x45, 0x39, 0xd6, 0x75, 0xf, 0x45, 0x39, 0xd6, 0x75, 0xa, 0x45, 0x39, 0xd6, 0x75, 0x5, 0x45, 0x39, 0xd6, 0x75, 0x0, 0xc3}, - "JPC": {0x45, 0x39, 0xd6, 0x7b, 0x37, 0x45, 0x39, 0xd6, 0x7b, 0x32, 0x45, 0x39, 0xd6, 0x7b, 0x2d, 0x45, 0x39, 0xd6, 0x7b, 0x28, 0x45, 0x39, 0xd6, 0x7b, 0x23, 0x45, 0x39, 0xd6, 0x7b, 0x1e, 0x45, 0x39, 0xd6, 0x7b, 0x19, 0x45, 0x39, 0xd6, 0x7b, 0x14, 0x45, 0x39, 0xd6, 0x7b, 0xf, 0x45, 0x39, 0xd6, 0x7b, 0xa, 0x45, 0x39, 0xd6, 0x7b, 0x5, 0x45, 0x39, 0xd6, 0x7b, 0x0, 0xc3}, - "JPS": {0x45, 0x39, 0xd6, 0x7a, 0x37, 0x45, 0x39, 0xd6, 0x7a, 0x32, 0x45, 0x39, 0xd6, 0x7a, 0x2d, 0x45, 0x39, 0xd6, 0x7a, 0x28, 0x45, 0x39, 0xd6, 0x7a, 0x23, 0x45, 0x39, 0xd6, 0x7a, 0x1e, 0x45, 0x39, 0xd6, 0x7a, 0x19, 0x45, 0x39, 0xd6, 0x7a, 0x14, 0x45, 0x39, 0xd6, 0x7a, 0xf, 0x45, 0x39, 0xd6, 0x7a, 0xa, 0x45, 0x39, 0xd6, 0x7a, 0x5, 0x45, 0x39, 0xd6, 0x7a, 0x0, 0xc3}, - }, - }, - { - name: "CMPQ(register to const)", - setupFn: func(assembler Assembler) { - assembler.CompileRegisterToConst(CMPQ, RegAX, math.MaxInt16) - }, - jmpInstToExpectedBytes: map[string][]uint8{ - "JCC": {0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x73, 0x70, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x73, 0x68, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x73, 0x60, 0xf, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x73, 0x50, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x73, 0x48, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x73, 0x40, 0xf, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x73, 0x30, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x73, 0x28, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x73, 0x20, 0xf, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x73, 0x10, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x73, 0x8, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x73, 0x0, 0xc3}, - "JCS": {0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x72, 0x70, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x72, 0x68, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x72, 0x60, 0xf, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x72, 0x50, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x72, 0x48, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x72, 0x40, 0xf, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x72, 0x30, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x72, 0x28, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x72, 0x20, 0xf, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x72, 0x10, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x72, 0x8, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x72, 0x0, 0xc3}, - "JEQ": {0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x74, 0x70, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x74, 0x68, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x74, 0x60, 0xf, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x74, 0x50, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x74, 0x48, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x74, 0x40, 0xf, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x74, 0x30, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x74, 0x28, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x74, 0x20, 0xf, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x74, 0x10, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x74, 0x8, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x74, 0x0, 0xc3}, - "JGE": {0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7d, 0x70, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7d, 0x68, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7d, 0x60, 0xf, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7d, 0x50, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7d, 0x48, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7d, 0x40, 0xf, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7d, 0x30, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7d, 0x28, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7d, 0x20, 0xf, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7d, 0x10, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7d, 0x8, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7d, 0x0, 0xc3}, - "JGT": {0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7f, 0x70, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7f, 0x68, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7f, 0x60, 0xf, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7f, 0x50, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7f, 0x48, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7f, 0x40, 0xf, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7f, 0x30, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7f, 0x28, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7f, 0x20, 0xf, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7f, 0x10, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7f, 0x8, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7f, 0x0, 0xc3}, - "JHI": {0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x77, 0x70, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x77, 0x68, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x77, 0x60, 0xf, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x77, 0x50, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x77, 0x48, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x77, 0x40, 0xf, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x77, 0x30, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x77, 0x28, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x77, 0x20, 0xf, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x77, 0x10, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x77, 0x8, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x77, 0x0, 0xc3}, - "JLE": {0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7e, 0x70, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7e, 0x68, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7e, 0x60, 0xf, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7e, 0x50, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7e, 0x48, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7e, 0x40, 0xf, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7e, 0x30, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7e, 0x28, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7e, 0x20, 0xf, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7e, 0x10, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7e, 0x8, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7e, 0x0, 0xc3}, - "JLS": {0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x76, 0x70, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x76, 0x68, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x76, 0x60, 0xf, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x76, 0x50, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x76, 0x48, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x76, 0x40, 0xf, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x76, 0x30, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x76, 0x28, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x76, 0x20, 0xf, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x76, 0x10, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x76, 0x8, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x76, 0x0, 0xc3}, - "JLT": {0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7c, 0x70, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7c, 0x68, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7c, 0x60, 0xf, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7c, 0x50, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7c, 0x48, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7c, 0x40, 0xf, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7c, 0x30, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7c, 0x28, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7c, 0x20, 0xf, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7c, 0x10, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7c, 0x8, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7c, 0x0, 0xc3}, - "JMI": {0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x78, 0x5a, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x78, 0x52, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x78, 0x4a, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x66, 0x90, 0x78, 0x40, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x78, 0x38, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x78, 0x30, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x78, 0x28, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x78, 0x20, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x78, 0x18, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x78, 0x10, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x78, 0x8, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x78, 0x0, 0xc3}, - "JNE": {0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x75, 0x70, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x75, 0x68, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x75, 0x60, 0xf, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x75, 0x50, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x75, 0x48, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x75, 0x40, 0xf, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x75, 0x30, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x75, 0x28, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x75, 0x20, 0xf, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x75, 0x10, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x75, 0x8, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x75, 0x0, 0xc3}, - "JPC": {0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7b, 0x5a, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7b, 0x52, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7b, 0x4a, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x66, 0x90, 0x7b, 0x40, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7b, 0x38, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7b, 0x30, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7b, 0x28, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7b, 0x20, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7b, 0x18, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7b, 0x10, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7b, 0x8, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7b, 0x0, 0xc3}, - "JPS": {0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7a, 0x5a, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7a, 0x52, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7a, 0x4a, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x66, 0x90, 0x7a, 0x40, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7a, 0x38, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7a, 0x30, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7a, 0x28, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7a, 0x20, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7a, 0x18, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7a, 0x10, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7a, 0x8, 0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0, 0x7a, 0x0, 0xc3}, - }, - }, - { - name: "CMPQ(register to register)", - setupFn: func(assembler Assembler) { - assembler.CompileRegisterToRegister(CMPQ, RegR14, RegR10) - }, - jmpInstToExpectedBytes: map[string][]uint8{ - "JCC": {0x4d, 0x39, 0xd6, 0x73, 0x39, 0x4d, 0x39, 0xd6, 0x73, 0x34, 0x4d, 0x39, 0xd6, 0x73, 0x2f, 0x4d, 0x39, 0xd6, 0x73, 0x2a, 0x4d, 0x39, 0xd6, 0x73, 0x25, 0x4d, 0x39, 0xd6, 0x73, 0x20, 0x66, 0x90, 0x4d, 0x39, 0xd6, 0x73, 0x19, 0x4d, 0x39, 0xd6, 0x73, 0x14, 0x4d, 0x39, 0xd6, 0x73, 0xf, 0x4d, 0x39, 0xd6, 0x73, 0xa, 0x4d, 0x39, 0xd6, 0x73, 0x5, 0x4d, 0x39, 0xd6, 0x73, 0x0, 0xc3}, - "JCS": {0x4d, 0x39, 0xd6, 0x72, 0x39, 0x4d, 0x39, 0xd6, 0x72, 0x34, 0x4d, 0x39, 0xd6, 0x72, 0x2f, 0x4d, 0x39, 0xd6, 0x72, 0x2a, 0x4d, 0x39, 0xd6, 0x72, 0x25, 0x4d, 0x39, 0xd6, 0x72, 0x20, 0x66, 0x90, 0x4d, 0x39, 0xd6, 0x72, 0x19, 0x4d, 0x39, 0xd6, 0x72, 0x14, 0x4d, 0x39, 0xd6, 0x72, 0xf, 0x4d, 0x39, 0xd6, 0x72, 0xa, 0x4d, 0x39, 0xd6, 0x72, 0x5, 0x4d, 0x39, 0xd6, 0x72, 0x0, 0xc3}, - "JEQ": {0x4d, 0x39, 0xd6, 0x74, 0x39, 0x4d, 0x39, 0xd6, 0x74, 0x34, 0x4d, 0x39, 0xd6, 0x74, 0x2f, 0x4d, 0x39, 0xd6, 0x74, 0x2a, 0x4d, 0x39, 0xd6, 0x74, 0x25, 0x4d, 0x39, 0xd6, 0x74, 0x20, 0x66, 0x90, 0x4d, 0x39, 0xd6, 0x74, 0x19, 0x4d, 0x39, 0xd6, 0x74, 0x14, 0x4d, 0x39, 0xd6, 0x74, 0xf, 0x4d, 0x39, 0xd6, 0x74, 0xa, 0x4d, 0x39, 0xd6, 0x74, 0x5, 0x4d, 0x39, 0xd6, 0x74, 0x0, 0xc3}, - "JGE": {0x4d, 0x39, 0xd6, 0x7d, 0x39, 0x4d, 0x39, 0xd6, 0x7d, 0x34, 0x4d, 0x39, 0xd6, 0x7d, 0x2f, 0x4d, 0x39, 0xd6, 0x7d, 0x2a, 0x4d, 0x39, 0xd6, 0x7d, 0x25, 0x4d, 0x39, 0xd6, 0x7d, 0x20, 0x66, 0x90, 0x4d, 0x39, 0xd6, 0x7d, 0x19, 0x4d, 0x39, 0xd6, 0x7d, 0x14, 0x4d, 0x39, 0xd6, 0x7d, 0xf, 0x4d, 0x39, 0xd6, 0x7d, 0xa, 0x4d, 0x39, 0xd6, 0x7d, 0x5, 0x4d, 0x39, 0xd6, 0x7d, 0x0, 0xc3}, - "JGT": {0x4d, 0x39, 0xd6, 0x7f, 0x39, 0x4d, 0x39, 0xd6, 0x7f, 0x34, 0x4d, 0x39, 0xd6, 0x7f, 0x2f, 0x4d, 0x39, 0xd6, 0x7f, 0x2a, 0x4d, 0x39, 0xd6, 0x7f, 0x25, 0x4d, 0x39, 0xd6, 0x7f, 0x20, 0x66, 0x90, 0x4d, 0x39, 0xd6, 0x7f, 0x19, 0x4d, 0x39, 0xd6, 0x7f, 0x14, 0x4d, 0x39, 0xd6, 0x7f, 0xf, 0x4d, 0x39, 0xd6, 0x7f, 0xa, 0x4d, 0x39, 0xd6, 0x7f, 0x5, 0x4d, 0x39, 0xd6, 0x7f, 0x0, 0xc3}, - "JHI": {0x4d, 0x39, 0xd6, 0x77, 0x39, 0x4d, 0x39, 0xd6, 0x77, 0x34, 0x4d, 0x39, 0xd6, 0x77, 0x2f, 0x4d, 0x39, 0xd6, 0x77, 0x2a, 0x4d, 0x39, 0xd6, 0x77, 0x25, 0x4d, 0x39, 0xd6, 0x77, 0x20, 0x66, 0x90, 0x4d, 0x39, 0xd6, 0x77, 0x19, 0x4d, 0x39, 0xd6, 0x77, 0x14, 0x4d, 0x39, 0xd6, 0x77, 0xf, 0x4d, 0x39, 0xd6, 0x77, 0xa, 0x4d, 0x39, 0xd6, 0x77, 0x5, 0x4d, 0x39, 0xd6, 0x77, 0x0, 0xc3}, - "JLE": {0x4d, 0x39, 0xd6, 0x7e, 0x39, 0x4d, 0x39, 0xd6, 0x7e, 0x34, 0x4d, 0x39, 0xd6, 0x7e, 0x2f, 0x4d, 0x39, 0xd6, 0x7e, 0x2a, 0x4d, 0x39, 0xd6, 0x7e, 0x25, 0x4d, 0x39, 0xd6, 0x7e, 0x20, 0x66, 0x90, 0x4d, 0x39, 0xd6, 0x7e, 0x19, 0x4d, 0x39, 0xd6, 0x7e, 0x14, 0x4d, 0x39, 0xd6, 0x7e, 0xf, 0x4d, 0x39, 0xd6, 0x7e, 0xa, 0x4d, 0x39, 0xd6, 0x7e, 0x5, 0x4d, 0x39, 0xd6, 0x7e, 0x0, 0xc3}, - "JLS": {0x4d, 0x39, 0xd6, 0x76, 0x39, 0x4d, 0x39, 0xd6, 0x76, 0x34, 0x4d, 0x39, 0xd6, 0x76, 0x2f, 0x4d, 0x39, 0xd6, 0x76, 0x2a, 0x4d, 0x39, 0xd6, 0x76, 0x25, 0x4d, 0x39, 0xd6, 0x76, 0x20, 0x66, 0x90, 0x4d, 0x39, 0xd6, 0x76, 0x19, 0x4d, 0x39, 0xd6, 0x76, 0x14, 0x4d, 0x39, 0xd6, 0x76, 0xf, 0x4d, 0x39, 0xd6, 0x76, 0xa, 0x4d, 0x39, 0xd6, 0x76, 0x5, 0x4d, 0x39, 0xd6, 0x76, 0x0, 0xc3}, - "JLT": {0x4d, 0x39, 0xd6, 0x7c, 0x39, 0x4d, 0x39, 0xd6, 0x7c, 0x34, 0x4d, 0x39, 0xd6, 0x7c, 0x2f, 0x4d, 0x39, 0xd6, 0x7c, 0x2a, 0x4d, 0x39, 0xd6, 0x7c, 0x25, 0x4d, 0x39, 0xd6, 0x7c, 0x20, 0x66, 0x90, 0x4d, 0x39, 0xd6, 0x7c, 0x19, 0x4d, 0x39, 0xd6, 0x7c, 0x14, 0x4d, 0x39, 0xd6, 0x7c, 0xf, 0x4d, 0x39, 0xd6, 0x7c, 0xa, 0x4d, 0x39, 0xd6, 0x7c, 0x5, 0x4d, 0x39, 0xd6, 0x7c, 0x0, 0xc3}, - "JMI": {0x4d, 0x39, 0xd6, 0x78, 0x37, 0x4d, 0x39, 0xd6, 0x78, 0x32, 0x4d, 0x39, 0xd6, 0x78, 0x2d, 0x4d, 0x39, 0xd6, 0x78, 0x28, 0x4d, 0x39, 0xd6, 0x78, 0x23, 0x4d, 0x39, 0xd6, 0x78, 0x1e, 0x4d, 0x39, 0xd6, 0x78, 0x19, 0x4d, 0x39, 0xd6, 0x78, 0x14, 0x4d, 0x39, 0xd6, 0x78, 0xf, 0x4d, 0x39, 0xd6, 0x78, 0xa, 0x4d, 0x39, 0xd6, 0x78, 0x5, 0x4d, 0x39, 0xd6, 0x78, 0x0, 0xc3}, - "JNE": {0x4d, 0x39, 0xd6, 0x75, 0x39, 0x4d, 0x39, 0xd6, 0x75, 0x34, 0x4d, 0x39, 0xd6, 0x75, 0x2f, 0x4d, 0x39, 0xd6, 0x75, 0x2a, 0x4d, 0x39, 0xd6, 0x75, 0x25, 0x4d, 0x39, 0xd6, 0x75, 0x20, 0x66, 0x90, 0x4d, 0x39, 0xd6, 0x75, 0x19, 0x4d, 0x39, 0xd6, 0x75, 0x14, 0x4d, 0x39, 0xd6, 0x75, 0xf, 0x4d, 0x39, 0xd6, 0x75, 0xa, 0x4d, 0x39, 0xd6, 0x75, 0x5, 0x4d, 0x39, 0xd6, 0x75, 0x0, 0xc3}, - "JPC": {0x4d, 0x39, 0xd6, 0x7b, 0x37, 0x4d, 0x39, 0xd6, 0x7b, 0x32, 0x4d, 0x39, 0xd6, 0x7b, 0x2d, 0x4d, 0x39, 0xd6, 0x7b, 0x28, 0x4d, 0x39, 0xd6, 0x7b, 0x23, 0x4d, 0x39, 0xd6, 0x7b, 0x1e, 0x4d, 0x39, 0xd6, 0x7b, 0x19, 0x4d, 0x39, 0xd6, 0x7b, 0x14, 0x4d, 0x39, 0xd6, 0x7b, 0xf, 0x4d, 0x39, 0xd6, 0x7b, 0xa, 0x4d, 0x39, 0xd6, 0x7b, 0x5, 0x4d, 0x39, 0xd6, 0x7b, 0x0, 0xc3}, - "JPS": {0x4d, 0x39, 0xd6, 0x7a, 0x37, 0x4d, 0x39, 0xd6, 0x7a, 0x32, 0x4d, 0x39, 0xd6, 0x7a, 0x2d, 0x4d, 0x39, 0xd6, 0x7a, 0x28, 0x4d, 0x39, 0xd6, 0x7a, 0x23, 0x4d, 0x39, 0xd6, 0x7a, 0x1e, 0x4d, 0x39, 0xd6, 0x7a, 0x19, 0x4d, 0x39, 0xd6, 0x7a, 0x14, 0x4d, 0x39, 0xd6, 0x7a, 0xf, 0x4d, 0x39, 0xd6, 0x7a, 0xa, 0x4d, 0x39, 0xd6, 0x7a, 0x5, 0x4d, 0x39, 0xd6, 0x7a, 0x0, 0xc3}, - }, - }, - { - name: "TESTL", - setupFn: func(assembler Assembler) { - assembler.CompileRegisterToRegister(TESTL, RegAX, RegAX) - }, - jmpInstToExpectedBytes: map[string][]uint8{ - "JCC": {0x85, 0xc0, 0x73, 0x30, 0x85, 0xc0, 0x73, 0x2c, 0x85, 0xc0, 0x73, 0x28, 0x85, 0xc0, 0x73, 0x24, 0x85, 0xc0, 0x73, 0x20, 0x85, 0xc0, 0x73, 0x1c, 0x85, 0xc0, 0x73, 0x18, 0xf, 0x1f, 0x40, 0x0, 0x85, 0xc0, 0x73, 0x10, 0x85, 0xc0, 0x73, 0xc, 0x85, 0xc0, 0x73, 0x8, 0x85, 0xc0, 0x73, 0x4, 0x85, 0xc0, 0x73, 0x0, 0xc3}, - "JCS": {0x85, 0xc0, 0x72, 0x30, 0x85, 0xc0, 0x72, 0x2c, 0x85, 0xc0, 0x72, 0x28, 0x85, 0xc0, 0x72, 0x24, 0x85, 0xc0, 0x72, 0x20, 0x85, 0xc0, 0x72, 0x1c, 0x85, 0xc0, 0x72, 0x18, 0xf, 0x1f, 0x40, 0x0, 0x85, 0xc0, 0x72, 0x10, 0x85, 0xc0, 0x72, 0xc, 0x85, 0xc0, 0x72, 0x8, 0x85, 0xc0, 0x72, 0x4, 0x85, 0xc0, 0x72, 0x0, 0xc3}, - "JEQ": {0x85, 0xc0, 0x74, 0x30, 0x85, 0xc0, 0x74, 0x2c, 0x85, 0xc0, 0x74, 0x28, 0x85, 0xc0, 0x74, 0x24, 0x85, 0xc0, 0x74, 0x20, 0x85, 0xc0, 0x74, 0x1c, 0x85, 0xc0, 0x74, 0x18, 0xf, 0x1f, 0x40, 0x0, 0x85, 0xc0, 0x74, 0x10, 0x85, 0xc0, 0x74, 0xc, 0x85, 0xc0, 0x74, 0x8, 0x85, 0xc0, 0x74, 0x4, 0x85, 0xc0, 0x74, 0x0, 0xc3}, - "JGE": {0x85, 0xc0, 0x7d, 0x30, 0x85, 0xc0, 0x7d, 0x2c, 0x85, 0xc0, 0x7d, 0x28, 0x85, 0xc0, 0x7d, 0x24, 0x85, 0xc0, 0x7d, 0x20, 0x85, 0xc0, 0x7d, 0x1c, 0x85, 0xc0, 0x7d, 0x18, 0xf, 0x1f, 0x40, 0x0, 0x85, 0xc0, 0x7d, 0x10, 0x85, 0xc0, 0x7d, 0xc, 0x85, 0xc0, 0x7d, 0x8, 0x85, 0xc0, 0x7d, 0x4, 0x85, 0xc0, 0x7d, 0x0, 0xc3}, - "JGT": {0x85, 0xc0, 0x7f, 0x30, 0x85, 0xc0, 0x7f, 0x2c, 0x85, 0xc0, 0x7f, 0x28, 0x85, 0xc0, 0x7f, 0x24, 0x85, 0xc0, 0x7f, 0x20, 0x85, 0xc0, 0x7f, 0x1c, 0x85, 0xc0, 0x7f, 0x18, 0xf, 0x1f, 0x40, 0x0, 0x85, 0xc0, 0x7f, 0x10, 0x85, 0xc0, 0x7f, 0xc, 0x85, 0xc0, 0x7f, 0x8, 0x85, 0xc0, 0x7f, 0x4, 0x85, 0xc0, 0x7f, 0x0, 0xc3}, - "JHI": {0x85, 0xc0, 0x77, 0x30, 0x85, 0xc0, 0x77, 0x2c, 0x85, 0xc0, 0x77, 0x28, 0x85, 0xc0, 0x77, 0x24, 0x85, 0xc0, 0x77, 0x20, 0x85, 0xc0, 0x77, 0x1c, 0x85, 0xc0, 0x77, 0x18, 0xf, 0x1f, 0x40, 0x0, 0x85, 0xc0, 0x77, 0x10, 0x85, 0xc0, 0x77, 0xc, 0x85, 0xc0, 0x77, 0x8, 0x85, 0xc0, 0x77, 0x4, 0x85, 0xc0, 0x77, 0x0, 0xc3}, - "JLE": {0x85, 0xc0, 0x7e, 0x30, 0x85, 0xc0, 0x7e, 0x2c, 0x85, 0xc0, 0x7e, 0x28, 0x85, 0xc0, 0x7e, 0x24, 0x85, 0xc0, 0x7e, 0x20, 0x85, 0xc0, 0x7e, 0x1c, 0x85, 0xc0, 0x7e, 0x18, 0xf, 0x1f, 0x40, 0x0, 0x85, 0xc0, 0x7e, 0x10, 0x85, 0xc0, 0x7e, 0xc, 0x85, 0xc0, 0x7e, 0x8, 0x85, 0xc0, 0x7e, 0x4, 0x85, 0xc0, 0x7e, 0x0, 0xc3}, - "JLS": {0x85, 0xc0, 0x76, 0x30, 0x85, 0xc0, 0x76, 0x2c, 0x85, 0xc0, 0x76, 0x28, 0x85, 0xc0, 0x76, 0x24, 0x85, 0xc0, 0x76, 0x20, 0x85, 0xc0, 0x76, 0x1c, 0x85, 0xc0, 0x76, 0x18, 0xf, 0x1f, 0x40, 0x0, 0x85, 0xc0, 0x76, 0x10, 0x85, 0xc0, 0x76, 0xc, 0x85, 0xc0, 0x76, 0x8, 0x85, 0xc0, 0x76, 0x4, 0x85, 0xc0, 0x76, 0x0, 0xc3}, - "JLT": {0x85, 0xc0, 0x7c, 0x30, 0x85, 0xc0, 0x7c, 0x2c, 0x85, 0xc0, 0x7c, 0x28, 0x85, 0xc0, 0x7c, 0x24, 0x85, 0xc0, 0x7c, 0x20, 0x85, 0xc0, 0x7c, 0x1c, 0x85, 0xc0, 0x7c, 0x18, 0xf, 0x1f, 0x40, 0x0, 0x85, 0xc0, 0x7c, 0x10, 0x85, 0xc0, 0x7c, 0xc, 0x85, 0xc0, 0x7c, 0x8, 0x85, 0xc0, 0x7c, 0x4, 0x85, 0xc0, 0x7c, 0x0, 0xc3}, - "JMI": {0x85, 0xc0, 0x78, 0x30, 0x85, 0xc0, 0x78, 0x2c, 0x85, 0xc0, 0x78, 0x28, 0x85, 0xc0, 0x78, 0x24, 0x85, 0xc0, 0x78, 0x20, 0x85, 0xc0, 0x78, 0x1c, 0x85, 0xc0, 0x78, 0x18, 0xf, 0x1f, 0x40, 0x0, 0x85, 0xc0, 0x78, 0x10, 0x85, 0xc0, 0x78, 0xc, 0x85, 0xc0, 0x78, 0x8, 0x85, 0xc0, 0x78, 0x4, 0x85, 0xc0, 0x78, 0x0, 0xc3}, - "JNE": {0x85, 0xc0, 0x75, 0x30, 0x85, 0xc0, 0x75, 0x2c, 0x85, 0xc0, 0x75, 0x28, 0x85, 0xc0, 0x75, 0x24, 0x85, 0xc0, 0x75, 0x20, 0x85, 0xc0, 0x75, 0x1c, 0x85, 0xc0, 0x75, 0x18, 0xf, 0x1f, 0x40, 0x0, 0x85, 0xc0, 0x75, 0x10, 0x85, 0xc0, 0x75, 0xc, 0x85, 0xc0, 0x75, 0x8, 0x85, 0xc0, 0x75, 0x4, 0x85, 0xc0, 0x75, 0x0, 0xc3}, - "JPC": {0x85, 0xc0, 0x7b, 0x30, 0x85, 0xc0, 0x7b, 0x2c, 0x85, 0xc0, 0x7b, 0x28, 0x85, 0xc0, 0x7b, 0x24, 0x85, 0xc0, 0x7b, 0x20, 0x85, 0xc0, 0x7b, 0x1c, 0x85, 0xc0, 0x7b, 0x18, 0xf, 0x1f, 0x40, 0x0, 0x85, 0xc0, 0x7b, 0x10, 0x85, 0xc0, 0x7b, 0xc, 0x85, 0xc0, 0x7b, 0x8, 0x85, 0xc0, 0x7b, 0x4, 0x85, 0xc0, 0x7b, 0x0, 0xc3}, - "JPS": {0x85, 0xc0, 0x7a, 0x30, 0x85, 0xc0, 0x7a, 0x2c, 0x85, 0xc0, 0x7a, 0x28, 0x85, 0xc0, 0x7a, 0x24, 0x85, 0xc0, 0x7a, 0x20, 0x85, 0xc0, 0x7a, 0x1c, 0x85, 0xc0, 0x7a, 0x18, 0xf, 0x1f, 0x40, 0x0, 0x85, 0xc0, 0x7a, 0x10, 0x85, 0xc0, 0x7a, 0xc, 0x85, 0xc0, 0x7a, 0x8, 0x85, 0xc0, 0x7a, 0x4, 0x85, 0xc0, 0x7a, 0x0, 0xc3}, - }, - }, - { - name: "TESTQ", - setupFn: func(assembler Assembler) { - assembler.CompileRegisterToRegister(TESTQ, RegAX, RegAX) - }, - jmpInstToExpectedBytes: map[string][]uint8{ - "JCC": {0x48, 0x85, 0xc0, 0x73, 0x39, 0x48, 0x85, 0xc0, 0x73, 0x34, 0x48, 0x85, 0xc0, 0x73, 0x2f, 0x48, 0x85, 0xc0, 0x73, 0x2a, 0x48, 0x85, 0xc0, 0x73, 0x25, 0x48, 0x85, 0xc0, 0x73, 0x20, 0x66, 0x90, 0x48, 0x85, 0xc0, 0x73, 0x19, 0x48, 0x85, 0xc0, 0x73, 0x14, 0x48, 0x85, 0xc0, 0x73, 0xf, 0x48, 0x85, 0xc0, 0x73, 0xa, 0x48, 0x85, 0xc0, 0x73, 0x5, 0x48, 0x85, 0xc0, 0x73, 0x0, 0xc3}, - "JCS": {0x48, 0x85, 0xc0, 0x72, 0x39, 0x48, 0x85, 0xc0, 0x72, 0x34, 0x48, 0x85, 0xc0, 0x72, 0x2f, 0x48, 0x85, 0xc0, 0x72, 0x2a, 0x48, 0x85, 0xc0, 0x72, 0x25, 0x48, 0x85, 0xc0, 0x72, 0x20, 0x66, 0x90, 0x48, 0x85, 0xc0, 0x72, 0x19, 0x48, 0x85, 0xc0, 0x72, 0x14, 0x48, 0x85, 0xc0, 0x72, 0xf, 0x48, 0x85, 0xc0, 0x72, 0xa, 0x48, 0x85, 0xc0, 0x72, 0x5, 0x48, 0x85, 0xc0, 0x72, 0x0, 0xc3}, - "JEQ": {0x48, 0x85, 0xc0, 0x74, 0x39, 0x48, 0x85, 0xc0, 0x74, 0x34, 0x48, 0x85, 0xc0, 0x74, 0x2f, 0x48, 0x85, 0xc0, 0x74, 0x2a, 0x48, 0x85, 0xc0, 0x74, 0x25, 0x48, 0x85, 0xc0, 0x74, 0x20, 0x66, 0x90, 0x48, 0x85, 0xc0, 0x74, 0x19, 0x48, 0x85, 0xc0, 0x74, 0x14, 0x48, 0x85, 0xc0, 0x74, 0xf, 0x48, 0x85, 0xc0, 0x74, 0xa, 0x48, 0x85, 0xc0, 0x74, 0x5, 0x48, 0x85, 0xc0, 0x74, 0x0, 0xc3}, - "JGE": {0x48, 0x85, 0xc0, 0x7d, 0x39, 0x48, 0x85, 0xc0, 0x7d, 0x34, 0x48, 0x85, 0xc0, 0x7d, 0x2f, 0x48, 0x85, 0xc0, 0x7d, 0x2a, 0x48, 0x85, 0xc0, 0x7d, 0x25, 0x48, 0x85, 0xc0, 0x7d, 0x20, 0x66, 0x90, 0x48, 0x85, 0xc0, 0x7d, 0x19, 0x48, 0x85, 0xc0, 0x7d, 0x14, 0x48, 0x85, 0xc0, 0x7d, 0xf, 0x48, 0x85, 0xc0, 0x7d, 0xa, 0x48, 0x85, 0xc0, 0x7d, 0x5, 0x48, 0x85, 0xc0, 0x7d, 0x0, 0xc3}, - "JGT": {0x48, 0x85, 0xc0, 0x7f, 0x39, 0x48, 0x85, 0xc0, 0x7f, 0x34, 0x48, 0x85, 0xc0, 0x7f, 0x2f, 0x48, 0x85, 0xc0, 0x7f, 0x2a, 0x48, 0x85, 0xc0, 0x7f, 0x25, 0x48, 0x85, 0xc0, 0x7f, 0x20, 0x66, 0x90, 0x48, 0x85, 0xc0, 0x7f, 0x19, 0x48, 0x85, 0xc0, 0x7f, 0x14, 0x48, 0x85, 0xc0, 0x7f, 0xf, 0x48, 0x85, 0xc0, 0x7f, 0xa, 0x48, 0x85, 0xc0, 0x7f, 0x5, 0x48, 0x85, 0xc0, 0x7f, 0x0, 0xc3}, - "JHI": {0x48, 0x85, 0xc0, 0x77, 0x39, 0x48, 0x85, 0xc0, 0x77, 0x34, 0x48, 0x85, 0xc0, 0x77, 0x2f, 0x48, 0x85, 0xc0, 0x77, 0x2a, 0x48, 0x85, 0xc0, 0x77, 0x25, 0x48, 0x85, 0xc0, 0x77, 0x20, 0x66, 0x90, 0x48, 0x85, 0xc0, 0x77, 0x19, 0x48, 0x85, 0xc0, 0x77, 0x14, 0x48, 0x85, 0xc0, 0x77, 0xf, 0x48, 0x85, 0xc0, 0x77, 0xa, 0x48, 0x85, 0xc0, 0x77, 0x5, 0x48, 0x85, 0xc0, 0x77, 0x0, 0xc3}, - "JLE": {0x48, 0x85, 0xc0, 0x7e, 0x39, 0x48, 0x85, 0xc0, 0x7e, 0x34, 0x48, 0x85, 0xc0, 0x7e, 0x2f, 0x48, 0x85, 0xc0, 0x7e, 0x2a, 0x48, 0x85, 0xc0, 0x7e, 0x25, 0x48, 0x85, 0xc0, 0x7e, 0x20, 0x66, 0x90, 0x48, 0x85, 0xc0, 0x7e, 0x19, 0x48, 0x85, 0xc0, 0x7e, 0x14, 0x48, 0x85, 0xc0, 0x7e, 0xf, 0x48, 0x85, 0xc0, 0x7e, 0xa, 0x48, 0x85, 0xc0, 0x7e, 0x5, 0x48, 0x85, 0xc0, 0x7e, 0x0, 0xc3}, - "JLS": {0x48, 0x85, 0xc0, 0x76, 0x39, 0x48, 0x85, 0xc0, 0x76, 0x34, 0x48, 0x85, 0xc0, 0x76, 0x2f, 0x48, 0x85, 0xc0, 0x76, 0x2a, 0x48, 0x85, 0xc0, 0x76, 0x25, 0x48, 0x85, 0xc0, 0x76, 0x20, 0x66, 0x90, 0x48, 0x85, 0xc0, 0x76, 0x19, 0x48, 0x85, 0xc0, 0x76, 0x14, 0x48, 0x85, 0xc0, 0x76, 0xf, 0x48, 0x85, 0xc0, 0x76, 0xa, 0x48, 0x85, 0xc0, 0x76, 0x5, 0x48, 0x85, 0xc0, 0x76, 0x0, 0xc3}, - "JLT": {0x48, 0x85, 0xc0, 0x7c, 0x39, 0x48, 0x85, 0xc0, 0x7c, 0x34, 0x48, 0x85, 0xc0, 0x7c, 0x2f, 0x48, 0x85, 0xc0, 0x7c, 0x2a, 0x48, 0x85, 0xc0, 0x7c, 0x25, 0x48, 0x85, 0xc0, 0x7c, 0x20, 0x66, 0x90, 0x48, 0x85, 0xc0, 0x7c, 0x19, 0x48, 0x85, 0xc0, 0x7c, 0x14, 0x48, 0x85, 0xc0, 0x7c, 0xf, 0x48, 0x85, 0xc0, 0x7c, 0xa, 0x48, 0x85, 0xc0, 0x7c, 0x5, 0x48, 0x85, 0xc0, 0x7c, 0x0, 0xc3}, - "JMI": {0x48, 0x85, 0xc0, 0x78, 0x39, 0x48, 0x85, 0xc0, 0x78, 0x34, 0x48, 0x85, 0xc0, 0x78, 0x2f, 0x48, 0x85, 0xc0, 0x78, 0x2a, 0x48, 0x85, 0xc0, 0x78, 0x25, 0x48, 0x85, 0xc0, 0x78, 0x20, 0x66, 0x90, 0x48, 0x85, 0xc0, 0x78, 0x19, 0x48, 0x85, 0xc0, 0x78, 0x14, 0x48, 0x85, 0xc0, 0x78, 0xf, 0x48, 0x85, 0xc0, 0x78, 0xa, 0x48, 0x85, 0xc0, 0x78, 0x5, 0x48, 0x85, 0xc0, 0x78, 0x0, 0xc3}, - "JNE": {0x48, 0x85, 0xc0, 0x75, 0x39, 0x48, 0x85, 0xc0, 0x75, 0x34, 0x48, 0x85, 0xc0, 0x75, 0x2f, 0x48, 0x85, 0xc0, 0x75, 0x2a, 0x48, 0x85, 0xc0, 0x75, 0x25, 0x48, 0x85, 0xc0, 0x75, 0x20, 0x66, 0x90, 0x48, 0x85, 0xc0, 0x75, 0x19, 0x48, 0x85, 0xc0, 0x75, 0x14, 0x48, 0x85, 0xc0, 0x75, 0xf, 0x48, 0x85, 0xc0, 0x75, 0xa, 0x48, 0x85, 0xc0, 0x75, 0x5, 0x48, 0x85, 0xc0, 0x75, 0x0, 0xc3}, - "JPC": {0x48, 0x85, 0xc0, 0x7b, 0x39, 0x48, 0x85, 0xc0, 0x7b, 0x34, 0x48, 0x85, 0xc0, 0x7b, 0x2f, 0x48, 0x85, 0xc0, 0x7b, 0x2a, 0x48, 0x85, 0xc0, 0x7b, 0x25, 0x48, 0x85, 0xc0, 0x7b, 0x20, 0x66, 0x90, 0x48, 0x85, 0xc0, 0x7b, 0x19, 0x48, 0x85, 0xc0, 0x7b, 0x14, 0x48, 0x85, 0xc0, 0x7b, 0xf, 0x48, 0x85, 0xc0, 0x7b, 0xa, 0x48, 0x85, 0xc0, 0x7b, 0x5, 0x48, 0x85, 0xc0, 0x7b, 0x0, 0xc3}, - "JPS": {0x48, 0x85, 0xc0, 0x7a, 0x39, 0x48, 0x85, 0xc0, 0x7a, 0x34, 0x48, 0x85, 0xc0, 0x7a, 0x2f, 0x48, 0x85, 0xc0, 0x7a, 0x2a, 0x48, 0x85, 0xc0, 0x7a, 0x25, 0x48, 0x85, 0xc0, 0x7a, 0x20, 0x66, 0x90, 0x48, 0x85, 0xc0, 0x7a, 0x19, 0x48, 0x85, 0xc0, 0x7a, 0x14, 0x48, 0x85, 0xc0, 0x7a, 0xf, 0x48, 0x85, 0xc0, 0x7a, 0xa, 0x48, 0x85, 0xc0, 0x7a, 0x5, 0x48, 0x85, 0xc0, 0x7a, 0x0, 0xc3}, - }, - }, - { - name: "ADDL (register to register)", - setupFn: func(assembler Assembler) { - assembler.CompileRegisterToRegister(ADDL, RegR10, RegAX) - }, - jmpInstToExpectedBytes: map[string][]uint8{ - "JCC": {0x44, 0x1, 0xd0, 0x73, 0x39, 0x44, 0x1, 0xd0, 0x73, 0x34, 0x44, 0x1, 0xd0, 0x73, 0x2f, 0x44, 0x1, 0xd0, 0x73, 0x2a, 0x44, 0x1, 0xd0, 0x73, 0x25, 0x44, 0x1, 0xd0, 0x73, 0x20, 0x66, 0x90, 0x44, 0x1, 0xd0, 0x73, 0x19, 0x44, 0x1, 0xd0, 0x73, 0x14, 0x44, 0x1, 0xd0, 0x73, 0xf, 0x44, 0x1, 0xd0, 0x73, 0xa, 0x44, 0x1, 0xd0, 0x73, 0x5, 0x44, 0x1, 0xd0, 0x73, 0x0, 0xc3}, - "JCS": {0x44, 0x1, 0xd0, 0x72, 0x39, 0x44, 0x1, 0xd0, 0x72, 0x34, 0x44, 0x1, 0xd0, 0x72, 0x2f, 0x44, 0x1, 0xd0, 0x72, 0x2a, 0x44, 0x1, 0xd0, 0x72, 0x25, 0x44, 0x1, 0xd0, 0x72, 0x20, 0x66, 0x90, 0x44, 0x1, 0xd0, 0x72, 0x19, 0x44, 0x1, 0xd0, 0x72, 0x14, 0x44, 0x1, 0xd0, 0x72, 0xf, 0x44, 0x1, 0xd0, 0x72, 0xa, 0x44, 0x1, 0xd0, 0x72, 0x5, 0x44, 0x1, 0xd0, 0x72, 0x0, 0xc3}, - "JEQ": {0x44, 0x1, 0xd0, 0x74, 0x39, 0x44, 0x1, 0xd0, 0x74, 0x34, 0x44, 0x1, 0xd0, 0x74, 0x2f, 0x44, 0x1, 0xd0, 0x74, 0x2a, 0x44, 0x1, 0xd0, 0x74, 0x25, 0x44, 0x1, 0xd0, 0x74, 0x20, 0x66, 0x90, 0x44, 0x1, 0xd0, 0x74, 0x19, 0x44, 0x1, 0xd0, 0x74, 0x14, 0x44, 0x1, 0xd0, 0x74, 0xf, 0x44, 0x1, 0xd0, 0x74, 0xa, 0x44, 0x1, 0xd0, 0x74, 0x5, 0x44, 0x1, 0xd0, 0x74, 0x0, 0xc3}, - "JGE": {0x44, 0x1, 0xd0, 0x7d, 0x39, 0x44, 0x1, 0xd0, 0x7d, 0x34, 0x44, 0x1, 0xd0, 0x7d, 0x2f, 0x44, 0x1, 0xd0, 0x7d, 0x2a, 0x44, 0x1, 0xd0, 0x7d, 0x25, 0x44, 0x1, 0xd0, 0x7d, 0x20, 0x66, 0x90, 0x44, 0x1, 0xd0, 0x7d, 0x19, 0x44, 0x1, 0xd0, 0x7d, 0x14, 0x44, 0x1, 0xd0, 0x7d, 0xf, 0x44, 0x1, 0xd0, 0x7d, 0xa, 0x44, 0x1, 0xd0, 0x7d, 0x5, 0x44, 0x1, 0xd0, 0x7d, 0x0, 0xc3}, - "JGT": {0x44, 0x1, 0xd0, 0x7f, 0x39, 0x44, 0x1, 0xd0, 0x7f, 0x34, 0x44, 0x1, 0xd0, 0x7f, 0x2f, 0x44, 0x1, 0xd0, 0x7f, 0x2a, 0x44, 0x1, 0xd0, 0x7f, 0x25, 0x44, 0x1, 0xd0, 0x7f, 0x20, 0x66, 0x90, 0x44, 0x1, 0xd0, 0x7f, 0x19, 0x44, 0x1, 0xd0, 0x7f, 0x14, 0x44, 0x1, 0xd0, 0x7f, 0xf, 0x44, 0x1, 0xd0, 0x7f, 0xa, 0x44, 0x1, 0xd0, 0x7f, 0x5, 0x44, 0x1, 0xd0, 0x7f, 0x0, 0xc3}, - "JHI": {0x44, 0x1, 0xd0, 0x77, 0x39, 0x44, 0x1, 0xd0, 0x77, 0x34, 0x44, 0x1, 0xd0, 0x77, 0x2f, 0x44, 0x1, 0xd0, 0x77, 0x2a, 0x44, 0x1, 0xd0, 0x77, 0x25, 0x44, 0x1, 0xd0, 0x77, 0x20, 0x66, 0x90, 0x44, 0x1, 0xd0, 0x77, 0x19, 0x44, 0x1, 0xd0, 0x77, 0x14, 0x44, 0x1, 0xd0, 0x77, 0xf, 0x44, 0x1, 0xd0, 0x77, 0xa, 0x44, 0x1, 0xd0, 0x77, 0x5, 0x44, 0x1, 0xd0, 0x77, 0x0, 0xc3}, - "JLE": {0x44, 0x1, 0xd0, 0x7e, 0x39, 0x44, 0x1, 0xd0, 0x7e, 0x34, 0x44, 0x1, 0xd0, 0x7e, 0x2f, 0x44, 0x1, 0xd0, 0x7e, 0x2a, 0x44, 0x1, 0xd0, 0x7e, 0x25, 0x44, 0x1, 0xd0, 0x7e, 0x20, 0x66, 0x90, 0x44, 0x1, 0xd0, 0x7e, 0x19, 0x44, 0x1, 0xd0, 0x7e, 0x14, 0x44, 0x1, 0xd0, 0x7e, 0xf, 0x44, 0x1, 0xd0, 0x7e, 0xa, 0x44, 0x1, 0xd0, 0x7e, 0x5, 0x44, 0x1, 0xd0, 0x7e, 0x0, 0xc3}, - "JLS": {0x44, 0x1, 0xd0, 0x76, 0x39, 0x44, 0x1, 0xd0, 0x76, 0x34, 0x44, 0x1, 0xd0, 0x76, 0x2f, 0x44, 0x1, 0xd0, 0x76, 0x2a, 0x44, 0x1, 0xd0, 0x76, 0x25, 0x44, 0x1, 0xd0, 0x76, 0x20, 0x66, 0x90, 0x44, 0x1, 0xd0, 0x76, 0x19, 0x44, 0x1, 0xd0, 0x76, 0x14, 0x44, 0x1, 0xd0, 0x76, 0xf, 0x44, 0x1, 0xd0, 0x76, 0xa, 0x44, 0x1, 0xd0, 0x76, 0x5, 0x44, 0x1, 0xd0, 0x76, 0x0, 0xc3}, - "JLT": {0x44, 0x1, 0xd0, 0x7c, 0x39, 0x44, 0x1, 0xd0, 0x7c, 0x34, 0x44, 0x1, 0xd0, 0x7c, 0x2f, 0x44, 0x1, 0xd0, 0x7c, 0x2a, 0x44, 0x1, 0xd0, 0x7c, 0x25, 0x44, 0x1, 0xd0, 0x7c, 0x20, 0x66, 0x90, 0x44, 0x1, 0xd0, 0x7c, 0x19, 0x44, 0x1, 0xd0, 0x7c, 0x14, 0x44, 0x1, 0xd0, 0x7c, 0xf, 0x44, 0x1, 0xd0, 0x7c, 0xa, 0x44, 0x1, 0xd0, 0x7c, 0x5, 0x44, 0x1, 0xd0, 0x7c, 0x0, 0xc3}, - "JMI": {0x44, 0x1, 0xd0, 0x78, 0x37, 0x44, 0x1, 0xd0, 0x78, 0x32, 0x44, 0x1, 0xd0, 0x78, 0x2d, 0x44, 0x1, 0xd0, 0x78, 0x28, 0x44, 0x1, 0xd0, 0x78, 0x23, 0x44, 0x1, 0xd0, 0x78, 0x1e, 0x44, 0x1, 0xd0, 0x78, 0x19, 0x44, 0x1, 0xd0, 0x78, 0x14, 0x44, 0x1, 0xd0, 0x78, 0xf, 0x44, 0x1, 0xd0, 0x78, 0xa, 0x44, 0x1, 0xd0, 0x78, 0x5, 0x44, 0x1, 0xd0, 0x78, 0x0, 0xc3}, - "JNE": {0x44, 0x1, 0xd0, 0x75, 0x39, 0x44, 0x1, 0xd0, 0x75, 0x34, 0x44, 0x1, 0xd0, 0x75, 0x2f, 0x44, 0x1, 0xd0, 0x75, 0x2a, 0x44, 0x1, 0xd0, 0x75, 0x25, 0x44, 0x1, 0xd0, 0x75, 0x20, 0x66, 0x90, 0x44, 0x1, 0xd0, 0x75, 0x19, 0x44, 0x1, 0xd0, 0x75, 0x14, 0x44, 0x1, 0xd0, 0x75, 0xf, 0x44, 0x1, 0xd0, 0x75, 0xa, 0x44, 0x1, 0xd0, 0x75, 0x5, 0x44, 0x1, 0xd0, 0x75, 0x0, 0xc3}, - "JPC": {0x44, 0x1, 0xd0, 0x7b, 0x37, 0x44, 0x1, 0xd0, 0x7b, 0x32, 0x44, 0x1, 0xd0, 0x7b, 0x2d, 0x44, 0x1, 0xd0, 0x7b, 0x28, 0x44, 0x1, 0xd0, 0x7b, 0x23, 0x44, 0x1, 0xd0, 0x7b, 0x1e, 0x44, 0x1, 0xd0, 0x7b, 0x19, 0x44, 0x1, 0xd0, 0x7b, 0x14, 0x44, 0x1, 0xd0, 0x7b, 0xf, 0x44, 0x1, 0xd0, 0x7b, 0xa, 0x44, 0x1, 0xd0, 0x7b, 0x5, 0x44, 0x1, 0xd0, 0x7b, 0x0, 0xc3}, - "JPS": {0x44, 0x1, 0xd0, 0x7a, 0x37, 0x44, 0x1, 0xd0, 0x7a, 0x32, 0x44, 0x1, 0xd0, 0x7a, 0x2d, 0x44, 0x1, 0xd0, 0x7a, 0x28, 0x44, 0x1, 0xd0, 0x7a, 0x23, 0x44, 0x1, 0xd0, 0x7a, 0x1e, 0x44, 0x1, 0xd0, 0x7a, 0x19, 0x44, 0x1, 0xd0, 0x7a, 0x14, 0x44, 0x1, 0xd0, 0x7a, 0xf, 0x44, 0x1, 0xd0, 0x7a, 0xa, 0x44, 0x1, 0xd0, 0x7a, 0x5, 0x44, 0x1, 0xd0, 0x7a, 0x0, 0xc3}, - }, - }, - { - name: "ADDL(memory to register)", - setupFn: func(assembler Assembler) { - assembler.CompileMemoryToRegister(ADDL, RegR10, 1234, RegAX) - }, - jmpInstToExpectedBytes: map[string][]uint8{ - "JCC": {0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x73, 0x72, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x73, 0x69, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x73, 0x60, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x73, 0x52, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x73, 0x49, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x73, 0x40, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x73, 0x32, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x73, 0x29, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x73, 0x20, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x73, 0x12, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x73, 0x9, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x73, 0x0, 0xc3}, - "JCS": {0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x72, 0x72, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x72, 0x69, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x72, 0x60, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x72, 0x52, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x72, 0x49, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x72, 0x40, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x72, 0x32, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x72, 0x29, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x72, 0x20, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x72, 0x12, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x72, 0x9, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x72, 0x0, 0xc3}, - "JEQ": {0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x74, 0x72, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x74, 0x69, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x74, 0x60, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x74, 0x52, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x74, 0x49, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x74, 0x40, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x74, 0x32, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x74, 0x29, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x74, 0x20, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x74, 0x12, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x74, 0x9, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x74, 0x0, 0xc3}, - "JGE": {0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7d, 0x72, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7d, 0x69, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7d, 0x60, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7d, 0x52, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7d, 0x49, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7d, 0x40, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7d, 0x32, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7d, 0x29, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7d, 0x20, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7d, 0x12, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7d, 0x9, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7d, 0x0, 0xc3}, - "JGT": {0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7f, 0x72, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7f, 0x69, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7f, 0x60, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7f, 0x52, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7f, 0x49, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7f, 0x40, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7f, 0x32, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7f, 0x29, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7f, 0x20, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7f, 0x12, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7f, 0x9, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7f, 0x0, 0xc3}, - "JHI": {0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x77, 0x72, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x77, 0x69, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x77, 0x60, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x77, 0x52, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x77, 0x49, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x77, 0x40, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x77, 0x32, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x77, 0x29, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x77, 0x20, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x77, 0x12, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x77, 0x9, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x77, 0x0, 0xc3}, - "JLE": {0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7e, 0x72, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7e, 0x69, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7e, 0x60, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7e, 0x52, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7e, 0x49, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7e, 0x40, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7e, 0x32, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7e, 0x29, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7e, 0x20, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7e, 0x12, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7e, 0x9, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7e, 0x0, 0xc3}, - "JLS": {0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x76, 0x72, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x76, 0x69, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x76, 0x60, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x76, 0x52, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x76, 0x49, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x76, 0x40, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x76, 0x32, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x76, 0x29, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x76, 0x20, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x76, 0x12, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x76, 0x9, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x76, 0x0, 0xc3}, - "JLT": {0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7c, 0x72, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7c, 0x69, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7c, 0x60, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7c, 0x52, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7c, 0x49, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7c, 0x40, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7c, 0x32, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7c, 0x29, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7c, 0x20, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7c, 0x12, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7c, 0x9, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7c, 0x0, 0xc3}, - "JMI": {0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x78, 0x63, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x78, 0x5a, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x78, 0x51, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x78, 0x48, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x78, 0x3f, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x78, 0x36, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x78, 0x2d, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x78, 0x24, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x78, 0x1b, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x78, 0x12, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x78, 0x9, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x78, 0x0, 0xc3}, - "JNE": {0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x75, 0x72, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x75, 0x69, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x75, 0x60, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x75, 0x52, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x75, 0x49, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x75, 0x40, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x75, 0x32, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x75, 0x29, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x75, 0x20, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x75, 0x12, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x75, 0x9, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x75, 0x0, 0xc3}, - "JPC": {0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7b, 0x63, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7b, 0x5a, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7b, 0x51, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7b, 0x48, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7b, 0x3f, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7b, 0x36, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7b, 0x2d, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7b, 0x24, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7b, 0x1b, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7b, 0x12, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7b, 0x9, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7b, 0x0, 0xc3}, - "JPS": {0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7a, 0x63, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7a, 0x5a, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7a, 0x51, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7a, 0x48, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7a, 0x3f, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7a, 0x36, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7a, 0x2d, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7a, 0x24, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7a, 0x1b, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7a, 0x12, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7a, 0x9, 0x41, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7a, 0x0, 0xc3}, - }, - }, - { - name: "ADDQ (register to register)", - setupFn: func(assembler Assembler) { - assembler.CompileRegisterToRegister(ADDQ, RegR10, RegAX) - }, - jmpInstToExpectedBytes: map[string][]uint8{ - "JCC": {0x4c, 0x1, 0xd0, 0x73, 0x39, 0x4c, 0x1, 0xd0, 0x73, 0x34, 0x4c, 0x1, 0xd0, 0x73, 0x2f, 0x4c, 0x1, 0xd0, 0x73, 0x2a, 0x4c, 0x1, 0xd0, 0x73, 0x25, 0x4c, 0x1, 0xd0, 0x73, 0x20, 0x66, 0x90, 0x4c, 0x1, 0xd0, 0x73, 0x19, 0x4c, 0x1, 0xd0, 0x73, 0x14, 0x4c, 0x1, 0xd0, 0x73, 0xf, 0x4c, 0x1, 0xd0, 0x73, 0xa, 0x4c, 0x1, 0xd0, 0x73, 0x5, 0x4c, 0x1, 0xd0, 0x73, 0x0, 0xc3}, - "JCS": {0x4c, 0x1, 0xd0, 0x72, 0x39, 0x4c, 0x1, 0xd0, 0x72, 0x34, 0x4c, 0x1, 0xd0, 0x72, 0x2f, 0x4c, 0x1, 0xd0, 0x72, 0x2a, 0x4c, 0x1, 0xd0, 0x72, 0x25, 0x4c, 0x1, 0xd0, 0x72, 0x20, 0x66, 0x90, 0x4c, 0x1, 0xd0, 0x72, 0x19, 0x4c, 0x1, 0xd0, 0x72, 0x14, 0x4c, 0x1, 0xd0, 0x72, 0xf, 0x4c, 0x1, 0xd0, 0x72, 0xa, 0x4c, 0x1, 0xd0, 0x72, 0x5, 0x4c, 0x1, 0xd0, 0x72, 0x0, 0xc3}, - "JEQ": {0x4c, 0x1, 0xd0, 0x74, 0x39, 0x4c, 0x1, 0xd0, 0x74, 0x34, 0x4c, 0x1, 0xd0, 0x74, 0x2f, 0x4c, 0x1, 0xd0, 0x74, 0x2a, 0x4c, 0x1, 0xd0, 0x74, 0x25, 0x4c, 0x1, 0xd0, 0x74, 0x20, 0x66, 0x90, 0x4c, 0x1, 0xd0, 0x74, 0x19, 0x4c, 0x1, 0xd0, 0x74, 0x14, 0x4c, 0x1, 0xd0, 0x74, 0xf, 0x4c, 0x1, 0xd0, 0x74, 0xa, 0x4c, 0x1, 0xd0, 0x74, 0x5, 0x4c, 0x1, 0xd0, 0x74, 0x0, 0xc3}, - "JGE": {0x4c, 0x1, 0xd0, 0x7d, 0x39, 0x4c, 0x1, 0xd0, 0x7d, 0x34, 0x4c, 0x1, 0xd0, 0x7d, 0x2f, 0x4c, 0x1, 0xd0, 0x7d, 0x2a, 0x4c, 0x1, 0xd0, 0x7d, 0x25, 0x4c, 0x1, 0xd0, 0x7d, 0x20, 0x66, 0x90, 0x4c, 0x1, 0xd0, 0x7d, 0x19, 0x4c, 0x1, 0xd0, 0x7d, 0x14, 0x4c, 0x1, 0xd0, 0x7d, 0xf, 0x4c, 0x1, 0xd0, 0x7d, 0xa, 0x4c, 0x1, 0xd0, 0x7d, 0x5, 0x4c, 0x1, 0xd0, 0x7d, 0x0, 0xc3}, - "JGT": {0x4c, 0x1, 0xd0, 0x7f, 0x39, 0x4c, 0x1, 0xd0, 0x7f, 0x34, 0x4c, 0x1, 0xd0, 0x7f, 0x2f, 0x4c, 0x1, 0xd0, 0x7f, 0x2a, 0x4c, 0x1, 0xd0, 0x7f, 0x25, 0x4c, 0x1, 0xd0, 0x7f, 0x20, 0x66, 0x90, 0x4c, 0x1, 0xd0, 0x7f, 0x19, 0x4c, 0x1, 0xd0, 0x7f, 0x14, 0x4c, 0x1, 0xd0, 0x7f, 0xf, 0x4c, 0x1, 0xd0, 0x7f, 0xa, 0x4c, 0x1, 0xd0, 0x7f, 0x5, 0x4c, 0x1, 0xd0, 0x7f, 0x0, 0xc3}, - "JHI": {0x4c, 0x1, 0xd0, 0x77, 0x39, 0x4c, 0x1, 0xd0, 0x77, 0x34, 0x4c, 0x1, 0xd0, 0x77, 0x2f, 0x4c, 0x1, 0xd0, 0x77, 0x2a, 0x4c, 0x1, 0xd0, 0x77, 0x25, 0x4c, 0x1, 0xd0, 0x77, 0x20, 0x66, 0x90, 0x4c, 0x1, 0xd0, 0x77, 0x19, 0x4c, 0x1, 0xd0, 0x77, 0x14, 0x4c, 0x1, 0xd0, 0x77, 0xf, 0x4c, 0x1, 0xd0, 0x77, 0xa, 0x4c, 0x1, 0xd0, 0x77, 0x5, 0x4c, 0x1, 0xd0, 0x77, 0x0, 0xc3}, - "JLE": {0x4c, 0x1, 0xd0, 0x7e, 0x39, 0x4c, 0x1, 0xd0, 0x7e, 0x34, 0x4c, 0x1, 0xd0, 0x7e, 0x2f, 0x4c, 0x1, 0xd0, 0x7e, 0x2a, 0x4c, 0x1, 0xd0, 0x7e, 0x25, 0x4c, 0x1, 0xd0, 0x7e, 0x20, 0x66, 0x90, 0x4c, 0x1, 0xd0, 0x7e, 0x19, 0x4c, 0x1, 0xd0, 0x7e, 0x14, 0x4c, 0x1, 0xd0, 0x7e, 0xf, 0x4c, 0x1, 0xd0, 0x7e, 0xa, 0x4c, 0x1, 0xd0, 0x7e, 0x5, 0x4c, 0x1, 0xd0, 0x7e, 0x0, 0xc3}, - "JLS": {0x4c, 0x1, 0xd0, 0x76, 0x39, 0x4c, 0x1, 0xd0, 0x76, 0x34, 0x4c, 0x1, 0xd0, 0x76, 0x2f, 0x4c, 0x1, 0xd0, 0x76, 0x2a, 0x4c, 0x1, 0xd0, 0x76, 0x25, 0x4c, 0x1, 0xd0, 0x76, 0x20, 0x66, 0x90, 0x4c, 0x1, 0xd0, 0x76, 0x19, 0x4c, 0x1, 0xd0, 0x76, 0x14, 0x4c, 0x1, 0xd0, 0x76, 0xf, 0x4c, 0x1, 0xd0, 0x76, 0xa, 0x4c, 0x1, 0xd0, 0x76, 0x5, 0x4c, 0x1, 0xd0, 0x76, 0x0, 0xc3}, - "JLT": {0x4c, 0x1, 0xd0, 0x7c, 0x39, 0x4c, 0x1, 0xd0, 0x7c, 0x34, 0x4c, 0x1, 0xd0, 0x7c, 0x2f, 0x4c, 0x1, 0xd0, 0x7c, 0x2a, 0x4c, 0x1, 0xd0, 0x7c, 0x25, 0x4c, 0x1, 0xd0, 0x7c, 0x20, 0x66, 0x90, 0x4c, 0x1, 0xd0, 0x7c, 0x19, 0x4c, 0x1, 0xd0, 0x7c, 0x14, 0x4c, 0x1, 0xd0, 0x7c, 0xf, 0x4c, 0x1, 0xd0, 0x7c, 0xa, 0x4c, 0x1, 0xd0, 0x7c, 0x5, 0x4c, 0x1, 0xd0, 0x7c, 0x0, 0xc3}, - "JMI": {0x4c, 0x1, 0xd0, 0x78, 0x37, 0x4c, 0x1, 0xd0, 0x78, 0x32, 0x4c, 0x1, 0xd0, 0x78, 0x2d, 0x4c, 0x1, 0xd0, 0x78, 0x28, 0x4c, 0x1, 0xd0, 0x78, 0x23, 0x4c, 0x1, 0xd0, 0x78, 0x1e, 0x4c, 0x1, 0xd0, 0x78, 0x19, 0x4c, 0x1, 0xd0, 0x78, 0x14, 0x4c, 0x1, 0xd0, 0x78, 0xf, 0x4c, 0x1, 0xd0, 0x78, 0xa, 0x4c, 0x1, 0xd0, 0x78, 0x5, 0x4c, 0x1, 0xd0, 0x78, 0x0, 0xc3}, - "JNE": {0x4c, 0x1, 0xd0, 0x75, 0x39, 0x4c, 0x1, 0xd0, 0x75, 0x34, 0x4c, 0x1, 0xd0, 0x75, 0x2f, 0x4c, 0x1, 0xd0, 0x75, 0x2a, 0x4c, 0x1, 0xd0, 0x75, 0x25, 0x4c, 0x1, 0xd0, 0x75, 0x20, 0x66, 0x90, 0x4c, 0x1, 0xd0, 0x75, 0x19, 0x4c, 0x1, 0xd0, 0x75, 0x14, 0x4c, 0x1, 0xd0, 0x75, 0xf, 0x4c, 0x1, 0xd0, 0x75, 0xa, 0x4c, 0x1, 0xd0, 0x75, 0x5, 0x4c, 0x1, 0xd0, 0x75, 0x0, 0xc3}, - "JPC": {0x4c, 0x1, 0xd0, 0x7b, 0x37, 0x4c, 0x1, 0xd0, 0x7b, 0x32, 0x4c, 0x1, 0xd0, 0x7b, 0x2d, 0x4c, 0x1, 0xd0, 0x7b, 0x28, 0x4c, 0x1, 0xd0, 0x7b, 0x23, 0x4c, 0x1, 0xd0, 0x7b, 0x1e, 0x4c, 0x1, 0xd0, 0x7b, 0x19, 0x4c, 0x1, 0xd0, 0x7b, 0x14, 0x4c, 0x1, 0xd0, 0x7b, 0xf, 0x4c, 0x1, 0xd0, 0x7b, 0xa, 0x4c, 0x1, 0xd0, 0x7b, 0x5, 0x4c, 0x1, 0xd0, 0x7b, 0x0, 0xc3}, - "JPS": {0x4c, 0x1, 0xd0, 0x7a, 0x37, 0x4c, 0x1, 0xd0, 0x7a, 0x32, 0x4c, 0x1, 0xd0, 0x7a, 0x2d, 0x4c, 0x1, 0xd0, 0x7a, 0x28, 0x4c, 0x1, 0xd0, 0x7a, 0x23, 0x4c, 0x1, 0xd0, 0x7a, 0x1e, 0x4c, 0x1, 0xd0, 0x7a, 0x19, 0x4c, 0x1, 0xd0, 0x7a, 0x14, 0x4c, 0x1, 0xd0, 0x7a, 0xf, 0x4c, 0x1, 0xd0, 0x7a, 0xa, 0x4c, 0x1, 0xd0, 0x7a, 0x5, 0x4c, 0x1, 0xd0, 0x7a, 0x0, 0xc3}, - }, - }, - { - name: "ADDQ(memory to register)", - setupFn: func(assembler Assembler) { - assembler.CompileMemoryToRegister(ADDQ, RegR10, 1234, RegAX) - }, - jmpInstToExpectedBytes: map[string][]uint8{ - "JCC": {0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x73, 0x72, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x73, 0x69, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x73, 0x60, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x73, 0x52, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x73, 0x49, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x73, 0x40, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x73, 0x32, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x73, 0x29, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x73, 0x20, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x73, 0x12, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x73, 0x9, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x73, 0x0, 0xc3}, - "JCS": {0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x72, 0x72, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x72, 0x69, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x72, 0x60, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x72, 0x52, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x72, 0x49, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x72, 0x40, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x72, 0x32, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x72, 0x29, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x72, 0x20, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x72, 0x12, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x72, 0x9, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x72, 0x0, 0xc3}, - "JEQ": {0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x74, 0x72, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x74, 0x69, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x74, 0x60, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x74, 0x52, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x74, 0x49, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x74, 0x40, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x74, 0x32, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x74, 0x29, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x74, 0x20, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x74, 0x12, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x74, 0x9, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x74, 0x0, 0xc3}, - "JGE": {0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7d, 0x72, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7d, 0x69, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7d, 0x60, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7d, 0x52, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7d, 0x49, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7d, 0x40, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7d, 0x32, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7d, 0x29, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7d, 0x20, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7d, 0x12, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7d, 0x9, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7d, 0x0, 0xc3}, - "JGT": {0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7f, 0x72, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7f, 0x69, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7f, 0x60, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7f, 0x52, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7f, 0x49, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7f, 0x40, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7f, 0x32, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7f, 0x29, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7f, 0x20, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7f, 0x12, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7f, 0x9, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7f, 0x0, 0xc3}, - "JHI": {0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x77, 0x72, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x77, 0x69, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x77, 0x60, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x77, 0x52, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x77, 0x49, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x77, 0x40, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x77, 0x32, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x77, 0x29, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x77, 0x20, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x77, 0x12, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x77, 0x9, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x77, 0x0, 0xc3}, - "JLE": {0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7e, 0x72, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7e, 0x69, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7e, 0x60, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7e, 0x52, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7e, 0x49, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7e, 0x40, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7e, 0x32, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7e, 0x29, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7e, 0x20, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7e, 0x12, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7e, 0x9, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7e, 0x0, 0xc3}, - "JLS": {0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x76, 0x72, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x76, 0x69, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x76, 0x60, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x76, 0x52, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x76, 0x49, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x76, 0x40, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x76, 0x32, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x76, 0x29, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x76, 0x20, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x76, 0x12, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x76, 0x9, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x76, 0x0, 0xc3}, - "JLT": {0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7c, 0x72, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7c, 0x69, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7c, 0x60, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7c, 0x52, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7c, 0x49, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7c, 0x40, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7c, 0x32, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7c, 0x29, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7c, 0x20, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7c, 0x12, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7c, 0x9, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7c, 0x0, 0xc3}, - "JMI": {0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x78, 0x63, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x78, 0x5a, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x78, 0x51, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x78, 0x48, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x78, 0x3f, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x78, 0x36, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x78, 0x2d, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x78, 0x24, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x78, 0x1b, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x78, 0x12, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x78, 0x9, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x78, 0x0, 0xc3}, - "JNE": {0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x75, 0x72, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x75, 0x69, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x75, 0x60, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x75, 0x52, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x75, 0x49, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x75, 0x40, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x75, 0x32, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x75, 0x29, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x75, 0x20, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x75, 0x12, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x75, 0x9, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x75, 0x0, 0xc3}, - "JPC": {0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7b, 0x63, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7b, 0x5a, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7b, 0x51, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7b, 0x48, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7b, 0x3f, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7b, 0x36, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7b, 0x2d, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7b, 0x24, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7b, 0x1b, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7b, 0x12, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7b, 0x9, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7b, 0x0, 0xc3}, - "JPS": {0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7a, 0x63, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7a, 0x5a, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7a, 0x51, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7a, 0x48, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7a, 0x3f, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7a, 0x36, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7a, 0x2d, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7a, 0x24, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7a, 0x1b, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7a, 0x12, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7a, 0x9, 0x49, 0x3, 0x82, 0xd2, 0x4, 0x0, 0x0, 0x7a, 0x0, 0xc3}, - }, - }, - { - name: "ADDQ(const to register)", - setupFn: func(assembler Assembler) { - assembler.CompileConstToRegister(ADDQ, 1234, RegR10) - }, - jmpInstToExpectedBytes: map[string][]uint8{ - "JCC": {0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x73, 0x72, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x73, 0x69, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x73, 0x60, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x73, 0x52, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x73, 0x49, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x73, 0x40, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x73, 0x32, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x73, 0x29, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x73, 0x20, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x73, 0x12, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x73, 0x9, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x73, 0x0, 0xc3}, - "JCS": {0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x72, 0x72, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x72, 0x69, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x72, 0x60, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x72, 0x52, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x72, 0x49, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x72, 0x40, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x72, 0x32, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x72, 0x29, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x72, 0x20, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x72, 0x12, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x72, 0x9, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x72, 0x0, 0xc3}, - "JEQ": {0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x74, 0x72, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x74, 0x69, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x74, 0x60, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x74, 0x52, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x74, 0x49, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x74, 0x40, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x74, 0x32, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x74, 0x29, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x74, 0x20, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x74, 0x12, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x74, 0x9, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x74, 0x0, 0xc3}, - "JGE": {0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7d, 0x72, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7d, 0x69, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7d, 0x60, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7d, 0x52, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7d, 0x49, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7d, 0x40, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7d, 0x32, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7d, 0x29, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7d, 0x20, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7d, 0x12, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7d, 0x9, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7d, 0x0, 0xc3}, - "JGT": {0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7f, 0x72, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7f, 0x69, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7f, 0x60, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7f, 0x52, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7f, 0x49, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7f, 0x40, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7f, 0x32, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7f, 0x29, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7f, 0x20, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7f, 0x12, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7f, 0x9, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7f, 0x0, 0xc3}, - "JHI": {0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x77, 0x72, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x77, 0x69, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x77, 0x60, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x77, 0x52, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x77, 0x49, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x77, 0x40, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x77, 0x32, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x77, 0x29, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x77, 0x20, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x77, 0x12, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x77, 0x9, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x77, 0x0, 0xc3}, - "JLE": {0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7e, 0x72, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7e, 0x69, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7e, 0x60, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7e, 0x52, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7e, 0x49, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7e, 0x40, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7e, 0x32, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7e, 0x29, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7e, 0x20, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7e, 0x12, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7e, 0x9, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7e, 0x0, 0xc3}, - "JLS": {0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x76, 0x72, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x76, 0x69, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x76, 0x60, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x76, 0x52, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x76, 0x49, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x76, 0x40, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x76, 0x32, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x76, 0x29, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x76, 0x20, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x76, 0x12, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x76, 0x9, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x76, 0x0, 0xc3}, - "JLT": {0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7c, 0x72, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7c, 0x69, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7c, 0x60, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7c, 0x52, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7c, 0x49, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7c, 0x40, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7c, 0x32, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7c, 0x29, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7c, 0x20, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7c, 0x12, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7c, 0x9, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7c, 0x0, 0xc3}, - "JMI": {0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x78, 0x63, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x78, 0x5a, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x78, 0x51, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x78, 0x48, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x78, 0x3f, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x78, 0x36, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x78, 0x2d, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x78, 0x24, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x78, 0x1b, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x78, 0x12, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x78, 0x9, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x78, 0x0, 0xc3}, - "JNE": {0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x75, 0x72, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x75, 0x69, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x75, 0x60, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x75, 0x52, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x75, 0x49, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x75, 0x40, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x75, 0x32, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x75, 0x29, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x75, 0x20, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x75, 0x12, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x75, 0x9, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x75, 0x0, 0xc3}, - "JPC": {0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7b, 0x63, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7b, 0x5a, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7b, 0x51, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7b, 0x48, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7b, 0x3f, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7b, 0x36, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7b, 0x2d, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7b, 0x24, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7b, 0x1b, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7b, 0x12, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7b, 0x9, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7b, 0x0, 0xc3}, - "JPS": {0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7a, 0x63, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7a, 0x5a, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7a, 0x51, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7a, 0x48, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7a, 0x3f, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7a, 0x36, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7a, 0x2d, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7a, 0x24, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7a, 0x1b, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7a, 0x12, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7a, 0x9, 0x49, 0x81, 0xc2, 0xd2, 0x4, 0x0, 0x0, 0x7a, 0x0, 0xc3}, - }, - }, - { - name: "SUBL", - setupFn: func(assembler Assembler) { - assembler.CompileRegisterToRegister(SUBL, RegR10, RegAX) - }, - jmpInstToExpectedBytes: map[string][]uint8{ - "JCC": {0x44, 0x29, 0xd0, 0x73, 0x39, 0x44, 0x29, 0xd0, 0x73, 0x34, 0x44, 0x29, 0xd0, 0x73, 0x2f, 0x44, 0x29, 0xd0, 0x73, 0x2a, 0x44, 0x29, 0xd0, 0x73, 0x25, 0x44, 0x29, 0xd0, 0x73, 0x20, 0x66, 0x90, 0x44, 0x29, 0xd0, 0x73, 0x19, 0x44, 0x29, 0xd0, 0x73, 0x14, 0x44, 0x29, 0xd0, 0x73, 0xf, 0x44, 0x29, 0xd0, 0x73, 0xa, 0x44, 0x29, 0xd0, 0x73, 0x5, 0x44, 0x29, 0xd0, 0x73, 0x0, 0xc3}, - "JCS": {0x44, 0x29, 0xd0, 0x72, 0x39, 0x44, 0x29, 0xd0, 0x72, 0x34, 0x44, 0x29, 0xd0, 0x72, 0x2f, 0x44, 0x29, 0xd0, 0x72, 0x2a, 0x44, 0x29, 0xd0, 0x72, 0x25, 0x44, 0x29, 0xd0, 0x72, 0x20, 0x66, 0x90, 0x44, 0x29, 0xd0, 0x72, 0x19, 0x44, 0x29, 0xd0, 0x72, 0x14, 0x44, 0x29, 0xd0, 0x72, 0xf, 0x44, 0x29, 0xd0, 0x72, 0xa, 0x44, 0x29, 0xd0, 0x72, 0x5, 0x44, 0x29, 0xd0, 0x72, 0x0, 0xc3}, - "JEQ": {0x44, 0x29, 0xd0, 0x74, 0x39, 0x44, 0x29, 0xd0, 0x74, 0x34, 0x44, 0x29, 0xd0, 0x74, 0x2f, 0x44, 0x29, 0xd0, 0x74, 0x2a, 0x44, 0x29, 0xd0, 0x74, 0x25, 0x44, 0x29, 0xd0, 0x74, 0x20, 0x66, 0x90, 0x44, 0x29, 0xd0, 0x74, 0x19, 0x44, 0x29, 0xd0, 0x74, 0x14, 0x44, 0x29, 0xd0, 0x74, 0xf, 0x44, 0x29, 0xd0, 0x74, 0xa, 0x44, 0x29, 0xd0, 0x74, 0x5, 0x44, 0x29, 0xd0, 0x74, 0x0, 0xc3}, - "JGE": {0x44, 0x29, 0xd0, 0x7d, 0x39, 0x44, 0x29, 0xd0, 0x7d, 0x34, 0x44, 0x29, 0xd0, 0x7d, 0x2f, 0x44, 0x29, 0xd0, 0x7d, 0x2a, 0x44, 0x29, 0xd0, 0x7d, 0x25, 0x44, 0x29, 0xd0, 0x7d, 0x20, 0x66, 0x90, 0x44, 0x29, 0xd0, 0x7d, 0x19, 0x44, 0x29, 0xd0, 0x7d, 0x14, 0x44, 0x29, 0xd0, 0x7d, 0xf, 0x44, 0x29, 0xd0, 0x7d, 0xa, 0x44, 0x29, 0xd0, 0x7d, 0x5, 0x44, 0x29, 0xd0, 0x7d, 0x0, 0xc3}, - "JGT": {0x44, 0x29, 0xd0, 0x7f, 0x39, 0x44, 0x29, 0xd0, 0x7f, 0x34, 0x44, 0x29, 0xd0, 0x7f, 0x2f, 0x44, 0x29, 0xd0, 0x7f, 0x2a, 0x44, 0x29, 0xd0, 0x7f, 0x25, 0x44, 0x29, 0xd0, 0x7f, 0x20, 0x66, 0x90, 0x44, 0x29, 0xd0, 0x7f, 0x19, 0x44, 0x29, 0xd0, 0x7f, 0x14, 0x44, 0x29, 0xd0, 0x7f, 0xf, 0x44, 0x29, 0xd0, 0x7f, 0xa, 0x44, 0x29, 0xd0, 0x7f, 0x5, 0x44, 0x29, 0xd0, 0x7f, 0x0, 0xc3}, - "JHI": {0x44, 0x29, 0xd0, 0x77, 0x39, 0x44, 0x29, 0xd0, 0x77, 0x34, 0x44, 0x29, 0xd0, 0x77, 0x2f, 0x44, 0x29, 0xd0, 0x77, 0x2a, 0x44, 0x29, 0xd0, 0x77, 0x25, 0x44, 0x29, 0xd0, 0x77, 0x20, 0x66, 0x90, 0x44, 0x29, 0xd0, 0x77, 0x19, 0x44, 0x29, 0xd0, 0x77, 0x14, 0x44, 0x29, 0xd0, 0x77, 0xf, 0x44, 0x29, 0xd0, 0x77, 0xa, 0x44, 0x29, 0xd0, 0x77, 0x5, 0x44, 0x29, 0xd0, 0x77, 0x0, 0xc3}, - "JLE": {0x44, 0x29, 0xd0, 0x7e, 0x39, 0x44, 0x29, 0xd0, 0x7e, 0x34, 0x44, 0x29, 0xd0, 0x7e, 0x2f, 0x44, 0x29, 0xd0, 0x7e, 0x2a, 0x44, 0x29, 0xd0, 0x7e, 0x25, 0x44, 0x29, 0xd0, 0x7e, 0x20, 0x66, 0x90, 0x44, 0x29, 0xd0, 0x7e, 0x19, 0x44, 0x29, 0xd0, 0x7e, 0x14, 0x44, 0x29, 0xd0, 0x7e, 0xf, 0x44, 0x29, 0xd0, 0x7e, 0xa, 0x44, 0x29, 0xd0, 0x7e, 0x5, 0x44, 0x29, 0xd0, 0x7e, 0x0, 0xc3}, - "JLS": {0x44, 0x29, 0xd0, 0x76, 0x39, 0x44, 0x29, 0xd0, 0x76, 0x34, 0x44, 0x29, 0xd0, 0x76, 0x2f, 0x44, 0x29, 0xd0, 0x76, 0x2a, 0x44, 0x29, 0xd0, 0x76, 0x25, 0x44, 0x29, 0xd0, 0x76, 0x20, 0x66, 0x90, 0x44, 0x29, 0xd0, 0x76, 0x19, 0x44, 0x29, 0xd0, 0x76, 0x14, 0x44, 0x29, 0xd0, 0x76, 0xf, 0x44, 0x29, 0xd0, 0x76, 0xa, 0x44, 0x29, 0xd0, 0x76, 0x5, 0x44, 0x29, 0xd0, 0x76, 0x0, 0xc3}, - "JLT": {0x44, 0x29, 0xd0, 0x7c, 0x39, 0x44, 0x29, 0xd0, 0x7c, 0x34, 0x44, 0x29, 0xd0, 0x7c, 0x2f, 0x44, 0x29, 0xd0, 0x7c, 0x2a, 0x44, 0x29, 0xd0, 0x7c, 0x25, 0x44, 0x29, 0xd0, 0x7c, 0x20, 0x66, 0x90, 0x44, 0x29, 0xd0, 0x7c, 0x19, 0x44, 0x29, 0xd0, 0x7c, 0x14, 0x44, 0x29, 0xd0, 0x7c, 0xf, 0x44, 0x29, 0xd0, 0x7c, 0xa, 0x44, 0x29, 0xd0, 0x7c, 0x5, 0x44, 0x29, 0xd0, 0x7c, 0x0, 0xc3}, - "JMI": {0x44, 0x29, 0xd0, 0x78, 0x37, 0x44, 0x29, 0xd0, 0x78, 0x32, 0x44, 0x29, 0xd0, 0x78, 0x2d, 0x44, 0x29, 0xd0, 0x78, 0x28, 0x44, 0x29, 0xd0, 0x78, 0x23, 0x44, 0x29, 0xd0, 0x78, 0x1e, 0x44, 0x29, 0xd0, 0x78, 0x19, 0x44, 0x29, 0xd0, 0x78, 0x14, 0x44, 0x29, 0xd0, 0x78, 0xf, 0x44, 0x29, 0xd0, 0x78, 0xa, 0x44, 0x29, 0xd0, 0x78, 0x5, 0x44, 0x29, 0xd0, 0x78, 0x0, 0xc3}, - "JNE": {0x44, 0x29, 0xd0, 0x75, 0x39, 0x44, 0x29, 0xd0, 0x75, 0x34, 0x44, 0x29, 0xd0, 0x75, 0x2f, 0x44, 0x29, 0xd0, 0x75, 0x2a, 0x44, 0x29, 0xd0, 0x75, 0x25, 0x44, 0x29, 0xd0, 0x75, 0x20, 0x66, 0x90, 0x44, 0x29, 0xd0, 0x75, 0x19, 0x44, 0x29, 0xd0, 0x75, 0x14, 0x44, 0x29, 0xd0, 0x75, 0xf, 0x44, 0x29, 0xd0, 0x75, 0xa, 0x44, 0x29, 0xd0, 0x75, 0x5, 0x44, 0x29, 0xd0, 0x75, 0x0, 0xc3}, - "JPC": {0x44, 0x29, 0xd0, 0x7b, 0x37, 0x44, 0x29, 0xd0, 0x7b, 0x32, 0x44, 0x29, 0xd0, 0x7b, 0x2d, 0x44, 0x29, 0xd0, 0x7b, 0x28, 0x44, 0x29, 0xd0, 0x7b, 0x23, 0x44, 0x29, 0xd0, 0x7b, 0x1e, 0x44, 0x29, 0xd0, 0x7b, 0x19, 0x44, 0x29, 0xd0, 0x7b, 0x14, 0x44, 0x29, 0xd0, 0x7b, 0xf, 0x44, 0x29, 0xd0, 0x7b, 0xa, 0x44, 0x29, 0xd0, 0x7b, 0x5, 0x44, 0x29, 0xd0, 0x7b, 0x0, 0xc3}, - "JPS": {0x44, 0x29, 0xd0, 0x7a, 0x37, 0x44, 0x29, 0xd0, 0x7a, 0x32, 0x44, 0x29, 0xd0, 0x7a, 0x2d, 0x44, 0x29, 0xd0, 0x7a, 0x28, 0x44, 0x29, 0xd0, 0x7a, 0x23, 0x44, 0x29, 0xd0, 0x7a, 0x1e, 0x44, 0x29, 0xd0, 0x7a, 0x19, 0x44, 0x29, 0xd0, 0x7a, 0x14, 0x44, 0x29, 0xd0, 0x7a, 0xf, 0x44, 0x29, 0xd0, 0x7a, 0xa, 0x44, 0x29, 0xd0, 0x7a, 0x5, 0x44, 0x29, 0xd0, 0x7a, 0x0, 0xc3}, - }, - }, - { - name: "SUBQ (register to register)", - setupFn: func(assembler Assembler) { - assembler.CompileRegisterToRegister(SUBQ, RegR10, RegAX) - }, - jmpInstToExpectedBytes: map[string][]uint8{ - "JCC": {0x4c, 0x29, 0xd0, 0x73, 0x39, 0x4c, 0x29, 0xd0, 0x73, 0x34, 0x4c, 0x29, 0xd0, 0x73, 0x2f, 0x4c, 0x29, 0xd0, 0x73, 0x2a, 0x4c, 0x29, 0xd0, 0x73, 0x25, 0x4c, 0x29, 0xd0, 0x73, 0x20, 0x66, 0x90, 0x4c, 0x29, 0xd0, 0x73, 0x19, 0x4c, 0x29, 0xd0, 0x73, 0x14, 0x4c, 0x29, 0xd0, 0x73, 0xf, 0x4c, 0x29, 0xd0, 0x73, 0xa, 0x4c, 0x29, 0xd0, 0x73, 0x5, 0x4c, 0x29, 0xd0, 0x73, 0x0, 0xc3}, - "JCS": {0x4c, 0x29, 0xd0, 0x72, 0x39, 0x4c, 0x29, 0xd0, 0x72, 0x34, 0x4c, 0x29, 0xd0, 0x72, 0x2f, 0x4c, 0x29, 0xd0, 0x72, 0x2a, 0x4c, 0x29, 0xd0, 0x72, 0x25, 0x4c, 0x29, 0xd0, 0x72, 0x20, 0x66, 0x90, 0x4c, 0x29, 0xd0, 0x72, 0x19, 0x4c, 0x29, 0xd0, 0x72, 0x14, 0x4c, 0x29, 0xd0, 0x72, 0xf, 0x4c, 0x29, 0xd0, 0x72, 0xa, 0x4c, 0x29, 0xd0, 0x72, 0x5, 0x4c, 0x29, 0xd0, 0x72, 0x0, 0xc3}, - "JEQ": {0x4c, 0x29, 0xd0, 0x74, 0x39, 0x4c, 0x29, 0xd0, 0x74, 0x34, 0x4c, 0x29, 0xd0, 0x74, 0x2f, 0x4c, 0x29, 0xd0, 0x74, 0x2a, 0x4c, 0x29, 0xd0, 0x74, 0x25, 0x4c, 0x29, 0xd0, 0x74, 0x20, 0x66, 0x90, 0x4c, 0x29, 0xd0, 0x74, 0x19, 0x4c, 0x29, 0xd0, 0x74, 0x14, 0x4c, 0x29, 0xd0, 0x74, 0xf, 0x4c, 0x29, 0xd0, 0x74, 0xa, 0x4c, 0x29, 0xd0, 0x74, 0x5, 0x4c, 0x29, 0xd0, 0x74, 0x0, 0xc3}, - "JGE": {0x4c, 0x29, 0xd0, 0x7d, 0x39, 0x4c, 0x29, 0xd0, 0x7d, 0x34, 0x4c, 0x29, 0xd0, 0x7d, 0x2f, 0x4c, 0x29, 0xd0, 0x7d, 0x2a, 0x4c, 0x29, 0xd0, 0x7d, 0x25, 0x4c, 0x29, 0xd0, 0x7d, 0x20, 0x66, 0x90, 0x4c, 0x29, 0xd0, 0x7d, 0x19, 0x4c, 0x29, 0xd0, 0x7d, 0x14, 0x4c, 0x29, 0xd0, 0x7d, 0xf, 0x4c, 0x29, 0xd0, 0x7d, 0xa, 0x4c, 0x29, 0xd0, 0x7d, 0x5, 0x4c, 0x29, 0xd0, 0x7d, 0x0, 0xc3}, - "JGT": {0x4c, 0x29, 0xd0, 0x7f, 0x39, 0x4c, 0x29, 0xd0, 0x7f, 0x34, 0x4c, 0x29, 0xd0, 0x7f, 0x2f, 0x4c, 0x29, 0xd0, 0x7f, 0x2a, 0x4c, 0x29, 0xd0, 0x7f, 0x25, 0x4c, 0x29, 0xd0, 0x7f, 0x20, 0x66, 0x90, 0x4c, 0x29, 0xd0, 0x7f, 0x19, 0x4c, 0x29, 0xd0, 0x7f, 0x14, 0x4c, 0x29, 0xd0, 0x7f, 0xf, 0x4c, 0x29, 0xd0, 0x7f, 0xa, 0x4c, 0x29, 0xd0, 0x7f, 0x5, 0x4c, 0x29, 0xd0, 0x7f, 0x0, 0xc3}, - "JHI": {0x4c, 0x29, 0xd0, 0x77, 0x39, 0x4c, 0x29, 0xd0, 0x77, 0x34, 0x4c, 0x29, 0xd0, 0x77, 0x2f, 0x4c, 0x29, 0xd0, 0x77, 0x2a, 0x4c, 0x29, 0xd0, 0x77, 0x25, 0x4c, 0x29, 0xd0, 0x77, 0x20, 0x66, 0x90, 0x4c, 0x29, 0xd0, 0x77, 0x19, 0x4c, 0x29, 0xd0, 0x77, 0x14, 0x4c, 0x29, 0xd0, 0x77, 0xf, 0x4c, 0x29, 0xd0, 0x77, 0xa, 0x4c, 0x29, 0xd0, 0x77, 0x5, 0x4c, 0x29, 0xd0, 0x77, 0x0, 0xc3}, - "JLE": {0x4c, 0x29, 0xd0, 0x7e, 0x39, 0x4c, 0x29, 0xd0, 0x7e, 0x34, 0x4c, 0x29, 0xd0, 0x7e, 0x2f, 0x4c, 0x29, 0xd0, 0x7e, 0x2a, 0x4c, 0x29, 0xd0, 0x7e, 0x25, 0x4c, 0x29, 0xd0, 0x7e, 0x20, 0x66, 0x90, 0x4c, 0x29, 0xd0, 0x7e, 0x19, 0x4c, 0x29, 0xd0, 0x7e, 0x14, 0x4c, 0x29, 0xd0, 0x7e, 0xf, 0x4c, 0x29, 0xd0, 0x7e, 0xa, 0x4c, 0x29, 0xd0, 0x7e, 0x5, 0x4c, 0x29, 0xd0, 0x7e, 0x0, 0xc3}, - "JLS": {0x4c, 0x29, 0xd0, 0x76, 0x39, 0x4c, 0x29, 0xd0, 0x76, 0x34, 0x4c, 0x29, 0xd0, 0x76, 0x2f, 0x4c, 0x29, 0xd0, 0x76, 0x2a, 0x4c, 0x29, 0xd0, 0x76, 0x25, 0x4c, 0x29, 0xd0, 0x76, 0x20, 0x66, 0x90, 0x4c, 0x29, 0xd0, 0x76, 0x19, 0x4c, 0x29, 0xd0, 0x76, 0x14, 0x4c, 0x29, 0xd0, 0x76, 0xf, 0x4c, 0x29, 0xd0, 0x76, 0xa, 0x4c, 0x29, 0xd0, 0x76, 0x5, 0x4c, 0x29, 0xd0, 0x76, 0x0, 0xc3}, - "JLT": {0x4c, 0x29, 0xd0, 0x7c, 0x39, 0x4c, 0x29, 0xd0, 0x7c, 0x34, 0x4c, 0x29, 0xd0, 0x7c, 0x2f, 0x4c, 0x29, 0xd0, 0x7c, 0x2a, 0x4c, 0x29, 0xd0, 0x7c, 0x25, 0x4c, 0x29, 0xd0, 0x7c, 0x20, 0x66, 0x90, 0x4c, 0x29, 0xd0, 0x7c, 0x19, 0x4c, 0x29, 0xd0, 0x7c, 0x14, 0x4c, 0x29, 0xd0, 0x7c, 0xf, 0x4c, 0x29, 0xd0, 0x7c, 0xa, 0x4c, 0x29, 0xd0, 0x7c, 0x5, 0x4c, 0x29, 0xd0, 0x7c, 0x0, 0xc3}, - "JMI": {0x4c, 0x29, 0xd0, 0x78, 0x37, 0x4c, 0x29, 0xd0, 0x78, 0x32, 0x4c, 0x29, 0xd0, 0x78, 0x2d, 0x4c, 0x29, 0xd0, 0x78, 0x28, 0x4c, 0x29, 0xd0, 0x78, 0x23, 0x4c, 0x29, 0xd0, 0x78, 0x1e, 0x4c, 0x29, 0xd0, 0x78, 0x19, 0x4c, 0x29, 0xd0, 0x78, 0x14, 0x4c, 0x29, 0xd0, 0x78, 0xf, 0x4c, 0x29, 0xd0, 0x78, 0xa, 0x4c, 0x29, 0xd0, 0x78, 0x5, 0x4c, 0x29, 0xd0, 0x78, 0x0, 0xc3}, - "JNE": {0x4c, 0x29, 0xd0, 0x75, 0x39, 0x4c, 0x29, 0xd0, 0x75, 0x34, 0x4c, 0x29, 0xd0, 0x75, 0x2f, 0x4c, 0x29, 0xd0, 0x75, 0x2a, 0x4c, 0x29, 0xd0, 0x75, 0x25, 0x4c, 0x29, 0xd0, 0x75, 0x20, 0x66, 0x90, 0x4c, 0x29, 0xd0, 0x75, 0x19, 0x4c, 0x29, 0xd0, 0x75, 0x14, 0x4c, 0x29, 0xd0, 0x75, 0xf, 0x4c, 0x29, 0xd0, 0x75, 0xa, 0x4c, 0x29, 0xd0, 0x75, 0x5, 0x4c, 0x29, 0xd0, 0x75, 0x0, 0xc3}, - "JPC": {0x4c, 0x29, 0xd0, 0x7b, 0x37, 0x4c, 0x29, 0xd0, 0x7b, 0x32, 0x4c, 0x29, 0xd0, 0x7b, 0x2d, 0x4c, 0x29, 0xd0, 0x7b, 0x28, 0x4c, 0x29, 0xd0, 0x7b, 0x23, 0x4c, 0x29, 0xd0, 0x7b, 0x1e, 0x4c, 0x29, 0xd0, 0x7b, 0x19, 0x4c, 0x29, 0xd0, 0x7b, 0x14, 0x4c, 0x29, 0xd0, 0x7b, 0xf, 0x4c, 0x29, 0xd0, 0x7b, 0xa, 0x4c, 0x29, 0xd0, 0x7b, 0x5, 0x4c, 0x29, 0xd0, 0x7b, 0x0, 0xc3}, - "JPS": {0x4c, 0x29, 0xd0, 0x7a, 0x37, 0x4c, 0x29, 0xd0, 0x7a, 0x32, 0x4c, 0x29, 0xd0, 0x7a, 0x2d, 0x4c, 0x29, 0xd0, 0x7a, 0x28, 0x4c, 0x29, 0xd0, 0x7a, 0x23, 0x4c, 0x29, 0xd0, 0x7a, 0x1e, 0x4c, 0x29, 0xd0, 0x7a, 0x19, 0x4c, 0x29, 0xd0, 0x7a, 0x14, 0x4c, 0x29, 0xd0, 0x7a, 0xf, 0x4c, 0x29, 0xd0, 0x7a, 0xa, 0x4c, 0x29, 0xd0, 0x7a, 0x5, 0x4c, 0x29, 0xd0, 0x7a, 0x0, 0xc3}, - }, - }, - { - name: "SUBQ (memory to register)", - setupFn: func(assembler Assembler) { - assembler.CompileMemoryToRegister(SUBQ, RegR10, math.MaxInt16, RegAX) - }, - jmpInstToExpectedBytes: map[string][]uint8{ - "JCC": {0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x73, 0x72, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x73, 0x69, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x73, 0x60, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x73, 0x52, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x73, 0x49, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x73, 0x40, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x73, 0x32, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x73, 0x29, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x73, 0x20, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x73, 0x12, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x73, 0x9, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x73, 0x0, 0xc3}, - "JCS": {0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x72, 0x72, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x72, 0x69, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x72, 0x60, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x72, 0x52, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x72, 0x49, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x72, 0x40, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x72, 0x32, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x72, 0x29, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x72, 0x20, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x72, 0x12, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x72, 0x9, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x72, 0x0, 0xc3}, - "JEQ": {0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x74, 0x72, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x74, 0x69, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x74, 0x60, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x74, 0x52, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x74, 0x49, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x74, 0x40, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x74, 0x32, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x74, 0x29, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x74, 0x20, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x74, 0x12, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x74, 0x9, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x74, 0x0, 0xc3}, - "JGE": {0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7d, 0x72, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7d, 0x69, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7d, 0x60, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7d, 0x52, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7d, 0x49, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7d, 0x40, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7d, 0x32, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7d, 0x29, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7d, 0x20, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7d, 0x12, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7d, 0x9, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7d, 0x0, 0xc3}, - "JGT": {0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7f, 0x72, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7f, 0x69, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7f, 0x60, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7f, 0x52, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7f, 0x49, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7f, 0x40, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7f, 0x32, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7f, 0x29, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7f, 0x20, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7f, 0x12, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7f, 0x9, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7f, 0x0, 0xc3}, - "JHI": {0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x77, 0x72, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x77, 0x69, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x77, 0x60, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x77, 0x52, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x77, 0x49, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x77, 0x40, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x77, 0x32, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x77, 0x29, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x77, 0x20, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x77, 0x12, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x77, 0x9, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x77, 0x0, 0xc3}, - "JLE": {0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7e, 0x72, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7e, 0x69, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7e, 0x60, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7e, 0x52, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7e, 0x49, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7e, 0x40, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7e, 0x32, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7e, 0x29, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7e, 0x20, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7e, 0x12, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7e, 0x9, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7e, 0x0, 0xc3}, - "JLS": {0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x76, 0x72, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x76, 0x69, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x76, 0x60, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x76, 0x52, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x76, 0x49, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x76, 0x40, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x76, 0x32, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x76, 0x29, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x76, 0x20, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x76, 0x12, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x76, 0x9, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x76, 0x0, 0xc3}, - "JLT": {0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7c, 0x72, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7c, 0x69, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7c, 0x60, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7c, 0x52, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7c, 0x49, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7c, 0x40, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7c, 0x32, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7c, 0x29, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7c, 0x20, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7c, 0x12, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7c, 0x9, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7c, 0x0, 0xc3}, - "JMI": {0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x78, 0x63, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x78, 0x5a, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x78, 0x51, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x78, 0x48, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x78, 0x3f, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x78, 0x36, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x78, 0x2d, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x78, 0x24, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x78, 0x1b, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x78, 0x12, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x78, 0x9, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x78, 0x0, 0xc3}, - "JNE": {0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x75, 0x72, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x75, 0x69, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x75, 0x60, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x75, 0x52, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x75, 0x49, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x75, 0x40, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x75, 0x32, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x75, 0x29, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x75, 0x20, 0xf, 0x1f, 0x44, 0x0, 0x0, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x75, 0x12, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x75, 0x9, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x75, 0x0, 0xc3}, - "JPC": {0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7b, 0x63, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7b, 0x5a, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7b, 0x51, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7b, 0x48, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7b, 0x3f, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7b, 0x36, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7b, 0x2d, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7b, 0x24, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7b, 0x1b, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7b, 0x12, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7b, 0x9, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7b, 0x0, 0xc3}, - "JPS": {0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7a, 0x63, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7a, 0x5a, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7a, 0x51, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7a, 0x48, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7a, 0x3f, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7a, 0x36, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7a, 0x2d, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7a, 0x24, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7a, 0x1b, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7a, 0x12, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7a, 0x9, 0x49, 0x2b, 0x82, 0xff, 0x7f, 0x0, 0x0, 0x7a, 0x0, 0xc3}, - }, - }, - { - name: "ANDL", - setupFn: func(assembler Assembler) { - assembler.CompileRegisterToRegister(ANDL, RegR10, RegAX) - }, - jmpInstToExpectedBytes: map[string][]uint8{ - "JCC": {0x44, 0x21, 0xd0, 0x73, 0x39, 0x44, 0x21, 0xd0, 0x73, 0x34, 0x44, 0x21, 0xd0, 0x73, 0x2f, 0x44, 0x21, 0xd0, 0x73, 0x2a, 0x44, 0x21, 0xd0, 0x73, 0x25, 0x44, 0x21, 0xd0, 0x73, 0x20, 0x66, 0x90, 0x44, 0x21, 0xd0, 0x73, 0x19, 0x44, 0x21, 0xd0, 0x73, 0x14, 0x44, 0x21, 0xd0, 0x73, 0xf, 0x44, 0x21, 0xd0, 0x73, 0xa, 0x44, 0x21, 0xd0, 0x73, 0x5, 0x44, 0x21, 0xd0, 0x73, 0x0, 0xc3}, - "JCS": {0x44, 0x21, 0xd0, 0x72, 0x39, 0x44, 0x21, 0xd0, 0x72, 0x34, 0x44, 0x21, 0xd0, 0x72, 0x2f, 0x44, 0x21, 0xd0, 0x72, 0x2a, 0x44, 0x21, 0xd0, 0x72, 0x25, 0x44, 0x21, 0xd0, 0x72, 0x20, 0x66, 0x90, 0x44, 0x21, 0xd0, 0x72, 0x19, 0x44, 0x21, 0xd0, 0x72, 0x14, 0x44, 0x21, 0xd0, 0x72, 0xf, 0x44, 0x21, 0xd0, 0x72, 0xa, 0x44, 0x21, 0xd0, 0x72, 0x5, 0x44, 0x21, 0xd0, 0x72, 0x0, 0xc3}, - "JEQ": {0x44, 0x21, 0xd0, 0x74, 0x39, 0x44, 0x21, 0xd0, 0x74, 0x34, 0x44, 0x21, 0xd0, 0x74, 0x2f, 0x44, 0x21, 0xd0, 0x74, 0x2a, 0x44, 0x21, 0xd0, 0x74, 0x25, 0x44, 0x21, 0xd0, 0x74, 0x20, 0x66, 0x90, 0x44, 0x21, 0xd0, 0x74, 0x19, 0x44, 0x21, 0xd0, 0x74, 0x14, 0x44, 0x21, 0xd0, 0x74, 0xf, 0x44, 0x21, 0xd0, 0x74, 0xa, 0x44, 0x21, 0xd0, 0x74, 0x5, 0x44, 0x21, 0xd0, 0x74, 0x0, 0xc3}, - "JGE": {0x44, 0x21, 0xd0, 0x7d, 0x39, 0x44, 0x21, 0xd0, 0x7d, 0x34, 0x44, 0x21, 0xd0, 0x7d, 0x2f, 0x44, 0x21, 0xd0, 0x7d, 0x2a, 0x44, 0x21, 0xd0, 0x7d, 0x25, 0x44, 0x21, 0xd0, 0x7d, 0x20, 0x66, 0x90, 0x44, 0x21, 0xd0, 0x7d, 0x19, 0x44, 0x21, 0xd0, 0x7d, 0x14, 0x44, 0x21, 0xd0, 0x7d, 0xf, 0x44, 0x21, 0xd0, 0x7d, 0xa, 0x44, 0x21, 0xd0, 0x7d, 0x5, 0x44, 0x21, 0xd0, 0x7d, 0x0, 0xc3}, - "JGT": {0x44, 0x21, 0xd0, 0x7f, 0x39, 0x44, 0x21, 0xd0, 0x7f, 0x34, 0x44, 0x21, 0xd0, 0x7f, 0x2f, 0x44, 0x21, 0xd0, 0x7f, 0x2a, 0x44, 0x21, 0xd0, 0x7f, 0x25, 0x44, 0x21, 0xd0, 0x7f, 0x20, 0x66, 0x90, 0x44, 0x21, 0xd0, 0x7f, 0x19, 0x44, 0x21, 0xd0, 0x7f, 0x14, 0x44, 0x21, 0xd0, 0x7f, 0xf, 0x44, 0x21, 0xd0, 0x7f, 0xa, 0x44, 0x21, 0xd0, 0x7f, 0x5, 0x44, 0x21, 0xd0, 0x7f, 0x0, 0xc3}, - "JHI": {0x44, 0x21, 0xd0, 0x77, 0x39, 0x44, 0x21, 0xd0, 0x77, 0x34, 0x44, 0x21, 0xd0, 0x77, 0x2f, 0x44, 0x21, 0xd0, 0x77, 0x2a, 0x44, 0x21, 0xd0, 0x77, 0x25, 0x44, 0x21, 0xd0, 0x77, 0x20, 0x66, 0x90, 0x44, 0x21, 0xd0, 0x77, 0x19, 0x44, 0x21, 0xd0, 0x77, 0x14, 0x44, 0x21, 0xd0, 0x77, 0xf, 0x44, 0x21, 0xd0, 0x77, 0xa, 0x44, 0x21, 0xd0, 0x77, 0x5, 0x44, 0x21, 0xd0, 0x77, 0x0, 0xc3}, - "JLE": {0x44, 0x21, 0xd0, 0x7e, 0x39, 0x44, 0x21, 0xd0, 0x7e, 0x34, 0x44, 0x21, 0xd0, 0x7e, 0x2f, 0x44, 0x21, 0xd0, 0x7e, 0x2a, 0x44, 0x21, 0xd0, 0x7e, 0x25, 0x44, 0x21, 0xd0, 0x7e, 0x20, 0x66, 0x90, 0x44, 0x21, 0xd0, 0x7e, 0x19, 0x44, 0x21, 0xd0, 0x7e, 0x14, 0x44, 0x21, 0xd0, 0x7e, 0xf, 0x44, 0x21, 0xd0, 0x7e, 0xa, 0x44, 0x21, 0xd0, 0x7e, 0x5, 0x44, 0x21, 0xd0, 0x7e, 0x0, 0xc3}, - "JLS": {0x44, 0x21, 0xd0, 0x76, 0x39, 0x44, 0x21, 0xd0, 0x76, 0x34, 0x44, 0x21, 0xd0, 0x76, 0x2f, 0x44, 0x21, 0xd0, 0x76, 0x2a, 0x44, 0x21, 0xd0, 0x76, 0x25, 0x44, 0x21, 0xd0, 0x76, 0x20, 0x66, 0x90, 0x44, 0x21, 0xd0, 0x76, 0x19, 0x44, 0x21, 0xd0, 0x76, 0x14, 0x44, 0x21, 0xd0, 0x76, 0xf, 0x44, 0x21, 0xd0, 0x76, 0xa, 0x44, 0x21, 0xd0, 0x76, 0x5, 0x44, 0x21, 0xd0, 0x76, 0x0, 0xc3}, - "JLT": {0x44, 0x21, 0xd0, 0x7c, 0x39, 0x44, 0x21, 0xd0, 0x7c, 0x34, 0x44, 0x21, 0xd0, 0x7c, 0x2f, 0x44, 0x21, 0xd0, 0x7c, 0x2a, 0x44, 0x21, 0xd0, 0x7c, 0x25, 0x44, 0x21, 0xd0, 0x7c, 0x20, 0x66, 0x90, 0x44, 0x21, 0xd0, 0x7c, 0x19, 0x44, 0x21, 0xd0, 0x7c, 0x14, 0x44, 0x21, 0xd0, 0x7c, 0xf, 0x44, 0x21, 0xd0, 0x7c, 0xa, 0x44, 0x21, 0xd0, 0x7c, 0x5, 0x44, 0x21, 0xd0, 0x7c, 0x0, 0xc3}, - "JMI": {0x44, 0x21, 0xd0, 0x78, 0x39, 0x44, 0x21, 0xd0, 0x78, 0x34, 0x44, 0x21, 0xd0, 0x78, 0x2f, 0x44, 0x21, 0xd0, 0x78, 0x2a, 0x44, 0x21, 0xd0, 0x78, 0x25, 0x44, 0x21, 0xd0, 0x78, 0x20, 0x66, 0x90, 0x44, 0x21, 0xd0, 0x78, 0x19, 0x44, 0x21, 0xd0, 0x78, 0x14, 0x44, 0x21, 0xd0, 0x78, 0xf, 0x44, 0x21, 0xd0, 0x78, 0xa, 0x44, 0x21, 0xd0, 0x78, 0x5, 0x44, 0x21, 0xd0, 0x78, 0x0, 0xc3}, - "JNE": {0x44, 0x21, 0xd0, 0x75, 0x39, 0x44, 0x21, 0xd0, 0x75, 0x34, 0x44, 0x21, 0xd0, 0x75, 0x2f, 0x44, 0x21, 0xd0, 0x75, 0x2a, 0x44, 0x21, 0xd0, 0x75, 0x25, 0x44, 0x21, 0xd0, 0x75, 0x20, 0x66, 0x90, 0x44, 0x21, 0xd0, 0x75, 0x19, 0x44, 0x21, 0xd0, 0x75, 0x14, 0x44, 0x21, 0xd0, 0x75, 0xf, 0x44, 0x21, 0xd0, 0x75, 0xa, 0x44, 0x21, 0xd0, 0x75, 0x5, 0x44, 0x21, 0xd0, 0x75, 0x0, 0xc3}, - "JPC": {0x44, 0x21, 0xd0, 0x7b, 0x39, 0x44, 0x21, 0xd0, 0x7b, 0x34, 0x44, 0x21, 0xd0, 0x7b, 0x2f, 0x44, 0x21, 0xd0, 0x7b, 0x2a, 0x44, 0x21, 0xd0, 0x7b, 0x25, 0x44, 0x21, 0xd0, 0x7b, 0x20, 0x66, 0x90, 0x44, 0x21, 0xd0, 0x7b, 0x19, 0x44, 0x21, 0xd0, 0x7b, 0x14, 0x44, 0x21, 0xd0, 0x7b, 0xf, 0x44, 0x21, 0xd0, 0x7b, 0xa, 0x44, 0x21, 0xd0, 0x7b, 0x5, 0x44, 0x21, 0xd0, 0x7b, 0x0, 0xc3}, - "JPS": {0x44, 0x21, 0xd0, 0x7a, 0x39, 0x44, 0x21, 0xd0, 0x7a, 0x34, 0x44, 0x21, 0xd0, 0x7a, 0x2f, 0x44, 0x21, 0xd0, 0x7a, 0x2a, 0x44, 0x21, 0xd0, 0x7a, 0x25, 0x44, 0x21, 0xd0, 0x7a, 0x20, 0x66, 0x90, 0x44, 0x21, 0xd0, 0x7a, 0x19, 0x44, 0x21, 0xd0, 0x7a, 0x14, 0x44, 0x21, 0xd0, 0x7a, 0xf, 0x44, 0x21, 0xd0, 0x7a, 0xa, 0x44, 0x21, 0xd0, 0x7a, 0x5, 0x44, 0x21, 0xd0, 0x7a, 0x0, 0xc3}, - }, - }, - { - name: "ANDQ (register to register)", - setupFn: func(assembler Assembler) { - assembler.CompileRegisterToRegister(ANDQ, RegR10, RegAX) - }, - jmpInstToExpectedBytes: map[string][]uint8{ - "JCC": {0x4c, 0x21, 0xd0, 0x73, 0x39, 0x4c, 0x21, 0xd0, 0x73, 0x34, 0x4c, 0x21, 0xd0, 0x73, 0x2f, 0x4c, 0x21, 0xd0, 0x73, 0x2a, 0x4c, 0x21, 0xd0, 0x73, 0x25, 0x4c, 0x21, 0xd0, 0x73, 0x20, 0x66, 0x90, 0x4c, 0x21, 0xd0, 0x73, 0x19, 0x4c, 0x21, 0xd0, 0x73, 0x14, 0x4c, 0x21, 0xd0, 0x73, 0xf, 0x4c, 0x21, 0xd0, 0x73, 0xa, 0x4c, 0x21, 0xd0, 0x73, 0x5, 0x4c, 0x21, 0xd0, 0x73, 0x0, 0xc3}, - "JCS": {0x4c, 0x21, 0xd0, 0x72, 0x39, 0x4c, 0x21, 0xd0, 0x72, 0x34, 0x4c, 0x21, 0xd0, 0x72, 0x2f, 0x4c, 0x21, 0xd0, 0x72, 0x2a, 0x4c, 0x21, 0xd0, 0x72, 0x25, 0x4c, 0x21, 0xd0, 0x72, 0x20, 0x66, 0x90, 0x4c, 0x21, 0xd0, 0x72, 0x19, 0x4c, 0x21, 0xd0, 0x72, 0x14, 0x4c, 0x21, 0xd0, 0x72, 0xf, 0x4c, 0x21, 0xd0, 0x72, 0xa, 0x4c, 0x21, 0xd0, 0x72, 0x5, 0x4c, 0x21, 0xd0, 0x72, 0x0, 0xc3}, - "JEQ": {0x4c, 0x21, 0xd0, 0x74, 0x39, 0x4c, 0x21, 0xd0, 0x74, 0x34, 0x4c, 0x21, 0xd0, 0x74, 0x2f, 0x4c, 0x21, 0xd0, 0x74, 0x2a, 0x4c, 0x21, 0xd0, 0x74, 0x25, 0x4c, 0x21, 0xd0, 0x74, 0x20, 0x66, 0x90, 0x4c, 0x21, 0xd0, 0x74, 0x19, 0x4c, 0x21, 0xd0, 0x74, 0x14, 0x4c, 0x21, 0xd0, 0x74, 0xf, 0x4c, 0x21, 0xd0, 0x74, 0xa, 0x4c, 0x21, 0xd0, 0x74, 0x5, 0x4c, 0x21, 0xd0, 0x74, 0x0, 0xc3}, - "JGE": {0x4c, 0x21, 0xd0, 0x7d, 0x39, 0x4c, 0x21, 0xd0, 0x7d, 0x34, 0x4c, 0x21, 0xd0, 0x7d, 0x2f, 0x4c, 0x21, 0xd0, 0x7d, 0x2a, 0x4c, 0x21, 0xd0, 0x7d, 0x25, 0x4c, 0x21, 0xd0, 0x7d, 0x20, 0x66, 0x90, 0x4c, 0x21, 0xd0, 0x7d, 0x19, 0x4c, 0x21, 0xd0, 0x7d, 0x14, 0x4c, 0x21, 0xd0, 0x7d, 0xf, 0x4c, 0x21, 0xd0, 0x7d, 0xa, 0x4c, 0x21, 0xd0, 0x7d, 0x5, 0x4c, 0x21, 0xd0, 0x7d, 0x0, 0xc3}, - "JGT": {0x4c, 0x21, 0xd0, 0x7f, 0x39, 0x4c, 0x21, 0xd0, 0x7f, 0x34, 0x4c, 0x21, 0xd0, 0x7f, 0x2f, 0x4c, 0x21, 0xd0, 0x7f, 0x2a, 0x4c, 0x21, 0xd0, 0x7f, 0x25, 0x4c, 0x21, 0xd0, 0x7f, 0x20, 0x66, 0x90, 0x4c, 0x21, 0xd0, 0x7f, 0x19, 0x4c, 0x21, 0xd0, 0x7f, 0x14, 0x4c, 0x21, 0xd0, 0x7f, 0xf, 0x4c, 0x21, 0xd0, 0x7f, 0xa, 0x4c, 0x21, 0xd0, 0x7f, 0x5, 0x4c, 0x21, 0xd0, 0x7f, 0x0, 0xc3}, - "JHI": {0x4c, 0x21, 0xd0, 0x77, 0x39, 0x4c, 0x21, 0xd0, 0x77, 0x34, 0x4c, 0x21, 0xd0, 0x77, 0x2f, 0x4c, 0x21, 0xd0, 0x77, 0x2a, 0x4c, 0x21, 0xd0, 0x77, 0x25, 0x4c, 0x21, 0xd0, 0x77, 0x20, 0x66, 0x90, 0x4c, 0x21, 0xd0, 0x77, 0x19, 0x4c, 0x21, 0xd0, 0x77, 0x14, 0x4c, 0x21, 0xd0, 0x77, 0xf, 0x4c, 0x21, 0xd0, 0x77, 0xa, 0x4c, 0x21, 0xd0, 0x77, 0x5, 0x4c, 0x21, 0xd0, 0x77, 0x0, 0xc3}, - "JLE": {0x4c, 0x21, 0xd0, 0x7e, 0x39, 0x4c, 0x21, 0xd0, 0x7e, 0x34, 0x4c, 0x21, 0xd0, 0x7e, 0x2f, 0x4c, 0x21, 0xd0, 0x7e, 0x2a, 0x4c, 0x21, 0xd0, 0x7e, 0x25, 0x4c, 0x21, 0xd0, 0x7e, 0x20, 0x66, 0x90, 0x4c, 0x21, 0xd0, 0x7e, 0x19, 0x4c, 0x21, 0xd0, 0x7e, 0x14, 0x4c, 0x21, 0xd0, 0x7e, 0xf, 0x4c, 0x21, 0xd0, 0x7e, 0xa, 0x4c, 0x21, 0xd0, 0x7e, 0x5, 0x4c, 0x21, 0xd0, 0x7e, 0x0, 0xc3}, - "JLS": {0x4c, 0x21, 0xd0, 0x76, 0x39, 0x4c, 0x21, 0xd0, 0x76, 0x34, 0x4c, 0x21, 0xd0, 0x76, 0x2f, 0x4c, 0x21, 0xd0, 0x76, 0x2a, 0x4c, 0x21, 0xd0, 0x76, 0x25, 0x4c, 0x21, 0xd0, 0x76, 0x20, 0x66, 0x90, 0x4c, 0x21, 0xd0, 0x76, 0x19, 0x4c, 0x21, 0xd0, 0x76, 0x14, 0x4c, 0x21, 0xd0, 0x76, 0xf, 0x4c, 0x21, 0xd0, 0x76, 0xa, 0x4c, 0x21, 0xd0, 0x76, 0x5, 0x4c, 0x21, 0xd0, 0x76, 0x0, 0xc3}, - "JLT": {0x4c, 0x21, 0xd0, 0x7c, 0x39, 0x4c, 0x21, 0xd0, 0x7c, 0x34, 0x4c, 0x21, 0xd0, 0x7c, 0x2f, 0x4c, 0x21, 0xd0, 0x7c, 0x2a, 0x4c, 0x21, 0xd0, 0x7c, 0x25, 0x4c, 0x21, 0xd0, 0x7c, 0x20, 0x66, 0x90, 0x4c, 0x21, 0xd0, 0x7c, 0x19, 0x4c, 0x21, 0xd0, 0x7c, 0x14, 0x4c, 0x21, 0xd0, 0x7c, 0xf, 0x4c, 0x21, 0xd0, 0x7c, 0xa, 0x4c, 0x21, 0xd0, 0x7c, 0x5, 0x4c, 0x21, 0xd0, 0x7c, 0x0, 0xc3}, - "JMI": {0x4c, 0x21, 0xd0, 0x78, 0x39, 0x4c, 0x21, 0xd0, 0x78, 0x34, 0x4c, 0x21, 0xd0, 0x78, 0x2f, 0x4c, 0x21, 0xd0, 0x78, 0x2a, 0x4c, 0x21, 0xd0, 0x78, 0x25, 0x4c, 0x21, 0xd0, 0x78, 0x20, 0x66, 0x90, 0x4c, 0x21, 0xd0, 0x78, 0x19, 0x4c, 0x21, 0xd0, 0x78, 0x14, 0x4c, 0x21, 0xd0, 0x78, 0xf, 0x4c, 0x21, 0xd0, 0x78, 0xa, 0x4c, 0x21, 0xd0, 0x78, 0x5, 0x4c, 0x21, 0xd0, 0x78, 0x0, 0xc3}, - "JNE": {0x4c, 0x21, 0xd0, 0x75, 0x39, 0x4c, 0x21, 0xd0, 0x75, 0x34, 0x4c, 0x21, 0xd0, 0x75, 0x2f, 0x4c, 0x21, 0xd0, 0x75, 0x2a, 0x4c, 0x21, 0xd0, 0x75, 0x25, 0x4c, 0x21, 0xd0, 0x75, 0x20, 0x66, 0x90, 0x4c, 0x21, 0xd0, 0x75, 0x19, 0x4c, 0x21, 0xd0, 0x75, 0x14, 0x4c, 0x21, 0xd0, 0x75, 0xf, 0x4c, 0x21, 0xd0, 0x75, 0xa, 0x4c, 0x21, 0xd0, 0x75, 0x5, 0x4c, 0x21, 0xd0, 0x75, 0x0, 0xc3}, - "JPC": {0x4c, 0x21, 0xd0, 0x7b, 0x39, 0x4c, 0x21, 0xd0, 0x7b, 0x34, 0x4c, 0x21, 0xd0, 0x7b, 0x2f, 0x4c, 0x21, 0xd0, 0x7b, 0x2a, 0x4c, 0x21, 0xd0, 0x7b, 0x25, 0x4c, 0x21, 0xd0, 0x7b, 0x20, 0x66, 0x90, 0x4c, 0x21, 0xd0, 0x7b, 0x19, 0x4c, 0x21, 0xd0, 0x7b, 0x14, 0x4c, 0x21, 0xd0, 0x7b, 0xf, 0x4c, 0x21, 0xd0, 0x7b, 0xa, 0x4c, 0x21, 0xd0, 0x7b, 0x5, 0x4c, 0x21, 0xd0, 0x7b, 0x0, 0xc3}, - "JPS": {0x4c, 0x21, 0xd0, 0x7a, 0x39, 0x4c, 0x21, 0xd0, 0x7a, 0x34, 0x4c, 0x21, 0xd0, 0x7a, 0x2f, 0x4c, 0x21, 0xd0, 0x7a, 0x2a, 0x4c, 0x21, 0xd0, 0x7a, 0x25, 0x4c, 0x21, 0xd0, 0x7a, 0x20, 0x66, 0x90, 0x4c, 0x21, 0xd0, 0x7a, 0x19, 0x4c, 0x21, 0xd0, 0x7a, 0x14, 0x4c, 0x21, 0xd0, 0x7a, 0xf, 0x4c, 0x21, 0xd0, 0x7a, 0xa, 0x4c, 0x21, 0xd0, 0x7a, 0x5, 0x4c, 0x21, 0xd0, 0x7a, 0x0, 0xc3}, - }, - }, - { - name: "ANDQ (const to register)", - setupFn: func(assembler Assembler) { - assembler.CompileConstToRegister(ANDQ, -123, RegR10) - }, - jmpInstToExpectedBytes: map[string][]uint8{ - "JCC": {0x49, 0x83, 0xe2, 0x85, 0x73, 0x46, 0x49, 0x83, 0xe2, 0x85, 0x73, 0x40, 0x49, 0x83, 0xe2, 0x85, 0x73, 0x3a, 0x49, 0x83, 0xe2, 0x85, 0x73, 0x34, 0x49, 0x83, 0xe2, 0x85, 0x73, 0x2e, 0x66, 0x90, 0x49, 0x83, 0xe2, 0x85, 0x73, 0x26, 0x49, 0x83, 0xe2, 0x85, 0x73, 0x20, 0x49, 0x83, 0xe2, 0x85, 0x73, 0x1a, 0x49, 0x83, 0xe2, 0x85, 0x73, 0x14, 0x49, 0x83, 0xe2, 0x85, 0x73, 0xe, 0x66, 0x90, 0x49, 0x83, 0xe2, 0x85, 0x73, 0x6, 0x49, 0x83, 0xe2, 0x85, 0x73, 0x0, 0xc3}, - "JCS": {0x49, 0x83, 0xe2, 0x85, 0x72, 0x46, 0x49, 0x83, 0xe2, 0x85, 0x72, 0x40, 0x49, 0x83, 0xe2, 0x85, 0x72, 0x3a, 0x49, 0x83, 0xe2, 0x85, 0x72, 0x34, 0x49, 0x83, 0xe2, 0x85, 0x72, 0x2e, 0x66, 0x90, 0x49, 0x83, 0xe2, 0x85, 0x72, 0x26, 0x49, 0x83, 0xe2, 0x85, 0x72, 0x20, 0x49, 0x83, 0xe2, 0x85, 0x72, 0x1a, 0x49, 0x83, 0xe2, 0x85, 0x72, 0x14, 0x49, 0x83, 0xe2, 0x85, 0x72, 0xe, 0x66, 0x90, 0x49, 0x83, 0xe2, 0x85, 0x72, 0x6, 0x49, 0x83, 0xe2, 0x85, 0x72, 0x0, 0xc3}, - "JEQ": {0x49, 0x83, 0xe2, 0x85, 0x74, 0x46, 0x49, 0x83, 0xe2, 0x85, 0x74, 0x40, 0x49, 0x83, 0xe2, 0x85, 0x74, 0x3a, 0x49, 0x83, 0xe2, 0x85, 0x74, 0x34, 0x49, 0x83, 0xe2, 0x85, 0x74, 0x2e, 0x66, 0x90, 0x49, 0x83, 0xe2, 0x85, 0x74, 0x26, 0x49, 0x83, 0xe2, 0x85, 0x74, 0x20, 0x49, 0x83, 0xe2, 0x85, 0x74, 0x1a, 0x49, 0x83, 0xe2, 0x85, 0x74, 0x14, 0x49, 0x83, 0xe2, 0x85, 0x74, 0xe, 0x66, 0x90, 0x49, 0x83, 0xe2, 0x85, 0x74, 0x6, 0x49, 0x83, 0xe2, 0x85, 0x74, 0x0, 0xc3}, - "JGE": {0x49, 0x83, 0xe2, 0x85, 0x7d, 0x46, 0x49, 0x83, 0xe2, 0x85, 0x7d, 0x40, 0x49, 0x83, 0xe2, 0x85, 0x7d, 0x3a, 0x49, 0x83, 0xe2, 0x85, 0x7d, 0x34, 0x49, 0x83, 0xe2, 0x85, 0x7d, 0x2e, 0x66, 0x90, 0x49, 0x83, 0xe2, 0x85, 0x7d, 0x26, 0x49, 0x83, 0xe2, 0x85, 0x7d, 0x20, 0x49, 0x83, 0xe2, 0x85, 0x7d, 0x1a, 0x49, 0x83, 0xe2, 0x85, 0x7d, 0x14, 0x49, 0x83, 0xe2, 0x85, 0x7d, 0xe, 0x66, 0x90, 0x49, 0x83, 0xe2, 0x85, 0x7d, 0x6, 0x49, 0x83, 0xe2, 0x85, 0x7d, 0x0, 0xc3}, - "JGT": {0x49, 0x83, 0xe2, 0x85, 0x7f, 0x46, 0x49, 0x83, 0xe2, 0x85, 0x7f, 0x40, 0x49, 0x83, 0xe2, 0x85, 0x7f, 0x3a, 0x49, 0x83, 0xe2, 0x85, 0x7f, 0x34, 0x49, 0x83, 0xe2, 0x85, 0x7f, 0x2e, 0x66, 0x90, 0x49, 0x83, 0xe2, 0x85, 0x7f, 0x26, 0x49, 0x83, 0xe2, 0x85, 0x7f, 0x20, 0x49, 0x83, 0xe2, 0x85, 0x7f, 0x1a, 0x49, 0x83, 0xe2, 0x85, 0x7f, 0x14, 0x49, 0x83, 0xe2, 0x85, 0x7f, 0xe, 0x66, 0x90, 0x49, 0x83, 0xe2, 0x85, 0x7f, 0x6, 0x49, 0x83, 0xe2, 0x85, 0x7f, 0x0, 0xc3}, - "JHI": {0x49, 0x83, 0xe2, 0x85, 0x77, 0x46, 0x49, 0x83, 0xe2, 0x85, 0x77, 0x40, 0x49, 0x83, 0xe2, 0x85, 0x77, 0x3a, 0x49, 0x83, 0xe2, 0x85, 0x77, 0x34, 0x49, 0x83, 0xe2, 0x85, 0x77, 0x2e, 0x66, 0x90, 0x49, 0x83, 0xe2, 0x85, 0x77, 0x26, 0x49, 0x83, 0xe2, 0x85, 0x77, 0x20, 0x49, 0x83, 0xe2, 0x85, 0x77, 0x1a, 0x49, 0x83, 0xe2, 0x85, 0x77, 0x14, 0x49, 0x83, 0xe2, 0x85, 0x77, 0xe, 0x66, 0x90, 0x49, 0x83, 0xe2, 0x85, 0x77, 0x6, 0x49, 0x83, 0xe2, 0x85, 0x77, 0x0, 0xc3}, - "JLE": {0x49, 0x83, 0xe2, 0x85, 0x7e, 0x46, 0x49, 0x83, 0xe2, 0x85, 0x7e, 0x40, 0x49, 0x83, 0xe2, 0x85, 0x7e, 0x3a, 0x49, 0x83, 0xe2, 0x85, 0x7e, 0x34, 0x49, 0x83, 0xe2, 0x85, 0x7e, 0x2e, 0x66, 0x90, 0x49, 0x83, 0xe2, 0x85, 0x7e, 0x26, 0x49, 0x83, 0xe2, 0x85, 0x7e, 0x20, 0x49, 0x83, 0xe2, 0x85, 0x7e, 0x1a, 0x49, 0x83, 0xe2, 0x85, 0x7e, 0x14, 0x49, 0x83, 0xe2, 0x85, 0x7e, 0xe, 0x66, 0x90, 0x49, 0x83, 0xe2, 0x85, 0x7e, 0x6, 0x49, 0x83, 0xe2, 0x85, 0x7e, 0x0, 0xc3}, - "JLS": {0x49, 0x83, 0xe2, 0x85, 0x76, 0x46, 0x49, 0x83, 0xe2, 0x85, 0x76, 0x40, 0x49, 0x83, 0xe2, 0x85, 0x76, 0x3a, 0x49, 0x83, 0xe2, 0x85, 0x76, 0x34, 0x49, 0x83, 0xe2, 0x85, 0x76, 0x2e, 0x66, 0x90, 0x49, 0x83, 0xe2, 0x85, 0x76, 0x26, 0x49, 0x83, 0xe2, 0x85, 0x76, 0x20, 0x49, 0x83, 0xe2, 0x85, 0x76, 0x1a, 0x49, 0x83, 0xe2, 0x85, 0x76, 0x14, 0x49, 0x83, 0xe2, 0x85, 0x76, 0xe, 0x66, 0x90, 0x49, 0x83, 0xe2, 0x85, 0x76, 0x6, 0x49, 0x83, 0xe2, 0x85, 0x76, 0x0, 0xc3}, - "JLT": {0x49, 0x83, 0xe2, 0x85, 0x7c, 0x46, 0x49, 0x83, 0xe2, 0x85, 0x7c, 0x40, 0x49, 0x83, 0xe2, 0x85, 0x7c, 0x3a, 0x49, 0x83, 0xe2, 0x85, 0x7c, 0x34, 0x49, 0x83, 0xe2, 0x85, 0x7c, 0x2e, 0x66, 0x90, 0x49, 0x83, 0xe2, 0x85, 0x7c, 0x26, 0x49, 0x83, 0xe2, 0x85, 0x7c, 0x20, 0x49, 0x83, 0xe2, 0x85, 0x7c, 0x1a, 0x49, 0x83, 0xe2, 0x85, 0x7c, 0x14, 0x49, 0x83, 0xe2, 0x85, 0x7c, 0xe, 0x66, 0x90, 0x49, 0x83, 0xe2, 0x85, 0x7c, 0x6, 0x49, 0x83, 0xe2, 0x85, 0x7c, 0x0, 0xc3}, - "JMI": {0x49, 0x83, 0xe2, 0x85, 0x78, 0x46, 0x49, 0x83, 0xe2, 0x85, 0x78, 0x40, 0x49, 0x83, 0xe2, 0x85, 0x78, 0x3a, 0x49, 0x83, 0xe2, 0x85, 0x78, 0x34, 0x49, 0x83, 0xe2, 0x85, 0x78, 0x2e, 0x66, 0x90, 0x49, 0x83, 0xe2, 0x85, 0x78, 0x26, 0x49, 0x83, 0xe2, 0x85, 0x78, 0x20, 0x49, 0x83, 0xe2, 0x85, 0x78, 0x1a, 0x49, 0x83, 0xe2, 0x85, 0x78, 0x14, 0x49, 0x83, 0xe2, 0x85, 0x78, 0xe, 0x66, 0x90, 0x49, 0x83, 0xe2, 0x85, 0x78, 0x6, 0x49, 0x83, 0xe2, 0x85, 0x78, 0x0, 0xc3}, - "JNE": {0x49, 0x83, 0xe2, 0x85, 0x75, 0x46, 0x49, 0x83, 0xe2, 0x85, 0x75, 0x40, 0x49, 0x83, 0xe2, 0x85, 0x75, 0x3a, 0x49, 0x83, 0xe2, 0x85, 0x75, 0x34, 0x49, 0x83, 0xe2, 0x85, 0x75, 0x2e, 0x66, 0x90, 0x49, 0x83, 0xe2, 0x85, 0x75, 0x26, 0x49, 0x83, 0xe2, 0x85, 0x75, 0x20, 0x49, 0x83, 0xe2, 0x85, 0x75, 0x1a, 0x49, 0x83, 0xe2, 0x85, 0x75, 0x14, 0x49, 0x83, 0xe2, 0x85, 0x75, 0xe, 0x66, 0x90, 0x49, 0x83, 0xe2, 0x85, 0x75, 0x6, 0x49, 0x83, 0xe2, 0x85, 0x75, 0x0, 0xc3}, - "JPC": {0x49, 0x83, 0xe2, 0x85, 0x7b, 0x46, 0x49, 0x83, 0xe2, 0x85, 0x7b, 0x40, 0x49, 0x83, 0xe2, 0x85, 0x7b, 0x3a, 0x49, 0x83, 0xe2, 0x85, 0x7b, 0x34, 0x49, 0x83, 0xe2, 0x85, 0x7b, 0x2e, 0x66, 0x90, 0x49, 0x83, 0xe2, 0x85, 0x7b, 0x26, 0x49, 0x83, 0xe2, 0x85, 0x7b, 0x20, 0x49, 0x83, 0xe2, 0x85, 0x7b, 0x1a, 0x49, 0x83, 0xe2, 0x85, 0x7b, 0x14, 0x49, 0x83, 0xe2, 0x85, 0x7b, 0xe, 0x66, 0x90, 0x49, 0x83, 0xe2, 0x85, 0x7b, 0x6, 0x49, 0x83, 0xe2, 0x85, 0x7b, 0x0, 0xc3}, - "JPS": {0x49, 0x83, 0xe2, 0x85, 0x7a, 0x46, 0x49, 0x83, 0xe2, 0x85, 0x7a, 0x40, 0x49, 0x83, 0xe2, 0x85, 0x7a, 0x3a, 0x49, 0x83, 0xe2, 0x85, 0x7a, 0x34, 0x49, 0x83, 0xe2, 0x85, 0x7a, 0x2e, 0x66, 0x90, 0x49, 0x83, 0xe2, 0x85, 0x7a, 0x26, 0x49, 0x83, 0xe2, 0x85, 0x7a, 0x20, 0x49, 0x83, 0xe2, 0x85, 0x7a, 0x1a, 0x49, 0x83, 0xe2, 0x85, 0x7a, 0x14, 0x49, 0x83, 0xe2, 0x85, 0x7a, 0xe, 0x66, 0x90, 0x49, 0x83, 0xe2, 0x85, 0x7a, 0x6, 0x49, 0x83, 0xe2, 0x85, 0x7a, 0x0, 0xc3}, - }, - }, - { - name: "INCQ", - setupFn: func(assembler Assembler) { - assembler.CompileNoneToMemory(INCQ, RegR10, 123) - }, - jmpInstToExpectedBytes: map[string][]uint8{ - "JCC": {0x49, 0xff, 0x42, 0x7b, 0x73, 0x42, 0x49, 0xff, 0x42, 0x7b, 0x73, 0x3c, 0x49, 0xff, 0x42, 0x7b, 0x73, 0x36, 0x49, 0xff, 0x42, 0x7b, 0x73, 0x30, 0x49, 0xff, 0x42, 0x7b, 0x73, 0x2a, 0x49, 0xff, 0x42, 0x7b, 0x73, 0x24, 0x49, 0xff, 0x42, 0x7b, 0x73, 0x1e, 0x49, 0xff, 0x42, 0x7b, 0x73, 0x18, 0x49, 0xff, 0x42, 0x7b, 0x73, 0x12, 0x49, 0xff, 0x42, 0x7b, 0x73, 0xc, 0x49, 0xff, 0x42, 0x7b, 0x73, 0x6, 0x49, 0xff, 0x42, 0x7b, 0x73, 0x0, 0xc3}, - "JCS": {0x49, 0xff, 0x42, 0x7b, 0x72, 0x42, 0x49, 0xff, 0x42, 0x7b, 0x72, 0x3c, 0x49, 0xff, 0x42, 0x7b, 0x72, 0x36, 0x49, 0xff, 0x42, 0x7b, 0x72, 0x30, 0x49, 0xff, 0x42, 0x7b, 0x72, 0x2a, 0x49, 0xff, 0x42, 0x7b, 0x72, 0x24, 0x49, 0xff, 0x42, 0x7b, 0x72, 0x1e, 0x49, 0xff, 0x42, 0x7b, 0x72, 0x18, 0x49, 0xff, 0x42, 0x7b, 0x72, 0x12, 0x49, 0xff, 0x42, 0x7b, 0x72, 0xc, 0x49, 0xff, 0x42, 0x7b, 0x72, 0x6, 0x49, 0xff, 0x42, 0x7b, 0x72, 0x0, 0xc3}, - "JEQ": {0x49, 0xff, 0x42, 0x7b, 0x74, 0x46, 0x49, 0xff, 0x42, 0x7b, 0x74, 0x40, 0x49, 0xff, 0x42, 0x7b, 0x74, 0x3a, 0x49, 0xff, 0x42, 0x7b, 0x74, 0x34, 0x49, 0xff, 0x42, 0x7b, 0x74, 0x2e, 0x66, 0x90, 0x49, 0xff, 0x42, 0x7b, 0x74, 0x26, 0x49, 0xff, 0x42, 0x7b, 0x74, 0x20, 0x49, 0xff, 0x42, 0x7b, 0x74, 0x1a, 0x49, 0xff, 0x42, 0x7b, 0x74, 0x14, 0x49, 0xff, 0x42, 0x7b, 0x74, 0xe, 0x66, 0x90, 0x49, 0xff, 0x42, 0x7b, 0x74, 0x6, 0x49, 0xff, 0x42, 0x7b, 0x74, 0x0, 0xc3}, - "JGE": {0x49, 0xff, 0x42, 0x7b, 0x7d, 0x46, 0x49, 0xff, 0x42, 0x7b, 0x7d, 0x40, 0x49, 0xff, 0x42, 0x7b, 0x7d, 0x3a, 0x49, 0xff, 0x42, 0x7b, 0x7d, 0x34, 0x49, 0xff, 0x42, 0x7b, 0x7d, 0x2e, 0x66, 0x90, 0x49, 0xff, 0x42, 0x7b, 0x7d, 0x26, 0x49, 0xff, 0x42, 0x7b, 0x7d, 0x20, 0x49, 0xff, 0x42, 0x7b, 0x7d, 0x1a, 0x49, 0xff, 0x42, 0x7b, 0x7d, 0x14, 0x49, 0xff, 0x42, 0x7b, 0x7d, 0xe, 0x66, 0x90, 0x49, 0xff, 0x42, 0x7b, 0x7d, 0x6, 0x49, 0xff, 0x42, 0x7b, 0x7d, 0x0, 0xc3}, - "JGT": {0x49, 0xff, 0x42, 0x7b, 0x7f, 0x46, 0x49, 0xff, 0x42, 0x7b, 0x7f, 0x40, 0x49, 0xff, 0x42, 0x7b, 0x7f, 0x3a, 0x49, 0xff, 0x42, 0x7b, 0x7f, 0x34, 0x49, 0xff, 0x42, 0x7b, 0x7f, 0x2e, 0x66, 0x90, 0x49, 0xff, 0x42, 0x7b, 0x7f, 0x26, 0x49, 0xff, 0x42, 0x7b, 0x7f, 0x20, 0x49, 0xff, 0x42, 0x7b, 0x7f, 0x1a, 0x49, 0xff, 0x42, 0x7b, 0x7f, 0x14, 0x49, 0xff, 0x42, 0x7b, 0x7f, 0xe, 0x66, 0x90, 0x49, 0xff, 0x42, 0x7b, 0x7f, 0x6, 0x49, 0xff, 0x42, 0x7b, 0x7f, 0x0, 0xc3}, - "JHI": {0x49, 0xff, 0x42, 0x7b, 0x77, 0x42, 0x49, 0xff, 0x42, 0x7b, 0x77, 0x3c, 0x49, 0xff, 0x42, 0x7b, 0x77, 0x36, 0x49, 0xff, 0x42, 0x7b, 0x77, 0x30, 0x49, 0xff, 0x42, 0x7b, 0x77, 0x2a, 0x49, 0xff, 0x42, 0x7b, 0x77, 0x24, 0x49, 0xff, 0x42, 0x7b, 0x77, 0x1e, 0x49, 0xff, 0x42, 0x7b, 0x77, 0x18, 0x49, 0xff, 0x42, 0x7b, 0x77, 0x12, 0x49, 0xff, 0x42, 0x7b, 0x77, 0xc, 0x49, 0xff, 0x42, 0x7b, 0x77, 0x6, 0x49, 0xff, 0x42, 0x7b, 0x77, 0x0, 0xc3}, - "JLE": {0x49, 0xff, 0x42, 0x7b, 0x7e, 0x46, 0x49, 0xff, 0x42, 0x7b, 0x7e, 0x40, 0x49, 0xff, 0x42, 0x7b, 0x7e, 0x3a, 0x49, 0xff, 0x42, 0x7b, 0x7e, 0x34, 0x49, 0xff, 0x42, 0x7b, 0x7e, 0x2e, 0x66, 0x90, 0x49, 0xff, 0x42, 0x7b, 0x7e, 0x26, 0x49, 0xff, 0x42, 0x7b, 0x7e, 0x20, 0x49, 0xff, 0x42, 0x7b, 0x7e, 0x1a, 0x49, 0xff, 0x42, 0x7b, 0x7e, 0x14, 0x49, 0xff, 0x42, 0x7b, 0x7e, 0xe, 0x66, 0x90, 0x49, 0xff, 0x42, 0x7b, 0x7e, 0x6, 0x49, 0xff, 0x42, 0x7b, 0x7e, 0x0, 0xc3}, - "JLS": {0x49, 0xff, 0x42, 0x7b, 0x76, 0x42, 0x49, 0xff, 0x42, 0x7b, 0x76, 0x3c, 0x49, 0xff, 0x42, 0x7b, 0x76, 0x36, 0x49, 0xff, 0x42, 0x7b, 0x76, 0x30, 0x49, 0xff, 0x42, 0x7b, 0x76, 0x2a, 0x49, 0xff, 0x42, 0x7b, 0x76, 0x24, 0x49, 0xff, 0x42, 0x7b, 0x76, 0x1e, 0x49, 0xff, 0x42, 0x7b, 0x76, 0x18, 0x49, 0xff, 0x42, 0x7b, 0x76, 0x12, 0x49, 0xff, 0x42, 0x7b, 0x76, 0xc, 0x49, 0xff, 0x42, 0x7b, 0x76, 0x6, 0x49, 0xff, 0x42, 0x7b, 0x76, 0x0, 0xc3}, - "JLT": {0x49, 0xff, 0x42, 0x7b, 0x7c, 0x46, 0x49, 0xff, 0x42, 0x7b, 0x7c, 0x40, 0x49, 0xff, 0x42, 0x7b, 0x7c, 0x3a, 0x49, 0xff, 0x42, 0x7b, 0x7c, 0x34, 0x49, 0xff, 0x42, 0x7b, 0x7c, 0x2e, 0x66, 0x90, 0x49, 0xff, 0x42, 0x7b, 0x7c, 0x26, 0x49, 0xff, 0x42, 0x7b, 0x7c, 0x20, 0x49, 0xff, 0x42, 0x7b, 0x7c, 0x1a, 0x49, 0xff, 0x42, 0x7b, 0x7c, 0x14, 0x49, 0xff, 0x42, 0x7b, 0x7c, 0xe, 0x66, 0x90, 0x49, 0xff, 0x42, 0x7b, 0x7c, 0x6, 0x49, 0xff, 0x42, 0x7b, 0x7c, 0x0, 0xc3}, - "JMI": {0x49, 0xff, 0x42, 0x7b, 0x78, 0x42, 0x49, 0xff, 0x42, 0x7b, 0x78, 0x3c, 0x49, 0xff, 0x42, 0x7b, 0x78, 0x36, 0x49, 0xff, 0x42, 0x7b, 0x78, 0x30, 0x49, 0xff, 0x42, 0x7b, 0x78, 0x2a, 0x49, 0xff, 0x42, 0x7b, 0x78, 0x24, 0x49, 0xff, 0x42, 0x7b, 0x78, 0x1e, 0x49, 0xff, 0x42, 0x7b, 0x78, 0x18, 0x49, 0xff, 0x42, 0x7b, 0x78, 0x12, 0x49, 0xff, 0x42, 0x7b, 0x78, 0xc, 0x49, 0xff, 0x42, 0x7b, 0x78, 0x6, 0x49, 0xff, 0x42, 0x7b, 0x78, 0x0, 0xc3}, - "JNE": {0x49, 0xff, 0x42, 0x7b, 0x75, 0x46, 0x49, 0xff, 0x42, 0x7b, 0x75, 0x40, 0x49, 0xff, 0x42, 0x7b, 0x75, 0x3a, 0x49, 0xff, 0x42, 0x7b, 0x75, 0x34, 0x49, 0xff, 0x42, 0x7b, 0x75, 0x2e, 0x66, 0x90, 0x49, 0xff, 0x42, 0x7b, 0x75, 0x26, 0x49, 0xff, 0x42, 0x7b, 0x75, 0x20, 0x49, 0xff, 0x42, 0x7b, 0x75, 0x1a, 0x49, 0xff, 0x42, 0x7b, 0x75, 0x14, 0x49, 0xff, 0x42, 0x7b, 0x75, 0xe, 0x66, 0x90, 0x49, 0xff, 0x42, 0x7b, 0x75, 0x6, 0x49, 0xff, 0x42, 0x7b, 0x75, 0x0, 0xc3}, - "JPC": {0x49, 0xff, 0x42, 0x7b, 0x7b, 0x42, 0x49, 0xff, 0x42, 0x7b, 0x7b, 0x3c, 0x49, 0xff, 0x42, 0x7b, 0x7b, 0x36, 0x49, 0xff, 0x42, 0x7b, 0x7b, 0x30, 0x49, 0xff, 0x42, 0x7b, 0x7b, 0x2a, 0x49, 0xff, 0x42, 0x7b, 0x7b, 0x24, 0x49, 0xff, 0x42, 0x7b, 0x7b, 0x1e, 0x49, 0xff, 0x42, 0x7b, 0x7b, 0x18, 0x49, 0xff, 0x42, 0x7b, 0x7b, 0x12, 0x49, 0xff, 0x42, 0x7b, 0x7b, 0xc, 0x49, 0xff, 0x42, 0x7b, 0x7b, 0x6, 0x49, 0xff, 0x42, 0x7b, 0x7b, 0x0, 0xc3}, - "JPS": {0x49, 0xff, 0x42, 0x7b, 0x7a, 0x42, 0x49, 0xff, 0x42, 0x7b, 0x7a, 0x3c, 0x49, 0xff, 0x42, 0x7b, 0x7a, 0x36, 0x49, 0xff, 0x42, 0x7b, 0x7a, 0x30, 0x49, 0xff, 0x42, 0x7b, 0x7a, 0x2a, 0x49, 0xff, 0x42, 0x7b, 0x7a, 0x24, 0x49, 0xff, 0x42, 0x7b, 0x7a, 0x1e, 0x49, 0xff, 0x42, 0x7b, 0x7a, 0x18, 0x49, 0xff, 0x42, 0x7b, 0x7a, 0x12, 0x49, 0xff, 0x42, 0x7b, 0x7a, 0xc, 0x49, 0xff, 0x42, 0x7b, 0x7a, 0x6, 0x49, 0xff, 0x42, 0x7b, 0x7a, 0x0, 0xc3}, - }, - }, - { - name: "DECQ", - setupFn: func(assembler Assembler) { - assembler.CompileNoneToMemory(DECQ, RegR10, 0) - }, - jmpInstToExpectedBytes: map[string][]uint8{ - "JCC": {0x49, 0xff, 0xa, 0x73, 0x37, 0x49, 0xff, 0xa, 0x73, 0x32, 0x49, 0xff, 0xa, 0x73, 0x2d, 0x49, 0xff, 0xa, 0x73, 0x28, 0x49, 0xff, 0xa, 0x73, 0x23, 0x49, 0xff, 0xa, 0x73, 0x1e, 0x49, 0xff, 0xa, 0x73, 0x19, 0x49, 0xff, 0xa, 0x73, 0x14, 0x49, 0xff, 0xa, 0x73, 0xf, 0x49, 0xff, 0xa, 0x73, 0xa, 0x49, 0xff, 0xa, 0x73, 0x5, 0x49, 0xff, 0xa, 0x73, 0x0, 0xc3}, - "JCS": {0x49, 0xff, 0xa, 0x72, 0x37, 0x49, 0xff, 0xa, 0x72, 0x32, 0x49, 0xff, 0xa, 0x72, 0x2d, 0x49, 0xff, 0xa, 0x72, 0x28, 0x49, 0xff, 0xa, 0x72, 0x23, 0x49, 0xff, 0xa, 0x72, 0x1e, 0x49, 0xff, 0xa, 0x72, 0x19, 0x49, 0xff, 0xa, 0x72, 0x14, 0x49, 0xff, 0xa, 0x72, 0xf, 0x49, 0xff, 0xa, 0x72, 0xa, 0x49, 0xff, 0xa, 0x72, 0x5, 0x49, 0xff, 0xa, 0x72, 0x0, 0xc3}, - "JEQ": {0x49, 0xff, 0xa, 0x74, 0x39, 0x49, 0xff, 0xa, 0x74, 0x34, 0x49, 0xff, 0xa, 0x74, 0x2f, 0x49, 0xff, 0xa, 0x74, 0x2a, 0x49, 0xff, 0xa, 0x74, 0x25, 0x49, 0xff, 0xa, 0x74, 0x20, 0x66, 0x90, 0x49, 0xff, 0xa, 0x74, 0x19, 0x49, 0xff, 0xa, 0x74, 0x14, 0x49, 0xff, 0xa, 0x74, 0xf, 0x49, 0xff, 0xa, 0x74, 0xa, 0x49, 0xff, 0xa, 0x74, 0x5, 0x49, 0xff, 0xa, 0x74, 0x0, 0xc3}, - "JGE": {0x49, 0xff, 0xa, 0x7d, 0x39, 0x49, 0xff, 0xa, 0x7d, 0x34, 0x49, 0xff, 0xa, 0x7d, 0x2f, 0x49, 0xff, 0xa, 0x7d, 0x2a, 0x49, 0xff, 0xa, 0x7d, 0x25, 0x49, 0xff, 0xa, 0x7d, 0x20, 0x66, 0x90, 0x49, 0xff, 0xa, 0x7d, 0x19, 0x49, 0xff, 0xa, 0x7d, 0x14, 0x49, 0xff, 0xa, 0x7d, 0xf, 0x49, 0xff, 0xa, 0x7d, 0xa, 0x49, 0xff, 0xa, 0x7d, 0x5, 0x49, 0xff, 0xa, 0x7d, 0x0, 0xc3}, - "JGT": {0x49, 0xff, 0xa, 0x7f, 0x39, 0x49, 0xff, 0xa, 0x7f, 0x34, 0x49, 0xff, 0xa, 0x7f, 0x2f, 0x49, 0xff, 0xa, 0x7f, 0x2a, 0x49, 0xff, 0xa, 0x7f, 0x25, 0x49, 0xff, 0xa, 0x7f, 0x20, 0x66, 0x90, 0x49, 0xff, 0xa, 0x7f, 0x19, 0x49, 0xff, 0xa, 0x7f, 0x14, 0x49, 0xff, 0xa, 0x7f, 0xf, 0x49, 0xff, 0xa, 0x7f, 0xa, 0x49, 0xff, 0xa, 0x7f, 0x5, 0x49, 0xff, 0xa, 0x7f, 0x0, 0xc3}, - "JHI": {0x49, 0xff, 0xa, 0x77, 0x37, 0x49, 0xff, 0xa, 0x77, 0x32, 0x49, 0xff, 0xa, 0x77, 0x2d, 0x49, 0xff, 0xa, 0x77, 0x28, 0x49, 0xff, 0xa, 0x77, 0x23, 0x49, 0xff, 0xa, 0x77, 0x1e, 0x49, 0xff, 0xa, 0x77, 0x19, 0x49, 0xff, 0xa, 0x77, 0x14, 0x49, 0xff, 0xa, 0x77, 0xf, 0x49, 0xff, 0xa, 0x77, 0xa, 0x49, 0xff, 0xa, 0x77, 0x5, 0x49, 0xff, 0xa, 0x77, 0x0, 0xc3}, - "JLE": {0x49, 0xff, 0xa, 0x7e, 0x39, 0x49, 0xff, 0xa, 0x7e, 0x34, 0x49, 0xff, 0xa, 0x7e, 0x2f, 0x49, 0xff, 0xa, 0x7e, 0x2a, 0x49, 0xff, 0xa, 0x7e, 0x25, 0x49, 0xff, 0xa, 0x7e, 0x20, 0x66, 0x90, 0x49, 0xff, 0xa, 0x7e, 0x19, 0x49, 0xff, 0xa, 0x7e, 0x14, 0x49, 0xff, 0xa, 0x7e, 0xf, 0x49, 0xff, 0xa, 0x7e, 0xa, 0x49, 0xff, 0xa, 0x7e, 0x5, 0x49, 0xff, 0xa, 0x7e, 0x0, 0xc3}, - "JLS": {0x49, 0xff, 0xa, 0x76, 0x37, 0x49, 0xff, 0xa, 0x76, 0x32, 0x49, 0xff, 0xa, 0x76, 0x2d, 0x49, 0xff, 0xa, 0x76, 0x28, 0x49, 0xff, 0xa, 0x76, 0x23, 0x49, 0xff, 0xa, 0x76, 0x1e, 0x49, 0xff, 0xa, 0x76, 0x19, 0x49, 0xff, 0xa, 0x76, 0x14, 0x49, 0xff, 0xa, 0x76, 0xf, 0x49, 0xff, 0xa, 0x76, 0xa, 0x49, 0xff, 0xa, 0x76, 0x5, 0x49, 0xff, 0xa, 0x76, 0x0, 0xc3}, - "JLT": {0x49, 0xff, 0xa, 0x7c, 0x39, 0x49, 0xff, 0xa, 0x7c, 0x34, 0x49, 0xff, 0xa, 0x7c, 0x2f, 0x49, 0xff, 0xa, 0x7c, 0x2a, 0x49, 0xff, 0xa, 0x7c, 0x25, 0x49, 0xff, 0xa, 0x7c, 0x20, 0x66, 0x90, 0x49, 0xff, 0xa, 0x7c, 0x19, 0x49, 0xff, 0xa, 0x7c, 0x14, 0x49, 0xff, 0xa, 0x7c, 0xf, 0x49, 0xff, 0xa, 0x7c, 0xa, 0x49, 0xff, 0xa, 0x7c, 0x5, 0x49, 0xff, 0xa, 0x7c, 0x0, 0xc3}, - "JMI": {0x49, 0xff, 0xa, 0x78, 0x37, 0x49, 0xff, 0xa, 0x78, 0x32, 0x49, 0xff, 0xa, 0x78, 0x2d, 0x49, 0xff, 0xa, 0x78, 0x28, 0x49, 0xff, 0xa, 0x78, 0x23, 0x49, 0xff, 0xa, 0x78, 0x1e, 0x49, 0xff, 0xa, 0x78, 0x19, 0x49, 0xff, 0xa, 0x78, 0x14, 0x49, 0xff, 0xa, 0x78, 0xf, 0x49, 0xff, 0xa, 0x78, 0xa, 0x49, 0xff, 0xa, 0x78, 0x5, 0x49, 0xff, 0xa, 0x78, 0x0, 0xc3}, - "JNE": {0x49, 0xff, 0xa, 0x75, 0x39, 0x49, 0xff, 0xa, 0x75, 0x34, 0x49, 0xff, 0xa, 0x75, 0x2f, 0x49, 0xff, 0xa, 0x75, 0x2a, 0x49, 0xff, 0xa, 0x75, 0x25, 0x49, 0xff, 0xa, 0x75, 0x20, 0x66, 0x90, 0x49, 0xff, 0xa, 0x75, 0x19, 0x49, 0xff, 0xa, 0x75, 0x14, 0x49, 0xff, 0xa, 0x75, 0xf, 0x49, 0xff, 0xa, 0x75, 0xa, 0x49, 0xff, 0xa, 0x75, 0x5, 0x49, 0xff, 0xa, 0x75, 0x0, 0xc3}, - "JPC": {0x49, 0xff, 0xa, 0x7b, 0x37, 0x49, 0xff, 0xa, 0x7b, 0x32, 0x49, 0xff, 0xa, 0x7b, 0x2d, 0x49, 0xff, 0xa, 0x7b, 0x28, 0x49, 0xff, 0xa, 0x7b, 0x23, 0x49, 0xff, 0xa, 0x7b, 0x1e, 0x49, 0xff, 0xa, 0x7b, 0x19, 0x49, 0xff, 0xa, 0x7b, 0x14, 0x49, 0xff, 0xa, 0x7b, 0xf, 0x49, 0xff, 0xa, 0x7b, 0xa, 0x49, 0xff, 0xa, 0x7b, 0x5, 0x49, 0xff, 0xa, 0x7b, 0x0, 0xc3}, - "JPS": {0x49, 0xff, 0xa, 0x7a, 0x37, 0x49, 0xff, 0xa, 0x7a, 0x32, 0x49, 0xff, 0xa, 0x7a, 0x2d, 0x49, 0xff, 0xa, 0x7a, 0x28, 0x49, 0xff, 0xa, 0x7a, 0x23, 0x49, 0xff, 0xa, 0x7a, 0x1e, 0x49, 0xff, 0xa, 0x7a, 0x19, 0x49, 0xff, 0xa, 0x7a, 0x14, 0x49, 0xff, 0xa, 0x7a, 0xf, 0x49, 0xff, 0xa, 0x7a, 0xa, 0x49, 0xff, 0xa, 0x7a, 0x5, 0x49, 0xff, 0xa, 0x7a, 0x0, 0xc3}, - }, - }, - } - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - for _, tc := range tests { - for _, jmpInst := range []asm.Instruction{JCC, JCS, JEQ, JGE, JGT, JHI, JLE, JLS, JLT, JMI, JNE, JPC, JPS} { - name := tc.name + "/" + InstructionName(jmpInst) - - a := NewAssembler() - - var jmps []asm.Node - for i := 0; i < 12; i++ { // Large enough so that this includes long jump. - tc.setupFn(a) - jmps = append(jmps, a.CompileJump(jmpInst)) - } - - target := a.CompileStandAlone(RET) - for _, jmp := range jmps { - jmp.AssignJumpTarget(target) - } - - buf := code.NextCodeSection() - err := a.Assemble(buf) - require.NoError(t, err, name) - - actual := buf.Bytes() - require.Equal(t, tc.jmpInstToExpectedBytes[InstructionName(jmpInst)], actual, name) - } - } -} - -func TestAssemblerImpl_encodeNoneToBranch_errors(t *testing.T) { - tests := []struct { - n *nodeImpl - expErr string - }{ - { - n: &nodeImpl{types: operandTypesNoneToBranch, instruction: JMP}, - expErr: "jump target must not be nil for relative JMP", - }, - } - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - for _, tc := range tests { - a := NewAssembler() - buf := code.NextCodeSection() - err := a.encodeRelativeJump(buf, tc.n) - require.EqualError(t, err, tc.expErr) - } -} - -func TestAssemblerImpl_encodeNoneToBranch_backward_jumps(t *testing.T) { - t.Run("too large offset", func(t *testing.T) { - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - a := NewAssembler() - targetOffsetInBinaryField := uint64(0) - OffsetInBinaryField := uint64(math.MaxInt32) - node := &nodeImpl{ - instruction: JMP, - jumpTarget: &nodeImpl{offsetInBinary: targetOffsetInBinaryField}, - flag: nodeFlagBackwardJump, - offsetInBinary: OffsetInBinaryField, - } - - buf := code.NextCodeSection() - err := a.encodeRelativeJump(buf, node) - require.Error(t, err) - }) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - for _, tc := range []struct { - jmpInst asm.Instruction - isShortJump bool - expected []byte - }{ - {jmpInst: JCC, isShortJump: true, expected: []byte{0x99, 0x73, 0xfd}}, - {jmpInst: JCS, isShortJump: true, expected: []byte{0x99, 0x72, 0xfd}}, - {jmpInst: JEQ, isShortJump: true, expected: []byte{0x99, 0x74, 0xfd}}, - {jmpInst: JGE, isShortJump: true, expected: []byte{0x99, 0x7d, 0xfd}}, - {jmpInst: JGT, isShortJump: true, expected: []byte{0x99, 0x7f, 0xfd}}, - {jmpInst: JHI, isShortJump: true, expected: []byte{0x99, 0x77, 0xfd}}, - {jmpInst: JLE, isShortJump: true, expected: []byte{0x99, 0x7e, 0xfd}}, - {jmpInst: JLS, isShortJump: true, expected: []byte{0x99, 0x76, 0xfd}}, - {jmpInst: JLT, isShortJump: true, expected: []byte{0x99, 0x7c, 0xfd}}, - {jmpInst: JMI, isShortJump: true, expected: []byte{0x99, 0x78, 0xfd}}, - {jmpInst: JMP, isShortJump: true, expected: []byte{0x99, 0xeb, 0xfd}}, - {jmpInst: JNE, isShortJump: true, expected: []byte{0x99, 0x75, 0xfd}}, - {jmpInst: JPC, isShortJump: true, expected: []byte{0x99, 0x7b, 0xfd}}, - {jmpInst: JPS, isShortJump: true, expected: []byte{0x99, 0x7a, 0xfd}}, - {jmpInst: JPL, isShortJump: true, expected: []byte{0x99, 0x79, 0xfd}}, - {jmpInst: JCC, isShortJump: false, expected: []byte{0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0xf, 0x83, 0x79, 0xff, 0xff, 0xff}}, - {jmpInst: JCS, isShortJump: false, expected: []byte{0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0xf, 0x82, 0x79, 0xff, 0xff, 0xff}}, - {jmpInst: JEQ, isShortJump: false, expected: []byte{0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0xf, 0x84, 0x79, 0xff, 0xff, 0xff}}, - {jmpInst: JGE, isShortJump: false, expected: []byte{0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0xf, 0x8d, 0x79, 0xff, 0xff, 0xff}}, - {jmpInst: JGT, isShortJump: false, expected: []byte{0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0xf, 0x8f, 0x79, 0xff, 0xff, 0xff}}, - {jmpInst: JHI, isShortJump: false, expected: []byte{0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0xf, 0x87, 0x79, 0xff, 0xff, 0xff}}, - {jmpInst: JLE, isShortJump: false, expected: []byte{0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0xf, 0x8e, 0x79, 0xff, 0xff, 0xff}}, - {jmpInst: JLS, isShortJump: false, expected: []byte{0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0xf, 0x86, 0x79, 0xff, 0xff, 0xff}}, - {jmpInst: JLT, isShortJump: false, expected: []byte{0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0xf, 0x8c, 0x79, 0xff, 0xff, 0xff}}, - {jmpInst: JMI, isShortJump: false, expected: []byte{0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0xf, 0x88, 0x79, 0xff, 0xff, 0xff}}, - {jmpInst: JMP, isShortJump: false, expected: []byte{0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0xe9, 0x7a, 0xff, 0xff, 0xff}}, - {jmpInst: JNE, isShortJump: false, expected: []byte{0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0xf, 0x85, 0x79, 0xff, 0xff, 0xff}}, - {jmpInst: JPC, isShortJump: false, expected: []byte{0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0xf, 0x8b, 0x79, 0xff, 0xff, 0xff}}, - {jmpInst: JPS, isShortJump: false, expected: []byte{0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0xf, 0x8a, 0x79, 0xff, 0xff, 0xff}}, - {jmpInst: JPL, isShortJump: false, expected: []byte{0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0xf, 0x89, 0x79, 0xff, 0xff, 0xff}}, - } { - name := fmt.Sprintf("%s/short=%v", InstructionName(tc.jmpInst), tc.isShortJump) - a := NewAssembler() - const dummyInstruction = CDQ - target := a.CompileStandAlone(dummyInstruction) - if !tc.isShortJump { - for i := 0; i < 128; i++ { - a.CompileStandAlone(dummyInstruction) - } - } - jmp := a.CompileJump(tc.jmpInst) - jmp.AssignJumpTarget(target) - - buf := code.NextCodeSection() - err := a.Assemble(buf) - require.NoError(t, err, name) - - actual := buf.Bytes() - require.Equal(t, tc.expected, actual, name) - } -} - -func TestAssemblerImpl_encodeNoneToBranch_forward_jumps(t *testing.T) { - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - for _, tc := range []struct { - jmpInst asm.Instruction - isShortJump bool - expected []byte - }{ - {jmpInst: JCC, isShortJump: true, expected: []byte{0x73, 0x0, 0x99}}, - {jmpInst: JCS, isShortJump: true, expected: []byte{0x72, 0x0, 0x99}}, - {jmpInst: JEQ, isShortJump: true, expected: []byte{0x74, 0x0, 0x99}}, - {jmpInst: JGE, isShortJump: true, expected: []byte{0x7d, 0x0, 0x99}}, - {jmpInst: JGT, isShortJump: true, expected: []byte{0x7f, 0x0, 0x99}}, - {jmpInst: JHI, isShortJump: true, expected: []byte{0x77, 0x0, 0x99}}, - {jmpInst: JLE, isShortJump: true, expected: []byte{0x7e, 0x0, 0x99}}, - {jmpInst: JLS, isShortJump: true, expected: []byte{0x76, 0x0, 0x99}}, - {jmpInst: JLT, isShortJump: true, expected: []byte{0x7c, 0x0, 0x99}}, - {jmpInst: JMI, isShortJump: true, expected: []byte{0x78, 0x0, 0x99}}, - {jmpInst: JMP, isShortJump: true, expected: []byte{0xeb, 0x0, 0x99}}, - {jmpInst: JNE, isShortJump: true, expected: []byte{0x75, 0x0, 0x99}}, - {jmpInst: JPC, isShortJump: true, expected: []byte{0x7b, 0x0, 0x99}}, - {jmpInst: JPS, isShortJump: true, expected: []byte{0x7a, 0x0, 0x99}}, - {jmpInst: JPL, isShortJump: true, expected: []byte{0x79, 0x0, 0x99}}, - {jmpInst: JCC, isShortJump: false, expected: []byte{0xf, 0x83, 0x80, 0x0, 0x0, 0x0, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99}}, - {jmpInst: JCS, isShortJump: false, expected: []byte{0xf, 0x82, 0x80, 0x0, 0x0, 0x0, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99}}, - {jmpInst: JEQ, isShortJump: false, expected: []byte{0xf, 0x84, 0x80, 0x0, 0x0, 0x0, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99}}, - {jmpInst: JGE, isShortJump: false, expected: []byte{0xf, 0x8d, 0x80, 0x0, 0x0, 0x0, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99}}, - {jmpInst: JGT, isShortJump: false, expected: []byte{0xf, 0x8f, 0x80, 0x0, 0x0, 0x0, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99}}, - {jmpInst: JHI, isShortJump: false, expected: []byte{0xf, 0x87, 0x80, 0x0, 0x0, 0x0, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99}}, - {jmpInst: JLE, isShortJump: false, expected: []byte{0xf, 0x8e, 0x80, 0x0, 0x0, 0x0, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99}}, - {jmpInst: JLS, isShortJump: false, expected: []byte{0xf, 0x86, 0x80, 0x0, 0x0, 0x0, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99}}, - {jmpInst: JLT, isShortJump: false, expected: []byte{0xf, 0x8c, 0x80, 0x0, 0x0, 0x0, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99}}, - {jmpInst: JMI, isShortJump: false, expected: []byte{0xf, 0x88, 0x80, 0x0, 0x0, 0x0, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99}}, - {jmpInst: JMP, isShortJump: false, expected: []byte{0xe9, 0x80, 0x0, 0x0, 0x0, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99}}, - {jmpInst: JNE, isShortJump: false, expected: []byte{0xf, 0x85, 0x80, 0x0, 0x0, 0x0, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99}}, - {jmpInst: JPC, isShortJump: false, expected: []byte{0xf, 0x8b, 0x80, 0x0, 0x0, 0x0, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99}}, - {jmpInst: JPS, isShortJump: false, expected: []byte{0xf, 0x8a, 0x80, 0x0, 0x0, 0x0, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99}}, - {jmpInst: JPL, isShortJump: false, expected: []byte{0xf, 0x89, 0x80, 0x0, 0x0, 0x0, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99}}, - } { - name := fmt.Sprintf("%s/short=%v", InstructionName(tc.jmpInst), tc.isShortJump) - - a := NewAssembler() - const dummyInstruction = CDQ - jmp := a.CompileJump(tc.jmpInst) - - if !tc.isShortJump { - for i := 0; i < 128; i++ { - a.CompileStandAlone(dummyInstruction) - } - } - target := a.CompileStandAlone(dummyInstruction) - jmp.AssignJumpTarget(target) - - buf := code.NextCodeSection() - err := a.Assemble(buf) - require.NoError(t, err, name) - - actual := buf.Bytes() - require.Equal(t, tc.expected, actual, name) - } -} diff --git a/internal/asm/amd64/impl_memorylocation_test.go b/internal/asm/amd64/impl_memorylocation_test.go deleted file mode 100644 index d7acd3ef5d..0000000000 --- a/internal/asm/amd64/impl_memorylocation_test.go +++ /dev/null @@ -1,1699 +0,0 @@ -package amd64 - -import ( - "math" - "testing" - - "github.com/tetratelabs/wazero/internal/asm" - "github.com/tetratelabs/wazero/internal/testing/require" -) - -func TestNodeImpl_GetMemoryLocation_errors(t *testing.T) { - tests := []struct { - n *nodeImpl - expErr string - }{ - { - n: &nodeImpl{instruction: ADDL, srcConst: math.MaxInt64, srcReg: RegAX, dstReg: RegR10}, - expErr: "offset does not fit in 32-bit integer", - }, - { - n: &nodeImpl{ - instruction: ADDL, - srcConst: 10, srcReg: asm.NilRegister, srcMemIndex: RegR12, srcMemScale: 1, dstReg: RegR10, - }, - expErr: "addressing without base register but with index is not implemented", - }, - { - n: &nodeImpl{ - instruction: ADDL, - srcConst: 10, srcReg: RegAX, srcMemIndex: RegSP, srcMemScale: 1, dstReg: RegR10, - }, - expErr: "SP cannot be used for SIB index", - }, - { - n: &nodeImpl{ - instruction: ADDL, - srcConst: 10, srcReg: RegAX, srcMemIndex: RegR9, srcMemScale: 3, dstReg: RegR10, - }, - expErr: "scale in SIB must be one of 1, 2, 4, 8 but got 3", - }, - } - for _, tt := range tests { - _, _, _, _, _, err := tt.n.getMemoryLocation(false) - require.EqualError(t, err, tt.expErr, tt.expErr) - } -} - -func TestNodeImpl_GetMemoryLocation_without_base(t *testing.T) { - tests := []struct { - offset int64 - modRM, sbi, displacementWidth byte - }{ - {offset: 0, modRM: 0x4, sbi: 0x25}, - {offset: 1, modRM: 0x4, sbi: 0x25}, - {offset: -1, modRM: 0x4, sbi: 0x25}, - {offset: 2147483647, modRM: 0x4, sbi: 0x25}, - {offset: -2147483648, modRM: 0x4, sbi: 0x25}, - } - for _, tc := range tests { - n := &nodeImpl{ - srcReg: asm.NilRegister, srcConst: tc.offset, - } - rexPrefix, modRM, sbi, sbiExist, displacementWidth, err := n.getMemoryLocation(false) - require.NoError(t, err) - require.Equal(t, rexPrefixNone, rexPrefix) - require.Equal(t, tc.modRM, modRM) - require.True(t, sbiExist) - require.Equal(t, tc.sbi, sbi) - require.Equal(t, byte(32), displacementWidth) - } -} - -func TestNodeImpl_GetMemoryLocation_with_base(t *testing.T) { - tests := []struct { - name string - baseReg, indexReg asm.Register - scale byte - offset int64 - expRex, expModRM byte - needSBI bool - expSBI byte - displacementWidth byte - }{ - {name: "baseReg=RegAX/indexReg=RegAX/scale=1/offset=0", baseReg: RegAX, indexReg: RegAX, scale: 1, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x0, displacementWidth: 0}, - {name: "baseReg=RegAX/indexReg=RegAX/scale=2/offset=0", baseReg: RegAX, indexReg: RegAX, scale: 2, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x40, displacementWidth: 0}, - {name: "baseReg=RegAX/indexReg=RegAX/scale=4/offset=0", baseReg: RegAX, indexReg: RegAX, scale: 4, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x80, displacementWidth: 0}, - {name: "baseReg=RegAX/indexReg=RegAX/scale=8/offset=0", baseReg: RegAX, indexReg: RegAX, scale: 8, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0xc0, displacementWidth: 0}, - {name: "baseReg=RegAX/indexReg=RegBX/scale=1/offset=0", baseReg: RegAX, indexReg: RegBX, scale: 1, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x18, displacementWidth: 0}, - {name: "baseReg=RegAX/indexReg=RegBX/scale=2/offset=0", baseReg: RegAX, indexReg: RegBX, scale: 2, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x58, displacementWidth: 0}, - {name: "baseReg=RegAX/indexReg=RegBX/scale=4/offset=0", baseReg: RegAX, indexReg: RegBX, scale: 4, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x98, displacementWidth: 0}, - {name: "baseReg=RegAX/indexReg=RegBX/scale=8/offset=0", baseReg: RegAX, indexReg: RegBX, scale: 8, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0xd8, displacementWidth: 0}, - {name: "baseReg=RegAX/indexReg=RegBP/scale=1/offset=0", baseReg: RegAX, indexReg: RegBP, scale: 1, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x28, displacementWidth: 0}, - {name: "baseReg=RegAX/indexReg=RegBP/scale=2/offset=0", baseReg: RegAX, indexReg: RegBP, scale: 2, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x68, displacementWidth: 0}, - {name: "baseReg=RegAX/indexReg=RegBP/scale=4/offset=0", baseReg: RegAX, indexReg: RegBP, scale: 4, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0xa8, displacementWidth: 0}, - {name: "baseReg=RegAX/indexReg=RegBP/scale=8/offset=0", baseReg: RegAX, indexReg: RegBP, scale: 8, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0xe8, displacementWidth: 0}, - {name: "baseReg=RegAX/indexReg=RegSI/scale=1/offset=0", baseReg: RegAX, indexReg: RegSI, scale: 1, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x30, displacementWidth: 0}, - {name: "baseReg=RegAX/indexReg=RegSI/scale=2/offset=0", baseReg: RegAX, indexReg: RegSI, scale: 2, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x70, displacementWidth: 0}, - {name: "baseReg=RegAX/indexReg=RegSI/scale=4/offset=0", baseReg: RegAX, indexReg: RegSI, scale: 4, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0xb0, displacementWidth: 0}, - {name: "baseReg=RegAX/indexReg=RegSI/scale=8/offset=0", baseReg: RegAX, indexReg: RegSI, scale: 8, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0xf0, displacementWidth: 0}, - {name: "baseReg=RegAX/indexReg=RegDI/scale=1/offset=0", baseReg: RegAX, indexReg: RegDI, scale: 1, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x38, displacementWidth: 0}, - {name: "baseReg=RegAX/indexReg=RegDI/scale=2/offset=0", baseReg: RegAX, indexReg: RegDI, scale: 2, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x78, displacementWidth: 0}, - {name: "baseReg=RegAX/indexReg=RegDI/scale=4/offset=0", baseReg: RegAX, indexReg: RegDI, scale: 4, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0xb8, displacementWidth: 0}, - {name: "baseReg=RegAX/indexReg=RegDI/scale=8/offset=0", baseReg: RegAX, indexReg: RegDI, scale: 8, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0xf8, displacementWidth: 0}, - {name: "baseReg=RegAX/indexReg=RegR8/scale=1/offset=0", baseReg: RegAX, indexReg: RegR8, scale: 1, offset: 0, expRex: 0x42, expModRM: 0x4, needSBI: true, expSBI: 0x0, displacementWidth: 0}, - {name: "baseReg=RegAX/indexReg=RegR8/scale=2/offset=0", baseReg: RegAX, indexReg: RegR8, scale: 2, offset: 0, expRex: 0x42, expModRM: 0x4, needSBI: true, expSBI: 0x40, displacementWidth: 0}, - {name: "baseReg=RegAX/indexReg=RegR8/scale=4/offset=0", baseReg: RegAX, indexReg: RegR8, scale: 4, offset: 0, expRex: 0x42, expModRM: 0x4, needSBI: true, expSBI: 0x80, displacementWidth: 0}, - {name: "baseReg=RegAX/indexReg=RegR8/scale=8/offset=0", baseReg: RegAX, indexReg: RegR8, scale: 8, offset: 0, expRex: 0x42, expModRM: 0x4, needSBI: true, expSBI: 0xc0, displacementWidth: 0}, - {name: "baseReg=RegAX/indexReg=RegR14/scale=1/offset=0", baseReg: RegAX, indexReg: RegR14, scale: 1, offset: 0, expRex: 0x42, expModRM: 0x4, needSBI: true, expSBI: 0x30, displacementWidth: 0}, - {name: "baseReg=RegAX/indexReg=RegR14/scale=2/offset=0", baseReg: RegAX, indexReg: RegR14, scale: 2, offset: 0, expRex: 0x42, expModRM: 0x4, needSBI: true, expSBI: 0x70, displacementWidth: 0}, - {name: "baseReg=RegAX/indexReg=RegR14/scale=4/offset=0", baseReg: RegAX, indexReg: RegR14, scale: 4, offset: 0, expRex: 0x42, expModRM: 0x4, needSBI: true, expSBI: 0xb0, displacementWidth: 0}, - {name: "baseReg=RegAX/indexReg=RegR14/scale=8/offset=0", baseReg: RegAX, indexReg: RegR14, scale: 8, offset: 0, expRex: 0x42, expModRM: 0x4, needSBI: true, expSBI: 0xf0, displacementWidth: 0}, - {name: "baseReg=RegAX/indexReg=Nil/scale=1/offset=0", baseReg: RegAX, indexReg: asm.NilRegister, scale: 1, offset: 0, expRex: 0x0, expModRM: 0x0, needSBI: false, displacementWidth: 0}, - {name: "baseReg=RegAX/indexReg=Nil/scale=2/offset=0", baseReg: RegAX, indexReg: asm.NilRegister, scale: 2, offset: 0, expRex: 0x0, expModRM: 0x0, needSBI: false, displacementWidth: 0}, - {name: "baseReg=RegAX/indexReg=Nil/scale=4/offset=0", baseReg: RegAX, indexReg: asm.NilRegister, scale: 4, offset: 0, expRex: 0x0, expModRM: 0x0, needSBI: false, displacementWidth: 0}, - {name: "baseReg=RegAX/indexReg=Nil/scale=8/offset=0", baseReg: RegAX, indexReg: asm.NilRegister, scale: 8, offset: 0, expRex: 0x0, expModRM: 0x0, needSBI: false, displacementWidth: 0}, - {name: "baseReg=RegAX/indexReg=RegAX/scale=1/offset=1", baseReg: RegAX, indexReg: RegAX, scale: 1, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x0, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegAX/scale=2/offset=1", baseReg: RegAX, indexReg: RegAX, scale: 2, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x40, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegAX/scale=4/offset=1", baseReg: RegAX, indexReg: RegAX, scale: 4, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x80, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegAX/scale=8/offset=1", baseReg: RegAX, indexReg: RegAX, scale: 8, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xc0, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegBX/scale=1/offset=1", baseReg: RegAX, indexReg: RegBX, scale: 1, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x18, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegBX/scale=2/offset=1", baseReg: RegAX, indexReg: RegBX, scale: 2, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x58, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegBX/scale=4/offset=1", baseReg: RegAX, indexReg: RegBX, scale: 4, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x98, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegBX/scale=8/offset=1", baseReg: RegAX, indexReg: RegBX, scale: 8, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xd8, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegBP/scale=1/offset=1", baseReg: RegAX, indexReg: RegBP, scale: 1, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x28, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegBP/scale=2/offset=1", baseReg: RegAX, indexReg: RegBP, scale: 2, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x68, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegBP/scale=4/offset=1", baseReg: RegAX, indexReg: RegBP, scale: 4, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xa8, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegBP/scale=8/offset=1", baseReg: RegAX, indexReg: RegBP, scale: 8, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xe8, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegSI/scale=1/offset=1", baseReg: RegAX, indexReg: RegSI, scale: 1, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x30, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegSI/scale=2/offset=1", baseReg: RegAX, indexReg: RegSI, scale: 2, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x70, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegSI/scale=4/offset=1", baseReg: RegAX, indexReg: RegSI, scale: 4, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xb0, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegSI/scale=8/offset=1", baseReg: RegAX, indexReg: RegSI, scale: 8, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xf0, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegDI/scale=1/offset=1", baseReg: RegAX, indexReg: RegDI, scale: 1, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x38, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegDI/scale=2/offset=1", baseReg: RegAX, indexReg: RegDI, scale: 2, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x78, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegDI/scale=4/offset=1", baseReg: RegAX, indexReg: RegDI, scale: 4, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xb8, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegDI/scale=8/offset=1", baseReg: RegAX, indexReg: RegDI, scale: 8, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xf8, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegR8/scale=1/offset=1", baseReg: RegAX, indexReg: RegR8, scale: 1, offset: 1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x0, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegR8/scale=2/offset=1", baseReg: RegAX, indexReg: RegR8, scale: 2, offset: 1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x40, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegR8/scale=4/offset=1", baseReg: RegAX, indexReg: RegR8, scale: 4, offset: 1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x80, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegR8/scale=8/offset=1", baseReg: RegAX, indexReg: RegR8, scale: 8, offset: 1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0xc0, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegR14/scale=1/offset=1", baseReg: RegAX, indexReg: RegR14, scale: 1, offset: 1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x30, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegR14/scale=2/offset=1", baseReg: RegAX, indexReg: RegR14, scale: 2, offset: 1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x70, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegR14/scale=4/offset=1", baseReg: RegAX, indexReg: RegR14, scale: 4, offset: 1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0xb0, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegR14/scale=8/offset=1", baseReg: RegAX, indexReg: RegR14, scale: 8, offset: 1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0xf0, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=Nil/scale=1/offset=1", baseReg: RegAX, indexReg: asm.NilRegister, scale: 1, offset: 1, expRex: 0x0, expModRM: 0x40, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=Nil/scale=2/offset=1", baseReg: RegAX, indexReg: asm.NilRegister, scale: 2, offset: 1, expRex: 0x0, expModRM: 0x40, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=Nil/scale=4/offset=1", baseReg: RegAX, indexReg: asm.NilRegister, scale: 4, offset: 1, expRex: 0x0, expModRM: 0x40, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=Nil/scale=8/offset=1", baseReg: RegAX, indexReg: asm.NilRegister, scale: 8, offset: 1, expRex: 0x0, expModRM: 0x40, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegAX/scale=1/offset=-1", baseReg: RegAX, indexReg: RegAX, scale: 1, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x0, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegAX/scale=2/offset=-1", baseReg: RegAX, indexReg: RegAX, scale: 2, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x40, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegAX/scale=4/offset=-1", baseReg: RegAX, indexReg: RegAX, scale: 4, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x80, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegAX/scale=8/offset=-1", baseReg: RegAX, indexReg: RegAX, scale: 8, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xc0, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegBX/scale=1/offset=-1", baseReg: RegAX, indexReg: RegBX, scale: 1, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x18, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegBX/scale=2/offset=-1", baseReg: RegAX, indexReg: RegBX, scale: 2, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x58, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegBX/scale=4/offset=-1", baseReg: RegAX, indexReg: RegBX, scale: 4, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x98, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegBX/scale=8/offset=-1", baseReg: RegAX, indexReg: RegBX, scale: 8, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xd8, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegBP/scale=1/offset=-1", baseReg: RegAX, indexReg: RegBP, scale: 1, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x28, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegBP/scale=2/offset=-1", baseReg: RegAX, indexReg: RegBP, scale: 2, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x68, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegBP/scale=4/offset=-1", baseReg: RegAX, indexReg: RegBP, scale: 4, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xa8, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegBP/scale=8/offset=-1", baseReg: RegAX, indexReg: RegBP, scale: 8, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xe8, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegSI/scale=1/offset=-1", baseReg: RegAX, indexReg: RegSI, scale: 1, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x30, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegSI/scale=2/offset=-1", baseReg: RegAX, indexReg: RegSI, scale: 2, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x70, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegSI/scale=4/offset=-1", baseReg: RegAX, indexReg: RegSI, scale: 4, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xb0, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegSI/scale=8/offset=-1", baseReg: RegAX, indexReg: RegSI, scale: 8, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xf0, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegDI/scale=1/offset=-1", baseReg: RegAX, indexReg: RegDI, scale: 1, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x38, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegDI/scale=2/offset=-1", baseReg: RegAX, indexReg: RegDI, scale: 2, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x78, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegDI/scale=4/offset=-1", baseReg: RegAX, indexReg: RegDI, scale: 4, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xb8, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegDI/scale=8/offset=-1", baseReg: RegAX, indexReg: RegDI, scale: 8, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xf8, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegR8/scale=1/offset=-1", baseReg: RegAX, indexReg: RegR8, scale: 1, offset: -1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x0, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegR8/scale=2/offset=-1", baseReg: RegAX, indexReg: RegR8, scale: 2, offset: -1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x40, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegR8/scale=4/offset=-1", baseReg: RegAX, indexReg: RegR8, scale: 4, offset: -1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x80, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegR8/scale=8/offset=-1", baseReg: RegAX, indexReg: RegR8, scale: 8, offset: -1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0xc0, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegR14/scale=1/offset=-1", baseReg: RegAX, indexReg: RegR14, scale: 1, offset: -1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x30, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegR14/scale=2/offset=-1", baseReg: RegAX, indexReg: RegR14, scale: 2, offset: -1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x70, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegR14/scale=4/offset=-1", baseReg: RegAX, indexReg: RegR14, scale: 4, offset: -1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0xb0, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegR14/scale=8/offset=-1", baseReg: RegAX, indexReg: RegR14, scale: 8, offset: -1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0xf0, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=Nil/scale=1/offset=-1", baseReg: RegAX, indexReg: asm.NilRegister, scale: 1, offset: -1, expRex: 0x0, expModRM: 0x40, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=Nil/scale=2/offset=-1", baseReg: RegAX, indexReg: asm.NilRegister, scale: 2, offset: -1, expRex: 0x0, expModRM: 0x40, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=Nil/scale=4/offset=-1", baseReg: RegAX, indexReg: asm.NilRegister, scale: 4, offset: -1, expRex: 0x0, expModRM: 0x40, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=Nil/scale=8/offset=-1", baseReg: RegAX, indexReg: asm.NilRegister, scale: 8, offset: -1, expRex: 0x0, expModRM: 0x40, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegAX/indexReg=RegAX/scale=1/offset=2147483647", baseReg: RegAX, indexReg: RegAX, scale: 1, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x0, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegAX/scale=2/offset=2147483647", baseReg: RegAX, indexReg: RegAX, scale: 2, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x40, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegAX/scale=4/offset=2147483647", baseReg: RegAX, indexReg: RegAX, scale: 4, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x80, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegAX/scale=8/offset=2147483647", baseReg: RegAX, indexReg: RegAX, scale: 8, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xc0, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegBX/scale=1/offset=2147483647", baseReg: RegAX, indexReg: RegBX, scale: 1, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x18, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegBX/scale=2/offset=2147483647", baseReg: RegAX, indexReg: RegBX, scale: 2, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x58, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegBX/scale=4/offset=2147483647", baseReg: RegAX, indexReg: RegBX, scale: 4, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x98, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegBX/scale=8/offset=2147483647", baseReg: RegAX, indexReg: RegBX, scale: 8, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xd8, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegBP/scale=1/offset=2147483647", baseReg: RegAX, indexReg: RegBP, scale: 1, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x28, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegBP/scale=2/offset=2147483647", baseReg: RegAX, indexReg: RegBP, scale: 2, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x68, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegBP/scale=4/offset=2147483647", baseReg: RegAX, indexReg: RegBP, scale: 4, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xa8, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegBP/scale=8/offset=2147483647", baseReg: RegAX, indexReg: RegBP, scale: 8, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xe8, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegSI/scale=1/offset=2147483647", baseReg: RegAX, indexReg: RegSI, scale: 1, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x30, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegSI/scale=2/offset=2147483647", baseReg: RegAX, indexReg: RegSI, scale: 2, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x70, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegSI/scale=4/offset=2147483647", baseReg: RegAX, indexReg: RegSI, scale: 4, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xb0, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegSI/scale=8/offset=2147483647", baseReg: RegAX, indexReg: RegSI, scale: 8, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xf0, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegDI/scale=1/offset=2147483647", baseReg: RegAX, indexReg: RegDI, scale: 1, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x38, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegDI/scale=2/offset=2147483647", baseReg: RegAX, indexReg: RegDI, scale: 2, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x78, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegDI/scale=4/offset=2147483647", baseReg: RegAX, indexReg: RegDI, scale: 4, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xb8, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegDI/scale=8/offset=2147483647", baseReg: RegAX, indexReg: RegDI, scale: 8, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xf8, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegR8/scale=1/offset=2147483647", baseReg: RegAX, indexReg: RegR8, scale: 1, offset: 2147483647, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x0, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegR8/scale=2/offset=2147483647", baseReg: RegAX, indexReg: RegR8, scale: 2, offset: 2147483647, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x40, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegR8/scale=4/offset=2147483647", baseReg: RegAX, indexReg: RegR8, scale: 4, offset: 2147483647, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x80, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegR8/scale=8/offset=2147483647", baseReg: RegAX, indexReg: RegR8, scale: 8, offset: 2147483647, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0xc0, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegR14/scale=1/offset=2147483647", baseReg: RegAX, indexReg: RegR14, scale: 1, offset: 2147483647, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x30, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegR14/scale=2/offset=2147483647", baseReg: RegAX, indexReg: RegR14, scale: 2, offset: 2147483647, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x70, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegR14/scale=4/offset=2147483647", baseReg: RegAX, indexReg: RegR14, scale: 4, offset: 2147483647, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0xb0, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegR14/scale=8/offset=2147483647", baseReg: RegAX, indexReg: RegR14, scale: 8, offset: 2147483647, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0xf0, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=Nil/scale=1/offset=2147483647", baseReg: RegAX, indexReg: asm.NilRegister, scale: 1, offset: 2147483647, expRex: 0x0, expModRM: 0x80, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=Nil/scale=2/offset=2147483647", baseReg: RegAX, indexReg: asm.NilRegister, scale: 2, offset: 2147483647, expRex: 0x0, expModRM: 0x80, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=Nil/scale=4/offset=2147483647", baseReg: RegAX, indexReg: asm.NilRegister, scale: 4, offset: 2147483647, expRex: 0x0, expModRM: 0x80, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=Nil/scale=8/offset=2147483647", baseReg: RegAX, indexReg: asm.NilRegister, scale: 8, offset: 2147483647, expRex: 0x0, expModRM: 0x80, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegAX/scale=1/offset=-2147483648", baseReg: RegAX, indexReg: RegAX, scale: 1, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x0, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegAX/scale=2/offset=-2147483648", baseReg: RegAX, indexReg: RegAX, scale: 2, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x40, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegAX/scale=4/offset=-2147483648", baseReg: RegAX, indexReg: RegAX, scale: 4, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x80, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegAX/scale=8/offset=-2147483648", baseReg: RegAX, indexReg: RegAX, scale: 8, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xc0, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegBX/scale=1/offset=-2147483648", baseReg: RegAX, indexReg: RegBX, scale: 1, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x18, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegBX/scale=2/offset=-2147483648", baseReg: RegAX, indexReg: RegBX, scale: 2, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x58, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegBX/scale=4/offset=-2147483648", baseReg: RegAX, indexReg: RegBX, scale: 4, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x98, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegBX/scale=8/offset=-2147483648", baseReg: RegAX, indexReg: RegBX, scale: 8, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xd8, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegBP/scale=1/offset=-2147483648", baseReg: RegAX, indexReg: RegBP, scale: 1, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x28, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegBP/scale=2/offset=-2147483648", baseReg: RegAX, indexReg: RegBP, scale: 2, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x68, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegBP/scale=4/offset=-2147483648", baseReg: RegAX, indexReg: RegBP, scale: 4, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xa8, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegBP/scale=8/offset=-2147483648", baseReg: RegAX, indexReg: RegBP, scale: 8, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xe8, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegSI/scale=1/offset=-2147483648", baseReg: RegAX, indexReg: RegSI, scale: 1, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x30, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegSI/scale=2/offset=-2147483648", baseReg: RegAX, indexReg: RegSI, scale: 2, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x70, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegSI/scale=4/offset=-2147483648", baseReg: RegAX, indexReg: RegSI, scale: 4, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xb0, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegSI/scale=8/offset=-2147483648", baseReg: RegAX, indexReg: RegSI, scale: 8, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xf0, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegDI/scale=1/offset=-2147483648", baseReg: RegAX, indexReg: RegDI, scale: 1, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x38, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegDI/scale=2/offset=-2147483648", baseReg: RegAX, indexReg: RegDI, scale: 2, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x78, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegDI/scale=4/offset=-2147483648", baseReg: RegAX, indexReg: RegDI, scale: 4, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xb8, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegDI/scale=8/offset=-2147483648", baseReg: RegAX, indexReg: RegDI, scale: 8, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xf8, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegR8/scale=1/offset=-2147483648", baseReg: RegAX, indexReg: RegR8, scale: 1, offset: -2147483648, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x0, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegR8/scale=2/offset=-2147483648", baseReg: RegAX, indexReg: RegR8, scale: 2, offset: -2147483648, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x40, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegR8/scale=4/offset=-2147483648", baseReg: RegAX, indexReg: RegR8, scale: 4, offset: -2147483648, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x80, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegR8/scale=8/offset=-2147483648", baseReg: RegAX, indexReg: RegR8, scale: 8, offset: -2147483648, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0xc0, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegR14/scale=1/offset=-2147483648", baseReg: RegAX, indexReg: RegR14, scale: 1, offset: -2147483648, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x30, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegR14/scale=2/offset=-2147483648", baseReg: RegAX, indexReg: RegR14, scale: 2, offset: -2147483648, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x70, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegR14/scale=4/offset=-2147483648", baseReg: RegAX, indexReg: RegR14, scale: 4, offset: -2147483648, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0xb0, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=RegR14/scale=8/offset=-2147483648", baseReg: RegAX, indexReg: RegR14, scale: 8, offset: -2147483648, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0xf0, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=Nil/scale=1/offset=-2147483648", baseReg: RegAX, indexReg: asm.NilRegister, scale: 1, offset: -2147483648, expRex: 0x0, expModRM: 0x80, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=Nil/scale=2/offset=-2147483648", baseReg: RegAX, indexReg: asm.NilRegister, scale: 2, offset: -2147483648, expRex: 0x0, expModRM: 0x80, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=Nil/scale=4/offset=-2147483648", baseReg: RegAX, indexReg: asm.NilRegister, scale: 4, offset: -2147483648, expRex: 0x0, expModRM: 0x80, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegAX/indexReg=Nil/scale=8/offset=-2147483648", baseReg: RegAX, indexReg: asm.NilRegister, scale: 8, offset: -2147483648, expRex: 0x0, expModRM: 0x80, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegAX/scale=1/offset=0", baseReg: RegBX, indexReg: RegAX, scale: 1, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x3, displacementWidth: 0}, - {name: "baseReg=RegBX/indexReg=RegAX/scale=2/offset=0", baseReg: RegBX, indexReg: RegAX, scale: 2, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x43, displacementWidth: 0}, - {name: "baseReg=RegBX/indexReg=RegAX/scale=4/offset=0", baseReg: RegBX, indexReg: RegAX, scale: 4, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x83, displacementWidth: 0}, - {name: "baseReg=RegBX/indexReg=RegAX/scale=8/offset=0", baseReg: RegBX, indexReg: RegAX, scale: 8, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0xc3, displacementWidth: 0}, - {name: "baseReg=RegBX/indexReg=RegBX/scale=1/offset=0", baseReg: RegBX, indexReg: RegBX, scale: 1, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x1b, displacementWidth: 0}, - {name: "baseReg=RegBX/indexReg=RegBX/scale=2/offset=0", baseReg: RegBX, indexReg: RegBX, scale: 2, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x5b, displacementWidth: 0}, - {name: "baseReg=RegBX/indexReg=RegBX/scale=4/offset=0", baseReg: RegBX, indexReg: RegBX, scale: 4, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x9b, displacementWidth: 0}, - {name: "baseReg=RegBX/indexReg=RegBX/scale=8/offset=0", baseReg: RegBX, indexReg: RegBX, scale: 8, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0xdb, displacementWidth: 0}, - {name: "baseReg=RegBX/indexReg=RegBP/scale=1/offset=0", baseReg: RegBX, indexReg: RegBP, scale: 1, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x2b, displacementWidth: 0}, - {name: "baseReg=RegBX/indexReg=RegBP/scale=2/offset=0", baseReg: RegBX, indexReg: RegBP, scale: 2, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x6b, displacementWidth: 0}, - {name: "baseReg=RegBX/indexReg=RegBP/scale=4/offset=0", baseReg: RegBX, indexReg: RegBP, scale: 4, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0xab, displacementWidth: 0}, - {name: "baseReg=RegBX/indexReg=RegBP/scale=8/offset=0", baseReg: RegBX, indexReg: RegBP, scale: 8, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0xeb, displacementWidth: 0}, - {name: "baseReg=RegBX/indexReg=RegSI/scale=1/offset=0", baseReg: RegBX, indexReg: RegSI, scale: 1, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x33, displacementWidth: 0}, - {name: "baseReg=RegBX/indexReg=RegSI/scale=2/offset=0", baseReg: RegBX, indexReg: RegSI, scale: 2, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x73, displacementWidth: 0}, - {name: "baseReg=RegBX/indexReg=RegSI/scale=4/offset=0", baseReg: RegBX, indexReg: RegSI, scale: 4, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0xb3, displacementWidth: 0}, - {name: "baseReg=RegBX/indexReg=RegSI/scale=8/offset=0", baseReg: RegBX, indexReg: RegSI, scale: 8, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0xf3, displacementWidth: 0}, - {name: "baseReg=RegBX/indexReg=RegDI/scale=1/offset=0", baseReg: RegBX, indexReg: RegDI, scale: 1, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x3b, displacementWidth: 0}, - {name: "baseReg=RegBX/indexReg=RegDI/scale=2/offset=0", baseReg: RegBX, indexReg: RegDI, scale: 2, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x7b, displacementWidth: 0}, - {name: "baseReg=RegBX/indexReg=RegDI/scale=4/offset=0", baseReg: RegBX, indexReg: RegDI, scale: 4, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0xbb, displacementWidth: 0}, - {name: "baseReg=RegBX/indexReg=RegDI/scale=8/offset=0", baseReg: RegBX, indexReg: RegDI, scale: 8, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0xfb, displacementWidth: 0}, - {name: "baseReg=RegBX/indexReg=RegR8/scale=1/offset=0", baseReg: RegBX, indexReg: RegR8, scale: 1, offset: 0, expRex: 0x42, expModRM: 0x4, needSBI: true, expSBI: 0x3, displacementWidth: 0}, - {name: "baseReg=RegBX/indexReg=RegR8/scale=2/offset=0", baseReg: RegBX, indexReg: RegR8, scale: 2, offset: 0, expRex: 0x42, expModRM: 0x4, needSBI: true, expSBI: 0x43, displacementWidth: 0}, - {name: "baseReg=RegBX/indexReg=RegR8/scale=4/offset=0", baseReg: RegBX, indexReg: RegR8, scale: 4, offset: 0, expRex: 0x42, expModRM: 0x4, needSBI: true, expSBI: 0x83, displacementWidth: 0}, - {name: "baseReg=RegBX/indexReg=RegR8/scale=8/offset=0", baseReg: RegBX, indexReg: RegR8, scale: 8, offset: 0, expRex: 0x42, expModRM: 0x4, needSBI: true, expSBI: 0xc3, displacementWidth: 0}, - {name: "baseReg=RegBX/indexReg=RegR14/scale=1/offset=0", baseReg: RegBX, indexReg: RegR14, scale: 1, offset: 0, expRex: 0x42, expModRM: 0x4, needSBI: true, expSBI: 0x33, displacementWidth: 0}, - {name: "baseReg=RegBX/indexReg=RegR14/scale=2/offset=0", baseReg: RegBX, indexReg: RegR14, scale: 2, offset: 0, expRex: 0x42, expModRM: 0x4, needSBI: true, expSBI: 0x73, displacementWidth: 0}, - {name: "baseReg=RegBX/indexReg=RegR14/scale=4/offset=0", baseReg: RegBX, indexReg: RegR14, scale: 4, offset: 0, expRex: 0x42, expModRM: 0x4, needSBI: true, expSBI: 0xb3, displacementWidth: 0}, - {name: "baseReg=RegBX/indexReg=RegR14/scale=8/offset=0", baseReg: RegBX, indexReg: RegR14, scale: 8, offset: 0, expRex: 0x42, expModRM: 0x4, needSBI: true, expSBI: 0xf3, displacementWidth: 0}, - {name: "baseReg=RegBX/indexReg=Nil/scale=1/offset=0", baseReg: RegBX, indexReg: asm.NilRegister, scale: 1, offset: 0, expRex: 0x0, expModRM: 0x3, needSBI: false, displacementWidth: 0}, - {name: "baseReg=RegBX/indexReg=Nil/scale=2/offset=0", baseReg: RegBX, indexReg: asm.NilRegister, scale: 2, offset: 0, expRex: 0x0, expModRM: 0x3, needSBI: false, displacementWidth: 0}, - {name: "baseReg=RegBX/indexReg=Nil/scale=4/offset=0", baseReg: RegBX, indexReg: asm.NilRegister, scale: 4, offset: 0, expRex: 0x0, expModRM: 0x3, needSBI: false, displacementWidth: 0}, - {name: "baseReg=RegBX/indexReg=Nil/scale=8/offset=0", baseReg: RegBX, indexReg: asm.NilRegister, scale: 8, offset: 0, expRex: 0x0, expModRM: 0x3, needSBI: false, displacementWidth: 0}, - {name: "baseReg=RegBX/indexReg=RegAX/scale=1/offset=1", baseReg: RegBX, indexReg: RegAX, scale: 1, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x3, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegAX/scale=2/offset=1", baseReg: RegBX, indexReg: RegAX, scale: 2, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x43, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegAX/scale=4/offset=1", baseReg: RegBX, indexReg: RegAX, scale: 4, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x83, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegAX/scale=8/offset=1", baseReg: RegBX, indexReg: RegAX, scale: 8, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xc3, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegBX/scale=1/offset=1", baseReg: RegBX, indexReg: RegBX, scale: 1, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x1b, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegBX/scale=2/offset=1", baseReg: RegBX, indexReg: RegBX, scale: 2, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x5b, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegBX/scale=4/offset=1", baseReg: RegBX, indexReg: RegBX, scale: 4, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x9b, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegBX/scale=8/offset=1", baseReg: RegBX, indexReg: RegBX, scale: 8, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xdb, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegBP/scale=1/offset=1", baseReg: RegBX, indexReg: RegBP, scale: 1, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x2b, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegBP/scale=2/offset=1", baseReg: RegBX, indexReg: RegBP, scale: 2, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x6b, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegBP/scale=4/offset=1", baseReg: RegBX, indexReg: RegBP, scale: 4, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xab, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegBP/scale=8/offset=1", baseReg: RegBX, indexReg: RegBP, scale: 8, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xeb, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegSI/scale=1/offset=1", baseReg: RegBX, indexReg: RegSI, scale: 1, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x33, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegSI/scale=2/offset=1", baseReg: RegBX, indexReg: RegSI, scale: 2, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x73, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegSI/scale=4/offset=1", baseReg: RegBX, indexReg: RegSI, scale: 4, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xb3, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegSI/scale=8/offset=1", baseReg: RegBX, indexReg: RegSI, scale: 8, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xf3, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegDI/scale=1/offset=1", baseReg: RegBX, indexReg: RegDI, scale: 1, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x3b, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegDI/scale=2/offset=1", baseReg: RegBX, indexReg: RegDI, scale: 2, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x7b, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegDI/scale=4/offset=1", baseReg: RegBX, indexReg: RegDI, scale: 4, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xbb, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegDI/scale=8/offset=1", baseReg: RegBX, indexReg: RegDI, scale: 8, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xfb, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegR8/scale=1/offset=1", baseReg: RegBX, indexReg: RegR8, scale: 1, offset: 1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x3, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegR8/scale=2/offset=1", baseReg: RegBX, indexReg: RegR8, scale: 2, offset: 1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x43, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegR8/scale=4/offset=1", baseReg: RegBX, indexReg: RegR8, scale: 4, offset: 1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x83, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegR8/scale=8/offset=1", baseReg: RegBX, indexReg: RegR8, scale: 8, offset: 1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0xc3, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegR14/scale=1/offset=1", baseReg: RegBX, indexReg: RegR14, scale: 1, offset: 1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x33, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegR14/scale=2/offset=1", baseReg: RegBX, indexReg: RegR14, scale: 2, offset: 1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x73, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegR14/scale=4/offset=1", baseReg: RegBX, indexReg: RegR14, scale: 4, offset: 1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0xb3, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegR14/scale=8/offset=1", baseReg: RegBX, indexReg: RegR14, scale: 8, offset: 1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0xf3, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=Nil/scale=1/offset=1", baseReg: RegBX, indexReg: asm.NilRegister, scale: 1, offset: 1, expRex: 0x0, expModRM: 0x43, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=Nil/scale=2/offset=1", baseReg: RegBX, indexReg: asm.NilRegister, scale: 2, offset: 1, expRex: 0x0, expModRM: 0x43, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=Nil/scale=4/offset=1", baseReg: RegBX, indexReg: asm.NilRegister, scale: 4, offset: 1, expRex: 0x0, expModRM: 0x43, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=Nil/scale=8/offset=1", baseReg: RegBX, indexReg: asm.NilRegister, scale: 8, offset: 1, expRex: 0x0, expModRM: 0x43, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegAX/scale=1/offset=-1", baseReg: RegBX, indexReg: RegAX, scale: 1, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x3, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegAX/scale=2/offset=-1", baseReg: RegBX, indexReg: RegAX, scale: 2, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x43, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegAX/scale=4/offset=-1", baseReg: RegBX, indexReg: RegAX, scale: 4, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x83, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegAX/scale=8/offset=-1", baseReg: RegBX, indexReg: RegAX, scale: 8, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xc3, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegBX/scale=1/offset=-1", baseReg: RegBX, indexReg: RegBX, scale: 1, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x1b, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegBX/scale=2/offset=-1", baseReg: RegBX, indexReg: RegBX, scale: 2, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x5b, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegBX/scale=4/offset=-1", baseReg: RegBX, indexReg: RegBX, scale: 4, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x9b, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegBX/scale=8/offset=-1", baseReg: RegBX, indexReg: RegBX, scale: 8, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xdb, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegBP/scale=1/offset=-1", baseReg: RegBX, indexReg: RegBP, scale: 1, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x2b, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegBP/scale=2/offset=-1", baseReg: RegBX, indexReg: RegBP, scale: 2, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x6b, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegBP/scale=4/offset=-1", baseReg: RegBX, indexReg: RegBP, scale: 4, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xab, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegBP/scale=8/offset=-1", baseReg: RegBX, indexReg: RegBP, scale: 8, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xeb, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegSI/scale=1/offset=-1", baseReg: RegBX, indexReg: RegSI, scale: 1, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x33, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegSI/scale=2/offset=-1", baseReg: RegBX, indexReg: RegSI, scale: 2, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x73, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegSI/scale=4/offset=-1", baseReg: RegBX, indexReg: RegSI, scale: 4, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xb3, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegSI/scale=8/offset=-1", baseReg: RegBX, indexReg: RegSI, scale: 8, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xf3, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegDI/scale=1/offset=-1", baseReg: RegBX, indexReg: RegDI, scale: 1, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x3b, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegDI/scale=2/offset=-1", baseReg: RegBX, indexReg: RegDI, scale: 2, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x7b, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegDI/scale=4/offset=-1", baseReg: RegBX, indexReg: RegDI, scale: 4, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xbb, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegDI/scale=8/offset=-1", baseReg: RegBX, indexReg: RegDI, scale: 8, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xfb, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegR8/scale=1/offset=-1", baseReg: RegBX, indexReg: RegR8, scale: 1, offset: -1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x3, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegR8/scale=2/offset=-1", baseReg: RegBX, indexReg: RegR8, scale: 2, offset: -1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x43, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegR8/scale=4/offset=-1", baseReg: RegBX, indexReg: RegR8, scale: 4, offset: -1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x83, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegR8/scale=8/offset=-1", baseReg: RegBX, indexReg: RegR8, scale: 8, offset: -1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0xc3, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegR14/scale=1/offset=-1", baseReg: RegBX, indexReg: RegR14, scale: 1, offset: -1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x33, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegR14/scale=2/offset=-1", baseReg: RegBX, indexReg: RegR14, scale: 2, offset: -1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x73, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegR14/scale=4/offset=-1", baseReg: RegBX, indexReg: RegR14, scale: 4, offset: -1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0xb3, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegR14/scale=8/offset=-1", baseReg: RegBX, indexReg: RegR14, scale: 8, offset: -1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0xf3, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=Nil/scale=1/offset=-1", baseReg: RegBX, indexReg: asm.NilRegister, scale: 1, offset: -1, expRex: 0x0, expModRM: 0x43, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=Nil/scale=2/offset=-1", baseReg: RegBX, indexReg: asm.NilRegister, scale: 2, offset: -1, expRex: 0x0, expModRM: 0x43, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=Nil/scale=4/offset=-1", baseReg: RegBX, indexReg: asm.NilRegister, scale: 4, offset: -1, expRex: 0x0, expModRM: 0x43, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=Nil/scale=8/offset=-1", baseReg: RegBX, indexReg: asm.NilRegister, scale: 8, offset: -1, expRex: 0x0, expModRM: 0x43, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegBX/indexReg=RegAX/scale=1/offset=2147483647", baseReg: RegBX, indexReg: RegAX, scale: 1, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x3, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegAX/scale=2/offset=2147483647", baseReg: RegBX, indexReg: RegAX, scale: 2, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x43, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegAX/scale=4/offset=2147483647", baseReg: RegBX, indexReg: RegAX, scale: 4, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x83, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegAX/scale=8/offset=2147483647", baseReg: RegBX, indexReg: RegAX, scale: 8, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xc3, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegBX/scale=1/offset=2147483647", baseReg: RegBX, indexReg: RegBX, scale: 1, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x1b, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegBX/scale=2/offset=2147483647", baseReg: RegBX, indexReg: RegBX, scale: 2, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x5b, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegBX/scale=4/offset=2147483647", baseReg: RegBX, indexReg: RegBX, scale: 4, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x9b, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegBX/scale=8/offset=2147483647", baseReg: RegBX, indexReg: RegBX, scale: 8, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xdb, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegBP/scale=1/offset=2147483647", baseReg: RegBX, indexReg: RegBP, scale: 1, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x2b, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegBP/scale=2/offset=2147483647", baseReg: RegBX, indexReg: RegBP, scale: 2, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x6b, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegBP/scale=4/offset=2147483647", baseReg: RegBX, indexReg: RegBP, scale: 4, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xab, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegBP/scale=8/offset=2147483647", baseReg: RegBX, indexReg: RegBP, scale: 8, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xeb, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegSI/scale=1/offset=2147483647", baseReg: RegBX, indexReg: RegSI, scale: 1, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x33, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegSI/scale=2/offset=2147483647", baseReg: RegBX, indexReg: RegSI, scale: 2, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x73, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegSI/scale=4/offset=2147483647", baseReg: RegBX, indexReg: RegSI, scale: 4, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xb3, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegSI/scale=8/offset=2147483647", baseReg: RegBX, indexReg: RegSI, scale: 8, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xf3, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegDI/scale=1/offset=2147483647", baseReg: RegBX, indexReg: RegDI, scale: 1, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x3b, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegDI/scale=2/offset=2147483647", baseReg: RegBX, indexReg: RegDI, scale: 2, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x7b, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegDI/scale=4/offset=2147483647", baseReg: RegBX, indexReg: RegDI, scale: 4, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xbb, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegDI/scale=8/offset=2147483647", baseReg: RegBX, indexReg: RegDI, scale: 8, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xfb, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegR8/scale=1/offset=2147483647", baseReg: RegBX, indexReg: RegR8, scale: 1, offset: 2147483647, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x3, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegR8/scale=2/offset=2147483647", baseReg: RegBX, indexReg: RegR8, scale: 2, offset: 2147483647, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x43, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegR8/scale=4/offset=2147483647", baseReg: RegBX, indexReg: RegR8, scale: 4, offset: 2147483647, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x83, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegR8/scale=8/offset=2147483647", baseReg: RegBX, indexReg: RegR8, scale: 8, offset: 2147483647, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0xc3, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegR14/scale=1/offset=2147483647", baseReg: RegBX, indexReg: RegR14, scale: 1, offset: 2147483647, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x33, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegR14/scale=2/offset=2147483647", baseReg: RegBX, indexReg: RegR14, scale: 2, offset: 2147483647, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x73, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegR14/scale=4/offset=2147483647", baseReg: RegBX, indexReg: RegR14, scale: 4, offset: 2147483647, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0xb3, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegR14/scale=8/offset=2147483647", baseReg: RegBX, indexReg: RegR14, scale: 8, offset: 2147483647, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0xf3, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=Nil/scale=1/offset=2147483647", baseReg: RegBX, indexReg: asm.NilRegister, scale: 1, offset: 2147483647, expRex: 0x0, expModRM: 0x83, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=Nil/scale=2/offset=2147483647", baseReg: RegBX, indexReg: asm.NilRegister, scale: 2, offset: 2147483647, expRex: 0x0, expModRM: 0x83, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=Nil/scale=4/offset=2147483647", baseReg: RegBX, indexReg: asm.NilRegister, scale: 4, offset: 2147483647, expRex: 0x0, expModRM: 0x83, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=Nil/scale=8/offset=2147483647", baseReg: RegBX, indexReg: asm.NilRegister, scale: 8, offset: 2147483647, expRex: 0x0, expModRM: 0x83, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegAX/scale=1/offset=-2147483648", baseReg: RegBX, indexReg: RegAX, scale: 1, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x3, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegAX/scale=2/offset=-2147483648", baseReg: RegBX, indexReg: RegAX, scale: 2, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x43, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegAX/scale=4/offset=-2147483648", baseReg: RegBX, indexReg: RegAX, scale: 4, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x83, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegAX/scale=8/offset=-2147483648", baseReg: RegBX, indexReg: RegAX, scale: 8, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xc3, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegBX/scale=1/offset=-2147483648", baseReg: RegBX, indexReg: RegBX, scale: 1, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x1b, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegBX/scale=2/offset=-2147483648", baseReg: RegBX, indexReg: RegBX, scale: 2, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x5b, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegBX/scale=4/offset=-2147483648", baseReg: RegBX, indexReg: RegBX, scale: 4, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x9b, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegBX/scale=8/offset=-2147483648", baseReg: RegBX, indexReg: RegBX, scale: 8, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xdb, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegBP/scale=1/offset=-2147483648", baseReg: RegBX, indexReg: RegBP, scale: 1, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x2b, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegBP/scale=2/offset=-2147483648", baseReg: RegBX, indexReg: RegBP, scale: 2, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x6b, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegBP/scale=4/offset=-2147483648", baseReg: RegBX, indexReg: RegBP, scale: 4, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xab, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegBP/scale=8/offset=-2147483648", baseReg: RegBX, indexReg: RegBP, scale: 8, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xeb, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegSI/scale=1/offset=-2147483648", baseReg: RegBX, indexReg: RegSI, scale: 1, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x33, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegSI/scale=2/offset=-2147483648", baseReg: RegBX, indexReg: RegSI, scale: 2, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x73, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegSI/scale=4/offset=-2147483648", baseReg: RegBX, indexReg: RegSI, scale: 4, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xb3, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegSI/scale=8/offset=-2147483648", baseReg: RegBX, indexReg: RegSI, scale: 8, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xf3, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegDI/scale=1/offset=-2147483648", baseReg: RegBX, indexReg: RegDI, scale: 1, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x3b, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegDI/scale=2/offset=-2147483648", baseReg: RegBX, indexReg: RegDI, scale: 2, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x7b, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegDI/scale=4/offset=-2147483648", baseReg: RegBX, indexReg: RegDI, scale: 4, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xbb, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegDI/scale=8/offset=-2147483648", baseReg: RegBX, indexReg: RegDI, scale: 8, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xfb, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegR8/scale=1/offset=-2147483648", baseReg: RegBX, indexReg: RegR8, scale: 1, offset: -2147483648, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x3, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegR8/scale=2/offset=-2147483648", baseReg: RegBX, indexReg: RegR8, scale: 2, offset: -2147483648, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x43, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegR8/scale=4/offset=-2147483648", baseReg: RegBX, indexReg: RegR8, scale: 4, offset: -2147483648, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x83, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegR8/scale=8/offset=-2147483648", baseReg: RegBX, indexReg: RegR8, scale: 8, offset: -2147483648, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0xc3, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegR14/scale=1/offset=-2147483648", baseReg: RegBX, indexReg: RegR14, scale: 1, offset: -2147483648, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x33, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegR14/scale=2/offset=-2147483648", baseReg: RegBX, indexReg: RegR14, scale: 2, offset: -2147483648, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x73, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegR14/scale=4/offset=-2147483648", baseReg: RegBX, indexReg: RegR14, scale: 4, offset: -2147483648, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0xb3, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=RegR14/scale=8/offset=-2147483648", baseReg: RegBX, indexReg: RegR14, scale: 8, offset: -2147483648, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0xf3, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=Nil/scale=1/offset=-2147483648", baseReg: RegBX, indexReg: asm.NilRegister, scale: 1, offset: -2147483648, expRex: 0x0, expModRM: 0x83, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=Nil/scale=2/offset=-2147483648", baseReg: RegBX, indexReg: asm.NilRegister, scale: 2, offset: -2147483648, expRex: 0x0, expModRM: 0x83, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=Nil/scale=4/offset=-2147483648", baseReg: RegBX, indexReg: asm.NilRegister, scale: 4, offset: -2147483648, expRex: 0x0, expModRM: 0x83, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegBX/indexReg=Nil/scale=8/offset=-2147483648", baseReg: RegBX, indexReg: asm.NilRegister, scale: 8, offset: -2147483648, expRex: 0x0, expModRM: 0x83, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegAX/scale=1/offset=0", baseReg: RegSP, indexReg: RegAX, scale: 1, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x4, displacementWidth: 0}, - {name: "baseReg=RegSP/indexReg=RegAX/scale=2/offset=0", baseReg: RegSP, indexReg: RegAX, scale: 2, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x44, displacementWidth: 0}, - {name: "baseReg=RegSP/indexReg=RegAX/scale=4/offset=0", baseReg: RegSP, indexReg: RegAX, scale: 4, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x84, displacementWidth: 0}, - {name: "baseReg=RegSP/indexReg=RegAX/scale=8/offset=0", baseReg: RegSP, indexReg: RegAX, scale: 8, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0xc4, displacementWidth: 0}, - {name: "baseReg=RegSP/indexReg=RegBX/scale=1/offset=0", baseReg: RegSP, indexReg: RegBX, scale: 1, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x1c, displacementWidth: 0}, - {name: "baseReg=RegSP/indexReg=RegBX/scale=2/offset=0", baseReg: RegSP, indexReg: RegBX, scale: 2, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x5c, displacementWidth: 0}, - {name: "baseReg=RegSP/indexReg=RegBX/scale=4/offset=0", baseReg: RegSP, indexReg: RegBX, scale: 4, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x9c, displacementWidth: 0}, - {name: "baseReg=RegSP/indexReg=RegBX/scale=8/offset=0", baseReg: RegSP, indexReg: RegBX, scale: 8, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0xdc, displacementWidth: 0}, - {name: "baseReg=RegSP/indexReg=RegBP/scale=1/offset=0", baseReg: RegSP, indexReg: RegBP, scale: 1, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x2c, displacementWidth: 0}, - {name: "baseReg=RegSP/indexReg=RegBP/scale=2/offset=0", baseReg: RegSP, indexReg: RegBP, scale: 2, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x6c, displacementWidth: 0}, - {name: "baseReg=RegSP/indexReg=RegBP/scale=4/offset=0", baseReg: RegSP, indexReg: RegBP, scale: 4, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0xac, displacementWidth: 0}, - {name: "baseReg=RegSP/indexReg=RegBP/scale=8/offset=0", baseReg: RegSP, indexReg: RegBP, scale: 8, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0xec, displacementWidth: 0}, - {name: "baseReg=RegSP/indexReg=RegSI/scale=1/offset=0", baseReg: RegSP, indexReg: RegSI, scale: 1, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x34, displacementWidth: 0}, - {name: "baseReg=RegSP/indexReg=RegSI/scale=2/offset=0", baseReg: RegSP, indexReg: RegSI, scale: 2, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x74, displacementWidth: 0}, - {name: "baseReg=RegSP/indexReg=RegSI/scale=4/offset=0", baseReg: RegSP, indexReg: RegSI, scale: 4, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0xb4, displacementWidth: 0}, - {name: "baseReg=RegSP/indexReg=RegSI/scale=8/offset=0", baseReg: RegSP, indexReg: RegSI, scale: 8, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0xf4, displacementWidth: 0}, - {name: "baseReg=RegSP/indexReg=RegDI/scale=1/offset=0", baseReg: RegSP, indexReg: RegDI, scale: 1, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x3c, displacementWidth: 0}, - {name: "baseReg=RegSP/indexReg=RegDI/scale=2/offset=0", baseReg: RegSP, indexReg: RegDI, scale: 2, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x7c, displacementWidth: 0}, - {name: "baseReg=RegSP/indexReg=RegDI/scale=4/offset=0", baseReg: RegSP, indexReg: RegDI, scale: 4, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0xbc, displacementWidth: 0}, - {name: "baseReg=RegSP/indexReg=RegDI/scale=8/offset=0", baseReg: RegSP, indexReg: RegDI, scale: 8, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0xfc, displacementWidth: 0}, - {name: "baseReg=RegSP/indexReg=RegR8/scale=1/offset=0", baseReg: RegSP, indexReg: RegR8, scale: 1, offset: 0, expRex: 0x42, expModRM: 0x4, needSBI: true, expSBI: 0x4, displacementWidth: 0}, - {name: "baseReg=RegSP/indexReg=RegR8/scale=2/offset=0", baseReg: RegSP, indexReg: RegR8, scale: 2, offset: 0, expRex: 0x42, expModRM: 0x4, needSBI: true, expSBI: 0x44, displacementWidth: 0}, - {name: "baseReg=RegSP/indexReg=RegR8/scale=4/offset=0", baseReg: RegSP, indexReg: RegR8, scale: 4, offset: 0, expRex: 0x42, expModRM: 0x4, needSBI: true, expSBI: 0x84, displacementWidth: 0}, - {name: "baseReg=RegSP/indexReg=RegR8/scale=8/offset=0", baseReg: RegSP, indexReg: RegR8, scale: 8, offset: 0, expRex: 0x42, expModRM: 0x4, needSBI: true, expSBI: 0xc4, displacementWidth: 0}, - {name: "baseReg=RegSP/indexReg=RegR14/scale=1/offset=0", baseReg: RegSP, indexReg: RegR14, scale: 1, offset: 0, expRex: 0x42, expModRM: 0x4, needSBI: true, expSBI: 0x34, displacementWidth: 0}, - {name: "baseReg=RegSP/indexReg=RegR14/scale=2/offset=0", baseReg: RegSP, indexReg: RegR14, scale: 2, offset: 0, expRex: 0x42, expModRM: 0x4, needSBI: true, expSBI: 0x74, displacementWidth: 0}, - {name: "baseReg=RegSP/indexReg=RegR14/scale=4/offset=0", baseReg: RegSP, indexReg: RegR14, scale: 4, offset: 0, expRex: 0x42, expModRM: 0x4, needSBI: true, expSBI: 0xb4, displacementWidth: 0}, - {name: "baseReg=RegSP/indexReg=RegR14/scale=8/offset=0", baseReg: RegSP, indexReg: RegR14, scale: 8, offset: 0, expRex: 0x42, expModRM: 0x4, needSBI: true, expSBI: 0xf4, displacementWidth: 0}, - {name: "baseReg=RegSP/indexReg=Nil/scale=1/offset=0", baseReg: RegSP, indexReg: asm.NilRegister, scale: 1, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x24, displacementWidth: 0}, - {name: "baseReg=RegSP/indexReg=Nil/scale=2/offset=0", baseReg: RegSP, indexReg: asm.NilRegister, scale: 2, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x24, displacementWidth: 0}, - {name: "baseReg=RegSP/indexReg=Nil/scale=4/offset=0", baseReg: RegSP, indexReg: asm.NilRegister, scale: 4, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x24, displacementWidth: 0}, - {name: "baseReg=RegSP/indexReg=Nil/scale=8/offset=0", baseReg: RegSP, indexReg: asm.NilRegister, scale: 8, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x24, displacementWidth: 0}, - {name: "baseReg=RegSP/indexReg=RegAX/scale=1/offset=1", baseReg: RegSP, indexReg: RegAX, scale: 1, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x4, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegAX/scale=2/offset=1", baseReg: RegSP, indexReg: RegAX, scale: 2, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x44, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegAX/scale=4/offset=1", baseReg: RegSP, indexReg: RegAX, scale: 4, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x84, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegAX/scale=8/offset=1", baseReg: RegSP, indexReg: RegAX, scale: 8, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xc4, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegBX/scale=1/offset=1", baseReg: RegSP, indexReg: RegBX, scale: 1, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x1c, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegBX/scale=2/offset=1", baseReg: RegSP, indexReg: RegBX, scale: 2, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x5c, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegBX/scale=4/offset=1", baseReg: RegSP, indexReg: RegBX, scale: 4, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x9c, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegBX/scale=8/offset=1", baseReg: RegSP, indexReg: RegBX, scale: 8, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xdc, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegBP/scale=1/offset=1", baseReg: RegSP, indexReg: RegBP, scale: 1, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x2c, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegBP/scale=2/offset=1", baseReg: RegSP, indexReg: RegBP, scale: 2, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x6c, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegBP/scale=4/offset=1", baseReg: RegSP, indexReg: RegBP, scale: 4, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xac, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegBP/scale=8/offset=1", baseReg: RegSP, indexReg: RegBP, scale: 8, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xec, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegSI/scale=1/offset=1", baseReg: RegSP, indexReg: RegSI, scale: 1, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x34, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegSI/scale=2/offset=1", baseReg: RegSP, indexReg: RegSI, scale: 2, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x74, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegSI/scale=4/offset=1", baseReg: RegSP, indexReg: RegSI, scale: 4, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xb4, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegSI/scale=8/offset=1", baseReg: RegSP, indexReg: RegSI, scale: 8, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xf4, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegDI/scale=1/offset=1", baseReg: RegSP, indexReg: RegDI, scale: 1, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x3c, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegDI/scale=2/offset=1", baseReg: RegSP, indexReg: RegDI, scale: 2, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x7c, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegDI/scale=4/offset=1", baseReg: RegSP, indexReg: RegDI, scale: 4, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xbc, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegDI/scale=8/offset=1", baseReg: RegSP, indexReg: RegDI, scale: 8, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xfc, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegR8/scale=1/offset=1", baseReg: RegSP, indexReg: RegR8, scale: 1, offset: 1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x4, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegR8/scale=2/offset=1", baseReg: RegSP, indexReg: RegR8, scale: 2, offset: 1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x44, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegR8/scale=4/offset=1", baseReg: RegSP, indexReg: RegR8, scale: 4, offset: 1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x84, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegR8/scale=8/offset=1", baseReg: RegSP, indexReg: RegR8, scale: 8, offset: 1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0xc4, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegR14/scale=1/offset=1", baseReg: RegSP, indexReg: RegR14, scale: 1, offset: 1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x34, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegR14/scale=2/offset=1", baseReg: RegSP, indexReg: RegR14, scale: 2, offset: 1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x74, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegR14/scale=4/offset=1", baseReg: RegSP, indexReg: RegR14, scale: 4, offset: 1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0xb4, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegR14/scale=8/offset=1", baseReg: RegSP, indexReg: RegR14, scale: 8, offset: 1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0xf4, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=Nil/scale=1/offset=1", baseReg: RegSP, indexReg: asm.NilRegister, scale: 1, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x24, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=Nil/scale=2/offset=1", baseReg: RegSP, indexReg: asm.NilRegister, scale: 2, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x24, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=Nil/scale=4/offset=1", baseReg: RegSP, indexReg: asm.NilRegister, scale: 4, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x24, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=Nil/scale=8/offset=1", baseReg: RegSP, indexReg: asm.NilRegister, scale: 8, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x24, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegAX/scale=1/offset=-1", baseReg: RegSP, indexReg: RegAX, scale: 1, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x4, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegAX/scale=2/offset=-1", baseReg: RegSP, indexReg: RegAX, scale: 2, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x44, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegAX/scale=4/offset=-1", baseReg: RegSP, indexReg: RegAX, scale: 4, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x84, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegAX/scale=8/offset=-1", baseReg: RegSP, indexReg: RegAX, scale: 8, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xc4, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegBX/scale=1/offset=-1", baseReg: RegSP, indexReg: RegBX, scale: 1, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x1c, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegBX/scale=2/offset=-1", baseReg: RegSP, indexReg: RegBX, scale: 2, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x5c, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegBX/scale=4/offset=-1", baseReg: RegSP, indexReg: RegBX, scale: 4, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x9c, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegBX/scale=8/offset=-1", baseReg: RegSP, indexReg: RegBX, scale: 8, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xdc, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegBP/scale=1/offset=-1", baseReg: RegSP, indexReg: RegBP, scale: 1, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x2c, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegBP/scale=2/offset=-1", baseReg: RegSP, indexReg: RegBP, scale: 2, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x6c, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegBP/scale=4/offset=-1", baseReg: RegSP, indexReg: RegBP, scale: 4, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xac, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegBP/scale=8/offset=-1", baseReg: RegSP, indexReg: RegBP, scale: 8, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xec, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegSI/scale=1/offset=-1", baseReg: RegSP, indexReg: RegSI, scale: 1, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x34, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegSI/scale=2/offset=-1", baseReg: RegSP, indexReg: RegSI, scale: 2, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x74, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegSI/scale=4/offset=-1", baseReg: RegSP, indexReg: RegSI, scale: 4, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xb4, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegSI/scale=8/offset=-1", baseReg: RegSP, indexReg: RegSI, scale: 8, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xf4, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegDI/scale=1/offset=-1", baseReg: RegSP, indexReg: RegDI, scale: 1, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x3c, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegDI/scale=2/offset=-1", baseReg: RegSP, indexReg: RegDI, scale: 2, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x7c, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegDI/scale=4/offset=-1", baseReg: RegSP, indexReg: RegDI, scale: 4, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xbc, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegDI/scale=8/offset=-1", baseReg: RegSP, indexReg: RegDI, scale: 8, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xfc, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegR8/scale=1/offset=-1", baseReg: RegSP, indexReg: RegR8, scale: 1, offset: -1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x4, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegR8/scale=2/offset=-1", baseReg: RegSP, indexReg: RegR8, scale: 2, offset: -1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x44, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegR8/scale=4/offset=-1", baseReg: RegSP, indexReg: RegR8, scale: 4, offset: -1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x84, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegR8/scale=8/offset=-1", baseReg: RegSP, indexReg: RegR8, scale: 8, offset: -1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0xc4, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegR14/scale=1/offset=-1", baseReg: RegSP, indexReg: RegR14, scale: 1, offset: -1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x34, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegR14/scale=2/offset=-1", baseReg: RegSP, indexReg: RegR14, scale: 2, offset: -1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x74, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegR14/scale=4/offset=-1", baseReg: RegSP, indexReg: RegR14, scale: 4, offset: -1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0xb4, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegR14/scale=8/offset=-1", baseReg: RegSP, indexReg: RegR14, scale: 8, offset: -1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0xf4, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=Nil/scale=1/offset=-1", baseReg: RegSP, indexReg: asm.NilRegister, scale: 1, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x24, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=Nil/scale=2/offset=-1", baseReg: RegSP, indexReg: asm.NilRegister, scale: 2, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x24, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=Nil/scale=4/offset=-1", baseReg: RegSP, indexReg: asm.NilRegister, scale: 4, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x24, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=Nil/scale=8/offset=-1", baseReg: RegSP, indexReg: asm.NilRegister, scale: 8, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x24, displacementWidth: 8}, - {name: "baseReg=RegSP/indexReg=RegAX/scale=1/offset=2147483647", baseReg: RegSP, indexReg: RegAX, scale: 1, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x4, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegAX/scale=2/offset=2147483647", baseReg: RegSP, indexReg: RegAX, scale: 2, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x44, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegAX/scale=4/offset=2147483647", baseReg: RegSP, indexReg: RegAX, scale: 4, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x84, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegAX/scale=8/offset=2147483647", baseReg: RegSP, indexReg: RegAX, scale: 8, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xc4, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegBX/scale=1/offset=2147483647", baseReg: RegSP, indexReg: RegBX, scale: 1, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x1c, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegBX/scale=2/offset=2147483647", baseReg: RegSP, indexReg: RegBX, scale: 2, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x5c, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegBX/scale=4/offset=2147483647", baseReg: RegSP, indexReg: RegBX, scale: 4, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x9c, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegBX/scale=8/offset=2147483647", baseReg: RegSP, indexReg: RegBX, scale: 8, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xdc, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegBP/scale=1/offset=2147483647", baseReg: RegSP, indexReg: RegBP, scale: 1, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x2c, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegBP/scale=2/offset=2147483647", baseReg: RegSP, indexReg: RegBP, scale: 2, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x6c, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegBP/scale=4/offset=2147483647", baseReg: RegSP, indexReg: RegBP, scale: 4, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xac, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegBP/scale=8/offset=2147483647", baseReg: RegSP, indexReg: RegBP, scale: 8, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xec, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegSI/scale=1/offset=2147483647", baseReg: RegSP, indexReg: RegSI, scale: 1, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x34, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegSI/scale=2/offset=2147483647", baseReg: RegSP, indexReg: RegSI, scale: 2, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x74, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegSI/scale=4/offset=2147483647", baseReg: RegSP, indexReg: RegSI, scale: 4, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xb4, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegSI/scale=8/offset=2147483647", baseReg: RegSP, indexReg: RegSI, scale: 8, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xf4, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegDI/scale=1/offset=2147483647", baseReg: RegSP, indexReg: RegDI, scale: 1, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x3c, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegDI/scale=2/offset=2147483647", baseReg: RegSP, indexReg: RegDI, scale: 2, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x7c, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegDI/scale=4/offset=2147483647", baseReg: RegSP, indexReg: RegDI, scale: 4, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xbc, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegDI/scale=8/offset=2147483647", baseReg: RegSP, indexReg: RegDI, scale: 8, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xfc, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegR8/scale=1/offset=2147483647", baseReg: RegSP, indexReg: RegR8, scale: 1, offset: 2147483647, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x4, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegR8/scale=2/offset=2147483647", baseReg: RegSP, indexReg: RegR8, scale: 2, offset: 2147483647, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x44, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegR8/scale=4/offset=2147483647", baseReg: RegSP, indexReg: RegR8, scale: 4, offset: 2147483647, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x84, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegR8/scale=8/offset=2147483647", baseReg: RegSP, indexReg: RegR8, scale: 8, offset: 2147483647, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0xc4, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegR14/scale=1/offset=2147483647", baseReg: RegSP, indexReg: RegR14, scale: 1, offset: 2147483647, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x34, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegR14/scale=2/offset=2147483647", baseReg: RegSP, indexReg: RegR14, scale: 2, offset: 2147483647, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x74, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegR14/scale=4/offset=2147483647", baseReg: RegSP, indexReg: RegR14, scale: 4, offset: 2147483647, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0xb4, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegR14/scale=8/offset=2147483647", baseReg: RegSP, indexReg: RegR14, scale: 8, offset: 2147483647, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0xf4, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=Nil/scale=1/offset=2147483647", baseReg: RegSP, indexReg: asm.NilRegister, scale: 1, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x24, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=Nil/scale=2/offset=2147483647", baseReg: RegSP, indexReg: asm.NilRegister, scale: 2, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x24, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=Nil/scale=4/offset=2147483647", baseReg: RegSP, indexReg: asm.NilRegister, scale: 4, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x24, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=Nil/scale=8/offset=2147483647", baseReg: RegSP, indexReg: asm.NilRegister, scale: 8, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x24, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegAX/scale=1/offset=-2147483648", baseReg: RegSP, indexReg: RegAX, scale: 1, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x4, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegAX/scale=2/offset=-2147483648", baseReg: RegSP, indexReg: RegAX, scale: 2, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x44, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegAX/scale=4/offset=-2147483648", baseReg: RegSP, indexReg: RegAX, scale: 4, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x84, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegAX/scale=8/offset=-2147483648", baseReg: RegSP, indexReg: RegAX, scale: 8, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xc4, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegBX/scale=1/offset=-2147483648", baseReg: RegSP, indexReg: RegBX, scale: 1, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x1c, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegBX/scale=2/offset=-2147483648", baseReg: RegSP, indexReg: RegBX, scale: 2, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x5c, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegBX/scale=4/offset=-2147483648", baseReg: RegSP, indexReg: RegBX, scale: 4, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x9c, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegBX/scale=8/offset=-2147483648", baseReg: RegSP, indexReg: RegBX, scale: 8, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xdc, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegBP/scale=1/offset=-2147483648", baseReg: RegSP, indexReg: RegBP, scale: 1, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x2c, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegBP/scale=2/offset=-2147483648", baseReg: RegSP, indexReg: RegBP, scale: 2, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x6c, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegBP/scale=4/offset=-2147483648", baseReg: RegSP, indexReg: RegBP, scale: 4, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xac, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegBP/scale=8/offset=-2147483648", baseReg: RegSP, indexReg: RegBP, scale: 8, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xec, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegSI/scale=1/offset=-2147483648", baseReg: RegSP, indexReg: RegSI, scale: 1, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x34, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegSI/scale=2/offset=-2147483648", baseReg: RegSP, indexReg: RegSI, scale: 2, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x74, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegSI/scale=4/offset=-2147483648", baseReg: RegSP, indexReg: RegSI, scale: 4, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xb4, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegSI/scale=8/offset=-2147483648", baseReg: RegSP, indexReg: RegSI, scale: 8, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xf4, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegDI/scale=1/offset=-2147483648", baseReg: RegSP, indexReg: RegDI, scale: 1, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x3c, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegDI/scale=2/offset=-2147483648", baseReg: RegSP, indexReg: RegDI, scale: 2, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x7c, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegDI/scale=4/offset=-2147483648", baseReg: RegSP, indexReg: RegDI, scale: 4, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xbc, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegDI/scale=8/offset=-2147483648", baseReg: RegSP, indexReg: RegDI, scale: 8, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xfc, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegR8/scale=1/offset=-2147483648", baseReg: RegSP, indexReg: RegR8, scale: 1, offset: -2147483648, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x4, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegR8/scale=2/offset=-2147483648", baseReg: RegSP, indexReg: RegR8, scale: 2, offset: -2147483648, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x44, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegR8/scale=4/offset=-2147483648", baseReg: RegSP, indexReg: RegR8, scale: 4, offset: -2147483648, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x84, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegR8/scale=8/offset=-2147483648", baseReg: RegSP, indexReg: RegR8, scale: 8, offset: -2147483648, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0xc4, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegR14/scale=1/offset=-2147483648", baseReg: RegSP, indexReg: RegR14, scale: 1, offset: -2147483648, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x34, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegR14/scale=2/offset=-2147483648", baseReg: RegSP, indexReg: RegR14, scale: 2, offset: -2147483648, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x74, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegR14/scale=4/offset=-2147483648", baseReg: RegSP, indexReg: RegR14, scale: 4, offset: -2147483648, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0xb4, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=RegR14/scale=8/offset=-2147483648", baseReg: RegSP, indexReg: RegR14, scale: 8, offset: -2147483648, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0xf4, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=Nil/scale=1/offset=-2147483648", baseReg: RegSP, indexReg: asm.NilRegister, scale: 1, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x24, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=Nil/scale=2/offset=-2147483648", baseReg: RegSP, indexReg: asm.NilRegister, scale: 2, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x24, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=Nil/scale=4/offset=-2147483648", baseReg: RegSP, indexReg: asm.NilRegister, scale: 4, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x24, displacementWidth: 32}, - {name: "baseReg=RegSP/indexReg=Nil/scale=8/offset=-2147483648", baseReg: RegSP, indexReg: asm.NilRegister, scale: 8, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x24, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegAX/scale=1/offset=0", baseReg: RegBP, indexReg: RegAX, scale: 1, offset: 0, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x5, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegAX/scale=2/offset=0", baseReg: RegBP, indexReg: RegAX, scale: 2, offset: 0, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x45, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegAX/scale=4/offset=0", baseReg: RegBP, indexReg: RegAX, scale: 4, offset: 0, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x85, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegAX/scale=8/offset=0", baseReg: RegBP, indexReg: RegAX, scale: 8, offset: 0, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xc5, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegBX/scale=1/offset=0", baseReg: RegBP, indexReg: RegBX, scale: 1, offset: 0, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x1d, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegBX/scale=2/offset=0", baseReg: RegBP, indexReg: RegBX, scale: 2, offset: 0, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x5d, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegBX/scale=4/offset=0", baseReg: RegBP, indexReg: RegBX, scale: 4, offset: 0, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x9d, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegBX/scale=8/offset=0", baseReg: RegBP, indexReg: RegBX, scale: 8, offset: 0, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xdd, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegBP/scale=1/offset=0", baseReg: RegBP, indexReg: RegBP, scale: 1, offset: 0, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x2d, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegBP/scale=2/offset=0", baseReg: RegBP, indexReg: RegBP, scale: 2, offset: 0, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x6d, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegBP/scale=4/offset=0", baseReg: RegBP, indexReg: RegBP, scale: 4, offset: 0, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xad, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegBP/scale=8/offset=0", baseReg: RegBP, indexReg: RegBP, scale: 8, offset: 0, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xed, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegSI/scale=1/offset=0", baseReg: RegBP, indexReg: RegSI, scale: 1, offset: 0, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x35, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegSI/scale=2/offset=0", baseReg: RegBP, indexReg: RegSI, scale: 2, offset: 0, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x75, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegSI/scale=4/offset=0", baseReg: RegBP, indexReg: RegSI, scale: 4, offset: 0, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xb5, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegSI/scale=8/offset=0", baseReg: RegBP, indexReg: RegSI, scale: 8, offset: 0, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xf5, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegDI/scale=1/offset=0", baseReg: RegBP, indexReg: RegDI, scale: 1, offset: 0, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x3d, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegDI/scale=2/offset=0", baseReg: RegBP, indexReg: RegDI, scale: 2, offset: 0, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x7d, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegDI/scale=4/offset=0", baseReg: RegBP, indexReg: RegDI, scale: 4, offset: 0, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xbd, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegDI/scale=8/offset=0", baseReg: RegBP, indexReg: RegDI, scale: 8, offset: 0, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xfd, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegR8/scale=1/offset=0", baseReg: RegBP, indexReg: RegR8, scale: 1, offset: 0, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x5, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegR8/scale=2/offset=0", baseReg: RegBP, indexReg: RegR8, scale: 2, offset: 0, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x45, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegR8/scale=4/offset=0", baseReg: RegBP, indexReg: RegR8, scale: 4, offset: 0, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x85, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegR8/scale=8/offset=0", baseReg: RegBP, indexReg: RegR8, scale: 8, offset: 0, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0xc5, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegR14/scale=1/offset=0", baseReg: RegBP, indexReg: RegR14, scale: 1, offset: 0, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x35, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegR14/scale=2/offset=0", baseReg: RegBP, indexReg: RegR14, scale: 2, offset: 0, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x75, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegR14/scale=4/offset=0", baseReg: RegBP, indexReg: RegR14, scale: 4, offset: 0, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0xb5, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegR14/scale=8/offset=0", baseReg: RegBP, indexReg: RegR14, scale: 8, offset: 0, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0xf5, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=Nil/scale=1/offset=0", baseReg: RegBP, indexReg: asm.NilRegister, scale: 1, offset: 0, expRex: 0x0, expModRM: 0x45, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=Nil/scale=2/offset=0", baseReg: RegBP, indexReg: asm.NilRegister, scale: 2, offset: 0, expRex: 0x0, expModRM: 0x45, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=Nil/scale=4/offset=0", baseReg: RegBP, indexReg: asm.NilRegister, scale: 4, offset: 0, expRex: 0x0, expModRM: 0x45, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=Nil/scale=8/offset=0", baseReg: RegBP, indexReg: asm.NilRegister, scale: 8, offset: 0, expRex: 0x0, expModRM: 0x45, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegAX/scale=1/offset=1", baseReg: RegBP, indexReg: RegAX, scale: 1, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x5, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegAX/scale=2/offset=1", baseReg: RegBP, indexReg: RegAX, scale: 2, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x45, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegAX/scale=4/offset=1", baseReg: RegBP, indexReg: RegAX, scale: 4, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x85, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegAX/scale=8/offset=1", baseReg: RegBP, indexReg: RegAX, scale: 8, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xc5, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegBX/scale=1/offset=1", baseReg: RegBP, indexReg: RegBX, scale: 1, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x1d, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegBX/scale=2/offset=1", baseReg: RegBP, indexReg: RegBX, scale: 2, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x5d, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegBX/scale=4/offset=1", baseReg: RegBP, indexReg: RegBX, scale: 4, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x9d, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegBX/scale=8/offset=1", baseReg: RegBP, indexReg: RegBX, scale: 8, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xdd, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegBP/scale=1/offset=1", baseReg: RegBP, indexReg: RegBP, scale: 1, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x2d, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegBP/scale=2/offset=1", baseReg: RegBP, indexReg: RegBP, scale: 2, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x6d, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegBP/scale=4/offset=1", baseReg: RegBP, indexReg: RegBP, scale: 4, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xad, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegBP/scale=8/offset=1", baseReg: RegBP, indexReg: RegBP, scale: 8, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xed, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegSI/scale=1/offset=1", baseReg: RegBP, indexReg: RegSI, scale: 1, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x35, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegSI/scale=2/offset=1", baseReg: RegBP, indexReg: RegSI, scale: 2, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x75, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegSI/scale=4/offset=1", baseReg: RegBP, indexReg: RegSI, scale: 4, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xb5, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegSI/scale=8/offset=1", baseReg: RegBP, indexReg: RegSI, scale: 8, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xf5, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegDI/scale=1/offset=1", baseReg: RegBP, indexReg: RegDI, scale: 1, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x3d, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegDI/scale=2/offset=1", baseReg: RegBP, indexReg: RegDI, scale: 2, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x7d, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegDI/scale=4/offset=1", baseReg: RegBP, indexReg: RegDI, scale: 4, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xbd, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegDI/scale=8/offset=1", baseReg: RegBP, indexReg: RegDI, scale: 8, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xfd, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegR8/scale=1/offset=1", baseReg: RegBP, indexReg: RegR8, scale: 1, offset: 1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x5, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegR8/scale=2/offset=1", baseReg: RegBP, indexReg: RegR8, scale: 2, offset: 1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x45, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegR8/scale=4/offset=1", baseReg: RegBP, indexReg: RegR8, scale: 4, offset: 1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x85, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegR8/scale=8/offset=1", baseReg: RegBP, indexReg: RegR8, scale: 8, offset: 1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0xc5, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegR14/scale=1/offset=1", baseReg: RegBP, indexReg: RegR14, scale: 1, offset: 1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x35, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegR14/scale=2/offset=1", baseReg: RegBP, indexReg: RegR14, scale: 2, offset: 1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x75, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegR14/scale=4/offset=1", baseReg: RegBP, indexReg: RegR14, scale: 4, offset: 1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0xb5, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegR14/scale=8/offset=1", baseReg: RegBP, indexReg: RegR14, scale: 8, offset: 1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0xf5, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=Nil/scale=1/offset=1", baseReg: RegBP, indexReg: asm.NilRegister, scale: 1, offset: 1, expRex: 0x0, expModRM: 0x45, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=Nil/scale=2/offset=1", baseReg: RegBP, indexReg: asm.NilRegister, scale: 2, offset: 1, expRex: 0x0, expModRM: 0x45, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=Nil/scale=4/offset=1", baseReg: RegBP, indexReg: asm.NilRegister, scale: 4, offset: 1, expRex: 0x0, expModRM: 0x45, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=Nil/scale=8/offset=1", baseReg: RegBP, indexReg: asm.NilRegister, scale: 8, offset: 1, expRex: 0x0, expModRM: 0x45, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegAX/scale=1/offset=-1", baseReg: RegBP, indexReg: RegAX, scale: 1, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x5, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegAX/scale=2/offset=-1", baseReg: RegBP, indexReg: RegAX, scale: 2, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x45, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegAX/scale=4/offset=-1", baseReg: RegBP, indexReg: RegAX, scale: 4, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x85, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegAX/scale=8/offset=-1", baseReg: RegBP, indexReg: RegAX, scale: 8, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xc5, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegBX/scale=1/offset=-1", baseReg: RegBP, indexReg: RegBX, scale: 1, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x1d, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegBX/scale=2/offset=-1", baseReg: RegBP, indexReg: RegBX, scale: 2, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x5d, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegBX/scale=4/offset=-1", baseReg: RegBP, indexReg: RegBX, scale: 4, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x9d, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegBX/scale=8/offset=-1", baseReg: RegBP, indexReg: RegBX, scale: 8, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xdd, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegBP/scale=1/offset=-1", baseReg: RegBP, indexReg: RegBP, scale: 1, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x2d, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegBP/scale=2/offset=-1", baseReg: RegBP, indexReg: RegBP, scale: 2, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x6d, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegBP/scale=4/offset=-1", baseReg: RegBP, indexReg: RegBP, scale: 4, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xad, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegBP/scale=8/offset=-1", baseReg: RegBP, indexReg: RegBP, scale: 8, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xed, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegSI/scale=1/offset=-1", baseReg: RegBP, indexReg: RegSI, scale: 1, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x35, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegSI/scale=2/offset=-1", baseReg: RegBP, indexReg: RegSI, scale: 2, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x75, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegSI/scale=4/offset=-1", baseReg: RegBP, indexReg: RegSI, scale: 4, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xb5, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegSI/scale=8/offset=-1", baseReg: RegBP, indexReg: RegSI, scale: 8, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xf5, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegDI/scale=1/offset=-1", baseReg: RegBP, indexReg: RegDI, scale: 1, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x3d, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegDI/scale=2/offset=-1", baseReg: RegBP, indexReg: RegDI, scale: 2, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x7d, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegDI/scale=4/offset=-1", baseReg: RegBP, indexReg: RegDI, scale: 4, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xbd, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegDI/scale=8/offset=-1", baseReg: RegBP, indexReg: RegDI, scale: 8, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xfd, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegR8/scale=1/offset=-1", baseReg: RegBP, indexReg: RegR8, scale: 1, offset: -1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x5, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegR8/scale=2/offset=-1", baseReg: RegBP, indexReg: RegR8, scale: 2, offset: -1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x45, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegR8/scale=4/offset=-1", baseReg: RegBP, indexReg: RegR8, scale: 4, offset: -1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x85, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegR8/scale=8/offset=-1", baseReg: RegBP, indexReg: RegR8, scale: 8, offset: -1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0xc5, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegR14/scale=1/offset=-1", baseReg: RegBP, indexReg: RegR14, scale: 1, offset: -1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x35, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegR14/scale=2/offset=-1", baseReg: RegBP, indexReg: RegR14, scale: 2, offset: -1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x75, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegR14/scale=4/offset=-1", baseReg: RegBP, indexReg: RegR14, scale: 4, offset: -1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0xb5, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegR14/scale=8/offset=-1", baseReg: RegBP, indexReg: RegR14, scale: 8, offset: -1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0xf5, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=Nil/scale=1/offset=-1", baseReg: RegBP, indexReg: asm.NilRegister, scale: 1, offset: -1, expRex: 0x0, expModRM: 0x45, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=Nil/scale=2/offset=-1", baseReg: RegBP, indexReg: asm.NilRegister, scale: 2, offset: -1, expRex: 0x0, expModRM: 0x45, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=Nil/scale=4/offset=-1", baseReg: RegBP, indexReg: asm.NilRegister, scale: 4, offset: -1, expRex: 0x0, expModRM: 0x45, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=Nil/scale=8/offset=-1", baseReg: RegBP, indexReg: asm.NilRegister, scale: 8, offset: -1, expRex: 0x0, expModRM: 0x45, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegBP/indexReg=RegAX/scale=1/offset=2147483647", baseReg: RegBP, indexReg: RegAX, scale: 1, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x5, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegAX/scale=2/offset=2147483647", baseReg: RegBP, indexReg: RegAX, scale: 2, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x45, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegAX/scale=4/offset=2147483647", baseReg: RegBP, indexReg: RegAX, scale: 4, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x85, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegAX/scale=8/offset=2147483647", baseReg: RegBP, indexReg: RegAX, scale: 8, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xc5, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegBX/scale=1/offset=2147483647", baseReg: RegBP, indexReg: RegBX, scale: 1, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x1d, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegBX/scale=2/offset=2147483647", baseReg: RegBP, indexReg: RegBX, scale: 2, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x5d, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegBX/scale=4/offset=2147483647", baseReg: RegBP, indexReg: RegBX, scale: 4, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x9d, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegBX/scale=8/offset=2147483647", baseReg: RegBP, indexReg: RegBX, scale: 8, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xdd, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegBP/scale=1/offset=2147483647", baseReg: RegBP, indexReg: RegBP, scale: 1, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x2d, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegBP/scale=2/offset=2147483647", baseReg: RegBP, indexReg: RegBP, scale: 2, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x6d, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegBP/scale=4/offset=2147483647", baseReg: RegBP, indexReg: RegBP, scale: 4, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xad, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegBP/scale=8/offset=2147483647", baseReg: RegBP, indexReg: RegBP, scale: 8, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xed, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegSI/scale=1/offset=2147483647", baseReg: RegBP, indexReg: RegSI, scale: 1, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x35, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegSI/scale=2/offset=2147483647", baseReg: RegBP, indexReg: RegSI, scale: 2, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x75, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegSI/scale=4/offset=2147483647", baseReg: RegBP, indexReg: RegSI, scale: 4, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xb5, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegSI/scale=8/offset=2147483647", baseReg: RegBP, indexReg: RegSI, scale: 8, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xf5, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegDI/scale=1/offset=2147483647", baseReg: RegBP, indexReg: RegDI, scale: 1, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x3d, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegDI/scale=2/offset=2147483647", baseReg: RegBP, indexReg: RegDI, scale: 2, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x7d, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegDI/scale=4/offset=2147483647", baseReg: RegBP, indexReg: RegDI, scale: 4, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xbd, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegDI/scale=8/offset=2147483647", baseReg: RegBP, indexReg: RegDI, scale: 8, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xfd, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegR8/scale=1/offset=2147483647", baseReg: RegBP, indexReg: RegR8, scale: 1, offset: 2147483647, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x5, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegR8/scale=2/offset=2147483647", baseReg: RegBP, indexReg: RegR8, scale: 2, offset: 2147483647, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x45, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegR8/scale=4/offset=2147483647", baseReg: RegBP, indexReg: RegR8, scale: 4, offset: 2147483647, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x85, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegR8/scale=8/offset=2147483647", baseReg: RegBP, indexReg: RegR8, scale: 8, offset: 2147483647, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0xc5, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegR14/scale=1/offset=2147483647", baseReg: RegBP, indexReg: RegR14, scale: 1, offset: 2147483647, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x35, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegR14/scale=2/offset=2147483647", baseReg: RegBP, indexReg: RegR14, scale: 2, offset: 2147483647, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x75, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegR14/scale=4/offset=2147483647", baseReg: RegBP, indexReg: RegR14, scale: 4, offset: 2147483647, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0xb5, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegR14/scale=8/offset=2147483647", baseReg: RegBP, indexReg: RegR14, scale: 8, offset: 2147483647, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0xf5, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=Nil/scale=1/offset=2147483647", baseReg: RegBP, indexReg: asm.NilRegister, scale: 1, offset: 2147483647, expRex: 0x0, expModRM: 0x85, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=Nil/scale=2/offset=2147483647", baseReg: RegBP, indexReg: asm.NilRegister, scale: 2, offset: 2147483647, expRex: 0x0, expModRM: 0x85, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=Nil/scale=4/offset=2147483647", baseReg: RegBP, indexReg: asm.NilRegister, scale: 4, offset: 2147483647, expRex: 0x0, expModRM: 0x85, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=Nil/scale=8/offset=2147483647", baseReg: RegBP, indexReg: asm.NilRegister, scale: 8, offset: 2147483647, expRex: 0x0, expModRM: 0x85, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegAX/scale=1/offset=-2147483648", baseReg: RegBP, indexReg: RegAX, scale: 1, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x5, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegAX/scale=2/offset=-2147483648", baseReg: RegBP, indexReg: RegAX, scale: 2, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x45, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegAX/scale=4/offset=-2147483648", baseReg: RegBP, indexReg: RegAX, scale: 4, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x85, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegAX/scale=8/offset=-2147483648", baseReg: RegBP, indexReg: RegAX, scale: 8, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xc5, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegBX/scale=1/offset=-2147483648", baseReg: RegBP, indexReg: RegBX, scale: 1, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x1d, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegBX/scale=2/offset=-2147483648", baseReg: RegBP, indexReg: RegBX, scale: 2, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x5d, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegBX/scale=4/offset=-2147483648", baseReg: RegBP, indexReg: RegBX, scale: 4, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x9d, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegBX/scale=8/offset=-2147483648", baseReg: RegBP, indexReg: RegBX, scale: 8, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xdd, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegBP/scale=1/offset=-2147483648", baseReg: RegBP, indexReg: RegBP, scale: 1, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x2d, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegBP/scale=2/offset=-2147483648", baseReg: RegBP, indexReg: RegBP, scale: 2, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x6d, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegBP/scale=4/offset=-2147483648", baseReg: RegBP, indexReg: RegBP, scale: 4, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xad, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegBP/scale=8/offset=-2147483648", baseReg: RegBP, indexReg: RegBP, scale: 8, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xed, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegSI/scale=1/offset=-2147483648", baseReg: RegBP, indexReg: RegSI, scale: 1, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x35, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegSI/scale=2/offset=-2147483648", baseReg: RegBP, indexReg: RegSI, scale: 2, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x75, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegSI/scale=4/offset=-2147483648", baseReg: RegBP, indexReg: RegSI, scale: 4, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xb5, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegSI/scale=8/offset=-2147483648", baseReg: RegBP, indexReg: RegSI, scale: 8, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xf5, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegDI/scale=1/offset=-2147483648", baseReg: RegBP, indexReg: RegDI, scale: 1, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x3d, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegDI/scale=2/offset=-2147483648", baseReg: RegBP, indexReg: RegDI, scale: 2, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x7d, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegDI/scale=4/offset=-2147483648", baseReg: RegBP, indexReg: RegDI, scale: 4, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xbd, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegDI/scale=8/offset=-2147483648", baseReg: RegBP, indexReg: RegDI, scale: 8, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xfd, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegR8/scale=1/offset=-2147483648", baseReg: RegBP, indexReg: RegR8, scale: 1, offset: -2147483648, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x5, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegR8/scale=2/offset=-2147483648", baseReg: RegBP, indexReg: RegR8, scale: 2, offset: -2147483648, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x45, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegR8/scale=4/offset=-2147483648", baseReg: RegBP, indexReg: RegR8, scale: 4, offset: -2147483648, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x85, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegR8/scale=8/offset=-2147483648", baseReg: RegBP, indexReg: RegR8, scale: 8, offset: -2147483648, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0xc5, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegR14/scale=1/offset=-2147483648", baseReg: RegBP, indexReg: RegR14, scale: 1, offset: -2147483648, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x35, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegR14/scale=2/offset=-2147483648", baseReg: RegBP, indexReg: RegR14, scale: 2, offset: -2147483648, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x75, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegR14/scale=4/offset=-2147483648", baseReg: RegBP, indexReg: RegR14, scale: 4, offset: -2147483648, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0xb5, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=RegR14/scale=8/offset=-2147483648", baseReg: RegBP, indexReg: RegR14, scale: 8, offset: -2147483648, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0xf5, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=Nil/scale=1/offset=-2147483648", baseReg: RegBP, indexReg: asm.NilRegister, scale: 1, offset: -2147483648, expRex: 0x0, expModRM: 0x85, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=Nil/scale=2/offset=-2147483648", baseReg: RegBP, indexReg: asm.NilRegister, scale: 2, offset: -2147483648, expRex: 0x0, expModRM: 0x85, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=Nil/scale=4/offset=-2147483648", baseReg: RegBP, indexReg: asm.NilRegister, scale: 4, offset: -2147483648, expRex: 0x0, expModRM: 0x85, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegBP/indexReg=Nil/scale=8/offset=-2147483648", baseReg: RegBP, indexReg: asm.NilRegister, scale: 8, offset: -2147483648, expRex: 0x0, expModRM: 0x85, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegAX/scale=1/offset=0", baseReg: RegSI, indexReg: RegAX, scale: 1, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x6, displacementWidth: 0}, - {name: "baseReg=RegSI/indexReg=RegAX/scale=2/offset=0", baseReg: RegSI, indexReg: RegAX, scale: 2, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x46, displacementWidth: 0}, - {name: "baseReg=RegSI/indexReg=RegAX/scale=4/offset=0", baseReg: RegSI, indexReg: RegAX, scale: 4, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x86, displacementWidth: 0}, - {name: "baseReg=RegSI/indexReg=RegAX/scale=8/offset=0", baseReg: RegSI, indexReg: RegAX, scale: 8, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0xc6, displacementWidth: 0}, - {name: "baseReg=RegSI/indexReg=RegBX/scale=1/offset=0", baseReg: RegSI, indexReg: RegBX, scale: 1, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x1e, displacementWidth: 0}, - {name: "baseReg=RegSI/indexReg=RegBX/scale=2/offset=0", baseReg: RegSI, indexReg: RegBX, scale: 2, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x5e, displacementWidth: 0}, - {name: "baseReg=RegSI/indexReg=RegBX/scale=4/offset=0", baseReg: RegSI, indexReg: RegBX, scale: 4, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x9e, displacementWidth: 0}, - {name: "baseReg=RegSI/indexReg=RegBX/scale=8/offset=0", baseReg: RegSI, indexReg: RegBX, scale: 8, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0xde, displacementWidth: 0}, - {name: "baseReg=RegSI/indexReg=RegBP/scale=1/offset=0", baseReg: RegSI, indexReg: RegBP, scale: 1, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x2e, displacementWidth: 0}, - {name: "baseReg=RegSI/indexReg=RegBP/scale=2/offset=0", baseReg: RegSI, indexReg: RegBP, scale: 2, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x6e, displacementWidth: 0}, - {name: "baseReg=RegSI/indexReg=RegBP/scale=4/offset=0", baseReg: RegSI, indexReg: RegBP, scale: 4, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0xae, displacementWidth: 0}, - {name: "baseReg=RegSI/indexReg=RegBP/scale=8/offset=0", baseReg: RegSI, indexReg: RegBP, scale: 8, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0xee, displacementWidth: 0}, - {name: "baseReg=RegSI/indexReg=RegSI/scale=1/offset=0", baseReg: RegSI, indexReg: RegSI, scale: 1, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x36, displacementWidth: 0}, - {name: "baseReg=RegSI/indexReg=RegSI/scale=2/offset=0", baseReg: RegSI, indexReg: RegSI, scale: 2, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x76, displacementWidth: 0}, - {name: "baseReg=RegSI/indexReg=RegSI/scale=4/offset=0", baseReg: RegSI, indexReg: RegSI, scale: 4, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0xb6, displacementWidth: 0}, - {name: "baseReg=RegSI/indexReg=RegSI/scale=8/offset=0", baseReg: RegSI, indexReg: RegSI, scale: 8, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0xf6, displacementWidth: 0}, - {name: "baseReg=RegSI/indexReg=RegDI/scale=1/offset=0", baseReg: RegSI, indexReg: RegDI, scale: 1, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x3e, displacementWidth: 0}, - {name: "baseReg=RegSI/indexReg=RegDI/scale=2/offset=0", baseReg: RegSI, indexReg: RegDI, scale: 2, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x7e, displacementWidth: 0}, - {name: "baseReg=RegSI/indexReg=RegDI/scale=4/offset=0", baseReg: RegSI, indexReg: RegDI, scale: 4, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0xbe, displacementWidth: 0}, - {name: "baseReg=RegSI/indexReg=RegDI/scale=8/offset=0", baseReg: RegSI, indexReg: RegDI, scale: 8, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0xfe, displacementWidth: 0}, - {name: "baseReg=RegSI/indexReg=RegR8/scale=1/offset=0", baseReg: RegSI, indexReg: RegR8, scale: 1, offset: 0, expRex: 0x42, expModRM: 0x4, needSBI: true, expSBI: 0x6, displacementWidth: 0}, - {name: "baseReg=RegSI/indexReg=RegR8/scale=2/offset=0", baseReg: RegSI, indexReg: RegR8, scale: 2, offset: 0, expRex: 0x42, expModRM: 0x4, needSBI: true, expSBI: 0x46, displacementWidth: 0}, - {name: "baseReg=RegSI/indexReg=RegR8/scale=4/offset=0", baseReg: RegSI, indexReg: RegR8, scale: 4, offset: 0, expRex: 0x42, expModRM: 0x4, needSBI: true, expSBI: 0x86, displacementWidth: 0}, - {name: "baseReg=RegSI/indexReg=RegR8/scale=8/offset=0", baseReg: RegSI, indexReg: RegR8, scale: 8, offset: 0, expRex: 0x42, expModRM: 0x4, needSBI: true, expSBI: 0xc6, displacementWidth: 0}, - {name: "baseReg=RegSI/indexReg=RegR14/scale=1/offset=0", baseReg: RegSI, indexReg: RegR14, scale: 1, offset: 0, expRex: 0x42, expModRM: 0x4, needSBI: true, expSBI: 0x36, displacementWidth: 0}, - {name: "baseReg=RegSI/indexReg=RegR14/scale=2/offset=0", baseReg: RegSI, indexReg: RegR14, scale: 2, offset: 0, expRex: 0x42, expModRM: 0x4, needSBI: true, expSBI: 0x76, displacementWidth: 0}, - {name: "baseReg=RegSI/indexReg=RegR14/scale=4/offset=0", baseReg: RegSI, indexReg: RegR14, scale: 4, offset: 0, expRex: 0x42, expModRM: 0x4, needSBI: true, expSBI: 0xb6, displacementWidth: 0}, - {name: "baseReg=RegSI/indexReg=RegR14/scale=8/offset=0", baseReg: RegSI, indexReg: RegR14, scale: 8, offset: 0, expRex: 0x42, expModRM: 0x4, needSBI: true, expSBI: 0xf6, displacementWidth: 0}, - {name: "baseReg=RegSI/indexReg=Nil/scale=1/offset=0", baseReg: RegSI, indexReg: asm.NilRegister, scale: 1, offset: 0, expRex: 0x0, expModRM: 0x6, needSBI: false, displacementWidth: 0}, - {name: "baseReg=RegSI/indexReg=Nil/scale=2/offset=0", baseReg: RegSI, indexReg: asm.NilRegister, scale: 2, offset: 0, expRex: 0x0, expModRM: 0x6, needSBI: false, displacementWidth: 0}, - {name: "baseReg=RegSI/indexReg=Nil/scale=4/offset=0", baseReg: RegSI, indexReg: asm.NilRegister, scale: 4, offset: 0, expRex: 0x0, expModRM: 0x6, needSBI: false, displacementWidth: 0}, - {name: "baseReg=RegSI/indexReg=Nil/scale=8/offset=0", baseReg: RegSI, indexReg: asm.NilRegister, scale: 8, offset: 0, expRex: 0x0, expModRM: 0x6, needSBI: false, displacementWidth: 0}, - {name: "baseReg=RegSI/indexReg=RegAX/scale=1/offset=1", baseReg: RegSI, indexReg: RegAX, scale: 1, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x6, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegAX/scale=2/offset=1", baseReg: RegSI, indexReg: RegAX, scale: 2, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x46, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegAX/scale=4/offset=1", baseReg: RegSI, indexReg: RegAX, scale: 4, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x86, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegAX/scale=8/offset=1", baseReg: RegSI, indexReg: RegAX, scale: 8, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xc6, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegBX/scale=1/offset=1", baseReg: RegSI, indexReg: RegBX, scale: 1, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x1e, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegBX/scale=2/offset=1", baseReg: RegSI, indexReg: RegBX, scale: 2, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x5e, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegBX/scale=4/offset=1", baseReg: RegSI, indexReg: RegBX, scale: 4, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x9e, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegBX/scale=8/offset=1", baseReg: RegSI, indexReg: RegBX, scale: 8, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xde, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegBP/scale=1/offset=1", baseReg: RegSI, indexReg: RegBP, scale: 1, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x2e, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegBP/scale=2/offset=1", baseReg: RegSI, indexReg: RegBP, scale: 2, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x6e, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegBP/scale=4/offset=1", baseReg: RegSI, indexReg: RegBP, scale: 4, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xae, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegBP/scale=8/offset=1", baseReg: RegSI, indexReg: RegBP, scale: 8, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xee, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegSI/scale=1/offset=1", baseReg: RegSI, indexReg: RegSI, scale: 1, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x36, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegSI/scale=2/offset=1", baseReg: RegSI, indexReg: RegSI, scale: 2, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x76, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegSI/scale=4/offset=1", baseReg: RegSI, indexReg: RegSI, scale: 4, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xb6, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegSI/scale=8/offset=1", baseReg: RegSI, indexReg: RegSI, scale: 8, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xf6, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegDI/scale=1/offset=1", baseReg: RegSI, indexReg: RegDI, scale: 1, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x3e, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegDI/scale=2/offset=1", baseReg: RegSI, indexReg: RegDI, scale: 2, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x7e, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegDI/scale=4/offset=1", baseReg: RegSI, indexReg: RegDI, scale: 4, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xbe, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegDI/scale=8/offset=1", baseReg: RegSI, indexReg: RegDI, scale: 8, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xfe, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegR8/scale=1/offset=1", baseReg: RegSI, indexReg: RegR8, scale: 1, offset: 1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x6, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegR8/scale=2/offset=1", baseReg: RegSI, indexReg: RegR8, scale: 2, offset: 1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x46, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegR8/scale=4/offset=1", baseReg: RegSI, indexReg: RegR8, scale: 4, offset: 1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x86, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegR8/scale=8/offset=1", baseReg: RegSI, indexReg: RegR8, scale: 8, offset: 1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0xc6, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegR14/scale=1/offset=1", baseReg: RegSI, indexReg: RegR14, scale: 1, offset: 1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x36, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegR14/scale=2/offset=1", baseReg: RegSI, indexReg: RegR14, scale: 2, offset: 1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x76, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegR14/scale=4/offset=1", baseReg: RegSI, indexReg: RegR14, scale: 4, offset: 1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0xb6, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegR14/scale=8/offset=1", baseReg: RegSI, indexReg: RegR14, scale: 8, offset: 1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0xf6, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=Nil/scale=1/offset=1", baseReg: RegSI, indexReg: asm.NilRegister, scale: 1, offset: 1, expRex: 0x0, expModRM: 0x46, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=Nil/scale=2/offset=1", baseReg: RegSI, indexReg: asm.NilRegister, scale: 2, offset: 1, expRex: 0x0, expModRM: 0x46, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=Nil/scale=4/offset=1", baseReg: RegSI, indexReg: asm.NilRegister, scale: 4, offset: 1, expRex: 0x0, expModRM: 0x46, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=Nil/scale=8/offset=1", baseReg: RegSI, indexReg: asm.NilRegister, scale: 8, offset: 1, expRex: 0x0, expModRM: 0x46, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegAX/scale=1/offset=-1", baseReg: RegSI, indexReg: RegAX, scale: 1, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x6, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegAX/scale=2/offset=-1", baseReg: RegSI, indexReg: RegAX, scale: 2, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x46, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegAX/scale=4/offset=-1", baseReg: RegSI, indexReg: RegAX, scale: 4, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x86, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegAX/scale=8/offset=-1", baseReg: RegSI, indexReg: RegAX, scale: 8, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xc6, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegBX/scale=1/offset=-1", baseReg: RegSI, indexReg: RegBX, scale: 1, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x1e, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegBX/scale=2/offset=-1", baseReg: RegSI, indexReg: RegBX, scale: 2, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x5e, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegBX/scale=4/offset=-1", baseReg: RegSI, indexReg: RegBX, scale: 4, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x9e, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegBX/scale=8/offset=-1", baseReg: RegSI, indexReg: RegBX, scale: 8, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xde, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegBP/scale=1/offset=-1", baseReg: RegSI, indexReg: RegBP, scale: 1, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x2e, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegBP/scale=2/offset=-1", baseReg: RegSI, indexReg: RegBP, scale: 2, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x6e, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegBP/scale=4/offset=-1", baseReg: RegSI, indexReg: RegBP, scale: 4, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xae, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegBP/scale=8/offset=-1", baseReg: RegSI, indexReg: RegBP, scale: 8, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xee, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegSI/scale=1/offset=-1", baseReg: RegSI, indexReg: RegSI, scale: 1, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x36, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegSI/scale=2/offset=-1", baseReg: RegSI, indexReg: RegSI, scale: 2, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x76, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegSI/scale=4/offset=-1", baseReg: RegSI, indexReg: RegSI, scale: 4, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xb6, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegSI/scale=8/offset=-1", baseReg: RegSI, indexReg: RegSI, scale: 8, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xf6, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegDI/scale=1/offset=-1", baseReg: RegSI, indexReg: RegDI, scale: 1, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x3e, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegDI/scale=2/offset=-1", baseReg: RegSI, indexReg: RegDI, scale: 2, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x7e, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegDI/scale=4/offset=-1", baseReg: RegSI, indexReg: RegDI, scale: 4, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xbe, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegDI/scale=8/offset=-1", baseReg: RegSI, indexReg: RegDI, scale: 8, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xfe, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegR8/scale=1/offset=-1", baseReg: RegSI, indexReg: RegR8, scale: 1, offset: -1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x6, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegR8/scale=2/offset=-1", baseReg: RegSI, indexReg: RegR8, scale: 2, offset: -1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x46, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegR8/scale=4/offset=-1", baseReg: RegSI, indexReg: RegR8, scale: 4, offset: -1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x86, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegR8/scale=8/offset=-1", baseReg: RegSI, indexReg: RegR8, scale: 8, offset: -1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0xc6, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegR14/scale=1/offset=-1", baseReg: RegSI, indexReg: RegR14, scale: 1, offset: -1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x36, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegR14/scale=2/offset=-1", baseReg: RegSI, indexReg: RegR14, scale: 2, offset: -1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x76, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegR14/scale=4/offset=-1", baseReg: RegSI, indexReg: RegR14, scale: 4, offset: -1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0xb6, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegR14/scale=8/offset=-1", baseReg: RegSI, indexReg: RegR14, scale: 8, offset: -1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0xf6, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=Nil/scale=1/offset=-1", baseReg: RegSI, indexReg: asm.NilRegister, scale: 1, offset: -1, expRex: 0x0, expModRM: 0x46, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=Nil/scale=2/offset=-1", baseReg: RegSI, indexReg: asm.NilRegister, scale: 2, offset: -1, expRex: 0x0, expModRM: 0x46, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=Nil/scale=4/offset=-1", baseReg: RegSI, indexReg: asm.NilRegister, scale: 4, offset: -1, expRex: 0x0, expModRM: 0x46, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=Nil/scale=8/offset=-1", baseReg: RegSI, indexReg: asm.NilRegister, scale: 8, offset: -1, expRex: 0x0, expModRM: 0x46, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegSI/indexReg=RegAX/scale=1/offset=2147483647", baseReg: RegSI, indexReg: RegAX, scale: 1, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x6, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegAX/scale=2/offset=2147483647", baseReg: RegSI, indexReg: RegAX, scale: 2, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x46, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegAX/scale=4/offset=2147483647", baseReg: RegSI, indexReg: RegAX, scale: 4, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x86, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegAX/scale=8/offset=2147483647", baseReg: RegSI, indexReg: RegAX, scale: 8, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xc6, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegBX/scale=1/offset=2147483647", baseReg: RegSI, indexReg: RegBX, scale: 1, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x1e, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegBX/scale=2/offset=2147483647", baseReg: RegSI, indexReg: RegBX, scale: 2, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x5e, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegBX/scale=4/offset=2147483647", baseReg: RegSI, indexReg: RegBX, scale: 4, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x9e, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegBX/scale=8/offset=2147483647", baseReg: RegSI, indexReg: RegBX, scale: 8, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xde, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegBP/scale=1/offset=2147483647", baseReg: RegSI, indexReg: RegBP, scale: 1, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x2e, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegBP/scale=2/offset=2147483647", baseReg: RegSI, indexReg: RegBP, scale: 2, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x6e, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegBP/scale=4/offset=2147483647", baseReg: RegSI, indexReg: RegBP, scale: 4, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xae, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegBP/scale=8/offset=2147483647", baseReg: RegSI, indexReg: RegBP, scale: 8, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xee, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegSI/scale=1/offset=2147483647", baseReg: RegSI, indexReg: RegSI, scale: 1, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x36, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegSI/scale=2/offset=2147483647", baseReg: RegSI, indexReg: RegSI, scale: 2, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x76, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegSI/scale=4/offset=2147483647", baseReg: RegSI, indexReg: RegSI, scale: 4, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xb6, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegSI/scale=8/offset=2147483647", baseReg: RegSI, indexReg: RegSI, scale: 8, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xf6, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegDI/scale=1/offset=2147483647", baseReg: RegSI, indexReg: RegDI, scale: 1, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x3e, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegDI/scale=2/offset=2147483647", baseReg: RegSI, indexReg: RegDI, scale: 2, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x7e, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegDI/scale=4/offset=2147483647", baseReg: RegSI, indexReg: RegDI, scale: 4, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xbe, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegDI/scale=8/offset=2147483647", baseReg: RegSI, indexReg: RegDI, scale: 8, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xfe, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegR8/scale=1/offset=2147483647", baseReg: RegSI, indexReg: RegR8, scale: 1, offset: 2147483647, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x6, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegR8/scale=2/offset=2147483647", baseReg: RegSI, indexReg: RegR8, scale: 2, offset: 2147483647, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x46, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegR8/scale=4/offset=2147483647", baseReg: RegSI, indexReg: RegR8, scale: 4, offset: 2147483647, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x86, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegR8/scale=8/offset=2147483647", baseReg: RegSI, indexReg: RegR8, scale: 8, offset: 2147483647, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0xc6, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegR14/scale=1/offset=2147483647", baseReg: RegSI, indexReg: RegR14, scale: 1, offset: 2147483647, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x36, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegR14/scale=2/offset=2147483647", baseReg: RegSI, indexReg: RegR14, scale: 2, offset: 2147483647, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x76, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegR14/scale=4/offset=2147483647", baseReg: RegSI, indexReg: RegR14, scale: 4, offset: 2147483647, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0xb6, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegR14/scale=8/offset=2147483647", baseReg: RegSI, indexReg: RegR14, scale: 8, offset: 2147483647, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0xf6, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=Nil/scale=1/offset=2147483647", baseReg: RegSI, indexReg: asm.NilRegister, scale: 1, offset: 2147483647, expRex: 0x0, expModRM: 0x86, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=Nil/scale=2/offset=2147483647", baseReg: RegSI, indexReg: asm.NilRegister, scale: 2, offset: 2147483647, expRex: 0x0, expModRM: 0x86, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=Nil/scale=4/offset=2147483647", baseReg: RegSI, indexReg: asm.NilRegister, scale: 4, offset: 2147483647, expRex: 0x0, expModRM: 0x86, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=Nil/scale=8/offset=2147483647", baseReg: RegSI, indexReg: asm.NilRegister, scale: 8, offset: 2147483647, expRex: 0x0, expModRM: 0x86, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegAX/scale=1/offset=-2147483648", baseReg: RegSI, indexReg: RegAX, scale: 1, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x6, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegAX/scale=2/offset=-2147483648", baseReg: RegSI, indexReg: RegAX, scale: 2, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x46, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegAX/scale=4/offset=-2147483648", baseReg: RegSI, indexReg: RegAX, scale: 4, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x86, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegAX/scale=8/offset=-2147483648", baseReg: RegSI, indexReg: RegAX, scale: 8, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xc6, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegBX/scale=1/offset=-2147483648", baseReg: RegSI, indexReg: RegBX, scale: 1, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x1e, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegBX/scale=2/offset=-2147483648", baseReg: RegSI, indexReg: RegBX, scale: 2, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x5e, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegBX/scale=4/offset=-2147483648", baseReg: RegSI, indexReg: RegBX, scale: 4, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x9e, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegBX/scale=8/offset=-2147483648", baseReg: RegSI, indexReg: RegBX, scale: 8, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xde, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegBP/scale=1/offset=-2147483648", baseReg: RegSI, indexReg: RegBP, scale: 1, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x2e, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegBP/scale=2/offset=-2147483648", baseReg: RegSI, indexReg: RegBP, scale: 2, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x6e, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegBP/scale=4/offset=-2147483648", baseReg: RegSI, indexReg: RegBP, scale: 4, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xae, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegBP/scale=8/offset=-2147483648", baseReg: RegSI, indexReg: RegBP, scale: 8, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xee, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegSI/scale=1/offset=-2147483648", baseReg: RegSI, indexReg: RegSI, scale: 1, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x36, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegSI/scale=2/offset=-2147483648", baseReg: RegSI, indexReg: RegSI, scale: 2, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x76, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegSI/scale=4/offset=-2147483648", baseReg: RegSI, indexReg: RegSI, scale: 4, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xb6, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegSI/scale=8/offset=-2147483648", baseReg: RegSI, indexReg: RegSI, scale: 8, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xf6, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegDI/scale=1/offset=-2147483648", baseReg: RegSI, indexReg: RegDI, scale: 1, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x3e, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegDI/scale=2/offset=-2147483648", baseReg: RegSI, indexReg: RegDI, scale: 2, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x7e, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegDI/scale=4/offset=-2147483648", baseReg: RegSI, indexReg: RegDI, scale: 4, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xbe, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegDI/scale=8/offset=-2147483648", baseReg: RegSI, indexReg: RegDI, scale: 8, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xfe, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegR8/scale=1/offset=-2147483648", baseReg: RegSI, indexReg: RegR8, scale: 1, offset: -2147483648, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x6, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegR8/scale=2/offset=-2147483648", baseReg: RegSI, indexReg: RegR8, scale: 2, offset: -2147483648, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x46, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegR8/scale=4/offset=-2147483648", baseReg: RegSI, indexReg: RegR8, scale: 4, offset: -2147483648, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x86, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegR8/scale=8/offset=-2147483648", baseReg: RegSI, indexReg: RegR8, scale: 8, offset: -2147483648, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0xc6, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegR14/scale=1/offset=-2147483648", baseReg: RegSI, indexReg: RegR14, scale: 1, offset: -2147483648, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x36, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegR14/scale=2/offset=-2147483648", baseReg: RegSI, indexReg: RegR14, scale: 2, offset: -2147483648, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x76, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegR14/scale=4/offset=-2147483648", baseReg: RegSI, indexReg: RegR14, scale: 4, offset: -2147483648, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0xb6, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=RegR14/scale=8/offset=-2147483648", baseReg: RegSI, indexReg: RegR14, scale: 8, offset: -2147483648, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0xf6, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=Nil/scale=1/offset=-2147483648", baseReg: RegSI, indexReg: asm.NilRegister, scale: 1, offset: -2147483648, expRex: 0x0, expModRM: 0x86, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=Nil/scale=2/offset=-2147483648", baseReg: RegSI, indexReg: asm.NilRegister, scale: 2, offset: -2147483648, expRex: 0x0, expModRM: 0x86, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=Nil/scale=4/offset=-2147483648", baseReg: RegSI, indexReg: asm.NilRegister, scale: 4, offset: -2147483648, expRex: 0x0, expModRM: 0x86, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegSI/indexReg=Nil/scale=8/offset=-2147483648", baseReg: RegSI, indexReg: asm.NilRegister, scale: 8, offset: -2147483648, expRex: 0x0, expModRM: 0x86, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegAX/scale=1/offset=0", baseReg: RegDI, indexReg: RegAX, scale: 1, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x7, displacementWidth: 0}, - {name: "baseReg=RegDI/indexReg=RegAX/scale=2/offset=0", baseReg: RegDI, indexReg: RegAX, scale: 2, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x47, displacementWidth: 0}, - {name: "baseReg=RegDI/indexReg=RegAX/scale=4/offset=0", baseReg: RegDI, indexReg: RegAX, scale: 4, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x87, displacementWidth: 0}, - {name: "baseReg=RegDI/indexReg=RegAX/scale=8/offset=0", baseReg: RegDI, indexReg: RegAX, scale: 8, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0xc7, displacementWidth: 0}, - {name: "baseReg=RegDI/indexReg=RegBX/scale=1/offset=0", baseReg: RegDI, indexReg: RegBX, scale: 1, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x1f, displacementWidth: 0}, - {name: "baseReg=RegDI/indexReg=RegBX/scale=2/offset=0", baseReg: RegDI, indexReg: RegBX, scale: 2, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x5f, displacementWidth: 0}, - {name: "baseReg=RegDI/indexReg=RegBX/scale=4/offset=0", baseReg: RegDI, indexReg: RegBX, scale: 4, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x9f, displacementWidth: 0}, - {name: "baseReg=RegDI/indexReg=RegBX/scale=8/offset=0", baseReg: RegDI, indexReg: RegBX, scale: 8, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0xdf, displacementWidth: 0}, - {name: "baseReg=RegDI/indexReg=RegBP/scale=1/offset=0", baseReg: RegDI, indexReg: RegBP, scale: 1, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x2f, displacementWidth: 0}, - {name: "baseReg=RegDI/indexReg=RegBP/scale=2/offset=0", baseReg: RegDI, indexReg: RegBP, scale: 2, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x6f, displacementWidth: 0}, - {name: "baseReg=RegDI/indexReg=RegBP/scale=4/offset=0", baseReg: RegDI, indexReg: RegBP, scale: 4, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0xaf, displacementWidth: 0}, - {name: "baseReg=RegDI/indexReg=RegBP/scale=8/offset=0", baseReg: RegDI, indexReg: RegBP, scale: 8, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0xef, displacementWidth: 0}, - {name: "baseReg=RegDI/indexReg=RegSI/scale=1/offset=0", baseReg: RegDI, indexReg: RegSI, scale: 1, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x37, displacementWidth: 0}, - {name: "baseReg=RegDI/indexReg=RegSI/scale=2/offset=0", baseReg: RegDI, indexReg: RegSI, scale: 2, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x77, displacementWidth: 0}, - {name: "baseReg=RegDI/indexReg=RegSI/scale=4/offset=0", baseReg: RegDI, indexReg: RegSI, scale: 4, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0xb7, displacementWidth: 0}, - {name: "baseReg=RegDI/indexReg=RegSI/scale=8/offset=0", baseReg: RegDI, indexReg: RegSI, scale: 8, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0xf7, displacementWidth: 0}, - {name: "baseReg=RegDI/indexReg=RegDI/scale=1/offset=0", baseReg: RegDI, indexReg: RegDI, scale: 1, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x3f, displacementWidth: 0}, - {name: "baseReg=RegDI/indexReg=RegDI/scale=2/offset=0", baseReg: RegDI, indexReg: RegDI, scale: 2, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0x7f, displacementWidth: 0}, - {name: "baseReg=RegDI/indexReg=RegDI/scale=4/offset=0", baseReg: RegDI, indexReg: RegDI, scale: 4, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0xbf, displacementWidth: 0}, - {name: "baseReg=RegDI/indexReg=RegDI/scale=8/offset=0", baseReg: RegDI, indexReg: RegDI, scale: 8, offset: 0, expRex: 0x0, expModRM: 0x4, needSBI: true, expSBI: 0xff, displacementWidth: 0}, - {name: "baseReg=RegDI/indexReg=RegR8/scale=1/offset=0", baseReg: RegDI, indexReg: RegR8, scale: 1, offset: 0, expRex: 0x42, expModRM: 0x4, needSBI: true, expSBI: 0x7, displacementWidth: 0}, - {name: "baseReg=RegDI/indexReg=RegR8/scale=2/offset=0", baseReg: RegDI, indexReg: RegR8, scale: 2, offset: 0, expRex: 0x42, expModRM: 0x4, needSBI: true, expSBI: 0x47, displacementWidth: 0}, - {name: "baseReg=RegDI/indexReg=RegR8/scale=4/offset=0", baseReg: RegDI, indexReg: RegR8, scale: 4, offset: 0, expRex: 0x42, expModRM: 0x4, needSBI: true, expSBI: 0x87, displacementWidth: 0}, - {name: "baseReg=RegDI/indexReg=RegR8/scale=8/offset=0", baseReg: RegDI, indexReg: RegR8, scale: 8, offset: 0, expRex: 0x42, expModRM: 0x4, needSBI: true, expSBI: 0xc7, displacementWidth: 0}, - {name: "baseReg=RegDI/indexReg=RegR14/scale=1/offset=0", baseReg: RegDI, indexReg: RegR14, scale: 1, offset: 0, expRex: 0x42, expModRM: 0x4, needSBI: true, expSBI: 0x37, displacementWidth: 0}, - {name: "baseReg=RegDI/indexReg=RegR14/scale=2/offset=0", baseReg: RegDI, indexReg: RegR14, scale: 2, offset: 0, expRex: 0x42, expModRM: 0x4, needSBI: true, expSBI: 0x77, displacementWidth: 0}, - {name: "baseReg=RegDI/indexReg=RegR14/scale=4/offset=0", baseReg: RegDI, indexReg: RegR14, scale: 4, offset: 0, expRex: 0x42, expModRM: 0x4, needSBI: true, expSBI: 0xb7, displacementWidth: 0}, - {name: "baseReg=RegDI/indexReg=RegR14/scale=8/offset=0", baseReg: RegDI, indexReg: RegR14, scale: 8, offset: 0, expRex: 0x42, expModRM: 0x4, needSBI: true, expSBI: 0xf7, displacementWidth: 0}, - {name: "baseReg=RegDI/indexReg=Nil/scale=1/offset=0", baseReg: RegDI, indexReg: asm.NilRegister, scale: 1, offset: 0, expRex: 0x0, expModRM: 0x7, needSBI: false, displacementWidth: 0}, - {name: "baseReg=RegDI/indexReg=Nil/scale=2/offset=0", baseReg: RegDI, indexReg: asm.NilRegister, scale: 2, offset: 0, expRex: 0x0, expModRM: 0x7, needSBI: false, displacementWidth: 0}, - {name: "baseReg=RegDI/indexReg=Nil/scale=4/offset=0", baseReg: RegDI, indexReg: asm.NilRegister, scale: 4, offset: 0, expRex: 0x0, expModRM: 0x7, needSBI: false, displacementWidth: 0}, - {name: "baseReg=RegDI/indexReg=Nil/scale=8/offset=0", baseReg: RegDI, indexReg: asm.NilRegister, scale: 8, offset: 0, expRex: 0x0, expModRM: 0x7, needSBI: false, displacementWidth: 0}, - {name: "baseReg=RegDI/indexReg=RegAX/scale=1/offset=1", baseReg: RegDI, indexReg: RegAX, scale: 1, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x7, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegAX/scale=2/offset=1", baseReg: RegDI, indexReg: RegAX, scale: 2, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x47, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegAX/scale=4/offset=1", baseReg: RegDI, indexReg: RegAX, scale: 4, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x87, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegAX/scale=8/offset=1", baseReg: RegDI, indexReg: RegAX, scale: 8, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xc7, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegBX/scale=1/offset=1", baseReg: RegDI, indexReg: RegBX, scale: 1, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x1f, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegBX/scale=2/offset=1", baseReg: RegDI, indexReg: RegBX, scale: 2, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x5f, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegBX/scale=4/offset=1", baseReg: RegDI, indexReg: RegBX, scale: 4, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x9f, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegBX/scale=8/offset=1", baseReg: RegDI, indexReg: RegBX, scale: 8, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xdf, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegBP/scale=1/offset=1", baseReg: RegDI, indexReg: RegBP, scale: 1, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x2f, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegBP/scale=2/offset=1", baseReg: RegDI, indexReg: RegBP, scale: 2, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x6f, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegBP/scale=4/offset=1", baseReg: RegDI, indexReg: RegBP, scale: 4, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xaf, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegBP/scale=8/offset=1", baseReg: RegDI, indexReg: RegBP, scale: 8, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xef, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegSI/scale=1/offset=1", baseReg: RegDI, indexReg: RegSI, scale: 1, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x37, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegSI/scale=2/offset=1", baseReg: RegDI, indexReg: RegSI, scale: 2, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x77, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegSI/scale=4/offset=1", baseReg: RegDI, indexReg: RegSI, scale: 4, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xb7, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegSI/scale=8/offset=1", baseReg: RegDI, indexReg: RegSI, scale: 8, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xf7, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegDI/scale=1/offset=1", baseReg: RegDI, indexReg: RegDI, scale: 1, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x3f, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegDI/scale=2/offset=1", baseReg: RegDI, indexReg: RegDI, scale: 2, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x7f, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegDI/scale=4/offset=1", baseReg: RegDI, indexReg: RegDI, scale: 4, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xbf, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegDI/scale=8/offset=1", baseReg: RegDI, indexReg: RegDI, scale: 8, offset: 1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xff, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegR8/scale=1/offset=1", baseReg: RegDI, indexReg: RegR8, scale: 1, offset: 1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x7, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegR8/scale=2/offset=1", baseReg: RegDI, indexReg: RegR8, scale: 2, offset: 1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x47, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegR8/scale=4/offset=1", baseReg: RegDI, indexReg: RegR8, scale: 4, offset: 1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x87, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegR8/scale=8/offset=1", baseReg: RegDI, indexReg: RegR8, scale: 8, offset: 1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0xc7, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegR14/scale=1/offset=1", baseReg: RegDI, indexReg: RegR14, scale: 1, offset: 1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x37, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegR14/scale=2/offset=1", baseReg: RegDI, indexReg: RegR14, scale: 2, offset: 1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x77, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegR14/scale=4/offset=1", baseReg: RegDI, indexReg: RegR14, scale: 4, offset: 1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0xb7, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegR14/scale=8/offset=1", baseReg: RegDI, indexReg: RegR14, scale: 8, offset: 1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0xf7, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=Nil/scale=1/offset=1", baseReg: RegDI, indexReg: asm.NilRegister, scale: 1, offset: 1, expRex: 0x0, expModRM: 0x47, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=Nil/scale=2/offset=1", baseReg: RegDI, indexReg: asm.NilRegister, scale: 2, offset: 1, expRex: 0x0, expModRM: 0x47, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=Nil/scale=4/offset=1", baseReg: RegDI, indexReg: asm.NilRegister, scale: 4, offset: 1, expRex: 0x0, expModRM: 0x47, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=Nil/scale=8/offset=1", baseReg: RegDI, indexReg: asm.NilRegister, scale: 8, offset: 1, expRex: 0x0, expModRM: 0x47, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegAX/scale=1/offset=-1", baseReg: RegDI, indexReg: RegAX, scale: 1, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x7, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegAX/scale=2/offset=-1", baseReg: RegDI, indexReg: RegAX, scale: 2, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x47, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegAX/scale=4/offset=-1", baseReg: RegDI, indexReg: RegAX, scale: 4, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x87, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegAX/scale=8/offset=-1", baseReg: RegDI, indexReg: RegAX, scale: 8, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xc7, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegBX/scale=1/offset=-1", baseReg: RegDI, indexReg: RegBX, scale: 1, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x1f, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegBX/scale=2/offset=-1", baseReg: RegDI, indexReg: RegBX, scale: 2, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x5f, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegBX/scale=4/offset=-1", baseReg: RegDI, indexReg: RegBX, scale: 4, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x9f, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegBX/scale=8/offset=-1", baseReg: RegDI, indexReg: RegBX, scale: 8, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xdf, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegBP/scale=1/offset=-1", baseReg: RegDI, indexReg: RegBP, scale: 1, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x2f, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegBP/scale=2/offset=-1", baseReg: RegDI, indexReg: RegBP, scale: 2, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x6f, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegBP/scale=4/offset=-1", baseReg: RegDI, indexReg: RegBP, scale: 4, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xaf, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegBP/scale=8/offset=-1", baseReg: RegDI, indexReg: RegBP, scale: 8, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xef, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegSI/scale=1/offset=-1", baseReg: RegDI, indexReg: RegSI, scale: 1, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x37, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegSI/scale=2/offset=-1", baseReg: RegDI, indexReg: RegSI, scale: 2, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x77, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegSI/scale=4/offset=-1", baseReg: RegDI, indexReg: RegSI, scale: 4, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xb7, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegSI/scale=8/offset=-1", baseReg: RegDI, indexReg: RegSI, scale: 8, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xf7, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegDI/scale=1/offset=-1", baseReg: RegDI, indexReg: RegDI, scale: 1, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x3f, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegDI/scale=2/offset=-1", baseReg: RegDI, indexReg: RegDI, scale: 2, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0x7f, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegDI/scale=4/offset=-1", baseReg: RegDI, indexReg: RegDI, scale: 4, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xbf, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegDI/scale=8/offset=-1", baseReg: RegDI, indexReg: RegDI, scale: 8, offset: -1, expRex: 0x0, expModRM: 0x44, needSBI: true, expSBI: 0xff, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegR8/scale=1/offset=-1", baseReg: RegDI, indexReg: RegR8, scale: 1, offset: -1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x7, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegR8/scale=2/offset=-1", baseReg: RegDI, indexReg: RegR8, scale: 2, offset: -1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x47, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegR8/scale=4/offset=-1", baseReg: RegDI, indexReg: RegR8, scale: 4, offset: -1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x87, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegR8/scale=8/offset=-1", baseReg: RegDI, indexReg: RegR8, scale: 8, offset: -1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0xc7, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegR14/scale=1/offset=-1", baseReg: RegDI, indexReg: RegR14, scale: 1, offset: -1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x37, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegR14/scale=2/offset=-1", baseReg: RegDI, indexReg: RegR14, scale: 2, offset: -1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0x77, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegR14/scale=4/offset=-1", baseReg: RegDI, indexReg: RegR14, scale: 4, offset: -1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0xb7, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegR14/scale=8/offset=-1", baseReg: RegDI, indexReg: RegR14, scale: 8, offset: -1, expRex: 0x42, expModRM: 0x44, needSBI: true, expSBI: 0xf7, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=Nil/scale=1/offset=-1", baseReg: RegDI, indexReg: asm.NilRegister, scale: 1, offset: -1, expRex: 0x0, expModRM: 0x47, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=Nil/scale=2/offset=-1", baseReg: RegDI, indexReg: asm.NilRegister, scale: 2, offset: -1, expRex: 0x0, expModRM: 0x47, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=Nil/scale=4/offset=-1", baseReg: RegDI, indexReg: asm.NilRegister, scale: 4, offset: -1, expRex: 0x0, expModRM: 0x47, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=Nil/scale=8/offset=-1", baseReg: RegDI, indexReg: asm.NilRegister, scale: 8, offset: -1, expRex: 0x0, expModRM: 0x47, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegDI/indexReg=RegAX/scale=1/offset=2147483647", baseReg: RegDI, indexReg: RegAX, scale: 1, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x7, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegAX/scale=2/offset=2147483647", baseReg: RegDI, indexReg: RegAX, scale: 2, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x47, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegAX/scale=4/offset=2147483647", baseReg: RegDI, indexReg: RegAX, scale: 4, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x87, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegAX/scale=8/offset=2147483647", baseReg: RegDI, indexReg: RegAX, scale: 8, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xc7, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegBX/scale=1/offset=2147483647", baseReg: RegDI, indexReg: RegBX, scale: 1, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x1f, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegBX/scale=2/offset=2147483647", baseReg: RegDI, indexReg: RegBX, scale: 2, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x5f, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegBX/scale=4/offset=2147483647", baseReg: RegDI, indexReg: RegBX, scale: 4, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x9f, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegBX/scale=8/offset=2147483647", baseReg: RegDI, indexReg: RegBX, scale: 8, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xdf, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegBP/scale=1/offset=2147483647", baseReg: RegDI, indexReg: RegBP, scale: 1, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x2f, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegBP/scale=2/offset=2147483647", baseReg: RegDI, indexReg: RegBP, scale: 2, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x6f, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegBP/scale=4/offset=2147483647", baseReg: RegDI, indexReg: RegBP, scale: 4, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xaf, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegBP/scale=8/offset=2147483647", baseReg: RegDI, indexReg: RegBP, scale: 8, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xef, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegSI/scale=1/offset=2147483647", baseReg: RegDI, indexReg: RegSI, scale: 1, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x37, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegSI/scale=2/offset=2147483647", baseReg: RegDI, indexReg: RegSI, scale: 2, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x77, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegSI/scale=4/offset=2147483647", baseReg: RegDI, indexReg: RegSI, scale: 4, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xb7, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegSI/scale=8/offset=2147483647", baseReg: RegDI, indexReg: RegSI, scale: 8, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xf7, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegDI/scale=1/offset=2147483647", baseReg: RegDI, indexReg: RegDI, scale: 1, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x3f, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegDI/scale=2/offset=2147483647", baseReg: RegDI, indexReg: RegDI, scale: 2, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x7f, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegDI/scale=4/offset=2147483647", baseReg: RegDI, indexReg: RegDI, scale: 4, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xbf, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegDI/scale=8/offset=2147483647", baseReg: RegDI, indexReg: RegDI, scale: 8, offset: 2147483647, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xff, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegR8/scale=1/offset=2147483647", baseReg: RegDI, indexReg: RegR8, scale: 1, offset: 2147483647, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x7, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegR8/scale=2/offset=2147483647", baseReg: RegDI, indexReg: RegR8, scale: 2, offset: 2147483647, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x47, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegR8/scale=4/offset=2147483647", baseReg: RegDI, indexReg: RegR8, scale: 4, offset: 2147483647, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x87, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegR8/scale=8/offset=2147483647", baseReg: RegDI, indexReg: RegR8, scale: 8, offset: 2147483647, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0xc7, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegR14/scale=1/offset=2147483647", baseReg: RegDI, indexReg: RegR14, scale: 1, offset: 2147483647, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x37, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegR14/scale=2/offset=2147483647", baseReg: RegDI, indexReg: RegR14, scale: 2, offset: 2147483647, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x77, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegR14/scale=4/offset=2147483647", baseReg: RegDI, indexReg: RegR14, scale: 4, offset: 2147483647, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0xb7, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegR14/scale=8/offset=2147483647", baseReg: RegDI, indexReg: RegR14, scale: 8, offset: 2147483647, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0xf7, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=Nil/scale=1/offset=2147483647", baseReg: RegDI, indexReg: asm.NilRegister, scale: 1, offset: 2147483647, expRex: 0x0, expModRM: 0x87, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=Nil/scale=2/offset=2147483647", baseReg: RegDI, indexReg: asm.NilRegister, scale: 2, offset: 2147483647, expRex: 0x0, expModRM: 0x87, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=Nil/scale=4/offset=2147483647", baseReg: RegDI, indexReg: asm.NilRegister, scale: 4, offset: 2147483647, expRex: 0x0, expModRM: 0x87, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=Nil/scale=8/offset=2147483647", baseReg: RegDI, indexReg: asm.NilRegister, scale: 8, offset: 2147483647, expRex: 0x0, expModRM: 0x87, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegAX/scale=1/offset=-2147483648", baseReg: RegDI, indexReg: RegAX, scale: 1, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x7, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegAX/scale=2/offset=-2147483648", baseReg: RegDI, indexReg: RegAX, scale: 2, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x47, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegAX/scale=4/offset=-2147483648", baseReg: RegDI, indexReg: RegAX, scale: 4, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x87, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegAX/scale=8/offset=-2147483648", baseReg: RegDI, indexReg: RegAX, scale: 8, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xc7, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegBX/scale=1/offset=-2147483648", baseReg: RegDI, indexReg: RegBX, scale: 1, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x1f, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegBX/scale=2/offset=-2147483648", baseReg: RegDI, indexReg: RegBX, scale: 2, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x5f, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegBX/scale=4/offset=-2147483648", baseReg: RegDI, indexReg: RegBX, scale: 4, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x9f, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegBX/scale=8/offset=-2147483648", baseReg: RegDI, indexReg: RegBX, scale: 8, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xdf, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegBP/scale=1/offset=-2147483648", baseReg: RegDI, indexReg: RegBP, scale: 1, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x2f, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegBP/scale=2/offset=-2147483648", baseReg: RegDI, indexReg: RegBP, scale: 2, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x6f, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegBP/scale=4/offset=-2147483648", baseReg: RegDI, indexReg: RegBP, scale: 4, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xaf, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegBP/scale=8/offset=-2147483648", baseReg: RegDI, indexReg: RegBP, scale: 8, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xef, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegSI/scale=1/offset=-2147483648", baseReg: RegDI, indexReg: RegSI, scale: 1, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x37, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegSI/scale=2/offset=-2147483648", baseReg: RegDI, indexReg: RegSI, scale: 2, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x77, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegSI/scale=4/offset=-2147483648", baseReg: RegDI, indexReg: RegSI, scale: 4, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xb7, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegSI/scale=8/offset=-2147483648", baseReg: RegDI, indexReg: RegSI, scale: 8, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xf7, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegDI/scale=1/offset=-2147483648", baseReg: RegDI, indexReg: RegDI, scale: 1, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x3f, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegDI/scale=2/offset=-2147483648", baseReg: RegDI, indexReg: RegDI, scale: 2, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0x7f, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegDI/scale=4/offset=-2147483648", baseReg: RegDI, indexReg: RegDI, scale: 4, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xbf, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegDI/scale=8/offset=-2147483648", baseReg: RegDI, indexReg: RegDI, scale: 8, offset: -2147483648, expRex: 0x0, expModRM: 0x84, needSBI: true, expSBI: 0xff, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegR8/scale=1/offset=-2147483648", baseReg: RegDI, indexReg: RegR8, scale: 1, offset: -2147483648, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x7, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegR8/scale=2/offset=-2147483648", baseReg: RegDI, indexReg: RegR8, scale: 2, offset: -2147483648, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x47, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegR8/scale=4/offset=-2147483648", baseReg: RegDI, indexReg: RegR8, scale: 4, offset: -2147483648, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x87, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegR8/scale=8/offset=-2147483648", baseReg: RegDI, indexReg: RegR8, scale: 8, offset: -2147483648, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0xc7, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegR14/scale=1/offset=-2147483648", baseReg: RegDI, indexReg: RegR14, scale: 1, offset: -2147483648, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x37, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegR14/scale=2/offset=-2147483648", baseReg: RegDI, indexReg: RegR14, scale: 2, offset: -2147483648, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0x77, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegR14/scale=4/offset=-2147483648", baseReg: RegDI, indexReg: RegR14, scale: 4, offset: -2147483648, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0xb7, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=RegR14/scale=8/offset=-2147483648", baseReg: RegDI, indexReg: RegR14, scale: 8, offset: -2147483648, expRex: 0x42, expModRM: 0x84, needSBI: true, expSBI: 0xf7, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=Nil/scale=1/offset=-2147483648", baseReg: RegDI, indexReg: asm.NilRegister, scale: 1, offset: -2147483648, expRex: 0x0, expModRM: 0x87, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=Nil/scale=2/offset=-2147483648", baseReg: RegDI, indexReg: asm.NilRegister, scale: 2, offset: -2147483648, expRex: 0x0, expModRM: 0x87, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=Nil/scale=4/offset=-2147483648", baseReg: RegDI, indexReg: asm.NilRegister, scale: 4, offset: -2147483648, expRex: 0x0, expModRM: 0x87, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegDI/indexReg=Nil/scale=8/offset=-2147483648", baseReg: RegDI, indexReg: asm.NilRegister, scale: 8, offset: -2147483648, expRex: 0x0, expModRM: 0x87, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegAX/scale=1/offset=0", baseReg: RegR8, indexReg: RegAX, scale: 1, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0x0, displacementWidth: 0}, - {name: "baseReg=RegR8/indexReg=RegAX/scale=2/offset=0", baseReg: RegR8, indexReg: RegAX, scale: 2, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0x40, displacementWidth: 0}, - {name: "baseReg=RegR8/indexReg=RegAX/scale=4/offset=0", baseReg: RegR8, indexReg: RegAX, scale: 4, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0x80, displacementWidth: 0}, - {name: "baseReg=RegR8/indexReg=RegAX/scale=8/offset=0", baseReg: RegR8, indexReg: RegAX, scale: 8, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0xc0, displacementWidth: 0}, - {name: "baseReg=RegR8/indexReg=RegBX/scale=1/offset=0", baseReg: RegR8, indexReg: RegBX, scale: 1, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0x18, displacementWidth: 0}, - {name: "baseReg=RegR8/indexReg=RegBX/scale=2/offset=0", baseReg: RegR8, indexReg: RegBX, scale: 2, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0x58, displacementWidth: 0}, - {name: "baseReg=RegR8/indexReg=RegBX/scale=4/offset=0", baseReg: RegR8, indexReg: RegBX, scale: 4, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0x98, displacementWidth: 0}, - {name: "baseReg=RegR8/indexReg=RegBX/scale=8/offset=0", baseReg: RegR8, indexReg: RegBX, scale: 8, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0xd8, displacementWidth: 0}, - {name: "baseReg=RegR8/indexReg=RegBP/scale=1/offset=0", baseReg: RegR8, indexReg: RegBP, scale: 1, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0x28, displacementWidth: 0}, - {name: "baseReg=RegR8/indexReg=RegBP/scale=2/offset=0", baseReg: RegR8, indexReg: RegBP, scale: 2, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0x68, displacementWidth: 0}, - {name: "baseReg=RegR8/indexReg=RegBP/scale=4/offset=0", baseReg: RegR8, indexReg: RegBP, scale: 4, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0xa8, displacementWidth: 0}, - {name: "baseReg=RegR8/indexReg=RegBP/scale=8/offset=0", baseReg: RegR8, indexReg: RegBP, scale: 8, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0xe8, displacementWidth: 0}, - {name: "baseReg=RegR8/indexReg=RegSI/scale=1/offset=0", baseReg: RegR8, indexReg: RegSI, scale: 1, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0x30, displacementWidth: 0}, - {name: "baseReg=RegR8/indexReg=RegSI/scale=2/offset=0", baseReg: RegR8, indexReg: RegSI, scale: 2, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0x70, displacementWidth: 0}, - {name: "baseReg=RegR8/indexReg=RegSI/scale=4/offset=0", baseReg: RegR8, indexReg: RegSI, scale: 4, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0xb0, displacementWidth: 0}, - {name: "baseReg=RegR8/indexReg=RegSI/scale=8/offset=0", baseReg: RegR8, indexReg: RegSI, scale: 8, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0xf0, displacementWidth: 0}, - {name: "baseReg=RegR8/indexReg=RegDI/scale=1/offset=0", baseReg: RegR8, indexReg: RegDI, scale: 1, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0x38, displacementWidth: 0}, - {name: "baseReg=RegR8/indexReg=RegDI/scale=2/offset=0", baseReg: RegR8, indexReg: RegDI, scale: 2, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0x78, displacementWidth: 0}, - {name: "baseReg=RegR8/indexReg=RegDI/scale=4/offset=0", baseReg: RegR8, indexReg: RegDI, scale: 4, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0xb8, displacementWidth: 0}, - {name: "baseReg=RegR8/indexReg=RegDI/scale=8/offset=0", baseReg: RegR8, indexReg: RegDI, scale: 8, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0xf8, displacementWidth: 0}, - {name: "baseReg=RegR8/indexReg=RegR8/scale=1/offset=0", baseReg: RegR8, indexReg: RegR8, scale: 1, offset: 0, expRex: 0x43, expModRM: 0x4, needSBI: true, expSBI: 0x0, displacementWidth: 0}, - {name: "baseReg=RegR8/indexReg=RegR8/scale=2/offset=0", baseReg: RegR8, indexReg: RegR8, scale: 2, offset: 0, expRex: 0x43, expModRM: 0x4, needSBI: true, expSBI: 0x40, displacementWidth: 0}, - {name: "baseReg=RegR8/indexReg=RegR8/scale=4/offset=0", baseReg: RegR8, indexReg: RegR8, scale: 4, offset: 0, expRex: 0x43, expModRM: 0x4, needSBI: true, expSBI: 0x80, displacementWidth: 0}, - {name: "baseReg=RegR8/indexReg=RegR8/scale=8/offset=0", baseReg: RegR8, indexReg: RegR8, scale: 8, offset: 0, expRex: 0x43, expModRM: 0x4, needSBI: true, expSBI: 0xc0, displacementWidth: 0}, - {name: "baseReg=RegR8/indexReg=RegR14/scale=1/offset=0", baseReg: RegR8, indexReg: RegR14, scale: 1, offset: 0, expRex: 0x43, expModRM: 0x4, needSBI: true, expSBI: 0x30, displacementWidth: 0}, - {name: "baseReg=RegR8/indexReg=RegR14/scale=2/offset=0", baseReg: RegR8, indexReg: RegR14, scale: 2, offset: 0, expRex: 0x43, expModRM: 0x4, needSBI: true, expSBI: 0x70, displacementWidth: 0}, - {name: "baseReg=RegR8/indexReg=RegR14/scale=4/offset=0", baseReg: RegR8, indexReg: RegR14, scale: 4, offset: 0, expRex: 0x43, expModRM: 0x4, needSBI: true, expSBI: 0xb0, displacementWidth: 0}, - {name: "baseReg=RegR8/indexReg=RegR14/scale=8/offset=0", baseReg: RegR8, indexReg: RegR14, scale: 8, offset: 0, expRex: 0x43, expModRM: 0x4, needSBI: true, expSBI: 0xf0, displacementWidth: 0}, - {name: "baseReg=RegR8/indexReg=Nil/scale=1/offset=0", baseReg: RegR8, indexReg: asm.NilRegister, scale: 1, offset: 0, expRex: 0x41, expModRM: 0x0, needSBI: false, displacementWidth: 0}, - {name: "baseReg=RegR8/indexReg=Nil/scale=2/offset=0", baseReg: RegR8, indexReg: asm.NilRegister, scale: 2, offset: 0, expRex: 0x41, expModRM: 0x0, needSBI: false, displacementWidth: 0}, - {name: "baseReg=RegR8/indexReg=Nil/scale=4/offset=0", baseReg: RegR8, indexReg: asm.NilRegister, scale: 4, offset: 0, expRex: 0x41, expModRM: 0x0, needSBI: false, displacementWidth: 0}, - {name: "baseReg=RegR8/indexReg=Nil/scale=8/offset=0", baseReg: RegR8, indexReg: asm.NilRegister, scale: 8, offset: 0, expRex: 0x41, expModRM: 0x0, needSBI: false, displacementWidth: 0}, - {name: "baseReg=RegR8/indexReg=RegAX/scale=1/offset=1", baseReg: RegR8, indexReg: RegAX, scale: 1, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x0, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegAX/scale=2/offset=1", baseReg: RegR8, indexReg: RegAX, scale: 2, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x40, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegAX/scale=4/offset=1", baseReg: RegR8, indexReg: RegAX, scale: 4, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x80, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegAX/scale=8/offset=1", baseReg: RegR8, indexReg: RegAX, scale: 8, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xc0, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegBX/scale=1/offset=1", baseReg: RegR8, indexReg: RegBX, scale: 1, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x18, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegBX/scale=2/offset=1", baseReg: RegR8, indexReg: RegBX, scale: 2, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x58, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegBX/scale=4/offset=1", baseReg: RegR8, indexReg: RegBX, scale: 4, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x98, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegBX/scale=8/offset=1", baseReg: RegR8, indexReg: RegBX, scale: 8, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xd8, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegBP/scale=1/offset=1", baseReg: RegR8, indexReg: RegBP, scale: 1, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x28, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegBP/scale=2/offset=1", baseReg: RegR8, indexReg: RegBP, scale: 2, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x68, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegBP/scale=4/offset=1", baseReg: RegR8, indexReg: RegBP, scale: 4, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xa8, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegBP/scale=8/offset=1", baseReg: RegR8, indexReg: RegBP, scale: 8, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xe8, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegSI/scale=1/offset=1", baseReg: RegR8, indexReg: RegSI, scale: 1, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x30, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegSI/scale=2/offset=1", baseReg: RegR8, indexReg: RegSI, scale: 2, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x70, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegSI/scale=4/offset=1", baseReg: RegR8, indexReg: RegSI, scale: 4, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xb0, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegSI/scale=8/offset=1", baseReg: RegR8, indexReg: RegSI, scale: 8, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xf0, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegDI/scale=1/offset=1", baseReg: RegR8, indexReg: RegDI, scale: 1, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x38, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegDI/scale=2/offset=1", baseReg: RegR8, indexReg: RegDI, scale: 2, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x78, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegDI/scale=4/offset=1", baseReg: RegR8, indexReg: RegDI, scale: 4, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xb8, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegDI/scale=8/offset=1", baseReg: RegR8, indexReg: RegDI, scale: 8, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xf8, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegR8/scale=1/offset=1", baseReg: RegR8, indexReg: RegR8, scale: 1, offset: 1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0x0, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegR8/scale=2/offset=1", baseReg: RegR8, indexReg: RegR8, scale: 2, offset: 1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0x40, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegR8/scale=4/offset=1", baseReg: RegR8, indexReg: RegR8, scale: 4, offset: 1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0x80, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegR8/scale=8/offset=1", baseReg: RegR8, indexReg: RegR8, scale: 8, offset: 1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0xc0, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegR14/scale=1/offset=1", baseReg: RegR8, indexReg: RegR14, scale: 1, offset: 1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0x30, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegR14/scale=2/offset=1", baseReg: RegR8, indexReg: RegR14, scale: 2, offset: 1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0x70, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegR14/scale=4/offset=1", baseReg: RegR8, indexReg: RegR14, scale: 4, offset: 1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0xb0, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegR14/scale=8/offset=1", baseReg: RegR8, indexReg: RegR14, scale: 8, offset: 1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0xf0, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=Nil/scale=1/offset=1", baseReg: RegR8, indexReg: asm.NilRegister, scale: 1, offset: 1, expRex: 0x41, expModRM: 0x40, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=Nil/scale=2/offset=1", baseReg: RegR8, indexReg: asm.NilRegister, scale: 2, offset: 1, expRex: 0x41, expModRM: 0x40, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=Nil/scale=4/offset=1", baseReg: RegR8, indexReg: asm.NilRegister, scale: 4, offset: 1, expRex: 0x41, expModRM: 0x40, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=Nil/scale=8/offset=1", baseReg: RegR8, indexReg: asm.NilRegister, scale: 8, offset: 1, expRex: 0x41, expModRM: 0x40, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegAX/scale=1/offset=-1", baseReg: RegR8, indexReg: RegAX, scale: 1, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x0, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegAX/scale=2/offset=-1", baseReg: RegR8, indexReg: RegAX, scale: 2, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x40, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegAX/scale=4/offset=-1", baseReg: RegR8, indexReg: RegAX, scale: 4, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x80, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegAX/scale=8/offset=-1", baseReg: RegR8, indexReg: RegAX, scale: 8, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xc0, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegBX/scale=1/offset=-1", baseReg: RegR8, indexReg: RegBX, scale: 1, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x18, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegBX/scale=2/offset=-1", baseReg: RegR8, indexReg: RegBX, scale: 2, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x58, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegBX/scale=4/offset=-1", baseReg: RegR8, indexReg: RegBX, scale: 4, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x98, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegBX/scale=8/offset=-1", baseReg: RegR8, indexReg: RegBX, scale: 8, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xd8, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegBP/scale=1/offset=-1", baseReg: RegR8, indexReg: RegBP, scale: 1, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x28, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegBP/scale=2/offset=-1", baseReg: RegR8, indexReg: RegBP, scale: 2, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x68, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegBP/scale=4/offset=-1", baseReg: RegR8, indexReg: RegBP, scale: 4, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xa8, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegBP/scale=8/offset=-1", baseReg: RegR8, indexReg: RegBP, scale: 8, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xe8, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegSI/scale=1/offset=-1", baseReg: RegR8, indexReg: RegSI, scale: 1, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x30, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegSI/scale=2/offset=-1", baseReg: RegR8, indexReg: RegSI, scale: 2, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x70, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegSI/scale=4/offset=-1", baseReg: RegR8, indexReg: RegSI, scale: 4, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xb0, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegSI/scale=8/offset=-1", baseReg: RegR8, indexReg: RegSI, scale: 8, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xf0, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegDI/scale=1/offset=-1", baseReg: RegR8, indexReg: RegDI, scale: 1, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x38, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegDI/scale=2/offset=-1", baseReg: RegR8, indexReg: RegDI, scale: 2, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x78, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegDI/scale=4/offset=-1", baseReg: RegR8, indexReg: RegDI, scale: 4, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xb8, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegDI/scale=8/offset=-1", baseReg: RegR8, indexReg: RegDI, scale: 8, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xf8, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegR8/scale=1/offset=-1", baseReg: RegR8, indexReg: RegR8, scale: 1, offset: -1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0x0, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegR8/scale=2/offset=-1", baseReg: RegR8, indexReg: RegR8, scale: 2, offset: -1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0x40, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegR8/scale=4/offset=-1", baseReg: RegR8, indexReg: RegR8, scale: 4, offset: -1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0x80, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegR8/scale=8/offset=-1", baseReg: RegR8, indexReg: RegR8, scale: 8, offset: -1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0xc0, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegR14/scale=1/offset=-1", baseReg: RegR8, indexReg: RegR14, scale: 1, offset: -1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0x30, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegR14/scale=2/offset=-1", baseReg: RegR8, indexReg: RegR14, scale: 2, offset: -1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0x70, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegR14/scale=4/offset=-1", baseReg: RegR8, indexReg: RegR14, scale: 4, offset: -1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0xb0, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegR14/scale=8/offset=-1", baseReg: RegR8, indexReg: RegR14, scale: 8, offset: -1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0xf0, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=Nil/scale=1/offset=-1", baseReg: RegR8, indexReg: asm.NilRegister, scale: 1, offset: -1, expRex: 0x41, expModRM: 0x40, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=Nil/scale=2/offset=-1", baseReg: RegR8, indexReg: asm.NilRegister, scale: 2, offset: -1, expRex: 0x41, expModRM: 0x40, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=Nil/scale=4/offset=-1", baseReg: RegR8, indexReg: asm.NilRegister, scale: 4, offset: -1, expRex: 0x41, expModRM: 0x40, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=Nil/scale=8/offset=-1", baseReg: RegR8, indexReg: asm.NilRegister, scale: 8, offset: -1, expRex: 0x41, expModRM: 0x40, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegR8/indexReg=RegAX/scale=1/offset=2147483647", baseReg: RegR8, indexReg: RegAX, scale: 1, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x0, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegAX/scale=2/offset=2147483647", baseReg: RegR8, indexReg: RegAX, scale: 2, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x40, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegAX/scale=4/offset=2147483647", baseReg: RegR8, indexReg: RegAX, scale: 4, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x80, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegAX/scale=8/offset=2147483647", baseReg: RegR8, indexReg: RegAX, scale: 8, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xc0, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegBX/scale=1/offset=2147483647", baseReg: RegR8, indexReg: RegBX, scale: 1, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x18, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegBX/scale=2/offset=2147483647", baseReg: RegR8, indexReg: RegBX, scale: 2, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x58, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegBX/scale=4/offset=2147483647", baseReg: RegR8, indexReg: RegBX, scale: 4, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x98, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegBX/scale=8/offset=2147483647", baseReg: RegR8, indexReg: RegBX, scale: 8, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xd8, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegBP/scale=1/offset=2147483647", baseReg: RegR8, indexReg: RegBP, scale: 1, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x28, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegBP/scale=2/offset=2147483647", baseReg: RegR8, indexReg: RegBP, scale: 2, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x68, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegBP/scale=4/offset=2147483647", baseReg: RegR8, indexReg: RegBP, scale: 4, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xa8, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegBP/scale=8/offset=2147483647", baseReg: RegR8, indexReg: RegBP, scale: 8, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xe8, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegSI/scale=1/offset=2147483647", baseReg: RegR8, indexReg: RegSI, scale: 1, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x30, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegSI/scale=2/offset=2147483647", baseReg: RegR8, indexReg: RegSI, scale: 2, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x70, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegSI/scale=4/offset=2147483647", baseReg: RegR8, indexReg: RegSI, scale: 4, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xb0, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegSI/scale=8/offset=2147483647", baseReg: RegR8, indexReg: RegSI, scale: 8, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xf0, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegDI/scale=1/offset=2147483647", baseReg: RegR8, indexReg: RegDI, scale: 1, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x38, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegDI/scale=2/offset=2147483647", baseReg: RegR8, indexReg: RegDI, scale: 2, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x78, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegDI/scale=4/offset=2147483647", baseReg: RegR8, indexReg: RegDI, scale: 4, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xb8, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegDI/scale=8/offset=2147483647", baseReg: RegR8, indexReg: RegDI, scale: 8, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xf8, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegR8/scale=1/offset=2147483647", baseReg: RegR8, indexReg: RegR8, scale: 1, offset: 2147483647, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0x0, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegR8/scale=2/offset=2147483647", baseReg: RegR8, indexReg: RegR8, scale: 2, offset: 2147483647, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0x40, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegR8/scale=4/offset=2147483647", baseReg: RegR8, indexReg: RegR8, scale: 4, offset: 2147483647, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0x80, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegR8/scale=8/offset=2147483647", baseReg: RegR8, indexReg: RegR8, scale: 8, offset: 2147483647, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0xc0, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegR14/scale=1/offset=2147483647", baseReg: RegR8, indexReg: RegR14, scale: 1, offset: 2147483647, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0x30, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegR14/scale=2/offset=2147483647", baseReg: RegR8, indexReg: RegR14, scale: 2, offset: 2147483647, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0x70, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegR14/scale=4/offset=2147483647", baseReg: RegR8, indexReg: RegR14, scale: 4, offset: 2147483647, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0xb0, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegR14/scale=8/offset=2147483647", baseReg: RegR8, indexReg: RegR14, scale: 8, offset: 2147483647, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0xf0, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=Nil/scale=1/offset=2147483647", baseReg: RegR8, indexReg: asm.NilRegister, scale: 1, offset: 2147483647, expRex: 0x41, expModRM: 0x80, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=Nil/scale=2/offset=2147483647", baseReg: RegR8, indexReg: asm.NilRegister, scale: 2, offset: 2147483647, expRex: 0x41, expModRM: 0x80, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=Nil/scale=4/offset=2147483647", baseReg: RegR8, indexReg: asm.NilRegister, scale: 4, offset: 2147483647, expRex: 0x41, expModRM: 0x80, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=Nil/scale=8/offset=2147483647", baseReg: RegR8, indexReg: asm.NilRegister, scale: 8, offset: 2147483647, expRex: 0x41, expModRM: 0x80, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegAX/scale=1/offset=-2147483648", baseReg: RegR8, indexReg: RegAX, scale: 1, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x0, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegAX/scale=2/offset=-2147483648", baseReg: RegR8, indexReg: RegAX, scale: 2, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x40, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegAX/scale=4/offset=-2147483648", baseReg: RegR8, indexReg: RegAX, scale: 4, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x80, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegAX/scale=8/offset=-2147483648", baseReg: RegR8, indexReg: RegAX, scale: 8, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xc0, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegBX/scale=1/offset=-2147483648", baseReg: RegR8, indexReg: RegBX, scale: 1, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x18, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegBX/scale=2/offset=-2147483648", baseReg: RegR8, indexReg: RegBX, scale: 2, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x58, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegBX/scale=4/offset=-2147483648", baseReg: RegR8, indexReg: RegBX, scale: 4, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x98, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegBX/scale=8/offset=-2147483648", baseReg: RegR8, indexReg: RegBX, scale: 8, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xd8, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegBP/scale=1/offset=-2147483648", baseReg: RegR8, indexReg: RegBP, scale: 1, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x28, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegBP/scale=2/offset=-2147483648", baseReg: RegR8, indexReg: RegBP, scale: 2, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x68, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegBP/scale=4/offset=-2147483648", baseReg: RegR8, indexReg: RegBP, scale: 4, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xa8, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegBP/scale=8/offset=-2147483648", baseReg: RegR8, indexReg: RegBP, scale: 8, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xe8, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegSI/scale=1/offset=-2147483648", baseReg: RegR8, indexReg: RegSI, scale: 1, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x30, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegSI/scale=2/offset=-2147483648", baseReg: RegR8, indexReg: RegSI, scale: 2, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x70, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegSI/scale=4/offset=-2147483648", baseReg: RegR8, indexReg: RegSI, scale: 4, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xb0, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegSI/scale=8/offset=-2147483648", baseReg: RegR8, indexReg: RegSI, scale: 8, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xf0, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegDI/scale=1/offset=-2147483648", baseReg: RegR8, indexReg: RegDI, scale: 1, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x38, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegDI/scale=2/offset=-2147483648", baseReg: RegR8, indexReg: RegDI, scale: 2, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x78, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegDI/scale=4/offset=-2147483648", baseReg: RegR8, indexReg: RegDI, scale: 4, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xb8, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegDI/scale=8/offset=-2147483648", baseReg: RegR8, indexReg: RegDI, scale: 8, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xf8, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegR8/scale=1/offset=-2147483648", baseReg: RegR8, indexReg: RegR8, scale: 1, offset: -2147483648, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0x0, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegR8/scale=2/offset=-2147483648", baseReg: RegR8, indexReg: RegR8, scale: 2, offset: -2147483648, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0x40, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegR8/scale=4/offset=-2147483648", baseReg: RegR8, indexReg: RegR8, scale: 4, offset: -2147483648, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0x80, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegR8/scale=8/offset=-2147483648", baseReg: RegR8, indexReg: RegR8, scale: 8, offset: -2147483648, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0xc0, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegR14/scale=1/offset=-2147483648", baseReg: RegR8, indexReg: RegR14, scale: 1, offset: -2147483648, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0x30, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegR14/scale=2/offset=-2147483648", baseReg: RegR8, indexReg: RegR14, scale: 2, offset: -2147483648, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0x70, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegR14/scale=4/offset=-2147483648", baseReg: RegR8, indexReg: RegR14, scale: 4, offset: -2147483648, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0xb0, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=RegR14/scale=8/offset=-2147483648", baseReg: RegR8, indexReg: RegR14, scale: 8, offset: -2147483648, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0xf0, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=Nil/scale=1/offset=-2147483648", baseReg: RegR8, indexReg: asm.NilRegister, scale: 1, offset: -2147483648, expRex: 0x41, expModRM: 0x80, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=Nil/scale=2/offset=-2147483648", baseReg: RegR8, indexReg: asm.NilRegister, scale: 2, offset: -2147483648, expRex: 0x41, expModRM: 0x80, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=Nil/scale=4/offset=-2147483648", baseReg: RegR8, indexReg: asm.NilRegister, scale: 4, offset: -2147483648, expRex: 0x41, expModRM: 0x80, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegR8/indexReg=Nil/scale=8/offset=-2147483648", baseReg: RegR8, indexReg: asm.NilRegister, scale: 8, offset: -2147483648, expRex: 0x41, expModRM: 0x80, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegAX/scale=1/offset=0", baseReg: RegR9, indexReg: RegAX, scale: 1, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0x1, displacementWidth: 0}, - {name: "baseReg=RegR9/indexReg=RegAX/scale=2/offset=0", baseReg: RegR9, indexReg: RegAX, scale: 2, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0x41, displacementWidth: 0}, - {name: "baseReg=RegR9/indexReg=RegAX/scale=4/offset=0", baseReg: RegR9, indexReg: RegAX, scale: 4, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0x81, displacementWidth: 0}, - {name: "baseReg=RegR9/indexReg=RegAX/scale=8/offset=0", baseReg: RegR9, indexReg: RegAX, scale: 8, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0xc1, displacementWidth: 0}, - {name: "baseReg=RegR9/indexReg=RegBX/scale=1/offset=0", baseReg: RegR9, indexReg: RegBX, scale: 1, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0x19, displacementWidth: 0}, - {name: "baseReg=RegR9/indexReg=RegBX/scale=2/offset=0", baseReg: RegR9, indexReg: RegBX, scale: 2, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0x59, displacementWidth: 0}, - {name: "baseReg=RegR9/indexReg=RegBX/scale=4/offset=0", baseReg: RegR9, indexReg: RegBX, scale: 4, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0x99, displacementWidth: 0}, - {name: "baseReg=RegR9/indexReg=RegBX/scale=8/offset=0", baseReg: RegR9, indexReg: RegBX, scale: 8, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0xd9, displacementWidth: 0}, - {name: "baseReg=RegR9/indexReg=RegBP/scale=1/offset=0", baseReg: RegR9, indexReg: RegBP, scale: 1, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0x29, displacementWidth: 0}, - {name: "baseReg=RegR9/indexReg=RegBP/scale=2/offset=0", baseReg: RegR9, indexReg: RegBP, scale: 2, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0x69, displacementWidth: 0}, - {name: "baseReg=RegR9/indexReg=RegBP/scale=4/offset=0", baseReg: RegR9, indexReg: RegBP, scale: 4, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0xa9, displacementWidth: 0}, - {name: "baseReg=RegR9/indexReg=RegBP/scale=8/offset=0", baseReg: RegR9, indexReg: RegBP, scale: 8, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0xe9, displacementWidth: 0}, - {name: "baseReg=RegR9/indexReg=RegSI/scale=1/offset=0", baseReg: RegR9, indexReg: RegSI, scale: 1, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0x31, displacementWidth: 0}, - {name: "baseReg=RegR9/indexReg=RegSI/scale=2/offset=0", baseReg: RegR9, indexReg: RegSI, scale: 2, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0x71, displacementWidth: 0}, - {name: "baseReg=RegR9/indexReg=RegSI/scale=4/offset=0", baseReg: RegR9, indexReg: RegSI, scale: 4, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0xb1, displacementWidth: 0}, - {name: "baseReg=RegR9/indexReg=RegSI/scale=8/offset=0", baseReg: RegR9, indexReg: RegSI, scale: 8, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0xf1, displacementWidth: 0}, - {name: "baseReg=RegR9/indexReg=RegDI/scale=1/offset=0", baseReg: RegR9, indexReg: RegDI, scale: 1, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0x39, displacementWidth: 0}, - {name: "baseReg=RegR9/indexReg=RegDI/scale=2/offset=0", baseReg: RegR9, indexReg: RegDI, scale: 2, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0x79, displacementWidth: 0}, - {name: "baseReg=RegR9/indexReg=RegDI/scale=4/offset=0", baseReg: RegR9, indexReg: RegDI, scale: 4, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0xb9, displacementWidth: 0}, - {name: "baseReg=RegR9/indexReg=RegDI/scale=8/offset=0", baseReg: RegR9, indexReg: RegDI, scale: 8, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0xf9, displacementWidth: 0}, - {name: "baseReg=RegR9/indexReg=RegR8/scale=1/offset=0", baseReg: RegR9, indexReg: RegR8, scale: 1, offset: 0, expRex: 0x43, expModRM: 0x4, needSBI: true, expSBI: 0x1, displacementWidth: 0}, - {name: "baseReg=RegR9/indexReg=RegR8/scale=2/offset=0", baseReg: RegR9, indexReg: RegR8, scale: 2, offset: 0, expRex: 0x43, expModRM: 0x4, needSBI: true, expSBI: 0x41, displacementWidth: 0}, - {name: "baseReg=RegR9/indexReg=RegR8/scale=4/offset=0", baseReg: RegR9, indexReg: RegR8, scale: 4, offset: 0, expRex: 0x43, expModRM: 0x4, needSBI: true, expSBI: 0x81, displacementWidth: 0}, - {name: "baseReg=RegR9/indexReg=RegR8/scale=8/offset=0", baseReg: RegR9, indexReg: RegR8, scale: 8, offset: 0, expRex: 0x43, expModRM: 0x4, needSBI: true, expSBI: 0xc1, displacementWidth: 0}, - {name: "baseReg=RegR9/indexReg=RegR14/scale=1/offset=0", baseReg: RegR9, indexReg: RegR14, scale: 1, offset: 0, expRex: 0x43, expModRM: 0x4, needSBI: true, expSBI: 0x31, displacementWidth: 0}, - {name: "baseReg=RegR9/indexReg=RegR14/scale=2/offset=0", baseReg: RegR9, indexReg: RegR14, scale: 2, offset: 0, expRex: 0x43, expModRM: 0x4, needSBI: true, expSBI: 0x71, displacementWidth: 0}, - {name: "baseReg=RegR9/indexReg=RegR14/scale=4/offset=0", baseReg: RegR9, indexReg: RegR14, scale: 4, offset: 0, expRex: 0x43, expModRM: 0x4, needSBI: true, expSBI: 0xb1, displacementWidth: 0}, - {name: "baseReg=RegR9/indexReg=RegR14/scale=8/offset=0", baseReg: RegR9, indexReg: RegR14, scale: 8, offset: 0, expRex: 0x43, expModRM: 0x4, needSBI: true, expSBI: 0xf1, displacementWidth: 0}, - {name: "baseReg=RegR9/indexReg=Nil/scale=1/offset=0", baseReg: RegR9, indexReg: asm.NilRegister, scale: 1, offset: 0, expRex: 0x41, expModRM: 0x1, needSBI: false, displacementWidth: 0}, - {name: "baseReg=RegR9/indexReg=Nil/scale=2/offset=0", baseReg: RegR9, indexReg: asm.NilRegister, scale: 2, offset: 0, expRex: 0x41, expModRM: 0x1, needSBI: false, displacementWidth: 0}, - {name: "baseReg=RegR9/indexReg=Nil/scale=4/offset=0", baseReg: RegR9, indexReg: asm.NilRegister, scale: 4, offset: 0, expRex: 0x41, expModRM: 0x1, needSBI: false, displacementWidth: 0}, - {name: "baseReg=RegR9/indexReg=Nil/scale=8/offset=0", baseReg: RegR9, indexReg: asm.NilRegister, scale: 8, offset: 0, expRex: 0x41, expModRM: 0x1, needSBI: false, displacementWidth: 0}, - {name: "baseReg=RegR9/indexReg=RegAX/scale=1/offset=1", baseReg: RegR9, indexReg: RegAX, scale: 1, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x1, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegAX/scale=2/offset=1", baseReg: RegR9, indexReg: RegAX, scale: 2, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x41, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegAX/scale=4/offset=1", baseReg: RegR9, indexReg: RegAX, scale: 4, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x81, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegAX/scale=8/offset=1", baseReg: RegR9, indexReg: RegAX, scale: 8, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xc1, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegBX/scale=1/offset=1", baseReg: RegR9, indexReg: RegBX, scale: 1, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x19, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegBX/scale=2/offset=1", baseReg: RegR9, indexReg: RegBX, scale: 2, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x59, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegBX/scale=4/offset=1", baseReg: RegR9, indexReg: RegBX, scale: 4, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x99, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegBX/scale=8/offset=1", baseReg: RegR9, indexReg: RegBX, scale: 8, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xd9, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegBP/scale=1/offset=1", baseReg: RegR9, indexReg: RegBP, scale: 1, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x29, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegBP/scale=2/offset=1", baseReg: RegR9, indexReg: RegBP, scale: 2, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x69, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegBP/scale=4/offset=1", baseReg: RegR9, indexReg: RegBP, scale: 4, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xa9, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegBP/scale=8/offset=1", baseReg: RegR9, indexReg: RegBP, scale: 8, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xe9, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegSI/scale=1/offset=1", baseReg: RegR9, indexReg: RegSI, scale: 1, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x31, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegSI/scale=2/offset=1", baseReg: RegR9, indexReg: RegSI, scale: 2, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x71, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegSI/scale=4/offset=1", baseReg: RegR9, indexReg: RegSI, scale: 4, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xb1, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegSI/scale=8/offset=1", baseReg: RegR9, indexReg: RegSI, scale: 8, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xf1, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegDI/scale=1/offset=1", baseReg: RegR9, indexReg: RegDI, scale: 1, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x39, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegDI/scale=2/offset=1", baseReg: RegR9, indexReg: RegDI, scale: 2, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x79, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegDI/scale=4/offset=1", baseReg: RegR9, indexReg: RegDI, scale: 4, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xb9, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegDI/scale=8/offset=1", baseReg: RegR9, indexReg: RegDI, scale: 8, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xf9, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegR8/scale=1/offset=1", baseReg: RegR9, indexReg: RegR8, scale: 1, offset: 1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0x1, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegR8/scale=2/offset=1", baseReg: RegR9, indexReg: RegR8, scale: 2, offset: 1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0x41, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegR8/scale=4/offset=1", baseReg: RegR9, indexReg: RegR8, scale: 4, offset: 1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0x81, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegR8/scale=8/offset=1", baseReg: RegR9, indexReg: RegR8, scale: 8, offset: 1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0xc1, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegR14/scale=1/offset=1", baseReg: RegR9, indexReg: RegR14, scale: 1, offset: 1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0x31, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegR14/scale=2/offset=1", baseReg: RegR9, indexReg: RegR14, scale: 2, offset: 1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0x71, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegR14/scale=4/offset=1", baseReg: RegR9, indexReg: RegR14, scale: 4, offset: 1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0xb1, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegR14/scale=8/offset=1", baseReg: RegR9, indexReg: RegR14, scale: 8, offset: 1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0xf1, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=Nil/scale=1/offset=1", baseReg: RegR9, indexReg: asm.NilRegister, scale: 1, offset: 1, expRex: 0x41, expModRM: 0x41, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=Nil/scale=2/offset=1", baseReg: RegR9, indexReg: asm.NilRegister, scale: 2, offset: 1, expRex: 0x41, expModRM: 0x41, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=Nil/scale=4/offset=1", baseReg: RegR9, indexReg: asm.NilRegister, scale: 4, offset: 1, expRex: 0x41, expModRM: 0x41, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=Nil/scale=8/offset=1", baseReg: RegR9, indexReg: asm.NilRegister, scale: 8, offset: 1, expRex: 0x41, expModRM: 0x41, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegAX/scale=1/offset=-1", baseReg: RegR9, indexReg: RegAX, scale: 1, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x1, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegAX/scale=2/offset=-1", baseReg: RegR9, indexReg: RegAX, scale: 2, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x41, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegAX/scale=4/offset=-1", baseReg: RegR9, indexReg: RegAX, scale: 4, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x81, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegAX/scale=8/offset=-1", baseReg: RegR9, indexReg: RegAX, scale: 8, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xc1, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegBX/scale=1/offset=-1", baseReg: RegR9, indexReg: RegBX, scale: 1, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x19, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegBX/scale=2/offset=-1", baseReg: RegR9, indexReg: RegBX, scale: 2, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x59, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegBX/scale=4/offset=-1", baseReg: RegR9, indexReg: RegBX, scale: 4, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x99, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegBX/scale=8/offset=-1", baseReg: RegR9, indexReg: RegBX, scale: 8, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xd9, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegBP/scale=1/offset=-1", baseReg: RegR9, indexReg: RegBP, scale: 1, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x29, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegBP/scale=2/offset=-1", baseReg: RegR9, indexReg: RegBP, scale: 2, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x69, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegBP/scale=4/offset=-1", baseReg: RegR9, indexReg: RegBP, scale: 4, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xa9, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegBP/scale=8/offset=-1", baseReg: RegR9, indexReg: RegBP, scale: 8, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xe9, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegSI/scale=1/offset=-1", baseReg: RegR9, indexReg: RegSI, scale: 1, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x31, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegSI/scale=2/offset=-1", baseReg: RegR9, indexReg: RegSI, scale: 2, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x71, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegSI/scale=4/offset=-1", baseReg: RegR9, indexReg: RegSI, scale: 4, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xb1, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegSI/scale=8/offset=-1", baseReg: RegR9, indexReg: RegSI, scale: 8, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xf1, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegDI/scale=1/offset=-1", baseReg: RegR9, indexReg: RegDI, scale: 1, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x39, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegDI/scale=2/offset=-1", baseReg: RegR9, indexReg: RegDI, scale: 2, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x79, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegDI/scale=4/offset=-1", baseReg: RegR9, indexReg: RegDI, scale: 4, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xb9, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegDI/scale=8/offset=-1", baseReg: RegR9, indexReg: RegDI, scale: 8, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xf9, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegR8/scale=1/offset=-1", baseReg: RegR9, indexReg: RegR8, scale: 1, offset: -1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0x1, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegR8/scale=2/offset=-1", baseReg: RegR9, indexReg: RegR8, scale: 2, offset: -1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0x41, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegR8/scale=4/offset=-1", baseReg: RegR9, indexReg: RegR8, scale: 4, offset: -1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0x81, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegR8/scale=8/offset=-1", baseReg: RegR9, indexReg: RegR8, scale: 8, offset: -1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0xc1, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegR14/scale=1/offset=-1", baseReg: RegR9, indexReg: RegR14, scale: 1, offset: -1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0x31, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegR14/scale=2/offset=-1", baseReg: RegR9, indexReg: RegR14, scale: 2, offset: -1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0x71, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegR14/scale=4/offset=-1", baseReg: RegR9, indexReg: RegR14, scale: 4, offset: -1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0xb1, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegR14/scale=8/offset=-1", baseReg: RegR9, indexReg: RegR14, scale: 8, offset: -1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0xf1, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=Nil/scale=1/offset=-1", baseReg: RegR9, indexReg: asm.NilRegister, scale: 1, offset: -1, expRex: 0x41, expModRM: 0x41, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=Nil/scale=2/offset=-1", baseReg: RegR9, indexReg: asm.NilRegister, scale: 2, offset: -1, expRex: 0x41, expModRM: 0x41, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=Nil/scale=4/offset=-1", baseReg: RegR9, indexReg: asm.NilRegister, scale: 4, offset: -1, expRex: 0x41, expModRM: 0x41, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=Nil/scale=8/offset=-1", baseReg: RegR9, indexReg: asm.NilRegister, scale: 8, offset: -1, expRex: 0x41, expModRM: 0x41, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegR9/indexReg=RegAX/scale=1/offset=2147483647", baseReg: RegR9, indexReg: RegAX, scale: 1, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x1, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegAX/scale=2/offset=2147483647", baseReg: RegR9, indexReg: RegAX, scale: 2, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x41, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegAX/scale=4/offset=2147483647", baseReg: RegR9, indexReg: RegAX, scale: 4, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x81, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegAX/scale=8/offset=2147483647", baseReg: RegR9, indexReg: RegAX, scale: 8, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xc1, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegBX/scale=1/offset=2147483647", baseReg: RegR9, indexReg: RegBX, scale: 1, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x19, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegBX/scale=2/offset=2147483647", baseReg: RegR9, indexReg: RegBX, scale: 2, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x59, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegBX/scale=4/offset=2147483647", baseReg: RegR9, indexReg: RegBX, scale: 4, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x99, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegBX/scale=8/offset=2147483647", baseReg: RegR9, indexReg: RegBX, scale: 8, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xd9, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegBP/scale=1/offset=2147483647", baseReg: RegR9, indexReg: RegBP, scale: 1, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x29, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegBP/scale=2/offset=2147483647", baseReg: RegR9, indexReg: RegBP, scale: 2, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x69, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegBP/scale=4/offset=2147483647", baseReg: RegR9, indexReg: RegBP, scale: 4, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xa9, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegBP/scale=8/offset=2147483647", baseReg: RegR9, indexReg: RegBP, scale: 8, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xe9, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegSI/scale=1/offset=2147483647", baseReg: RegR9, indexReg: RegSI, scale: 1, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x31, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegSI/scale=2/offset=2147483647", baseReg: RegR9, indexReg: RegSI, scale: 2, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x71, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegSI/scale=4/offset=2147483647", baseReg: RegR9, indexReg: RegSI, scale: 4, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xb1, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegSI/scale=8/offset=2147483647", baseReg: RegR9, indexReg: RegSI, scale: 8, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xf1, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegDI/scale=1/offset=2147483647", baseReg: RegR9, indexReg: RegDI, scale: 1, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x39, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegDI/scale=2/offset=2147483647", baseReg: RegR9, indexReg: RegDI, scale: 2, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x79, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegDI/scale=4/offset=2147483647", baseReg: RegR9, indexReg: RegDI, scale: 4, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xb9, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegDI/scale=8/offset=2147483647", baseReg: RegR9, indexReg: RegDI, scale: 8, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xf9, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegR8/scale=1/offset=2147483647", baseReg: RegR9, indexReg: RegR8, scale: 1, offset: 2147483647, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0x1, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegR8/scale=2/offset=2147483647", baseReg: RegR9, indexReg: RegR8, scale: 2, offset: 2147483647, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0x41, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegR8/scale=4/offset=2147483647", baseReg: RegR9, indexReg: RegR8, scale: 4, offset: 2147483647, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0x81, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegR8/scale=8/offset=2147483647", baseReg: RegR9, indexReg: RegR8, scale: 8, offset: 2147483647, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0xc1, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegR14/scale=1/offset=2147483647", baseReg: RegR9, indexReg: RegR14, scale: 1, offset: 2147483647, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0x31, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegR14/scale=2/offset=2147483647", baseReg: RegR9, indexReg: RegR14, scale: 2, offset: 2147483647, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0x71, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegR14/scale=4/offset=2147483647", baseReg: RegR9, indexReg: RegR14, scale: 4, offset: 2147483647, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0xb1, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegR14/scale=8/offset=2147483647", baseReg: RegR9, indexReg: RegR14, scale: 8, offset: 2147483647, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0xf1, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=Nil/scale=1/offset=2147483647", baseReg: RegR9, indexReg: asm.NilRegister, scale: 1, offset: 2147483647, expRex: 0x41, expModRM: 0x81, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=Nil/scale=2/offset=2147483647", baseReg: RegR9, indexReg: asm.NilRegister, scale: 2, offset: 2147483647, expRex: 0x41, expModRM: 0x81, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=Nil/scale=4/offset=2147483647", baseReg: RegR9, indexReg: asm.NilRegister, scale: 4, offset: 2147483647, expRex: 0x41, expModRM: 0x81, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=Nil/scale=8/offset=2147483647", baseReg: RegR9, indexReg: asm.NilRegister, scale: 8, offset: 2147483647, expRex: 0x41, expModRM: 0x81, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegAX/scale=1/offset=-2147483648", baseReg: RegR9, indexReg: RegAX, scale: 1, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x1, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegAX/scale=2/offset=-2147483648", baseReg: RegR9, indexReg: RegAX, scale: 2, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x41, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegAX/scale=4/offset=-2147483648", baseReg: RegR9, indexReg: RegAX, scale: 4, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x81, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegAX/scale=8/offset=-2147483648", baseReg: RegR9, indexReg: RegAX, scale: 8, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xc1, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegBX/scale=1/offset=-2147483648", baseReg: RegR9, indexReg: RegBX, scale: 1, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x19, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegBX/scale=2/offset=-2147483648", baseReg: RegR9, indexReg: RegBX, scale: 2, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x59, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegBX/scale=4/offset=-2147483648", baseReg: RegR9, indexReg: RegBX, scale: 4, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x99, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegBX/scale=8/offset=-2147483648", baseReg: RegR9, indexReg: RegBX, scale: 8, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xd9, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegBP/scale=1/offset=-2147483648", baseReg: RegR9, indexReg: RegBP, scale: 1, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x29, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegBP/scale=2/offset=-2147483648", baseReg: RegR9, indexReg: RegBP, scale: 2, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x69, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegBP/scale=4/offset=-2147483648", baseReg: RegR9, indexReg: RegBP, scale: 4, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xa9, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegBP/scale=8/offset=-2147483648", baseReg: RegR9, indexReg: RegBP, scale: 8, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xe9, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegSI/scale=1/offset=-2147483648", baseReg: RegR9, indexReg: RegSI, scale: 1, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x31, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegSI/scale=2/offset=-2147483648", baseReg: RegR9, indexReg: RegSI, scale: 2, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x71, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegSI/scale=4/offset=-2147483648", baseReg: RegR9, indexReg: RegSI, scale: 4, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xb1, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegSI/scale=8/offset=-2147483648", baseReg: RegR9, indexReg: RegSI, scale: 8, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xf1, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegDI/scale=1/offset=-2147483648", baseReg: RegR9, indexReg: RegDI, scale: 1, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x39, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegDI/scale=2/offset=-2147483648", baseReg: RegR9, indexReg: RegDI, scale: 2, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x79, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegDI/scale=4/offset=-2147483648", baseReg: RegR9, indexReg: RegDI, scale: 4, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xb9, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegDI/scale=8/offset=-2147483648", baseReg: RegR9, indexReg: RegDI, scale: 8, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xf9, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegR8/scale=1/offset=-2147483648", baseReg: RegR9, indexReg: RegR8, scale: 1, offset: -2147483648, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0x1, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegR8/scale=2/offset=-2147483648", baseReg: RegR9, indexReg: RegR8, scale: 2, offset: -2147483648, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0x41, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegR8/scale=4/offset=-2147483648", baseReg: RegR9, indexReg: RegR8, scale: 4, offset: -2147483648, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0x81, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegR8/scale=8/offset=-2147483648", baseReg: RegR9, indexReg: RegR8, scale: 8, offset: -2147483648, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0xc1, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegR14/scale=1/offset=-2147483648", baseReg: RegR9, indexReg: RegR14, scale: 1, offset: -2147483648, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0x31, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegR14/scale=2/offset=-2147483648", baseReg: RegR9, indexReg: RegR14, scale: 2, offset: -2147483648, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0x71, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegR14/scale=4/offset=-2147483648", baseReg: RegR9, indexReg: RegR14, scale: 4, offset: -2147483648, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0xb1, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=RegR14/scale=8/offset=-2147483648", baseReg: RegR9, indexReg: RegR14, scale: 8, offset: -2147483648, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0xf1, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=Nil/scale=1/offset=-2147483648", baseReg: RegR9, indexReg: asm.NilRegister, scale: 1, offset: -2147483648, expRex: 0x41, expModRM: 0x81, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=Nil/scale=2/offset=-2147483648", baseReg: RegR9, indexReg: asm.NilRegister, scale: 2, offset: -2147483648, expRex: 0x41, expModRM: 0x81, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=Nil/scale=4/offset=-2147483648", baseReg: RegR9, indexReg: asm.NilRegister, scale: 4, offset: -2147483648, expRex: 0x41, expModRM: 0x81, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegR9/indexReg=Nil/scale=8/offset=-2147483648", baseReg: RegR9, indexReg: asm.NilRegister, scale: 8, offset: -2147483648, expRex: 0x41, expModRM: 0x81, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegAX/scale=1/offset=0", baseReg: RegR13, indexReg: RegAX, scale: 1, offset: 0, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x5, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegAX/scale=2/offset=0", baseReg: RegR13, indexReg: RegAX, scale: 2, offset: 0, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x45, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegAX/scale=4/offset=0", baseReg: RegR13, indexReg: RegAX, scale: 4, offset: 0, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x85, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegAX/scale=8/offset=0", baseReg: RegR13, indexReg: RegAX, scale: 8, offset: 0, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xc5, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegBX/scale=1/offset=0", baseReg: RegR13, indexReg: RegBX, scale: 1, offset: 0, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x1d, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegBX/scale=2/offset=0", baseReg: RegR13, indexReg: RegBX, scale: 2, offset: 0, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x5d, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegBX/scale=4/offset=0", baseReg: RegR13, indexReg: RegBX, scale: 4, offset: 0, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x9d, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegBX/scale=8/offset=0", baseReg: RegR13, indexReg: RegBX, scale: 8, offset: 0, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xdd, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegBP/scale=1/offset=0", baseReg: RegR13, indexReg: RegBP, scale: 1, offset: 0, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x2d, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegBP/scale=2/offset=0", baseReg: RegR13, indexReg: RegBP, scale: 2, offset: 0, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x6d, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegBP/scale=4/offset=0", baseReg: RegR13, indexReg: RegBP, scale: 4, offset: 0, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xad, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegBP/scale=8/offset=0", baseReg: RegR13, indexReg: RegBP, scale: 8, offset: 0, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xed, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegSI/scale=1/offset=0", baseReg: RegR13, indexReg: RegSI, scale: 1, offset: 0, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x35, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegSI/scale=2/offset=0", baseReg: RegR13, indexReg: RegSI, scale: 2, offset: 0, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x75, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegSI/scale=4/offset=0", baseReg: RegR13, indexReg: RegSI, scale: 4, offset: 0, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xb5, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegSI/scale=8/offset=0", baseReg: RegR13, indexReg: RegSI, scale: 8, offset: 0, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xf5, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegDI/scale=1/offset=0", baseReg: RegR13, indexReg: RegDI, scale: 1, offset: 0, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x3d, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegDI/scale=2/offset=0", baseReg: RegR13, indexReg: RegDI, scale: 2, offset: 0, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x7d, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegDI/scale=4/offset=0", baseReg: RegR13, indexReg: RegDI, scale: 4, offset: 0, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xbd, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegDI/scale=8/offset=0", baseReg: RegR13, indexReg: RegDI, scale: 8, offset: 0, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xfd, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegR8/scale=1/offset=0", baseReg: RegR13, indexReg: RegR8, scale: 1, offset: 0, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0x5, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegR8/scale=2/offset=0", baseReg: RegR13, indexReg: RegR8, scale: 2, offset: 0, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0x45, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegR8/scale=4/offset=0", baseReg: RegR13, indexReg: RegR8, scale: 4, offset: 0, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0x85, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegR8/scale=8/offset=0", baseReg: RegR13, indexReg: RegR8, scale: 8, offset: 0, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0xc5, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegR14/scale=1/offset=0", baseReg: RegR13, indexReg: RegR14, scale: 1, offset: 0, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0x35, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegR14/scale=2/offset=0", baseReg: RegR13, indexReg: RegR14, scale: 2, offset: 0, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0x75, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegR14/scale=4/offset=0", baseReg: RegR13, indexReg: RegR14, scale: 4, offset: 0, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0xb5, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegR14/scale=8/offset=0", baseReg: RegR13, indexReg: RegR14, scale: 8, offset: 0, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0xf5, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=Nil/scale=1/offset=0", baseReg: RegR13, indexReg: asm.NilRegister, scale: 1, offset: 0, expRex: 0x41, expModRM: 0x45, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=Nil/scale=2/offset=0", baseReg: RegR13, indexReg: asm.NilRegister, scale: 2, offset: 0, expRex: 0x41, expModRM: 0x45, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=Nil/scale=4/offset=0", baseReg: RegR13, indexReg: asm.NilRegister, scale: 4, offset: 0, expRex: 0x41, expModRM: 0x45, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=Nil/scale=8/offset=0", baseReg: RegR13, indexReg: asm.NilRegister, scale: 8, offset: 0, expRex: 0x41, expModRM: 0x45, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegAX/scale=1/offset=1", baseReg: RegR13, indexReg: RegAX, scale: 1, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x5, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegAX/scale=2/offset=1", baseReg: RegR13, indexReg: RegAX, scale: 2, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x45, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegAX/scale=4/offset=1", baseReg: RegR13, indexReg: RegAX, scale: 4, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x85, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegAX/scale=8/offset=1", baseReg: RegR13, indexReg: RegAX, scale: 8, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xc5, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegBX/scale=1/offset=1", baseReg: RegR13, indexReg: RegBX, scale: 1, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x1d, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegBX/scale=2/offset=1", baseReg: RegR13, indexReg: RegBX, scale: 2, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x5d, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegBX/scale=4/offset=1", baseReg: RegR13, indexReg: RegBX, scale: 4, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x9d, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegBX/scale=8/offset=1", baseReg: RegR13, indexReg: RegBX, scale: 8, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xdd, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegBP/scale=1/offset=1", baseReg: RegR13, indexReg: RegBP, scale: 1, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x2d, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegBP/scale=2/offset=1", baseReg: RegR13, indexReg: RegBP, scale: 2, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x6d, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegBP/scale=4/offset=1", baseReg: RegR13, indexReg: RegBP, scale: 4, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xad, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegBP/scale=8/offset=1", baseReg: RegR13, indexReg: RegBP, scale: 8, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xed, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegSI/scale=1/offset=1", baseReg: RegR13, indexReg: RegSI, scale: 1, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x35, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegSI/scale=2/offset=1", baseReg: RegR13, indexReg: RegSI, scale: 2, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x75, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegSI/scale=4/offset=1", baseReg: RegR13, indexReg: RegSI, scale: 4, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xb5, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegSI/scale=8/offset=1", baseReg: RegR13, indexReg: RegSI, scale: 8, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xf5, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegDI/scale=1/offset=1", baseReg: RegR13, indexReg: RegDI, scale: 1, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x3d, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegDI/scale=2/offset=1", baseReg: RegR13, indexReg: RegDI, scale: 2, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x7d, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegDI/scale=4/offset=1", baseReg: RegR13, indexReg: RegDI, scale: 4, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xbd, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegDI/scale=8/offset=1", baseReg: RegR13, indexReg: RegDI, scale: 8, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xfd, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegR8/scale=1/offset=1", baseReg: RegR13, indexReg: RegR8, scale: 1, offset: 1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0x5, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegR8/scale=2/offset=1", baseReg: RegR13, indexReg: RegR8, scale: 2, offset: 1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0x45, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegR8/scale=4/offset=1", baseReg: RegR13, indexReg: RegR8, scale: 4, offset: 1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0x85, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegR8/scale=8/offset=1", baseReg: RegR13, indexReg: RegR8, scale: 8, offset: 1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0xc5, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegR14/scale=1/offset=1", baseReg: RegR13, indexReg: RegR14, scale: 1, offset: 1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0x35, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegR14/scale=2/offset=1", baseReg: RegR13, indexReg: RegR14, scale: 2, offset: 1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0x75, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegR14/scale=4/offset=1", baseReg: RegR13, indexReg: RegR14, scale: 4, offset: 1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0xb5, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegR14/scale=8/offset=1", baseReg: RegR13, indexReg: RegR14, scale: 8, offset: 1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0xf5, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=Nil/scale=1/offset=1", baseReg: RegR13, indexReg: asm.NilRegister, scale: 1, offset: 1, expRex: 0x41, expModRM: 0x45, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=Nil/scale=2/offset=1", baseReg: RegR13, indexReg: asm.NilRegister, scale: 2, offset: 1, expRex: 0x41, expModRM: 0x45, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=Nil/scale=4/offset=1", baseReg: RegR13, indexReg: asm.NilRegister, scale: 4, offset: 1, expRex: 0x41, expModRM: 0x45, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=Nil/scale=8/offset=1", baseReg: RegR13, indexReg: asm.NilRegister, scale: 8, offset: 1, expRex: 0x41, expModRM: 0x45, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegAX/scale=1/offset=-1", baseReg: RegR13, indexReg: RegAX, scale: 1, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x5, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegAX/scale=2/offset=-1", baseReg: RegR13, indexReg: RegAX, scale: 2, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x45, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegAX/scale=4/offset=-1", baseReg: RegR13, indexReg: RegAX, scale: 4, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x85, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegAX/scale=8/offset=-1", baseReg: RegR13, indexReg: RegAX, scale: 8, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xc5, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegBX/scale=1/offset=-1", baseReg: RegR13, indexReg: RegBX, scale: 1, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x1d, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegBX/scale=2/offset=-1", baseReg: RegR13, indexReg: RegBX, scale: 2, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x5d, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegBX/scale=4/offset=-1", baseReg: RegR13, indexReg: RegBX, scale: 4, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x9d, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegBX/scale=8/offset=-1", baseReg: RegR13, indexReg: RegBX, scale: 8, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xdd, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegBP/scale=1/offset=-1", baseReg: RegR13, indexReg: RegBP, scale: 1, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x2d, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegBP/scale=2/offset=-1", baseReg: RegR13, indexReg: RegBP, scale: 2, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x6d, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegBP/scale=4/offset=-1", baseReg: RegR13, indexReg: RegBP, scale: 4, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xad, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegBP/scale=8/offset=-1", baseReg: RegR13, indexReg: RegBP, scale: 8, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xed, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegSI/scale=1/offset=-1", baseReg: RegR13, indexReg: RegSI, scale: 1, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x35, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegSI/scale=2/offset=-1", baseReg: RegR13, indexReg: RegSI, scale: 2, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x75, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegSI/scale=4/offset=-1", baseReg: RegR13, indexReg: RegSI, scale: 4, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xb5, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegSI/scale=8/offset=-1", baseReg: RegR13, indexReg: RegSI, scale: 8, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xf5, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegDI/scale=1/offset=-1", baseReg: RegR13, indexReg: RegDI, scale: 1, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x3d, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegDI/scale=2/offset=-1", baseReg: RegR13, indexReg: RegDI, scale: 2, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x7d, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegDI/scale=4/offset=-1", baseReg: RegR13, indexReg: RegDI, scale: 4, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xbd, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegDI/scale=8/offset=-1", baseReg: RegR13, indexReg: RegDI, scale: 8, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xfd, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegR8/scale=1/offset=-1", baseReg: RegR13, indexReg: RegR8, scale: 1, offset: -1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0x5, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegR8/scale=2/offset=-1", baseReg: RegR13, indexReg: RegR8, scale: 2, offset: -1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0x45, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegR8/scale=4/offset=-1", baseReg: RegR13, indexReg: RegR8, scale: 4, offset: -1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0x85, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegR8/scale=8/offset=-1", baseReg: RegR13, indexReg: RegR8, scale: 8, offset: -1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0xc5, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegR14/scale=1/offset=-1", baseReg: RegR13, indexReg: RegR14, scale: 1, offset: -1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0x35, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegR14/scale=2/offset=-1", baseReg: RegR13, indexReg: RegR14, scale: 2, offset: -1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0x75, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegR14/scale=4/offset=-1", baseReg: RegR13, indexReg: RegR14, scale: 4, offset: -1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0xb5, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegR14/scale=8/offset=-1", baseReg: RegR13, indexReg: RegR14, scale: 8, offset: -1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0xf5, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=Nil/scale=1/offset=-1", baseReg: RegR13, indexReg: asm.NilRegister, scale: 1, offset: -1, expRex: 0x41, expModRM: 0x45, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=Nil/scale=2/offset=-1", baseReg: RegR13, indexReg: asm.NilRegister, scale: 2, offset: -1, expRex: 0x41, expModRM: 0x45, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=Nil/scale=4/offset=-1", baseReg: RegR13, indexReg: asm.NilRegister, scale: 4, offset: -1, expRex: 0x41, expModRM: 0x45, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=Nil/scale=8/offset=-1", baseReg: RegR13, indexReg: asm.NilRegister, scale: 8, offset: -1, expRex: 0x41, expModRM: 0x45, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegR13/indexReg=RegAX/scale=1/offset=2147483647", baseReg: RegR13, indexReg: RegAX, scale: 1, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x5, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegAX/scale=2/offset=2147483647", baseReg: RegR13, indexReg: RegAX, scale: 2, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x45, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegAX/scale=4/offset=2147483647", baseReg: RegR13, indexReg: RegAX, scale: 4, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x85, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegAX/scale=8/offset=2147483647", baseReg: RegR13, indexReg: RegAX, scale: 8, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xc5, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegBX/scale=1/offset=2147483647", baseReg: RegR13, indexReg: RegBX, scale: 1, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x1d, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegBX/scale=2/offset=2147483647", baseReg: RegR13, indexReg: RegBX, scale: 2, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x5d, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegBX/scale=4/offset=2147483647", baseReg: RegR13, indexReg: RegBX, scale: 4, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x9d, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegBX/scale=8/offset=2147483647", baseReg: RegR13, indexReg: RegBX, scale: 8, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xdd, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegBP/scale=1/offset=2147483647", baseReg: RegR13, indexReg: RegBP, scale: 1, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x2d, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegBP/scale=2/offset=2147483647", baseReg: RegR13, indexReg: RegBP, scale: 2, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x6d, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegBP/scale=4/offset=2147483647", baseReg: RegR13, indexReg: RegBP, scale: 4, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xad, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegBP/scale=8/offset=2147483647", baseReg: RegR13, indexReg: RegBP, scale: 8, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xed, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegSI/scale=1/offset=2147483647", baseReg: RegR13, indexReg: RegSI, scale: 1, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x35, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegSI/scale=2/offset=2147483647", baseReg: RegR13, indexReg: RegSI, scale: 2, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x75, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegSI/scale=4/offset=2147483647", baseReg: RegR13, indexReg: RegSI, scale: 4, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xb5, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegSI/scale=8/offset=2147483647", baseReg: RegR13, indexReg: RegSI, scale: 8, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xf5, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegDI/scale=1/offset=2147483647", baseReg: RegR13, indexReg: RegDI, scale: 1, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x3d, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegDI/scale=2/offset=2147483647", baseReg: RegR13, indexReg: RegDI, scale: 2, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x7d, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegDI/scale=4/offset=2147483647", baseReg: RegR13, indexReg: RegDI, scale: 4, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xbd, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegDI/scale=8/offset=2147483647", baseReg: RegR13, indexReg: RegDI, scale: 8, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xfd, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegR8/scale=1/offset=2147483647", baseReg: RegR13, indexReg: RegR8, scale: 1, offset: 2147483647, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0x5, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegR8/scale=2/offset=2147483647", baseReg: RegR13, indexReg: RegR8, scale: 2, offset: 2147483647, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0x45, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegR8/scale=4/offset=2147483647", baseReg: RegR13, indexReg: RegR8, scale: 4, offset: 2147483647, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0x85, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegR8/scale=8/offset=2147483647", baseReg: RegR13, indexReg: RegR8, scale: 8, offset: 2147483647, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0xc5, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegR14/scale=1/offset=2147483647", baseReg: RegR13, indexReg: RegR14, scale: 1, offset: 2147483647, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0x35, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegR14/scale=2/offset=2147483647", baseReg: RegR13, indexReg: RegR14, scale: 2, offset: 2147483647, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0x75, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegR14/scale=4/offset=2147483647", baseReg: RegR13, indexReg: RegR14, scale: 4, offset: 2147483647, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0xb5, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegR14/scale=8/offset=2147483647", baseReg: RegR13, indexReg: RegR14, scale: 8, offset: 2147483647, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0xf5, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=Nil/scale=1/offset=2147483647", baseReg: RegR13, indexReg: asm.NilRegister, scale: 1, offset: 2147483647, expRex: 0x41, expModRM: 0x85, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=Nil/scale=2/offset=2147483647", baseReg: RegR13, indexReg: asm.NilRegister, scale: 2, offset: 2147483647, expRex: 0x41, expModRM: 0x85, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=Nil/scale=4/offset=2147483647", baseReg: RegR13, indexReg: asm.NilRegister, scale: 4, offset: 2147483647, expRex: 0x41, expModRM: 0x85, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=Nil/scale=8/offset=2147483647", baseReg: RegR13, indexReg: asm.NilRegister, scale: 8, offset: 2147483647, expRex: 0x41, expModRM: 0x85, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegAX/scale=1/offset=-2147483648", baseReg: RegR13, indexReg: RegAX, scale: 1, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x5, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegAX/scale=2/offset=-2147483648", baseReg: RegR13, indexReg: RegAX, scale: 2, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x45, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegAX/scale=4/offset=-2147483648", baseReg: RegR13, indexReg: RegAX, scale: 4, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x85, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegAX/scale=8/offset=-2147483648", baseReg: RegR13, indexReg: RegAX, scale: 8, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xc5, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegBX/scale=1/offset=-2147483648", baseReg: RegR13, indexReg: RegBX, scale: 1, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x1d, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegBX/scale=2/offset=-2147483648", baseReg: RegR13, indexReg: RegBX, scale: 2, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x5d, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegBX/scale=4/offset=-2147483648", baseReg: RegR13, indexReg: RegBX, scale: 4, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x9d, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegBX/scale=8/offset=-2147483648", baseReg: RegR13, indexReg: RegBX, scale: 8, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xdd, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegBP/scale=1/offset=-2147483648", baseReg: RegR13, indexReg: RegBP, scale: 1, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x2d, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegBP/scale=2/offset=-2147483648", baseReg: RegR13, indexReg: RegBP, scale: 2, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x6d, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegBP/scale=4/offset=-2147483648", baseReg: RegR13, indexReg: RegBP, scale: 4, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xad, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegBP/scale=8/offset=-2147483648", baseReg: RegR13, indexReg: RegBP, scale: 8, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xed, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegSI/scale=1/offset=-2147483648", baseReg: RegR13, indexReg: RegSI, scale: 1, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x35, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegSI/scale=2/offset=-2147483648", baseReg: RegR13, indexReg: RegSI, scale: 2, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x75, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegSI/scale=4/offset=-2147483648", baseReg: RegR13, indexReg: RegSI, scale: 4, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xb5, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegSI/scale=8/offset=-2147483648", baseReg: RegR13, indexReg: RegSI, scale: 8, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xf5, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegDI/scale=1/offset=-2147483648", baseReg: RegR13, indexReg: RegDI, scale: 1, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x3d, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegDI/scale=2/offset=-2147483648", baseReg: RegR13, indexReg: RegDI, scale: 2, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x7d, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegDI/scale=4/offset=-2147483648", baseReg: RegR13, indexReg: RegDI, scale: 4, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xbd, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegDI/scale=8/offset=-2147483648", baseReg: RegR13, indexReg: RegDI, scale: 8, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xfd, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegR8/scale=1/offset=-2147483648", baseReg: RegR13, indexReg: RegR8, scale: 1, offset: -2147483648, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0x5, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegR8/scale=2/offset=-2147483648", baseReg: RegR13, indexReg: RegR8, scale: 2, offset: -2147483648, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0x45, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegR8/scale=4/offset=-2147483648", baseReg: RegR13, indexReg: RegR8, scale: 4, offset: -2147483648, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0x85, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegR8/scale=8/offset=-2147483648", baseReg: RegR13, indexReg: RegR8, scale: 8, offset: -2147483648, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0xc5, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegR14/scale=1/offset=-2147483648", baseReg: RegR13, indexReg: RegR14, scale: 1, offset: -2147483648, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0x35, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegR14/scale=2/offset=-2147483648", baseReg: RegR13, indexReg: RegR14, scale: 2, offset: -2147483648, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0x75, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegR14/scale=4/offset=-2147483648", baseReg: RegR13, indexReg: RegR14, scale: 4, offset: -2147483648, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0xb5, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=RegR14/scale=8/offset=-2147483648", baseReg: RegR13, indexReg: RegR14, scale: 8, offset: -2147483648, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0xf5, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=Nil/scale=1/offset=-2147483648", baseReg: RegR13, indexReg: asm.NilRegister, scale: 1, offset: -2147483648, expRex: 0x41, expModRM: 0x85, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=Nil/scale=2/offset=-2147483648", baseReg: RegR13, indexReg: asm.NilRegister, scale: 2, offset: -2147483648, expRex: 0x41, expModRM: 0x85, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=Nil/scale=4/offset=-2147483648", baseReg: RegR13, indexReg: asm.NilRegister, scale: 4, offset: -2147483648, expRex: 0x41, expModRM: 0x85, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegR13/indexReg=Nil/scale=8/offset=-2147483648", baseReg: RegR13, indexReg: asm.NilRegister, scale: 8, offset: -2147483648, expRex: 0x41, expModRM: 0x85, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegAX/scale=1/offset=0", baseReg: RegR15, indexReg: RegAX, scale: 1, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0x7, displacementWidth: 0}, - {name: "baseReg=RegR15/indexReg=RegAX/scale=2/offset=0", baseReg: RegR15, indexReg: RegAX, scale: 2, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0x47, displacementWidth: 0}, - {name: "baseReg=RegR15/indexReg=RegAX/scale=4/offset=0", baseReg: RegR15, indexReg: RegAX, scale: 4, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0x87, displacementWidth: 0}, - {name: "baseReg=RegR15/indexReg=RegAX/scale=8/offset=0", baseReg: RegR15, indexReg: RegAX, scale: 8, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0xc7, displacementWidth: 0}, - {name: "baseReg=RegR15/indexReg=RegBX/scale=1/offset=0", baseReg: RegR15, indexReg: RegBX, scale: 1, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0x1f, displacementWidth: 0}, - {name: "baseReg=RegR15/indexReg=RegBX/scale=2/offset=0", baseReg: RegR15, indexReg: RegBX, scale: 2, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0x5f, displacementWidth: 0}, - {name: "baseReg=RegR15/indexReg=RegBX/scale=4/offset=0", baseReg: RegR15, indexReg: RegBX, scale: 4, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0x9f, displacementWidth: 0}, - {name: "baseReg=RegR15/indexReg=RegBX/scale=8/offset=0", baseReg: RegR15, indexReg: RegBX, scale: 8, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0xdf, displacementWidth: 0}, - {name: "baseReg=RegR15/indexReg=RegBP/scale=1/offset=0", baseReg: RegR15, indexReg: RegBP, scale: 1, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0x2f, displacementWidth: 0}, - {name: "baseReg=RegR15/indexReg=RegBP/scale=2/offset=0", baseReg: RegR15, indexReg: RegBP, scale: 2, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0x6f, displacementWidth: 0}, - {name: "baseReg=RegR15/indexReg=RegBP/scale=4/offset=0", baseReg: RegR15, indexReg: RegBP, scale: 4, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0xaf, displacementWidth: 0}, - {name: "baseReg=RegR15/indexReg=RegBP/scale=8/offset=0", baseReg: RegR15, indexReg: RegBP, scale: 8, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0xef, displacementWidth: 0}, - {name: "baseReg=RegR15/indexReg=RegSI/scale=1/offset=0", baseReg: RegR15, indexReg: RegSI, scale: 1, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0x37, displacementWidth: 0}, - {name: "baseReg=RegR15/indexReg=RegSI/scale=2/offset=0", baseReg: RegR15, indexReg: RegSI, scale: 2, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0x77, displacementWidth: 0}, - {name: "baseReg=RegR15/indexReg=RegSI/scale=4/offset=0", baseReg: RegR15, indexReg: RegSI, scale: 4, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0xb7, displacementWidth: 0}, - {name: "baseReg=RegR15/indexReg=RegSI/scale=8/offset=0", baseReg: RegR15, indexReg: RegSI, scale: 8, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0xf7, displacementWidth: 0}, - {name: "baseReg=RegR15/indexReg=RegDI/scale=1/offset=0", baseReg: RegR15, indexReg: RegDI, scale: 1, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0x3f, displacementWidth: 0}, - {name: "baseReg=RegR15/indexReg=RegDI/scale=2/offset=0", baseReg: RegR15, indexReg: RegDI, scale: 2, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0x7f, displacementWidth: 0}, - {name: "baseReg=RegR15/indexReg=RegDI/scale=4/offset=0", baseReg: RegR15, indexReg: RegDI, scale: 4, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0xbf, displacementWidth: 0}, - {name: "baseReg=RegR15/indexReg=RegDI/scale=8/offset=0", baseReg: RegR15, indexReg: RegDI, scale: 8, offset: 0, expRex: 0x41, expModRM: 0x4, needSBI: true, expSBI: 0xff, displacementWidth: 0}, - {name: "baseReg=RegR15/indexReg=RegR8/scale=1/offset=0", baseReg: RegR15, indexReg: RegR8, scale: 1, offset: 0, expRex: 0x43, expModRM: 0x4, needSBI: true, expSBI: 0x7, displacementWidth: 0}, - {name: "baseReg=RegR15/indexReg=RegR8/scale=2/offset=0", baseReg: RegR15, indexReg: RegR8, scale: 2, offset: 0, expRex: 0x43, expModRM: 0x4, needSBI: true, expSBI: 0x47, displacementWidth: 0}, - {name: "baseReg=RegR15/indexReg=RegR8/scale=4/offset=0", baseReg: RegR15, indexReg: RegR8, scale: 4, offset: 0, expRex: 0x43, expModRM: 0x4, needSBI: true, expSBI: 0x87, displacementWidth: 0}, - {name: "baseReg=RegR15/indexReg=RegR8/scale=8/offset=0", baseReg: RegR15, indexReg: RegR8, scale: 8, offset: 0, expRex: 0x43, expModRM: 0x4, needSBI: true, expSBI: 0xc7, displacementWidth: 0}, - {name: "baseReg=RegR15/indexReg=RegR14/scale=1/offset=0", baseReg: RegR15, indexReg: RegR14, scale: 1, offset: 0, expRex: 0x43, expModRM: 0x4, needSBI: true, expSBI: 0x37, displacementWidth: 0}, - {name: "baseReg=RegR15/indexReg=RegR14/scale=2/offset=0", baseReg: RegR15, indexReg: RegR14, scale: 2, offset: 0, expRex: 0x43, expModRM: 0x4, needSBI: true, expSBI: 0x77, displacementWidth: 0}, - {name: "baseReg=RegR15/indexReg=RegR14/scale=4/offset=0", baseReg: RegR15, indexReg: RegR14, scale: 4, offset: 0, expRex: 0x43, expModRM: 0x4, needSBI: true, expSBI: 0xb7, displacementWidth: 0}, - {name: "baseReg=RegR15/indexReg=RegR14/scale=8/offset=0", baseReg: RegR15, indexReg: RegR14, scale: 8, offset: 0, expRex: 0x43, expModRM: 0x4, needSBI: true, expSBI: 0xf7, displacementWidth: 0}, - {name: "baseReg=RegR15/indexReg=Nil/scale=1/offset=0", baseReg: RegR15, indexReg: asm.NilRegister, scale: 1, offset: 0, expRex: 0x41, expModRM: 0x7, needSBI: false, displacementWidth: 0}, - {name: "baseReg=RegR15/indexReg=Nil/scale=2/offset=0", baseReg: RegR15, indexReg: asm.NilRegister, scale: 2, offset: 0, expRex: 0x41, expModRM: 0x7, needSBI: false, displacementWidth: 0}, - {name: "baseReg=RegR15/indexReg=Nil/scale=4/offset=0", baseReg: RegR15, indexReg: asm.NilRegister, scale: 4, offset: 0, expRex: 0x41, expModRM: 0x7, needSBI: false, displacementWidth: 0}, - {name: "baseReg=RegR15/indexReg=Nil/scale=8/offset=0", baseReg: RegR15, indexReg: asm.NilRegister, scale: 8, offset: 0, expRex: 0x41, expModRM: 0x7, needSBI: false, displacementWidth: 0}, - {name: "baseReg=RegR15/indexReg=RegAX/scale=1/offset=1", baseReg: RegR15, indexReg: RegAX, scale: 1, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x7, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegAX/scale=2/offset=1", baseReg: RegR15, indexReg: RegAX, scale: 2, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x47, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegAX/scale=4/offset=1", baseReg: RegR15, indexReg: RegAX, scale: 4, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x87, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegAX/scale=8/offset=1", baseReg: RegR15, indexReg: RegAX, scale: 8, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xc7, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegBX/scale=1/offset=1", baseReg: RegR15, indexReg: RegBX, scale: 1, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x1f, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegBX/scale=2/offset=1", baseReg: RegR15, indexReg: RegBX, scale: 2, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x5f, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegBX/scale=4/offset=1", baseReg: RegR15, indexReg: RegBX, scale: 4, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x9f, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegBX/scale=8/offset=1", baseReg: RegR15, indexReg: RegBX, scale: 8, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xdf, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegBP/scale=1/offset=1", baseReg: RegR15, indexReg: RegBP, scale: 1, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x2f, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegBP/scale=2/offset=1", baseReg: RegR15, indexReg: RegBP, scale: 2, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x6f, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegBP/scale=4/offset=1", baseReg: RegR15, indexReg: RegBP, scale: 4, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xaf, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegBP/scale=8/offset=1", baseReg: RegR15, indexReg: RegBP, scale: 8, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xef, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegSI/scale=1/offset=1", baseReg: RegR15, indexReg: RegSI, scale: 1, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x37, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegSI/scale=2/offset=1", baseReg: RegR15, indexReg: RegSI, scale: 2, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x77, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegSI/scale=4/offset=1", baseReg: RegR15, indexReg: RegSI, scale: 4, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xb7, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegSI/scale=8/offset=1", baseReg: RegR15, indexReg: RegSI, scale: 8, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xf7, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegDI/scale=1/offset=1", baseReg: RegR15, indexReg: RegDI, scale: 1, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x3f, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegDI/scale=2/offset=1", baseReg: RegR15, indexReg: RegDI, scale: 2, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x7f, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegDI/scale=4/offset=1", baseReg: RegR15, indexReg: RegDI, scale: 4, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xbf, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegDI/scale=8/offset=1", baseReg: RegR15, indexReg: RegDI, scale: 8, offset: 1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xff, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegR8/scale=1/offset=1", baseReg: RegR15, indexReg: RegR8, scale: 1, offset: 1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0x7, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegR8/scale=2/offset=1", baseReg: RegR15, indexReg: RegR8, scale: 2, offset: 1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0x47, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegR8/scale=4/offset=1", baseReg: RegR15, indexReg: RegR8, scale: 4, offset: 1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0x87, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegR8/scale=8/offset=1", baseReg: RegR15, indexReg: RegR8, scale: 8, offset: 1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0xc7, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegR14/scale=1/offset=1", baseReg: RegR15, indexReg: RegR14, scale: 1, offset: 1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0x37, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegR14/scale=2/offset=1", baseReg: RegR15, indexReg: RegR14, scale: 2, offset: 1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0x77, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegR14/scale=4/offset=1", baseReg: RegR15, indexReg: RegR14, scale: 4, offset: 1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0xb7, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegR14/scale=8/offset=1", baseReg: RegR15, indexReg: RegR14, scale: 8, offset: 1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0xf7, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=Nil/scale=1/offset=1", baseReg: RegR15, indexReg: asm.NilRegister, scale: 1, offset: 1, expRex: 0x41, expModRM: 0x47, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=Nil/scale=2/offset=1", baseReg: RegR15, indexReg: asm.NilRegister, scale: 2, offset: 1, expRex: 0x41, expModRM: 0x47, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=Nil/scale=4/offset=1", baseReg: RegR15, indexReg: asm.NilRegister, scale: 4, offset: 1, expRex: 0x41, expModRM: 0x47, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=Nil/scale=8/offset=1", baseReg: RegR15, indexReg: asm.NilRegister, scale: 8, offset: 1, expRex: 0x41, expModRM: 0x47, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegAX/scale=1/offset=-1", baseReg: RegR15, indexReg: RegAX, scale: 1, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x7, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegAX/scale=2/offset=-1", baseReg: RegR15, indexReg: RegAX, scale: 2, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x47, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegAX/scale=4/offset=-1", baseReg: RegR15, indexReg: RegAX, scale: 4, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x87, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegAX/scale=8/offset=-1", baseReg: RegR15, indexReg: RegAX, scale: 8, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xc7, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegBX/scale=1/offset=-1", baseReg: RegR15, indexReg: RegBX, scale: 1, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x1f, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegBX/scale=2/offset=-1", baseReg: RegR15, indexReg: RegBX, scale: 2, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x5f, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegBX/scale=4/offset=-1", baseReg: RegR15, indexReg: RegBX, scale: 4, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x9f, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegBX/scale=8/offset=-1", baseReg: RegR15, indexReg: RegBX, scale: 8, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xdf, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegBP/scale=1/offset=-1", baseReg: RegR15, indexReg: RegBP, scale: 1, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x2f, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegBP/scale=2/offset=-1", baseReg: RegR15, indexReg: RegBP, scale: 2, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x6f, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegBP/scale=4/offset=-1", baseReg: RegR15, indexReg: RegBP, scale: 4, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xaf, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegBP/scale=8/offset=-1", baseReg: RegR15, indexReg: RegBP, scale: 8, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xef, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegSI/scale=1/offset=-1", baseReg: RegR15, indexReg: RegSI, scale: 1, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x37, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegSI/scale=2/offset=-1", baseReg: RegR15, indexReg: RegSI, scale: 2, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x77, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegSI/scale=4/offset=-1", baseReg: RegR15, indexReg: RegSI, scale: 4, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xb7, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegSI/scale=8/offset=-1", baseReg: RegR15, indexReg: RegSI, scale: 8, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xf7, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegDI/scale=1/offset=-1", baseReg: RegR15, indexReg: RegDI, scale: 1, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x3f, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegDI/scale=2/offset=-1", baseReg: RegR15, indexReg: RegDI, scale: 2, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0x7f, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegDI/scale=4/offset=-1", baseReg: RegR15, indexReg: RegDI, scale: 4, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xbf, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegDI/scale=8/offset=-1", baseReg: RegR15, indexReg: RegDI, scale: 8, offset: -1, expRex: 0x41, expModRM: 0x44, needSBI: true, expSBI: 0xff, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegR8/scale=1/offset=-1", baseReg: RegR15, indexReg: RegR8, scale: 1, offset: -1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0x7, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegR8/scale=2/offset=-1", baseReg: RegR15, indexReg: RegR8, scale: 2, offset: -1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0x47, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegR8/scale=4/offset=-1", baseReg: RegR15, indexReg: RegR8, scale: 4, offset: -1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0x87, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegR8/scale=8/offset=-1", baseReg: RegR15, indexReg: RegR8, scale: 8, offset: -1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0xc7, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegR14/scale=1/offset=-1", baseReg: RegR15, indexReg: RegR14, scale: 1, offset: -1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0x37, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegR14/scale=2/offset=-1", baseReg: RegR15, indexReg: RegR14, scale: 2, offset: -1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0x77, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegR14/scale=4/offset=-1", baseReg: RegR15, indexReg: RegR14, scale: 4, offset: -1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0xb7, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegR14/scale=8/offset=-1", baseReg: RegR15, indexReg: RegR14, scale: 8, offset: -1, expRex: 0x43, expModRM: 0x44, needSBI: true, expSBI: 0xf7, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=Nil/scale=1/offset=-1", baseReg: RegR15, indexReg: asm.NilRegister, scale: 1, offset: -1, expRex: 0x41, expModRM: 0x47, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=Nil/scale=2/offset=-1", baseReg: RegR15, indexReg: asm.NilRegister, scale: 2, offset: -1, expRex: 0x41, expModRM: 0x47, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=Nil/scale=4/offset=-1", baseReg: RegR15, indexReg: asm.NilRegister, scale: 4, offset: -1, expRex: 0x41, expModRM: 0x47, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=Nil/scale=8/offset=-1", baseReg: RegR15, indexReg: asm.NilRegister, scale: 8, offset: -1, expRex: 0x41, expModRM: 0x47, needSBI: false, displacementWidth: 8}, - {name: "baseReg=RegR15/indexReg=RegAX/scale=1/offset=2147483647", baseReg: RegR15, indexReg: RegAX, scale: 1, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x7, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegAX/scale=2/offset=2147483647", baseReg: RegR15, indexReg: RegAX, scale: 2, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x47, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegAX/scale=4/offset=2147483647", baseReg: RegR15, indexReg: RegAX, scale: 4, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x87, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegAX/scale=8/offset=2147483647", baseReg: RegR15, indexReg: RegAX, scale: 8, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xc7, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegBX/scale=1/offset=2147483647", baseReg: RegR15, indexReg: RegBX, scale: 1, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x1f, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegBX/scale=2/offset=2147483647", baseReg: RegR15, indexReg: RegBX, scale: 2, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x5f, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegBX/scale=4/offset=2147483647", baseReg: RegR15, indexReg: RegBX, scale: 4, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x9f, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegBX/scale=8/offset=2147483647", baseReg: RegR15, indexReg: RegBX, scale: 8, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xdf, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegBP/scale=1/offset=2147483647", baseReg: RegR15, indexReg: RegBP, scale: 1, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x2f, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegBP/scale=2/offset=2147483647", baseReg: RegR15, indexReg: RegBP, scale: 2, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x6f, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegBP/scale=4/offset=2147483647", baseReg: RegR15, indexReg: RegBP, scale: 4, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xaf, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegBP/scale=8/offset=2147483647", baseReg: RegR15, indexReg: RegBP, scale: 8, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xef, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegSI/scale=1/offset=2147483647", baseReg: RegR15, indexReg: RegSI, scale: 1, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x37, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegSI/scale=2/offset=2147483647", baseReg: RegR15, indexReg: RegSI, scale: 2, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x77, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegSI/scale=4/offset=2147483647", baseReg: RegR15, indexReg: RegSI, scale: 4, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xb7, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegSI/scale=8/offset=2147483647", baseReg: RegR15, indexReg: RegSI, scale: 8, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xf7, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegDI/scale=1/offset=2147483647", baseReg: RegR15, indexReg: RegDI, scale: 1, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x3f, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegDI/scale=2/offset=2147483647", baseReg: RegR15, indexReg: RegDI, scale: 2, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x7f, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegDI/scale=4/offset=2147483647", baseReg: RegR15, indexReg: RegDI, scale: 4, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xbf, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegDI/scale=8/offset=2147483647", baseReg: RegR15, indexReg: RegDI, scale: 8, offset: 2147483647, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xff, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegR8/scale=1/offset=2147483647", baseReg: RegR15, indexReg: RegR8, scale: 1, offset: 2147483647, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0x7, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegR8/scale=2/offset=2147483647", baseReg: RegR15, indexReg: RegR8, scale: 2, offset: 2147483647, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0x47, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegR8/scale=4/offset=2147483647", baseReg: RegR15, indexReg: RegR8, scale: 4, offset: 2147483647, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0x87, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegR8/scale=8/offset=2147483647", baseReg: RegR15, indexReg: RegR8, scale: 8, offset: 2147483647, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0xc7, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegR14/scale=1/offset=2147483647", baseReg: RegR15, indexReg: RegR14, scale: 1, offset: 2147483647, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0x37, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegR14/scale=2/offset=2147483647", baseReg: RegR15, indexReg: RegR14, scale: 2, offset: 2147483647, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0x77, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegR14/scale=4/offset=2147483647", baseReg: RegR15, indexReg: RegR14, scale: 4, offset: 2147483647, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0xb7, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegR14/scale=8/offset=2147483647", baseReg: RegR15, indexReg: RegR14, scale: 8, offset: 2147483647, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0xf7, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=Nil/scale=1/offset=2147483647", baseReg: RegR15, indexReg: asm.NilRegister, scale: 1, offset: 2147483647, expRex: 0x41, expModRM: 0x87, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=Nil/scale=2/offset=2147483647", baseReg: RegR15, indexReg: asm.NilRegister, scale: 2, offset: 2147483647, expRex: 0x41, expModRM: 0x87, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=Nil/scale=4/offset=2147483647", baseReg: RegR15, indexReg: asm.NilRegister, scale: 4, offset: 2147483647, expRex: 0x41, expModRM: 0x87, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=Nil/scale=8/offset=2147483647", baseReg: RegR15, indexReg: asm.NilRegister, scale: 8, offset: 2147483647, expRex: 0x41, expModRM: 0x87, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegAX/scale=1/offset=-2147483648", baseReg: RegR15, indexReg: RegAX, scale: 1, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x7, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegAX/scale=2/offset=-2147483648", baseReg: RegR15, indexReg: RegAX, scale: 2, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x47, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegAX/scale=4/offset=-2147483648", baseReg: RegR15, indexReg: RegAX, scale: 4, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x87, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegAX/scale=8/offset=-2147483648", baseReg: RegR15, indexReg: RegAX, scale: 8, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xc7, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegBX/scale=1/offset=-2147483648", baseReg: RegR15, indexReg: RegBX, scale: 1, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x1f, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegBX/scale=2/offset=-2147483648", baseReg: RegR15, indexReg: RegBX, scale: 2, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x5f, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegBX/scale=4/offset=-2147483648", baseReg: RegR15, indexReg: RegBX, scale: 4, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x9f, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegBX/scale=8/offset=-2147483648", baseReg: RegR15, indexReg: RegBX, scale: 8, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xdf, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegBP/scale=1/offset=-2147483648", baseReg: RegR15, indexReg: RegBP, scale: 1, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x2f, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegBP/scale=2/offset=-2147483648", baseReg: RegR15, indexReg: RegBP, scale: 2, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x6f, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegBP/scale=4/offset=-2147483648", baseReg: RegR15, indexReg: RegBP, scale: 4, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xaf, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegBP/scale=8/offset=-2147483648", baseReg: RegR15, indexReg: RegBP, scale: 8, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xef, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegSI/scale=1/offset=-2147483648", baseReg: RegR15, indexReg: RegSI, scale: 1, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x37, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegSI/scale=2/offset=-2147483648", baseReg: RegR15, indexReg: RegSI, scale: 2, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x77, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegSI/scale=4/offset=-2147483648", baseReg: RegR15, indexReg: RegSI, scale: 4, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xb7, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegSI/scale=8/offset=-2147483648", baseReg: RegR15, indexReg: RegSI, scale: 8, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xf7, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegDI/scale=1/offset=-2147483648", baseReg: RegR15, indexReg: RegDI, scale: 1, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x3f, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegDI/scale=2/offset=-2147483648", baseReg: RegR15, indexReg: RegDI, scale: 2, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0x7f, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegDI/scale=4/offset=-2147483648", baseReg: RegR15, indexReg: RegDI, scale: 4, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xbf, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegDI/scale=8/offset=-2147483648", baseReg: RegR15, indexReg: RegDI, scale: 8, offset: -2147483648, expRex: 0x41, expModRM: 0x84, needSBI: true, expSBI: 0xff, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegR8/scale=1/offset=-2147483648", baseReg: RegR15, indexReg: RegR8, scale: 1, offset: -2147483648, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0x7, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegR8/scale=2/offset=-2147483648", baseReg: RegR15, indexReg: RegR8, scale: 2, offset: -2147483648, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0x47, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegR8/scale=4/offset=-2147483648", baseReg: RegR15, indexReg: RegR8, scale: 4, offset: -2147483648, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0x87, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegR8/scale=8/offset=-2147483648", baseReg: RegR15, indexReg: RegR8, scale: 8, offset: -2147483648, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0xc7, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegR14/scale=1/offset=-2147483648", baseReg: RegR15, indexReg: RegR14, scale: 1, offset: -2147483648, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0x37, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegR14/scale=2/offset=-2147483648", baseReg: RegR15, indexReg: RegR14, scale: 2, offset: -2147483648, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0x77, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegR14/scale=4/offset=-2147483648", baseReg: RegR15, indexReg: RegR14, scale: 4, offset: -2147483648, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0xb7, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=RegR14/scale=8/offset=-2147483648", baseReg: RegR15, indexReg: RegR14, scale: 8, offset: -2147483648, expRex: 0x43, expModRM: 0x84, needSBI: true, expSBI: 0xf7, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=Nil/scale=1/offset=-2147483648", baseReg: RegR15, indexReg: asm.NilRegister, scale: 1, offset: -2147483648, expRex: 0x41, expModRM: 0x87, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=Nil/scale=2/offset=-2147483648", baseReg: RegR15, indexReg: asm.NilRegister, scale: 2, offset: -2147483648, expRex: 0x41, expModRM: 0x87, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=Nil/scale=4/offset=-2147483648", baseReg: RegR15, indexReg: asm.NilRegister, scale: 4, offset: -2147483648, expRex: 0x41, expModRM: 0x87, needSBI: false, displacementWidth: 32}, - {name: "baseReg=RegR15/indexReg=Nil/scale=8/offset=-2147483648", baseReg: RegR15, indexReg: asm.NilRegister, scale: 8, offset: -2147483648, expRex: 0x41, expModRM: 0x87, needSBI: false, displacementWidth: 32}, - } - for _, tc := range tests { - n := &nodeImpl{ - srcReg: tc.baseReg, srcConst: tc.offset, srcMemIndex: tc.indexReg, srcMemScale: tc.scale, - } - rexPrefix, modRM, sbi, sbiExist, displacementWidth, err := n.getMemoryLocation(false) - require.NoError(t, err, tc.name) - require.Equal(t, tc.expRex, rexPrefix, tc.name) - require.Equal(t, tc.expModRM, modRM, tc.name) - require.Equal(t, tc.needSBI, sbiExist) - if tc.needSBI { - require.Equal(t, tc.expSBI, sbi, tc.name) - } - require.Equal(t, tc.displacementWidth, displacementWidth, tc.name) - } -} diff --git a/internal/asm/amd64/impl_staticconst.go b/internal/asm/amd64/impl_staticconst.go deleted file mode 100644 index 17a7f228cf..0000000000 --- a/internal/asm/amd64/impl_staticconst.go +++ /dev/null @@ -1,181 +0,0 @@ -package amd64 - -import ( - "fmt" - "math" - - "github.com/tetratelabs/wazero/internal/asm" -) - -// defaultMaxDisplacementForConstantPool is the maximum displacement allowed for literal move instructions which access -// the constant pool. This is set as 2 ^30 conservatively while the actual limit is 2^31 since we actually allow this -// limit plus max(length(c) for c in the pool) so we must ensure that limit is less than 2^31. -const defaultMaxDisplacementForConstantPool = 1 << 30 - -func (a *AssemblerImpl) maybeFlushConstants(buf asm.Buffer, isEndOfFunction bool) { - if a.pool.Empty() { - return - } - - if isEndOfFunction || - // If the distance between (the first use in binary) and (end of constant pool) can be larger - // than MaxDisplacementForConstantPool, we have to emit the constant pool now, otherwise - // a const might be unreachable by a literal move whose maximum offset is +- 2^31. - ((a.pool.PoolSizeInBytes+buf.Len())-int(a.pool.FirstUseOffsetInBinary)) >= a.MaxDisplacementForConstantPool { - - if !isEndOfFunction { - // Adds the jump instruction to skip the constants if this is not the end of function. - // - // TODO: consider NOP padding for this jump, though this rarely happens as most functions should be - // small enough to fit all consts after the end of function. - if a.pool.PoolSizeInBytes >= math.MaxInt8-2 { - // long (near-relative) jump: https://www.felixcloutier.com/x86/jmp - buf.AppendByte(0xe9) - buf.AppendUint32(uint32(a.pool.PoolSizeInBytes)) - } else { - // short jump: https://www.felixcloutier.com/x86/jmp - buf.AppendByte(0xeb) - buf.AppendByte(byte(a.pool.PoolSizeInBytes)) - } - } - - for _, c := range a.pool.Consts { - c.SetOffsetInBinary(uint64(buf.Len())) - buf.AppendBytes(c.Raw) - } - - a.pool.Reset() - } -} - -func (a *AssemblerImpl) encodeRegisterToStaticConst(buf asm.Buffer, n *nodeImpl) (err error) { - var opc []byte - var rex byte - switch n.instruction { - case CMPL: - opc, rex = []byte{0x3b}, rexPrefixNone - case CMPQ: - opc, rex = []byte{0x3b}, rexPrefixW - default: - return errorEncodingUnsupported(n) - } - return a.encodeStaticConstImpl(buf, n, opc, rex, 0) -} - -var staticConstToRegisterOpcodes = [...]struct { - opcode, vopcode []byte - mandatoryPrefix, vmandatoryPrefix byte - rex rexPrefix -}{ - // https://www.felixcloutier.com/x86/movdqu:vmovdqu8:vmovdqu16:vmovdqu32:vmovdqu64 - MOVDQU: {mandatoryPrefix: 0xf3, opcode: []byte{0x0f, 0x6f}}, - // https://www.felixcloutier.com/x86/lea - LEAQ: {opcode: []byte{0x8d}, rex: rexPrefixW}, - // https://www.felixcloutier.com/x86/movupd - MOVUPD: {mandatoryPrefix: 0x66, opcode: []byte{0x0f, 0x10}}, - // https://www.felixcloutier.com/x86/mov - MOVL: {opcode: []byte{0x8b}, vopcode: []byte{0x0f, 0x6e}, vmandatoryPrefix: 0x66}, - MOVQ: {opcode: []byte{0x8b}, rex: rexPrefixW, vopcode: []byte{0x0f, 0x7e}, vmandatoryPrefix: 0xf3}, - // https://www.felixcloutier.com/x86/ucomisd - UCOMISD: {opcode: []byte{0x0f, 0x2e}, mandatoryPrefix: 0x66}, - // https://www.felixcloutier.com/x86/ucomiss - UCOMISS: {opcode: []byte{0x0f, 0x2e}}, - // https://www.felixcloutier.com/x86/subss - SUBSS: {opcode: []byte{0x0f, 0x5c}, mandatoryPrefix: 0xf3}, - // https://www.felixcloutier.com/x86/subsd - SUBSD: {opcode: []byte{0x0f, 0x5c}, mandatoryPrefix: 0xf2}, - // https://www.felixcloutier.com/x86/cmp - CMPL: {opcode: []byte{0x39}}, - CMPQ: {opcode: []byte{0x39}, rex: rexPrefixW}, - // https://www.felixcloutier.com/x86/add - ADDL: {opcode: []byte{0x03}}, - ADDQ: {opcode: []byte{0x03}, rex: rexPrefixW}, -} - -func (a *AssemblerImpl) encodeStaticConstToRegister(buf asm.Buffer, n *nodeImpl) (err error) { - var opc []byte - var rex, mandatoryPrefix byte - info := staticConstToRegisterOpcodes[n.instruction] - switch n.instruction { - case MOVL, MOVQ: - if isVectorRegister(n.dstReg) { - opc, mandatoryPrefix = info.vopcode, info.vmandatoryPrefix - break - } - fallthrough - default: - opc, rex, mandatoryPrefix = info.opcode, info.rex, info.mandatoryPrefix - } - return a.encodeStaticConstImpl(buf, n, opc, rex, mandatoryPrefix) -} - -// encodeStaticConstImpl encodes an instruction where mod:r/m points to the memory location of the static constant n.staticConst, -// and the other operand is the register given at n.srcReg or n.dstReg. -func (a *AssemblerImpl) encodeStaticConstImpl(buf asm.Buffer, n *nodeImpl, opcode []byte, rex rexPrefix, mandatoryPrefix byte) error { - a.pool.AddConst(n.staticConst, uint64(buf.Len())) - - var reg asm.Register - if n.dstReg != asm.NilRegister { - reg = n.dstReg - } else { - reg = n.srcReg - } - - reg3Bits, rexPrefix := register3bits(reg, registerSpecifierPositionModRMFieldReg) - rexPrefix |= rex - - base := buf.Len() - code := buf.Append(len(opcode) + 7)[:0] - - if mandatoryPrefix != 0 { - code = append(code, mandatoryPrefix) - } - - if rexPrefix != rexPrefixNone { - code = append(code, rexPrefix) - } - - code = append(code, opcode...) - - // https://wiki.osdev.org/X86-64_Instruction_Encoding#32.2F64-bit_addressing - modRM := 0b00_000_101 | // Indicate "[RIP + 32bit displacement]" encoding. - (reg3Bits << 3) // Place the reg on ModRM:reg. - code = append(code, modRM) - - // Preserve 4 bytes for displacement which will be filled after we finalize the location. - code = append(code, 0, 0, 0, 0) - - if !n.staticConstReferrersAdded { - a.staticConstReferrers = append(a.staticConstReferrers, staticConstReferrer{n: n, instLen: len(code)}) - n.staticConstReferrersAdded = true - } - - buf.Truncate(base + len(code)) - return nil -} - -// CompileStaticConstToRegister implements Assembler.CompileStaticConstToRegister. -func (a *AssemblerImpl) CompileStaticConstToRegister(instruction asm.Instruction, c *asm.StaticConst, dstReg asm.Register) (err error) { - if len(c.Raw)%2 != 0 { - err = fmt.Errorf("the length of a static constant must be even but was %d", len(c.Raw)) - return - } - - n := a.newNode(instruction, operandTypesStaticConstToRegister) - n.dstReg = dstReg - n.staticConst = c - return -} - -// CompileRegisterToStaticConst implements Assembler.CompileRegisterToStaticConst. -func (a *AssemblerImpl) CompileRegisterToStaticConst(instruction asm.Instruction, srcReg asm.Register, c *asm.StaticConst) (err error) { - if len(c.Raw)%2 != 0 { - err = fmt.Errorf("the length of a static constant must be even but was %d", len(c.Raw)) - return - } - - n := a.newNode(instruction, operandTypesRegisterToStaticConst) - n.srcReg = srcReg - n.staticConst = c - return -} diff --git a/internal/asm/amd64/impl_staticconst_test.go b/internal/asm/amd64/impl_staticconst_test.go deleted file mode 100644 index d253d9aa2a..0000000000 --- a/internal/asm/amd64/impl_staticconst_test.go +++ /dev/null @@ -1,641 +0,0 @@ -package amd64 - -import ( - "encoding/hex" - "testing" - - "github.com/tetratelabs/wazero/internal/asm" - "github.com/tetratelabs/wazero/internal/testing/require" -) - -func TestAssemblerImpl_CompileStaticConstToRegister(t *testing.T) { - a := NewAssembler() - t.Run("odd count of bytes", func(t *testing.T) { - err := a.CompileStaticConstToRegister(MOVDQU, asm.NewStaticConst([]byte{1}), RegAX) - require.Error(t, err) - }) - t.Run("ok", func(t *testing.T) { - cons := asm.NewStaticConst([]byte{1, 2, 3, 4}) - err := a.CompileStaticConstToRegister(MOVDQU, cons, RegAX) - require.NoError(t, err) - actualNode := a.current - require.Equal(t, MOVDQU, actualNode.instruction) - require.Equal(t, operandTypesStaticConstToRegister, actualNode.types) - require.Equal(t, cons, actualNode.staticConst) - }) -} - -func TestAssemblerImpl_CompileRegisterToStaticConst(t *testing.T) { - a := NewAssembler() - t.Run("odd count of bytes", func(t *testing.T) { - err := a.CompileRegisterToStaticConst(MOVDQU, RegAX, asm.NewStaticConst([]byte{1})) - require.Error(t, err) - }) - t.Run("ok", func(t *testing.T) { - cons := asm.NewStaticConst([]byte{1, 2, 3, 4}) - err := a.CompileRegisterToStaticConst(MOVDQU, RegAX, cons) - require.NoError(t, err) - actualNode := a.current - require.Equal(t, MOVDQU, actualNode.instruction) - require.Equal(t, operandTypesRegisterToStaticConst, actualNode.types) - require.Equal(t, cons, actualNode.staticConst) - }) -} - -func TestAssemblerImpl_maybeFlushConstants(t *testing.T) { - t.Run("no consts", func(t *testing.T) { - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - a := NewAssembler() - // Invoking maybeFlushConstants before encoding consts usage should not panic. - a.maybeFlushConstants(code.NextCodeSection(), false) - a.maybeFlushConstants(code.NextCodeSection(), true) - }) - - largeData := make([]byte, 256) - - tests := []struct { - name string - endOfFunction bool - dummyBodyBeforeFlush []byte - firstUseOffsetInBinary uint64 - consts [][]byte - expectedOffsetForConsts []uint64 - exp []byte - maxDisplacement int - }{ - { - name: "end of function", - endOfFunction: true, - dummyBodyBeforeFlush: []byte{'?', '?', '?', '?'}, - consts: [][]byte{{1, 2, 3, 4, 5, 6, 7, 8}, {10, 11, 12, 13}}, - expectedOffsetForConsts: []uint64{4, 4 + 8}, // 4 = len(dummyBodyBeforeFlush) - firstUseOffsetInBinary: 0, - exp: []byte{'?', '?', '?', '?', 1, 2, 3, 4, 5, 6, 7, 8, 10, 11, 12, 13}, - maxDisplacement: 1 << 31, // large displacement will emit the consts at the end of function. - }, - { - name: "not flush", - endOfFunction: false, - dummyBodyBeforeFlush: []byte{'?', '?', '?', '?'}, - consts: [][]byte{{1, 2, 3, 4, 5, 6, 7, 8}, {10, 11, 12, 13}}, - firstUseOffsetInBinary: 0, - exp: []byte{'?', '?', '?', '?'}, - maxDisplacement: 1 << 31, // large displacement will emit the consts at the end of function. - }, - { - name: "not end of function but flush - short jump", - endOfFunction: false, - dummyBodyBeforeFlush: []byte{'?', '?', '?', '?'}, - consts: [][]byte{{1, 2, 3, 4, 5, 6, 7, 8}, {10, 11, 12, 13}}, - expectedOffsetForConsts: []uint64{4 + 2, 4 + 2 + 8}, // 4 = len(dummyBodyBeforeFlush), 2 = the size of jump - firstUseOffsetInBinary: 0, - exp: []byte{ - '?', '?', '?', '?', - 0xeb, 0x0c, // short jump with offset = len(consts[0]) + len(consts[1]) = 12 = 0xc. - 1, 2, 3, 4, 5, 6, 7, 8, 10, 11, 12, 13, - }, - maxDisplacement: 0, // small displacement flushes the const immediately, not at the end of function. - }, - { - name: "not end of function but flush - long jump", - endOfFunction: false, - dummyBodyBeforeFlush: []byte{'?', '?', '?', '?'}, - consts: [][]byte{largeData}, - expectedOffsetForConsts: []uint64{4 + 5}, // 4 = len(dummyBodyBeforeFlush), 5 = the size of jump - firstUseOffsetInBinary: 0, - exp: append([]byte{ - '?', '?', '?', '?', - 0xe9, 0x0, 0x1, 0x0, 0x0, // short jump with offset = 256 = 0x0, 0x1, 0x0, 0x0 (in Little Endian). - }, largeData...), - maxDisplacement: 0, // small displacement flushes the const immediately, not at the end of function. - }, - } - - for _, tc := range tests { - t.Run(tc.name, func(t *testing.T) { - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - a := NewAssembler() - a.MaxDisplacementForConstantPool = tc.maxDisplacement - - buf := code.NextCodeSection() - buf.AppendBytes(tc.dummyBodyBeforeFlush) - - for i, c := range tc.consts { - sc := asm.NewStaticConst(c) - a.pool.AddConst(sc, 100) - i := i - sc.AddOffsetFinalizedCallback(func(offsetOfConstInBinary uint64) { - require.Equal(t, tc.expectedOffsetForConsts[i], offsetOfConstInBinary) - }) - } - - a.pool.FirstUseOffsetInBinary = tc.firstUseOffsetInBinary - a.maybeFlushConstants(buf, tc.endOfFunction) - - require.Equal(t, tc.exp, buf.Bytes()) - }) - } -} - -func TestAssemblerImpl_encodeRegisterToStaticConst(t *testing.T) { - tests := []struct { - name string - ins asm.Instruction - c []byte - reg asm.Register - ud2sBeforeConst int - exp []byte - }{ - { - name: "cmp r12d, dword ptr [rip + 0x14]", - ins: CMPL, - c: []byte{0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8}, - reg: RegR12, - ud2sBeforeConst: 10, - exp: []byte{ - // cmp r12d, dword ptr [rip + 0x14] - // where rip = 0x7, therefore [rip + 0x14] = [0x1b] - 0x44, 0x3b, 0x25, 0x14, 0x0, 0x0, 0x0, - // UD2 * ud2sBeforeConst - 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, - // 0x1b: consts - 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, - }, - }, - { - name: "cmp eax, dword ptr [rip + 0x14]", - ins: CMPL, - c: []byte{0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8}, - reg: RegAX, - ud2sBeforeConst: 10, - exp: []byte{ - // cmp eax, dword ptr [rip + 0x14] - // where rip = 0x6, therefore [rip + 0x14] = [0x1a] - 0x3b, 0x5, 0x14, 0x0, 0x0, 0x0, - // UD2 * ud2sBeforeConst - 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, - // 0x1a: consts - 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, - }, - }, - { - name: "cmp r12, qword ptr [rip]", - ins: CMPQ, - c: []byte{0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8}, - reg: RegR12, - ud2sBeforeConst: 0, - exp: []byte{ - // cmp r12, qword ptr [rip] - // where rip points to the end of this instruction == the const. - 0x4c, 0x3b, 0x25, 0x0, 0x0, 0x0, 0x0, - 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, - }, - }, - { - name: "cmp rsp, qword ptr [rip + 0xa]", - ins: CMPQ, - c: []byte{0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8}, - reg: RegSP, - ud2sBeforeConst: 5, - exp: []byte{ - // cmp rsp, qword ptr [rip + 0xa] - // where rip = 0x6, therefore [rip + 0xa] = [0x11] - 0x48, 0x3b, 0x25, 0xa, 0x0, 0x0, 0x0, - // UD2 * ud2sBeforeConst - 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, - // 0x11: - 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, - }, - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - a := NewAssembler() - - err := a.CompileRegisterToStaticConst(tc.ins, tc.reg, asm.NewStaticConst(tc.c)) - require.NoError(t, err) - - for i := 0; i < tc.ud2sBeforeConst; i++ { - a.CompileStandAlone(UD2) - } - - buf := code.NextCodeSection() - err = a.Assemble(buf) - require.NoError(t, err) - - actual := buf.Bytes() - require.Equal(t, tc.exp, actual, hex.EncodeToString(actual)) - }) - } -} - -func TestAssemblerImpl_encodeStaticConstToRegister(t *testing.T) { - tests := []struct { - name string - ins asm.Instruction - c []byte - reg asm.Register - ud2sBeforeConst int - exp []byte - }{ - { - name: "movdqu xmm14, xmmword ptr [rip + 0xa]", - ins: MOVDQU, - c: []byte{ - 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, - 0x10, 0x20, 0x30, 0x40, 0x50, 0x60, 0x70, 0x80, - }, - reg: RegX14, - ud2sBeforeConst: 5, - exp: []byte{ - // movdqu xmm14, xmmword ptr [rip + 0xa] - // where rip = 0x9, therefore [rip + 0xa] = [0x13] - 0xf3, 0x44, 0xf, 0x6f, 0x35, 0xa, 0x0, 0x0, 0x0, - // UD2 * ud2sBeforeConst - 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, - // 0x13: - 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, - 0x10, 0x20, 0x30, 0x40, 0x50, 0x60, 0x70, 0x80, - }, - }, - { - name: "movupd xmm1, xmmword ptr [rip + 0xa]", - ins: MOVUPD, - c: []byte{ - 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, - 0x10, 0x20, 0x30, 0x40, 0x50, 0x60, 0x70, 0x80, - }, - reg: RegX1, - ud2sBeforeConst: 5, - exp: []byte{ - // movdqu xmm14, xmmword ptr [rip + 0xa] - // where rip = 0x8, therefore [rip + 0xa] = [0x12] - 0x66, 0xf, 0x10, 0xd, 0xa, 0x0, 0x0, 0x0, - // UD2 * ud2sBeforeConst - 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, - // 0x12: - 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, - 0x10, 0x20, 0x30, 0x40, 0x50, 0x60, 0x70, 0x80, - }, - }, - { - name: "lea r11, [rip + 0x14]", - ins: LEAQ, - c: []byte{ - 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, - 0x10, 0x20, 0x30, 0x40, 0x50, 0x60, 0x70, 0x80, - }, - reg: RegR11, - ud2sBeforeConst: 10, - exp: []byte{ - // lea r11, [rip + 0x14] - // where rip = 0x7, therefore [rip + 0x14] = [0x1b] - 0x4c, 0x8d, 0x1d, 0x14, 0x0, 0x0, 0x0, - // UD2 * ud2sBeforeConst - 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, - 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, - // 0x1b: - 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, - 0x10, 0x20, 0x30, 0x40, 0x50, 0x60, 0x70, 0x80, - }, - }, - { - name: "mov r11d, dword ptr [rip + 0x3c]", - ins: MOVL, - c: []byte{ - 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, - 0x10, 0x20, 0x30, 0x40, 0x50, 0x60, 0x70, 0x80, - }, - reg: RegR11, - ud2sBeforeConst: 30, - exp: []byte{ - // mov r11d, dword ptr [rip + 0x3c] - // where rip = 0x7, therefore [rip + 0x3c] = [0x43] - 0x44, 0x8b, 0x1d, 0x3c, 0x0, 0x0, 0x0, - // UD2 * ud2sBeforeConst - 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, - 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, - 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, - 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, - 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, - 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, - // 0x43: - 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, - 0x10, 0x20, 0x30, 0x40, 0x50, 0x60, 0x70, 0x80, - }, - }, - { - name: "movd xmm14, dword ptr [rip + 0x3c]", - ins: MOVL, - c: []byte{ - 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, - 0x10, 0x20, 0x30, 0x40, 0x50, 0x60, 0x70, 0x80, - }, - reg: RegX14, - ud2sBeforeConst: 30, - exp: []byte{ - // movd xmm14, dword ptr [rip + 0x3c] - // where rip = 0x9, therefore [rip + 0x3c] = [0x45] - 0x66, 0x44, 0xf, 0x6e, 0x35, 0x3c, 0x0, 0x0, 0x0, - // UD2 * ud2sBeforeConst - 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, - 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, - 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, - 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, - 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, - 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, - // 0x45: - 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, - 0x10, 0x20, 0x30, 0x40, 0x50, 0x60, 0x70, 0x80, - }, - }, - { - name: "mov rsp, qword ptr [rip + 0x3c]", - ins: MOVQ, - c: []byte{ - 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, - 0x10, 0x20, 0x30, 0x40, 0x50, 0x60, 0x70, 0x80, - }, - reg: RegSP, - ud2sBeforeConst: 30, - exp: []byte{ - // mov rsp, qword ptr [rip + 0x3c] - // where rip = 0x7, therefore [rip + 0x3c] = [0x43] - 0x48, 0x8b, 0x25, 0x3c, 0x0, 0x0, 0x0, - // UD2 * ud2sBeforeConst - 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, - 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, - 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, - 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, - 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, - 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, - // 0x43: - 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, - 0x10, 0x20, 0x30, 0x40, 0x50, 0x60, 0x70, 0x80, - }, - }, - { - name: "movq xmm1, qword ptr [rip + 0x3c]", - ins: MOVQ, - c: []byte{ - 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, - 0x10, 0x20, 0x30, 0x40, 0x50, 0x60, 0x70, 0x80, - }, - reg: RegX1, - ud2sBeforeConst: 30, - exp: []byte{ - // movq xmm1, qword ptr [rip + 0x3c] - // where rip = 0x8, therefore [rip + 0x3c] = [0x44] - 0xf3, 0xf, 0x7e, 0xd, 0x3c, 0x0, 0x0, 0x0, - // UD2 * ud2sBeforeConst - 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, - 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, - 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, - 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, - 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, - 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, - // 0x44: - 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, - 0x10, 0x20, 0x30, 0x40, 0x50, 0x60, 0x70, 0x80, - }, - }, - { - name: "ucomisd xmm15, qword ptr [rip + 6]", - ins: UCOMISD, - c: []byte{0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8}, - reg: RegX15, - ud2sBeforeConst: 3, - exp: []byte{ - // ucomisd xmm15, qword ptr [rip + 6] - // where rip = 0x9, therefore [rip + 6] = [0xf] - 0x66, 0x44, 0xf, 0x2e, 0x3d, 0x6, 0x0, 0x0, 0x0, - // UD2 * ud2sBeforeConst - 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, - // 0xf: - 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, - }, - }, - { - name: "ucomiss xmm15, dword ptr [rip + 6]", - ins: UCOMISS, - c: []byte{0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8}, - reg: RegX15, - ud2sBeforeConst: 3, - exp: []byte{ - // ucomiss xmm15, dword ptr [rip + 6] - // where rip = 0x8, therefore [rip + 6] = [0xe] - 0x44, 0xf, 0x2e, 0x3d, 0x6, 0x0, 0x0, 0x0, - // UD2 * ud2sBeforeConst - 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, - // 0xe: - 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, - }, - }, - { - name: "subss xmm13, dword ptr [rip + 0xa]", - ins: SUBSS, - c: []byte{0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8}, - reg: RegX13, - ud2sBeforeConst: 5, - exp: []byte{ - // subss xmm13, dword ptr [rip + 0xa] - // where rip = 0x9, therefore [rip + 0xa] = [0x13] - 0xf3, 0x44, 0xf, 0x5c, 0x2d, 0xa, 0x0, 0x0, 0x0, - // UD2 * ud2sBeforeConst - 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, - // 0x12: - 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, - }, - }, - { - name: "subsd xmm1, qword ptr [rip + 0xa]", - ins: SUBSD, - c: []byte{0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8}, - reg: RegX1, - ud2sBeforeConst: 5, - exp: []byte{ - // subsd xmm1, qword ptr [rip + 0xa] - // where rip = 0x8, therefore [rip + 0xa] = [0x12] - 0xf2, 0xf, 0x5c, 0xd, 0xa, 0x0, 0x0, 0x0, - // UD2 * ud2sBeforeConst - 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, - // 0x12: - 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, - }, - }, - { - name: "cmp dword ptr [rip + 0x14], r12d", - ins: CMPL, - c: []byte{0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8}, - reg: RegR12, - ud2sBeforeConst: 10, - exp: []byte{ - // cmp dword ptr [rip + 0x14], r12d - // where rip = 0x7, therefore [rip + 0x14] = [0x1b] - 0x44, 0x39, 0x25, 0x14, 0x0, 0x0, 0x0, - // UD2 * ud2sBeforeConst - 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, - // 0x1b: consts - 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, - }, - }, - { - name: "cmp dword ptr [rip + 0x14], eax", - ins: CMPL, - c: []byte{0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8}, - reg: RegAX, - ud2sBeforeConst: 10, - exp: []byte{ - // cmp dword ptr [rip + 0x14], eax - // where rip = 0x6, therefore [rip + 0x14] = [0x1a] - 0x39, 0x5, 0x14, 0x0, 0x0, 0x0, - // UD2 * ud2sBeforeConst - 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, - // 0x1a: consts - 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, - }, - }, - { - name: "cmp qword ptr [rip], r12", - ins: CMPQ, - c: []byte{0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8}, - reg: RegR12, - ud2sBeforeConst: 0, - exp: []byte{ - // cmp qword ptr [rip], r12 - // where rip points to the end of this instruction == the const. - 0x4c, 0x39, 0x25, 0x0, 0x0, 0x0, 0x0, - 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, - }, - }, - { - name: "cmp qword ptr [rip + 0xa], rsp", - ins: CMPQ, - c: []byte{0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8}, - reg: RegSP, - ud2sBeforeConst: 5, - exp: []byte{ - // cmp qword ptr [rip + 0xa], rsp - // where rip = 0x6, therefore [rip + 0xa] = [0x11] - 0x48, 0x39, 0x25, 0xa, 0x0, 0x0, 0x0, - // UD2 * ud2sBeforeConst - 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, - // 0x11: - 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, - }, - }, - { - name: "ucomiss xmm15, dword ptr [rip + 6]", - ins: UCOMISS, - c: []byte{0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8}, - reg: RegX15, - ud2sBeforeConst: 3, - exp: []byte{ - // ucomiss xmm15, dword ptr [rip + 6] - // where rip = 0x8, therefore [rip + 6] = [0xe] - 0x44, 0xf, 0x2e, 0x3d, 0x6, 0x0, 0x0, 0x0, - // UD2 * ud2sBeforeConst - 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, - // 0xe: - 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, - }, - }, - { - name: "subss xmm13, dword ptr [rip + 0xa]", - ins: SUBSS, - c: []byte{0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8}, - reg: RegX13, - ud2sBeforeConst: 5, - exp: []byte{ - // subss xmm13, dword ptr [rip + 0xa] - // where rip = 0x9, therefore [rip + 0xa] = [0x13] - 0xf3, 0x44, 0xf, 0x5c, 0x2d, 0xa, 0x0, 0x0, 0x0, - // UD2 * ud2sBeforeConst - 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, - // 0x12: - 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, - }, - }, - { - name: "subsd xmm1, qword ptr [rip + 0xa]", - ins: SUBSD, - c: []byte{0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8}, - reg: RegX1, - ud2sBeforeConst: 5, - exp: []byte{ - // subsd xmm1, qword ptr [rip + 0xa] - // where rip = 0x8, therefore [rip + 0xa] = [0x12] - 0xf2, 0xf, 0x5c, 0xd, 0xa, 0x0, 0x0, 0x0, - // UD2 * ud2sBeforeConst - 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, - // 0x12: - 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, - }, - }, - { - name: "add eax, dword ptr [rip + 0xa]", - ins: ADDL, - c: []byte{0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8}, - reg: RegAX, - ud2sBeforeConst: 5, - exp: []byte{ - // add eax, dword ptr [rip + 0xa] - // where rip = 0x6, therefore [rip + 0xa] = [0x10] - 0x3, 0x5, 0xa, 0x0, 0x0, 0x0, - // UD2 * ud2sBeforeConst - 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, - // 0x10: - 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, - }, - }, - { - name: "add rax, qword ptr [rip + 0xa]", - ins: ADDQ, - c: []byte{0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8}, - reg: RegAX, - ud2sBeforeConst: 5, - exp: []byte{ - // add rax, dword ptr [rip + 0xa] - // where rip = 0x7, therefore [rip + 0xa] = [0x11] - 0x48, 0x3, 0x5, 0xa, 0x0, 0x0, 0x0, - // UD2 * ud2sBeforeConst - 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, 0xf, 0xb, - // 0x11: - 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, - }, - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - a := NewAssembler() - - err := a.CompileStaticConstToRegister(tc.ins, asm.NewStaticConst(tc.c), tc.reg) - require.NoError(t, err) - - for i := 0; i < tc.ud2sBeforeConst; i++ { - a.CompileStandAlone(UD2) - } - - buf := code.NextCodeSection() - err = a.Assemble(buf) - require.NoError(t, err) - - actual := buf.Bytes() - require.Equal(t, tc.exp, actual, hex.EncodeToString(actual)) - }) - } -} diff --git a/internal/asm/arm64/assembler.go b/internal/asm/arm64/assembler.go deleted file mode 100644 index b83c8b99a3..0000000000 --- a/internal/asm/arm64/assembler.go +++ /dev/null @@ -1,123 +0,0 @@ -package arm64 - -import ( - "github.com/tetratelabs/wazero/internal/asm" -) - -// Assembler is the interface for arm64 specific assembler. -type Assembler interface { - asm.AssemblerBase - - // CompileMemoryWithRegisterOffsetToRegister adds an instruction where source operand is the memory address - // specified as `srcBaseReg + srcOffsetReg` and dst is the register `dstReg`. - CompileMemoryWithRegisterOffsetToRegister(instruction asm.Instruction, srcBaseReg, srcOffsetReg, dstReg asm.Register) - - // CompileMemoryWithRegisterSourceToRegister adds an instruction where source operand is the memory address - // and dst is the register `dstReg`. - CompileMemoryWithRegisterSourceToRegister(instruction asm.Instruction, srcReg, dstReg asm.Register) - - // CompileRegisterToMemoryWithRegisterOffset adds an instruction where source operand is the register `srcReg`, - // and the destination is the memory address specified as `dstBaseReg + dstOffsetReg` - CompileRegisterToMemoryWithRegisterOffset(instruction asm.Instruction, srcReg, dstBaseReg, dstOffsetReg asm.Register) - - // CompileRegisterToMemoryWithRegisterDest adds an instruction where source operand is the register `srcReg`, - // and the destination is the memory address specified as `dstReg` - CompileRegisterToMemoryWithRegisterDest(instruction asm.Instruction, srcReg, dstReg asm.Register) - - // CompileTwoRegistersToRegister adds an instruction where source operands consists of two registers `src1` and `src2`, - // and the destination is the register `dst`. - CompileTwoRegistersToRegister(instruction asm.Instruction, src1, src2, dst asm.Register) - - // CompileThreeRegistersToRegister adds an instruction where source operands consist of three registers - // `src1`, `src2` and `src3`, and destination operands consist of `dst` register. - CompileThreeRegistersToRegister(instruction asm.Instruction, src1, src2, src3, dst asm.Register) - - // CompileTwoRegistersToNone adds an instruction where source operands consist of two registers `src1` and `src2`, - // and destination operand is unspecified. - CompileTwoRegistersToNone(instruction asm.Instruction, src1, src2 asm.Register) - - // CompileRegisterAndConstToNone adds an instruction where source operands consist of one register `src` and - // constant `srcConst`, and destination operand is unspecified. - CompileRegisterAndConstToNone(instruction asm.Instruction, src asm.Register, srcConst asm.ConstantValue) - - // CompileRegisterAndConstToRegister adds an instruction where source operands consist of one register `src` and - // constant `srcConst`, and destination operand is a register `dst`. - CompileRegisterAndConstToRegister(instruction asm.Instruction, src asm.Register, srcConst asm.ConstantValue, dst asm.Register) - - // CompileLeftShiftedRegisterToRegister adds an instruction where source operand is the "left shifted register" - // represented as `srcReg << shiftNum` and the destination is the register `dstReg`. - CompileLeftShiftedRegisterToRegister( - instruction asm.Instruction, - shiftedSourceReg asm.Register, - shiftNum asm.ConstantValue, - srcReg, dstReg asm.Register, - ) - - // CompileConditionalRegisterSet adds an instruction to set 1 on dstReg if the condition satisfies, - // otherwise set 0. - CompileConditionalRegisterSet(cond asm.ConditionalRegisterState, dstReg asm.Register) - - // CompileMemoryToVectorRegister adds an instruction where source operands is the memory address specified by - // `srcBaseReg+srcOffset` and the destination is `dstReg` vector register. - CompileMemoryToVectorRegister(instruction asm.Instruction, srcBaseReg asm.Register, srcOffset asm.ConstantValue, - dstReg asm.Register, arrangement VectorArrangement) - - // CompileMemoryWithRegisterOffsetToVectorRegister is the same as CompileMemoryToVectorRegister except that the - // offset is specified by the `srcOffsetRegister` register. - CompileMemoryWithRegisterOffsetToVectorRegister(instruction asm.Instruction, srcBaseReg, - srcOffsetRegister asm.Register, dstReg asm.Register, arrangement VectorArrangement) - - // CompileVectorRegisterToMemory adds an instruction where source operand is `srcReg` vector register and the - // destination is the memory address specified by `dstBaseReg+dstOffset`. - CompileVectorRegisterToMemory(instruction asm.Instruction, srcReg, dstBaseReg asm.Register, - dstOffset asm.ConstantValue, arrangement VectorArrangement) - - // CompileVectorRegisterToMemoryWithRegisterOffset is the same as CompileVectorRegisterToMemory except that the - // offset is specified by the `dstOffsetRegister` register. - CompileVectorRegisterToMemoryWithRegisterOffset(instruction asm.Instruction, srcReg, dstBaseReg, - dstOffsetRegister asm.Register, arrangement VectorArrangement) - - // CompileRegisterToVectorRegister adds an instruction where source operand is `srcReg` general purpose register and - // the destination is the `dstReg` vector register. The destination vector's arrangement and index of element can be - // given by `arrangement` and `index`, but not all the instructions will use them. - CompileRegisterToVectorRegister(instruction asm.Instruction, srcReg, dstReg asm.Register, - arrangement VectorArrangement, index VectorIndex) - - // CompileVectorRegisterToRegister adds an instruction where destination operand is `dstReg` general purpose register - // and the source is the `srcReg` vector register. The source vector's arrangement and index of element can be - // given by `arrangement` and `index`, but not all the instructions will use them. - CompileVectorRegisterToRegister(instruction asm.Instruction, srcReg, dstReg asm.Register, - arrangement VectorArrangement, index VectorIndex) - - // CompileVectorRegisterToVectorRegister adds an instruction where both source and destination operands are vector - // registers. The vector's arrangement can be specified `arrangement`, and the source and destination element's - // index are given by `srcIndex` and `dstIndex` respectively, but not all the instructions will use them. - CompileVectorRegisterToVectorRegister(instruction asm.Instruction, srcReg, dstReg asm.Register, - arrangement VectorArrangement, srcIndex, dstIndex VectorIndex) - - // CompileVectorRegisterToVectorRegisterWithConst is the same as CompileVectorRegisterToVectorRegister but the - // additional constant can be provided. - // For example, the const can be used to specify the shift amount for USHLL instruction. - CompileVectorRegisterToVectorRegisterWithConst(instruction asm.Instruction, srcReg, dstReg asm.Register, - arrangement VectorArrangement, c asm.ConstantValue) - - // CompileStaticConstToRegister adds an instruction where the source operand is StaticConstant located in - // the memory and the destination is the dstReg. - CompileStaticConstToRegister(instruction asm.Instruction, c *asm.StaticConst, dstReg asm.Register) - - // CompileStaticConstToVectorRegister adds an instruction where the source operand is StaticConstant located in - // the memory and the destination is the dstReg. - CompileStaticConstToVectorRegister(instruction asm.Instruction, c *asm.StaticConst, dstReg asm.Register, - arrangement VectorArrangement) - - // CompileTwoVectorRegistersToVectorRegister adds an instruction where source are two vectors and destination is one - // vector. The vector's arrangement can be specified `arrangement`. - CompileTwoVectorRegistersToVectorRegister(instruction asm.Instruction, srcReg, srcReg2, dstReg asm.Register, - arrangement VectorArrangement) - - // CompileTwoVectorRegistersToVectorRegisterWithConst is the same as CompileTwoVectorRegistersToVectorRegister except - // that this also accept additional constant. - // For example EXIT instruction needs the extraction target immediate as const. - CompileTwoVectorRegistersToVectorRegisterWithConst(instruction asm.Instruction, srcReg, srcReg2, dstReg asm.Register, - arrangement VectorArrangement, c asm.ConstantValue) -} diff --git a/internal/asm/arm64/consts.go b/internal/asm/arm64/consts.go deleted file mode 100644 index 3a9e3cf241..0000000000 --- a/internal/asm/arm64/consts.go +++ /dev/null @@ -1,1639 +0,0 @@ -package arm64 - -import ( - "fmt" - - "github.com/tetratelabs/wazero/internal/asm" -) - -// Arm64-specific register states. -// -// Note: Naming conventions intentionally match the Go assembler: https://go.dev/doc/asm -// See https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/condition-codes-1-condition-flags-and-codes -const ( - // CondEQ is the eq (equal) condition code - CondEQ = asm.ConditionalRegisterStateUnset + 1 + iota - // CondNE is the ne (not equal) condition code - CondNE - // CondHS is the hs (unsigned higher or same) condition code - CondHS - // CondLO is the lo (unsigned lower) condition code - CondLO - // CondMI is the mi (negative) condition code - CondMI - // CondPL is the pl (positive or zero) condition code - CondPL - // CondVS is the vs (signed overflow) condition code - CondVS - // CondVC is the vc (no signed overflow) condition code - CondVC - // CondHI is the hi (unsigned higher) condition code - CondHI - // CondLS is the ls (unsigned lower or same) condition code - CondLS - // CondGE is the ge (signed greater than or equal) condition code - CondGE - // CondLT is the lt (signed less than) condition code - CondLT - // CondGT is the gt (signed greater than) condition code - CondGT - // CondLE is the le (signed less than or equal) condition code - CondLE - // CondAL is the al (always executed) condition code - CondAL - // CondNV has the same meaning as CondAL - CondNV -) - -// Arm64-specific registers. -// -// Note: Naming conventions intentionally match the Go assembler: https://go.dev/doc/asm -// See https://developer.arm.com/documentation/dui0801/a/Overview-of-AArch64-state/Predeclared-core-register-names-in-AArch64-state -const ( - // Integer registers. - - // RegR0 is the R0 register - RegR0 asm.Register = asm.NilRegister + 1 + iota - // RegR1 is the R1 register - RegR1 - // RegR2 is the R2 register - RegR2 - // RegR3 is the R3 register - RegR3 - // RegR4 is the R4 register - RegR4 - // RegR5 is the R5 register - RegR5 - // RegR6 is the R6 register - RegR6 - // RegR7 is the R7 register - RegR7 - // RegR8 is the R8 register - RegR8 - // RegR9 is the R9 register - RegR9 - // RegR10 is the R10 register - RegR10 - // RegR11 is the R11 register - RegR11 - // RegR12 is the R12 register - RegR12 - // RegR13 is the R13 register - RegR13 - // RegR14 is the R14 register - RegR14 - // RegR15 is the R15 register - RegR15 - // RegR16 is the R16 register - RegR16 - // RegR17 is the R17 register - RegR17 - // RegR18 is the R18 register - RegR18 - // RegR19 is the R19 register - RegR19 - // RegR20 is the R20 register - RegR20 - // RegR21 is the R21 register - RegR21 - // RegR22 is the R22 register - RegR22 - // RegR23 is the R23 register - RegR23 - // RegR24 is the R24 register - RegR24 - // RegR25 is the R25 register - RegR25 - // RegR26 is the R26 register - RegR26 - // RegR27 is the R27 register - RegR27 - // RegR28 is the R28 register - RegR28 - // RegR29 is the R29 register - RegR29 - // RegR30 is the R30 register - RegR30 - // RegRZR is the RZR register (read-only, always returning zero) - RegRZR - // RegSP is the SP register - RegSP - - // Scalar floating point registers. - - // RegV0 is the V0 register - RegV0 - // RegV1 is the V1 register - RegV1 - // RegV2 is the V2 register - RegV2 - // RegV3 is the V3 register - RegV3 - // RegV4 is the V4 register - RegV4 - // RegV5 is the V5 register - RegV5 - // RegV6 is the V6 register - RegV6 - // RegV7 is the V7 register - RegV7 - // RegV8 is the V8 register - RegV8 - // RegV9 is the V9 register - RegV9 - // RegV10 is the V10 register - RegV10 - // RegV11 is the V11 register - RegV11 - // RegV12 is the V12 register - RegV12 - // RegV13 is the V13 register - RegV13 - // RegV14 is the V14 register - RegV14 - // RegV15 is the V15 register - RegV15 - // RegV16 is the V16 register - RegV16 - // RegV17 is the V17 register - RegV17 - // RegV18 is the V18 register - RegV18 - // RegV19 is the V19 register - RegV19 - // RegV20 is the V20 register - RegV20 - // RegV21 is the V21 register - RegV21 - // RegV22 is the V22 register - RegV22 - // RegV23 is the V23 register - RegV23 - // RegV24 is the V24 register - RegV24 - // RegV25 is the V25 register - RegV25 - // RegV26 is the V26 register - RegV26 - // RegV27 is the V27 register - RegV27 - // RegV28 is the V28 register - RegV28 - // RegV29 is the V29 register - RegV29 - // RegV30 is the V30 register - RegV30 - // RegV31 is the V31 register - RegV31 - - // Floating point status register. - - // RegFPSR is the FPSR register - RegFPSR - - // Assign each conditional register state to the unique register ID. - // This is to reduce the size of nodeImpl struct without having dedicated field - // for conditional register state which would not be used by most nodes. - // This is taking advantage of the fact that conditional operations are always - // on a single register and condition code, and never two registers. - - // RegCondEQ encodes CondEQ into a field that would otherwise store a register - RegCondEQ - // RegCondNE encodes CondNE into a field that would otherwise store a register - RegCondNE - // RegCondHS encodes CondHS into a field that would otherwise store a register - RegCondHS - // RegCondLO encodes CondLO into a field that would otherwise store a register - RegCondLO - // RegCondMI encodes CondMI into a field that would otherwise store a register - RegCondMI - // RegCondPL encodes CondPL into a field that would otherwise store a register - RegCondPL - // RegCondVS encodes CondVS into a field that would otherwise store a register - RegCondVS - // RegCondVC encodes CondVC into a field that would otherwise store a register - RegCondVC - // RegCondHI encodes CondHI into a field that would otherwise store a register - RegCondHI - // RegCondLS encodes CondLS into a field that would otherwise store a register - RegCondLS - // RegCondGE encodes CondGE into a field that would otherwise store a register - RegCondGE - // RegCondLT encodes CondLT into a field that would otherwise store a register - RegCondLT - // RegCondGT encodes CondGT into a field that would otherwise store a register - RegCondGT - // RegCondLE encodes CondLE into a field that would otherwise store a register - RegCondLE - // RegCondAL encodes CondAL into a field that would otherwise store a register - RegCondAL - // RegCondNV encodes CondNV into a field that would otherwise store a register - RegCondNV -) - -// conditionalRegisterStateToRegister cast a conditional register to its unique register ID. -// See the comment on RegCondEQ above. -func conditionalRegisterStateToRegister(c asm.ConditionalRegisterState) asm.Register { - switch c { - case CondEQ: - return RegCondEQ - case CondNE: - return RegCondNE - case CondHS: - return RegCondHS - case CondLO: - return RegCondLO - case CondMI: - return RegCondMI - case CondPL: - return RegCondPL - case CondVS: - return RegCondVS - case CondVC: - return RegCondVC - case CondHI: - return RegCondHI - case CondLS: - return RegCondLS - case CondGE: - return RegCondGE - case CondLT: - return RegCondLT - case CondGT: - return RegCondGT - case CondLE: - return RegCondLE - case CondAL: - return RegCondAL - case CondNV: - return RegCondNV - } - return asm.NilRegister -} - -// RegisterName returns the name of a given register -func RegisterName(r asm.Register) string { - switch r { - case asm.NilRegister: - return "nil" - case RegR0: - return "R0" - case RegR1: - return "R1" - case RegR2: - return "R2" - case RegR3: - return "R3" - case RegR4: - return "R4" - case RegR5: - return "R5" - case RegR6: - return "R6" - case RegR7: - return "R7" - case RegR8: - return "R8" - case RegR9: - return "R9" - case RegR10: - return "R10" - case RegR11: - return "R11" - case RegR12: - return "R12" - case RegR13: - return "R13" - case RegR14: - return "R14" - case RegR15: - return "R15" - case RegR16: - return "R16" - case RegR17: - return "R17" - case RegR18: - return "R18" - case RegR19: - return "R19" - case RegR20: - return "R20" - case RegR21: - return "R21" - case RegR22: - return "R22" - case RegR23: - return "R23" - case RegR24: - return "R24" - case RegR25: - return "R25" - case RegR26: - return "R26" - case RegR27: - return "R27" - case RegR28: - return "R28" - case RegR29: - return "R29" - case RegR30: - return "R30" - case RegRZR: - return "RZR" - case RegSP: - return "SP" - case RegV0: - return "V0" - case RegV1: - return "V1" - case RegV2: - return "V2" - case RegV3: - return "V3" - case RegV4: - return "V4" - case RegV5: - return "V5" - case RegV6: - return "V6" - case RegV7: - return "V7" - case RegV8: - return "V8" - case RegV9: - return "V9" - case RegV10: - return "V10" - case RegV11: - return "V11" - case RegV12: - return "V12" - case RegV13: - return "V13" - case RegV14: - return "V14" - case RegV15: - return "V15" - case RegV16: - return "V16" - case RegV17: - return "V17" - case RegV18: - return "V18" - case RegV19: - return "V19" - case RegV20: - return "V20" - case RegV21: - return "V21" - case RegV22: - return "V22" - case RegV23: - return "V23" - case RegV24: - return "V24" - case RegV25: - return "V25" - case RegV26: - return "V26" - case RegV27: - return "V27" - case RegV28: - return "V28" - case RegV29: - return "V29" - case RegV30: - return "V30" - case RegV31: - return "V31" - case RegFPSR: - return "FPSR" - case RegCondEQ: - return "COND_EQ" - case RegCondNE: - return "COND_NE" - case RegCondHS: - return "COND_HS" - case RegCondLO: - return "COND_LO" - case RegCondMI: - return "COND_MI" - case RegCondPL: - return "COND_PL" - case RegCondVS: - return "COND_VS" - case RegCondVC: - return "COND_VC" - case RegCondHI: - return "COND_HI" - case RegCondLS: - return "COND_LS" - case RegCondGE: - return "COND_GE" - case RegCondLT: - return "COND_LT" - case RegCondGT: - return "COND_GT" - case RegCondLE: - return "COND_LE" - case RegCondAL: - return "COND_AL" - case RegCondNV: - return "COND_NV" - } - return "UNKNOWN" -} - -// Arm64-specific instructions. -// -// Note: This only defines arm64 instructions used by wazero's compiler. -// Note: Naming conventions partially match the Go assembler: https://go.dev/doc/asm -const ( - // NOP is the NOP instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/NOP - NOP asm.Instruction = iota - // RET is the RET instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/RET - RET - // ADD is the ADD instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ADD--shifted-register- - ADD - // ADDS is the ADDS instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ADDS--shifted-register- - ADDS - // ADDW is the ADD instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ADD--shifted-register- - ADDW - // ADR is the ADR instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ADR - ADR - // AND is the AND instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/AND--shifted-register- - AND - // ANDIMM32 is the AND(immediate) instruction in 32-bit mode https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/AND--immediate---Bitwise-AND--immediate--?lang=en - ANDIMM32 - // ANDIMM64 is the AND(immediate) instruction in 64-bit mode https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/AND--immediate---Bitwise-AND--immediate--?lang=en - ANDIMM64 - // ANDW is the AND instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/AND--register- - ANDW - // ANDS is the ANDS instruction in 64-bit mode https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/ANDS--immediate---Bitwise-AND--immediate---setting-flags-?lang=en - ANDS - // ANDSW is the ANDS instruction in 32-bit mode https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/ANDS--immediate---Bitwise-AND--immediate---setting-flags-?lang=en - ANDSW - // ASR is the ASR instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ASR--register- - ASR - // ASRW is the ASR instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ASR--register- - ASRW - // B is the B instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/B - B - - // Below are B.cond instructions. - // * https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/B-cond - // * https://developer.arm.com/documentation/dui0802/a/A32-and-T32-Instructions/Condition-codes - - // BCONDEQ is the B.cond instruction with CondEQ. - BCONDEQ - // BCONDGE is the B.cond instruction with CondGE. - BCONDGE - // BCONDGT is the B.cond instruction with CondGT. - BCONDGT - // BCONDHI is the B.cond instruction with CondHI. - BCONDHI - // BCONDHS is the B.cond instruction with CondHS. - BCONDHS - // BCONDLE is the B.cond instruction with CondLE. - BCONDLE - // BCONDLO is the B.cond instruction with CondLO. - BCONDLO - // BCONDLS is the B.cond instruction with CondLS. - BCONDLS - // BCONDLT is the B.cond instruction with CondLT. - BCONDLT - // BCONDMI is the B.cond instruction with CondMI. - BCONDMI - // BCONDPL is the B.cond instruction with CondPL. - BCONDPL - // BCONDNE is the B.cond instruction with CondNE. - BCONDNE - // BCONDVS is the B.cond instruction with CondVS. - BCONDVS - // BCONDVC is the B.cond instruction with CondVC. - BCONDVC - - // CLZ is the CLZ instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/CLZ - CLZ - // CLZW is the CLZ instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/CLZ - CLZW - // CMP is the CMP instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/CMP--shifted-register- - CMP - // CMPW is the CMP instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/CMP--shifted-register- - CMPW - // CSET is the CSET instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/CSET - CSET - // EOR is the EOR instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/EOR--shifted-register- - EOR - // EORW is the EOR instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/EOR--shifted-register- - EORW - // FABSD is the FABS instruction, for double-precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FABS--scalar- - FABSD - // FABSS is the FABS instruction, for single-precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FABS--scalar- - FABSS - // FADDD is the FADD instruction, for double-precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FADD--scalar- - FADDD - // FADDS is the FADD instruction, for single-precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FADD--scalar- - FADDS - // FCMPD is the FCMP instruction, for double-precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCMP - FCMPD - // FCMPS is the FCMP instruction, for single-precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCMP - FCMPS - // FCVTDS is the FCVT instruction, for single to double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVT - FCVTDS - // FCVTSD is the FCVT instruction, for double to single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVT - FCVTSD - // FCVTZSD is the FCVTZS instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVTZS--scalar--integer- - FCVTZSD - // FCVTZSDW is the FCVTZS instruction, for double precision in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVTZS--scalar--integer- - FCVTZSDW - // FCVTZSS is the FCVTZS instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVTZS--scalar--integer- - FCVTZSS - // FCVTZSSW is the FCVTZS instruction, for single precision in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVTZS--scalar--integer- - FCVTZSSW - // FCVTZUD is the FCVTZU instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVTZU--scalar--integer- - FCVTZUD - // FCVTZUDW is the FCVTZU instruction, for double precision in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVTZU--scalar--integer- - FCVTZUDW - // FCVTZUS is the FCVTZU instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVTZU--scalar--integer- - FCVTZUS - // FCVTZUSW is the FCVTZU instruction, for single precision in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVTZU--scalar--integer- - FCVTZUSW - // FDIVD is the FDIV instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FDIV--scalar- - FDIVD - // FDIVS is the FDIV instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FDIV--scalar- - FDIVS - // FMAXD is the FMAX instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FMAX--scalar- - FMAXD - // FMAXS is the FMAX instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FMAX--scalar- - FMAXS - // FMIND is the FMIN instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FMIN--scalar- - FMIND - // FMINS is the FMIN instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FMIN--scalar- - FMINS - // FMOVD is the FMOV instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FMOV--register- - FMOVD - // FMOVS is the FMOV instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FMOV--register- - FMOVS - // FMULD is the FMUL instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FMUL--scalar- - FMULD - // FMULS is the FMUL instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FMUL--scalar- - FMULS - // FNEGD is the FNEG instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FNEG--scalar- - FNEGD - // FNEGS is the FNEG instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FNEG--scalar- - FNEGS - // FRINTMD is the FRINTM instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FRINTM--scalar- - FRINTMD - // FRINTMS is the FRINTM instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FRINTM--scalar- - FRINTMS - // FRINTND is the FRINTN instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FRINTN--scalar- - FRINTND - // FRINTNS is the FRINTN instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FRINTN--scalar- - FRINTNS - // FRINTPD is the FRINTP instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FRINTP--scalar- - FRINTPD - // FRINTPS is the FRINTP instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FRINTP--scalar- - FRINTPS - // FRINTZD is the FRINTZ instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FRINTZ--scalar- - FRINTZD - // FRINTZS is the FRINTZ instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FRINTZ--scalar- - FRINTZS - // FSQRTD is the FSQRT instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FSQRT--scalar- - FSQRTD - // FSQRTS is the FSQRT instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FSQRT--scalar- - FSQRTS - // FSUBD is the FSUB instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FSUB--scalar- - FSUBD - // FSUBS is the FSUB instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FSUB--scalar- - FSUBS - // LSL is the LSL instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/LSL--register- - LSL - // LSLW is the LSL instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/LSL--register- - LSLW - // LSR is the LSR instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/LSR--register- - LSR - // LSRW is the LSR instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/LSR--register- - LSRW - // FLDRD is the LDR (SIMD&FP) instruction for double precisions. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/LDR--register--SIMD-FP---Load-SIMD-FP-Register--register-offset--?lang=en - FLDRD - // FLDRS is the LDR (SIMD&FP) instruction for single precisions. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/LDR--register--SIMD-FP---Load-SIMD-FP-Register--register-offset--?lang=en - FLDRS - // LDRD is the LDR instruction in 64-bit mode. https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/LDR--register---Load-Register--register--?lang=en - LDRD - // LDRW is the LDR instruction in 32-bit mode. https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/LDR--register---Load-Register--register--?lang=en - LDRW - // LDRSBD is the LDRSB instruction in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Data-Transfer-Instructions/LDRSB--register- - LDRSBD - // LDRSBW is the LDRSB instruction in 32-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Data-Transfer-Instructions/LDRSB--register- - LDRSBW - // LDRB is the LDRB instruction. https://developer.arm.com/documentation/dui0802/a/A64-Data-Transfer-Instructions/LDRB--register- - LDRB - // LDRSHD is the LDRSHW instruction in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Data-Transfer-Instructions/LDRSH--register- - LDRSHD - // LDRSHW is the LDRSHW instruction in 32-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Data-Transfer-Instructions/LDRSH--register- - LDRSHW - // LDRH is the LDRH instruction. https://developer.arm.com/documentation/dui0802/a/A64-Data-Transfer-Instructions/LDRH--register- - LDRH - // LDRSW is the LDRSW instruction https://developer.arm.com/documentation/dui0802/a/A64-Data-Transfer-Instructions/LDRSW--register- - LDRSW - // FSTRD is the STR (SIMD&FP) instruction for double precisions. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/STR--immediate--SIMD-FP---Store-SIMD-FP-register--immediate-offset--?lang=en - FSTRD - // FSTRS is the STR (SIMD&FP) instruction for single precisions. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/STR--immediate--SIMD-FP---Store-SIMD-FP-register--immediate-offset--?lang=en - FSTRS - // STRD is the STR instruction in 64-bit mode. https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/STR--register---Store-Register--register--?lang=en - STRD - // STRW is the STR instruction in 32-bit mode. https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/STR--register---Store-Register--register--?lang=en - STRW - // STRH is the STRH instruction. https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/STRH--register---Store-Register-Halfword--register--?lang=en - STRH - // STRB is the STRB instruction. https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/STRB--register---Store-Register-Byte--register--?lang=en - STRB - // MOVD moves a double word from register to register, or const to register. - MOVD - // MOVW moves a word from register to register, or const to register. - MOVW - // MRS is the MRS instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/MRS - MRS - // MSR is the MSR instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/MSR--register- - MSR - // MSUB is the MSUB instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/MSUB - MSUB - // MSUBW is the MSUB instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/MSUB - MSUBW - // MUL is the MUL instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/MUL - MUL - // MULW is the MUL instruction, in 32-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/MUL - MULW - // NEG is the NEG instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/NEG - NEG - // NEGW is the NEG instruction, in 32-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/NEG - NEGW - // ORR is the ORR instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ORR--shifted-register- - ORR - // ORRW is the ORR instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ORR--shifted-register- - ORRW - // ORN is the ORN instruction. https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/ORN--shifted-register---Bitwise-OR-NOT--shifted-register--?lang=en#ORN_32_log_shift - ORN - // ORNW is the ORN instruction, in 32-bit mode. https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/ORN--shifted-register---Bitwise-OR-NOT--shifted-register--?lang=en#ORN_32_log_shift - ORNW - // RBIT is the RBIT instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/RBIT - RBIT - // RBITW is the RBIT instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/RBIT - RBITW - // ROR is the ROR instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ROR--register- - ROR - // RORW is the RORW instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ROR--register- - RORW - // SCVTFD is the SCVTF instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/SCVTF--scalar--integer- - SCVTFD - // SCVTFS is the SCVTF instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/SCVTF--scalar--integer- - SCVTFS - // SCVTFWD is the SCVTF instruction, for double precision in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/SCVTF--scalar--integer- - SCVTFWD - // SCVTFWS is the SCVTF instruction, for single precision in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/SCVTF--scalar--integer- - SCVTFWS - // SDIV is the SDIV instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SDIV - SDIV - // SDIVW is the SDIV instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SDIV - SDIVW - // SUB is the SUB instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SUB--shifted-register- - SUB - // SUBS is the SUBS instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SUBS--shifted-register- - SUBS - // SUBW is the SUB instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SUB--shifted-register- - SUBW - // SXTB is the SXTB instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SXTB - SXTB - // SXTBW is the SXTB instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SXTB - SXTBW - // SXTH is the SXTH instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SXTH - SXTH - // SXTHW is the SXTH instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SXTH - SXTHW - // SXTW is the SXTW instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SXTW - SXTW - // UCVTFD is the UCVTF instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/UCVTF--scalar--integer- - UCVTFD - // UCVTFS is the UCVTF instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/UCVTF--scalar--integer- - UCVTFS - // UCVTFWD is the UCVTF instruction, for double precision in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/UCVTF--scalar--integer- - UCVTFWD - // UCVTFWS is the UCVTF instruction, for single precision in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/UCVTF--scalar--integer- - UCVTFWS - // UDIV is the UDIV instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/UDIV - UDIV - // UDIVW is the UDIV instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/UDIV - UDIVW - // VBIT is the BIT instruction. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/BIT--vector- - VBIT - // VCNT is the CNT instruction. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/CNT--vector- - VCNT - // VMOV has different semantics depending on the types of operands: - // - LDR(SIMD&FP) if the src is memory and dst is a vector: https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/LDR--immediate--SIMD-FP---Load-SIMD-FP-Register--immediate-offset-- - // - LDR(literal, SIMD&FP) if the src is static const and dst is a vector: https://developer.arm.com/documentation/dui0801/h/A64-Floating-point-Instructions/LDR--literal--SIMD-and-FP- - // - STR(SIMD&FP) if the dst is memory and src is a vector: https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/STR--immediate--SIMD-FP---Store-SIMD-FP-register--immediate-offset-- - VMOV - // UMOV is the UMOV instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UMOV--Unsigned-Move-vector-element-to-general-purpose-register-?lang=en - UMOV - // INSGEN is the INS(general) instruction https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/INS--general---Insert-vector-element-from-general-purpose-register-?lang=en - INSGEN - // INSELEM is the INS(element) instruction https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/INS--element---Insert-vector-element-from-another-vector-element-?lang=en - INSELEM - // UADDLV is the UADDLV(vector) instruction. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/UADDLV--vector- - UADDLV - // VADD is the ADD(vector) instruction. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/ADD--vector- - VADD - // VFADDS is the FADD(vector) instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/FADD--vector- - VFADDS - // VFADDD is the FADD(vector) instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/FADD--vector- - VFADDD - // VSUB is the SUB(vector) instruction. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/SUB--vector- - VSUB - // VFSUBS is the FSUB(vector) instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/FSUB--vector- - VFSUBS - // VFSUBD is the FSUB(vector) instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/FSUB--vector- - VFSUBD - // SSHL is the SSHL(vector,register) instruction. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SSHL--Signed-Shift-Left--register--?lang=en - SSHL - // SSHLL is the SSHLL(vector,immediate) instruction. https://developer.arm.com/documentation/dui0801/h/A64-SIMD-Vector-Instructions/SSHLL--SSHLL2--vector- - SSHLL - // USHL is the USHL(vector,register) instruction. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SSHL--Signed-Shift-Left--register--?lang=en - USHL - // USHLL is the USHLL(vector,immediate) instruction. https://developer.arm.com/documentation/dui0801/h/A64-SIMD-Vector-Instructions/SSHLL--SSHLL2--vector- - USHLL - // LD1R is the LD1R instruction. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/LD1R--Load-one-single-element-structure-and-Replicate-to-all-lanes--of-one-register-- - LD1R - // SMOV32 is the 32-bit variant of SMOV(vector) instruction. https://developer.arm.com/documentation/100069/0610/A64-SIMD-Vector-Instructions/SMOV--vector- - SMOV32 - // DUPGEN is the DUP(general) instruction. https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/DUP--general---Duplicate-general-purpose-register-to-vector- - DUPGEN - // DUPELEM is the DUP(element) instruction. https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/DUP--element---Duplicate-vector-element-to-vector-or-scalar- - DUPELEM - // UMAXP is the UMAXP(vector) instruction. https://developer.arm.com/documentation/dui0801/g/A64-SIMD-Vector-Instructions/UMAXP--vector- - UMAXP - // UMINV is the UMINV(vector) instruction. https://developer.arm.com/documentation/100069/0610/A64-SIMD-Vector-Instructions/UMINV--vector- - UMINV - // CMEQ is the CMEQ(vector, register) instruction. https://developer.arm.com/documentation/dui0801/g/A64-SIMD-Vector-Instructions/CMEQ--vector--register- - CMEQ - // CMEQZERO is the CMEP(zero) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/CMEQ--zero---Compare-bitwise-Equal-to-zero--vector--?lang=en - CMEQZERO - // ADDP is the ADDP(scalar) instruction. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/ADDP--scalar---Add-Pair-of-elements--scalar--?lang=en - ADDP - // VADDP is the ADDP(vector) instruction. https://developer.arm.com/documentation/dui0801/g/A64-SIMD-Vector-Instructions/ADDP--vector- - // Note: prefixed by V to distinguish from the non-vector variant of ADDP(scalar). - VADDP - // TBL1 is the TBL instruction whose source is one vector. https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/TBL--Table-vector-Lookup- - TBL1 - // TBL2 is the TBL instruction whose source is two vectors. https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/TBL--Table-vector-Lookup- - TBL2 - // NOT is the NOT(vector) instruction https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/NOT--Bitwise-NOT--vector--?lang=en - NOT - // VAND is the AND(vector) instruction https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/AND--vector---Bitwise-AND--vector-- - // Note: prefixed by V to distinguish from the non-vector variant of AND. - VAND - // VORR is the ORR(vector) instruction https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/ORR--vector--register---Bitwise-inclusive-OR--vector--register-- - // Note: prefixed by V to distinguish from the non-vector variant of ORR. - VORR - // BSL https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/BSL--Bitwise-Select- - BSL - // BIC is the BIC(vector) instruction https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/BIC--vector--register---Bitwise-bit-Clear--vector--register-- - BIC - // VFNEG is the FNEG(vector) instruction https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/FNEG--vector---Floating-point-Negate--vector-- - // Note: prefixed by V to distinguish from the non-vector variant of FNEG. - VFNEG - // ADDV is the ADDV instruction https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/ADDV--Add-across-Vector- - ADDV - // ZIP1 is the ZIP1 instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/ZIP1--Zip-vectors--primary--?lang=en - ZIP1 - // SSHR is the SSHR(immediate,vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SSHR--Signed-Shift-Right--immediate--?lang=en - SSHR - // EXT is the EXT instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/EXT--Extract-vector-from-pair-of-vectors-?lang=en - EXT - // CMGT is the CMGT(register) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/CMGT--register---Compare-signed-Greater-than--vector--?lang=en - CMGT - // CMHI is the CMHI(register) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/CMHI--register---Compare-unsigned-Higher--vector--?lang=en - CMHI - // CMGE is the CMGE(register) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/CMGE--register---Compare-signed-Greater-than-or-Equal--vector--?lang=en - CMGE - // CMHS is the CMHS(register) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/CMHS--register---Compare-unsigned-Higher-or-Same--vector--?lang=en - CMHS - // FCMEQ is the FCMEQ(register) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FCMEQ--register---Floating-point-Compare-Equal--vector--?lang=en - FCMEQ - // FCMGT is the FCMGT(register) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FCMGT--register---Floating-point-Compare-Greater-than--vector--?lang=en - FCMGT - // FCMGE is the FCMGE(register) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FCMGE--register---Floating-point-Compare-Greater-than-or-Equal--vector--?lang=en - FCMGE - // VFMUL is the FMUL(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FMUL--vector---Floating-point-Multiply--vector--?lang=en - // Note: prefixed by V to distinguish from the non-vector variant. - VFMUL - // VFDIV is the FDIV(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FDIV--vector---Floating-point-Divide--vector--?lang=en - // Note: prefixed by V to distinguish from the non-vector variant. - VFDIV - // VFSQRT is the FSQRT(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FSQRT--vector---Floating-point-Square-Root--vector--?lang=en - // Note: prefixed by V to distinguish from the non-vector variant. - VFSQRT - // VFMIN is the FMIN(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FMIN--vector---Floating-point-minimum--vector--?lang=en - // Note: prefixed by V to distinguish from the non-vector variant. - VFMIN - // VFMAX is the FMAX(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FMAX--vector---Floating-point-Maximum--vector--?lang=en - // Note: prefixed by V to distinguish from the non-vector variant. - VFMAX - // VFABS is the FABS(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FABS--vector---Floating-point-Absolute-value--vector--?lang=en - // Note: prefixed by V to distinguish from the non-vector variant. - VFABS - // VFRINTP is the FRINTP(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FRINTP--vector---Floating-point-Round-to-Integral--toward-Plus-infinity--vector--?lang=en - // Note: prefixed by V to distinguish from the non-vector variant. - VFRINTP - // VFRINTM is the FRINTM(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FRINTM--vector---Floating-point-Round-to-Integral--toward-Minus-infinity--vector--?lang=en - // Note: prefixed by V to distinguish from the non-vector variant. - VFRINTM - // VFRINTZ is the FRINTZ(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FRINTZ--vector---Floating-point-Round-to-Integral--toward-Zero--vector--?lang=en - // Note: prefixed by V to distinguish from the non-vector variant. - VFRINTZ - // VFRINTN is the FRINTN(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FRINTN--vector---Floating-point-Round-to-Integral--to-nearest-with-ties-to-even--vector--?lang=en - // Note: prefixed by V to distinguish from the non-vector variant. - VFRINTN - // VMUL is the MUL(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/MUL--vector---Multiply--vector--?lang=en - // Note: prefixed by V to distinguish from the non-vector variant. - VMUL - // VNEG is the NEG(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/NEG--vector---Negate--vector--?lang=en - // Note: prefixed by V to distinguish from the non-vector variant. - VNEG - // VABS is the ABS(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/ABS--Absolute-value--vector--?lang=en - // Note: prefixed by V to distinguish from the non-vector variant. - VABS - // VSQADD is the SQADD(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SQADD--Signed-saturating-Add-?lang=en - // Note: prefixed by V to distinguish from the non-vector variant. - VSQADD - // VUQADD is the UQADD(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UQADD--Unsigned-saturating-Add-?lang=en - // Note: prefixed by V to distinguish from the non-vector variant. - VUQADD - // VSQSUB is the SQSUB(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SQSUB--Signed-saturating-Subtract-?lang=en - // Note: prefixed by V to distinguish from the non-vector variant. - VSQSUB - // VUQSUB is the UQSUB(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UQSUB--Unsigned-saturating-Subtract-?lang=en - // Note: prefixed by V to distinguish from the non-vector variant. - VUQSUB - // SMIN is the SMIN instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SMIN--Signed-Minimum--vector--?lang=en - SMIN - // SMAX is the SMAX instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SMAX--Signed-Maximum--vector--?lang=en - SMAX - // UMIN is the UMIN instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UMIN--Unsigned-Minimum--vector--?lang=en - UMIN - // UMAX is the UMAX instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UMAX--Unsigned-Maximum--vector--?lang=en - UMAX - // URHADD is the URHADD instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/URHADD--Unsigned-Rounding-Halving-Add-?lang=en - URHADD - // REV64 is the REV64 instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/REV64--Reverse-elements-in-64-bit-doublewords--vector--?lang=en - REV64 - // XTN is the XTN instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/XTN--XTN2--Extract-Narrow-?lang=en - XTN - // VUMLAL is the UMLAL(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UMLAL--UMLAL2--vector---Unsigned-Multiply-Add-Long--vector--?lang=en - // Note: prefixed by V to distinguish from the non-vector variant. - VUMLAL - // SHLL is the SHLL instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SHLL--SHLL2--Shift-Left-Long--by-element-size--?lang=en - SHLL - // SADDLP is the SADDLP instruction. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SADDLP--Signed-Add-Long-Pairwise-?lang=en - SADDLP - // UADDLP is the UADDLP instruction. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UADDLP--Unsigned-Add-Long-Pairwise-?lang=en - UADDLP - // SSHLL2 is the SSHLL2(vector,immediate) instruction. https://developer.arm.com/documentation/dui0801/h/A64-SIMD-Vector-Instructions/SSHLL--SSHLL2--vector- - SSHLL2 - // USHLL2 is the USHLL2(vector,immediate) instruction. https://developer.arm.com/documentation/dui0801/h/A64-SIMD-Vector-Instructions/SSHLL--SSHLL2--vector- - USHLL2 - // SQRDMULH is the SQRDMULH(vector) instruction. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SQRDMULH--vector---Signed-saturating-Rounding-Doubling-Multiply-returning-High-half-?lang=en - SQRDMULH - // SMULL is the SMULL(vector) instruction. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SMULL--SMULL2--vector---Signed-Multiply-Long--vector--?lang=en - SMULL - // SMULL2 is the SMULL2(vector) instruction. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SMULL--SMULL2--vector---Signed-Multiply-Long--vector--?lang=en - SMULL2 - // UMULL is the UMULL instruction. https://developer.arm.com/documentation/ddi0596/2021-12/Index-by-Encoding/Data-Processing----Scalar-Floating-Point-and-Advanced-SIMD?lang=en - UMULL - // UMULL2 is the UMULL2 instruction. https://developer.arm.com/documentation/ddi0596/2021-12/Index-by-Encoding/Data-Processing----Scalar-Floating-Point-and-Advanced-SIMD?lang=en - UMULL2 - // VFCVTZS is the FCVTZS(vector,integer) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FCVTZS--vector--integer---Floating-point-Convert-to-Signed-integer--rounding-toward-Zero--vector--?lang=en - // Note: prefixed by V to distinguish from the non-vector variant. - VFCVTZS - // VFCVTZU is the FCVTZU(vector,integer) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FCVTZU--vector--integer---Floating-point-Convert-to-Unsigned-integer--rounding-toward-Zero--vector--?lang=en - // Note: prefixed by V to distinguish from the non-vector variant. - VFCVTZU - // SQXTN is the SQXTN instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SQXTN--SQXTN2--Signed-saturating-extract-Narrow-?lang=en - SQXTN - // UQXTN is the UQXTN instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UQXTN--UQXTN2--Unsigned-saturating-extract-Narrow-?lang=en - UQXTN - // SQXTN2 is the SQXTN2 instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SQXTN--SQXTN2--Signed-saturating-extract-Narrow-?lang=en - SQXTN2 - // SQXTUN is the SQXTUN instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SQXTUN--SQXTUN2--Signed-saturating-extract-Unsigned-Narrow-?lang=en - SQXTUN - // SQXTUN2 is the SQXTUN2 instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SQXTUN--SQXTUN2--Signed-saturating-extract-Unsigned-Narrow-?lang=en - SQXTUN2 - // VSCVTF is the SCVTF(vector, integer) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SCVTF--vector--integer---Signed-integer-Convert-to-Floating-point--vector--?lang=en - // Note: prefixed by V to distinguish from the non-vector variant. - VSCVTF - // VUCVTF is the UCVTF(vector, integer) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UCVTF--vector--integer---Unsigned-integer-Convert-to-Floating-point--vector--?lang=en - // Note: prefixed by V to distinguish from the non-vector variant. - VUCVTF - // FCVTL is the FCVTL instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FCVTL--FCVTL2--Floating-point-Convert-to-higher-precision-Long--vector--?lang=en - FCVTL - // FCVTN is the FCVTN instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FCVTN--FCVTN2--Floating-point-Convert-to-lower-precision-Narrow--vector--?lang=en - FCVTN - - // LDARD is the LDAR instruction in 64-bit mode https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/LDAR--Load-Acquire-Register- - LDARD - // LDARD is the LDAR instruction in 32-bit mode https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/LDAR--Load-Acquire-Register- - LDARW - // LDARH is the LDARH instruction https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/LDARH--Load-Acquire-Register-Halfword- - LDARH - // LDARB is the LDARB instruction https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/LDARB--Load-Acquire-Register-Byte- - LDARB - - // STLRD is the STLR instruction in 64-bit mode https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/STLR--Store-Release-Register- - STLRD - // STLRW is the STLR instruction in 64-bit mode https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/STLR--Store-Release-Register- - STLRW - // STLRH is the STLRH instruction https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/STLRH--Store-Release-Register-Halfword- - STLRH - // STLRB is the STLRB instruction https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/STLRB--Store-Release-Register-Byte- - STLRB - - // Note, there is no LDSUB type of instruction, so sub needs to be implemented by first negating the second parameter. - - // LDADDALD is the LDADDAL instruction in 64-bit mode https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/LDADD--LDADDA--LDADDAL--LDADDL--Atomic-add-on-word-or-doubleword-in-memory- - LDADDALD - // LDADDALW is the LDADDAL instruction in 32-bit mode https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/LDADD--LDADDA--LDADDAL--LDADDL--Atomic-add-on-word-or-doubleword-in-memory- - LDADDALW - // LDADDALH is the LDADDALH instruction https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/LDADDH--LDADDAH--LDADDALH--LDADDLH--Atomic-add-on-halfword-in-memory- - LDADDALH - // LDADDALB is the LDADDALB instruction https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/LDADDB--LDADDAB--LDADDALB--LDADDLB--Atomic-add-on-byte-in-memory- - LDADDALB - - // Note, arm's CLR is equivalent to AND NOT - - // LDCLRALD is the LDCLRAL instruction in 64-bit mode https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/LDCLR--LDCLRA--LDCLRAL--LDCLRL--Atomic-bit-clear-on-word-or-doubleword-in-memory- - LDCLRALD - // LDCLRALW is the LDCLRAL instruction in 32-bit mode https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/LDCLR--LDCLRA--LDCLRAL--LDCLRL--Atomic-bit-clear-on-word-or-doubleword-in-memory- - LDCLRALW - // LDCLRALH is the LDCLRALH instruction https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/LDCLRH--LDCLRAH--LDCLRALH--LDCLRLH--Atomic-bit-clear-on-halfword-in-memory- - LDCLRALH - // LDCLRALB is the LDCLRALB instruction https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/LDCLRB--LDCLRAB--LDCLRALB--LDCLRLB--Atomic-bit-clear-on-byte-in-memory- - LDCLRALB - - // Note, arm's SET is equivalent to OR - - // LDSETALD is the LDSETAL instruction in 64-bit mode https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/LDSET--LDSETA--LDSETAL--LDSETL--Atomic-bit-set-on-word-or-doubleword-in-memory- - LDSETALD - // LDSETALW is the LDSETAL instruction in 32-bit mode https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/LDSET--LDSETA--LDSETAL--LDSETL--Atomic-bit-set-on-word-or-doubleword-in-memory- - LDSETALW - // LDSETALH is the LDSETALH instruction https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/LDSETH--LDSETAH--LDSETALH--LDSETLH--Atomic-bit-set-on-halfword-in-memory- - LDSETALH - // LDSETALB is the LDSETALB instruction https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/LDSETB--LDSETAB--LDSETALB--LDSETLB--Atomic-bit-set-on-byte-in-memory- - LDSETALB - - // LDEORALD is the LDEORAL instruction in 64-bit mode https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/LDEOR--LDEORA--LDEORAL--LDEORL--Atomic-bitwise-exclusive-OR-on-word-or-doubleword-in-memory- - LDEORALD - // LDEORALW is the LDEORAL instruction in 32-bit mode https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/LDEOR--LDEORA--LDEORAL--LDEORL--Atomic-bitwise-exclusive-OR-on-word-or-doubleword-in-memory- - LDEORALW - // LDEORALH is the LDEORALH instruction https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/LDEORH--LDEORAH--LDEORALH--LDEORLH--Atomic-bitwise-exclusive-OR-on-halfword-in-memory- - LDEORALH - // LDEORALB is the LDEORALB instruction https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/LDEORB--LDEORAB--LDEORALB--LDEORLB--Atomic-bitwise-exclusive-OR-on-byte-in-memory- - LDEORALB - - // SWPALD is the SWPAL instruction in 64-bit mode https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/SWP--SWPA--SWPAL--SWPL--Swap-word-or-doubleword-in-memory- - SWPALD - // SWPALW is the SWPAL instruction in 32-bit mode https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/SWP--SWPA--SWPAL--SWPL--Swap-word-or-doubleword-in-memory- - SWPALW - // SWPALH is the SWPALH instruction https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/SWPH--SWPAH--SWPALH--SWPLH--Swap-halfword-in-memory- - SWPALH - // SWPALB is the SWPALB instruction https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/SWPB--SWPAB--SWPALB--SWPLB--Swap-byte-in-memory- - SWPALB - - // CASALD is the CASAL instruction in 64-bit mode https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/CAS--CASA--CASAL--CASL--Compare-and-swap-word-or-doubleword-in-memory- - CASALD - // CASALW is the CASAL instruction in 32-bit mode https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/CAS--CASA--CASAL--CASL--Compare-and-swap-word-or-doubleword-in-memory- - CASALW - // CASALH is the CASALH instruction https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/CASH--CASA--CASALH--CASLH--Compare-and-swap-halfword-in-memory- - CASALH - // CASALB is the CASALB instruction https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/CASB--CASAB--CASALB--CASLB--Compare-and-swap-byte-in-memory- - CASALB - - // DMB is the DMB instruction for inner-sharable domain https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/DMB--Data-Memory-Barrier- - DMB - - // UDF is the UDF instruction https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/UDF--Permanently-Undefined-?lang=en - UDF - - // instructionEnd is always placed at the bottom of this iota definition to be used in the test. - instructionEnd -) - -// VectorArrangement is the arrangement of data within a vector register. -type VectorArrangement byte - -const ( - // VectorArrangementNone is an arrangement indicating no data is stored. - VectorArrangementNone VectorArrangement = iota - // VectorArrangement8B is an arrangement of 8 bytes (64-bit vector) - VectorArrangement8B - // VectorArrangement16B is an arrangement of 16 bytes (128-bit vector) - VectorArrangement16B - // VectorArrangement4H is an arrangement of 4 half precisions (64-bit vector) - VectorArrangement4H - // VectorArrangement8H is an arrangement of 8 half precisions (128-bit vector) - VectorArrangement8H - // VectorArrangement2S is an arrangement of 2 single precisions (64-bit vector) - VectorArrangement2S - // VectorArrangement4S is an arrangement of 4 single precisions (128-bit vector) - VectorArrangement4S - // VectorArrangement1D is an arrangement of 1 double precision (64-bit vector) - VectorArrangement1D - // VectorArrangement2D is an arrangement of 2 double precisions (128-bit vector) - VectorArrangement2D - - // Assign each vector size specifier to a vector arrangement ID. - // Instructions can only have an arrangement or a size specifier, but not both, so it - // simplifies the internal representation of vector instructions by being able to - // store either into the same field. - - // VectorArrangementB is a size specifier of byte - VectorArrangementB - // VectorArrangementH is a size specifier of word (16-bit) - VectorArrangementH - // VectorArrangementS is a size specifier of double word (32-bit) - VectorArrangementS - // VectorArrangementD is a size specifier of quad word (64-bit) - VectorArrangementD - // VectorArrangementQ is a size specifier of the entire vector (128-bit) - VectorArrangementQ -) - -func (v VectorArrangement) String() (ret string) { - switch v { - case VectorArrangement8B: - ret = "8B" - case VectorArrangement16B: - ret = "16B" - case VectorArrangement4H: - ret = "4H" - case VectorArrangement8H: - ret = "8H" - case VectorArrangement2S: - ret = "2S" - case VectorArrangement4S: - ret = "4S" - case VectorArrangement1D: - ret = "1D" - case VectorArrangement2D: - ret = "2D" - case VectorArrangementB: - ret = "B" - case VectorArrangementH: - ret = "H" - case VectorArrangementS: - ret = "S" - case VectorArrangementD: - ret = "D" - case VectorArrangementQ: - ret = "Q" - case VectorArrangementNone: - ret = "none" - default: - panic(v) - } - return -} - -// VectorIndex is the index of an element of a vector register -type VectorIndex byte - -// VectorIndexNone indicates no vector index specified. -const VectorIndexNone = ^VectorIndex(0) - -// InstructionName returns the name of the given instruction -func InstructionName(i asm.Instruction) string { - switch i { - case NOP: - return "NOP" - case RET: - return "RET" - case ADD: - return "ADD" - case ADDS: - return "ADDS" - case ADDW: - return "ADDW" - case ADR: - return "ADR" - case AND: - return "AND" - case ANDIMM32: - return "ANDIMM32" - case ANDIMM64: - return "ANDIMM64" - case ANDW: - return "ANDW" - case ANDS: - return "ANDS" - case ANDSW: - return "ANDSW" - case ASR: - return "ASR" - case ASRW: - return "ASRW" - case B: - return "B" - case BCONDEQ: - return "BCONDEQ" - case BCONDGE: - return "BCONDGE" - case BCONDGT: - return "BCONDGT" - case BCONDHI: - return "BCONDHI" - case BCONDHS: - return "BCONDHS" - case BCONDLE: - return "BCONDLE" - case BCONDLO: - return "BCONDLO" - case BCONDLS: - return "BCONDLS" - case BCONDLT: - return "BCONDLT" - case BCONDMI: - return "BCONDMI" - case BCONDPL: - return "BCONDPL" - case BCONDNE: - return "BCONDNE" - case BCONDVS: - return "BCONDVS" - case BCONDVC: - return "BCONDVC" - case CLZ: - return "CLZ" - case CLZW: - return "CLZW" - case CMP: - return "CMP" - case CMPW: - return "CMPW" - case CSET: - return "CSET" - case EOR: - return "EOR" - case EORW: - return "EORW" - case FABSD: - return "FABSD" - case FABSS: - return "FABSS" - case FADDD: - return "FADDD" - case FADDS: - return "FADDS" - case FCMPD: - return "FCMPD" - case FCMPS: - return "FCMPS" - case FCVTDS: - return "FCVTDS" - case FCVTSD: - return "FCVTSD" - case FCVTZSD: - return "FCVTZSD" - case FCVTZSDW: - return "FCVTZSDW" - case FCVTZSS: - return "FCVTZSS" - case FCVTZSSW: - return "FCVTZSSW" - case FCVTZUD: - return "FCVTZUD" - case FCVTZUDW: - return "FCVTZUDW" - case FCVTZUS: - return "FCVTZUS" - case FCVTZUSW: - return "FCVTZUSW" - case FDIVD: - return "FDIVD" - case FDIVS: - return "FDIVS" - case FMAXD: - return "FMAXD" - case FMAXS: - return "FMAXS" - case FMIND: - return "FMIND" - case FMINS: - return "FMINS" - case FMOVD: - return "FMOVD" - case FMOVS: - return "FMOVS" - case FMULD: - return "FMULD" - case FMULS: - return "FMULS" - case FNEGD: - return "FNEGD" - case FNEGS: - return "FNEGS" - case FRINTMD: - return "FRINTMD" - case FRINTMS: - return "FRINTMS" - case FRINTND: - return "FRINTND" - case FRINTNS: - return "FRINTNS" - case FRINTPD: - return "FRINTPD" - case FRINTPS: - return "FRINTPS" - case FRINTZD: - return "FRINTZD" - case FRINTZS: - return "FRINTZS" - case FSQRTD: - return "FSQRTD" - case FSQRTS: - return "FSQRTS" - case FSUBD: - return "FSUBD" - case FSUBS: - return "FSUBS" - case LSL: - return "LSL" - case LSLW: - return "LSLW" - case LSR: - return "LSR" - case LSRW: - return "LSRW" - case LDRSBD: - return "LDRSBD" - case LDRSBW: - return "LDRSBW" - case LDRB: - return "LDRB" - case MOVD: - return "MOVD" - case LDRSHD: - return "LDRSHD" - case LDRSHW: - return "LDRSHW" - case LDRH: - return "LDRH" - case LDRSW: - return "LDRSW" - case STRD: - return "STRD" - case STRW: - return "STRW" - case STRH: - return "STRH" - case STRB: - return "STRB" - case MOVW: - return "MOVW" - case MRS: - return "MRS" - case MSR: - return "MSR" - case MSUB: - return "MSUB" - case MSUBW: - return "MSUBW" - case MUL: - return "MUL" - case MULW: - return "MULW" - case NEG: - return "NEG" - case NEGW: - return "NEGW" - case ORR: - return "ORR" - case ORRW: - return "ORRW" - case ORN: - return "ORN" - case ORNW: - return "ORNW" - case RBIT: - return "RBIT" - case RBITW: - return "RBITW" - case ROR: - return "ROR" - case RORW: - return "RORW" - case SCVTFD: - return "SCVTFD" - case SCVTFS: - return "SCVTFS" - case SCVTFWD: - return "SCVTFWD" - case SCVTFWS: - return "SCVTFWS" - case SDIV: - return "SDIV" - case SDIVW: - return "SDIVW" - case SUB: - return "SUB" - case SUBS: - return "SUBS" - case SUBW: - return "SUBW" - case SXTB: - return "SXTB" - case SXTBW: - return "SXTBW" - case SXTH: - return "SXTH" - case SXTHW: - return "SXTHW" - case SXTW: - return "SXTW" - case UCVTFD: - return "UCVTFD" - case UCVTFS: - return "UCVTFS" - case UCVTFWD: - return "UCVTFWD" - case UCVTFWS: - return "UCVTFWS" - case UDIV: - return "UDIV" - case UDIVW: - return "UDIVW" - case VBIT: - return "VBIT" - case VCNT: - return "VCNT" - case UADDLV: - return "UADDLV" - case VMOV: - return "VMOV" - case INSELEM: - return "INSELEM" - case UMOV: - return "UMOV" - case INSGEN: - return "INSGEN" - case VADD: - return "VADD" - case VFADDS: - return "VFADDS" - case VFADDD: - return "VFADDD" - case VSUB: - return "VSUB" - case VFSUBS: - return "VFSUBS" - case VFSUBD: - return "VFSUBD" - case SSHL: - return "SSHL" - case USHL: - return "USHL" - case SSHLL: - return "SSHLL" - case USHLL: - return "USHLL" - case LD1R: - return "LD1R" - case SMOV32: - return "SMOV32" - case DUPGEN: - return "DUPGEN" - case DUPELEM: - return "DUPELEM" - case UMAXP: - return "UMAXP" - case UMINV: - return "UMINV" - case CMEQ: - return "CMEQ" - case ADDP: - return "ADDP" - case VADDP: - return "VADDP" - case TBL1: - return "TBL1" - case TBL2: - return "TBL2" - case NOT: - return "NOT" - case VAND: - return "VAND" - case VORR: - return "VORR" - case BSL: - return "BSL" - case BIC: - return "BIC" - case VFNEG: - return "VFNEG" - case ADDV: - return "ADDV" - case CMEQZERO: - return "CMEQZERO" - case ZIP1: - return "ZIP1" - case SSHR: - return "SSHR" - case EXT: - return "EXT" - case CMGT: - return "CMGT" - case CMHI: - return "CMHI" - case CMGE: - return "CMGE" - case CMHS: - return "CMHS" - case FCMEQ: - return "FCMEQ" - case FCMGT: - return "FCMGT" - case FCMGE: - return "FCMGE" - case VFMUL: - return "VFMUL" - case VFDIV: - return "VFDIV" - case VFSQRT: - return "VFSQRT" - case VFMIN: - return "VFMIN" - case VFMAX: - return "VFMAX" - case VFABS: - return "VFABS" - case VFRINTP: - return "VFRINTP" - case VFRINTM: - return "VFRINTM" - case VFRINTZ: - return "VFRINTZ" - case VFRINTN: - return "VFRINTN" - case VMUL: - return "VMUL" - case VNEG: - return "VNEG" - case VABS: - return "VABS" - case VSQADD: - return "VSQADD" - case VUQADD: - return "VUQADD" - case SMIN: - return "SMIN" - case SMAX: - return "SMAX" - case UMIN: - return "UMIN" - case UMAX: - return "UMAX" - case URHADD: - return "URHADD" - case VSQSUB: - return "VSQSUB" - case VUQSUB: - return "VUQSUB" - case REV64: - return "REV64" - case XTN: - return "XTN" - case VUMLAL: - return "VUMLAL" - case SHLL: - return "SHLL" - case SSHLL2: - return "SSHLL2" - case USHLL2: - return "USHLL2" - case SQRDMULH: - return "SQRDMULH" - case SADDLP: - return "SADDLP" - case UADDLP: - return "UADDLP" - case SMULL: - return "SMULL" - case SMULL2: - return "SMULL2" - case UMULL: - return "UMULL" - case UMULL2: - return "UMULL2" - case VFCVTZS: - return "VFCVTZS" - case VFCVTZU: - return "VFCVTZU" - case SQXTN: - return "SQXTN" - case UQXTN: - return "UQXTN" - case SQXTN2: - return "SQXTN2" - case SQXTUN: - return "SQXTUN" - case SQXTUN2: - return "SQXTUN2" - case VSCVTF: - return "VSCVTF" - case VUCVTF: - return "VUCVTF" - case FCVTL: - return "FCVTL" - case FCVTN: - return "FCVTN" - case LDARD: - return "LDARD" - case LDARW: - return "LDARW" - case LDARH: - return "LDARH" - case LDARB: - return "LDARB" - case STLRD: - return "STLRD" - case STLRW: - return "STLRW" - case STLRH: - return "STLRH" - case STLRB: - return "STLRB" - case LDADDALD: - return "LDADDALD" - case LDADDALW: - return "LDADDALW" - case LDADDALH: - return "LDADDALH" - case LDADDALB: - return "LDADDALB" - case LDCLRALD: - return "LDCLRALD" - case LDCLRALW: - return "LDCLRALW" - case LDCLRALH: - return "LDCLRALH" - case LDCLRALB: - return "LDCLRALB" - case LDSETALD: - return "LDSETALD" - case LDSETALW: - return "LDSETALW" - case LDSETALH: - return "LDSETALH" - case LDSETALB: - return "LDSETALB" - case LDEORALD: - return "LDEORALD" - case LDEORALW: - return "LDEORALW" - case LDEORALH: - return "LDEORALH" - case LDEORALB: - return "LDEORALB" - case SWPALD: - return "SWPALD" - case SWPALW: - return "SWPALW" - case SWPALH: - return "SWPALH" - case SWPALB: - return "SWPALB" - case CASALD: - return "CASALD" - case CASALW: - return "CASALW" - case CASALH: - return "CASALH" - case CASALB: - return "CASALB" - case DMB: - return "DMB" - case FSTRD: - return "FSTRD" - case FSTRS: - return "FSTRS" - case LDRD: - return "LDRD" - case LDRW: - return "LDRW" - case FLDRD: - return "FLDRD" - case FLDRS: - return "FLDRS" - case UDF: - return "UDF" - } - panic(fmt.Errorf("unknown instruction %d", i)) -} diff --git a/internal/asm/arm64/consts_test.go b/internal/asm/arm64/consts_test.go deleted file mode 100644 index 93410f387a..0000000000 --- a/internal/asm/arm64/consts_test.go +++ /dev/null @@ -1,15 +0,0 @@ -package arm64 - -import ( - "testing" - - "github.com/tetratelabs/wazero/internal/asm" - "github.com/tetratelabs/wazero/internal/testing/require" -) - -// TestInstructionName ensures that all the instruction's name is defined. -func TestInstructionName(t *testing.T) { - for inst := asm.Instruction(0); inst < instructionEnd; inst++ { - require.NotEqual(t, "", InstructionName(inst)) - } -} diff --git a/internal/asm/arm64/impl.go b/internal/asm/arm64/impl.go deleted file mode 100644 index eacc2ecd64..0000000000 --- a/internal/asm/arm64/impl.go +++ /dev/null @@ -1,4058 +0,0 @@ -package arm64 - -import ( - "encoding/binary" - "errors" - "fmt" - - "github.com/tetratelabs/wazero/internal/asm" -) - -type nodeImpl struct { - // jumpTarget holds the target node in the linked for the jump-kind instruction. - jumpTarget *nodeImpl - // next holds the next node from this node in the assembled linked list. - next *nodeImpl - staticConst *asm.StaticConst - - instruction asm.Instruction - types operandTypes - srcReg, srcReg2, dstReg, dstReg2 asm.Register - srcConst, dstConst asm.ConstantValue - - offsetInBinary asm.NodeOffsetInBinary - - // readInstructionAddressBeforeTargetInstruction holds the instruction right before the target of - // read instruction address instruction. See asm.assemblerBase.CompileReadInstructionAddress. - readInstructionAddressBeforeTargetInstruction asm.Instruction - - vectorArrangement VectorArrangement - srcVectorIndex, dstVectorIndex VectorIndex -} - -// AssignJumpTarget implements the same method as documented on asm.Node. -func (n *nodeImpl) AssignJumpTarget(target asm.Node) { - n.jumpTarget = target.(*nodeImpl) -} - -// AssignDestinationConstant implements the same method as documented on asm.Node. -func (n *nodeImpl) AssignDestinationConstant(value asm.ConstantValue) { - n.dstConst = value -} - -// AssignSourceConstant implements the same method as documented on asm.Node. -func (n *nodeImpl) AssignSourceConstant(value asm.ConstantValue) { - n.srcConst = value -} - -// OffsetInBinary implements the same method as documented on asm.Node. -func (n *nodeImpl) OffsetInBinary() asm.NodeOffsetInBinary { - return n.offsetInBinary -} - -// String implements fmt.Stringer. -// -// This is for debugging purpose, and the format is similar to the AT&T assembly syntax, -// meaning that this should look like "INSTRUCTION ${from}, ${to}" where each operand -// might be embraced by '[]' to represent the memory location, and multiple operands -// are embraced by `()`. -func (n *nodeImpl) String() (ret string) { - instName := InstructionName(n.instruction) - switch n.types { - case operandTypesNoneToNone: - ret = instName - case operandTypesNoneToRegister: - ret = fmt.Sprintf("%s %s", instName, RegisterName(n.dstReg)) - case operandTypesNoneToBranch: - ret = fmt.Sprintf("%s {%v}", instName, n.jumpTarget) - case operandTypesRegisterToRegister: - ret = fmt.Sprintf("%s %s, %s", instName, RegisterName(n.srcReg), RegisterName(n.dstReg)) - case operandTypesLeftShiftedRegisterToRegister: - ret = fmt.Sprintf("%s (%s, %s << %d), %s", instName, RegisterName(n.srcReg), RegisterName(n.srcReg2), n.srcConst, RegisterName(n.dstReg)) - case operandTypesTwoRegistersToRegister: - ret = fmt.Sprintf("%s (%s, %s), %s", instName, RegisterName(n.srcReg), RegisterName(n.srcReg2), RegisterName(n.dstReg)) - case operandTypesThreeRegistersToRegister: - ret = fmt.Sprintf("%s (%s, %s, %s), %s)", instName, RegisterName(n.srcReg), RegisterName(n.srcReg2), RegisterName(n.dstReg), RegisterName(n.dstReg2)) - case operandTypesTwoRegistersToNone: - ret = fmt.Sprintf("%s (%s, %s)", instName, RegisterName(n.srcReg), RegisterName(n.srcReg2)) - case operandTypesRegisterAndConstToNone: - ret = fmt.Sprintf("%s (%s, 0x%x)", instName, RegisterName(n.srcReg), n.srcConst) - case operandTypesRegisterAndConstToRegister: - ret = fmt.Sprintf("%s (%s, 0x%x), %s", instName, RegisterName(n.srcReg), n.srcConst, RegisterName(n.dstReg)) - case operandTypesRegisterToMemory: - if n.dstReg2 != asm.NilRegister { - ret = fmt.Sprintf("%s %s, [%s + %s]", instName, RegisterName(n.srcReg), RegisterName(n.dstReg), RegisterName(n.dstReg2)) - } else { - ret = fmt.Sprintf("%s %s, [%s + 0x%x]", instName, RegisterName(n.srcReg), RegisterName(n.dstReg), n.dstConst) - } - case operandTypesMemoryToRegister: - if n.srcReg2 != asm.NilRegister { - ret = fmt.Sprintf("%s [%s + %s], %s", instName, RegisterName(n.srcReg), RegisterName(n.srcReg2), RegisterName(n.dstReg)) - } else { - ret = fmt.Sprintf("%s [%s + 0x%x], %s", instName, RegisterName(n.srcReg), n.srcConst, RegisterName(n.dstReg)) - } - case operandTypesConstToRegister: - ret = fmt.Sprintf("%s 0x%x, %s", instName, n.srcConst, RegisterName(n.dstReg)) - case operandTypesRegisterToVectorRegister: - ret = fmt.Sprintf("%s %s, %s.%s[%d]", instName, RegisterName(n.srcReg), RegisterName(n.dstReg), n.vectorArrangement, n.dstVectorIndex) - case operandTypesVectorRegisterToRegister: - ret = fmt.Sprintf("%s %s.%s[%d], %s", instName, RegisterName(n.srcReg), n.vectorArrangement, n.srcVectorIndex, RegisterName(n.dstReg)) - case operandTypesVectorRegisterToMemory: - if n.dstReg2 != asm.NilRegister { - ret = fmt.Sprintf("%s %s.%s, [%s + %s]", instName, RegisterName(n.srcReg), n.vectorArrangement, RegisterName(n.dstReg), RegisterName(n.dstReg2)) - } else { - ret = fmt.Sprintf("%s %s.%s, [%s + 0x%x]", instName, RegisterName(n.srcReg), n.vectorArrangement, RegisterName(n.dstReg), n.dstConst) - } - case operandTypesMemoryToVectorRegister: - ret = fmt.Sprintf("%s [%s], %s.%s", instName, RegisterName(n.srcReg), RegisterName(n.dstReg), n.vectorArrangement) - case operandTypesVectorRegisterToVectorRegister: - ret = fmt.Sprintf("%s %[2]s.%[4]s, %[3]s.%[4]s", instName, RegisterName(n.srcReg), RegisterName(n.dstReg), n.vectorArrangement) - case operandTypesStaticConstToVectorRegister: - ret = fmt.Sprintf("%s $%#x %s.%s", instName, n.staticConst.Raw, RegisterName(n.dstReg), n.vectorArrangement) - case operandTypesTwoVectorRegistersToVectorRegister: - ret = fmt.Sprintf("%s (%s.%[5]s, %[3]s.%[5]s), %[4]s.%[5]s", instName, RegisterName(n.srcReg), RegisterName(n.srcReg2), RegisterName(n.dstReg), n.vectorArrangement) - } - return -} - -// operandTypes represents types of operands of a node. -type operandTypes byte - -const ( - operandTypesNoneToNone operandTypes = iota - operandTypesNoneToRegister - operandTypesNoneToBranch - operandTypesRegisterToRegister - operandTypesLeftShiftedRegisterToRegister - operandTypesTwoRegistersToRegister - operandTypesThreeRegistersToRegister - operandTypesTwoRegistersToNone - operandTypesRegisterAndConstToNone - operandTypesRegisterAndConstToRegister - operandTypesRegisterToMemory - operandTypesMemoryToRegister - operandTypesConstToRegister - operandTypesRegisterToVectorRegister - operandTypesVectorRegisterToRegister - operandTypesMemoryToVectorRegister - operandTypesVectorRegisterToMemory - operandTypesVectorRegisterToVectorRegister - operandTypesTwoVectorRegistersToVectorRegister - operandTypesStaticConstToVectorRegister -) - -// String implements fmt.Stringer -func (o operandTypes) String() (ret string) { - switch o { - case operandTypesNoneToNone: - ret = "NoneToNone" - case operandTypesNoneToRegister: - ret = "NoneToRegister" - case operandTypesNoneToBranch: - ret = "NoneToBranch" - case operandTypesRegisterToRegister: - ret = "RegisterToRegister" - case operandTypesLeftShiftedRegisterToRegister: - ret = "LeftShiftedRegisterToRegister" - case operandTypesTwoRegistersToRegister: - ret = "TwoRegistersToRegister" - case operandTypesThreeRegistersToRegister: - ret = "ThreeRegistersToRegister" - case operandTypesTwoRegistersToNone: - ret = "TwoRegistersToNone" - case operandTypesRegisterAndConstToNone: - ret = "RegisterAndConstToNone" - case operandTypesRegisterAndConstToRegister: - ret = "RegisterAndConstToRegister" - case operandTypesRegisterToMemory: - ret = "RegisterToMemory" - case operandTypesMemoryToRegister: - ret = "MemoryToRegister" - case operandTypesConstToRegister: - ret = "ConstToRegister" - case operandTypesRegisterToVectorRegister: - ret = "RegisterToVectorRegister" - case operandTypesVectorRegisterToRegister: - ret = "VectorRegisterToRegister" - case operandTypesMemoryToVectorRegister: - ret = "MemoryToVectorRegister" - case operandTypesVectorRegisterToMemory: - ret = "VectorRegisterToMemory" - case operandTypesVectorRegisterToVectorRegister: - ret = "VectorRegisterToVectorRegister" - case operandTypesTwoVectorRegistersToVectorRegister: - ret = "TwoVectorRegistersToVectorRegister" - case operandTypesStaticConstToVectorRegister: - ret = "StaticConstToVectorRegister" - } - return -} - -const ( - maxSignedInt26 int64 = 1<<25 - 1 - minSignedInt26 int64 = -(1 << 25) - - maxSignedInt19 int64 = 1<<19 - 1 - minSignedInt19 int64 = -(1 << 19) -) - -// AssemblerImpl implements Assembler. -type AssemblerImpl struct { - root *nodeImpl - current *nodeImpl - asm.BaseAssemblerImpl - relativeJumpNodes []*nodeImpl - adrInstructionNodes []*nodeImpl - nodePool nodePool - pool asm.StaticConstPool - nodeCount int - - // MaxDisplacementForConstantPool is fixed to defaultMaxDisplacementForConstPool - // but have it as a field here for testability. - MaxDisplacementForConstantPool int - - temporaryRegister asm.Register -} - -const nodePageSize = 128 - -type nodePage = [nodePageSize]nodeImpl - -// nodePool is the central allocation pool for nodeImpl used by a single AssemblerImpl. -// This reduces the allocations over compilation by reusing AssemblerImpl. -type nodePool struct { - pages []*nodePage - index int -} - -// allocNode allocates a new nodeImpl for use from the pool. -// This expands the pool if there is no space left for it. -func (n *nodePool) allocNode() *nodeImpl { - if n.index == nodePageSize { - if len(n.pages) == cap(n.pages) { - n.pages = append(n.pages, new(nodePage)) - } else { - i := len(n.pages) - n.pages = n.pages[:i+1] - if n.pages[i] == nil { - n.pages[i] = new(nodePage) - } - } - n.index = 0 - } - ret := &n.pages[len(n.pages)-1][n.index] - n.index++ - return ret -} - -func (n *nodePool) reset() { - for _, ns := range n.pages { - pages := ns[:] - for i := range pages { - pages[i] = nodeImpl{} - } - } - n.pages = n.pages[:0] - n.index = nodePageSize -} - -func NewAssembler(temporaryRegister asm.Register) *AssemblerImpl { - return &AssemblerImpl{ - nodePool: nodePool{index: nodePageSize}, - temporaryRegister: temporaryRegister, - pool: asm.NewStaticConstPool(), - MaxDisplacementForConstantPool: defaultMaxDisplacementForConstPool, - } -} - -// AllocateNOP implements asm.AssemblerBase. -func (a *AssemblerImpl) AllocateNOP() asm.Node { - n := a.nodePool.allocNode() - n.instruction = NOP - n.types = operandTypesNoneToNone - return n -} - -// Add implements asm.AssemblerBase. -func (a *AssemblerImpl) Add(n asm.Node) { - a.addNode(n.(*nodeImpl)) -} - -// Reset implements asm.AssemblerBase. -func (a *AssemblerImpl) Reset() { - pool := a.pool - pool.Reset() - *a = AssemblerImpl{ - nodePool: a.nodePool, - pool: pool, - temporaryRegister: a.temporaryRegister, - adrInstructionNodes: a.adrInstructionNodes[:0], - relativeJumpNodes: a.relativeJumpNodes[:0], - BaseAssemblerImpl: asm.BaseAssemblerImpl{ - SetBranchTargetOnNextNodes: a.SetBranchTargetOnNextNodes[:0], - JumpTableEntries: a.JumpTableEntries[:0], - }, - } - a.nodePool.reset() -} - -// newNode creates a new Node and appends it into the linked list. -func (a *AssemblerImpl) newNode(instruction asm.Instruction, types operandTypes) *nodeImpl { - n := a.nodePool.allocNode() - n.instruction = instruction - n.types = types - - a.addNode(n) - return n -} - -// addNode appends the new node into the linked list. -func (a *AssemblerImpl) addNode(node *nodeImpl) { - a.nodeCount++ - - if a.root == nil { - a.root = node - a.current = node - } else { - parent := a.current - parent.next = node - a.current = node - } - - for _, o := range a.SetBranchTargetOnNextNodes { - origin := o.(*nodeImpl) - origin.jumpTarget = node - } - // Reuse the underlying slice to avoid re-allocations. - a.SetBranchTargetOnNextNodes = a.SetBranchTargetOnNextNodes[:0] -} - -// Assemble implements asm.AssemblerBase -func (a *AssemblerImpl) Assemble(buf asm.Buffer) error { - // arm64 has 32-bit fixed length instructions, - // but note that some nodes are encoded as multiple instructions, - // so the resulting binary might not be the size of count*8. - buf.Grow(a.nodeCount * 8) - - for n := a.root; n != nil; n = n.next { - n.offsetInBinary = uint64(buf.Len()) - if err := a.encodeNode(buf, n); err != nil { - return err - } - a.maybeFlushConstPool(buf, n.next == nil) - } - - code := buf.Bytes() - - if err := a.FinalizeJumpTableEntry(code); err != nil { - return err - } - - for _, rel := range a.relativeJumpNodes { - if err := a.relativeBranchFinalize(code, rel); err != nil { - return err - } - } - - for _, adr := range a.adrInstructionNodes { - if err := a.finalizeADRInstructionNode(code, adr); err != nil { - return err - } - } - return nil -} - -const defaultMaxDisplacementForConstPool = (1 << 20) - 1 - 4 // -4 for unconditional branch to skip the constants. - -// maybeFlushConstPool flushes the constant pool if endOfBinary or a boundary condition was met. -func (a *AssemblerImpl) maybeFlushConstPool(buf asm.Buffer, endOfBinary bool) { - if a.pool.Empty() { - return - } - - // If endOfBinary = true, we no longer need to emit the instructions, therefore - // flush all the constants. - if endOfBinary || - // Also, if the offset between the first usage of the constant pool and - // the first constant would exceed 2^20 -1(= 2MiB-1), which is the maximum offset - // for LDR(literal)/ADR instruction, flush all the constants in the pool. - (buf.Len()+a.pool.PoolSizeInBytes-int(a.pool.FirstUseOffsetInBinary)) >= a.MaxDisplacementForConstantPool { - - // Before emitting consts, we have to add br instruction to skip the const pool. - // https://github.com/golang/go/blob/release-branch.go1.15/src/cmd/internal/obj/arm64/asm7.go#L1123-L1129 - skipOffset := a.pool.PoolSizeInBytes/4 + 1 - if a.pool.PoolSizeInBytes%4 != 0 { - skipOffset++ - } - if endOfBinary { - // If this is the end of binary, we never reach this block, - // so offset can be zero (which is the behavior of Go's assembler). - skipOffset = 0 - } - - buf.Append4Bytes( - byte(skipOffset), - byte(skipOffset>>8), - byte(skipOffset>>16), - 0x14, - ) - - // Then adding the consts into the binary. - for _, c := range a.pool.Consts { - c.SetOffsetInBinary(uint64(buf.Len())) - buf.AppendBytes(c.Raw) - } - - // arm64 instructions are 4-byte (32-bit) aligned, so we must pad the zero consts here. - if pad := buf.Len() % 4; pad != 0 { - buf.AppendBytes(make([]byte, 4-pad)) - } - - // After the flush, reset the constant pool. - a.pool.Reset() - } -} - -// encodeNode encodes the given node into writer. -func (a *AssemblerImpl) encodeNode(buf asm.Buffer, n *nodeImpl) (err error) { - switch n.types { - case operandTypesNoneToNone: - err = a.encodeNoneToNone(buf, n) - case operandTypesNoneToRegister: - err = a.encodeJumpToRegister(buf, n) - case operandTypesNoneToBranch: - err = a.encodeRelativeBranch(buf, n) - case operandTypesRegisterToRegister: - err = a.encodeRegisterToRegister(buf, n) - case operandTypesLeftShiftedRegisterToRegister: - err = a.encodeLeftShiftedRegisterToRegister(buf, n) - case operandTypesTwoRegistersToRegister: - err = a.encodeTwoRegistersToRegister(buf, n) - case operandTypesThreeRegistersToRegister: - err = a.encodeThreeRegistersToRegister(buf, n) - case operandTypesTwoRegistersToNone: - err = a.encodeTwoRegistersToNone(buf, n) - case operandTypesRegisterAndConstToNone: - err = a.encodeRegisterAndConstToNone(buf, n) - case operandTypesRegisterToMemory: - err = a.encodeRegisterToMemory(buf, n) - case operandTypesMemoryToRegister: - err = a.encodeMemoryToRegister(buf, n) - case operandTypesRegisterAndConstToRegister, operandTypesConstToRegister: - err = a.encodeConstToRegister(buf, n) - case operandTypesRegisterToVectorRegister: - err = a.encodeRegisterToVectorRegister(buf, n) - case operandTypesVectorRegisterToRegister: - err = a.encodeVectorRegisterToRegister(buf, n) - case operandTypesMemoryToVectorRegister: - err = a.encodeMemoryToVectorRegister(buf, n) - case operandTypesVectorRegisterToMemory: - err = a.encodeVectorRegisterToMemory(buf, n) - case operandTypesVectorRegisterToVectorRegister: - err = a.encodeVectorRegisterToVectorRegister(buf, n) - case operandTypesStaticConstToVectorRegister: - err = a.encodeStaticConstToVectorRegister(buf, n) - case operandTypesTwoVectorRegistersToVectorRegister: - err = a.encodeTwoVectorRegistersToVectorRegister(buf, n) - default: - err = fmt.Errorf("encoder undefined for [%s] operand type", n.types) - } - if err != nil { - err = fmt.Errorf("%w: %s", err, n) // Ensure the error is debuggable by including the string value of the node. - } - return -} - -// CompileStandAlone implements the same method as documented on asm.AssemblerBase. -func (a *AssemblerImpl) CompileStandAlone(instruction asm.Instruction) asm.Node { - return a.newNode(instruction, operandTypesNoneToNone) -} - -// CompileConstToRegister implements the same method as documented on asm.AssemblerBase. -func (a *AssemblerImpl) CompileConstToRegister( - instruction asm.Instruction, - value asm.ConstantValue, - destinationReg asm.Register, -) (inst asm.Node) { - n := a.newNode(instruction, operandTypesConstToRegister) - n.srcConst = value - n.dstReg = destinationReg - return n -} - -// CompileRegisterToRegister implements the same method as documented on asm.AssemblerBase. -func (a *AssemblerImpl) CompileRegisterToRegister(instruction asm.Instruction, from, to asm.Register) { - n := a.newNode(instruction, operandTypesRegisterToRegister) - n.srcReg = from - n.dstReg = to -} - -// CompileMemoryToRegister implements the same method as documented on asm.AssemblerBase. -func (a *AssemblerImpl) CompileMemoryToRegister( - instruction asm.Instruction, - sourceBaseReg asm.Register, - sourceOffsetConst asm.ConstantValue, - destinationReg asm.Register, -) { - n := a.newNode(instruction, operandTypesMemoryToRegister) - n.srcReg = sourceBaseReg - n.srcConst = sourceOffsetConst - n.dstReg = destinationReg -} - -// CompileRegisterToMemory implements the same method as documented on asm.AssemblerBase. -func (a *AssemblerImpl) CompileRegisterToMemory( - instruction asm.Instruction, - sourceRegister, destinationBaseRegister asm.Register, - destinationOffsetConst asm.ConstantValue, -) { - n := a.newNode(instruction, operandTypesRegisterToMemory) - n.srcReg = sourceRegister - n.dstReg = destinationBaseRegister - n.dstConst = destinationOffsetConst -} - -// CompileJump implements the same method as documented on asm.AssemblerBase. -func (a *AssemblerImpl) CompileJump(jmpInstruction asm.Instruction) asm.Node { - return a.newNode(jmpInstruction, operandTypesNoneToBranch) -} - -// CompileJumpToRegister implements the same method as documented on asm.AssemblerBase. -func (a *AssemblerImpl) CompileJumpToRegister(jmpInstruction asm.Instruction, reg asm.Register) { - n := a.newNode(jmpInstruction, operandTypesNoneToRegister) - n.dstReg = reg -} - -// CompileReadInstructionAddress implements the same method as documented on asm.AssemblerBase. -func (a *AssemblerImpl) CompileReadInstructionAddress( - destinationRegister asm.Register, - beforeAcquisitionTargetInstruction asm.Instruction, -) { - n := a.newNode(ADR, operandTypesMemoryToRegister) - n.dstReg = destinationRegister - n.readInstructionAddressBeforeTargetInstruction = beforeAcquisitionTargetInstruction -} - -// CompileMemoryWithRegisterOffsetToRegister implements Assembler.CompileMemoryWithRegisterOffsetToRegister -func (a *AssemblerImpl) CompileMemoryWithRegisterOffsetToRegister( - instruction asm.Instruction, - srcBaseReg, srcOffsetReg, dstReg asm.Register, -) { - n := a.newNode(instruction, operandTypesMemoryToRegister) - n.dstReg = dstReg - n.srcReg = srcBaseReg - n.srcReg2 = srcOffsetReg -} - -// CompileMemoryWithRegisterSourceToRegister implements Assembler.CompileMemoryWithRegisterSourceToRegister -func (a *AssemblerImpl) CompileMemoryWithRegisterSourceToRegister(instruction asm.Instruction, srcReg, dstReg asm.Register) { - n := a.newNode(instruction, operandTypesMemoryToRegister) - n.dstReg = dstReg - n.srcReg = srcReg -} - -// CompileRegisterToMemoryWithRegisterOffset implements Assembler.CompileRegisterToMemoryWithRegisterOffset -func (a *AssemblerImpl) CompileRegisterToMemoryWithRegisterOffset( - instruction asm.Instruction, - srcReg, dstBaseReg, dstOffsetReg asm.Register, -) { - n := a.newNode(instruction, operandTypesRegisterToMemory) - n.srcReg = srcReg - n.dstReg = dstBaseReg - n.dstReg2 = dstOffsetReg -} - -// CompileRegisterToMemoryWithRegisterDest implements Assembler.CompileRegisterToMemoryWithRegisterDest -func (a *AssemblerImpl) CompileRegisterToMemoryWithRegisterDest(instruction asm.Instruction, srcReg, dstReg asm.Register) { - n := a.newNode(instruction, operandTypesRegisterToMemory) - n.srcReg = srcReg - n.dstReg = dstReg -} - -// CompileTwoRegistersToRegister implements Assembler.CompileTwoRegistersToRegister -func (a *AssemblerImpl) CompileTwoRegistersToRegister(instruction asm.Instruction, src1, src2, dst asm.Register) { - n := a.newNode(instruction, operandTypesTwoRegistersToRegister) - n.srcReg = src1 - n.srcReg2 = src2 - n.dstReg = dst -} - -// CompileThreeRegistersToRegister implements Assembler.CompileThreeRegistersToRegister -func (a *AssemblerImpl) CompileThreeRegistersToRegister( - instruction asm.Instruction, - src1, src2, src3, dst asm.Register, -) { - n := a.newNode(instruction, operandTypesThreeRegistersToRegister) - n.srcReg = src1 - n.srcReg2 = src2 - n.dstReg = src3 // To minimize the size of nodeImpl struct, we reuse dstReg for the third source operand. - n.dstReg2 = dst -} - -// CompileTwoRegistersToNone implements Assembler.CompileTwoRegistersToNone -func (a *AssemblerImpl) CompileTwoRegistersToNone(instruction asm.Instruction, src1, src2 asm.Register) { - n := a.newNode(instruction, operandTypesTwoRegistersToNone) - n.srcReg = src1 - n.srcReg2 = src2 -} - -// CompileRegisterAndConstToNone implements Assembler.CompileRegisterAndConstToNone -func (a *AssemblerImpl) CompileRegisterAndConstToNone( - instruction asm.Instruction, - src asm.Register, - srcConst asm.ConstantValue, -) { - n := a.newNode(instruction, operandTypesRegisterAndConstToNone) - n.srcReg = src - n.srcConst = srcConst -} - -// CompileRegisterAndConstToRegister implements Assembler.CompileRegisterAndConstToRegister -func (a *AssemblerImpl) CompileRegisterAndConstToRegister( - instruction asm.Instruction, - src asm.Register, - srcConst asm.ConstantValue, - dst asm.Register, -) { - n := a.newNode(instruction, operandTypesRegisterAndConstToRegister) - n.srcReg = src - n.srcConst = srcConst - n.dstReg = dst -} - -// CompileLeftShiftedRegisterToRegister implements Assembler.CompileLeftShiftedRegisterToRegister -func (a *AssemblerImpl) CompileLeftShiftedRegisterToRegister( - instruction asm.Instruction, - shiftedSourceReg asm.Register, - shiftNum asm.ConstantValue, - srcReg, dstReg asm.Register, -) { - n := a.newNode(instruction, operandTypesLeftShiftedRegisterToRegister) - n.srcReg = srcReg - n.srcReg2 = shiftedSourceReg - n.srcConst = shiftNum - n.dstReg = dstReg -} - -// CompileConditionalRegisterSet implements Assembler.CompileConditionalRegisterSet -func (a *AssemblerImpl) CompileConditionalRegisterSet(cond asm.ConditionalRegisterState, dstReg asm.Register) { - n := a.newNode(CSET, operandTypesRegisterToRegister) - n.srcReg = conditionalRegisterStateToRegister(cond) - n.dstReg = dstReg -} - -// CompileMemoryToVectorRegister implements Assembler.CompileMemoryToVectorRegister -func (a *AssemblerImpl) CompileMemoryToVectorRegister( - instruction asm.Instruction, srcBaseReg asm.Register, dstOffset asm.ConstantValue, dstReg asm.Register, arrangement VectorArrangement, -) { - n := a.newNode(instruction, operandTypesMemoryToVectorRegister) - n.srcReg = srcBaseReg - n.srcConst = dstOffset - n.dstReg = dstReg - n.vectorArrangement = arrangement -} - -// CompileMemoryWithRegisterOffsetToVectorRegister implements Assembler.CompileMemoryWithRegisterOffsetToVectorRegister -func (a *AssemblerImpl) CompileMemoryWithRegisterOffsetToVectorRegister(instruction asm.Instruction, - srcBaseReg, srcOffsetRegister asm.Register, dstReg asm.Register, arrangement VectorArrangement, -) { - n := a.newNode(instruction, operandTypesMemoryToVectorRegister) - n.srcReg = srcBaseReg - n.srcReg2 = srcOffsetRegister - n.dstReg = dstReg - n.vectorArrangement = arrangement -} - -// CompileVectorRegisterToMemory implements Assembler.CompileVectorRegisterToMemory -func (a *AssemblerImpl) CompileVectorRegisterToMemory( - instruction asm.Instruction, srcReg, dstBaseReg asm.Register, dstOffset asm.ConstantValue, arrangement VectorArrangement, -) { - n := a.newNode(instruction, operandTypesVectorRegisterToMemory) - n.srcReg = srcReg - n.dstReg = dstBaseReg - n.dstConst = dstOffset - n.vectorArrangement = arrangement -} - -// CompileVectorRegisterToMemoryWithRegisterOffset implements Assembler.CompileVectorRegisterToMemoryWithRegisterOffset -func (a *AssemblerImpl) CompileVectorRegisterToMemoryWithRegisterOffset(instruction asm.Instruction, - srcReg, dstBaseReg, dstOffsetRegister asm.Register, arrangement VectorArrangement, -) { - n := a.newNode(instruction, operandTypesVectorRegisterToMemory) - n.srcReg = srcReg - n.dstReg = dstBaseReg - n.dstReg2 = dstOffsetRegister - n.vectorArrangement = arrangement -} - -// CompileRegisterToVectorRegister implements Assembler.CompileRegisterToVectorRegister -func (a *AssemblerImpl) CompileRegisterToVectorRegister( - instruction asm.Instruction, srcReg, dstReg asm.Register, arrangement VectorArrangement, index VectorIndex, -) { - n := a.newNode(instruction, operandTypesRegisterToVectorRegister) - n.srcReg = srcReg - n.dstReg = dstReg - n.vectorArrangement = arrangement - n.dstVectorIndex = index -} - -// CompileVectorRegisterToRegister implements Assembler.CompileVectorRegisterToRegister -func (a *AssemblerImpl) CompileVectorRegisterToRegister(instruction asm.Instruction, srcReg, dstReg asm.Register, - arrangement VectorArrangement, index VectorIndex, -) { - n := a.newNode(instruction, operandTypesVectorRegisterToRegister) - n.srcReg = srcReg - n.dstReg = dstReg - n.vectorArrangement = arrangement - n.srcVectorIndex = index -} - -// CompileVectorRegisterToVectorRegister implements Assembler.CompileVectorRegisterToVectorRegister -func (a *AssemblerImpl) CompileVectorRegisterToVectorRegister( - instruction asm.Instruction, srcReg, dstReg asm.Register, arrangement VectorArrangement, srcIndex, dstIndex VectorIndex, -) { - n := a.newNode(instruction, operandTypesVectorRegisterToVectorRegister) - n.srcReg = srcReg - n.dstReg = dstReg - n.vectorArrangement = arrangement - n.srcVectorIndex = srcIndex - n.dstVectorIndex = dstIndex -} - -// CompileVectorRegisterToVectorRegisterWithConst implements Assembler.CompileVectorRegisterToVectorRegisterWithConst -func (a *AssemblerImpl) CompileVectorRegisterToVectorRegisterWithConst(instruction asm.Instruction, - srcReg, dstReg asm.Register, arrangement VectorArrangement, c asm.ConstantValue, -) { - n := a.newNode(instruction, operandTypesVectorRegisterToVectorRegister) - n.srcReg = srcReg - n.srcConst = c - n.dstReg = dstReg - n.vectorArrangement = arrangement -} - -// CompileStaticConstToRegister implements Assembler.CompileStaticConstToVectorRegister -func (a *AssemblerImpl) CompileStaticConstToRegister(instruction asm.Instruction, c *asm.StaticConst, dstReg asm.Register) { - n := a.newNode(instruction, operandTypesMemoryToRegister) - n.staticConst = c - n.dstReg = dstReg -} - -// CompileStaticConstToVectorRegister implements Assembler.CompileStaticConstToVectorRegister -func (a *AssemblerImpl) CompileStaticConstToVectorRegister(instruction asm.Instruction, - c *asm.StaticConst, dstReg asm.Register, arrangement VectorArrangement, -) { - n := a.newNode(instruction, operandTypesStaticConstToVectorRegister) - n.staticConst = c - n.dstReg = dstReg - n.vectorArrangement = arrangement -} - -// CompileTwoVectorRegistersToVectorRegister implements Assembler.CompileTwoVectorRegistersToVectorRegister. -func (a *AssemblerImpl) CompileTwoVectorRegistersToVectorRegister(instruction asm.Instruction, srcReg, srcReg2, dstReg asm.Register, - arrangement VectorArrangement, -) { - n := a.newNode(instruction, operandTypesTwoVectorRegistersToVectorRegister) - n.srcReg = srcReg - n.srcReg2 = srcReg2 - n.dstReg = dstReg - n.vectorArrangement = arrangement -} - -// CompileTwoVectorRegistersToVectorRegisterWithConst implements Assembler.CompileTwoVectorRegistersToVectorRegisterWithConst. -func (a *AssemblerImpl) CompileTwoVectorRegistersToVectorRegisterWithConst(instruction asm.Instruction, - srcReg, srcReg2, dstReg asm.Register, arrangement VectorArrangement, c asm.ConstantValue, -) { - n := a.newNode(instruction, operandTypesTwoVectorRegistersToVectorRegister) - n.srcReg = srcReg - n.srcReg2 = srcReg2 - n.srcConst = c - n.dstReg = dstReg - n.vectorArrangement = arrangement -} - -func errorEncodingUnsupported(n *nodeImpl) error { - return fmt.Errorf("%s is unsupported for %s type", InstructionName(n.instruction), n.types) -} - -func (a *AssemblerImpl) encodeNoneToNone(buf asm.Buffer, n *nodeImpl) error { - switch n.instruction { - case UDF: - buf.Append4Bytes(0, 0, 0, 0) - return nil - case DMB: - // InnerSharable, All - buf.Append4Bytes( - 0b10111111, - 0b00111011, - 0b00000011, - 0b11010101, - ) - return nil - case NOP: - return nil - default: - return errorEncodingUnsupported(n) - } -} - -func (a *AssemblerImpl) encodeJumpToRegister(buf asm.Buffer, n *nodeImpl) error { - // "Unconditional branch (register)" in https://developer.arm.com/documentation/ddi0596/2021-12/Index-by-Encoding/Branches--Exception-Generating-and-System-instructions - var opc byte - switch n.instruction { - case RET: - opc = 0b0010 - case B: - opc = 0b0000 - default: - return errorEncodingUnsupported(n) - } - - regBits, err := intRegisterBits(n.dstReg) - if err != nil { - return fmt.Errorf("invalid destination register: %w", err) - } - - buf.Append4Bytes( - 0x00|(regBits<<5), - 0x00|(regBits>>3), - 0b000_11111|(opc<<5), - 0b1101011_0|(opc>>3), - ) - return err -} - -func (a *AssemblerImpl) relativeBranchFinalize(code []byte, n *nodeImpl) error { - var condBits byte - const condBitsUnconditional = 0xff // Indicates this is not conditional jump. - - // https://developer.arm.com/documentation/den0024/a/CHDEEABE - switch n.instruction { - case B: - condBits = condBitsUnconditional - case BCONDEQ: - condBits = 0b0000 - case BCONDGE: - condBits = 0b1010 - case BCONDGT: - condBits = 0b1100 - case BCONDHI: - condBits = 0b1000 - case BCONDHS: - condBits = 0b0010 - case BCONDLE: - condBits = 0b1101 - case BCONDLO: - condBits = 0b0011 - case BCONDLS: - condBits = 0b1001 - case BCONDLT: - condBits = 0b1011 - case BCONDMI: - condBits = 0b0100 - case BCONDPL: - condBits = 0b0101 - case BCONDNE: - condBits = 0b0001 - case BCONDVS: - condBits = 0b0110 - case BCONDVC: - condBits = 0b0111 - } - - branchInstOffset := int64(n.OffsetInBinary()) - offset := int64(n.jumpTarget.OffsetInBinary()) - branchInstOffset - if offset%4 != 0 { - return errors.New("BUG: relative jump offset must be 4 bytes aligned") - } - - branchInst := code[branchInstOffset : branchInstOffset+4] - if condBits == condBitsUnconditional { - imm26 := offset >> 2 // divide by 4. - if imm26 < minSignedInt26 || imm26 > maxSignedInt26 { - // In theory this could happen if a Wasm binary has a huge single label (more than 128MB for a single block), - // and in that case, we use load the offset into a register and do the register jump, but to avoid the complexity, - // we impose this limit for now as that would be *unlikely* happen in practice. - return fmt.Errorf("relative jump offset %d/4 must be within %d and %d", offset, minSignedInt26, maxSignedInt26) - } - // https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/B--Branch-?lang=en - branchInst[0] = byte(imm26) - branchInst[1] = byte(imm26 >> 8) - branchInst[2] = byte(imm26 >> 16) - branchInst[3] = (byte(imm26 >> 24 & 0b000000_11)) | 0b000101_00 - } else { - imm19 := offset >> 2 // divide by 4. - if imm19 < minSignedInt19 || imm19 > maxSignedInt19 { - // This should be a bug in our compiler as the conditional jumps are only used in the small offsets (~a few bytes), - // and if ever happens, compiler can be fixed. - return fmt.Errorf("BUG: relative jump offset %d/4(=%d) must be within %d and %d", offset, imm19, minSignedInt19, maxSignedInt19) - } - // https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/B-cond--Branch-conditionally-?lang=en - branchInst[0] = (byte(imm19<<5) & 0b111_0_0000) | condBits - branchInst[1] = byte(imm19 >> 3) - branchInst[2] = byte(imm19 >> 11) - branchInst[3] = 0b01010100 - } - return nil -} - -func (a *AssemblerImpl) encodeRelativeBranch(buf asm.Buffer, n *nodeImpl) error { - switch n.instruction { - case B, BCONDEQ, BCONDGE, BCONDGT, BCONDHI, BCONDHS, BCONDLE, BCONDLO, BCONDLS, BCONDLT, BCONDMI, BCONDNE, BCONDVS, BCONDVC, BCONDPL: - default: - return errorEncodingUnsupported(n) - } - - if n.jumpTarget == nil { - return fmt.Errorf("branch target must be set for %s", InstructionName(n.instruction)) - } - - // At this point, we don't yet know that target's branch, so emit the placeholder (4 bytes). - buf.Append4Bytes(0, 0, 0, 0) - a.relativeJumpNodes = append(a.relativeJumpNodes, n) - return nil -} - -func checkRegisterToRegisterType(src, dst asm.Register, requireSrcInt, requireDstInt bool) (err error) { - isSrcInt, isDstInt := isIntRegister(src), isIntRegister(dst) - if isSrcInt && !requireSrcInt { - err = fmt.Errorf("src requires float register but got %s", RegisterName(src)) - } else if !isSrcInt && requireSrcInt { - err = fmt.Errorf("src requires int register but got %s", RegisterName(src)) - } else if isDstInt && !requireDstInt { - err = fmt.Errorf("dst requires float register but got %s", RegisterName(dst)) - } else if !isDstInt && requireDstInt { - err = fmt.Errorf("dst requires int register but got %s", RegisterName(dst)) - } - return -} - -func (a *AssemblerImpl) encodeRegisterToRegister(buf asm.Buffer, n *nodeImpl) (err error) { - switch inst := n.instruction; inst { - case ADD, ADDW, SUB: - if err = checkRegisterToRegisterType(n.srcReg, n.dstReg, true, true); err != nil { - return - } - - // https://developer.arm.com/documentation/ddi0596/2021-12/Index-by-Encoding/Data-Processing----Register?lang=en#addsub_shift - var sfops byte - switch inst { - case ADD: - sfops = 0b100 - case ADDW: - case SUB: - sfops = 0b110 - } - - srcRegBits, dstRegBits := registerBits(n.srcReg), registerBits(n.dstReg) - buf.Append4Bytes( - (dstRegBits<<5)|dstRegBits, - dstRegBits>>3, - srcRegBits, - (sfops<<5)|0b01011, - ) - case CLZ, CLZW, RBIT, RBITW: - if err = checkRegisterToRegisterType(n.srcReg, n.dstReg, true, true); err != nil { - return - } - - var sf, opcode byte - switch inst { - case CLZ: - // https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/CLZ--Count-Leading-Zeros-?lang=en - sf, opcode = 0b1, 0b000_100 - case CLZW: - // https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/CLZ--Count-Leading-Zeros-?lang=en - sf, opcode = 0b0, 0b000_100 - case RBIT: - // https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/RBIT--Reverse-Bits-?lang=en - sf, opcode = 0b1, 0b000_000 - case RBITW: - // https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/RBIT--Reverse-Bits-?lang=en - sf, opcode = 0b0, 0b000_000 - } - if inst == CLZ { - sf = 1 - } - - srcRegBits, dstRegBits := registerBits(n.srcReg), registerBits(n.dstReg) - buf.Append4Bytes( - (srcRegBits<<5)|dstRegBits, - opcode<<2|(srcRegBits>>3), - 0b110_00000, - (sf<<7)|0b0_1011010, - ) - case CSET: - if !isConditionalRegister(n.srcReg) { - return fmt.Errorf("CSET requires conditional register but got %s", RegisterName(n.srcReg)) - } - - dstRegBits, err := intRegisterBits(n.dstReg) - if err != nil { - return err - } - - // CSET encodes the conditional bits with its least significant bit inverted. - // https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/CSET--Conditional-Set--an-alias-of-CSINC-?lang=en - // - // https://developer.arm.com/documentation/den0024/a/CHDEEABE - var conditionalBits byte - switch n.srcReg { - case RegCondEQ: - conditionalBits = 0b0001 - case RegCondNE: - conditionalBits = 0b0000 - case RegCondHS: - conditionalBits = 0b0011 - case RegCondLO: - conditionalBits = 0b0010 - case RegCondMI: - conditionalBits = 0b0101 - case RegCondPL: - conditionalBits = 0b0100 - case RegCondVS: - conditionalBits = 0b0111 - case RegCondVC: - conditionalBits = 0b0110 - case RegCondHI: - conditionalBits = 0b1001 - case RegCondLS: - conditionalBits = 0b1000 - case RegCondGE: - conditionalBits = 0b1011 - case RegCondLT: - conditionalBits = 0b1010 - case RegCondGT: - conditionalBits = 0b1101 - case RegCondLE: - conditionalBits = 0b1100 - case RegCondAL: - conditionalBits = 0b1111 - case RegCondNV: - conditionalBits = 0b1110 - } - - // https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/CSET--Conditional-Set--an-alias-of-CSINC-?lang=en - buf.Append4Bytes( - 0b111_00000|dstRegBits, - (conditionalBits<<4)|0b0000_0111, - 0b100_11111, - 0b10011010, - ) - - case FABSD, FABSS, FNEGD, FNEGS, FSQRTD, FSQRTS, FCVTSD, FCVTDS, FRINTMD, FRINTMS, - FRINTND, FRINTNS, FRINTPD, FRINTPS, FRINTZD, FRINTZS: - if err = checkRegisterToRegisterType(n.srcReg, n.dstReg, false, false); err != nil { - return - } - - srcRegBits, dstRegBits := registerBits(n.srcReg), registerBits(n.dstReg) - - // https://developer.arm.com/documentation/ddi0596/2021-12/Index-by-Encoding/Data-Processing----Scalar-Floating-Point-and-Advanced-SIMD?lang=en#floatdp1 - var tp, opcode byte - switch inst { - case FABSD: - opcode, tp = 0b000001, 0b01 - case FABSS: - opcode, tp = 0b000001, 0b00 - case FNEGD: - opcode, tp = 0b000010, 0b01 - case FNEGS: - opcode, tp = 0b000010, 0b00 - case FSQRTD: - opcode, tp = 0b000011, 0b01 - case FSQRTS: - opcode, tp = 0b000011, 0b00 - case FCVTSD: - opcode, tp = 0b000101, 0b00 - case FCVTDS: - opcode, tp = 0b000100, 0b01 - case FRINTMD: - opcode, tp = 0b001010, 0b01 - case FRINTMS: - opcode, tp = 0b001010, 0b00 - case FRINTND: - opcode, tp = 0b001000, 0b01 - case FRINTNS: - opcode, tp = 0b001000, 0b00 - case FRINTPD: - opcode, tp = 0b001001, 0b01 - case FRINTPS: - opcode, tp = 0b001001, 0b00 - case FRINTZD: - opcode, tp = 0b001011, 0b01 - case FRINTZS: - opcode, tp = 0b001011, 0b00 - } - buf.Append4Bytes( - (srcRegBits<<5)|dstRegBits, - (opcode<<7)|0b0_10000_00|(srcRegBits>>3), - tp<<6|0b00_1_00000|opcode>>1, - 0b0_00_11110, - ) - - case FADDD, FADDS, FDIVS, FDIVD, FMAXD, FMAXS, FMIND, FMINS, FMULS, FMULD: - if err = checkRegisterToRegisterType(n.srcReg, n.dstReg, false, false); err != nil { - return - } - - srcRegBits, dstRegBits := registerBits(n.srcReg), registerBits(n.dstReg) - - // "Floating-point data-processing (2 source)" in - // https://developer.arm.com/documentation/ddi0596/2021-12/Index-by-Encoding/Data-Processing----Scalar-Floating-Point-and-Advanced-SIMD?lang=en#floatdp1 - var tp, opcode byte - switch inst { - case FADDD: - opcode, tp = 0b0010, 0b01 - case FADDS: - opcode, tp = 0b0010, 0b00 - case FDIVD: - opcode, tp = 0b0001, 0b01 - case FDIVS: - opcode, tp = 0b0001, 0b00 - case FMAXD: - opcode, tp = 0b0100, 0b01 - case FMAXS: - opcode, tp = 0b0100, 0b00 - case FMIND: - opcode, tp = 0b0101, 0b01 - case FMINS: - opcode, tp = 0b0101, 0b00 - case FMULS: - opcode, tp = 0b0000, 0b00 - case FMULD: - opcode, tp = 0b0000, 0b01 - } - - buf.Append4Bytes( - (dstRegBits<<5)|dstRegBits, - opcode<<4|0b0000_10_00|(dstRegBits>>3), - tp<<6|0b00_1_00000|srcRegBits, - 0b0001_1110, - ) - - case FCVTZSD, FCVTZSDW, FCVTZSS, FCVTZSSW, FCVTZUD, FCVTZUDW, FCVTZUS, FCVTZUSW: - if err = checkRegisterToRegisterType(n.srcReg, n.dstReg, false, true); err != nil { - return - } - - srcRegBits, dstRegBits := registerBits(n.srcReg), registerBits(n.dstReg) - - // "Conversion between floating-point and integer" in - // https://developer.arm.com/documentation/ddi0596/2021-12/Index-by-Encoding/Data-Processing----Scalar-Floating-Point-and-Advanced-SIMD?lang=en#floatdp1 - var sf, tp, opcode byte - switch inst { - case FCVTZSD: // Double to signed 64-bit - sf, tp, opcode = 0b1, 0b01, 0b000 - case FCVTZSDW: // Double to signed 32-bit. - sf, tp, opcode = 0b0, 0b01, 0b000 - case FCVTZSS: // Single to signed 64-bit. - sf, tp, opcode = 0b1, 0b00, 0b000 - case FCVTZSSW: // Single to signed 32-bit. - sf, tp, opcode = 0b0, 0b00, 0b000 - case FCVTZUD: // Double to unsigned 64-bit. - sf, tp, opcode = 0b1, 0b01, 0b001 - case FCVTZUDW: // Double to unsigned 32-bit. - sf, tp, opcode = 0b0, 0b01, 0b001 - case FCVTZUS: // Single to unsigned 64-bit. - sf, tp, opcode = 0b1, 0b00, 0b001 - case FCVTZUSW: // Single to unsigned 32-bit. - sf, tp, opcode = 0b0, 0b00, 0b001 - } - - buf.Append4Bytes( - (srcRegBits<<5)|dstRegBits, - 0|(srcRegBits>>3), - tp<<6|0b00_1_11_000|opcode, - sf<<7|0b0_0_0_11110, - ) - - case FMOVD, FMOVS: - isSrcInt, isDstInt := isIntRegister(n.srcReg), isIntRegister(n.dstReg) - if isSrcInt && isDstInt { - return errors.New("FMOV needs at least one of operands to be integer") - } - - srcRegBits, dstRegBits := registerBits(n.srcReg), registerBits(n.dstReg) - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FMOV--register---Floating-point-Move-register-without-conversion-?lang=en - if !isSrcInt && !isDstInt { // Float to float. - var tp byte - if inst == FMOVD { - tp = 0b01 - } - buf.Append4Bytes( - (srcRegBits<<5)|dstRegBits, - 0b0_10000_00|(srcRegBits>>3), - tp<<6|0b00_1_00000, - 0b000_11110, - ) - } else if isSrcInt && !isDstInt { // Int to float. - var tp, sf byte - if inst == FMOVD { - tp, sf = 0b01, 0b1 - } - buf.Append4Bytes( - (srcRegBits<<5)|dstRegBits, - srcRegBits>>3, - tp<<6|0b00_1_00_111, - sf<<7|0b0_00_11110, - ) - } else { // Float to int. - var tp, sf byte - if inst == FMOVD { - tp, sf = 0b01, 0b1 - } - buf.Append4Bytes( - (srcRegBits<<5)|dstRegBits, - srcRegBits>>3, - tp<<6|0b00_1_00_110, - sf<<7|0b0_00_11110, - ) - } - - case MOVD, MOVW: - if err = checkRegisterToRegisterType(n.srcReg, n.dstReg, true, true); err != nil { - return - } - srcRegBits, dstRegBits := registerBits(n.srcReg), registerBits(n.dstReg) - - if n.srcReg == RegSP || n.dstReg == RegSP { - // Moving between stack pointers. - // https://developer.arm.com/documentation/ddi0602/2021-12/Base-Instructions/MOV--to-from-SP---Move-between-register-and-stack-pointer--an-alias-of-ADD--immediate-- - buf.Append4Bytes( - (srcRegBits<<5)|dstRegBits, - srcRegBits>>3, - 0x0, - 0b1001_0001, - ) - return - } - - if n.srcReg == RegRZR && inst == MOVD { - // If this is 64-bit mov from zero register, then we encode this as MOVK. - // See "Move wide (immediate)" in - // https://developer.arm.com/documentation/ddi0602/2021-06/Index-by-Encoding/Data-Processing----Immediate - buf.Append4Bytes( - dstRegBits, - 0x0, - 0b1000_0000, - 0b1_10_10010, - ) - } else { - // MOV can be encoded as ORR (shifted register): "ORR Wd, WZR, Wm". - // https://developer.arm.com/documentation/100069/0609/A64-General-Instructions/MOV--register- - var sf byte - if inst == MOVD { - sf = 0b1 - } - buf.Append4Bytes( - (zeroRegisterBits<<5)|dstRegBits, - zeroRegisterBits>>3, - 0b000_00000|srcRegBits, - sf<<7|0b0_01_01010, - ) - } - - case MRS: - if n.srcReg != RegFPSR { - return fmt.Errorf("MRS has only support for FPSR register as a src but got %s", RegisterName(n.srcReg)) - } - - // For how to specify FPSR register, see "Accessing FPSR" in: - // https://developer.arm.com/documentation/ddi0595/2021-12/AArch64-Registers/FPSR--Floating-point-Status-Register?lang=en - dstRegBits := registerBits(n.dstReg) - buf.Append4Bytes( - 0b001<<5|dstRegBits, - 0b0100<<4|0b0100, - 0b0011_0000|0b11<<3|0b011, - 0b1101_0101, - ) - - case MSR: - if n.dstReg != RegFPSR { - return fmt.Errorf("MSR has only support for FPSR register as a dst but got %s", RegisterName(n.srcReg)) - } - - // For how to specify FPSR register, see "Accessing FPSR" in: - // https://developer.arm.com/documentation/ddi0595/2021-12/AArch64-Registers/FPSR--Floating-point-Status-Register?lang=en - srcRegBits := registerBits(n.srcReg) - buf.Append4Bytes( - 0b001<<5|srcRegBits, - 0b0100<<4|0b0100, - 0b0001_0000|0b11<<3|0b011, - 0b1101_0101, - ) - - case MUL, MULW: - // Multiplications are encoded as MADD (zero register, src, dst), dst = zero + (src * dst) = src * dst. - // See "Data-processing (3 source)" in - // https://developer.arm.com/documentation/ddi0602/2021-06/Index-by-Encoding/Data-Processing----Register?lang=en - if err = checkRegisterToRegisterType(n.srcReg, n.dstReg, true, true); err != nil { - return - } - - var sf byte - if inst == MUL { - sf = 0b1 - } - - srcRegBits, dstRegBits := registerBits(n.srcReg), registerBits(n.dstReg) - - buf.Append4Bytes( - dstRegBits<<5|dstRegBits, - zeroRegisterBits<<2|dstRegBits>>3, - srcRegBits, - sf<<7|0b11011, - ) - - case NEG, NEGW: - srcRegBits, dstRegBits := registerBits(n.srcReg), registerBits(n.dstReg) - - if err = checkRegisterToRegisterType(n.srcReg, n.dstReg, true, true); err != nil { - return - } - - // NEG is encoded as "SUB dst, XZR, src" = "dst = 0 - src" - // https://developer.arm.com/documentation/ddi0596/2021-12/Index-by-Encoding/Data-Processing----Register?lang=en#addsub_shift - var sf byte - if inst == NEG { - sf = 0b1 - } - - buf.Append4Bytes( - (zeroRegisterBits<<5)|dstRegBits, - zeroRegisterBits>>3, - srcRegBits, - sf<<7|0b0_10_00000|0b0_00_01011, - ) - - case SDIV, SDIVW, UDIV, UDIVW: - srcRegBits, dstRegBits := registerBits(n.srcReg), registerBits(n.dstReg) - - if err = checkRegisterToRegisterType(n.srcReg, n.dstReg, true, true); err != nil { - return - } - - // See "Data-processing (2 source)" in - // https://developer.arm.com/documentation/ddi0602/2021-06/Index-by-Encoding/Data-Processing----Register?lang=en - var sf, opcode byte - switch inst { - case SDIV: - sf, opcode = 0b1, 0b000011 - case SDIVW: - sf, opcode = 0b0, 0b000011 - case UDIV: - sf, opcode = 0b1, 0b000010 - case UDIVW: - sf, opcode = 0b0, 0b000010 - } - - buf.Append4Bytes( - (dstRegBits<<5)|dstRegBits, - opcode<<2|(dstRegBits>>3), - 0b110_00000|srcRegBits, - sf<<7|0b0_00_11010, - ) - - case SCVTFD, SCVTFWD, SCVTFS, SCVTFWS, UCVTFD, UCVTFS, UCVTFWD, UCVTFWS: - srcRegBits, dstRegBits := registerBits(n.srcReg), registerBits(n.dstReg) - - if err = checkRegisterToRegisterType(n.srcReg, n.dstReg, true, false); err != nil { - return - } - - // "Conversion between floating-point and integer" in - // https://developer.arm.com/documentation/ddi0596/2021-12/Index-by-Encoding/Data-Processing----Scalar-Floating-Point-and-Advanced-SIMD?lang=en#floatdp1 - var sf, tp, opcode byte - switch inst { - case SCVTFD: // 64-bit integer to double - sf, tp, opcode = 0b1, 0b01, 0b010 - case SCVTFWD: // 32-bit integer to double - sf, tp, opcode = 0b0, 0b01, 0b010 - case SCVTFS: // 64-bit integer to single - sf, tp, opcode = 0b1, 0b00, 0b010 - case SCVTFWS: // 32-bit integer to single - sf, tp, opcode = 0b0, 0b00, 0b010 - case UCVTFD: // 64-bit to double - sf, tp, opcode = 0b1, 0b01, 0b011 - case UCVTFWD: // 32-bit to double - sf, tp, opcode = 0b0, 0b01, 0b011 - case UCVTFS: // 64-bit to single - sf, tp, opcode = 0b1, 0b00, 0b011 - case UCVTFWS: // 32-bit to single - sf, tp, opcode = 0b0, 0b00, 0b011 - } - - buf.Append4Bytes( - (srcRegBits<<5)|dstRegBits, - srcRegBits>>3, - tp<<6|0b00_1_00_000|opcode, - sf<<7|0b0_0_0_11110, - ) - - case SXTB, SXTBW, SXTH, SXTHW, SXTW: - if err = checkRegisterToRegisterType(n.srcReg, n.dstReg, true, true); err != nil { - return - } - - srcRegBits, dstRegBits := registerBits(n.srcReg), registerBits(n.dstReg) - if n.srcReg == RegRZR { - // If the source is zero register, we encode as MOV dst, zero. - var sf byte - if inst == MOVD { - sf = 0b1 - } - buf.Append4Bytes( - (zeroRegisterBits<<5)|dstRegBits, - zeroRegisterBits>>3, - 0b000_00000|srcRegBits, - sf<<7|0b0_01_01010, - ) - return - } - - // SXTB is encoded as "SBFM Wd, Wn, #0, #7" - // https://developer.arm.com/documentation/dui0801/g/A64-General-Instructions/SXTB - // SXTH is encoded as "SBFM Wd, Wn, #0, #15" - // https://developer.arm.com/documentation/dui0801/g/A64-General-Instructions/SXTH - // SXTW is encoded as "SBFM Xd, Xn, #0, #31" - // https://developer.arm.com/documentation/dui0802/b/A64-General-Instructions/SXTW - - var n, sf, imms, opc byte - switch inst { - case SXTB: - n, sf, imms = 0b1, 0b1, 0x7 - case SXTBW: - n, sf, imms = 0b0, 0b0, 0x7 - case SXTH: - n, sf, imms = 0b1, 0b1, 0xf - case SXTHW: - n, sf, imms = 0b0, 0b0, 0xf - case SXTW: - n, sf, imms = 0b1, 0b1, 0x1f - } - - buf.Append4Bytes( - (srcRegBits<<5)|dstRegBits, - imms<<2|(srcRegBits>>3), - n<<6, - sf<<7|opc<<5|0b10011, - ) - default: - return errorEncodingUnsupported(n) - } - return -} - -func (a *AssemblerImpl) encodeLeftShiftedRegisterToRegister(buf asm.Buffer, n *nodeImpl) error { - baseRegBits, err := intRegisterBits(n.srcReg) - if err != nil { - return err - } - shiftTargetRegBits, err := intRegisterBits(n.srcReg2) - if err != nil { - return err - } - dstRegBits, err := intRegisterBits(n.dstReg) - if err != nil { - return err - } - - switch n.instruction { - case ADD: - // https://developer.arm.com/documentation/ddi0596/2021-12/Index-by-Encoding/Data-Processing----Register?lang=en#addsub_shift - const logicalLeftShiftBits = 0b00 - if n.srcConst < 0 || n.srcConst > 64 { - return fmt.Errorf("shift amount must fit in unsigned 6-bit integer (0-64) but got %d", n.srcConst) - } - shiftByte := byte(n.srcConst) - buf.Append4Bytes( - (baseRegBits<<5)|dstRegBits, - (shiftByte<<2)|(baseRegBits>>3), - (logicalLeftShiftBits<<6)|shiftTargetRegBits, - 0b1000_1011, - ) - return err - default: - return errorEncodingUnsupported(n) - } -} - -func (a *AssemblerImpl) encodeTwoRegistersToRegister(buf asm.Buffer, n *nodeImpl) (err error) { - switch inst := n.instruction; inst { - case AND, ANDW, ORR, ORRW, ORN, ORNW, EOR, EORW: - // See "Logical (shifted register)" in - // https://developer.arm.com/documentation/ddi0596/2021-12/Index-by-Encoding/Data-Processing----Register?lang=en - srcRegBits, srcReg2Bits, dstRegBits := registerBits(n.srcReg), registerBits(n.srcReg2), registerBits(n.dstReg) - var sf, opc, n byte - switch inst { - case AND: - sf, opc = 0b1, 0b00 - case ANDW: - sf, opc = 0b0, 0b00 - case ORR: - sf, opc = 0b1, 0b01 - case ORRW: - sf, opc = 0b0, 0b01 - case ORN: - sf, opc, n = 0b1, 0b01, 0b1 - case ORNW: - sf, opc, n = 0b0, 0b01, 0b1 - case EOR: - sf, opc = 0b1, 0b10 - case EORW: - sf, opc = 0b0, 0b10 - } - buf.Append4Bytes( - (srcReg2Bits<<5)|dstRegBits, - srcReg2Bits>>3, - (n<<5)|srcRegBits, - sf<<7|opc<<5|0b01010, - ) - case ASR, ASRW, LSL, LSLW, LSR, LSRW, ROR, RORW: - // See "Data-processing (2 source)" in - // https://developer.arm.com/documentation/ddi0596/2021-12/Index-by-Encoding/Data-Processing----Register?lang=en - srcRegBits, srcReg2Bits, dstRegBits := registerBits(n.srcReg), registerBits(n.srcReg2), registerBits(n.dstReg) - - var sf, opcode byte - switch inst { - case ASR: - sf, opcode = 0b1, 0b001010 - case ASRW: - sf, opcode = 0b0, 0b001010 - case LSL: - sf, opcode = 0b1, 0b001000 - case LSLW: - sf, opcode = 0b0, 0b001000 - case LSR: - sf, opcode = 0b1, 0b001001 - case LSRW: - sf, opcode = 0b0, 0b001001 - case ROR: - sf, opcode = 0b1, 0b001011 - case RORW: - sf, opcode = 0b0, 0b001011 - } - buf.Append4Bytes( - (srcReg2Bits<<5)|dstRegBits, - opcode<<2|(srcReg2Bits>>3), - 0b110_00000|srcRegBits, - sf<<7|0b0_00_11010, - ) - case SDIV, SDIVW, UDIV, UDIVW: - srcRegBits, srcReg2Bits, dstRegBits := registerBits(n.srcReg), registerBits(n.srcReg2), registerBits(n.dstReg) - - // See "Data-processing (2 source)" in - // https://developer.arm.com/documentation/ddi0602/2021-06/Index-by-Encoding/Data-Processing----Register?lang=en - var sf, opcode byte - switch inst { - case SDIV: - sf, opcode = 0b1, 0b000011 - case SDIVW: - sf, opcode = 0b0, 0b000011 - case UDIV: - sf, opcode = 0b1, 0b000010 - case UDIVW: - sf, opcode = 0b0, 0b000010 - } - - buf.Append4Bytes( - (srcReg2Bits<<5)|dstRegBits, - opcode<<2|(srcReg2Bits>>3), - 0b110_00000|srcRegBits, - sf<<7|0b0_00_11010, - ) - case SUB, SUBW: - srcRegBits, srcReg2Bits, dstRegBits := registerBits(n.srcReg), registerBits(n.srcReg2), registerBits(n.dstReg) - - // See "Add/subtract (shifted register)" in - // https://developer.arm.com/documentation/ddi0596/2021-12/Index-by-Encoding/Data-Processing----Register?lang=en - var sf byte - if inst == SUB { - sf = 0b1 - } - - buf.Append4Bytes( - (srcReg2Bits<<5)|dstRegBits, - srcReg2Bits>>3, - srcRegBits, - sf<<7|0b0_10_01011, - ) - case FSUBD, FSUBS: - srcRegBits, srcReg2Bits, dstRegBits := registerBits(n.srcReg), registerBits(n.srcReg2), registerBits(n.dstReg) - - // See "Floating-point data-processing (2 source)" in - // https://developer.arm.com/documentation/ddi0596/2021-12/Index-by-Encoding/Data-Processing----Scalar-Floating-Point-and-Advanced-SIMD?lang=en - var tp byte - if inst == FSUBD { - tp = 0b01 - } - buf.Append4Bytes( - (srcReg2Bits<<5)|dstRegBits, - 0b0011_10_00|(srcReg2Bits>>3), - tp<<6|0b00_1_00000|srcRegBits, - 0b0_00_11110, - ) - - case LDADDALD, LDADDALW, LDADDALH, LDADDALB, - LDCLRALD, LDCLRALW, LDCLRALH, LDCLRALB, - LDSETALD, LDSETALW, LDSETALH, LDSETALB, - LDEORALD, LDEORALW, LDEORALH, LDEORALB, - SWPALD, SWPALW, SWPALH, SWPALB: - srcRegBits, srcReg2Bits, dstRegBits := registerBits(n.srcReg), registerBits(n.srcReg2), registerBits(n.dstReg) - - // While arm's docs don't group the opcodes together for the arithmetic and swap instructions, they are - // actually identical except for the single bit before the opcode being 1 for swap, so we encode them together. - var size, opcode byte - switch n.instruction { - case LDADDALD: - size, opcode = 0b11, 0b0000 - case LDADDALW: - size, opcode = 0b10, 0b0000 - case LDADDALH: - size, opcode = 0b01, 0b0000 - case LDADDALB: - size, opcode = 0b00, 0b0000 - case LDCLRALD: - size, opcode = 0b11, 0b0001 - case LDCLRALW: - size, opcode = 0b10, 0b0001 - case LDCLRALH: - size, opcode = 0b01, 0b0001 - case LDCLRALB: - size, opcode = 0b00, 0b0001 - case LDSETALD: - size, opcode = 0b11, 0b0011 - case LDSETALW: - size, opcode = 0b10, 0b0011 - case LDSETALH: - size, opcode = 0b01, 0b0011 - case LDSETALB: - size, opcode = 0b00, 0b0011 - case LDEORALD: - size, opcode = 0b11, 0b0010 - case LDEORALW: - size, opcode = 0b10, 0b0010 - case LDEORALH: - size, opcode = 0b01, 0b0010 - case LDEORALB: - size, opcode = 0b00, 0b0010 - case SWPALD: - size, opcode = 0b11, 0b1000 - case SWPALW: - size, opcode = 0b10, 0b1000 - case SWPALH: - size, opcode = 0b01, 0b1000 - case SWPALB: - size, opcode = 0b00, 0b1000 - } - - buf.Append4Bytes( - (srcReg2Bits<<5)|dstRegBits, - (opcode<<4)|(srcReg2Bits>>3), - 0b111_00000|srcRegBits, - (size<<6)|0b00_111_000, - ) - - case CASALD, CASALW, CASALH, CASALB: - srcRegBits, srcReg2Bits, dstRegBits := registerBits(n.srcReg), registerBits(n.srcReg2), registerBits(n.dstReg) - - var size byte - switch n.instruction { - case CASALD: - size = 0b11 - case CASALW: - size = 0b10 - case CASALH: - size = 0b01 - case CASALB: - size = 0b00 - } - - buf.Append4Bytes( - (srcReg2Bits<<5)|dstRegBits, - 0b111111_00|(srcReg2Bits>>3), - 0b111_00000|srcRegBits, - (size<<6)|0b00_001_000, - ) - - default: - return errorEncodingUnsupported(n) - } - return -} - -func (a *AssemblerImpl) encodeThreeRegistersToRegister(buf asm.Buffer, n *nodeImpl) error { - switch n.instruction { - case MSUB, MSUBW: - // Dst = Src2 - (Src1 * Src3) - // "Data-processing (3 source)" in: - // https://developer.arm.com/documentation/ddi0596/2021-12/Index-by-Encoding/Data-Processing----Register?lang=en - src1RegBits, err := intRegisterBits(n.srcReg) - if err != nil { - return err - } - src2RegBits, err := intRegisterBits(n.srcReg2) - if err != nil { - return err - } - src3RegBits, err := intRegisterBits(n.dstReg) - if err != nil { - return err - } - dstRegBits, err := intRegisterBits(n.dstReg2) - if err != nil { - return err - } - - var sf byte // is zero for MSUBW (32-bit MSUB). - if n.instruction == MSUB { - sf = 0b1 - } - - buf.Append4Bytes( - (src3RegBits<<5)|dstRegBits, - 0b1_0000000|(src2RegBits<<2)|(src3RegBits>>3), - src1RegBits, - sf<<7|0b00_11011, - ) - return nil - - default: - return errorEncodingUnsupported(n) - } -} - -func (a *AssemblerImpl) encodeTwoRegistersToNone(buf asm.Buffer, n *nodeImpl) error { - switch n.instruction { - case CMPW, CMP: - // Compare on two registers is an alias for "SUBS (src1, src2) ZERO" - // which can be encoded as SUBS (shifted registers) with zero shifting. - // https://developer.arm.com/documentation/ddi0596/2021-12/Index-by-Encoding/Data-Processing----Register?lang=en#addsub_shift - src1RegBits, err := intRegisterBits(n.srcReg) - if err != nil { - return err - } - src2RegBits, err := intRegisterBits(n.srcReg2) - if err != nil { - return err - } - - var op byte - if n.instruction == CMP { - op = 0b111 - } else { - op = 0b011 - } - - buf.Append4Bytes( - (src2RegBits<<5)|zeroRegisterBits, - src2RegBits>>3, - src1RegBits, - 0b01011|(op<<5), - ) - return nil - case FCMPS, FCMPD: - // "Floating-point compare" section in: - // https://developer.arm.com/documentation/ddi0596/2021-12/Index-by-Encoding/Data-Processing----Scalar-Floating-Point-and-Advanced-SIMD?lang=en - src1RegBits, err := vectorRegisterBits(n.srcReg) - if err != nil { - return err - } - src2RegBits, err := vectorRegisterBits(n.srcReg2) - if err != nil { - return err - } - - var ftype byte // is zero for FCMPS (single precision float compare). - if n.instruction == FCMPD { - ftype = 0b01 - } - buf.Append4Bytes( - src2RegBits<<5, - 0b001000_00|(src2RegBits>>3), - ftype<<6|0b1_00000|src1RegBits, - 0b000_11110, - ) - return nil - default: - return errorEncodingUnsupported(n) - } -} - -func (a *AssemblerImpl) encodeRegisterAndConstToNone(buf asm.Buffer, n *nodeImpl) error { - if n.instruction != CMP { - return errorEncodingUnsupported(n) - } - - // https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/CMP--immediate---Compare--immediate---an-alias-of-SUBS--immediate--?lang=en - if n.srcConst < 0 || n.srcConst > 4095 { - return fmt.Errorf("immediate for CMP must fit in 0 to 4095 but got %d", n.srcConst) - } else if n.srcReg == RegRZR { - return errors.New("zero register is not supported for CMP (immediate)") - } - - srcRegBits, err := intRegisterBits(n.srcReg) - if err != nil { - return err - } - - buf.Append4Bytes( - (srcRegBits<<5)|zeroRegisterBits, - (byte(n.srcConst)<<2)|(srcRegBits>>3), - byte(n.srcConst>>6), - 0b111_10001, - ) - return nil -} - -func fitInSigned9Bits(v int64) bool { - return v >= -256 && v <= 255 -} - -func (a *AssemblerImpl) encodeLoadOrStoreWithRegisterOffset( - buf asm.Buffer, baseRegBits, offsetRegBits, targetRegBits byte, opcode, size, v byte, -) { - // See "Load/store register (register offset)". - // https://developer.arm.com/documentation/ddi0596/2021-12/Index-by-Encoding/Loads-and-Stores?lang=en#ldst_regoff - buf.Append4Bytes( - (baseRegBits<<5)|targetRegBits, - 0b011_010_00|(baseRegBits>>3), - opcode<<6|0b00_1_00000|offsetRegBits, - size<<6|v<<2|0b00_111_0_00, - ) -} - -func (a *AssemblerImpl) encodeLoadOrStoreWithAcquireRelease( - buf asm.Buffer, baseRegBits, targetRegBits byte, l, size byte, -) { - buf.Append4Bytes( - (baseRegBits<<5)|targetRegBits, - 0b1_11111_00|(baseRegBits>>3), - 0b1_0_011111|l<<6, - size<<6|0b00_001000, - ) -} - -// validateMemoryOffset validates the memory offset if the given offset can be encoded in the assembler. -// In theory, offset can be any, but for simplicity of our homemade assembler, we limit the offset range -// that can be encoded enough for supporting compiler. -func validateMemoryOffset(offset int64) error { - if offset > 255 && offset%4 != 0 { - // This is because we only have large offsets for load/store with Wasm value stack or reading type IDs, and its offset - // is always multiplied by 4 or 8 (== the size of uint32 or uint64 == the type of wasm.FunctionTypeID or value stack in Go) - return fmt.Errorf("large memory offset (>255) must be a multiple of 4 but got %d", offset) - } else if offset < -256 { // 9-bit signed integer's minimum = 2^8. - return fmt.Errorf("negative memory offset must be larget than or equal -256 but got %d", offset) - } else if offset > 1<<31-1 { - return fmt.Errorf("large memory offset must be less than %d but got %d", 1<<31-1, offset) - } else { - return nil - } -} - -// encodeLoadOrStoreWithConstOffset encodes load/store instructions with the constant offset. -// -// Note: Encoding strategy intentionally matches the Go assembler: https://go.dev/doc/asm -func (a *AssemblerImpl) encodeLoadOrStoreWithConstOffset( - buf asm.Buffer, - baseRegBits, targetRegBits byte, - offset int64, - opcode, size, v byte, - datasize, datasizeLog2 int64, -) (err error) { - if err = validateMemoryOffset(offset); err != nil { - return - } - - if fitInSigned9Bits(offset) { - // See "LDAPR/STLR (unscaled immediate)" - // https://developer.arm.com/documentation/ddi0596/2021-12/Index-by-Encoding/Loads-and-Stores?lang=en#ldapstl_unscaled - if offset < 0 || offset%datasize != 0 { - // This case is encoded as one "unscaled signed store". - buf.Append4Bytes( - (baseRegBits<<5)|targetRegBits, - byte(offset<<4)|(baseRegBits>>3), - opcode<<6|(0b00_00_11111&byte(offset>>4)), - size<<6|v<<2|0b00_1_11_0_00, - ) - return - } - } - - // At this point we have the assumption that offset is positive. - // Plus if it is a multiple of datasize, then it can be encoded as a single "unsigned immediate". - if offset%datasize == 0 && - offset < (1<<12)<>3), - opcode<<6|0b00_111111&byte(m>>6), - size<<6|v<<2|0b00_1_11_0_01, - ) - return - } - - // Otherwise, we need multiple instructions. - tmpRegBits := registerBits(a.temporaryRegister) - offset32 := int32(offset) - - // Go's assembler adds a const into the const pool at this point, - // regardless of its usage; e.g. if we enter the then block of the following if statement, - // the const is not used but it is added into the const pool. - c := asm.NewStaticConst(make([]byte, 4)) - binary.LittleEndian.PutUint32(c.Raw, uint32(offset)) - a.pool.AddConst(c, uint64(buf.Len())) - - // https://github.com/golang/go/blob/release-branch.go1.15/src/cmd/internal/obj/arm64/asm7.go#L3529-L3532 - // If the offset is within 24-bits, we can load it with two ADD instructions. - hi := offset32 - (offset32 & (0xfff << uint(datasizeLog2))) - if hi&^0xfff000 == 0 { - var sfops byte = 0b100 - m := ((offset32 - hi) >> datasizeLog2) & 0xfff - hi >>= 12 - - // https://github.com/golang/go/blob/release-branch.go1.15/src/cmd/internal/obj/arm64/asm7.go#L3534-L3535 - buf.Append4Bytes( - (baseRegBits<<5)|tmpRegBits, - (byte(hi)<<2)|(baseRegBits>>3), - 0b01<<6 /* shift by 12 */ |byte(hi>>6), - sfops<<5|0b10001, - ) - - buf.Append4Bytes( - (tmpRegBits<<5)|targetRegBits, - (byte(m<<2))|(tmpRegBits>>3), - opcode<<6|0b00_111111&byte(m>>6), - size<<6|v<<2|0b00_1_11_0_01, - ) - } else { - // This case we load the const via ldr(literal) into tem register, - // and the target const is placed after this instruction below. - loadLiteralOffsetInBinary := uint64(buf.Len()) - - // First we emit the ldr(literal) with offset zero as we don't yet know the const's placement in the binary. - // https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/LDR--literal---Load-Register--literal-- - buf.Append4Bytes(tmpRegBits, 0x0, 0x0, 0b00_011_0_00) - - // Set the callback for the constant, and we set properly the offset in the callback. - - c.AddOffsetFinalizedCallback(func(offsetOfConst uint64) { - // ldr(literal) encodes offset divided by 4. - offset := (int(offsetOfConst) - int(loadLiteralOffsetInBinary)) / 4 - bin := buf.Bytes() - bin[loadLiteralOffsetInBinary] |= byte(offset << 5) - bin[loadLiteralOffsetInBinary+1] |= byte(offset >> 3) - bin[loadLiteralOffsetInBinary+2] |= byte(offset >> 11) - }) - - // Then, load the constant with the register offset. - // https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/LDR--register---Load-Register--register-- - buf.Append4Bytes( - (baseRegBits<<5)|targetRegBits, - 0b011_010_00|(baseRegBits>>3), - opcode<<6|0b00_1_00000|tmpRegBits, - size<<6|v<<2|0b00_111_0_00, - ) - } - return -} - -func (a *AssemblerImpl) encodeRegisterToMemory(buf asm.Buffer, n *nodeImpl) (err error) { - // https://developer.arm.com/documentation/ddi0596/2021-12/Index-by-Encoding/Loads-and-Stores?lang=en#ldst_regoff - var ( - size, v byte - datasize, datasizeLog2 int64 - isTargetFloat bool - isRelease bool - ) - switch n.instruction { - case STRD: - size, v, datasize, datasizeLog2 = 0b11, 0x0, 8, 3 - case STRW: - size, v, datasize, datasizeLog2 = 0b10, 0x0, 4, 2 - case STRH: - size, v, datasize, datasizeLog2 = 0b01, 0x0, 2, 1 - case STRB: - size, v, datasize, datasizeLog2 = 0b00, 0x0, 1, 0 - case FSTRD: - size, v, datasize, datasizeLog2, isTargetFloat = 0b11, 0x1, 8, 3, true - case FSTRS: - size, v, datasize, datasizeLog2, isTargetFloat = 0b10, 0x1, 4, 2, true - case STLRD: - size, isRelease = 0b11, true - case STLRW: - size, isRelease = 0b10, true - case STLRH: - size, isRelease = 0b01, true - case STLRB: - size, isRelease = 0b00, true - default: - return errorEncodingUnsupported(n) - } - - var srcRegBits byte - if isTargetFloat { - srcRegBits, err = vectorRegisterBits(n.srcReg) - } else { - srcRegBits, err = intRegisterBits(n.srcReg) - } - if err != nil { - return - } - - baseRegBits, err := intRegisterBits(n.dstReg) - if err != nil { - return err - } - - if isRelease { - a.encodeLoadOrStoreWithAcquireRelease(buf, baseRegBits, srcRegBits, 0, size) - return nil - } - - const opcode = 0x00 // opcode for store instructions. - if n.dstReg2 != asm.NilRegister { - offsetRegBits, err := intRegisterBits(n.dstReg2) - if err != nil { - return err - } - a.encodeLoadOrStoreWithRegisterOffset(buf, baseRegBits, offsetRegBits, srcRegBits, opcode, size, v) - } else { - err = a.encodeLoadOrStoreWithConstOffset(buf, baseRegBits, srcRegBits, n.dstConst, opcode, size, v, datasize, datasizeLog2) - } - return -} - -func (a *AssemblerImpl) encodeADR(buf asm.Buffer, n *nodeImpl) (err error) { - dstRegBits, err := intRegisterBits(n.dstReg) - if err != nil { - return err - } - - adrInstructionOffsetInBinary := uint64(buf.Len()) - - // At this point, we don't yet know the target offset to read from, - // so we emit the ADR instruction with 0 offset, and replace later in the callback. - // https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/ADR--Form-PC-relative-address-?lang=en - buf.Append4Bytes(dstRegBits, 0x0, 0x0, 0b10000) - - // This case, the ADR's target offset is for the staticConst's initial address. - if sc := n.staticConst; sc != nil { - a.pool.AddConst(sc, adrInstructionOffsetInBinary) - sc.AddOffsetFinalizedCallback(func(offsetOfConst uint64) { - adrInstructionBytes := buf.Bytes()[adrInstructionOffsetInBinary : adrInstructionOffsetInBinary+4] - offset := int(offsetOfConst) - int(adrInstructionOffsetInBinary) - - // See https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/ADR--Form-PC-relative-address-?lang=en - adrInstructionBytes[3] |= byte(offset & 0b00000011 << 5) - offset >>= 2 - adrInstructionBytes[0] |= byte(offset << 5) - offset >>= 3 - adrInstructionBytes[1] |= byte(offset) - offset >>= 8 - adrInstructionBytes[2] |= byte(offset) - }) - return - } else { - a.adrInstructionNodes = append(a.adrInstructionNodes, n) - } - return -} - -func (a *AssemblerImpl) finalizeADRInstructionNode(code []byte, n *nodeImpl) (err error) { - // Find the target instruction node. - targetNode := n - for ; targetNode != nil; targetNode = targetNode.next { - if targetNode.instruction == n.readInstructionAddressBeforeTargetInstruction { - targetNode = targetNode.next - break - } - } - - if targetNode == nil { - return fmt.Errorf("BUG: target instruction %s not found for ADR", InstructionName(n.readInstructionAddressBeforeTargetInstruction)) - } - - offset := targetNode.OffsetInBinary() - n.OffsetInBinary() - if i64 := int64(offset); i64 >= 1<<20 || i64 < -1<<20 { - // We could support offset over 20-bit range by special casing them here, - // but 20-bit range should be enough for our impl. If the necessity comes up, - // we could add the special casing here to support arbitrary large offset. - return fmt.Errorf("BUG: too large offset for ADR: %#x", offset) - } - - adrInstructionBytes := code[n.OffsetInBinary() : n.OffsetInBinary()+4] - // According to the binary format of ADR instruction: - // https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/ADR--Form-PC-relative-address-?lang=en - adrInstructionBytes[3] |= byte(offset & 0b00000011 << 5) - offset >>= 2 - adrInstructionBytes[0] |= byte(offset << 5) - offset >>= 3 - adrInstructionBytes[1] |= byte(offset) - offset >>= 8 - adrInstructionBytes[2] |= byte(offset) - return nil -} - -func (a *AssemblerImpl) encodeMemoryToRegister(buf asm.Buffer, n *nodeImpl) (err error) { - // https://developer.arm.com/documentation/ddi0596/2021-12/Index-by-Encoding/Loads-and-Stores?lang=en#ldst_regoff - var ( - size, v, opcode byte - datasize, datasizeLog2 int64 - isTargetFloat bool - isAcquire bool - ) - switch n.instruction { - case ADR: - return a.encodeADR(buf, n) - case FLDRD: - size, v, datasize, datasizeLog2, opcode, isTargetFloat = 0b11, 0x1, 8, 3, 0b01, true - case FLDRS: - size, v, datasize, datasizeLog2, opcode, isTargetFloat = 0b10, 0x1, 4, 2, 0b01, true - case LDRD: - size, v, datasize, datasizeLog2, opcode = 0b11, 0x0, 8, 3, 0b01 - case LDRW: - size, v, datasize, datasizeLog2, opcode = 0b10, 0x0, 4, 2, 0b01 - case LDRSHD: - size, v, datasize, datasizeLog2, opcode = 0b01, 0x0, 2, 1, 0b10 - case LDRSHW: - size, v, datasize, datasizeLog2, opcode = 0b01, 0x0, 2, 1, 0b11 - case LDRH: - size, v, datasize, datasizeLog2, opcode = 0b01, 0x0, 2, 1, 0b01 - case LDRSBD: - size, v, datasize, datasizeLog2, opcode = 0b00, 0x0, 1, 0, 0b10 - case LDRSBW: - size, v, datasize, datasizeLog2, opcode = 0b00, 0x0, 1, 0, 0b11 - case LDRB: - size, v, datasize, datasizeLog2, opcode = 0b00, 0x0, 1, 0, 0b01 - case LDRSW: - size, v, datasize, datasizeLog2, opcode = 0b10, 0x0, 4, 2, 0b10 - case LDARD: - size, isAcquire = 0b11, true - case LDARW: - size, isAcquire = 0b10, true - case LDARH: - size, isAcquire = 0b01, true - case LDARB: - size, isAcquire = 0b00, true - default: - return errorEncodingUnsupported(n) - } - - var dstRegBits byte - if isTargetFloat { - dstRegBits, err = vectorRegisterBits(n.dstReg) - } else { - dstRegBits, err = intRegisterBits(n.dstReg) - } - if err != nil { - return - } - baseRegBits, err := intRegisterBits(n.srcReg) - if err != nil { - return err - } - - if isAcquire { - a.encodeLoadOrStoreWithAcquireRelease(buf, baseRegBits, dstRegBits, 1, size) - return nil - } - - if n.srcReg2 != asm.NilRegister { - offsetRegBits, err := intRegisterBits(n.srcReg2) - if err != nil { - return err - } - a.encodeLoadOrStoreWithRegisterOffset(buf, baseRegBits, offsetRegBits, dstRegBits, opcode, - size, v) - } else { - err = a.encodeLoadOrStoreWithConstOffset(buf, baseRegBits, dstRegBits, n.srcConst, opcode, - size, v, datasize, datasizeLog2) - } - return -} - -// const16bitAligned check if the value is on the 16-bit alignment. -// If so, returns the shift num divided by 16, and otherwise -1. -func const16bitAligned(v int64) (ret int) { - ret = -1 - for s := 0; s < 64; s += 16 { - if (uint64(v) &^ (uint64(0xffff) << uint(s))) == 0 { - ret = s / 16 - break - } - } - return -} - -// isBitMaskImmediate determines if the value can be encoded as "bitmask immediate". -// -// Such an immediate is a 32-bit or 64-bit pattern viewed as a vector of identical elements of size e = 2, 4, 8, 16, 32, or 64 bits. -// Each element contains the same sub-pattern: a single run of 1 to e-1 non-zero bits, rotated by 0 to e-1 bits. -// -// See https://developer.arm.com/documentation/dui0802/b/A64-General-Instructions/MOV--bitmask-immediate- -func isBitMaskImmediate(x uint64) bool { - // All zeros and ones are not "bitmask immediate" by defainition. - if x == 0 || x == 0xffff_ffff_ffff_ffff { - return false - } - - switch { - case x != x>>32|x<<32: - // e = 64 - case x != x>>16|x<<48: - // e = 32 (x == x>>32|x<<32). - // e.g. 0x00ff_ff00_00ff_ff00 - x = uint64(int32(x)) - case x != x>>8|x<<56: - // e = 16 (x == x>>16|x<<48). - // e.g. 0x00ff_00ff_00ff_00ff - x = uint64(int16(x)) - case x != x>>4|x<<60: - // e = 8 (x == x>>8|x<<56). - // e.g. 0x0f0f_0f0f_0f0f_0f0f - x = uint64(int8(x)) - default: - // e = 4 or 2. - return true - } - return sequenceOfSetbits(x) || sequenceOfSetbits(^x) -} - -// sequenceOfSetbits returns true if the number's binary representation is the sequence set bit (1). -// For example: 0b1110 -> true, 0b1010 -> false -func sequenceOfSetbits(x uint64) bool { - y := getLowestBit(x) - // If x is a sequence of set bit, this should results in the number - // with only one set bit (i.e. power of two). - y += x - return (y-1)&y == 0 -} - -func getLowestBit(x uint64) uint64 { - // See https://stackoverflow.com/questions/12247186/find-the-lowest-set-bit - return x & (^x + 1) -} - -func (a *AssemblerImpl) addOrSub64BitRegisters(buf asm.Buffer, sfops byte, sp bool, dstRegBits, src1RegBits, src2RegBits byte) { - // src1Reg = src1Reg +/- src2Reg - if sp { - // https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/ADD--extended-register---Add--extended-register--?lang=en - buf.Append4Bytes( - (src1RegBits<<5)|dstRegBits, - 0b011<<5|src1RegBits>>3, - 1<<5|src2RegBits, - sfops<<5|0b01011, - ) - } else { - buf.Append4Bytes( - (src1RegBits<<5)|dstRegBits, - src1RegBits>>3, - src2RegBits, - sfops<<5|0b01011, - ) - } -} - -func bitmaskImmediate(c uint64, is64bit bool) (immr, imms, N byte) { - var size uint32 - switch { - case c != c>>32|c<<32: - size = 64 - case c != c>>16|c<<48: - size = 32 - c = uint64(int32(c)) - case c != c>>8|c<<56: - size = 16 - c = uint64(int16(c)) - case c != c>>4|c<<60: - size = 8 - c = uint64(int8(c)) - case c != c>>2|c<<62: - size = 4 - c = uint64(int64(c<<60) >> 60) - default: - size = 2 - c = uint64(int64(c<<62) >> 62) - } - - neg := false - if int64(c) < 0 { - c = ^c - neg = true - } - - onesSize, nonZeroPos := getOnesSequenceSize(c) - if neg { - nonZeroPos = onesSize + nonZeroPos - onesSize = size - onesSize - } - - var mode byte = 32 - if is64bit { - N, mode = 0b1, 64 - } - - immr = byte((size - nonZeroPos) & (size - 1) & uint32(mode-1)) - imms = byte((onesSize - 1) | 63&^(size<<1-1)) - return -} - -func (a *AssemblerImpl) encodeConstToRegister(buf asm.Buffer, n *nodeImpl) (err error) { - // Alias for readability. - c := n.srcConst - - dstRegBits, err := intRegisterBits(n.dstReg) - if err != nil { - return err - } - - // See "Logical (immediate)" in - // https://developer.arm.com/documentation/ddi0596/2021-12/Index-by-Encoding/Data-Processing----Immediate - switch n.instruction { - case ANDIMM32, ANDIMM64, ANDSW, ANDS: - if !isBitMaskImmediate(uint64(c)) { - err = fmt.Errorf("const %d must be valid bitmask immediate for %s", c, InstructionName(n.instruction)) - return - } - srcRegBits := dstRegBits - var sf, opc, immr, imms, N byte - switch n.instruction { - case ANDIMM32: - sf, opc = 0b0, 0b00 - immr, imms, N = bitmaskImmediate(uint64(c), false) - case ANDIMM64: - sf, opc = 0b1, 0b00 - immr, imms, N = bitmaskImmediate(uint64(c), true) - case ANDSW: - srcRegBits, err = intRegisterBits(n.srcReg) - if err != nil { - return err - } - sf, opc = 0b0, 0b11 - immr, imms, N = bitmaskImmediate(uint64(c), false) - case ANDS: - srcRegBits, err = intRegisterBits(n.srcReg) - if err != nil { - return err - } - sf, opc = 0b1, 0b11 - immr, imms, N = bitmaskImmediate(uint64(c), true) - } - buf.Append4Bytes( - (srcRegBits<<5)|dstRegBits, - imms<<2|srcRegBits>>3, - N<<6|immr, - sf<<7|opc<<5|0b10010, - ) - return - } - - switch inst := n.instruction; inst { - case ADD, ADDS, SUB, SUBS: - srcRegBits := dstRegBits - if n.srcReg != asm.NilRegister { - srcRegBits, err = intRegisterBits(n.srcReg) - if err != nil { - return err - } - } - - var sfops byte - if inst == ADD { - sfops = 0b100 - } else if inst == ADDS { - sfops = 0b101 - } else if inst == SUB { - sfops = 0b110 - } else if inst == SUBS { - sfops = 0b111 - } - - isSP := n.srcReg == RegSP || n.dstReg == RegSP - if c == 0 { - // If the constant equals zero, we encode it as ADD (register) with zero register. - a.addOrSub64BitRegisters(buf, sfops, isSP, dstRegBits, srcRegBits, zeroRegisterBits) - return - } - - if c >= 0 && (c <= 0xfff || (c&0xfff) == 0 && (uint64(c>>12) <= 0xfff)) { - // If the const can be represented as "imm12" or "imm12 << 12": one instruction - // https://github.com/golang/go/blob/release-branch.go1.15/src/cmd/internal/obj/arm64/asm7.go#L2992 - - if c <= 0xfff { - buf.Append4Bytes( - (srcRegBits<<5)|dstRegBits, - (byte(c)<<2)|(srcRegBits>>3), - byte(c>>6), - sfops<<5|0b10001, - ) - } else { - c >>= 12 - buf.Append4Bytes( - (srcRegBits<<5)|dstRegBits, - (byte(c)<<2)|(srcRegBits>>3), - 0b01<<6 /* shift by 12 */ |byte(c>>6), - sfops<<5|0b10001, - ) - } - return - } - - if t := const16bitAligned(c); t >= 0 { - // If the const can fit within 16-bit alignment, for example, 0xffff, 0xffff_0000 or 0xffff_0000_0000_0000 - // We could load it into temporary with movk. - // https://github.com/golang/go/blob/release-branch.go1.15/src/cmd/internal/obj/arm64/asm7.go#L4029 - tmpRegBits := registerBits(a.temporaryRegister) - - // MOVZ $c, tmpReg with shifting. - a.load16bitAlignedConst(buf, c>>(16*t), byte(t), tmpRegBits, false, true) - - // ADD/SUB tmpReg, dstReg - a.addOrSub64BitRegisters(buf, sfops, isSP, dstRegBits, srcRegBits, tmpRegBits) - return - } else if t := const16bitAligned(^c); t >= 0 { - // Also if the reverse of the const can fit within 16-bit range, do the same ^^. - // https://github.com/golang/go/blob/release-branch.go1.15/src/cmd/internal/obj/arm64/asm7.go#L4029 - tmpRegBits := registerBits(a.temporaryRegister) - - // MOVN $c, tmpReg with shifting. - a.load16bitAlignedConst(buf, ^c>>(16*t), byte(t), tmpRegBits, true, true) - - // ADD/SUB tmpReg, dstReg - a.addOrSub64BitRegisters(buf, sfops, isSP, dstRegBits, srcRegBits, tmpRegBits) - return - } - - if uc := uint64(c); isBitMaskImmediate(uc) { - // If the const can be represented as "bitmask immediate", we load it via ORR into temp register. - // https://github.com/golang/go/blob/release-branch.go1.15/src/cmd/internal/obj/arm64/asm7.go#L6570-L6583 - tmpRegBits := registerBits(a.temporaryRegister) - // OOR $c, tmpReg - a.loadConstViaBitMaskImmediate(buf, uc, tmpRegBits, true) - - // ADD/SUB tmpReg, dstReg - a.addOrSub64BitRegisters(buf, sfops, isSP, dstRegBits, srcRegBits, tmpRegBits) - return - } - - // If the value fits within 24-bit, then we emit two add instructions - if 0 <= c && c <= 0xffffff && inst != SUBS && inst != ADDS { - // https://github.com/golang/go/blob/release-branch.go1.15/src/cmd/internal/obj/arm64/asm7.go#L3849-L3862 - buf.Append4Bytes( - (dstRegBits<<5)|dstRegBits, - (byte(c)<<2)|(dstRegBits>>3), - byte(c&0xfff>>6), - sfops<<5|0b10001, - ) - c = c >> 12 - buf.Append4Bytes( - (dstRegBits<<5)|dstRegBits, - (byte(c)<<2)|(dstRegBits>>3), - 0b01_000000 /* shift by 12 */ |byte(c>>6), - sfops<<5|0b10001, - ) - return - } - - // https://github.com/golang/go/blob/release-branch.go1.15/src/cmd/internal/obj/arm64/asm7.go#L3163-L3203 - // Otherwise we use MOVZ and MOVNs for loading const into tmpRegister. - tmpRegBits := registerBits(a.temporaryRegister) - a.load64bitConst(buf, c, tmpRegBits) - a.addOrSub64BitRegisters(buf, sfops, isSP, dstRegBits, srcRegBits, tmpRegBits) - case MOVW: - if c == 0 { - buf.Append4Bytes( - (zeroRegisterBits<<5)|dstRegBits, - zeroRegisterBits>>3, - 0b000_00000|zeroRegisterBits, - 0b0_01_01010, - ) - return - } - - // Following the logic here: - // https://github.com/golang/go/blob/release-branch.go1.15/src/cmd/internal/obj/arm64/asm7.go#L1637 - c32 := uint32(c) - ic := int64(c32) - if ic >= 0 && (ic <= 0xfff || (ic&0xfff) == 0 && (uint64(ic>>12) <= 0xfff)) { - if isBitMaskImmediate(uint64(c)) { - a.loadConstViaBitMaskImmediate(buf, uint64(c), dstRegBits, false) - return - } - } - - if t := const16bitAligned(int64(c32)); t >= 0 { - // If the const can fit within 16-bit alignment, for example, 0xffff, 0xffff_0000 or 0xffff_0000_0000_0000 - // We could load it into temporary with movk. - a.load16bitAlignedConst(buf, int64(c32)>>(16*t), byte(t), dstRegBits, false, false) - } else if t := const16bitAligned(int64(^c32)); t >= 0 { - // Also, if the reverse of the const can fit within 16-bit range, do the same ^^. - a.load16bitAlignedConst(buf, int64(^c32)>>(16*t), byte(t), dstRegBits, true, false) - } else if isBitMaskImmediate(uint64(c)) { - a.loadConstViaBitMaskImmediate(buf, uint64(c), dstRegBits, false) - } else { - // Otherwise, we use MOVZ and MOVK to load it. - // https://github.com/golang/go/blob/release-branch.go1.15/src/cmd/internal/obj/arm64/asm7.go#L6623-L6630 - c16 := uint16(c32) - // MOVZ: https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/MOVZ - buf.Append4Bytes( - (byte(c16)<<5)|dstRegBits, - byte(c16>>3), - 1<<7|byte(c16>>11), - 0b0_10_10010, - ) - // MOVK: https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/MOVK - c16 = uint16(c32 >> 16) - if c16 != 0 { - buf.Append4Bytes( - (byte(c16)<<5)|dstRegBits, - byte(c16>>3), - 1<<7|0b0_01_00000 /* shift by 16 */ |byte(c16>>11), - 0b0_11_10010, - ) - } - } - case MOVD: - // Following the logic here: - // https://github.com/golang/go/blob/release-branch.go1.15/src/cmd/internal/obj/arm64/asm7.go#L1798-L1852 - if c >= 0 && (c <= 0xfff || (c&0xfff) == 0 && (uint64(c>>12) <= 0xfff)) { - if isBitMaskImmediate(uint64(c)) { - a.loadConstViaBitMaskImmediate(buf, uint64(c), dstRegBits, true) - return - } - } - - if t := const16bitAligned(c); t >= 0 { - // If the const can fit within 16-bit alignment, for example, 0xffff, 0xffff_0000 or 0xffff_0000_0000_0000 - // We could load it into temporary with movk. - a.load16bitAlignedConst(buf, c>>(16*t), byte(t), dstRegBits, false, true) - } else if t := const16bitAligned(^c); t >= 0 { - // Also, if the reverse of the const can fit within 16-bit range, do the same ^^. - a.load16bitAlignedConst(buf, (^c)>>(16*t), byte(t), dstRegBits, true, true) - } else if isBitMaskImmediate(uint64(c)) { - a.loadConstViaBitMaskImmediate(buf, uint64(c), dstRegBits, true) - } else { - a.load64bitConst(buf, c, dstRegBits) - } - case LSR: - if c == 0 { - err = errors.New("LSR with zero constant should be optimized out") - return - } else if c < 0 || c > 63 { - err = fmt.Errorf("LSR requires immediate to be within 0 to 63, but got %d", c) - return - } - - // LSR(immediate) is an alias of UBFM - // https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/LSR--immediate---Logical-Shift-Right--immediate---an-alias-of-UBFM-?lang=en - buf.Append4Bytes( - (dstRegBits<<5)|dstRegBits, - 0b111111_00|dstRegBits>>3, - 0b01_000000|byte(c), - 0b110_10011, - ) - case LSL: - if c == 0 { - err = errors.New("LSL with zero constant should be optimized out") - return - } else if c < 0 || c > 63 { - err = fmt.Errorf("LSL requires immediate to be within 0 to 63, but got %d", c) - return - } - - // LSL(immediate) is an alias of UBFM - // https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/LSL--immediate---Logical-Shift-Left--immediate---an-alias-of-UBFM- - cb := byte(c) - buf.Append4Bytes( - (dstRegBits<<5)|dstRegBits, - (0b111111-cb)<<2|dstRegBits>>3, - 0b01_000000|(64-cb), - 0b110_10011, - ) - - default: - return errorEncodingUnsupported(n) - } - return -} - -func (a *AssemblerImpl) movk(buf asm.Buffer, v uint64, shfitNum int, dstRegBits byte) { - // https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/MOVK - buf.Append4Bytes( - (byte(v)<<5)|dstRegBits, - byte(v>>3), - 1<<7|byte(shfitNum)<<5|(0b000_11111&byte(v>>11)), - 0b1_11_10010, - ) -} - -func (a *AssemblerImpl) movz(buf asm.Buffer, v uint64, shfitNum int, dstRegBits byte) { - // https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/MOVZ - buf.Append4Bytes( - (byte(v)<<5)|dstRegBits, - byte(v>>3), - 1<<7|byte(shfitNum)<<5|(0b000_11111&byte(v>>11)), - 0b1_10_10010, - ) -} - -func (a *AssemblerImpl) movn(buf asm.Buffer, v uint64, shfitNum int, dstRegBits byte) { - // https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/MOVZ - buf.Append4Bytes( - (byte(v)<<5)|dstRegBits, - byte(v>>3), - 1<<7|byte(shfitNum)<<5|(0b000_11111&byte(v>>11)), - 0b1_00_10010, - ) -} - -// load64bitConst loads a 64-bit constant into the register, following the same logic to decide how to load large 64-bit -// consts as in the Go assembler. -// -// See https://github.com/golang/go/blob/release-branch.go1.15/src/cmd/internal/obj/arm64/asm7.go#L6632-L6759 -func (a *AssemblerImpl) load64bitConst(buf asm.Buffer, c int64, dstRegBits byte) { - var bits [4]uint64 - var zeros, negs int - for i := 0; i < 4; i++ { - bits[i] = uint64((c >> uint(i*16)) & 0xffff) - if v := bits[i]; v == 0 { - zeros++ - } else if v == 0xffff { - negs++ - } - } - - if zeros == 3 { - // one MOVZ instruction. - for i, v := range bits { - if v != 0 { - a.movz(buf, v, i, dstRegBits) - } - } - } else if negs == 3 { - // one MOVN instruction. - for i, v := range bits { - if v != 0xffff { - v = ^v - a.movn(buf, v, i, dstRegBits) - } - } - } else if zeros == 2 { - // one MOVZ then one OVK. - var movz bool - for i, v := range bits { - if !movz && v != 0 { // MOVZ. - // https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/MOVZ - a.movz(buf, v, i, dstRegBits) - movz = true - } else if v != 0 { - a.movk(buf, v, i, dstRegBits) - } - } - - } else if negs == 2 { - // one MOVN then one or two MOVK. - var movn bool - for i, v := range bits { // Emit MOVN. - if !movn && v != 0xffff { - v = ^v - // https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/MOVN - a.movn(buf, v, i, dstRegBits) - movn = true - } else if v != 0xffff { - a.movk(buf, v, i, dstRegBits) - } - } - - } else if zeros == 1 { - // one MOVZ then two MOVK. - var movz bool - for i, v := range bits { - if !movz && v != 0 { // MOVZ. - // https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/MOVZ - a.movz(buf, v, i, dstRegBits) - movz = true - } else if v != 0 { - a.movk(buf, v, i, dstRegBits) - } - } - - } else if negs == 1 { - // one MOVN then two MOVK. - var movn bool - for i, v := range bits { // Emit MOVN. - if !movn && v != 0xffff { - v = ^v - // https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/MOVN - a.movn(buf, v, i, dstRegBits) - movn = true - } else if v != 0xffff { - a.movk(buf, v, i, dstRegBits) - } - } - - } else { - // one MOVZ then tree MOVK. - var movz bool - for i, v := range bits { - if !movz && v != 0 { // MOVZ. - // https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/MOVZ - a.movz(buf, v, i, dstRegBits) - movz = true - } else if v != 0 { - a.movk(buf, v, i, dstRegBits) - } - } - - } -} - -func (a *AssemblerImpl) load16bitAlignedConst(buf asm.Buffer, c int64, shiftNum byte, regBits byte, reverse bool, dst64bit bool) { - var lastByte byte - if reverse { - // MOVN: https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/MOVZ - lastByte = 0b0_00_10010 - } else { - // MOVZ: https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/MOVN - lastByte = 0b0_10_10010 - } - if dst64bit { - lastByte |= 0b1 << 7 - } - buf.Append4Bytes( - (byte(c)<<5)|regBits, - byte(c>>3), - 1<<7|(shiftNum<<5)|byte(c>>11), - lastByte, - ) -} - -// loadConstViaBitMaskImmediate loads the constant with ORR (bitmask immediate). -// https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/ORR--immediate---Bitwise-OR--immediate--?lang=en -func (a *AssemblerImpl) loadConstViaBitMaskImmediate(buf asm.Buffer, c uint64, regBits byte, dst64bit bool) { - var size uint32 - switch { - case c != c>>32|c<<32: - size = 64 - case c != c>>16|c<<48: - size = 32 - c = uint64(int32(c)) - case c != c>>8|c<<56: - size = 16 - c = uint64(int16(c)) - case c != c>>4|c<<60: - size = 8 - c = uint64(int8(c)) - case c != c>>2|c<<62: - size = 4 - c = uint64(int64(c<<60) >> 60) - default: - size = 2 - c = uint64(int64(c<<62) >> 62) - } - - neg := false - if int64(c) < 0 { - c = ^c - neg = true - } - - onesSize, nonZeroPos := getOnesSequenceSize(c) - if neg { - nonZeroPos = onesSize + nonZeroPos - onesSize = size - onesSize - } - - // See the following article for understanding the encoding. - // https://dinfuehr.github.io/blog/encoding-of-immediate-values-on-aarch64/ - var n byte - mode := 32 - if dst64bit && size == 64 { - n = 0b1 - mode = 64 - } - - r := byte((size - nonZeroPos) & (size - 1) & uint32(mode-1)) - s := byte((onesSize - 1) | 63&^(size<<1-1)) - - var sf byte - if dst64bit { - sf = 0b1 - } - buf.Append4Bytes( - (zeroRegisterBits<<5)|regBits, - s<<2|(zeroRegisterBits>>3), - n<<6|r, - sf<<7|0b0_01_10010, - ) -} - -func getOnesSequenceSize(x uint64) (size, nonZeroPos uint32) { - // Take 0b00111000 for example: - y := getLowestBit(x) // = 0b0000100 - nonZeroPos = setBitPos(y) // = 2 - size = setBitPos(x+y) - nonZeroPos // = setBitPos(0b0100000) - 2 = 5 - 2 = 3 - return -} - -func setBitPos(x uint64) (ret uint32) { - for ; ; ret++ { - if x == 0b1 { - break - } - x = x >> 1 - } - return -} - -func checkArrangementIndexPair(arr VectorArrangement, index VectorIndex) (err error) { - if arr == VectorArrangementNone { - return nil - } - var valid bool - switch arr { - case VectorArrangement8B: - valid = index < 8 - case VectorArrangement16B: - valid = index < 16 - case VectorArrangement4H: - valid = index < 4 - case VectorArrangement8H: - valid = index < 8 - case VectorArrangement2S: - valid = index < 2 - case VectorArrangement4S: - valid = index < 4 - case VectorArrangement1D: - valid = index < 1 - case VectorArrangement2D: - valid = index < 2 - case VectorArrangementB: - valid = index < 16 - case VectorArrangementH: - valid = index < 8 - case VectorArrangementS: - valid = index < 4 - case VectorArrangementD: - valid = index < 2 - } - if !valid { - err = fmt.Errorf("invalid arrangement and index pair: %s[%d]", arr, index) - } - return -} - -func (a *AssemblerImpl) encodeMemoryToVectorRegister(buf asm.Buffer, n *nodeImpl) (err error) { - srcBaseRegBits, err := intRegisterBits(n.srcReg) - if err != nil { - return err - } - - dstVectorRegBits, err := vectorRegisterBits(n.dstReg) - if err != nil { - return err - } - - switch n.instruction { - case VMOV: // translated as LDR(immediate,SIMD&FP) - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/LDR--immediate--SIMD-FP---Load-SIMD-FP-Register--immediate-offset--?lang=en - var size, opcode byte - var dataSize, dataSizeLog2 int64 - switch n.vectorArrangement { - case VectorArrangementB: - size, opcode, dataSize, dataSizeLog2 = 0b00, 0b01, 1, 0 - case VectorArrangementH: - size, opcode, dataSize, dataSizeLog2 = 0b01, 0b01, 2, 1 - case VectorArrangementS: - size, opcode, dataSize, dataSizeLog2 = 0b10, 0b01, 4, 2 - case VectorArrangementD: - size, opcode, dataSize, dataSizeLog2 = 0b11, 0b01, 8, 3 - case VectorArrangementQ: - size, opcode, dataSize, dataSizeLog2 = 0b00, 0b11, 16, 4 - } - const v = 1 // v as in https://developer.arm.com/documentation/ddi0596/2021-12/Index-by-Encoding/Loads-and-Stores?lang=en#ldst_pos - if n.srcReg2 != asm.NilRegister { - offsetRegBits, err := intRegisterBits(n.srcReg2) - if err != nil { - return err - } - a.encodeLoadOrStoreWithRegisterOffset(buf, srcBaseRegBits, offsetRegBits, dstVectorRegBits, opcode, size, v) - } else { - err = a.encodeLoadOrStoreWithConstOffset(buf, srcBaseRegBits, dstVectorRegBits, - n.srcConst, opcode, size, v, dataSize, dataSizeLog2) - } - case LD1R: - if n.srcReg2 != asm.NilRegister || n.srcConst != 0 { - return fmt.Errorf("offset for %s is not implemented", InstructionName(LD1R)) - } - - var size, q byte - switch n.vectorArrangement { - case VectorArrangement8B: - size, q = 0b00, 0b0 - case VectorArrangement16B: - size, q = 0b00, 0b1 - case VectorArrangement4H: - size, q = 0b01, 0b0 - case VectorArrangement8H: - size, q = 0b01, 0b1 - case VectorArrangement2S: - size, q = 0b10, 0b0 - case VectorArrangement4S: - size, q = 0b10, 0b1 - case VectorArrangement1D: - size, q = 0b11, 0b0 - case VectorArrangement2D: - size, q = 0b11, 0b1 - } - - // No offset encoding. - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/LD1R--Load-one-single-element-structure-and-Replicate-to-all-lanes--of-one-register--?lang=en#iclass_as_post_index - buf.Append4Bytes( - (srcBaseRegBits<<5)|dstVectorRegBits, - 0b11_000000|size<<2|srcBaseRegBits>>3, - 0b01_000000, - q<<6|0b1101, - ) - default: - return errorEncodingUnsupported(n) - } - return -} - -func arrangementSizeQ(arr VectorArrangement) (size, q byte) { - switch arr { - case VectorArrangement8B: - size, q = 0b00, 0 - case VectorArrangement16B: - size, q = 0b00, 1 - case VectorArrangement4H: - size, q = 0b01, 0 - case VectorArrangement8H: - size, q = 0b01, 1 - case VectorArrangement2S: - size, q = 0b10, 0 - case VectorArrangement4S: - size, q = 0b10, 1 - case VectorArrangement1D: - size, q = 0b11, 0 - case VectorArrangement2D: - size, q = 0b11, 1 - } - return -} - -func (a *AssemblerImpl) encodeVectorRegisterToMemory(buf asm.Buffer, n *nodeImpl) (err error) { - srcVectorRegBits, err := vectorRegisterBits(n.srcReg) - if err != nil { - return err - } - - dstBaseRegBits, err := intRegisterBits(n.dstReg) - if err != nil { - return err - } - - switch n.instruction { - case VMOV: // translated as STR(immediate,SIMD&FP) - // https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/STR--immediate--SIMD-FP---Store-SIMD-FP-register--immediate-offset-- - var size, opcode byte - var dataSize, dataSizeLog2 int64 - switch n.vectorArrangement { - case VectorArrangementB: - size, opcode, dataSize, dataSizeLog2 = 0b00, 0b00, 1, 0 - case VectorArrangementH: - size, opcode, dataSize, dataSizeLog2 = 0b01, 0b00, 2, 1 - case VectorArrangementS: - size, opcode, dataSize, dataSizeLog2 = 0b10, 0b00, 4, 2 - case VectorArrangementD: - size, opcode, dataSize, dataSizeLog2 = 0b11, 0b00, 8, 3 - case VectorArrangementQ: - size, opcode, dataSize, dataSizeLog2 = 0b00, 0b10, 16, 4 - } - const v = 1 // v as in https://developer.arm.com/documentation/ddi0596/2021-12/Index-by-Encoding/Loads-and-Stores?lang=en#ldst_pos - - if n.dstReg2 != asm.NilRegister { - offsetRegBits, err := intRegisterBits(n.dstReg2) - if err != nil { - return err - } - a.encodeLoadOrStoreWithRegisterOffset(buf, dstBaseRegBits, offsetRegBits, srcVectorRegBits, opcode, size, v) - } else { - err = a.encodeLoadOrStoreWithConstOffset(buf, dstBaseRegBits, srcVectorRegBits, - n.dstConst, opcode, size, v, dataSize, dataSizeLog2) - } - default: - return errorEncodingUnsupported(n) - } - return -} - -func (a *AssemblerImpl) encodeStaticConstToVectorRegister(buf asm.Buffer, n *nodeImpl) (err error) { - if n.instruction != VMOV { - return errorEncodingUnsupported(n) - } - - dstRegBits, err := vectorRegisterBits(n.dstReg) - if err != nil { - return err - } - - // LDR (literal, SIMD&FP) - // https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/LDR--literal--SIMD-FP---Load-SIMD-FP-Register--PC-relative-literal-- - var opc byte - var constLength int - switch n.vectorArrangement { - case VectorArrangementS: - opc, constLength = 0b00, 4 - case VectorArrangementD: - opc, constLength = 0b01, 8 - case VectorArrangementQ: - opc, constLength = 0b10, 16 - } - - loadLiteralOffsetInBinary := uint64(buf.Len()) - a.pool.AddConst(n.staticConst, loadLiteralOffsetInBinary) - - if len(n.staticConst.Raw) != constLength { - return fmt.Errorf("invalid const length for %s: want %d but was %d", - n.vectorArrangement, constLength, len(n.staticConst.Raw)) - } - - buf.Append4Bytes(dstRegBits, 0x0, 0x0, opc<<6|0b11100) - n.staticConst.AddOffsetFinalizedCallback(func(offsetOfConst uint64) { - // LDR (literal, SIMD&FP) encodes offset divided by 4. - offset := (int(offsetOfConst) - int(loadLiteralOffsetInBinary)) / 4 - bin := buf.Bytes() - bin[loadLiteralOffsetInBinary] |= byte(offset << 5) - bin[loadLiteralOffsetInBinary+1] |= byte(offset >> 3) - bin[loadLiteralOffsetInBinary+2] |= byte(offset >> 11) - }) - return -} - -// advancedSIMDTwoRegisterMisc holds information to encode instructions as "Advanced SIMD two-register miscellaneous" in -// https://developer.arm.com/documentation/ddi0596/2021-12/Index-by-Encoding/Data-Processing----Scalar-Floating-Point-and-Advanced-SIMD?lang=en -var advancedSIMDTwoRegisterMisc = map[asm.Instruction]struct { - qAndSize map[VectorArrangement]qAndSize - u, opcode byte -}{ - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/NOT--Bitwise-NOT--vector--?lang=en - NOT: { - u: 0b1, opcode: 0b00101, - qAndSize: map[VectorArrangement]qAndSize{ - VectorArrangement16B: {size: 0b00, q: 0b1}, - VectorArrangement8B: {size: 0b00, q: 0b0}, - }, - }, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FNEG--vector---Floating-point-Negate--vector--?lang=en - VFNEG: { - u: 0b1, opcode: 0b01111, - qAndSize: map[VectorArrangement]qAndSize{ - VectorArrangement4S: {size: 0b10, q: 0b1}, - VectorArrangement2S: {size: 0b10, q: 0b0}, - VectorArrangement2D: {size: 0b11, q: 0b1}, - }, - }, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FABS--vector---Floating-point-Absolute-value--vector--?lang=en - VFABS: {u: 0, opcode: 0b01111, qAndSize: map[VectorArrangement]qAndSize{ - VectorArrangement2D: {size: 0b11, q: 0b1}, - VectorArrangement4S: {size: 0b10, q: 0b1}, - VectorArrangement2S: {size: 0b10, q: 0b0}, - }}, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FSQRT--vector---Floating-point-Square-Root--vector--?lang=en - VFSQRT: {u: 1, opcode: 0b11111, qAndSize: map[VectorArrangement]qAndSize{ - VectorArrangement2D: {size: 0b11, q: 0b1}, - VectorArrangement4S: {size: 0b10, q: 0b1}, - VectorArrangement2S: {size: 0b10, q: 0b0}, - }}, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FRINTM--vector---Floating-point-Round-to-Integral--toward-Minus-infinity--vector--?lang=en - VFRINTM: {u: 0, opcode: 0b11001, qAndSize: map[VectorArrangement]qAndSize{ - VectorArrangement2D: {size: 0b01, q: 0b1}, - VectorArrangement4S: {size: 0b00, q: 0b1}, - VectorArrangement2S: {size: 0b00, q: 0b0}, - }}, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FRINTN--vector---Floating-point-Round-to-Integral--to-nearest-with-ties-to-even--vector--?lang=en - VFRINTN: {u: 0, opcode: 0b11000, qAndSize: map[VectorArrangement]qAndSize{ - VectorArrangement2D: {size: 0b01, q: 0b1}, - VectorArrangement4S: {size: 0b00, q: 0b1}, - VectorArrangement2S: {size: 0b00, q: 0b0}, - }}, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FRINTP--vector---Floating-point-Round-to-Integral--toward-Plus-infinity--vector--?lang=en - VFRINTP: {u: 0, opcode: 0b11000, qAndSize: map[VectorArrangement]qAndSize{ - VectorArrangement2D: {size: 0b11, q: 0b1}, - VectorArrangement4S: {size: 0b10, q: 0b1}, - VectorArrangement2S: {size: 0b10, q: 0b0}, - }}, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FRINTZ--vector---Floating-point-Round-to-Integral--toward-Zero--vector--?lang=en - VFRINTZ: {u: 0, opcode: 0b11001, qAndSize: map[VectorArrangement]qAndSize{ - VectorArrangement2D: {size: 0b11, q: 0b1}, - VectorArrangement4S: {size: 0b10, q: 0b1}, - VectorArrangement2S: {size: 0b10, q: 0b0}, - }}, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/CNT--Population-Count-per-byte-?lang=en - VCNT: {u: 0b0, opcode: 0b00101, qAndSize: map[VectorArrangement]qAndSize{ - VectorArrangement8B: {size: 0b00, q: 0b0}, - VectorArrangement16B: {size: 0b00, q: 0b1}, - }}, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/NEG--vector---Negate--vector--?lang=en - VNEG: {u: 0b1, opcode: 0b01011, qAndSize: defaultQAndSize}, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/ABS--Absolute-value--vector--?lang=en - VABS: {u: 0b0, opcode: 0b01011, qAndSize: defaultQAndSize}, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/REV64--Reverse-elements-in-64-bit-doublewords--vector--?lang=en - REV64: {u: 0b0, opcode: 0b00000, qAndSize: defaultQAndSize}, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/XTN--XTN2--Extract-Narrow-?lang=en - XTN: {u: 0b0, opcode: 0b10010, qAndSize: map[VectorArrangement]qAndSize{ - VectorArrangement2D: {q: 0, size: 0b10}, - VectorArrangement4S: {q: 0, size: 0b01}, - VectorArrangement8H: {q: 0, size: 0b00}, - }}, - SHLL: {u: 0b1, opcode: 0b10011, qAndSize: map[VectorArrangement]qAndSize{ - VectorArrangement8B: {q: 0b00, size: 0b00}, - VectorArrangement4H: {q: 0b00, size: 0b01}, - VectorArrangement2S: {q: 0b00, size: 0b10}, - }}, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/CMEQ--zero---Compare-bitwise-Equal-to-zero--vector--?lang=en - CMEQZERO: {u: 0b0, opcode: 0b01001, qAndSize: defaultQAndSize}, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SADDLP--Signed-Add-Long-Pairwise-?lang=en - SADDLP: {u: 0b0, opcode: 0b00010, qAndSize: defaultQAndSize}, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UADDLP--Unsigned-Add-Long-Pairwise-?lang=en - UADDLP: {u: 0b1, opcode: 0b00010, qAndSize: defaultQAndSize}, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FCVTZS--vector--integer---Floating-point-Convert-to-Signed-integer--rounding-toward-Zero--vector--?lang=en - VFCVTZS: {u: 0b0, opcode: 0b11011, qAndSize: map[VectorArrangement]qAndSize{ - VectorArrangement4S: {size: 0b10, q: 0b1}, - VectorArrangement2S: {size: 0b10, q: 0b0}, - VectorArrangement2D: {size: 0b11, q: 0b1}, - }}, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FCVTZU--vector--integer---Floating-point-Convert-to-Unsigned-integer--rounding-toward-Zero--vector--?lang=en - VFCVTZU: {u: 0b1, opcode: 0b11011, qAndSize: map[VectorArrangement]qAndSize{ - VectorArrangement4S: {size: 0b10, q: 0b1}, - VectorArrangement2S: {size: 0b10, q: 0b0}, - VectorArrangement2D: {size: 0b11, q: 0b1}, - }}, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SQXTN--SQXTN2--Signed-saturating-extract-Narrow-?lang=en - SQXTN: {u: 0b0, opcode: 0b10100, qAndSize: map[VectorArrangement]qAndSize{ - VectorArrangement8B: {q: 0b0, size: 0b00}, - VectorArrangement4H: {q: 0b0, size: 0b01}, - VectorArrangement2S: {q: 0b0, size: 0b10}, - }}, - - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SQXTN--SQXTN2--Signed-saturating-extract-Narrow-?lang=en - SQXTN2: {u: 0b0, opcode: 0b10100, qAndSize: map[VectorArrangement]qAndSize{ - VectorArrangement16B: {q: 0b1, size: 0b00}, - VectorArrangement8H: {q: 0b1, size: 0b01}, - VectorArrangement4S: {q: 0b1, size: 0b10}, - }}, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UQXTN--UQXTN2--Unsigned-saturating-extract-Narrow-?lang=en - UQXTN: {u: 0b1, opcode: 0b10100, qAndSize: defaultQAndSize}, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SQXTUN--SQXTUN2--Signed-saturating-extract-Unsigned-Narrow-?lang=en - SQXTUN: {u: 0b1, opcode: 0b10010, qAndSize: map[VectorArrangement]qAndSize{ - VectorArrangement8B: {q: 0b0, size: 0b00}, - VectorArrangement4H: {q: 0b0, size: 0b01}, - VectorArrangement2S: {q: 0b0, size: 0b10}, - }}, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SQXTUN--SQXTUN2--Signed-saturating-extract-Unsigned-Narrow-?lang=en - SQXTUN2: {u: 0b1, opcode: 0b10010, qAndSize: map[VectorArrangement]qAndSize{ - VectorArrangement16B: {q: 0b1, size: 0b00}, - VectorArrangement8H: {q: 0b1, size: 0b01}, - VectorArrangement4S: {q: 0b1, size: 0b10}, - }}, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SCVTF--vector--integer---Signed-integer-Convert-to-Floating-point--vector--?lang=en - VSCVTF: {u: 0b0, opcode: 0b11101, qAndSize: map[VectorArrangement]qAndSize{ - VectorArrangement2D: {q: 0b1, size: 0b01}, - VectorArrangement4S: {q: 0b1, size: 0b00}, - VectorArrangement2S: {q: 0b0, size: 0b00}, - }}, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UCVTF--vector--integer---Unsigned-integer-Convert-to-Floating-point--vector--?lang=en - VUCVTF: {u: 0b1, opcode: 0b11101, qAndSize: map[VectorArrangement]qAndSize{ - VectorArrangement2D: {q: 0b1, size: 0b01}, - VectorArrangement4S: {q: 0b1, size: 0b00}, - VectorArrangement2S: {q: 0b0, size: 0b00}, - }}, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FCVTL--FCVTL2--Floating-point-Convert-to-higher-precision-Long--vector--?lang=en - FCVTL: {u: 0b0, opcode: 0b10111, qAndSize: map[VectorArrangement]qAndSize{ - VectorArrangement2S: {size: 0b01, q: 0b0}, - VectorArrangement4H: {size: 0b00, q: 0b0}, - }}, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FCVTN--FCVTN2--Floating-point-Convert-to-lower-precision-Narrow--vector--?lang=en - FCVTN: {u: 0b0, opcode: 0b10110, qAndSize: map[VectorArrangement]qAndSize{ - VectorArrangement2S: {size: 0b01, q: 0b0}, - VectorArrangement4H: {size: 0b00, q: 0b0}, - }}, -} - -// advancedSIMDThreeDifferent holds information to encode instructions as "Advanced SIMD three different" in -// https://developer.arm.com/documentation/ddi0596/2021-12/Index-by-Encoding/Data-Processing----Scalar-Floating-Point-and-Advanced-SIMD?lang=en -var advancedSIMDThreeDifferent = map[asm.Instruction]struct { - qAndSize map[VectorArrangement]qAndSize - u, opcode byte -}{ - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UMLAL--UMLAL2--vector---Unsigned-Multiply-Add-Long--vector--?lang=en - VUMLAL: {u: 0b1, opcode: 0b1000, qAndSize: map[VectorArrangement]qAndSize{ - VectorArrangement2S: {q: 0b0, size: 0b10}, - VectorArrangement4H: {q: 0b0, size: 0b01}, - VectorArrangement8B: {q: 0b0, size: 0b00}, - }}, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SMULL--SMULL2--vector---Signed-Multiply-Long--vector--?lang=en - SMULL: {u: 0b0, opcode: 0b1100, qAndSize: map[VectorArrangement]qAndSize{ - VectorArrangement8B: {q: 0b0, size: 0b00}, - VectorArrangement4H: {q: 0b0, size: 0b01}, - VectorArrangement2S: {q: 0b0, size: 0b10}, - }}, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SMULL--SMULL2--vector---Signed-Multiply-Long--vector--?lang=en - SMULL2: {u: 0b0, opcode: 0b1100, qAndSize: map[VectorArrangement]qAndSize{ - VectorArrangement16B: {q: 0b1, size: 0b00}, - VectorArrangement8H: {q: 0b1, size: 0b01}, - VectorArrangement4S: {q: 0b1, size: 0b10}, - }}, - // https://developer.arm.com/documentation/ddi0596/2021-12/Index-by-Encoding/Data-Processing----Scalar-Floating-Point-and-Advanced-SIMD?lang=en - UMULL: {u: 0b1, opcode: 0b1100, qAndSize: map[VectorArrangement]qAndSize{ - VectorArrangement8B: {q: 0b0, size: 0b00}, - VectorArrangement4H: {q: 0b0, size: 0b01}, - VectorArrangement2S: {q: 0b0, size: 0b10}, - }}, - // https://developer.arm.com/documentation/ddi0596/2021-12/Index-by-Encoding/Data-Processing----Scalar-Floating-Point-and-Advanced-SIMD?lang=en - UMULL2: {u: 0b1, opcode: 0b1100, qAndSize: map[VectorArrangement]qAndSize{ - VectorArrangement16B: {q: 0b1, size: 0b00}, - VectorArrangement8H: {q: 0b1, size: 0b01}, - VectorArrangement4S: {q: 0b1, size: 0b10}, - }}, -} - -// advancedSIMDThreeSame holds information to encode instructions as "Advanced SIMD three same" in -// https://developer.arm.com/documentation/ddi0596/2021-12/Index-by-Encoding/Data-Processing----Scalar-Floating-Point-and-Advanced-SIMD?lang=en -var advancedSIMDThreeSame = map[asm.Instruction]struct { - qAndSize map[VectorArrangement]qAndSize - u, opcode byte -}{ - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/AND--vector---Bitwise-AND--vector--?lang=en - VAND: { - u: 0b0, opcode: 0b00011, - qAndSize: map[VectorArrangement]qAndSize{ - VectorArrangement16B: {size: 0b00, q: 0b1}, - VectorArrangement8B: {size: 0b00, q: 0b0}, - }, - }, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/BSL--Bitwise-Select-?lang=en - BSL: { - u: 0b1, opcode: 0b00011, - qAndSize: map[VectorArrangement]qAndSize{ - VectorArrangement16B: {size: 0b01, q: 0b1}, - VectorArrangement8B: {size: 0b01, q: 0b0}, - }, - }, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/EOR--vector---Bitwise-Exclusive-OR--vector--?lang=en - EOR: { - u: 0b1, opcode: 0b00011, - qAndSize: map[VectorArrangement]qAndSize{ - VectorArrangement16B: {size: 0b00, q: 0b1}, - VectorArrangement8B: {size: 0b00, q: 0b0}, - }, - }, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/ORR--vector--register---Bitwise-inclusive-OR--vector--register--?lang=en - VORR: { - u: 0b0, opcode: 0b00011, - qAndSize: map[VectorArrangement]qAndSize{ - VectorArrangement16B: {size: 0b10, q: 0b1}, - VectorArrangement8B: {size: 0b10, q: 0b0}, - }, - }, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/BIC--vector--register---Bitwise-bit-Clear--vector--register--?lang=en - BIC: { - u: 0b0, opcode: 0b00011, - qAndSize: map[VectorArrangement]qAndSize{ - VectorArrangement16B: {size: 0b01, q: 0b1}, - VectorArrangement8B: {size: 0b01, q: 0b0}, - }, - }, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FADD--vector---Floating-point-Add--vector--?lang=en - VFADDS: { - u: 0b0, opcode: 0b11010, - qAndSize: map[VectorArrangement]qAndSize{ - VectorArrangement4S: {size: 0b00, q: 0b1}, - VectorArrangement2S: {size: 0b00, q: 0b0}, - }, - }, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FADD--vector---Floating-point-Add--vector--?lang=en - VFADDD: { - u: 0b0, opcode: 0b11010, - qAndSize: map[VectorArrangement]qAndSize{ - VectorArrangement2D: {size: 0b01, q: 0b1}, - }, - }, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FSUB--vector---Floating-point-Subtract--vector--?lang=en - VFSUBS: { - u: 0b0, opcode: 0b11010, - qAndSize: map[VectorArrangement]qAndSize{ - VectorArrangement4S: {size: 0b10, q: 0b1}, - VectorArrangement2S: {size: 0b10, q: 0b0}, - }, - }, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FSUB--vector---Floating-point-Subtract--vector--?lang=en - VFSUBD: { - u: 0b0, opcode: 0b11010, - qAndSize: map[VectorArrangement]qAndSize{ - VectorArrangement2D: {size: 0b11, q: 0b1}, - }, - }, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UMAXP--Unsigned-Maximum-Pairwise-?lang=en - UMAXP: {u: 0b1, opcode: 0b10100, qAndSize: defaultQAndSize}, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/CMEQ--register---Compare-bitwise-Equal--vector--?lang=en - CMEQ: {u: 0b1, opcode: 0b10001, qAndSize: defaultQAndSize}, - // https://developer.arm.com/documentation/dui0801/g/A64-SIMD-Vector-Instructions/ADDP--vector- - VADDP: {u: 0b0, opcode: 0b10111, qAndSize: defaultQAndSize}, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/ADD--vector---Add--vector--?lang=en - VADD: {u: 0, opcode: 0b10000, qAndSize: defaultQAndSize}, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SUB--vector---Subtract--vector--?lang=en - VSUB: {u: 1, opcode: 0b10000, qAndSize: defaultQAndSize}, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SSHL--Signed-Shift-Left--register--?lang=en - SSHL: {u: 0, opcode: 0b01000, qAndSize: defaultQAndSize}, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SSHL--Signed-Shift-Left--register--?lang=en - USHL: {u: 0b1, opcode: 0b01000, qAndSize: defaultQAndSize}, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/CMGT--register---Compare-signed-Greater-than--vector--?lang=en - CMGT: {u: 0b0, opcode: 0b00110, qAndSize: defaultQAndSize}, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/CMHI--register---Compare-unsigned-Higher--vector--?lang=en - CMHI: {u: 0b1, opcode: 0b00110, qAndSize: defaultQAndSize}, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/CMGE--register---Compare-signed-Greater-than-or-Equal--vector--?lang=en - CMGE: {u: 0b0, opcode: 0b00111, qAndSize: defaultQAndSize}, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/CMHS--register---Compare-unsigned-Higher-or-Same--vector--?lang=en - CMHS: {u: 0b1, opcode: 0b00111, qAndSize: defaultQAndSize}, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FCMEQ--register---Floating-point-Compare-Equal--vector--?lang=en - FCMEQ: { - u: 0b0, opcode: 0b11100, - qAndSize: map[VectorArrangement]qAndSize{ - VectorArrangement4S: {size: 0b00, q: 0b1}, - VectorArrangement2S: {size: 0b00, q: 0b0}, - VectorArrangement2D: {size: 0b01, q: 0b1}, - }, - }, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FCMGT--register---Floating-point-Compare-Greater-than--vector--?lang=en - FCMGT: { - u: 0b1, opcode: 0b11100, - qAndSize: map[VectorArrangement]qAndSize{ - VectorArrangement4S: {size: 0b10, q: 0b1}, - VectorArrangement2S: {size: 0b10, q: 0b0}, - VectorArrangement2D: {size: 0b11, q: 0b1}, - }, - }, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FCMGE--register---Floating-point-Compare-Greater-than-or-Equal--vector--?lang=en - FCMGE: { - u: 0b1, opcode: 0b11100, - qAndSize: map[VectorArrangement]qAndSize{ - VectorArrangement4S: {size: 0b00, q: 0b1}, - VectorArrangement2S: {size: 0b00, q: 0b0}, - VectorArrangement2D: {size: 0b01, q: 0b1}, - }, - }, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FMIN--vector---Floating-point-minimum--vector--?lang=en - VFMIN: { - u: 0b0, opcode: 0b11110, - qAndSize: map[VectorArrangement]qAndSize{ - VectorArrangement4S: {size: 0b10, q: 0b1}, - VectorArrangement2S: {size: 0b10, q: 0b0}, - VectorArrangement2D: {size: 0b11, q: 0b1}, - }, - }, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FMAX--vector---Floating-point-Maximum--vector--?lang=en - VFMAX: { - u: 0b0, opcode: 0b11110, - qAndSize: map[VectorArrangement]qAndSize{ - VectorArrangement4S: {size: 0b00, q: 0b1}, - VectorArrangement2S: {size: 0b00, q: 0b0}, - VectorArrangement2D: {size: 0b01, q: 0b1}, - }, - }, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FMUL--vector---Floating-point-Multiply--vector--?lang=en - VFMUL: { - u: 0b1, opcode: 0b11011, - qAndSize: map[VectorArrangement]qAndSize{ - VectorArrangement4S: {size: 0b00, q: 0b1}, - VectorArrangement2S: {size: 0b00, q: 0b0}, - VectorArrangement2D: {size: 0b01, q: 0b1}, - }, - }, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FDIV--vector---Floating-point-Divide--vector--?lang=en - VFDIV: { - u: 0b1, opcode: 0b11111, - qAndSize: map[VectorArrangement]qAndSize{ - VectorArrangement4S: {size: 0b00, q: 0b1}, - VectorArrangement2S: {size: 0b00, q: 0b0}, - VectorArrangement2D: {size: 0b01, q: 0b1}, - }, - }, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/MUL--vector---Multiply--vector--?lang=en - VMUL: {u: 0b0, opcode: 0b10011, qAndSize: defaultQAndSize}, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SQADD--Signed-saturating-Add-?lang=en - VSQADD: {u: 0b0, opcode: 0b00001, qAndSize: defaultQAndSize}, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UQADD--Unsigned-saturating-Add-?lang=en - VUQADD: {u: 0b1, opcode: 0b00001, qAndSize: defaultQAndSize}, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SMIN--Signed-Minimum--vector--?lang=en - SMIN: {u: 0b0, opcode: 0b01101, qAndSize: defaultQAndSize}, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SMAX--Signed-Maximum--vector--?lang=en - SMAX: {u: 0b0, opcode: 0b01100, qAndSize: defaultQAndSize}, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UMIN--Unsigned-Minimum--vector--?lang=en - UMIN: {u: 0b1, opcode: 0b01101, qAndSize: defaultQAndSize}, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UMAX--Unsigned-Maximum--vector--?lang=en - UMAX: {u: 0b1, opcode: 0b01100, qAndSize: defaultQAndSize}, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/URHADD--Unsigned-Rounding-Halving-Add-?lang=en - URHADD: {u: 0b1, opcode: 0b00010, qAndSize: defaultQAndSize}, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SQSUB--Signed-saturating-Subtract-?lang=en - VSQSUB: {u: 0b0, opcode: 0b00101, qAndSize: defaultQAndSize}, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UQSUB--Unsigned-saturating-Subtract-?lang=en - VUQSUB: {u: 0b1, opcode: 0b00101, qAndSize: defaultQAndSize}, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/BIT--Bitwise-Insert-if-True-?lang=en - VBIT: {u: 0b1, opcode: 0b00011, qAndSize: map[VectorArrangement]qAndSize{ - VectorArrangement8B: {q: 0b0, size: 0b10}, - VectorArrangement16B: {q: 0b1, size: 0b10}, - }}, - SQRDMULH: {u: 0b1, opcode: 0b10110, qAndSize: map[VectorArrangement]qAndSize{ - VectorArrangement4H: {q: 0b0, size: 0b01}, - VectorArrangement8H: {q: 0b1, size: 0b01}, - VectorArrangement2S: {q: 0b0, size: 0b10}, - VectorArrangement4S: {q: 0b1, size: 0b10}, - }}, -} - -// aAndSize is a pair of "Q" and "size" that appear in https://developer.arm.com/documentation/ddi0596/2021-12/Index-by-Encoding/Data-Processing----Scalar-Floating-Point-and-Advanced-SIMD?lang=en -type qAndSize struct{ q, size byte } - -// defaultQAndSize maps a vector arrangement to the default qAndSize which is encoded by many instructions. -var defaultQAndSize = map[VectorArrangement]qAndSize{ - VectorArrangement8B: {size: 0b00, q: 0b0}, - VectorArrangement16B: {size: 0b00, q: 0b1}, - VectorArrangement4H: {size: 0b01, q: 0b0}, - VectorArrangement8H: {size: 0b01, q: 0b1}, - VectorArrangement2S: {size: 0b10, q: 0b0}, - VectorArrangement4S: {size: 0b10, q: 0b1}, - VectorArrangement1D: {size: 0b11, q: 0b0}, - VectorArrangement2D: {size: 0b11, q: 0b1}, -} - -// advancedSIMDAcrossLanes holds information to encode instructions as "Advanced SIMD across lanes" in -// https://developer.arm.com/documentation/ddi0596/2021-12/Index-by-Encoding/Data-Processing----Scalar-Floating-Point-and-Advanced-SIMD?lang=en -var advancedSIMDAcrossLanes = map[asm.Instruction]struct { - qAndSize map[VectorArrangement]qAndSize - u, opcode byte -}{ - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/ADDV--Add-across-Vector-?lang=en - ADDV: { - u: 0b0, opcode: 0b11011, - qAndSize: map[VectorArrangement]qAndSize{ - VectorArrangement16B: {size: 0b00, q: 0b1}, - VectorArrangement8B: {size: 0b00, q: 0b0}, - VectorArrangement8H: {size: 0b01, q: 0b1}, - VectorArrangement4H: {size: 0b01, q: 0b0}, - VectorArrangement4S: {size: 0b10, q: 0b1}, - }, - }, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UMINV--Unsigned-Minimum-across-Vector-?lang=en - UMINV: { - u: 0b1, opcode: 0b11010, - qAndSize: map[VectorArrangement]qAndSize{ - VectorArrangement16B: {size: 0b00, q: 0b1}, - VectorArrangement8B: {size: 0b00, q: 0b0}, - VectorArrangement8H: {size: 0b01, q: 0b1}, - VectorArrangement4H: {size: 0b01, q: 0b0}, - VectorArrangement4S: {size: 0b10, q: 0b1}, - }, - }, - UADDLV: {u: 0b1, opcode: 0b00011, qAndSize: map[VectorArrangement]qAndSize{ - VectorArrangement16B: {size: 0b00, q: 0b1}, - VectorArrangement8B: {size: 0b00, q: 0b0}, - VectorArrangement8H: {size: 0b01, q: 0b1}, - VectorArrangement4H: {size: 0b01, q: 0b0}, - VectorArrangement4S: {size: 0b10, q: 0b1}, - }}, -} - -// advancedSIMDScalarPairwise holds information to encode instructions as "Advanced SIMD scalar pairwise" in -// https://developer.arm.com/documentation/ddi0596/2021-12/Index-by-Encoding/Data-Processing----Scalar-Floating-Point-and-Advanced-SIMD?lang=en -var advancedSIMDScalarPairwise = map[asm.Instruction]struct { - size map[VectorArrangement]byte - u, opcode byte -}{ - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/ADDP--scalar---Add-Pair-of-elements--scalar--?lang=en - ADDP: {u: 0b0, opcode: 0b11011, size: map[VectorArrangement]byte{VectorArrangement2D: 0b11}}, -} - -// advancedSIMDCopy holds information to encode instructions as "Advanced SIMD copy" in -// https://developer.arm.com/documentation/ddi0596/2021-12/Index-by-Encoding/Data-Processing----Scalar-Floating-Point-and-Advanced-SIMD?lang=en -var advancedSIMDCopy = map[asm.Instruction]struct { - // TODO: extract common implementation of resolver. - resolver func(srcIndex, dstIndex VectorIndex, arr VectorArrangement) (imm5, imm4, q byte, err error) - op byte -}{ - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/DUP--element---Duplicate-vector-element-to-vector-or-scalar-?lang=en - DUPELEM: {op: 0, resolver: func(srcIndex, dstIndex VectorIndex, arr VectorArrangement) (imm5, imm4, q byte, err error) { - imm4 = 0b0000 - q = 0b1 - - switch arr { - case VectorArrangementB: - imm5 |= 0b1 - imm5 |= byte(srcIndex) << 1 - case VectorArrangementH: - imm5 |= 0b10 - imm5 |= byte(srcIndex) << 2 - case VectorArrangementS: - imm5 |= 0b100 - imm5 |= byte(srcIndex) << 3 - case VectorArrangementD: - imm5 |= 0b1000 - imm5 |= byte(srcIndex) << 4 - default: - err = fmt.Errorf("unsupported arrangement for DUPELEM: %d", arr) - } - - return - }}, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/DUP--general---Duplicate-general-purpose-register-to-vector-?lang=en - DUPGEN: {op: 0b0, resolver: func(srcIndex, dstIndex VectorIndex, arr VectorArrangement) (imm5, imm4, q byte, err error) { - imm4 = 0b0001 - switch arr { - case VectorArrangement8B: - imm5 = 0b1 - case VectorArrangement16B: - imm5 = 0b1 - q = 0b1 - case VectorArrangement4H: - imm5 = 0b10 - case VectorArrangement8H: - imm5 = 0b10 - q = 0b1 - case VectorArrangement2S: - imm5 = 0b100 - case VectorArrangement4S: - imm5 = 0b100 - q = 0b1 - case VectorArrangement2D: - imm5 = 0b1000 - q = 0b1 - default: - err = fmt.Errorf("unsupported arrangement for DUPGEN: %s", arr) - } - return - }}, - // https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/INS--general---Insert-vector-element-from-general-purpose-register-?lang=en - INSGEN: {op: 0b0, resolver: func(srcIndex, dstIndex VectorIndex, arr VectorArrangement) (imm5, imm4, q byte, err error) { - imm4, q = 0b0011, 0b1 - switch arr { - case VectorArrangementB: - imm5 |= 0b1 - imm5 |= byte(dstIndex) << 1 - case VectorArrangementH: - imm5 |= 0b10 - imm5 |= byte(dstIndex) << 2 - case VectorArrangementS: - imm5 |= 0b100 - imm5 |= byte(dstIndex) << 3 - case VectorArrangementD: - imm5 |= 0b1000 - imm5 |= byte(dstIndex) << 4 - default: - err = fmt.Errorf("unsupported arrangement for INSGEN: %s", arr) - } - return - }}, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UMOV--Unsigned-Move-vector-element-to-general-purpose-register-?lang=en - UMOV: {op: 0b0, resolver: func(srcIndex, dstIndex VectorIndex, arr VectorArrangement) (imm5, imm4, q byte, err error) { - imm4 = 0b0111 - switch arr { - case VectorArrangementB: - imm5 |= 0b1 - imm5 |= byte(srcIndex) << 1 - case VectorArrangementH: - imm5 |= 0b10 - imm5 |= byte(srcIndex) << 2 - case VectorArrangementS: - imm5 |= 0b100 - imm5 |= byte(srcIndex) << 3 - case VectorArrangementD: - imm5 |= 0b1000 - imm5 |= byte(srcIndex) << 4 - q = 0b1 - default: - err = fmt.Errorf("unsupported arrangement for UMOV: %s", arr) - } - return - }}, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SMOV--Signed-Move-vector-element-to-general-purpose-register-?lang=en - SMOV32: {op: 0b0, resolver: func(srcIndex, dstIndex VectorIndex, arr VectorArrangement) (imm5, imm4, q byte, err error) { - imm4 = 0b0101 - switch arr { - case VectorArrangementB: - imm5 |= 0b1 - imm5 |= byte(srcIndex) << 1 - case VectorArrangementH: - imm5 |= 0b10 - imm5 |= byte(srcIndex) << 2 - default: - err = fmt.Errorf("unsupported arrangement for SMOV32: %s", arr) - } - return - }}, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/INS--element---Insert-vector-element-from-another-vector-element-?lang=en - INSELEM: {op: 0b1, resolver: func(srcIndex, dstIndex VectorIndex, arr VectorArrangement) (imm5, imm4, q byte, err error) { - q = 0b1 - switch arr { - case VectorArrangementB: - imm5 |= 0b1 - imm5 |= byte(dstIndex) << 1 - imm4 = byte(srcIndex) - case VectorArrangementH: - imm5 |= 0b10 - imm5 |= byte(dstIndex) << 2 - imm4 = byte(srcIndex) << 1 - case VectorArrangementS: - imm5 |= 0b100 - imm5 |= byte(dstIndex) << 3 - imm4 = byte(srcIndex) << 2 - case VectorArrangementD: - imm5 |= 0b1000 - imm5 |= byte(dstIndex) << 4 - imm4 = byte(srcIndex) << 3 - default: - err = fmt.Errorf("unsupported arrangement for INSELEM: %d", arr) - } - return - }}, -} - -// advancedSIMDTableLookup holds information to encode instructions as "Advanced SIMD table lookup" in -// https://developer.arm.com/documentation/ddi0596/2021-12/Index-by-Encoding/Data-Processing----Scalar-Floating-Point-and-Advanced-SIMD?lang=en -var advancedSIMDTableLookup = map[asm.Instruction]struct { - q map[VectorArrangement]byte - op, op2, Len byte -}{ - TBL1: {op: 0, op2: 0, Len: 0b00, q: map[VectorArrangement]byte{VectorArrangement16B: 0b1, VectorArrangement8B: 0b0}}, - TBL2: {op: 0, op2: 0, Len: 0b01, q: map[VectorArrangement]byte{VectorArrangement16B: 0b1, VectorArrangement8B: 0b0}}, -} - -// advancedSIMDShiftByImmediate holds information to encode instructions as "Advanced SIMD shift by immediate" in -// https://developer.arm.com/documentation/ddi0596/2021-12/Index-by-Encoding/Data-Processing----Scalar-Floating-Point-and-Advanced-SIMD?lang=en -var advancedSIMDShiftByImmediate = map[asm.Instruction]struct { - q map[VectorArrangement]byte - immResolver func(shiftAmount int64, arr VectorArrangement) (immh, immb byte, err error) - U, opcode byte -}{ - // https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/SSHLL--SSHLL2--Signed-Shift-Left-Long--immediate-- - SSHLL: { - U: 0b0, opcode: 0b10100, - q: map[VectorArrangement]byte{VectorArrangement8B: 0b0, VectorArrangement4H: 0b0, VectorArrangement2S: 0b0}, - immResolver: immResolverForSIMDSiftLeftByImmediate, - }, - // https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/SSHLL--SSHLL2--Signed-Shift-Left-Long--immediate-- - SSHLL2: { - U: 0b0, opcode: 0b10100, - q: map[VectorArrangement]byte{VectorArrangement16B: 0b1, VectorArrangement8H: 0b1, VectorArrangement4S: 0b1}, - immResolver: immResolverForSIMDSiftLeftByImmediate, - }, - // https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/USHLL--USHLL2--Unsigned-Shift-Left-Long--immediate-- - USHLL: { - U: 0b1, opcode: 0b10100, - q: map[VectorArrangement]byte{VectorArrangement8B: 0b0, VectorArrangement4H: 0b0, VectorArrangement2S: 0b0}, - immResolver: immResolverForSIMDSiftLeftByImmediate, - }, - // https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/USHLL--USHLL2--Unsigned-Shift-Left-Long--immediate-- - USHLL2: { - U: 0b1, opcode: 0b10100, - q: map[VectorArrangement]byte{VectorArrangement16B: 0b1, VectorArrangement8H: 0b1, VectorArrangement4S: 0b1}, - immResolver: immResolverForSIMDSiftLeftByImmediate, - }, - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SSHR--Signed-Shift-Right--immediate--?lang=en - SSHR: { - U: 0b0, opcode: 0b00000, - q: map[VectorArrangement]byte{ - VectorArrangement16B: 0b1, VectorArrangement8H: 0b1, VectorArrangement4S: 0b1, VectorArrangement2D: 0b1, - VectorArrangement8B: 0b0, VectorArrangement4H: 0b0, VectorArrangement2S: 0b0, - }, - immResolver: func(shiftAmount int64, arr VectorArrangement) (immh, immb byte, err error) { - switch arr { - case VectorArrangement16B, VectorArrangement8B: - immh = 0b0001 - immb = 8 - byte(shiftAmount&0b111) - case VectorArrangement8H, VectorArrangement4H: - v := 16 - byte(shiftAmount&0b1111) - immb = v & 0b111 - immh = 0b0010 | (v >> 3) - case VectorArrangement4S, VectorArrangement2S: - v := 32 - byte(shiftAmount&0b11111) - immb = v & 0b111 - immh = 0b0100 | (v >> 3) - case VectorArrangement2D: - v := 64 - byte(shiftAmount&0b111111) - immb = v & 0b111 - immh = 0b1000 | (v >> 3) - default: - err = fmt.Errorf("unsupported arrangement %s", arr) - } - return - }, - }, -} - -// advancedSIMDPermute holds information to encode instructions as "Advanced SIMD permute" in -// https://developer.arm.com/documentation/ddi0596/2021-12/Index-by-Encoding/Data-Processing----Scalar-Floating-Point-and-Advanced-SIMD?lang=en -var advancedSIMDPermute = map[asm.Instruction]struct { - opcode byte -}{ - ZIP1: {opcode: 0b011}, -} - -func immResolverForSIMDSiftLeftByImmediate(shiftAmount int64, arr VectorArrangement) (immh, immb byte, err error) { - switch arr { - case VectorArrangement16B, VectorArrangement8B: - immb = byte(shiftAmount) - immh = 0b0001 - case VectorArrangement8H, VectorArrangement4H: - immb = byte(shiftAmount) & 0b111 - immh = 0b0010 | byte(shiftAmount>>3) - case VectorArrangement4S, VectorArrangement2S: - immb = byte(shiftAmount) & 0b111 - immh = 0b0100 | byte(shiftAmount>>3) - default: - err = fmt.Errorf("unsupported arrangement %s", arr) - } - return -} - -// encodeAdvancedSIMDCopy encodes instruction as "Advanced SIMD copy" in -// https://developer.arm.com/documentation/ddi0596/2021-12/Index-by-Encoding/Data-Processing----Scalar-Floating-Point-and-Advanced-SIMD?lang=en -func (a *AssemblerImpl) encodeAdvancedSIMDCopy(buf asm.Buffer, srcRegBits, dstRegBits, op, imm5, imm4, q byte) { - buf.Append4Bytes( - (srcRegBits<<5)|dstRegBits, - imm4<<3|0b1<<2|srcRegBits>>3, - imm5, - q<<6|op<<5|0b1110, - ) -} - -// encodeAdvancedSIMDThreeSame encodes instruction as "Advanced SIMD three same" in -// https://developer.arm.com/documentation/ddi0596/2021-12/Index-by-Encoding/Data-Processing----Scalar-Floating-Point-and-Advanced-SIMD?lang=en -func (a *AssemblerImpl) encodeAdvancedSIMDThreeSame(buf asm.Buffer, src1, src2, dst, opcode, size, q, u byte) { - buf.Append4Bytes( - (src2<<5)|dst, - opcode<<3|1<<2|src2>>3, - size<<6|0b1<<5|src1, - q<<6|u<<5|0b1110, - ) -} - -// encodeAdvancedSIMDThreeDifferent encodes instruction as "Advanced SIMD three different" in -// https://developer.arm.com/documentation/ddi0596/2021-12/Index-by-Encoding/Data-Processing----Scalar-Floating-Point-and-Advanced-SIMD?lang=en -func (a *AssemblerImpl) encodeAdvancedSIMDThreeDifferent(buf asm.Buffer, src1, src2, dst, opcode, size, q, u byte) { - buf.Append4Bytes( - (src2<<5)|dst, - opcode<<4|src2>>3, - size<<6|0b1<<5|src1, - q<<6|u<<5|0b1110, - ) -} - -// encodeAdvancedSIMDPermute encodes instruction as "Advanced SIMD permute" in -// https://developer.arm.com/documentation/ddi0596/2021-12/Index-by-Encoding/Data-Processing----Scalar-Floating-Point-and-Advanced-SIMD?lang=en -func (a *AssemblerImpl) encodeAdvancedSIMDPermute(buf asm.Buffer, src1, src2, dst, opcode, size, q byte) { - buf.Append4Bytes( - (src2<<5)|dst, - opcode<<4|0b1<<3|src2>>3, - size<<6|src1, - q<<6|0b1110, - ) -} - -func (a *AssemblerImpl) encodeVectorRegisterToVectorRegister(buf asm.Buffer, n *nodeImpl) (err error) { - var srcVectorRegBits byte - if n.srcReg != RegRZR { - srcVectorRegBits, err = vectorRegisterBits(n.srcReg) - } else if n.instruction == CMEQZERO { - // CMEQZERO has RegRZR as the src, and we apply the instruction to the same register as the destination. - srcVectorRegBits, err = vectorRegisterBits(n.dstReg) - } - - if err != nil { - return err - } - - dstVectorRegBits, err := vectorRegisterBits(n.dstReg) - if err != nil { - return err - } - - if simdCopy, ok := advancedSIMDCopy[n.instruction]; ok { - imm5, imm4, q, err := simdCopy.resolver(n.srcVectorIndex, n.dstVectorIndex, n.vectorArrangement) - if err != nil { - return err - } - a.encodeAdvancedSIMDCopy(buf, srcVectorRegBits, dstVectorRegBits, simdCopy.op, imm5, imm4, q) - return nil - } - - if scalarPairwise, ok := advancedSIMDScalarPairwise[n.instruction]; ok { - // See "Advanced SIMD scalar pairwise" in - // https://developer.arm.com/documentation/ddi0596/2021-12/Index-by-Encoding/Data-Processing----Scalar-Floating-Point-and-Advanced-SIMD?lang=en - size, ok := scalarPairwise.size[n.vectorArrangement] - if !ok { - return fmt.Errorf("unsupported vector arrangement %s for %s", n.vectorArrangement, InstructionName(n.instruction)) - } - buf.Append4Bytes( - (srcVectorRegBits<<5)|dstVectorRegBits, - scalarPairwise.opcode<<4|1<<3|srcVectorRegBits>>3, - size<<6|0b11<<4|scalarPairwise.opcode>>4, - 0b1<<6|scalarPairwise.u<<5|0b11110, - ) - return - } - - if twoRegMisc, ok := advancedSIMDTwoRegisterMisc[n.instruction]; ok { - // See "Advanced SIMD two-register miscellaneous" in - // https://developer.arm.com/documentation/ddi0596/2021-12/Index-by-Encoding/Data-Processing----Scalar-Floating-Point-and-Advanced-SIMD?lang=en - qs, ok := twoRegMisc.qAndSize[n.vectorArrangement] - if !ok { - return fmt.Errorf("unsupported vector arrangement %s for %s", n.vectorArrangement, InstructionName(n.instruction)) - } - buf.Append4Bytes( - (srcVectorRegBits<<5)|dstVectorRegBits, - twoRegMisc.opcode<<4|0b1<<3|srcVectorRegBits>>3, - qs.size<<6|0b1<<5|twoRegMisc.opcode>>4, - qs.q<<6|twoRegMisc.u<<5|0b01110, - ) - return nil - } - - if threeSame, ok := advancedSIMDThreeSame[n.instruction]; ok { - qs, ok := threeSame.qAndSize[n.vectorArrangement] - if !ok { - return fmt.Errorf("unsupported vector arrangement %s for %s", n.vectorArrangement, InstructionName(n.instruction)) - } - a.encodeAdvancedSIMDThreeSame(buf, srcVectorRegBits, dstVectorRegBits, dstVectorRegBits, threeSame.opcode, qs.size, qs.q, threeSame.u) - return nil - } - - if threeDifferent, ok := advancedSIMDThreeDifferent[n.instruction]; ok { - qs, ok := threeDifferent.qAndSize[n.vectorArrangement] - if !ok { - return fmt.Errorf("unsupported vector arrangement %s for %s", n.vectorArrangement, InstructionName(n.instruction)) - } - a.encodeAdvancedSIMDThreeDifferent(buf, srcVectorRegBits, dstVectorRegBits, dstVectorRegBits, threeDifferent.opcode, qs.size, qs.q, threeDifferent.u) - return nil - } - - if acrossLanes, ok := advancedSIMDAcrossLanes[n.instruction]; ok { - // See "Advanced SIMD across lanes" in - // https://developer.arm.com/documentation/ddi0596/2021-12/Index-by-Encoding/Data-Processing----Scalar-Floating-Point-and-Advanced-SIMD?lang=en - qs, ok := acrossLanes.qAndSize[n.vectorArrangement] - if !ok { - return fmt.Errorf("unsupported vector arrangement %s for %s", n.vectorArrangement, InstructionName(n.instruction)) - } - buf.Append4Bytes( - (srcVectorRegBits<<5)|dstVectorRegBits, - acrossLanes.opcode<<4|0b1<<3|srcVectorRegBits>>3, - qs.size<<6|0b11000<<1|acrossLanes.opcode>>4, - qs.q<<6|acrossLanes.u<<5|0b01110, - ) - return nil - } - - if lookup, ok := advancedSIMDTableLookup[n.instruction]; ok { - q, ok := lookup.q[n.vectorArrangement] - if !ok { - return fmt.Errorf("unsupported vector arrangement %s for %s", n.vectorArrangement, InstructionName(n.instruction)) - } - buf.Append4Bytes( - (srcVectorRegBits<<5)|dstVectorRegBits, - lookup.Len<<5|lookup.op<<4|srcVectorRegBits>>3, - lookup.op2<<6|dstVectorRegBits, - q<<6|0b1110, - ) - return - } - - if shiftByImmediate, ok := advancedSIMDShiftByImmediate[n.instruction]; ok { - immh, immb, err := shiftByImmediate.immResolver(n.srcConst, n.vectorArrangement) - if err != nil { - return err - } - - q, ok := shiftByImmediate.q[n.vectorArrangement] - if !ok { - return fmt.Errorf("unsupported vector arrangement %s for %s", n.vectorArrangement, InstructionName(n.instruction)) - } - - buf.Append4Bytes( - (srcVectorRegBits<<5)|dstVectorRegBits, - shiftByImmediate.opcode<<3|0b1<<2|srcVectorRegBits>>3, - immh<<3|immb, - q<<6|shiftByImmediate.U<<5|0b1111, - ) - return nil - } - - if permute, ok := advancedSIMDPermute[n.instruction]; ok { - size, q := arrangementSizeQ(n.vectorArrangement) - a.encodeAdvancedSIMDPermute(buf, srcVectorRegBits, dstVectorRegBits, dstVectorRegBits, permute.opcode, size, q) - return - } - return errorEncodingUnsupported(n) -} - -func (a *AssemblerImpl) encodeTwoVectorRegistersToVectorRegister(buf asm.Buffer, n *nodeImpl) (err error) { - var srcRegBits, srcRegBits2, dstRegBits byte - srcRegBits, err = vectorRegisterBits(n.srcReg) - if err != nil { - return err - } - - srcRegBits2, err = vectorRegisterBits(n.srcReg2) - if err != nil { - return err - } - - dstRegBits, err = vectorRegisterBits(n.dstReg) - if err != nil { - return err - } - - if threeSame, ok := advancedSIMDThreeSame[n.instruction]; ok { - qs, ok := threeSame.qAndSize[n.vectorArrangement] - if !ok { - return fmt.Errorf("unsupported vector arrangement %s for %s", n.vectorArrangement, InstructionName(n.instruction)) - } - a.encodeAdvancedSIMDThreeSame(buf, srcRegBits, srcRegBits2, dstRegBits, threeSame.opcode, qs.size, qs.q, threeSame.u) - return nil - } - - if threeDifferent, ok := advancedSIMDThreeDifferent[n.instruction]; ok { - qs, ok := threeDifferent.qAndSize[n.vectorArrangement] - if !ok { - return fmt.Errorf("unsupported vector arrangement %s for %s", n.vectorArrangement, InstructionName(n.instruction)) - } - a.encodeAdvancedSIMDThreeDifferent(buf, srcRegBits, srcRegBits2, dstRegBits, threeDifferent.opcode, qs.size, qs.q, threeDifferent.u) - return nil - } - - if permute, ok := advancedSIMDPermute[n.instruction]; ok { - size, q := arrangementSizeQ(n.vectorArrangement) - a.encodeAdvancedSIMDPermute(buf, srcRegBits, srcRegBits2, dstRegBits, permute.opcode, size, q) - return - } - - if n.instruction == EXT { - // EXT is the only instruction in "Advanced SIMD extract", so inline the encoding here. - // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/EXT--Extract-vector-from-pair-of-vectors-?lang=en - var q, imm4 byte - switch n.vectorArrangement { - case VectorArrangement16B: - imm4 = 0b1111 & byte(n.srcConst) - q = 0b1 - case VectorArrangement8B: - imm4 = 0b111 & byte(n.srcConst) - default: - return fmt.Errorf("invalid arrangement %s for EXT", n.vectorArrangement) - } - buf.Append4Bytes( - (srcRegBits2<<5)|dstRegBits, - imm4<<3|srcRegBits2>>3, - srcRegBits, - q<<6|0b101110, - ) - return - } - return -} - -func (a *AssemblerImpl) encodeVectorRegisterToRegister(buf asm.Buffer, n *nodeImpl) (err error) { - if err = checkArrangementIndexPair(n.vectorArrangement, n.srcVectorIndex); err != nil { - return - } - - srcVecRegBits, err := vectorRegisterBits(n.srcReg) - if err != nil { - return err - } - - dstRegBits, err := intRegisterBits(n.dstReg) - if err != nil { - return err - } - - if simdCopy, ok := advancedSIMDCopy[n.instruction]; ok { - imm5, imm4, q, err := simdCopy.resolver(n.srcVectorIndex, n.dstVectorIndex, n.vectorArrangement) - if err != nil { - return err - } - a.encodeAdvancedSIMDCopy(buf, srcVecRegBits, dstRegBits, simdCopy.op, imm5, imm4, q) - return nil - } - return errorEncodingUnsupported(n) -} - -func (a *AssemblerImpl) encodeRegisterToVectorRegister(buf asm.Buffer, n *nodeImpl) (err error) { - srcRegBits, err := intRegisterBits(n.srcReg) - if err != nil { - return err - } - - dstVectorRegBits, err := vectorRegisterBits(n.dstReg) - if err != nil { - return err - } - - if simdCopy, ok := advancedSIMDCopy[n.instruction]; ok { - imm5, imm4, q, err := simdCopy.resolver(n.srcVectorIndex, n.dstVectorIndex, n.vectorArrangement) - if err != nil { - return err - } - a.encodeAdvancedSIMDCopy(buf, srcRegBits, dstVectorRegBits, simdCopy.op, imm5, imm4, q) - return nil - } - return errorEncodingUnsupported(n) -} - -var zeroRegisterBits byte = 0b11111 - -func isIntRegister(r asm.Register) bool { - return RegR0 <= r && r <= RegSP -} - -func isVectorRegister(r asm.Register) bool { - return RegV0 <= r && r <= RegV31 -} - -func isConditionalRegister(r asm.Register) bool { - return RegCondEQ <= r && r <= RegCondNV -} - -func intRegisterBits(r asm.Register) (ret byte, err error) { - if !isIntRegister(r) { - err = fmt.Errorf("%s is not integer", RegisterName(r)) - } else if r == RegSP { - // SP has the same bit representations as RegRZR. - r = RegRZR - } - ret = byte(r - RegR0) - return -} - -func vectorRegisterBits(r asm.Register) (ret byte, err error) { - if !isVectorRegister(r) { - err = fmt.Errorf("%s is not vector", RegisterName(r)) - } else { - ret = byte(r - RegV0) - } - return -} - -func registerBits(r asm.Register) (ret byte) { - if isIntRegister(r) { - if r == RegSP { - // SP has the same bit representations as RegRZR. - r = RegRZR - } - ret = byte(r - RegR0) - } else { - ret = byte(r - RegV0) - } - return -} diff --git a/internal/asm/arm64/impl_1_test.go b/internal/asm/arm64/impl_1_test.go deleted file mode 100644 index e3a0960e1c..0000000000 --- a/internal/asm/arm64/impl_1_test.go +++ /dev/null @@ -1,4125 +0,0 @@ -package arm64 - -import ( - "encoding/hex" - "testing" - - "github.com/tetratelabs/wazero/internal/asm" - "github.com/tetratelabs/wazero/internal/testing/require" -) - -func TestNodePool_allocNode(t *testing.T) { - np := nodePool{index: nodePageSize} - - for i := 0; i < nodePageSize; i++ { - n := np.allocNode() - require.Equal(t, &np.pages[0][i], n) - require.Equal(t, i+1, np.index) - require.Equal(t, 1, len(np.pages)) - } - require.Equal(t, nodePageSize, np.index) - - // Reached the next page. - secondPageBegin := np.allocNode() - require.Equal(t, 1, np.index) - require.Equal(t, 2, len(np.pages)) - require.Equal(t, &np.pages[1][0], secondPageBegin) -} - -func TestAssemblerImpl_Reset(t *testing.T) { - // Existing values. - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - buf := code.NextCodeSection() - buf.AppendBytes([]byte{0, 0, 0, 0, 0}) - - staticConsts := asm.NewStaticConstPool() - staticConsts.AddConst(asm.NewStaticConst(nil), 1234) - adrInstructionNodes := make([]*nodeImpl, 5) - relativeJumpNodes := make([]*nodeImpl, 10) - ba := asm.BaseAssemblerImpl{ - SetBranchTargetOnNextNodes: make([]asm.Node, 5), - JumpTableEntries: make([]asm.JumpTableEntry, 10), - } - - // Create assembler and reset. - a := &AssemblerImpl{ - nodePool: nodePool{ - pages: []*nodePage{new(nodePage), new(nodePage)}, - index: 12, - }, - pool: staticConsts, - temporaryRegister: RegV2, - relativeJumpNodes: relativeJumpNodes, - adrInstructionNodes: adrInstructionNodes, - BaseAssemblerImpl: ba, - } - a.Reset() - buf.Reset() - - // Check each field. - require.Equal(t, 65536, buf.Cap()) - require.Equal(t, 0, buf.Len()) - - require.Zero(t, len(a.nodePool.pages)) - require.Equal(t, nodePageSize, a.nodePool.index) - - require.NotEqual(t, staticConsts, a.pool) - - require.Equal(t, RegV2, a.temporaryRegister) - - require.Equal(t, 0, len(a.adrInstructionNodes)) - require.Equal(t, cap(adrInstructionNodes), cap(a.adrInstructionNodes)) - - require.Equal(t, 0, len(a.relativeJumpNodes)) - require.Equal(t, cap(relativeJumpNodes), cap(a.relativeJumpNodes)) - - require.Equal(t, 0, len(a.SetBranchTargetOnNextNodes)) - require.Equal(t, cap(ba.SetBranchTargetOnNextNodes), cap(a.SetBranchTargetOnNextNodes)) - - require.Equal(t, 0, len(a.JumpTableEntries)) - require.Equal(t, cap(ba.JumpTableEntries), cap(a.JumpTableEntries)) -} - -func TestNodeImpl_AssignJumpTarget(t *testing.T) { - n := &nodeImpl{} - target := &nodeImpl{} - n.AssignJumpTarget(target) - require.Equal(t, n.jumpTarget, target) -} - -func TestNodeImpl_AssignDestinationConstant(t *testing.T) { - n := &nodeImpl{} - n.AssignDestinationConstant(12345) - require.Equal(t, int64(12345), n.dstConst) -} - -func TestNodeImpl_AssignSourceConstant(t *testing.T) { - n := &nodeImpl{} - n.AssignSourceConstant(12345) - require.Equal(t, int64(12345), n.srcConst) -} - -func TestNodeImpl_String(t *testing.T) { - tests := []struct { - in *nodeImpl - exp string - }{ - { - in: &nodeImpl{instruction: NOP, types: operandTypesNoneToNone}, - exp: "NOP", - }, - { - in: &nodeImpl{instruction: BCONDEQ, types: operandTypesNoneToRegister, dstReg: RegR1}, - exp: "BCONDEQ R1", - }, - { - in: &nodeImpl{instruction: BCONDNE, types: operandTypesNoneToBranch, jumpTarget: &nodeImpl{instruction: NOP}}, - exp: "BCONDNE {NOP}", - }, - { - in: &nodeImpl{instruction: ADD, types: operandTypesRegisterToRegister, srcReg: RegV0, dstReg: RegV10}, - exp: "ADD V0, V10", - }, - { - in: &nodeImpl{ - instruction: ADD, types: operandTypesLeftShiftedRegisterToRegister, - srcReg: RegR0, srcReg2: RegR11, srcConst: 4, dstReg: RegR10, - }, - exp: "ADD (R0, R11 << 4), R10", - }, - { - in: &nodeImpl{instruction: ADD, types: operandTypesTwoRegistersToRegister, srcReg: RegR0, srcReg2: RegR8, dstReg: RegR10}, - exp: "ADD (R0, R8), R10", - }, - { - in: &nodeImpl{ - instruction: MSUB, types: operandTypesThreeRegistersToRegister, - srcReg: RegR0, srcReg2: RegR8, dstReg: RegR10, dstReg2: RegR1, - }, - exp: "MSUB (R0, R8, R10), R1)", - }, - { - in: &nodeImpl{instruction: CMPW, types: operandTypesTwoRegistersToNone, srcReg: RegR0, srcReg2: RegR8}, - exp: "CMPW (R0, R8)", - }, - { - in: &nodeImpl{instruction: CMP, types: operandTypesRegisterAndConstToNone, srcReg: RegR0, srcConst: 0x123}, - exp: "CMP (R0, 0x123)", - }, - { - in: &nodeImpl{instruction: MOVD, types: operandTypesRegisterToMemory, srcReg: RegR0, dstReg: RegR8, dstConst: 0x123}, - exp: "MOVD R0, [R8 + 0x123]", - }, - { - in: &nodeImpl{instruction: MOVD, types: operandTypesRegisterToMemory, srcReg: RegR0, dstReg: RegR8, dstReg2: RegR6}, - exp: "MOVD R0, [R8 + R6]", - }, - { - in: &nodeImpl{instruction: MOVD, types: operandTypesMemoryToRegister, srcReg: RegR0, srcConst: 0x123, dstReg: RegR8}, - exp: "MOVD [R0 + 0x123], R8", - }, - { - in: &nodeImpl{instruction: MOVD, types: operandTypesMemoryToRegister, srcReg: RegR0, srcReg2: RegR6, dstReg: RegR8}, - exp: "MOVD [R0 + R6], R8", - }, - { - in: &nodeImpl{instruction: MOVD, types: operandTypesConstToRegister, srcConst: 0x123, dstReg: RegR8}, - exp: "MOVD 0x123, R8", - }, - { - in: &nodeImpl{ - instruction: VMOV, types: operandTypesMemoryToVectorRegister, - srcReg: RegR1, dstReg: RegV29, vectorArrangement: VectorArrangement2S, - }, - exp: "VMOV [R1], V29.2S", - }, - { - in: &nodeImpl{ - instruction: VMOV, types: operandTypesVectorRegisterToMemory, - dstReg: RegR1, dstReg2: RegR6, - srcReg: RegV29, vectorArrangement: VectorArrangementQ, - }, - exp: "VMOV V29.Q, [R1 + R6]", - }, - { - in: &nodeImpl{ - instruction: VMOV, types: operandTypesVectorRegisterToMemory, - dstReg: RegR1, dstConst: 0x10, - srcReg: RegV29, vectorArrangement: VectorArrangementQ, - }, - exp: "VMOV V29.Q, [R1 + 0x10]", - }, - { - in: &nodeImpl{ - instruction: VMOV, types: operandTypesRegisterToVectorRegister, - srcReg: RegR1, dstReg: RegV29, vectorArrangement: VectorArrangement2D, dstVectorIndex: 1, - }, - exp: "VMOV R1, V29.2D[1]", - }, - { - in: &nodeImpl{ - instruction: VCNT, types: operandTypesVectorRegisterToVectorRegister, - srcReg: RegV3, dstReg: RegV29, vectorArrangement: VectorArrangement2D, srcVectorIndex: 1, - }, - exp: "VCNT V3.2D, V29.2D", - }, - { - in: &nodeImpl{ - instruction: VCNT, types: operandTypesVectorRegisterToVectorRegister, - srcReg: RegV3, dstReg: RegV29, vectorArrangement: VectorArrangement2D, srcVectorIndex: 1, - }, - exp: "VCNT V3.2D, V29.2D", - }, - { - in: &nodeImpl{ - instruction: UMOV, types: operandTypesVectorRegisterToRegister, - srcReg: RegV31, dstReg: RegR8, vectorArrangement: VectorArrangementS, srcVectorIndex: 1, - }, - exp: "UMOV V31.S[1], R8", - }, - { - in: &nodeImpl{ - instruction: UMOV, types: operandTypesTwoVectorRegistersToVectorRegister, - srcReg: RegV31, srcReg2: RegV1, dstReg: RegV8, vectorArrangement: VectorArrangementS, srcVectorIndex: 1, - }, - exp: "UMOV (V31.S, V1.S), V8.S", - }, - { - in: &nodeImpl{ - instruction: VORR, types: operandTypesStaticConstToVectorRegister, - staticConst: &asm.StaticConst{Raw: []byte{1, 2, 3, 4}}, - dstReg: RegV8, vectorArrangement: VectorArrangement16B, srcVectorIndex: 1, - }, - exp: "VORR $0x01020304 V8.16B", - }, - } - - for _, tt := range tests { - tc := tt - t.Run(tc.exp, func(t *testing.T) { - require.Equal(t, tc.exp, tc.in.String()) - }) - } -} - -func TestAssemblerImpl_addNode(t *testing.T) { - a := NewAssembler(RegR10) - - root := &nodeImpl{} - a.addNode(root) - require.Equal(t, a.root, root) - require.Equal(t, a.current, root) - require.Nil(t, root.next) - - next := &nodeImpl{} - a.addNode(next) - require.Equal(t, a.root, root) - require.Equal(t, a.current, next) - require.Equal(t, next, root.next) - require.Nil(t, next.next) -} - -func TestAssemblerImpl_newNode(t *testing.T) { - a := NewAssembler(RegR10) - actual := a.newNode(MOVD, operandTypesMemoryToRegister) - require.Equal(t, MOVD, actual.instruction) - require.Equal(t, operandTypesMemoryToRegister, actual.types) - require.Equal(t, actual, a.root) - require.Equal(t, actual, a.current) -} - -func TestAssemblerImpl_CompileStandAlone(t *testing.T) { - a := NewAssembler(RegR10) - a.CompileStandAlone(RET) - actualNode := a.current - require.Equal(t, RET, actualNode.instruction) - require.Equal(t, operandTypesNoneToNone, actualNode.types) -} - -func TestAssemblerImpl_CompileConstToRegister(t *testing.T) { - a := NewAssembler(RegR10) - a.CompileConstToRegister(MOVD, 1000, RegR10) - actualNode := a.current - require.Equal(t, MOVD, actualNode.instruction) - require.Equal(t, int64(1000), actualNode.srcConst) - require.Equal(t, RegR10, actualNode.dstReg) - require.Equal(t, operandTypesConstToRegister, actualNode.types) -} - -func TestAssemblerImpl_CompileRegisterToRegister(t *testing.T) { - a := NewAssembler(RegR10) - a.CompileRegisterToRegister(MOVD, RegR15, RegR27) - actualNode := a.current - require.Equal(t, MOVD, actualNode.instruction) - require.Equal(t, RegR15, actualNode.srcReg) - require.Equal(t, RegR27, actualNode.dstReg) - require.Equal(t, operandTypesRegisterToRegister, actualNode.types) -} - -func TestAssemblerImpl_CompileMemoryToRegister(t *testing.T) { - a := NewAssembler(RegR10) - a.CompileMemoryToRegister(MOVD, RegR15, 100, RegR27) - actualNode := a.current - require.Equal(t, MOVD, actualNode.instruction) - require.Equal(t, RegR15, actualNode.srcReg) - require.Equal(t, int64(100), actualNode.srcConst) - require.Equal(t, RegR27, actualNode.dstReg) - require.Equal(t, operandTypesMemoryToRegister, actualNode.types) -} - -func TestAssemblerImpl_CompileRegisterToMemory(t *testing.T) { - a := NewAssembler(RegR10) - a.CompileRegisterToMemory(MOVD, RegR15, RegR27, 100) - actualNode := a.current - require.Equal(t, MOVD, actualNode.instruction) - require.Equal(t, RegR15, actualNode.srcReg) - require.Equal(t, RegR27, actualNode.dstReg) - require.Equal(t, int64(100), actualNode.dstConst) - require.Equal(t, operandTypesRegisterToMemory, actualNode.types) -} - -func TestAssemblerImpl_CompileJump(t *testing.T) { - a := NewAssembler(RegR10) - a.CompileJump(B) - actualNode := a.current - require.Equal(t, B, actualNode.instruction) - require.Equal(t, operandTypesNoneToBranch, actualNode.types) -} - -func TestAssemblerImpl_CompileJumpToRegister(t *testing.T) { - a := NewAssembler(RegR10) - a.CompileJumpToRegister(BCONDNE, RegR27) - actualNode := a.current - require.Equal(t, BCONDNE, actualNode.instruction) - require.Equal(t, RegR27, actualNode.dstReg) - require.Equal(t, operandTypesNoneToRegister, actualNode.types) -} - -func TestAssemblerImpl_CompileReadInstructionAddress(t *testing.T) { - a := NewAssembler(RegR10) - a.CompileReadInstructionAddress(RegR10, RET) - actualNode := a.current - require.Equal(t, ADR, actualNode.instruction) - require.Equal(t, RegR10, actualNode.dstReg) - require.Equal(t, operandTypesMemoryToRegister, actualNode.types) - require.Equal(t, RET, actualNode.readInstructionAddressBeforeTargetInstruction) -} - -func Test_CompileMemoryWithRegisterOffsetToRegister(t *testing.T) { - a := NewAssembler(RegR10) - a.CompileMemoryWithRegisterOffsetToRegister(MOVD, RegR27, RegR10, RegR0) - actualNode := a.current - require.Equal(t, MOVD, actualNode.instruction) - require.Equal(t, RegR27, actualNode.srcReg) - require.Equal(t, RegR10, actualNode.srcReg2) - require.Equal(t, RegR0, actualNode.dstReg) - require.Equal(t, operandTypesMemoryToRegister, actualNode.types) -} - -func Test_CompileMemoryWithRegisterOffsetToVectorRegister(t *testing.T) { - a := NewAssembler(RegR10) - a.CompileMemoryWithRegisterOffsetToVectorRegister(MOVD, RegR27, RegR10, RegV31, VectorArrangementS) - actualNode := a.current - require.Equal(t, MOVD, actualNode.instruction) - require.Equal(t, RegR27, actualNode.srcReg) - require.Equal(t, RegR10, actualNode.srcReg2) - require.Equal(t, RegV31, actualNode.dstReg) - require.Equal(t, VectorArrangementS, actualNode.vectorArrangement) - require.Equal(t, operandTypesMemoryToVectorRegister, actualNode.types) -} - -func Test_CompileRegisterToMemoryWithRegisterOffset(t *testing.T) { - a := NewAssembler(RegR10) - a.CompileRegisterToMemoryWithRegisterOffset(MOVD, RegR27, RegR10, RegR0) - actualNode := a.current - require.Equal(t, MOVD, actualNode.instruction) - require.Equal(t, RegR27, actualNode.srcReg) - require.Equal(t, RegR10, actualNode.dstReg) - require.Equal(t, RegR0, actualNode.dstReg2) - require.Equal(t, operandTypesRegisterToMemory, actualNode.types) -} - -func Test_CompileVectorRegisterToMemoryWithRegisterOffset(t *testing.T) { - a := NewAssembler(RegR10) - a.CompileVectorRegisterToMemoryWithRegisterOffset(MOVD, RegV31, RegR10, RegR0, VectorArrangement2D) - actualNode := a.current - require.Equal(t, MOVD, actualNode.instruction) - require.Equal(t, RegV31, actualNode.srcReg) - require.Equal(t, RegR10, actualNode.dstReg) - require.Equal(t, RegR0, actualNode.dstReg2) - require.Equal(t, VectorArrangement2D, actualNode.vectorArrangement) - require.Equal(t, operandTypesVectorRegisterToMemory, actualNode.types) -} - -func Test_CompileTwoRegistersToRegister(t *testing.T) { - a := NewAssembler(RegR10) - a.CompileTwoRegistersToRegister(MOVD, RegR27, RegR10, RegR0) - actualNode := a.current - require.Equal(t, MOVD, actualNode.instruction) - require.Equal(t, RegR27, actualNode.srcReg) - require.Equal(t, RegR10, actualNode.srcReg2) - require.Equal(t, RegR0, actualNode.dstReg) - require.Equal(t, operandTypesTwoRegistersToRegister, actualNode.types) -} - -func Test_CompileThreeRegistersToRegister(t *testing.T) { - a := NewAssembler(RegR10) - a.CompileThreeRegistersToRegister(MOVD, RegR27, RegR10, RegR0, RegR28) - actualNode := a.current - require.Equal(t, MOVD, actualNode.instruction) - require.Equal(t, RegR27, actualNode.srcReg) - require.Equal(t, RegR10, actualNode.srcReg2) - require.Equal(t, RegR0, actualNode.dstReg) - require.Equal(t, RegR28, actualNode.dstReg2) - require.Equal(t, operandTypesThreeRegistersToRegister, actualNode.types) -} - -func Test_CompileTwoRegistersToNone(t *testing.T) { - a := NewAssembler(RegR10) - a.CompileTwoRegistersToNone(CMP, RegR27, RegR10) - actualNode := a.current - require.Equal(t, CMP, actualNode.instruction) - require.Equal(t, RegR27, actualNode.srcReg) - require.Equal(t, RegR10, actualNode.srcReg2) - require.Equal(t, operandTypesTwoRegistersToNone, actualNode.types) -} - -func Test_CompileRegisterAndConstToNone(t *testing.T) { - a := NewAssembler(RegR10) - a.CompileRegisterAndConstToNone(CMP, RegR27, 10) - actualNode := a.current - require.Equal(t, CMP, actualNode.instruction) - require.Equal(t, RegR27, actualNode.srcReg) - require.Equal(t, int64(10), actualNode.srcConst) - require.Equal(t, operandTypesRegisterAndConstToNone, actualNode.types) -} - -func Test_CompileRegisterAndConstToRegister(t *testing.T) { - a := NewAssembler(RegR10) - a.CompileRegisterAndConstToRegister(CMP, RegR27, 10, RegSP) - actualNode := a.current - require.Equal(t, CMP, actualNode.instruction) - require.Equal(t, RegR27, actualNode.srcReg) - require.Equal(t, int64(10), actualNode.srcConst) - require.Equal(t, RegSP, actualNode.dstReg) - require.Equal(t, operandTypesRegisterAndConstToRegister, actualNode.types) -} - -func Test_CompileLeftShiftedRegisterToRegister(t *testing.T) { - a := NewAssembler(RegR10) - a.CompileLeftShiftedRegisterToRegister(ADD, RegR27, 10, RegR28, RegR5) - actualNode := a.current - require.Equal(t, ADD, actualNode.instruction) - require.Equal(t, RegR28, actualNode.srcReg) - require.Equal(t, RegR27, actualNode.srcReg2) - require.Equal(t, int64(10), actualNode.srcConst) - require.Equal(t, RegR5, actualNode.dstReg) - require.Equal(t, operandTypesLeftShiftedRegisterToRegister, actualNode.types) -} - -func Test_CompileConditionalRegisterSet(t *testing.T) { - a := NewAssembler(RegR10) - a.CompileConditionalRegisterSet(CondNE, RegR10) - actualNode := a.current - require.Equal(t, CSET, actualNode.instruction) - require.Equal(t, RegCondNE, actualNode.srcReg) - require.Equal(t, RegR10, actualNode.dstReg) - require.Equal(t, operandTypesRegisterToRegister, actualNode.types) -} - -func Test_CompileMemoryToVectorRegister(t *testing.T) { - a := NewAssembler(RegR10) - a.CompileMemoryToVectorRegister(VMOV, RegR10, 10, RegV3, VectorArrangement1D) - actualNode := a.current - require.Equal(t, VMOV, actualNode.instruction) - require.Equal(t, RegR10, actualNode.srcReg) - require.Equal(t, int64(10), actualNode.srcConst) - require.Equal(t, RegV3, actualNode.dstReg) - require.Equal(t, operandTypesMemoryToVectorRegister, actualNode.types) - require.Equal(t, VectorArrangement1D, actualNode.vectorArrangement) -} - -func Test_CompileVectorRegisterToMemory(t *testing.T) { - a := NewAssembler(RegR10) - a.CompileVectorRegisterToMemory(VMOV, RegV3, RegR10, 12, VectorArrangement1D) - actualNode := a.current - require.Equal(t, VMOV, actualNode.instruction) - require.Equal(t, RegV3, actualNode.srcReg) - require.Equal(t, RegR10, actualNode.dstReg) - require.Equal(t, int64(12), actualNode.dstConst) - require.Equal(t, operandTypesVectorRegisterToMemory, actualNode.types) - require.Equal(t, VectorArrangement1D, actualNode.vectorArrangement) -} - -func Test_CompileRegisterToVectorRegister(t *testing.T) { - a := NewAssembler(RegR10) - a.CompileRegisterToVectorRegister(VMOV, RegV3, RegR10, VectorArrangement1D, 10) - actualNode := a.current - require.Equal(t, VMOV, actualNode.instruction) - require.Equal(t, RegV3, actualNode.srcReg) - require.Equal(t, RegR10, actualNode.dstReg) - require.Equal(t, operandTypesRegisterToVectorRegister, actualNode.types) - require.Equal(t, VectorArrangement1D, actualNode.vectorArrangement) - require.Equal(t, VectorIndex(10), actualNode.dstVectorIndex) -} - -func Test_CompileVectorRegisterToRegister(t *testing.T) { - a := NewAssembler(RegR10) - a.CompileVectorRegisterToRegister(VMOV, RegR10, RegV3, VectorArrangement1D, 10) - actualNode := a.current - require.Equal(t, VMOV, actualNode.instruction) - require.Equal(t, RegR10, actualNode.srcReg) - require.Equal(t, RegV3, actualNode.dstReg) - require.Equal(t, operandTypesVectorRegisterToRegister, actualNode.types) - require.Equal(t, VectorArrangement1D, actualNode.vectorArrangement) - require.Equal(t, VectorIndex(10), actualNode.srcVectorIndex) -} - -func Test_CompileVectorRegisterToVectorRegister(t *testing.T) { - a := NewAssembler(RegR10) - a.CompileVectorRegisterToVectorRegister(VMOV, RegV3, RegV10, VectorArrangement1D, 1, 2) - actualNode := a.current - require.Equal(t, VMOV, actualNode.instruction) - require.Equal(t, RegV3, actualNode.srcReg) - require.Equal(t, RegV10, actualNode.dstReg) - require.Equal(t, operandTypesVectorRegisterToVectorRegister, actualNode.types) - require.Equal(t, VectorArrangement1D, actualNode.vectorArrangement) - require.Equal(t, VectorIndex(1), actualNode.srcVectorIndex) - require.Equal(t, VectorIndex(2), actualNode.dstVectorIndex) -} - -func Test_CompileVectorRegisterToVectorRegisterWithConst(t *testing.T) { - a := NewAssembler(RegR10) - a.CompileVectorRegisterToVectorRegisterWithConst(VMOV, RegV3, RegV10, VectorArrangement1D, 1234) - actualNode := a.current - require.Equal(t, VMOV, actualNode.instruction) - require.Equal(t, RegV3, actualNode.srcReg) - require.Equal(t, RegV10, actualNode.dstReg) - require.Equal(t, operandTypesVectorRegisterToVectorRegister, actualNode.types) - require.Equal(t, VectorArrangement1D, actualNode.vectorArrangement) - require.Equal(t, int64(1234), actualNode.srcConst) -} - -func Test_CompileTwoVectorRegistersToVectorRegister(t *testing.T) { - a := NewAssembler(RegR10) - a.CompileTwoVectorRegistersToVectorRegister(VMOV, RegV3, RegV15, RegV10, VectorArrangement1D) - actualNode := a.current - require.Equal(t, VMOV, actualNode.instruction) - require.Equal(t, RegV3, actualNode.srcReg) - require.Equal(t, RegV15, actualNode.srcReg2) - require.Equal(t, RegV10, actualNode.dstReg) - require.Equal(t, operandTypesTwoVectorRegistersToVectorRegister, actualNode.types) - require.Equal(t, VectorArrangement1D, actualNode.vectorArrangement) -} - -func Test_CompileTwoVectorRegistersToVectorRegisterWithConst(t *testing.T) { - a := NewAssembler(RegR10) - a.CompileTwoVectorRegistersToVectorRegisterWithConst(VMOV, RegV3, RegV15, RegV10, VectorArrangement1D, 1234) - actualNode := a.current - require.Equal(t, VMOV, actualNode.instruction) - require.Equal(t, RegV3, actualNode.srcReg) - require.Equal(t, RegV15, actualNode.srcReg2) - require.Equal(t, int64(1234), actualNode.srcConst) - require.Equal(t, RegV10, actualNode.dstReg) - require.Equal(t, operandTypesTwoVectorRegistersToVectorRegister, actualNode.types) - require.Equal(t, VectorArrangement1D, actualNode.vectorArrangement) -} - -func Test_CompileStaticConstToVectorRegister(t *testing.T) { - s := asm.NewStaticConst([]byte{1, 2, 3, 4}) - a := NewAssembler(RegR10) - a.CompileStaticConstToVectorRegister(VMOV, s, RegV3, VectorArrangement2D) - actualNode := a.current - require.Equal(t, VMOV, actualNode.instruction) - require.Equal(t, s, actualNode.staticConst) - require.Equal(t, RegV3, actualNode.dstReg) - require.Equal(t, operandTypesStaticConstToVectorRegister, actualNode.types) - require.Equal(t, VectorArrangement2D, actualNode.vectorArrangement) -} - -func Test_CompileStaticConstToRegister(t *testing.T) { - s := asm.NewStaticConst([]byte{1, 2, 3, 4}) - a := NewAssembler(RegR10) - a.CompileStaticConstToRegister(ADR, s, RegR27) - actualNode := a.current - require.Equal(t, ADR, actualNode.instruction) - require.Equal(t, s, actualNode.staticConst) - require.Equal(t, RegR27, actualNode.dstReg) - require.Equal(t, operandTypesMemoryToRegister, actualNode.types) -} - -func Test_checkRegisterToRegisterType(t *testing.T) { - tests := []struct { - expErr string - src asm.Register - dst asm.Register - requireSrcInt bool - requireDstInt bool - }{ - {src: RegR10, dst: RegR30, requireSrcInt: true, requireDstInt: true, expErr: ""}, - {src: RegR10, dst: RegR30, requireSrcInt: false, requireDstInt: true, expErr: "src requires float register but got R10"}, - {src: RegR10, dst: RegR30, requireSrcInt: false, requireDstInt: false, expErr: "src requires float register but got R10"}, - {src: RegR10, dst: RegR30, requireSrcInt: true, requireDstInt: false, expErr: "dst requires float register but got R30"}, - - {src: RegR10, dst: RegV30, requireSrcInt: true, requireDstInt: false, expErr: ""}, - {src: RegR10, dst: RegV30, requireSrcInt: false, requireDstInt: true, expErr: "src requires float register but got R10"}, - {src: RegR10, dst: RegV30, requireSrcInt: false, requireDstInt: false, expErr: "src requires float register but got R10"}, - {src: RegR10, dst: RegV30, requireSrcInt: true, requireDstInt: true, expErr: "dst requires int register but got V30"}, - - {src: RegV10, dst: RegR30, requireSrcInt: false, requireDstInt: true, expErr: ""}, - {src: RegV10, dst: RegR30, requireSrcInt: true, requireDstInt: true, expErr: "src requires int register but got V10"}, - {src: RegV10, dst: RegR30, requireSrcInt: true, requireDstInt: false, expErr: "src requires int register but got V10"}, - {src: RegV10, dst: RegR30, requireSrcInt: false, requireDstInt: false, expErr: "dst requires float register but got R30"}, - - {src: RegV10, dst: RegV30, requireSrcInt: false, requireDstInt: false, expErr: ""}, - {src: RegV10, dst: RegV30, requireSrcInt: true, requireDstInt: false, expErr: "src requires int register but got V10"}, - {src: RegV10, dst: RegV30, requireSrcInt: true, requireDstInt: true, expErr: "src requires int register but got V10"}, - {src: RegV10, dst: RegV30, requireSrcInt: false, requireDstInt: true, expErr: "dst requires int register but got V30"}, - } - - for _, tt := range tests { - tc := tt - actual := checkRegisterToRegisterType(tc.src, tc.dst, tc.requireSrcInt, tc.requireDstInt) - if tc.expErr != "" { - require.EqualError(t, actual, tc.expErr) - } else { - require.NoError(t, actual) - } - } -} - -func TestAssemblerImpl_encodeNoneToNone(t *testing.T) { - t.Run("error", func(t *testing.T) { - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - a := NewAssembler(asm.NilRegister) - buf := code.NextCodeSection() - err := a.encodeNoneToNone(buf, &nodeImpl{instruction: ADD}) - require.EqualError(t, err, "ADD is unsupported for NoneToNone type") - }) - t.Run("NOP", func(t *testing.T) { - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - a := NewAssembler(asm.NilRegister) - buf := code.NextCodeSection() - err := a.encodeNoneToNone(buf, &nodeImpl{instruction: NOP}) - require.NoError(t, err) - - // NOP must be ignored. - actual := buf.Bytes() - require.Zero(t, len(actual)) - }) - t.Run("UDF", func(t *testing.T) { - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - a := NewAssembler(asm.NilRegister) - buf := code.NextCodeSection() - err := a.encodeNoneToNone(buf, &nodeImpl{instruction: UDF}) - require.NoError(t, err) - - actual := buf.Bytes() - require.Equal(t, []byte{0x0, 0x0, 0x0, 0x0}, actual, hex.EncodeToString(actual)) - }) - t.Run("dmb ish", func(t *testing.T) { - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - a := NewAssembler(asm.NilRegister) - buf := code.NextCodeSection() - err := a.encodeNoneToNone(buf, &nodeImpl{instruction: DMB}) - require.NoError(t, err) - - actual := buf.Bytes() - require.Equal(t, []byte{0xbf, 0x3b, 0x3, 0xd5}, actual, hex.EncodeToString(actual)) - }) -} - -func Test_validateMemoryOffset(t *testing.T) { - tests := []struct { - expErr string - offset int64 - }{ - {offset: 0}, - {offset: -256}, - {offset: 255}, - {offset: 123 * 8}, - {offset: 123 * 4}, - {offset: -257, expErr: "negative memory offset must be larget than or equal -256 but got -257"}, - {offset: 257, expErr: "large memory offset (>255) must be a multiple of 4 but got 257"}, - } - - for _, tt := range tests { - tc := tt - actual := validateMemoryOffset(tc.offset) - if tc.expErr == "" { - require.NoError(t, actual) - } else { - require.EqualError(t, actual, tc.expErr) - } - } -} - -func TestAssemblerImpl_EncodeVectorRegisterToMemory(t *testing.T) { - tests := []struct { - name string - n *nodeImpl - exp []byte - }{ - // Register offset cases. - { - name: "str b11, [x12, x6]", - n: &nodeImpl{ - instruction: VMOV, - srcReg: RegV11, - dstReg: RegR12, - dstReg2: RegR6, - vectorArrangement: VectorArrangementB, - }, - exp: []byte{0x8b, 0x69, 0x26, 0x3c}, - }, - { - name: "str h11, [x12, x6]", - n: &nodeImpl{ - instruction: VMOV, - srcReg: RegV11, - dstReg: RegR0, - dstReg2: RegR6, - vectorArrangement: VectorArrangementH, - }, - exp: []byte{0xb, 0x68, 0x26, 0x7c}, - }, - { - name: "str s11, [x29, x6]", - n: &nodeImpl{ - instruction: VMOV, - srcReg: RegV11, - dstReg: RegR29, - dstReg2: RegR6, - vectorArrangement: VectorArrangementS, - }, - exp: []byte{0xab, 0x6b, 0x26, 0xbc}, - }, - { - name: "str d0, [x0, x0]", - n: &nodeImpl{ - instruction: VMOV, - srcReg: RegV0, - dstReg: RegR0, - dstReg2: RegR0, - vectorArrangement: VectorArrangementD, - }, - exp: []byte{0x0, 0x68, 0x20, 0xfc}, - }, - { - name: "str q30, [x30, x29]", - n: &nodeImpl{ - instruction: VMOV, - srcReg: RegV30, - dstReg: RegR30, - dstReg2: RegR29, - vectorArrangement: VectorArrangementQ, - }, - exp: []byte{0xde, 0x6b, 0xbd, 0x3c}, - }, - // Constant offset cases. - { - name: "str b11, [x12, #0x7b]", - n: &nodeImpl{ - instruction: VMOV, - srcReg: RegV11, - dstReg: RegR12, - dstConst: 0x7b, - vectorArrangement: VectorArrangementB, - }, - exp: []byte{0x8b, 0xed, 0x1, 0x3d}, - }, - { - name: "ldr w10, #0xc ; str h11, [x12, x10]", - n: &nodeImpl{ - instruction: VMOV, - srcReg: RegV11, - dstReg: RegR12, - dstConst: 1 << 30, - vectorArrangement: VectorArrangementH, - }, - exp: []byte{0x6a, 0x0, 0x0, 0x18, 0x8b, 0x69, 0x2a, 0x7c, 0x0, 0x0, 0x0, 0x14, 0x0, 0x0, 0x0, 0x40}, - }, - { - name: "ldr w10, #0xc ; str s11, [x12, x10]", - n: &nodeImpl{ - instruction: VMOV, - srcReg: RegV11, - dstReg: RegR12, - dstConst: (1 << 28) + 4, - vectorArrangement: VectorArrangementS, - }, - exp: []byte{0x6a, 0x0, 0x0, 0x18, 0x8b, 0x69, 0x2a, 0xbc, 0x0, 0x0, 0x0, 0x14, 0x4, 0x0, 0x0, 0x10}, - }, - { - name: "str d11, [x12, #0x3d8]", - n: &nodeImpl{ - instruction: VMOV, - srcReg: RegV11, - dstReg: RegR12, - dstConst: 0x3d8, - vectorArrangement: VectorArrangementD, - }, - exp: []byte{0x8b, 0xed, 0x1, 0xfd}, - }, - { - name: "stur q1, [x30, #1]", - n: &nodeImpl{ - instruction: VMOV, - srcReg: RegV1, - dstReg: RegR30, - dstConst: 1, - vectorArrangement: VectorArrangementQ, - }, - exp: []byte{0xc1, 0x13, 0x80, 0x3c}, - }, - { - name: "str q1, [x30, #0x100]", - n: &nodeImpl{ - instruction: VMOV, - srcReg: RegV1, - dstReg: RegR30, - dstConst: 0x100, - vectorArrangement: VectorArrangementQ, - }, - exp: []byte{0xc1, 0x43, 0x80, 0x3d}, - }, - { - name: "stur q1, [x30, #0xfc]", - n: &nodeImpl{ - instruction: VMOV, - srcReg: RegV1, - dstReg: RegR30, - // This offset is not a multiple of 16 bytes, but fits in 9-bit signed integer, - // therefore it can be encoded as one instruction of "unscaled immediate". - dstConst: 0xfc, - vectorArrangement: VectorArrangementQ, - }, - exp: []byte{0xc1, 0xc3, 0x8f, 0x3c}, - }, - { - name: `ldr w10, #0xc; str q11, [x12, x10]`, - n: &nodeImpl{ - instruction: VMOV, - srcReg: RegV11, - dstReg: RegR12, - // This case offset is not a multiple of 16 bytes and doesn't fit in 9-bit signed integer, - // therefore, we encode the offset in a temporary register, then store it with the register offset variant. - dstConst: 0x108, - vectorArrangement: VectorArrangementQ, - }, - exp: []byte{0x6a, 0x0, 0x0, 0x18, 0x8b, 0x69, 0xaa, 0x3c, 0x0, 0x0, 0x0, 0x14, 0x8, 0x1, 0x0, 0x0}, - }, - } - - for _, tt := range tests { - tc := tt - t.Run(tc.name, func(t *testing.T) { - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - a := NewAssembler(RegR10) - buf := code.NextCodeSection() - err := a.encodeVectorRegisterToMemory(buf, tc.n) - require.NoError(t, err) - - a.maybeFlushConstPool(buf, true) - - err = a.Assemble(buf) - require.NoError(t, err) - - actual := buf.Bytes() - require.Equal(t, tc.exp, actual, hex.EncodeToString(actual)) - }) - } -} - -func TestAssemblerImpl_EncodeMemoryToVectorRegister(t *testing.T) { - tests := []struct { - name string - n *nodeImpl - exp []byte - }{ - // ldr Register offset cases. - { - name: "ldr b11, [x12, x8]", - n: &nodeImpl{ - instruction: VMOV, - srcReg: RegR12, - srcReg2: RegR8, - dstReg: RegV11, - vectorArrangement: VectorArrangementB, - }, - exp: []byte{0x8b, 0x69, 0x68, 0x3c}, - }, - { - name: "ldr h11, [x30, x0]", - n: &nodeImpl{ - instruction: VMOV, - srcReg: RegR30, - srcReg2: RegR0, - dstReg: RegV11, - vectorArrangement: VectorArrangementH, - }, - exp: []byte{0xcb, 0x6b, 0x60, 0x7c}, - }, - { - name: "ldr s11, [x0, x30]", - n: &nodeImpl{ - instruction: VMOV, - srcReg: RegR0, - srcReg2: RegR30, - dstReg: RegV11, - vectorArrangement: VectorArrangementS, - }, - exp: []byte{0xb, 0x68, 0x7e, 0xbc}, - }, - { - name: "ldr d11, [x15, x15]", - n: &nodeImpl{ - instruction: VMOV, - srcReg: RegR15, - srcReg2: RegR15, - dstReg: RegV11, - vectorArrangement: VectorArrangementD, - }, - exp: []byte{0xeb, 0x69, 0x6f, 0xfc}, - }, - { - name: "ldr q30, [x0, x0]", - n: &nodeImpl{ - instruction: VMOV, - srcReg: RegR0, - srcReg2: RegR0, - dstReg: RegV30, - vectorArrangement: VectorArrangementQ, - }, - exp: []byte{0x1e, 0x68, 0xe0, 0x3c}, - }, - // ldr Constant offset cases. - { - name: "ldr b11, [x12, #0x7b]", - n: &nodeImpl{ - instruction: VMOV, - srcReg: RegR12, - srcConst: 0x7b, - dstReg: RegV11, - vectorArrangement: VectorArrangementB, - }, - exp: []byte{0x8b, 0xed, 0x41, 0x3d}, - }, - { - name: "str h11, [x12, w30, uxtw]", - n: &nodeImpl{ - instruction: VMOV, - dstReg: RegV11, - srcReg: RegR12, - vectorArrangement: VectorArrangementH, - }, - exp: []byte{0x8b, 0x1, 0x40, 0x7d}, - }, - { - name: "ldr w10, #0xc ; ldr s11, [x12, x10]", - n: &nodeImpl{ - instruction: VMOV, - dstReg: RegV11, - srcReg: RegR12, - srcConst: 1 << 28, - vectorArrangement: VectorArrangementS, - }, - exp: []byte{0x6a, 0x0, 0x0, 0x18, 0x8b, 0x69, 0x6a, 0xbc, 0x0, 0x0, 0x0, 0x14, 0x0, 0x0, 0x0, 0x10}, - }, - { - name: "ldr w10, #0xc ; ldr d11, [x12, x10]", - n: &nodeImpl{ - instruction: VMOV, - dstReg: RegV11, - srcReg: RegR12, - srcConst: 1<<29 + 4, - vectorArrangement: VectorArrangementD, - }, - exp: []byte{0x6a, 0x0, 0x0, 0x18, 0x8b, 0x69, 0x6a, 0xfc, 0x0, 0x0, 0x0, 0x14, 0x4, 0x0, 0x0, 0x20}, - }, - { - name: "ldr w10, #0xc ; ldr q1, [x30, x10]", - n: &nodeImpl{ - instruction: VMOV, - dstReg: RegV1, - srcReg: RegR30, - srcConst: 1<<17 + 4, - vectorArrangement: VectorArrangementQ, - }, - exp: []byte{0x6a, 0x0, 0x0, 0x18, 0xc1, 0x6b, 0xea, 0x3c, 0x0, 0x0, 0x0, 0x14, 0x4, 0x0, 0x2, 0x0}, - }, - { - name: "ld1r {v11.8b}, [x12]", - n: &nodeImpl{ - instruction: LD1R, - srcReg: RegR12, - dstReg: RegV11, - vectorArrangement: VectorArrangement8B, - }, - exp: []byte{0x8b, 0xc1, 0x40, 0xd}, - }, - { - name: "ld1r {v11.16b}, [x12]", - n: &nodeImpl{ - instruction: LD1R, - srcReg: RegR12, - dstReg: RegV11, - vectorArrangement: VectorArrangement16B, - }, - exp: []byte{0x8b, 0xc1, 0x40, 0x4d}, - }, - { - name: "ld1r {v11.4h}, [x12]", - n: &nodeImpl{ - instruction: LD1R, - srcReg: RegR12, - dstReg: RegV11, - vectorArrangement: VectorArrangement4H, - }, - exp: []byte{0x8b, 0xc5, 0x40, 0xd}, - }, - { - name: "ld1r {v9.8h}, [x0]", - n: &nodeImpl{ - instruction: LD1R, - srcReg: RegR0, - dstReg: RegV0, - vectorArrangement: VectorArrangement8H, - }, - exp: []byte{0x0, 0xc4, 0x40, 0x4d}, - }, - { - name: "ld1r {v11.2s}, [x12]", - n: &nodeImpl{ - instruction: LD1R, - srcReg: RegR12, - dstReg: RegV11, - vectorArrangement: VectorArrangement2S, - }, - exp: []byte{0x8b, 0xc9, 0x40, 0xd}, - }, - { - name: "ld1r {v0.4s}, [x0]", - n: &nodeImpl{ - instruction: LD1R, - srcReg: RegR0, - dstReg: RegV0, - vectorArrangement: VectorArrangement4S, - }, - exp: []byte{0x0, 0xc8, 0x40, 0x4d}, - }, - { - name: "ld1r {v11.1d}, [x12]", - n: &nodeImpl{ - instruction: LD1R, - srcReg: RegR12, - dstReg: RegV11, - vectorArrangement: VectorArrangement1D, - }, - exp: []byte{0x8b, 0xcd, 0x40, 0xd}, - }, - { - name: "ld1r {v0.2d}, [x0]", - n: &nodeImpl{ - instruction: LD1R, - srcReg: RegR0, - dstReg: RegV0, - vectorArrangement: VectorArrangement2D, - }, - exp: []byte{0x0, 0xcc, 0x40, 0x4d}, - }, - } - - for _, tt := range tests { - tc := tt - t.Run(tc.name, func(t *testing.T) { - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - a := NewAssembler(RegR10) - buf := code.NextCodeSection() - err := a.encodeMemoryToVectorRegister(buf, tc.n) - require.NoError(t, err) - - a.maybeFlushConstPool(buf, true) - - err = a.Assemble(buf) - require.NoError(t, err) - - actual := buf.Bytes() - require.Equal(t, tc.exp, actual, hex.EncodeToString(actual)) - }) - } -} - -func TestAssemblerImpl_EncodeVectorRegisterToVectorRegister(t *testing.T) { - tests := []struct { - name string - exp []byte - c asm.ConstantValue - inst asm.Instruction - x1 asm.Register - x2 asm.Register - arr VectorArrangement - srcIndex VectorIndex - dstIndex VectorIndex - }{ - { - inst: XTN, - name: "xtn v10.2s, v2.2d", - x1: RegV2, - x2: RegV10, - arr: VectorArrangement2D, - exp: []byte{0x4a, 0x28, 0xa1, 0xe}, - }, - { - inst: XTN, - name: "xtn v10.4h, v2.4s", - x1: RegV2, - x2: RegV10, - arr: VectorArrangement4S, - exp: []byte{0x4a, 0x28, 0x61, 0xe}, - }, - { - inst: XTN, - name: "xtn v10.8b, v2.8h", - x1: RegV2, - x2: RegV10, - arr: VectorArrangement8H, - exp: []byte{0x4a, 0x28, 0x21, 0xe}, - }, - { - inst: REV64, - name: "rev64 v10.16b, v2.16b", - x1: RegV2, - x2: RegV10, - arr: VectorArrangement16B, - exp: []byte{0x4a, 0x8, 0x20, 0x4e}, - }, - { - inst: REV64, - name: "rev64 v10.4s, v2.4s", - x1: RegV2, - x2: RegV10, - arr: VectorArrangement4S, - exp: []byte{0x4a, 0x8, 0xa0, 0x4e}, - }, - { - inst: VCNT, - name: "cnt v10.16b, v2.16b", - x1: RegV2, - x2: RegV10, - arr: VectorArrangement16B, - exp: []byte{0x4a, 0x58, 0x20, 0x4e}, - }, - { - inst: VCNT, - name: "cnt v10.8b, v2.8b", - x1: RegV2, - x2: RegV10, - arr: VectorArrangement8B, - exp: []byte{0x4a, 0x58, 0x20, 0xe}, - }, - { - inst: VNEG, - name: "neg v10.16b, v2.16b", - x1: RegV2, - x2: RegV10, - arr: VectorArrangement16B, - exp: []byte{0x4a, 0xb8, 0x20, 0x6e}, - }, - { - inst: VNEG, - name: "neg v10.8h, v2.18h", - x1: RegV2, - x2: RegV10, - arr: VectorArrangement8H, - exp: []byte{0x4a, 0xb8, 0x60, 0x6e}, - }, - { - inst: VNEG, - name: "neg v10.4s, v2.4s", - x1: RegV2, - x2: RegV10, - arr: VectorArrangement4S, - exp: []byte{0x4a, 0xb8, 0xa0, 0x6e}, - }, - { - inst: VNEG, - name: "neg v10.2d, v2.2d", - x1: RegV2, - x2: RegV10, - arr: VectorArrangement2D, - exp: []byte{0x4a, 0xb8, 0xe0, 0x6e}, - }, - { - inst: VABS, - name: "abs v10.16b, v2.16b", - x1: RegV2, - x2: RegV10, - arr: VectorArrangement16B, - exp: []byte{0x4a, 0xb8, 0x20, 0x4e}, - }, - { - inst: VABS, - name: "abs v10.8h, v2.18h", - x1: RegV2, - x2: RegV10, - arr: VectorArrangement8H, - exp: []byte{0x4a, 0xb8, 0x60, 0x4e}, - }, - { - inst: VABS, - name: "abs v10.4s, v2.4s", - x1: RegV2, - x2: RegV10, - arr: VectorArrangement4S, - exp: []byte{0x4a, 0xb8, 0xa0, 0x4e}, - }, - { - inst: VABS, - name: "abs v10.2d, v2.2d", - x1: RegV2, - x2: RegV10, - arr: VectorArrangement2D, - exp: []byte{0x4a, 0xb8, 0xe0, 0x4e}, - }, - { - inst: ZIP1, - name: "zip1 v10.16b, v10.16b, v2.16b", - x1: RegV2, - x2: RegV10, - arr: VectorArrangement16B, - exp: []byte{0x4a, 0x39, 0x2, 0x4e}, - }, - { - inst: ADDV, - name: "addv b10, v2.16b", - x1: RegV2, - x2: RegV10, - arr: VectorArrangement16B, - exp: []byte{0x4a, 0xb8, 0x31, 0x4e}, - }, - { - inst: VORR, - name: "orr v10.16b, v10.16b, v2.16b", - x1: RegV2, - x2: RegV10, - arr: VectorArrangement16B, - exp: []byte{0x4a, 0x1d, 0xa2, 0x4e}, - }, - { - inst: VORR, - name: "orr v10.8b, v10.8b, v2.8b", - x1: RegV2, - x2: RegV10, - arr: VectorArrangement8B, - exp: []byte{0x4a, 0x1d, 0xa2, 0xe}, - }, - { - name: "fadd v10.2d, v10.2d, v2.2d", - x1: RegV2, - x2: RegV10, - inst: VFADDD, - arr: VectorArrangement2D, - exp: []byte{0x4a, 0xd5, 0x62, 0x4e}, - }, - { - name: "fadd v10.4s, v10.4s, v2.4s", - x1: RegV2, - x2: RegV10, - inst: VFADDS, - arr: VectorArrangement4S, - exp: []byte{0x4a, 0xd5, 0x22, 0x4e}, - }, - { - name: "fsub v10.2d, v10.2d, v2.2d", - x1: RegV2, - x2: RegV10, - inst: VFSUBD, - arr: VectorArrangement2D, - exp: []byte{0x4a, 0xd5, 0xe2, 0x4e}, - }, - { - name: "fsub v10.4s, v10.4s, v2.4s", - x1: RegV2, - x2: RegV10, - inst: VFSUBS, - arr: VectorArrangement4S, - exp: []byte{0x4a, 0xd5, 0xa2, 0x4e}, - }, - { - name: "ushll v10.8h, v2.8b, #0", - x1: RegV2, - x2: RegV10, - inst: USHLL, - exp: []byte{0x4a, 0xa4, 0x8, 0x2f}, - arr: VectorArrangement8B, - }, - { - name: "ushll v10.8h, v2.8b, #7", - x1: RegV2, - x2: RegV10, - inst: USHLL, - exp: []byte{0x4a, 0xa4, 0xf, 0x2f}, - arr: VectorArrangement8B, - c: 7, - }, - { - name: "10.8h, v2.8b, #0", - x1: RegV2, - x2: RegV10, - inst: SSHR, - exp: []byte{0x4a, 0x4, 0x8, 0x4f}, - arr: VectorArrangement16B, - c: 8, - }, - { - name: "sshr v10.16b, v2.16b, #3", - x1: RegV2, - x2: RegV10, - inst: SSHR, - exp: []byte{0x4a, 0x4, 0xd, 0x4f}, - arr: VectorArrangement16B, - c: 3, - }, - { - name: "sshr v10.16b, v2.16b, #1", - x1: RegV2, - x2: RegV10, - inst: SSHR, - exp: []byte{0x4a, 0x4, 0xf, 0x4f}, - arr: VectorArrangement16B, - c: 1, - }, - { - name: "sshr v10.8b, v2.8b, #3", - x1: RegV2, - x2: RegV10, - inst: SSHR, - exp: []byte{0x4a, 0x4, 0xd, 0xf}, - arr: VectorArrangement8B, - c: 3, - }, - { - name: "sshr v10.8h, v2.8h, #0x10", - x1: RegV2, - x2: RegV10, - inst: SSHR, - exp: []byte{0x4a, 0x4, 0x10, 0x4f}, - arr: VectorArrangement8H, - c: 16, - }, - { - name: "sshr v10.8h, v2.8h, #0xf", - x1: RegV2, - x2: RegV10, - inst: SSHR, - exp: []byte{0x4a, 0x4, 0x11, 0x4f}, - arr: VectorArrangement8H, - c: 15, - }, - { - name: "sshr v10.8h, v2.8h, #3", - x1: RegV2, - x2: RegV10, - inst: SSHR, - exp: []byte{0x4a, 0x4, 0x1d, 0x4f}, - arr: VectorArrangement8H, - c: 3, - }, - { - name: "sshr v10.4h, v2.4h, #0xf", - x1: RegV2, - x2: RegV10, - inst: SSHR, - exp: []byte{0x4a, 0x4, 0x11, 0xf}, - arr: VectorArrangement4H, - c: 15, - }, - { - name: "sshr v10.2s, v2.2s, #0x20", - x1: RegV2, - x2: RegV10, - inst: SSHR, - exp: []byte{0x4a, 0x4, 0x20, 0xf}, - arr: VectorArrangement2S, - c: 32, - }, - { - name: "sshr v10.2s, v2.2s, #0x1f", - x1: RegV2, - x2: RegV10, - inst: SSHR, - exp: []byte{0x4a, 0x4, 0x21, 0xf}, - arr: VectorArrangement2S, - c: 31, - }, - { - name: "sshr v10.2s, v2.2s, #7", - x1: RegV2, - x2: RegV10, - inst: SSHR, - exp: []byte{0x4a, 0x4, 0x39, 0xf}, - arr: VectorArrangement2S, - c: 7, - }, - { - name: "sshr v10.4s, v2.4s, #7", - x1: RegV2, - x2: RegV10, - inst: SSHR, - exp: []byte{0x4a, 0x4, 0x39, 0x4f}, - arr: VectorArrangement4S, - c: 7, - }, - { - name: "sshr v10.2d, v2.2d, #0x3f", - x1: RegV2, - x2: RegV10, - inst: SSHR, - exp: []byte{0x4a, 0x4, 0x41, 0x4f}, - arr: VectorArrangement2D, - c: 63, - }, - { - name: "sshr v10.2d, v2.2d, #0x21", - x1: RegV2, - x2: RegV10, - inst: SSHR, - exp: []byte{0x4a, 0x4, 0x5f, 0x4f}, - arr: VectorArrangement2D, - c: 33, - }, - { - name: "sshr v10.2d, v2.2d, #1", - x1: RegV2, - x2: RegV10, - inst: SSHR, - exp: []byte{0x4a, 0x4, 0x7f, 0x4f}, - arr: VectorArrangement2D, - c: 1, - }, - { - name: "sshll v10.8h, v2.8b, #7", - x1: RegV2, - x2: RegV10, - inst: SSHLL, exp: []byte{0x4a, 0xa4, 0xf, 0xf}, - arr: VectorArrangement8B, - c: 7, - }, - { - name: "sshll v10.4s, v2.4h, #0", - x1: RegV2, - x2: RegV10, - inst: SSHLL, - exp: []byte{0x4a, 0xa4, 0x10, 0xf}, - arr: VectorArrangement4H, - }, - { - name: "sshll v10.4s, v2.4h, #0xf", - x1: RegV2, - x2: RegV10, - inst: SSHLL, - exp: []byte{0x4a, 0xa4, 0x1f, 0xf}, - arr: VectorArrangement4H, - c: 15, - }, - { - name: "sshll v10.2d, v2.2s, #0", - x1: RegV2, - x2: RegV10, - inst: SSHLL, - exp: []byte{0x4a, 0xa4, 0x20, 0xf}, - arr: VectorArrangement2S, - }, - { - name: "sshll v10.2d, v2.2s, #0x1f", - x1: RegV2, - x2: RegV10, - inst: SSHLL, - exp: []byte{0x4a, 0xa4, 0x3f, 0xf}, - arr: VectorArrangement2S, - c: 31, - }, - { - x1: RegV2, - x2: RegV10, - name: "ins v10.s[2], v2.s[1]", - inst: INSELEM, - exp: []byte{0x4a, 0x24, 0x14, 0x6e}, - arr: VectorArrangementS, - srcIndex: 1, - dstIndex: 2, - }, - { - x1: RegV2, - x2: RegV10, - name: "ins v10.s[0], v2.s[3]", - inst: INSELEM, - exp: []byte{0x4a, 0x64, 0x4, 0x6e}, - arr: VectorArrangementS, - srcIndex: 3, - dstIndex: 0, - }, - { - x1: RegV2, - x2: RegV10, - name: "ins v10.b[0], v2.b[0xf]", - inst: INSELEM, - exp: []byte{0x4a, 0x7c, 0x1, 0x6e}, - arr: VectorArrangementB, - srcIndex: 15, - dstIndex: 0, - }, - { - x1: RegV2, - x2: RegV10, - name: "ins v10.d[1], v2.d[0]", - inst: INSELEM, - exp: []byte{0x4a, 0x4, 0x18, 0x6e}, - arr: VectorArrangementD, - srcIndex: 0, - dstIndex: 1, - }, - { - x1: RegV2, - x2: RegV10, - name: "dup v10.2d, v2.d[0]", - inst: DUPELEM, - exp: []byte{0x4a, 0x4, 0x8, 0x4e}, - arr: VectorArrangementD, - srcIndex: 0, - }, - { - x1: RegV2, - x2: RegV10, - name: "dup v10.2d, v2.d[1]", - inst: DUPELEM, - exp: []byte{0x4a, 0x4, 0x18, 0x4e}, - arr: VectorArrangementD, - srcIndex: 1, - }, - { - x1: RegV2, - x2: RegV10, - name: "dup v10.4s, v2.s[3]", - inst: DUPELEM, - exp: []byte{0x4a, 0x4, 0x1c, 0x4e}, - arr: VectorArrangementS, - srcIndex: 3, - }, - { - x1: RegV2, - x2: RegV10, - name: "dup v10.8h, v2.h[7]", - inst: DUPELEM, - exp: []byte{0x4a, 0x4, 0x1e, 0x4e}, - arr: VectorArrangementH, - srcIndex: 7, - }, - { - x1: RegV2, - x2: RegV10, - name: "dup v10.16b, v2.b[0xf]", - inst: DUPELEM, - exp: []byte{0x4a, 0x4, 0x1f, 0x4e}, - arr: VectorArrangementB, - srcIndex: 15, - }, - { - x1: RegV2, - x2: RegV10, - name: "umaxp v10.16b, v10.16b, v2.16b", - inst: UMAXP, - exp: []byte{0x4a, 0xa5, 0x22, 0x6e}, - arr: VectorArrangement16B, - }, - { - x1: RegV2, - x2: RegV10, - name: "umaxp v10.8h, v10.8h, v2.8h", - inst: UMAXP, - exp: []byte{0x4a, 0xa5, 0x62, 0x6e}, - arr: VectorArrangement8H, - }, - { - x1: RegV2, - x2: RegV10, - name: "umaxp v10.4s, v10.4s, v2.4s", - inst: UMAXP, - exp: []byte{0x4a, 0xa5, 0xa2, 0x6e}, - arr: VectorArrangement4S, - }, - { - x1: RegV11, - x2: RegV11, - name: "addp d11, v11.2d", - inst: ADDP, - arr: VectorArrangement2D, - exp: []byte{0x6b, 0xb9, 0xf1, 0x5e}, - }, - { - x1: RegV2, - x2: RegV10, - name: "addp v10.16b, v10.16b, v2.16b", - inst: VADDP, - exp: []byte{0x4a, 0xbd, 0x22, 0x4e}, - arr: VectorArrangement16B, - }, - { - x1: RegV2, - x2: RegV10, - name: "addp v10.8h, v10.8h, v2.8h", - inst: VADDP, - exp: []byte{0x4a, 0xbd, 0x62, 0x4e}, - arr: VectorArrangement8H, - }, - { - x1: RegV2, - x2: RegV10, - name: "addp v10.4s, v10.4s, v2.4s", - inst: VADDP, - exp: []byte{0x4a, 0xbd, 0xa2, 0x4e}, - arr: VectorArrangement4S, - }, - { - x1: RegV2, - x2: RegV10, - name: "uminv b10, v2.16b", - inst: UMINV, - exp: []byte{0x4a, 0xa8, 0x31, 0x6e}, - arr: VectorArrangement16B, - }, - { - x1: RegV2, - x2: RegV10, - name: "uminv h10, v2.8h", - inst: UMINV, - exp: []byte{0x4a, 0xa8, 0x71, 0x6e}, - arr: VectorArrangement8H, - }, - { - x1: RegV2, - x2: RegV10, - name: "uminv s10, v2.4s", - inst: UMINV, - exp: []byte{0x4a, 0xa8, 0xb1, 0x6e}, - arr: VectorArrangement4S, - }, - { - x1: RegV2, - x2: RegV10, - name: "cmeq v10.2d, v10.2d, v2.2d", - arr: VectorArrangement2D, - inst: CMEQ, - exp: []byte{0x4a, 0x8d, 0xe2, 0x6e}, - }, - { - x1: RegRZR, - x2: RegV12, - name: "cmeq v12.2d, v12.2d, #0", - inst: CMEQZERO, - arr: VectorArrangement2D, - exp: []byte{0x8c, 0x99, 0xe0, 0x4e}, - }, - { - name: "tbl v1.8b, {v0.16b}, v1.8b", - x1: RegV0, - x2: RegV1, - inst: TBL1, - arr: VectorArrangement8B, - exp: []byte{0x1, 0x0, 0x1, 0xe}, - }, - { - name: "tbl v1.16b, {v0.16b}, v1.16b", - x1: RegV0, - x2: RegV1, - inst: TBL1, - arr: VectorArrangement16B, - exp: []byte{0x1, 0x0, 0x1, 0x4e}, - }, - { - name: "tbl v30.8b, {v0.16b, v1.16b}, v30.8b", - x1: RegV0, - x2: RegV30, - inst: TBL2, - arr: VectorArrangement8B, - exp: []byte{0x1e, 0x20, 0x1e, 0xe}, - }, - { - name: "tbl v1.16b, {v31.16b, v0.16b}, v1.16b", - x1: RegV31, - x2: RegV1, - inst: TBL2, - arr: VectorArrangement16B, - exp: []byte{0xe1, 0x23, 0x1, 0x4e}, - }, - { - x1: RegV2, - x2: RegV10, - name: "add v10.4s, v10.4s, v2.4s", - inst: VADD, - exp: []byte{0x4a, 0x85, 0xa2, 0x4e}, - arr: VectorArrangement4S, - }, - { - x1: RegV2, - x2: RegV10, - name: "add v10.2d, v10.2d, v2.2d", - inst: VADD, - exp: []byte{0x4a, 0x85, 0xe2, 0x4e}, - arr: VectorArrangement2D, - }, - { - x1: RegV2, - x2: RegV10, - name: "sub v10.8h, v10.8h, v2.8h", - inst: VSUB, - exp: []byte{0x4a, 0x85, 0x62, 0x6e}, - arr: VectorArrangement8H, - }, - { - x1: RegV29, - x2: RegV30, - name: "sub v30.16b, v30.16b, v29.16b", - inst: VSUB, - exp: []byte{0xde, 0x87, 0x3d, 0x6e}, - arr: VectorArrangement16B, - }, - { - name: "bic v10.16b, v10.16b, v2.16b", - x1: RegV2, - x2: RegV10, - inst: BIC, - arr: VectorArrangement16B, - exp: []byte{0x4a, 0x1d, 0x62, 0x4e}, - }, - { - name: "eor v10.16b, v10.16b, v2.16b", - x1: RegV2, - x2: RegV10, - inst: EOR, - arr: VectorArrangement16B, - exp: []byte{0x4a, 0x1d, 0x22, 0x6e}, - }, - { - name: "bsl v10.16b, v10.16b, v2.16b", - x1: RegV2, - x2: RegV10, - inst: BSL, - arr: VectorArrangement16B, - exp: []byte{0x4a, 0x1d, 0x62, 0x6e}, - }, - { - name: "bsl v10.16b, v10.16b, v2.16b", - x1: RegV2, - x2: RegV10, - inst: BSL, - arr: VectorArrangement16B, - exp: []byte{0x4a, 0x1d, 0x62, 0x6e}, - }, - { - name: "and v10.16b, v10.16b, v2.16b", - x1: RegV2, - x2: RegV10, - inst: VAND, - arr: VectorArrangement16B, - exp: []byte{0x4a, 0x1d, 0x22, 0x4e}, - }, - { - // mvn is an alias of NOT: https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/MVN--Bitwise-NOT--vector---an-alias-of-NOT-?lang=en - name: "mvn v10.16b, v2.16b", - x1: RegV2, - x2: RegV10, - inst: NOT, - arr: VectorArrangement16B, - exp: []byte{0x4a, 0x58, 0x20, 0x6e}, - }, - { - name: "fneg v10.2d, v2.2d", - x1: RegV2, - x2: RegV10, - inst: VFNEG, - arr: VectorArrangement2D, - exp: []byte{0x4a, 0xf8, 0xe0, 0x6e}, - }, - { - name: "fneg v10.4s, v2.4s", - x1: RegV2, - x2: RegV10, - inst: VFNEG, - arr: VectorArrangement4S, - exp: []byte{0x4a, 0xf8, 0xa0, 0x6e}, - }, - { - x1: RegV2, - x2: RegV10, - name: "sshl v10.2d, v10.2d, v2.2d", - inst: SSHL, - exp: []byte{0x4a, 0x45, 0xe2, 0x4e}, - arr: VectorArrangement2D, - }, - { - x1: RegV25, - x2: RegV30, - name: "sshl v30.4s, v30.4s, v25.4s", - inst: SSHL, - exp: []byte{0xde, 0x47, 0xb9, 0x4e}, - arr: VectorArrangement4S, - }, - { - x1: RegV2, - x2: RegV10, - name: "ushl v10.8h, v10.8h, v2.8h", - inst: USHL, - exp: []byte{0x4a, 0x45, 0x62, 0x6e}, - arr: VectorArrangement8H, - }, - { - x1: RegV25, - x2: RegV30, - name: "ushl v30.16b, v30.16b, v25.16b", - inst: USHL, - exp: []byte{0xde, 0x47, 0x39, 0x6e}, - arr: VectorArrangement16B, - }, - { - x1: RegV25, - x2: RegV30, - name: "fabs v30.4s, v25.4s", - inst: VFABS, - exp: []byte{0x3e, 0xfb, 0xa0, 0x4e}, - arr: VectorArrangement4S, - }, - { - x1: RegV25, - x2: RegV30, - name: "fabs v30.2s, v25.2s", - inst: VFABS, - exp: []byte{0x3e, 0xfb, 0xa0, 0xe}, - arr: VectorArrangement2S, - }, - { - x1: RegV25, - x2: RegV30, - name: "fabs v30.2d, v25.2d", - inst: VFABS, - exp: []byte{0x3e, 0xfb, 0xe0, 0x4e}, - arr: VectorArrangement2D, - }, - { - x1: RegV25, - x2: RegV30, - name: "fsqrt v30.4s, v25.4s", - inst: VFSQRT, - exp: []byte{0x3e, 0xfb, 0xa1, 0x6e}, - arr: VectorArrangement4S, - }, - { - x1: RegV25, - x2: RegV30, - name: "fsqrt v30.2s, v25.2s", - inst: VFSQRT, - exp: []byte{0x3e, 0xfb, 0xa1, 0x2e}, - arr: VectorArrangement2S, - }, - { - x1: RegV25, - x2: RegV30, - name: "fsqrt v30.2d, v25.2d", - inst: VFSQRT, - exp: []byte{0x3e, 0xfb, 0xe1, 0x6e}, - arr: VectorArrangement2D, - }, - { - x1: RegV25, - x2: RegV30, - name: "frintm v30.4s, v25.4s", - inst: VFRINTM, - exp: []byte{0x3e, 0x9b, 0x21, 0x4e}, - arr: VectorArrangement4S, - }, - { - x1: RegV25, - x2: RegV30, - name: "frintm v30.2s, v25.2s", - inst: VFRINTM, - exp: []byte{0x3e, 0x9b, 0x21, 0xe}, - arr: VectorArrangement2S, - }, - { - x1: RegV25, - x2: RegV30, - name: "frintm v30.2d, v25.2d", - inst: VFRINTM, - exp: []byte{0x3e, 0x9b, 0x61, 0x4e}, - arr: VectorArrangement2D, - }, - { - x1: RegV25, - x2: RegV30, - name: "frintn v30.4s, v25.4s", - inst: VFRINTN, - exp: []byte{0x3e, 0x8b, 0x21, 0x4e}, - arr: VectorArrangement4S, - }, - { - x1: RegV25, - x2: RegV30, - name: "frintn v30.2s, v25.2s", - inst: VFRINTN, - exp: []byte{0x3e, 0x8b, 0x21, 0xe}, - arr: VectorArrangement2S, - }, - { - x1: RegV25, - x2: RegV30, - name: "frintn v30.2d, v25.2d", - inst: VFRINTN, - exp: []byte{0x3e, 0x8b, 0x61, 0x4e}, - arr: VectorArrangement2D, - }, - { - x1: RegV25, - x2: RegV30, - name: "frintp v30.4s, v25.4s", - inst: VFRINTP, - exp: []byte{0x3e, 0x8b, 0xa1, 0x4e}, - arr: VectorArrangement4S, - }, - { - x1: RegV25, - x2: RegV30, - name: "frintp v30.2s, v25.2s", - inst: VFRINTP, - exp: []byte{0x3e, 0x8b, 0xa1, 0xe}, - arr: VectorArrangement2S, - }, - { - x1: RegV25, - x2: RegV30, - name: "frintp v30.2d, v25.2d", - inst: VFRINTP, - exp: []byte{0x3e, 0x8b, 0xe1, 0x4e}, - arr: VectorArrangement2D, - }, - { - x1: RegV25, - x2: RegV30, - name: "frintp v30.4s, v25.4s", - inst: VFRINTN, - exp: []byte{0x3e, 0x8b, 0x21, 0x4e}, - arr: VectorArrangement4S, - }, - { - x1: RegV25, - x2: RegV30, - name: "frintp v30.2s, v25.2s", - inst: VFRINTN, - exp: []byte{0x3e, 0x8b, 0x21, 0xe}, - arr: VectorArrangement2S, - }, - { - x1: RegV25, - x2: RegV30, - name: "frintp v30.2d, v25.2d", - inst: VFRINTN, - exp: []byte{0x3e, 0x8b, 0x61, 0x4e}, - arr: VectorArrangement2D, - }, - { - x1: RegV25, - x2: RegV30, - name: "shll v30.8h, v25.8b, #8", - inst: SHLL, - exp: []byte{0x3e, 0x3b, 0x21, 0x2e}, - arr: VectorArrangement8B, - }, - { - x1: RegV25, - x2: RegV30, - name: "shll v30.4s, v25.4h, #16", - inst: SHLL, - exp: []byte{0x3e, 0x3b, 0x61, 0x2e}, - arr: VectorArrangement4H, - }, - { - x1: RegV25, - x2: RegV30, - name: "shll v30.2d, v25.2s, #32", - inst: SHLL, - exp: []byte{0x3e, 0x3b, 0xa1, 0x2e}, - arr: VectorArrangement2S, - }, - { - x1: RegV25, - x2: RegV30, - name: "uaddlv h30, v25.16b", - inst: UADDLV, - exp: []byte{0x3e, 0x3b, 0x30, 0x6e}, - arr: VectorArrangement16B, - }, - { - x1: RegV25, - x2: RegV30, - name: "uaddlv s30, v25.8h", - inst: UADDLV, - exp: []byte{0x3e, 0x3b, 0x70, 0x6e}, - arr: VectorArrangement8H, - }, - { - x1: RegV25, - x2: RegV30, - name: "uaddlv d30, v25.4s", - inst: UADDLV, - exp: []byte{0x3e, 0x3b, 0xb0, 0x6e}, - arr: VectorArrangement4S, - }, - { - x1: RegV25, - x2: RegV30, - name: "saddlp v30.2d, v25.4s", - inst: SADDLP, - exp: []byte{0x3e, 0x2b, 0xa0, 0x4e}, - arr: VectorArrangement4S, - }, - { - x1: RegV25, - x2: RegV30, - name: "saddlp v30.4s, v25.8h", - inst: SADDLP, - exp: []byte{0x3e, 0x2b, 0x60, 0x4e}, - arr: VectorArrangement8H, - }, - { - x1: RegV25, - x2: RegV30, - name: "uaddlp v30.2d, v25.4s", - inst: UADDLP, - exp: []byte{0x3e, 0x2b, 0xa0, 0x6e}, - arr: VectorArrangement4S, - }, - { - x1: RegV25, - x2: RegV30, - name: "uaddlp v30.4s, v25.8h", - inst: UADDLP, - exp: []byte{0x3e, 0x2b, 0x60, 0x6e}, - arr: VectorArrangement8H, - }, - { - name: "sshll2 v10.8h, v2.16b, #7", - x1: RegV2, - x2: RegV10, - inst: SSHLL2, - exp: []byte{0x4a, 0xa4, 0xf, 0x4f}, - arr: VectorArrangement16B, - c: 7, - }, - { - name: "sshll2 v10.4s, v2.8h, #0", - x1: RegV2, - x2: RegV10, - inst: SSHLL2, - exp: []byte{0x4a, 0xa4, 0x10, 0x4f}, - arr: VectorArrangement8H, - }, - { - name: "sshll2 v10.2d, v2.4s, #0x15", - x1: RegV2, - x2: RegV10, - inst: SSHLL2, - exp: []byte{0x4a, 0xa4, 0x35, 0x4f}, - arr: VectorArrangement4S, - c: 21, - }, - { - name: "ushll2 v10.8h, v2.16b, #7", - x1: RegV2, - x2: RegV10, - inst: USHLL2, - exp: []byte{0x4a, 0xa4, 0xf, 0x6f}, - arr: VectorArrangement16B, - c: 7, - }, - { - name: "ushll2 v10.4s, v2.8h, #0", - x1: RegV2, - x2: RegV10, - inst: USHLL2, - exp: []byte{0x4a, 0xa4, 0x10, 0x6f}, - arr: VectorArrangement8H, - }, - { - name: "ushll2 v10.2d, v2.4s, #0x15", - x1: RegV2, - x2: RegV10, - inst: USHLL2, - exp: []byte{0x4a, 0xa4, 0x35, 0x6f}, - arr: VectorArrangement4S, - c: 21, - }, - { - x1: RegV25, - x2: RegV30, - name: "fcvtzs v30.4s, v25.4s", - inst: VFCVTZS, - exp: []byte{0x3e, 0xbb, 0xa1, 0x4e}, - arr: VectorArrangement4S, - }, - { - x1: RegV25, - x2: RegV30, - name: "fcvtzs v30.2s, v25.2s", - inst: VFCVTZS, - exp: []byte{0x3e, 0xbb, 0xa1, 0xe}, - arr: VectorArrangement2S, - }, - { - x1: RegV25, - x2: RegV30, - name: "fcvtzs v30.2d, v25.2d", - inst: VFCVTZS, - exp: []byte{0x3e, 0xbb, 0xe1, 0x4e}, - arr: VectorArrangement2D, - }, - { - x1: RegV25, - x2: RegV30, - name: "fcvtzu v30.4s, v25.4s", - inst: VFCVTZU, - exp: []byte{0x3e, 0xbb, 0xa1, 0x6e}, - arr: VectorArrangement4S, - }, - { - x1: RegV25, - x2: RegV30, - name: "fcvtzu v30.2s, v25.2s", - inst: VFCVTZU, - exp: []byte{0x3e, 0xbb, 0xa1, 0x2e}, - arr: VectorArrangement2S, - }, - { - x1: RegV25, - x2: RegV30, - name: "fcvtzu v30.2d, v25.2d", - inst: VFCVTZU, - exp: []byte{0x3e, 0xbb, 0xe1, 0x6e}, - arr: VectorArrangement2D, - }, - { - x1: RegV25, - x2: RegV30, - name: "sqxtn v30.2s, v25.2d", - inst: SQXTN, - exp: []byte{0x3e, 0x4b, 0xa1, 0xe}, - arr: VectorArrangement2S, - }, - { - x1: RegV25, - x2: RegV30, - name: "sqxtn v30.4h, v25.4s", - inst: SQXTN, - exp: []byte{0x3e, 0x4b, 0x61, 0xe}, - arr: VectorArrangement4H, - }, - { - x1: RegV25, - x2: RegV30, - name: "uqxtn v30.2s, v25.2d", - inst: UQXTN, - exp: []byte{0x3e, 0x4b, 0xa1, 0x2e}, - arr: VectorArrangement2S, - }, - { - x1: RegV25, - x2: RegV30, - name: "uqxtn v30.4h, v25.4s", - inst: UQXTN, - exp: []byte{0x3e, 0x4b, 0x61, 0x2e}, - arr: VectorArrangement4H, - }, - { - x1: RegV25, - x2: RegV30, - name: "sqxtn2 v30.16b, v25.8h", - inst: SQXTN2, - exp: []byte{0x3e, 0x4b, 0x21, 0x4e}, - arr: VectorArrangement16B, - }, - { - x1: RegV25, - x2: RegV30, - name: "sqxtn2 v30.8h, v25.4s", - inst: SQXTN2, - exp: []byte{0x3e, 0x4b, 0x61, 0x4e}, - arr: VectorArrangement8H, - }, - { - x1: RegV25, - x2: RegV30, - name: "sqxtn2 v30.4s, v25.2d", - inst: SQXTN2, - exp: []byte{0x3e, 0x4b, 0xa1, 0x4e}, - arr: VectorArrangement4S, - }, - { - x1: RegV25, - x2: RegV30, - name: "sqxtun v30.8b, v25.8h", - inst: SQXTUN, - exp: []byte{0x3e, 0x2b, 0x21, 0x2e}, - arr: VectorArrangement8B, - }, - { - x1: RegV25, - x2: RegV30, - name: "sqxtun v30.4h, v25.4s", - inst: SQXTUN, - exp: []byte{0x3e, 0x2b, 0x61, 0x2e}, - arr: VectorArrangement4H, - }, - { - x1: RegV25, - x2: RegV30, - name: "sqxtun v30.2s, v25.2d", - inst: SQXTUN, - exp: []byte{0x3e, 0x2b, 0xa1, 0x2e}, - arr: VectorArrangement2S, - }, - { - x1: RegV25, - x2: RegV30, - name: "sqxtun2 v30.16b, v25.8h", - inst: SQXTUN2, - exp: []byte{0x3e, 0x2b, 0x21, 0x6e}, - arr: VectorArrangement16B, - }, - { - x1: RegV25, - x2: RegV30, - name: "sqxtun2 v30.8h, v25.4s", - inst: SQXTUN2, - exp: []byte{0x3e, 0x2b, 0x61, 0x6e}, - arr: VectorArrangement8H, - }, - { - x1: RegV25, - x2: RegV30, - name: "sqxtun2 v30.4s, v25.2d", - inst: SQXTUN2, - exp: []byte{0x3e, 0x2b, 0xa1, 0x6e}, - arr: VectorArrangement4S, - }, - { - x1: RegV25, - x2: RegV30, - name: "scvtf v30.2d, v25.2d", - inst: VSCVTF, - exp: []byte{0x3e, 0xdb, 0x61, 0x4e}, - arr: VectorArrangement2D, - }, - { - x1: RegV25, - x2: RegV30, - name: "scvtf v30.4s, v25.4s", - inst: VSCVTF, - exp: []byte{0x3e, 0xdb, 0x21, 0x4e}, - arr: VectorArrangement4S, - }, - { - x1: RegV25, - x2: RegV30, - name: "ucvtf v30.2d, v25.2d", - inst: VUCVTF, - exp: []byte{0x3e, 0xdb, 0x61, 0x6e}, - arr: VectorArrangement2D, - }, - { - x1: RegV25, - x2: RegV30, - name: "ucvtf v30.4s, v25.4s", - inst: VUCVTF, - exp: []byte{0x3e, 0xdb, 0x21, 0x6e}, - arr: VectorArrangement4S, - }, - { - x1: RegV25, - x2: RegV30, - name: "fcvtl v30.2d, v25.2s", - inst: FCVTL, - exp: []byte{0x3e, 0x7b, 0x61, 0xe}, - arr: VectorArrangement2S, - }, - { - x1: RegV25, - x2: RegV30, - name: "fcvtl v30.4s, v25.4h", - inst: FCVTL, - exp: []byte{0x3e, 0x7b, 0x21, 0xe}, - arr: VectorArrangement4H, - }, - { - x1: RegV25, - x2: RegV30, - name: "fcvtn v30.2s, v25.2d", - inst: FCVTN, - exp: []byte{0x3e, 0x6b, 0x61, 0xe}, - arr: VectorArrangement2S, - }, - { - x1: RegV25, - x2: RegV30, - name: "fcvtn v30.4h, v25.4s", - inst: FCVTN, - exp: []byte{0x3e, 0x6b, 0x21, 0xe}, - arr: VectorArrangement4H, - }, - } - - for _, tt := range tests { - tc := tt - t.Run(tc.name, func(t *testing.T) { - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - a := NewAssembler(asm.NilRegister) - buf := code.NextCodeSection() - err := a.encodeVectorRegisterToVectorRegister(buf, &nodeImpl{ - instruction: tc.inst, - srcReg: tc.x1, - srcConst: tc.c, - dstReg: tc.x2, - vectorArrangement: tc.arr, - srcVectorIndex: tc.srcIndex, - dstVectorIndex: tc.dstIndex, - }) - require.NoError(t, err) - actual := buf.Bytes() - require.Equal(t, tc.exp, actual, hex.EncodeToString(actual)) - }) - } -} - -func TestAssemblerImpl_EncodeVectorRegisterToRegister(t *testing.T) { - tests := []struct { - name string - n *nodeImpl - exp []byte - }{ - { - name: "umov w10, v0.b[0xf]", - n: &nodeImpl{ - instruction: UMOV, - srcReg: RegV0, - dstReg: RegR10, - vectorArrangement: VectorArrangementB, - srcVectorIndex: 15, - }, - exp: []byte{0xa, 0x3c, 0x1f, 0xe}, - }, - { - name: "mov w10, v0.s[3]", - n: &nodeImpl{ - instruction: UMOV, - srcReg: RegV0, - dstReg: RegR10, - vectorArrangement: VectorArrangementS, - srcVectorIndex: 3, - }, - exp: []byte{0xa, 0x3c, 0x1c, 0xe}, - }, - { - name: "mov x5, v30.d[1]", - n: &nodeImpl{ - instruction: UMOV, - srcReg: RegV30, - dstReg: RegR5, - vectorArrangement: VectorArrangementD, - srcVectorIndex: 1, - }, - exp: []byte{0xc5, 0x3f, 0x18, 0x4e}, - }, - { - name: "smov w10, v0.b[0xf]", - n: &nodeImpl{ - instruction: SMOV32, - srcReg: RegV0, - dstReg: RegR10, - vectorArrangement: VectorArrangementB, - srcVectorIndex: 15, - }, - exp: []byte{0xa, 0x2c, 0x1f, 0xe}, - }, - { - name: "smov w10, v0.b[0]", - n: &nodeImpl{ - instruction: SMOV32, - srcReg: RegV0, - dstReg: RegR10, - vectorArrangement: VectorArrangementB, - srcVectorIndex: 0, - }, - exp: []byte{0xa, 0x2c, 0x1, 0xe}, - }, - { - name: "smov w1, v30.h[7]", - n: &nodeImpl{ - instruction: SMOV32, - srcReg: RegV30, - dstReg: RegR1, - vectorArrangement: VectorArrangementH, - srcVectorIndex: 7, - }, - exp: []byte{0xc1, 0x2f, 0x1e, 0xe}, - }, - { - name: "smov w1, v30.h[0]", - n: &nodeImpl{ - instruction: SMOV32, - srcReg: RegV30, - dstReg: RegR1, - vectorArrangement: VectorArrangementH, - srcVectorIndex: 0, - }, - exp: []byte{0xc1, 0x2f, 0x2, 0xe}, - }, - } - - for _, tt := range tests { - tc := tt - t.Run(tc.name, func(t *testing.T) { - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - a := NewAssembler(asm.NilRegister) - buf := code.NextCodeSection() - err := a.encodeVectorRegisterToRegister(buf, tc.n) - require.NoError(t, err) - - actual := buf.Bytes() - require.Equal(t, tc.exp, actual, hex.EncodeToString(actual)) - }) - } -} - -func TestAssemblerImpl_EncodeLeftShiftedRegisterToRegister(t *testing.T) { - t.Run("error", func(t *testing.T) { - tests := []struct { - n *nodeImpl - expErr string - }{ - { - n: &nodeImpl{ - instruction: SUB, types: operandTypesLeftShiftedRegisterToRegister, - srcReg: RegR0, srcReg2: RegR0, dstReg: RegR0, - }, - expErr: "SUB is unsupported for LeftShiftedRegisterToRegister type", - }, - { - n: &nodeImpl{ - instruction: ADD, - srcConst: -1, srcReg: RegR0, srcReg2: RegR0, dstReg: RegR0, - }, - expErr: "shift amount must fit in unsigned 6-bit integer (0-64) but got -1", - }, - { - n: &nodeImpl{ - instruction: ADD, - srcConst: -1, srcReg: RegV0, srcReg2: RegR0, dstReg: RegR0, - }, - expErr: "V0 is not integer", - }, - { - n: &nodeImpl{ - instruction: ADD, - srcConst: -1, srcReg: RegR0, srcReg2: RegV0, dstReg: RegR0, - }, - expErr: "V0 is not integer", - }, - { - n: &nodeImpl{ - instruction: ADD, - srcConst: -1, srcReg: RegR0, srcReg2: RegR0, dstReg: RegV0, - }, - expErr: "V0 is not integer", - }, - } - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - for _, tt := range tests { - tc := tt - a := NewAssembler(asm.NilRegister) - buf := code.NextCodeSection() - err := a.encodeLeftShiftedRegisterToRegister(buf, tc.n) - require.EqualError(t, err, tc.expErr) - } - }) - - tests := []struct { - name string - n *nodeImpl - exp []byte - }{ - { - name: "ADD", - n: &nodeImpl{ - instruction: ADD, - srcReg: RegR0, - srcReg2: RegR29, - srcConst: 1, - dstReg: RegR21, - vectorArrangement: VectorArrangementH, - srcVectorIndex: 0, - }, - exp: []byte{0x15, 0x4, 0x1d, 0x8b}, - }, - { - name: "ADD", - n: &nodeImpl{ - instruction: ADD, - srcReg: RegR0, - srcReg2: RegR29, - srcConst: 2, - dstReg: RegR21, - vectorArrangement: VectorArrangementH, - srcVectorIndex: 0, - }, - exp: []byte{0x15, 0x8, 0x1d, 0x8b}, - }, - { - name: "ADD", - n: &nodeImpl{ - instruction: ADD, - srcReg: RegR0, - srcReg2: RegR29, - srcConst: 8, - dstReg: RegR21, - vectorArrangement: VectorArrangementH, - srcVectorIndex: 0, - }, - exp: []byte{0x15, 0x20, 0x1d, 0x8b}, - }, - { - name: "ADD", - n: &nodeImpl{ - instruction: ADD, - srcReg: RegR29, - srcReg2: RegR0, - srcConst: 16, - dstReg: RegR21, - vectorArrangement: VectorArrangementH, - srcVectorIndex: 0, - }, - exp: []byte{0xb5, 0x43, 0x0, 0x8b}, - }, - { - name: "ADD", - n: &nodeImpl{ - instruction: ADD, - srcReg: RegR29, - srcReg2: RegR0, - srcConst: 64, - dstReg: RegR21, - vectorArrangement: VectorArrangementH, - srcVectorIndex: 0, - }, - exp: []byte{0xb5, 0x3, 0x0, 0x8b}, - }, - { - name: "ADD", - n: &nodeImpl{ - instruction: ADD, - srcReg: RegRZR, - srcReg2: RegR0, - srcConst: 64, - dstReg: RegR21, - vectorArrangement: VectorArrangementH, - srcVectorIndex: 0, - }, - exp: []byte{0xf5, 0x3, 0x0, 0x8b}, - }, - { - name: "ADD", - n: &nodeImpl{ - instruction: ADD, - srcReg: RegRZR, - srcReg2: RegRZR, - srcConst: 64, - dstReg: RegR21, - vectorArrangement: VectorArrangementH, - srcVectorIndex: 0, - }, - exp: []byte{0xf5, 0x3, 0x1f, 0x8b}, - }, - { - name: "ADD", - n: &nodeImpl{ - instruction: ADD, - srcReg: RegRZR, - srcReg2: RegRZR, - srcConst: 64, - dstReg: RegRZR, - vectorArrangement: VectorArrangementH, - srcVectorIndex: 0, - }, - exp: []byte{0xff, 0x3, 0x1f, 0x8b}, - }, - } - - for _, tt := range tests { - tc := tt - t.Run(tc.name, func(t *testing.T) { - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - a := NewAssembler(asm.NilRegister) - buf := code.NextCodeSection() - err := a.encodeLeftShiftedRegisterToRegister(buf, tc.n) - require.NoError(t, err) - - actual := buf.Bytes() - require.Equal(t, tc.exp, actual, hex.EncodeToString(actual)) - }) - } -} - -func TestAssemblerImpl_encodeTwoRegistersToNone(t *testing.T) { - t.Run("error", func(t *testing.T) { - tests := []struct { - n *nodeImpl - expErr string - }{ - { - n: &nodeImpl{ - instruction: SUB, types: operandTypesTwoRegistersToNone, - srcReg: RegR0, srcReg2: RegR0, dstReg: RegR0, - }, - expErr: "SUB is unsupported for TwoRegistersToNone type", - }, - { - n: &nodeImpl{ - instruction: CMP, - srcReg: RegR0, srcReg2: RegV0, - }, - expErr: "V0 is not integer", - }, - { - n: &nodeImpl{ - instruction: FCMPS, - srcReg: RegR0, srcReg2: RegV0, - }, - expErr: "R0 is not vector", - }, - } - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - for _, tt := range tests { - tc := tt - a := NewAssembler(asm.NilRegister) - buf := code.NextCodeSection() - err := a.encodeTwoRegistersToNone(buf, tc.n) - require.EqualError(t, err, tc.expErr) - } - }) - - tests := []struct { - name string - n *nodeImpl - exp []byte - }{ - { - name: "CMP", - n: &nodeImpl{ - instruction: CMP, - srcReg: RegRZR, - srcReg2: RegRZR, - vectorArrangement: VectorArrangementH, - srcVectorIndex: 0, - }, - exp: []byte{0xff, 0x3, 0x1f, 0xeb}, - }, - { - name: "CMP", - n: &nodeImpl{ - instruction: CMP, - srcReg: RegRZR, - srcReg2: RegR30, - vectorArrangement: VectorArrangementH, - srcVectorIndex: 0, - }, - exp: []byte{0xdf, 0x3, 0x1f, 0xeb}, - }, - { - name: "CMP", - n: &nodeImpl{ - instruction: CMP, - srcReg: RegR30, - srcReg2: RegRZR, - vectorArrangement: VectorArrangementH, - srcVectorIndex: 0, - }, - exp: []byte{0xff, 0x3, 0x1e, 0xeb}, - }, - { - name: "CMP", - n: &nodeImpl{ - instruction: CMP, - srcReg: RegR30, - srcReg2: RegR30, - vectorArrangement: VectorArrangementH, - srcVectorIndex: 0, - }, - exp: []byte{0xdf, 0x3, 0x1e, 0xeb}, - }, - { - name: "CMPW", - n: &nodeImpl{ - instruction: CMPW, - srcReg: RegRZR, - srcReg2: RegRZR, - vectorArrangement: VectorArrangementH, - srcVectorIndex: 0, - }, - exp: []byte{0xff, 0x3, 0x1f, 0x6b}, - }, - { - name: "CMPW", - n: &nodeImpl{ - instruction: CMPW, - srcReg: RegRZR, - srcReg2: RegR30, - vectorArrangement: VectorArrangementH, - srcVectorIndex: 0, - }, - exp: []byte{0xdf, 0x3, 0x1f, 0x6b}, - }, - { - name: "CMPW", - n: &nodeImpl{ - instruction: CMPW, - srcReg: RegR30, - srcReg2: RegRZR, - vectorArrangement: VectorArrangementH, - srcVectorIndex: 0, - }, - exp: []byte{0xff, 0x3, 0x1e, 0x6b}, - }, - { - name: "CMPW", - n: &nodeImpl{ - instruction: CMPW, - srcReg: RegR30, - srcReg2: RegR30, - vectorArrangement: VectorArrangementH, - srcVectorIndex: 0, - }, - exp: []byte{0xdf, 0x3, 0x1e, 0x6b}, - }, - { - name: "FCMPD", - n: &nodeImpl{ - instruction: FCMPD, - srcReg: RegV0, - srcReg2: RegV0, - vectorArrangement: VectorArrangementH, - srcVectorIndex: 0, - }, - exp: []byte{0x0, 0x20, 0x60, 0x1e}, - }, - { - name: "FCMPD", - n: &nodeImpl{ - instruction: FCMPD, - srcReg: RegV0, - srcReg2: RegV31, - vectorArrangement: VectorArrangementH, - srcVectorIndex: 0, - }, - exp: []byte{0xe0, 0x23, 0x60, 0x1e}, - }, - { - name: "FCMPD", - n: &nodeImpl{ - instruction: FCMPD, - srcReg: RegV31, - srcReg2: RegV0, - vectorArrangement: VectorArrangementH, - srcVectorIndex: 0, - }, - exp: []byte{0x0, 0x20, 0x7f, 0x1e}, - }, - { - name: "FCMPD", - n: &nodeImpl{ - instruction: FCMPD, - srcReg: RegV31, - srcReg2: RegV31, - vectorArrangement: VectorArrangementH, - srcVectorIndex: 0, - }, - exp: []byte{0xe0, 0x23, 0x7f, 0x1e}, - }, - { - name: "FCMPS", - n: &nodeImpl{ - instruction: FCMPS, - srcReg: RegV0, - srcReg2: RegV0, - vectorArrangement: VectorArrangementH, - srcVectorIndex: 0, - }, - exp: []byte{0x0, 0x20, 0x20, 0x1e}, - }, - { - name: "FCMPS", - n: &nodeImpl{ - instruction: FCMPS, - srcReg: RegV0, - srcReg2: RegV31, - vectorArrangement: VectorArrangementH, - srcVectorIndex: 0, - }, - exp: []byte{0xe0, 0x23, 0x20, 0x1e}, - }, - { - name: "FCMPS", - n: &nodeImpl{ - instruction: FCMPS, - srcReg: RegV31, - srcReg2: RegV0, - vectorArrangement: VectorArrangementH, - srcVectorIndex: 0, - }, - exp: []byte{0x0, 0x20, 0x3f, 0x1e}, - }, - { - name: "FCMPS", - n: &nodeImpl{ - instruction: FCMPS, - srcReg: RegV31, - srcReg2: RegV31, - vectorArrangement: VectorArrangementH, - srcVectorIndex: 0, - }, - exp: []byte{0xe0, 0x23, 0x3f, 0x1e}, - }, - } - - for _, tt := range tests { - tc := tt - t.Run(tc.name, func(t *testing.T) { - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - a := NewAssembler(asm.NilRegister) - buf := code.NextCodeSection() - err := a.encodeTwoRegistersToNone(buf, tc.n) - require.NoError(t, err) - - actual := buf.Bytes() - require.Equal(t, tc.exp, actual, hex.EncodeToString(actual)) - }) - } -} - -func TestAssemblerImpl_EncodeThreeRegistersToRegister(t *testing.T) { - const src1, src2, src3, dst = RegR1, RegR10, RegR30, RegR11 - - tests := []struct { - name string - exp []byte - inst asm.Instruction - }{ - { - name: "MSUB/src1=R1,src2=R10,src3=R30,dst=R11", - inst: MSUB, - exp: []byte{0xcb, 0xab, 0x1, 0x9b}, - }, - { - name: "MSUBW/src1=R1,src2=R10,src3=R30,dst=R11", - inst: MSUBW, - exp: []byte{0xcb, 0xab, 0x1, 0x1b}, - }, - } - - for _, tc := range tests { - t.Run(tc.name, func(t *testing.T) { - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - a := NewAssembler(asm.NilRegister) - buf := code.NextCodeSection() - err := a.encodeThreeRegistersToRegister(buf, &nodeImpl{ - instruction: tc.inst, srcReg: src1, srcReg2: src2, dstReg: src3, dstReg2: dst, - }) - require.NoError(t, err) - - actual := buf.Bytes() - require.Equal(t, tc.exp, actual[:4]) - }) - } -} - -func TestAssemblerImpl_encodeTwoVectorRegistersToVectorRegister(t *testing.T) { - tests := []struct { - name string - n *nodeImpl - exp []byte - }{ - { - name: "orr v30.16b, v10.16b, v1.16b", - n: &nodeImpl{ - instruction: VORR, - dstReg: RegV30, - srcReg: RegV1, - srcReg2: RegV10, - vectorArrangement: VectorArrangement16B, - }, - exp: []byte{0x5e, 0x1d, 0xa1, 0x4e}, - }, - { - name: "orr v30.8b, v10.8b, v1.8b", - n: &nodeImpl{ - instruction: VORR, - dstReg: RegV30, - srcReg: RegV1, - srcReg2: RegV10, - vectorArrangement: VectorArrangement8B, - }, - exp: []byte{0x5e, 0x1d, 0xa1, 0xe}, - }, - { - name: "bsl v0.8b, v15.8b, v1.8b", - n: &nodeImpl{ - instruction: BSL, - dstReg: RegV0, - srcReg: RegV1, - srcReg2: RegV15, - vectorArrangement: VectorArrangement8B, - }, - exp: []byte{0xe0, 0x1d, 0x61, 0x2e}, - }, - { - name: "zip1 v0.4s, v15.4s, v1.4s", - n: &nodeImpl{ - instruction: ZIP1, - dstReg: RegV0, - srcReg: RegV1, - srcReg2: RegV15, - vectorArrangement: VectorArrangement4S, - }, - exp: []byte{0xe0, 0x39, 0x81, 0x4e}, - }, - { - name: "zip1 v0.2d, v15.2d, v1.2d", - n: &nodeImpl{ - instruction: ZIP1, - dstReg: RegV0, - srcReg: RegV1, - srcReg2: RegV15, - vectorArrangement: VectorArrangement2D, - }, - exp: []byte{0xe0, 0x39, 0xc1, 0x4e}, - }, - { - name: "ext v0.16b, v15.16b, v1.16b, #0xf", - n: &nodeImpl{ - instruction: EXT, - dstReg: RegV0, - srcReg: RegV1, - srcReg2: RegV15, - srcConst: 0xf, - vectorArrangement: VectorArrangement16B, - }, - exp: []byte{0xe0, 0x79, 0x1, 0x6e}, - }, - { - name: "ext v0.16b, v15.16b, v1.16b, #8", - n: &nodeImpl{ - instruction: EXT, - dstReg: RegV0, - srcReg: RegV1, - srcReg2: RegV15, - srcConst: 8, - vectorArrangement: VectorArrangement16B, - }, - exp: []byte{0xe0, 0x41, 0x1, 0x6e}, - }, - { - name: "ext v0.16b, v15.16b, v1.16b, #0", - n: &nodeImpl{ - instruction: EXT, - dstReg: RegV0, - srcReg: RegV1, - srcReg2: RegV15, - srcConst: 0, - vectorArrangement: VectorArrangement16B, - }, - exp: []byte{0xe0, 0x1, 0x1, 0x6e}, - }, - { - name: "ext v0.8b, v15.8b, v1.8b, #7", - n: &nodeImpl{ - instruction: EXT, - dstReg: RegV0, - srcReg: RegV1, - srcReg2: RegV15, - srcConst: 7, - vectorArrangement: VectorArrangement8B, - }, - exp: []byte{0xe0, 0x39, 0x1, 0x2e}, - }, - { - name: "cmeq v0.8b, v15.8b, v1.8b", - n: &nodeImpl{ - instruction: CMEQ, - dstReg: RegV0, - srcReg: RegV1, - srcReg2: RegV15, - vectorArrangement: VectorArrangement8B, - }, - exp: []byte{0xe0, 0x8d, 0x21, 0x2e}, - }, - { - name: "cmgt v0.16b, v15.16b, v1.16b", - n: &nodeImpl{ - instruction: CMGT, - dstReg: RegV0, - srcReg: RegV1, - srcReg2: RegV15, - vectorArrangement: VectorArrangement16B, - }, - exp: []byte{0xe0, 0x35, 0x21, 0x4e}, - }, - { - name: "cmhi v0.8h, v15.8h, v1.8h", - n: &nodeImpl{ - instruction: CMHI, - dstReg: RegV0, - srcReg: RegV1, - srcReg2: RegV15, - vectorArrangement: VectorArrangement8H, - }, - exp: []byte{0xe0, 0x35, 0x61, 0x6e}, - }, - { - name: "cmhi v0.4h, v15.4h, v1.4h", - n: &nodeImpl{ - instruction: CMHI, - dstReg: RegV0, - srcReg: RegV1, - srcReg2: RegV15, - vectorArrangement: VectorArrangement4H, - }, - exp: []byte{0xe0, 0x35, 0x61, 0x2e}, - }, - { - name: "cmge v0.4s, v15.4s, v1.4s", - n: &nodeImpl{ - instruction: CMGE, - dstReg: RegV0, - srcReg: RegV1, - srcReg2: RegV15, - vectorArrangement: VectorArrangement4S, - }, - exp: []byte{0xe0, 0x3d, 0xa1, 0x4e}, - }, - { - name: "cmge v0.2s, v15.2s, v1.2s", - n: &nodeImpl{ - instruction: CMGE, - dstReg: RegV0, - srcReg: RegV1, - srcReg2: RegV15, - vectorArrangement: VectorArrangement2S, - }, - exp: []byte{0xe0, 0x3d, 0xa1, 0xe}, - }, - { - name: "cmhs v30.2d, v4.2d, v11.2d", - n: &nodeImpl{ - instruction: CMHS, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement2D, - }, - exp: []byte{0x9e, 0x3c, 0xeb, 0x6e}, - }, - { - name: "fcmeq v30.2d, v4.2d, v11.2d", - n: &nodeImpl{ - instruction: FCMEQ, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement2D, - }, - exp: []byte{0x9e, 0xe4, 0x6b, 0x4e}, - }, - { - name: "fcmeq v30.4s, v4.4s, v11.4s", - n: &nodeImpl{ - instruction: FCMEQ, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement4S, - }, - exp: []byte{0x9e, 0xe4, 0x2b, 0x4e}, - }, - { - name: "fcmeq v30.2s, v4.2s, v11.2s", - n: &nodeImpl{ - instruction: FCMEQ, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement2S, - }, - exp: []byte{0x9e, 0xe4, 0x2b, 0xe}, - }, - { - name: "fcmgt v30.2d, v4.2d, v11.2d", - n: &nodeImpl{ - instruction: FCMGT, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement2D, - }, - exp: []byte{0x9e, 0xe4, 0xeb, 0x6e}, - }, - { - name: "fcmgt v30.4s, v4.4s, v11.4s", - n: &nodeImpl{ - instruction: FCMGT, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement4S, - }, - exp: []byte{0x9e, 0xe4, 0xab, 0x6e}, - }, - { - name: "fcmgt v30.2s, v4.2s, v11.2s", - n: &nodeImpl{ - instruction: FCMGT, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement2S, - }, - exp: []byte{0x9e, 0xe4, 0xab, 0x2e}, - }, - { - name: "fcmge v30.2d, v4.2d, v11.2d", - n: &nodeImpl{ - instruction: FCMGE, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement2D, - }, - exp: []byte{0x9e, 0xe4, 0x6b, 0x6e}, - }, - { - name: "fcmge v30.4s, v4.4s, v11.4s", - n: &nodeImpl{ - instruction: FCMGE, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement4S, - }, - exp: []byte{0x9e, 0xe4, 0x2b, 0x6e}, - }, - { - name: "fcmge v30.2s, v4.2s, v11.2s", - n: &nodeImpl{ - instruction: FCMGE, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement2S, - }, - exp: []byte{0x9e, 0xe4, 0x2b, 0x2e}, - }, - { - name: "fdiv v30.4s, v4.4s, v11.4s", - n: &nodeImpl{ - instruction: VFDIV, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement4S, - }, - exp: []byte{0x9e, 0xfc, 0x2b, 0x6e}, - }, - { - name: "fdiv v30.2s, v4.2s, v11.2s", - n: &nodeImpl{ - instruction: VFDIV, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement2S, - }, - exp: []byte{0x9e, 0xfc, 0x2b, 0x2e}, - }, - { - name: "fdiv v30.2d, v4.2d, v11.2d", - n: &nodeImpl{ - instruction: VFDIV, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement2D, - }, - exp: []byte{0x9e, 0xfc, 0x6b, 0x6e}, - }, - { - name: "fmul v30.4s, v4.4s, v11.4s", - n: &nodeImpl{ - instruction: VFMUL, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement4S, - }, - exp: []byte{0x9e, 0xdc, 0x2b, 0x6e}, - }, - { - name: "fmul v30.2s, v4.2s, v11.2s", - n: &nodeImpl{ - instruction: VFMUL, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement2S, - }, - exp: []byte{0x9e, 0xdc, 0x2b, 0x2e}, - }, - { - name: "fmul v30.2d, v4.2d, v11.2d", - n: &nodeImpl{ - instruction: VFMUL, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement2D, - }, - exp: []byte{0x9e, 0xdc, 0x6b, 0x6e}, - }, - { - name: "fmin v30.4s, v4.4s, v11.4s", - n: &nodeImpl{ - instruction: VFMIN, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement4S, - }, - exp: []byte{0x9e, 0xf4, 0xab, 0x4e}, - }, - { - name: "fmin v30.2s, v4.2s, v11.2s", - n: &nodeImpl{ - instruction: VFMIN, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement2S, - }, - exp: []byte{0x9e, 0xf4, 0xab, 0xe}, - }, - { - name: "fmin v30.2d, v4.2d, v11.2d", - n: &nodeImpl{ - instruction: VFMIN, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement2D, - }, - exp: []byte{0x9e, 0xf4, 0xeb, 0x4e}, - }, - { - name: "fmax v30.4s, v4.4s, v11.4s", - n: &nodeImpl{ - instruction: VFMAX, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement4S, - }, - exp: []byte{0x9e, 0xf4, 0x2b, 0x4e}, - }, - { - name: "fmax v30.2s, v4.2s, v11.2s", - n: &nodeImpl{ - instruction: VFMAX, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement2S, - }, - exp: []byte{0x9e, 0xf4, 0x2b, 0xe}, - }, - { - name: "fmax v30.2d, v4.2d, v11.2d", - n: &nodeImpl{ - instruction: VFMAX, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement2D, - }, - exp: []byte{0x9e, 0xf4, 0x6b, 0x4e}, - }, - { - name: "mul v30.4s, v4.4s, v11.4s", - n: &nodeImpl{ - instruction: VMUL, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement4S, - }, - exp: []byte{0x9e, 0x9c, 0xab, 0x4e}, - }, - { - name: "mul v30.16b, v4.16b, v11.16b", - n: &nodeImpl{ - instruction: VMUL, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement16B, - }, - exp: []byte{0x9e, 0x9c, 0x2b, 0x4e}, - }, - { - name: "sqadd v30.2d, v4.2d, v11.2d", - n: &nodeImpl{ - instruction: VSQADD, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement2D, - }, - exp: []byte{0x9e, 0xc, 0xeb, 0x4e}, - }, - { - name: "sqadd v30.8h, v4.8h, v11.8h", - n: &nodeImpl{ - instruction: VSQADD, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement8H, - }, - exp: []byte{0x9e, 0xc, 0x6b, 0x4e}, - }, - { - name: "uqadd v30.4s, v4.4s, v11.4s", - n: &nodeImpl{ - instruction: VUQADD, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement4S, - }, - exp: []byte{0x9e, 0xc, 0xab, 0x6e}, - }, - { - name: "uqadd v30.8h, v4.8h, v11.8h", - n: &nodeImpl{ - instruction: VUQADD, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement8H, - }, - exp: []byte{0x9e, 0xc, 0x6b, 0x6e}, - }, - { - name: "smax v30.4s, v4.4s, v11.4s", - n: &nodeImpl{ - instruction: SMAX, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement4S, - }, - exp: []byte{0x9e, 0x64, 0xab, 0x4e}, - }, - { - name: "smax v30.8h, v4.8h, v11.8h", - n: &nodeImpl{ - instruction: SMAX, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement8H, - }, - exp: []byte{0x9e, 0x64, 0x6b, 0x4e}, - }, - { - name: "smin v30.16b, v4.16b, v11.16b", - n: &nodeImpl{ - instruction: SMIN, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement16B, - }, - exp: []byte{0x9e, 0x6c, 0x2b, 0x4e}, - }, - { - name: "smin v30.4s, v4.4s, v11.4s", - n: &nodeImpl{ - instruction: SMIN, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement4S, - }, - exp: []byte{0x9e, 0x6c, 0xab, 0x4e}, - }, - { - name: "umin v30.16b, v4.16b, v11.16b", - n: &nodeImpl{ - instruction: UMIN, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement16B, - }, - exp: []byte{0x9e, 0x6c, 0x2b, 0x6e}, - }, - { - name: "umin v30.4s, v4.4s, v11.4s", - n: &nodeImpl{ - instruction: UMIN, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement4S, - }, - exp: []byte{0x9e, 0x6c, 0xab, 0x6e}, - }, - { - name: "umax v30.4s, v4.4s, v11.4s", - n: &nodeImpl{ - instruction: UMAX, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement4S, - }, - exp: []byte{0x9e, 0x64, 0xab, 0x6e}, - }, - { - name: "umax v30.8h, v4.8h, v11.8h", - n: &nodeImpl{ - instruction: UMAX, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement8H, - }, - exp: []byte{0x9e, 0x64, 0x6b, 0x6e}, - }, - { - name: "umax v30.8h, v4.8h, v11.8h", - n: &nodeImpl{ - instruction: URHADD, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement8H, - }, - exp: []byte{0x9e, 0x14, 0x6b, 0x6e}, - }, - { - name: "umax v30.16b, v4.16b, v11.16b", - n: &nodeImpl{ - instruction: URHADD, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement16B, - }, - exp: []byte{0x9e, 0x14, 0x2b, 0x6e}, - }, - { - name: "sqsub v30.16b, v4.16b, v11.16b", - n: &nodeImpl{ - instruction: VSQSUB, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement16B, - }, - exp: []byte{0x9e, 0x2c, 0x2b, 0x4e}, - }, - { - name: "sqsub v308hb, v4.8h, v11.8h", - n: &nodeImpl{ - instruction: VSQSUB, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement8H, - }, - exp: []byte{0x9e, 0x2c, 0x6b, 0x4e}, - }, - { - name: "uqsub v30.16b, v4.16b, v11.16b", - n: &nodeImpl{ - instruction: VUQSUB, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement16B, - }, - exp: []byte{0x9e, 0x2c, 0x2b, 0x6e}, - }, - { - name: "uqsub v308hb, v4.8h, v11.8h", - n: &nodeImpl{ - instruction: VUQSUB, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement8H, - }, - exp: []byte{0x9e, 0x2c, 0x6b, 0x6e}, - }, - { - name: "umlal v0.2d, v6.2s, v2.2s", - n: &nodeImpl{ - instruction: VUMLAL, - dstReg: RegV0, - srcReg: RegV2, - srcReg2: RegV6, - vectorArrangement: VectorArrangement2S, - }, - exp: []byte{0xc0, 0x80, 0xa2, 0x2e}, - }, - { - name: "umlal v0.4s, v6.4h, v2.4h", - n: &nodeImpl{ - instruction: VUMLAL, - dstReg: RegV0, - srcReg: RegV2, - srcReg2: RegV6, - vectorArrangement: VectorArrangement4H, - }, - exp: []byte{0xc0, 0x80, 0x62, 0x2e}, - }, - { - name: "umlal v0.8h, v6.8b, v2.8b", - n: &nodeImpl{ - instruction: VUMLAL, - dstReg: RegV0, - srcReg: RegV2, - srcReg2: RegV6, - vectorArrangement: VectorArrangement8B, - }, - exp: []byte{0xc0, 0x80, 0x22, 0x2e}, - }, - { - name: "bit v30.16b, v4.16b, v11.16b", - n: &nodeImpl{ - instruction: VBIT, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement16B, - }, - exp: []byte{0x9e, 0x1c, 0xab, 0x6e}, - }, - { - name: "bit v30.8b, v4.8b, v11.8b", - n: &nodeImpl{ - instruction: VBIT, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement8B, - }, - exp: []byte{0x9e, 0x1c, 0xab, 0x2e}, - }, - { - name: "sqrdmulh v30.8h, v4.8h, v11.8h", - n: &nodeImpl{ - instruction: SQRDMULH, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement8H, - }, - exp: []byte{0x9e, 0xb4, 0x6b, 0x6e}, - }, - { - name: "sqrdmulh v30.4s, v4.4s, v11.4s", - n: &nodeImpl{ - instruction: SQRDMULH, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement4S, - }, - exp: []byte{0x9e, 0xb4, 0xab, 0x6e}, - }, - { - name: "smull v30.8h, v4.8b, v11.8b", - n: &nodeImpl{ - instruction: SMULL, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement8B, - }, - exp: []byte{0x9e, 0xc0, 0x2b, 0xe}, - }, - { - name: "smull v30.4s, v4.4h, v11.4h", - n: &nodeImpl{ - instruction: SMULL, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement4H, - }, - exp: []byte{0x9e, 0xc0, 0x6b, 0xe}, - }, - { - name: "smull v30.2d, v4.2s, v11.2s", - n: &nodeImpl{ - instruction: SMULL, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement2S, - }, - exp: []byte{0x9e, 0xc0, 0xab, 0xe}, - }, - { - name: "smull2 v30.8h, v4.16b, v11.16b", - n: &nodeImpl{ - instruction: SMULL2, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement16B, - }, - exp: []byte{0x9e, 0xc0, 0x2b, 0x4e}, - }, - { - name: "smull2 v30.4s, v4.8h, v11.8h", - n: &nodeImpl{ - instruction: SMULL2, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement8H, - }, - exp: []byte{0x9e, 0xc0, 0x6b, 0x4e}, - }, - { - name: "smull2 v30.2d, v4.4s, v11.4s", - n: &nodeImpl{ - instruction: SMULL2, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement4S, - }, - exp: []byte{0x9e, 0xc0, 0xab, 0x4e}, - }, - - ////////////////////// - - { - name: "umull v30.8h, v4.8b, v11.8b", - n: &nodeImpl{ - instruction: UMULL, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement8B, - }, - exp: []byte{0x9e, 0xc0, 0x2b, 0x2e}, - }, - { - name: "umull v30.4s, v4.4h, v11.4h", - n: &nodeImpl{ - instruction: UMULL, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement4H, - }, - exp: []byte{0x9e, 0xc0, 0x6b, 0x2e}, - }, - { - name: "umull v30.2d, v4.2s, v11.2s", - n: &nodeImpl{ - instruction: UMULL, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement2S, - }, - exp: []byte{0x9e, 0xc0, 0xab, 0x2e}, - }, - { - name: "umull2 v30.8h, v4.16b, v11.16b", - n: &nodeImpl{ - instruction: UMULL2, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement16B, - }, - exp: []byte{0x9e, 0xc0, 0x2b, 0x6e}, - }, - { - name: "umull2 v30.4s, v4.8h, v11.8h", - n: &nodeImpl{ - instruction: UMULL2, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement8H, - }, - exp: []byte{0x9e, 0xc0, 0x6b, 0x6e}, - }, - { - name: "umull2 v30.2d, v4.4s, v11.4s", - n: &nodeImpl{ - instruction: UMULL2, - dstReg: RegV30, - srcReg: RegV11, - srcReg2: RegV4, - vectorArrangement: VectorArrangement4S, - }, - exp: []byte{0x9e, 0xc0, 0xab, 0x6e}, - }, - } - - for _, tt := range tests { - tc := tt - t.Run(tc.name, func(t *testing.T) { - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - a := NewAssembler(asm.NilRegister) - buf := code.NextCodeSection() - err := a.encodeTwoVectorRegistersToVectorRegister(buf, tc.n) - require.NoError(t, err) - - actual := buf.Bytes() - require.Equal(t, tc.exp, actual, hex.EncodeToString(actual)) - }) - } -} - -func TestAssemblerImpl_EncodeRegisterToVectorRegister(t *testing.T) { - tests := []struct { - name string - n *nodeImpl - exp []byte - }{ - { - name: "ins v10.d[0], x10", - n: &nodeImpl{ - instruction: INSGEN, - dstReg: RegV10, - srcReg: RegR10, - vectorArrangement: VectorArrangementD, - }, - exp: []byte{0x4a, 0x1d, 0x8, 0x4e}, - }, - { - name: "ins v10.d[1], x10", - n: &nodeImpl{ - instruction: INSGEN, - dstReg: RegV10, - srcReg: RegR10, - vectorArrangement: VectorArrangementD, - dstVectorIndex: 1, - }, - exp: []byte{0x4a, 0x1d, 0x18, 0x4e}, - }, - { - name: "dup v10.2d, x10", - n: &nodeImpl{ - instruction: DUPGEN, - srcReg: RegR10, - dstReg: RegV10, - vectorArrangement: VectorArrangement2D, - }, - exp: []byte{0x4a, 0xd, 0x8, 0x4e}, - }, - { - name: "dup v1.4s, w30", - n: &nodeImpl{ - instruction: DUPGEN, - srcReg: RegR30, - dstReg: RegV1, - vectorArrangement: VectorArrangement4S, - }, - exp: []byte{0xc1, 0xf, 0x4, 0x4e}, - }, - { - name: "dup v30.8h, w1", - n: &nodeImpl{ - instruction: DUPGEN, - srcReg: RegR1, - dstReg: RegV30, - vectorArrangement: VectorArrangement8H, - }, - exp: []byte{0x3e, 0xc, 0x2, 0x4e}, - }, - { - name: "dup v30.16b, w1", - n: &nodeImpl{ - instruction: DUPGEN, - srcReg: RegR1, - dstReg: RegV30, - vectorArrangement: VectorArrangement16B, - }, - exp: []byte{0x3e, 0xc, 0x1, 0x4e}, - }, - } - - for _, tt := range tests { - tc := tt - t.Run(tc.name, func(t *testing.T) { - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - a := NewAssembler(asm.NilRegister) - buf := code.NextCodeSection() - err := a.encodeRegisterToVectorRegister(buf, tc.n) - require.NoError(t, err) - - actual := buf.Bytes() - require.Equal(t, tc.exp, actual, hex.EncodeToString(actual)) - }) - } -} - -func TestAssemblerImpl_maybeFlushConstPool(t *testing.T) { - tests := []struct { - name string - c []byte - exp []byte - }{ - { - name: "1 byte consts", - c: []byte{1}, - exp: []byte{ - // 0x0: - // b #0x8 - 0x2, 0x0, 0x0, 0x14, - // 0x4: - 0x1, - 0x0, 0x0, 0x0, // padding to be 4-byte aligned. - // 0x8: <- branch dst. - }, - }, - { - name: "2 byte consts", - c: []byte{0xff, 0xfe}, - exp: []byte{ - // 0x0: - // b #0x8 - 0x2, 0x0, 0x0, 0x14, - // 0x4: - 0xff, 0xfe, - 0x0, 0x0, // padding to be 4-byte aligned. - // 0x8: <- branch dst. - }, - }, - { - name: "3 byte consts", - c: []byte{0xff, 0xfe, 0xa}, - exp: []byte{ - // 0x0: - // b #0x8 - 0x2, 0x0, 0x0, 0x14, - // 0x4: - 0xff, 0xfe, 0xa, - 0x0, // padding to be 4-byte aligned. - // 0x8: <- branch dst. - }, - }, - { - name: "4 byte consts", - c: []byte{1, 2, 3, 4}, - exp: []byte{ - // 0x0: - // b #0x8 - 0x2, 0x0, 0x0, 0x14, - // 0x4: - 0x1, 0x2, 0x3, 0x4, - // 0x8: <- branch dst. - }, - }, - { - name: "12 byte consts", - c: []byte{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12}, - exp: []byte{ - // 0x0: - // b #0x10 - 0x4, 0x0, 0x0, 0x14, - // 0x4: - 1, 2, 3, 4, - 5, 6, 7, 8, - 9, 10, 11, 12, - // 0x10: <- branch dst. - }, - }, - { - name: "16 byte consts", - c: []byte{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, - exp: []byte{ - // 0x0: - // b #0x14 - 0x5, 0x0, 0x0, 0x14, - // 0x04: - 0x1, 0x2, 0x3, 0x4, - 0x5, 0x6, 0x7, 0x8, - 0x9, 0xa, 0xb, 0xc, - 0xd, 0xe, 0xf, 0x10, - // 0x14: <- branch dst. - }, - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - a := NewAssembler(asm.NilRegister) - sc := asm.NewStaticConst(tc.c) - a.pool.AddConst(sc, 0) - - var called bool - sc.AddOffsetFinalizedCallback(func(uint64) { - called = true - }) - - a.MaxDisplacementForConstantPool = 0 - buf := code.NextCodeSection() - a.maybeFlushConstPool(buf, false) - require.True(t, called) - - actual := buf.Bytes() - require.Equal(t, tc.exp, actual) - }) - } -} - -func TestAssemblerImpl_EncodeStaticConstToVectorRegister(t *testing.T) { - tests := []struct { - name string - n *nodeImpl - exp []byte - }{ - { - name: "ldr q8, #8", - n: &nodeImpl{ - instruction: VMOV, - dstReg: RegV8, - vectorArrangement: VectorArrangementQ, - staticConst: asm.NewStaticConst([]byte{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}), - }, - exp: []byte{ - // 0x0: ldr q8, #8 - 0x48, 0x0, 0x0, 0x9c, - // Emitted after the end of function. - // 0x4: br #4 (See AssemblerImpl.maybeFlushConstPool) - 0x0, 0x0, 0x0, 0x14, - // 0x8: consts. - 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, - 0x10, - }, - }, - { - name: "ldr d30, #8", - n: &nodeImpl{ - instruction: VMOV, - dstReg: RegV30, - vectorArrangement: VectorArrangementD, - staticConst: asm.NewStaticConst([]byte{1, 2, 3, 4, 5, 6, 7, 8}), - }, - exp: []byte{ - // 0x0: ldr d30, #8 - 0x5e, 0x0, 0x0, 0x5c, - // Emitted after the end of function. - // 0x4: br #4 (See AssemblerImpl.maybeFlushConstPool) - 0x0, 0x0, 0x0, 0x14, - // 0x8: consts. - 0x1, 0x2, 0x3, 0x4, - 0x5, 0x6, 0x7, 0x8, - }, - }, - { - name: "ldr s8, #8", - n: &nodeImpl{ - instruction: VMOV, - dstReg: RegV8, - vectorArrangement: VectorArrangementS, - staticConst: asm.NewStaticConst([]byte{1, 2, 3, 4}), - }, - exp: []byte{ - // 0x0: ldr s8, #8 - 0x48, 0x0, 0x0, 0x1c, - // Emitted after the end of function. - // 0x4: br #4 (See AssemblerImpl.maybeFlushConstPool) - 0x0, 0x0, 0x0, 0x14, - // 0x8: consts. - 0x1, 0x2, 0x3, 0x4, - }, - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - a := NewAssembler(asm.NilRegister) - buf := code.NextCodeSection() - err := a.encodeStaticConstToVectorRegister(buf, tc.n) - require.NoError(t, err) - a.maybeFlushConstPool(buf, true) - - err = a.Assemble(buf) - require.NoError(t, err) - - actual := buf.Bytes() - require.Equal(t, tc.exp, actual, hex.EncodeToString(actual)) - }) - } -} - -func TestAssemblerImpl_encodeADR_staticConst(t *testing.T) { - const beforeADRByteNum uint64 = 2 - - tests := []struct { - name string - expADRInstructionBytes []byte - offsetOfConstInBinary uint64 - reg asm.Register - }{ - { - // #8 = offsetOfConstInBinary - beforeADRByteNum. - name: "adr x12, #8", - reg: RegR12, - offsetOfConstInBinary: 10, - expADRInstructionBytes: []byte{0x4c, 0x0, 0x0, 0x10}, - }, - { - // #0x7fffd = offsetOfConstInBinary - beforeADRByteNum. - name: "adr x12, #0x7fffd", - reg: RegR12, - offsetOfConstInBinary: 0x7ffff, - expADRInstructionBytes: []byte{0xec, 0xff, 0x3f, 0x30}, - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - sc := asm.NewStaticConst([]byte{1, 2, 3, 4}) // Arbitrary data is fine. - - a := NewAssembler(asm.NilRegister) - - buf := code.NextCodeSection() - buf.AppendBytes(make([]byte, beforeADRByteNum)) - - err := a.encodeADR(buf, &nodeImpl{instruction: ADR, dstReg: tc.reg, staticConst: sc}) - require.NoError(t, err) - require.Equal(t, 1, len(a.pool.Consts)) - require.Equal(t, sc, a.pool.Consts[0]) - require.Equal(t, beforeADRByteNum, a.pool.FirstUseOffsetInBinary) - - // Finalize the ADR instruction bytes. - sc.SetOffsetInBinary(tc.offsetOfConstInBinary) - - actual := buf.Bytes()[beforeADRByteNum : beforeADRByteNum+4] - require.Equal(t, tc.expADRInstructionBytes, actual, hex.EncodeToString(actual)) - }) - } -} diff --git a/internal/asm/arm64/impl_2_test.go b/internal/asm/arm64/impl_2_test.go deleted file mode 100644 index 96771503e2..0000000000 --- a/internal/asm/arm64/impl_2_test.go +++ /dev/null @@ -1,1403 +0,0 @@ -package arm64 - -import ( - "encoding/hex" - "testing" - - "github.com/tetratelabs/wazero/internal/asm" - "github.com/tetratelabs/wazero/internal/testing/require" -) - -func TestAssemblerImpl_EncodeConstToRegister(t *testing.T) { - t.Run("error", func(t *testing.T) { - tests := []struct { - n *nodeImpl - expErr string - }{ - { - n: &nodeImpl{ - instruction: ADR, types: operandTypesConstToRegister, - srcReg: RegR0, srcReg2: RegR0, dstReg: RegR0, - }, - expErr: "ADR is unsupported for ConstToRegister type", - }, - { - n: &nodeImpl{instruction: LSR, types: operandTypesConstToRegister, dstReg: RegR0}, - expErr: "LSR with zero constant should be optimized out", - }, - { - n: &nodeImpl{instruction: LSL, types: operandTypesConstToRegister, dstReg: RegR0}, - expErr: "LSL with zero constant should be optimized out", - }, - } - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - for _, tt := range tests { - tc := tt - a := NewAssembler(asm.NilRegister) - buf := code.NextCodeSection() - err := a.encodeConstToRegister(buf, tc.n) - require.EqualError(t, err, tc.expErr) - } - }) - - tests := []struct { - name string - n *nodeImpl - exp []byte - }{ - { - name: "add x29, sp, #0x200", - n: &nodeImpl{ - instruction: ADD, - srcReg: RegSP, - dstReg: RegR29, - srcConst: 512, - }, - exp: []byte{0xfd, 0x3, 0x8, 0x91}, - }, - { - name: "add x29, sp, #0x100, lsl #12", - n: &nodeImpl{ - instruction: ADD, - srcReg: RegSP, - dstReg: RegR29, - srcConst: 0x100000, - }, - exp: []byte{0xfd, 0x3, 0x44, 0x91}, - }, - { - name: "sub x29, sp, #0x200", - n: &nodeImpl{ - instruction: SUB, - srcReg: RegSP, - dstReg: RegR29, - srcConst: 512, - }, - exp: []byte{0xfd, 0x3, 0x8, 0xd1}, - }, - { - name: "sub x29, sp, #0x100, lsl #12", - n: &nodeImpl{ - instruction: SUB, - srcReg: RegSP, - dstReg: RegR29, - srcConst: 0x100000, - }, - exp: []byte{0xfd, 0x3, 0x44, 0xd1}, - }, - { - name: "movz x27, #0x1f54; add sp, sp, x27", - n: &nodeImpl{ - instruction: ADD, - dstReg: RegSP, - srcConst: 8020, - }, - exp: []byte{0x9b, 0xea, 0x83, 0xd2, 0xff, 0x63, 0x3b, 0x8b}, - }, - { - name: "movz x27, #0x1f54; add x28, sp, x27", - n: &nodeImpl{ - instruction: ADD, - srcReg: RegSP, - dstReg: RegR28, - srcConst: 8020, - }, - exp: []byte{0x9b, 0xea, 0x83, 0xd2, 0xfc, 0x63, 0x3b, 0x8b}, - }, - { - name: "movz x27, #0x1f54; sub sp, sp, x27", - n: &nodeImpl{ - instruction: SUB, - dstReg: RegSP, - srcConst: 8020, - }, - exp: []byte{0x9b, 0xea, 0x83, 0xd2, 0xff, 0x63, 0x3b, 0xcb}, - }, - { - name: "movz x27, #0x1f54; sub x28, sp, x27", - n: &nodeImpl{ - instruction: SUB, - srcReg: RegSP, - dstReg: RegR28, - srcConst: 8020, - }, - exp: []byte{0x9b, 0xea, 0x83, 0xd2, 0xfc, 0x63, 0x3b, 0xcb}, - }, - { - name: "add sp, sp, #0x200", - n: &nodeImpl{ - instruction: ADD, - dstReg: RegSP, - srcConst: 512, - }, - exp: []byte{0xff, 0x3, 0x8, 0x91}, - }, - { - name: "sub sp, sp, #0x200", - n: &nodeImpl{ - instruction: SUB, - dstReg: RegSP, - srcConst: 512, - }, - exp: []byte{0xff, 0x3, 0x8, 0xd1}, - }, - { - name: "and w30, w30, #1", - n: &nodeImpl{ - instruction: ANDIMM32, - dstReg: RegR30, - srcConst: 1, - vectorArrangement: VectorArrangement16B, - }, - exp: []byte{0xde, 0x3, 0x0, 0x12}, - }, - { - name: "and w30, w30, #7", - n: &nodeImpl{ - instruction: ANDIMM32, - dstReg: RegR30, - srcConst: 0x7, - vectorArrangement: VectorArrangement16B, - }, - exp: []byte{0xde, 0xb, 0x0, 0x12}, - }, - { - name: "and w30, w30, #0xf", - n: &nodeImpl{ - instruction: ANDIMM32, - dstReg: RegR30, - srcConst: 0xf, - vectorArrangement: VectorArrangement16B, - }, - exp: []byte{0xde, 0xf, 0x0, 0x12}, - }, - { - name: "and w30, w30, #0x1f", - n: &nodeImpl{ - instruction: ANDIMM32, - dstReg: RegR30, - srcConst: 0x1f, - vectorArrangement: VectorArrangement16B, - }, - exp: []byte{0xde, 0x13, 0x0, 0x12}, - }, - { - name: "and w30, w30, #0x3f", - n: &nodeImpl{ - instruction: ANDIMM32, - dstReg: RegR30, - srcConst: 0x3f, - vectorArrangement: VectorArrangement16B, - }, - exp: []byte{0xde, 0x17, 0x0, 0x12}, - }, - { - name: "and x30, x30, #1", - n: &nodeImpl{ - instruction: ANDIMM64, - dstReg: RegR30, - srcConst: 1, - vectorArrangement: VectorArrangement16B, - }, - exp: []byte{0xde, 0x3, 0x40, 0x92}, - }, - { - name: "and x30, x30, #7", - n: &nodeImpl{ - instruction: ANDIMM64, - dstReg: RegR30, - srcConst: 0x7, - vectorArrangement: VectorArrangement16B, - }, - exp: []byte{0xde, 0xb, 0x40, 0x92}, - }, - { - name: "and x30, x30, #0xf", - n: &nodeImpl{ - instruction: ANDIMM64, - dstReg: RegR30, - srcConst: 0xf, - vectorArrangement: VectorArrangement16B, - }, - exp: []byte{0xde, 0xf, 0x40, 0x92}, - }, - { - name: "and x30, x30, #0x1f", - n: &nodeImpl{ - instruction: ANDIMM64, - dstReg: RegR30, - srcConst: 0x1f, - vectorArrangement: VectorArrangement16B, - }, - exp: []byte{0xde, 0x13, 0x40, 0x92}, - }, - { - name: "and x30, x30, #0x3f", - n: &nodeImpl{ - instruction: ANDIMM64, - dstReg: RegR30, - srcConst: 0x3f, - vectorArrangement: VectorArrangement16B, - }, - exp: []byte{0xde, 0x17, 0x40, 0x92}, - }, - {name: "ADD/dst=R30/0x1", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 1}, exp: []byte{0xde, 0x7, 0x0, 0x91}}, - {name: "ADD/dst=R30/0xffffffffffffffff", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -1}, exp: []byte{0x1b, 0x0, 0x80, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xfff", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 4095}, exp: []byte{0xde, 0xff, 0x3f, 0x91}}, - {name: "ADD/dst=R30/0xfffffffffffff001", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -4095}, exp: []byte{0xdb, 0xff, 0x81, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xfff000", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 16773120}, exp: []byte{0xde, 0xff, 0x7f, 0x91}}, - {name: "ADD/dst=R30/0xffffffffff001000", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -16773120}, exp: []byte{0xfb, 0xff, 0x9d, 0x92, 0x1b, 0xe0, 0xbf, 0xf2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x7b000", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 503808}, exp: []byte{0xde, 0xef, 0x41, 0x91}}, - {name: "ADD/dst=R30/0xfffffffffff85000", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -503808}, exp: []byte{0xfb, 0xff, 0x95, 0x92, 0x1b, 0xff, 0xbf, 0xf2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x8001", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 32769}, exp: []byte{0x3b, 0x0, 0x90, 0xd2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xffffffffffff7fff", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -32769}, exp: []byte{0x1b, 0x0, 0x90, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x80010000", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 2147549184}, exp: []byte{0x3b, 0x0, 0xb0, 0xd2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xffffffff7fff0000", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -2147549184}, exp: []byte{0xfb, 0xff, 0x9f, 0x92, 0xfb, 0xff, 0xaf, 0xf2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x800100000000", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 140741783322624}, exp: []byte{0x3b, 0x0, 0xd0, 0xd2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xffff7fff00000000", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -140741783322624}, exp: []byte{0xfb, 0xff, 0xcf, 0xd2, 0xfb, 0xff, 0xff, 0xf2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xffffffffffff", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 281474976710655}, exp: []byte{0xfb, 0xff, 0xff, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xffff000000000001", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -281474976710655}, exp: []byte{0xfb, 0x43, 0x50, 0xb2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xffff0000ffffffff", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -281470681743361}, exp: []byte{0xfb, 0xff, 0xdf, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xffff00000001", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 281470681743361}, exp: []byte{0x3b, 0x0, 0x80, 0xd2, 0xfb, 0xff, 0xdf, 0xf2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xffffffff80000001", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -2147483647}, exp: []byte{0xfb, 0x87, 0x61, 0xb2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x7fffffff", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 2147483647}, exp: []byte{0xfb, 0x7b, 0x40, 0xb2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xffff00000000ffff", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -281474976645121}, exp: []byte{0xfb, 0x7f, 0x50, 0xb2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xffffffff0001", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 281474976645121}, exp: []byte{0xdb, 0xff, 0x9f, 0x92, 0x1b, 0x0, 0xe0, 0xf2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x100001", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 1048577}, exp: []byte{0xde, 0x7, 0x0, 0x91, 0xde, 0x3, 0x44, 0x91}}, - {name: "ADD/dst=R30/0xffffffffffefffff", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -1048577}, exp: []byte{0x1b, 0x2, 0xa0, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xfffff", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 1048575}, exp: []byte{0xfb, 0x4f, 0x40, 0xb2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xfffffffffff00001", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -1048575}, exp: []byte{0xfb, 0xb3, 0x6c, 0xb2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x800001", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 8388609}, exp: []byte{0xde, 0x7, 0x0, 0x91, 0xde, 0x3, 0x60, 0x91}}, - {name: "ADD/dst=R30/0xffffffffff7fffff", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -8388609}, exp: []byte{0x1b, 0x10, 0xa0, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x40000001", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 1073741825}, exp: []byte{0x3b, 0x0, 0x80, 0xd2, 0x1b, 0x0, 0xa8, 0xf2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xffffffffbfffffff", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -1073741825}, exp: []byte{0x1b, 0x0, 0xa8, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x2", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 2}, exp: []byte{0xde, 0xb, 0x0, 0x91}}, - {name: "ADD/dst=R30/0xfffffffffffffffe", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -2}, exp: []byte{0x3b, 0x0, 0x80, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x3", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 3}, exp: []byte{0xde, 0xf, 0x0, 0x91}}, - {name: "ADD/dst=R30/0xfffffffffffffffd", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -3}, exp: []byte{0x5b, 0x0, 0x80, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x1", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 1}, exp: []byte{0xde, 0x7, 0x0, 0x91}}, - {name: "ADD/dst=R30/0xffffffffffffffff", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -1}, exp: []byte{0x1b, 0x0, 0x80, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x11", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 17}, exp: []byte{0xde, 0x47, 0x0, 0x91}}, - {name: "ADD/dst=R30/0xffffffffffffffef", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -17}, exp: []byte{0x1b, 0x2, 0x80, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x4", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 4}, exp: []byte{0xde, 0x13, 0x0, 0x91}}, - {name: "ADD/dst=R30/0xfffffffffffffffc", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -4}, exp: []byte{0x7b, 0x0, 0x80, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x5", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 5}, exp: []byte{0xde, 0x17, 0x0, 0x91}}, - {name: "ADD/dst=R30/0xfffffffffffffffb", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -5}, exp: []byte{0x9b, 0x0, 0x80, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x3", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 3}, exp: []byte{0xde, 0xf, 0x0, 0x91}}, - {name: "ADD/dst=R30/0xfffffffffffffffd", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -3}, exp: []byte{0x5b, 0x0, 0x80, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x13", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 19}, exp: []byte{0xde, 0x4f, 0x0, 0x91}}, - {name: "ADD/dst=R30/0xffffffffffffffed", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -19}, exp: []byte{0x5b, 0x2, 0x80, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x8", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 8}, exp: []byte{0xde, 0x23, 0x0, 0x91}}, - {name: "ADD/dst=R30/0xfffffffffffffff8", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -8}, exp: []byte{0xfb, 0x0, 0x80, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x9", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 9}, exp: []byte{0xde, 0x27, 0x0, 0x91}}, - {name: "ADD/dst=R30/0xfffffffffffffff7", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -9}, exp: []byte{0x1b, 0x1, 0x80, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x7", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 7}, exp: []byte{0xde, 0x1f, 0x0, 0x91}}, - {name: "ADD/dst=R30/0xfffffffffffffff9", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -7}, exp: []byte{0xdb, 0x0, 0x80, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x17", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 23}, exp: []byte{0xde, 0x5f, 0x0, 0x91}}, - {name: "ADD/dst=R30/0xffffffffffffffe9", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -23}, exp: []byte{0xdb, 0x2, 0x80, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x10", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 16}, exp: []byte{0xde, 0x43, 0x0, 0x91}}, - {name: "ADD/dst=R30/0xfffffffffffffff0", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -16}, exp: []byte{0xfb, 0x1, 0x80, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x11", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 17}, exp: []byte{0xde, 0x47, 0x0, 0x91}}, - {name: "ADD/dst=R30/0xffffffffffffffef", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -17}, exp: []byte{0x1b, 0x2, 0x80, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xf", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 15}, exp: []byte{0xde, 0x3f, 0x0, 0x91}}, - {name: "ADD/dst=R30/0xfffffffffffffff1", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -15}, exp: []byte{0xdb, 0x1, 0x80, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x1f", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 31}, exp: []byte{0xde, 0x7f, 0x0, 0x91}}, - {name: "ADD/dst=R30/0xffffffffffffffe1", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -31}, exp: []byte{0xdb, 0x3, 0x80, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x20", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 32}, exp: []byte{0xde, 0x83, 0x0, 0x91}}, - {name: "ADD/dst=R30/0xffffffffffffffe0", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -32}, exp: []byte{0xfb, 0x3, 0x80, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x21", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 33}, exp: []byte{0xde, 0x87, 0x0, 0x91}}, - {name: "ADD/dst=R30/0xffffffffffffffdf", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -33}, exp: []byte{0x1b, 0x4, 0x80, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x1f", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 31}, exp: []byte{0xde, 0x7f, 0x0, 0x91}}, - {name: "ADD/dst=R30/0xffffffffffffffe1", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -31}, exp: []byte{0xdb, 0x3, 0x80, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x2f", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 47}, exp: []byte{0xde, 0xbf, 0x0, 0x91}}, - {name: "ADD/dst=R30/0xffffffffffffffd1", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -47}, exp: []byte{0xdb, 0x5, 0x80, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x40", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 64}, exp: []byte{0xde, 0x3, 0x1, 0x91}}, - {name: "ADD/dst=R30/0xffffffffffffffc0", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -64}, exp: []byte{0xfb, 0x7, 0x80, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x41", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 65}, exp: []byte{0xde, 0x7, 0x1, 0x91}}, - {name: "ADD/dst=R30/0xffffffffffffffbf", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -65}, exp: []byte{0x1b, 0x8, 0x80, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x3f", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 63}, exp: []byte{0xde, 0xff, 0x0, 0x91}}, - {name: "ADD/dst=R30/0xffffffffffffffc1", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -63}, exp: []byte{0xdb, 0x7, 0x80, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x4f", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 79}, exp: []byte{0xde, 0x3f, 0x1, 0x91}}, - {name: "ADD/dst=R30/0xffffffffffffffb1", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -79}, exp: []byte{0xdb, 0x9, 0x80, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x1ffe", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 8190}, exp: []byte{0xdb, 0xff, 0x83, 0xd2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xffffffffffffe002", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -8190}, exp: []byte{0xbb, 0xff, 0x83, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x1ffd", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 8189}, exp: []byte{0xbb, 0xff, 0x83, 0xd2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xffffffffffffe003", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -8189}, exp: []byte{0x9b, 0xff, 0x83, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x1fff", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 8191}, exp: []byte{0xfb, 0xff, 0x83, 0xd2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xffffffffffffe001", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -8191}, exp: []byte{0xdb, 0xff, 0x83, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x0", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 0}, exp: []byte{0xde, 0x3, 0x1f, 0x8b}}, - {name: "ADD/dst=R30/0x1", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 1}, exp: []byte{0xde, 0x7, 0x0, 0x91}}, - {name: "ADD/dst=R30/0xffffffffffffffff", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -1}, exp: []byte{0x1b, 0x0, 0x80, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xffffffffffffffff", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -1}, exp: []byte{0x1b, 0x0, 0x80, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x1", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 1}, exp: []byte{0xde, 0x7, 0x0, 0x91}}, - {name: "ADD/dst=R30/0x2", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 2}, exp: []byte{0xde, 0xb, 0x0, 0x91}}, - {name: "ADD/dst=R30/0xfffffffffffffffe", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -2}, exp: []byte{0x3b, 0x0, 0x80, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x3", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 3}, exp: []byte{0xde, 0xf, 0x0, 0x91}}, - {name: "ADD/dst=R30/0xfffffffffffffffd", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -3}, exp: []byte{0x5b, 0x0, 0x80, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xa", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 10}, exp: []byte{0xde, 0x2b, 0x0, 0x91}}, - {name: "ADD/dst=R30/0xfffffffffffffff6", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -10}, exp: []byte{0x3b, 0x1, 0x80, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xfffffffffffffff6", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -10}, exp: []byte{0x3b, 0x1, 0x80, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xa", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 10}, exp: []byte{0xde, 0x2b, 0x0, 0x91}}, - {name: "ADD/dst=R30/0x7b", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 123}, exp: []byte{0xde, 0xef, 0x1, 0x91}}, - {name: "ADD/dst=R30/0xffffffffffffff85", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -123}, exp: []byte{0x5b, 0xf, 0x80, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xffffffffffffff85", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -123}, exp: []byte{0x5b, 0xf, 0x80, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x7b", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 123}, exp: []byte{0xde, 0xef, 0x1, 0x91}}, - {name: "ADD/dst=R30/0x7fff", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 32767}, exp: []byte{0xfb, 0xff, 0x8f, 0xd2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xffffffffffff8001", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -32767}, exp: []byte{0xdb, 0xff, 0x8f, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x7fffffff", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 2147483647}, exp: []byte{0xfb, 0x7b, 0x40, 0xb2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xffffffff80000001", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -2147483647}, exp: []byte{0xfb, 0x87, 0x61, 0xb2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xffffffff", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 4294967295}, exp: []byte{0xfb, 0x7f, 0x40, 0xb2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xffffffff00000001", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -4294967295}, exp: []byte{0xfb, 0x83, 0x60, 0xb2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x4002", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 16386}, exp: []byte{0x5b, 0x0, 0x88, 0xd2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xffffffffffffbffe", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -16386}, exp: []byte{0x3b, 0x0, 0x88, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xffff0000", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 4294901760}, exp: []byte{0xfb, 0xff, 0xbf, 0xd2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xffffffff00010000", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -4294901760}, exp: []byte{0xfb, 0xff, 0x9f, 0x92, 0x3b, 0x0, 0xa0, 0xf2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xffff0001", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 4294901761}, exp: []byte{0x3b, 0x0, 0x80, 0xd2, 0xfb, 0xff, 0xbf, 0xf2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xffffffff0000ffff", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -4294901761}, exp: []byte{0xfb, 0xff, 0xbf, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xf00000f", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 251658255}, exp: []byte{0xfb, 0x1, 0x80, 0xd2, 0x1b, 0xe0, 0xa1, 0xf2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xfffffffff0fffff1", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -251658255}, exp: []byte{0xdb, 0x1, 0x80, 0x92, 0xfb, 0x1f, 0xbe, 0xf2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x7ffe", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 32766}, exp: []byte{0xdb, 0xff, 0x8f, 0xd2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xffffffffffff8002", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -32766}, exp: []byte{0xbb, 0xff, 0x8f, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x7ffffffe", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 2147483646}, exp: []byte{0xfb, 0x77, 0x7f, 0xb2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xffffffff80000002", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -2147483646}, exp: []byte{0xbb, 0xff, 0x9f, 0x92, 0x1b, 0x0, 0xb0, 0xf2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xfffffffe", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 4294967294}, exp: []byte{0xfb, 0x7b, 0x7f, 0xb2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xffffffff00000002", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -4294967294}, exp: []byte{0xbb, 0xff, 0x9f, 0x92, 0x1b, 0x0, 0xa0, 0xf2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x4001", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 16385}, exp: []byte{0x3b, 0x0, 0x88, 0xd2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xffffffffffffbfff", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -16385}, exp: []byte{0x1b, 0x0, 0x88, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xfffeffff", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 4294901759}, exp: []byte{0xfb, 0xff, 0x9f, 0xd2, 0xdb, 0xff, 0xbf, 0xf2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xffffffff00010001", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -4294901759}, exp: []byte{0xdb, 0xff, 0x9f, 0x92, 0x3b, 0x0, 0xa0, 0xf2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xffff0000", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 4294901760}, exp: []byte{0xfb, 0xff, 0xbf, 0xd2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xffffffff00010000", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -4294901760}, exp: []byte{0xfb, 0xff, 0x9f, 0x92, 0x3b, 0x0, 0xa0, 0xf2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xf00000e", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 251658254}, exp: []byte{0xdb, 0x1, 0x80, 0xd2, 0x1b, 0xe0, 0xa1, 0xf2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xfffffffff0fffff2", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -251658254}, exp: []byte{0xbb, 0x1, 0x80, 0x92, 0xfb, 0x1f, 0xbe, 0xf2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x8000", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 32768}, exp: []byte{0xde, 0x23, 0x40, 0x91}}, - {name: "ADD/dst=R30/0xffffffffffff8000", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -32768}, exp: []byte{0xfb, 0xff, 0x8f, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x4009", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 16393}, exp: []byte{0x3b, 0x1, 0x88, 0xd2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xffffffffffffbff7", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -16393}, exp: []byte{0x1b, 0x1, 0x88, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xffeffff", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 268369919}, exp: []byte{0xfb, 0xff, 0x9f, 0xd2, 0xdb, 0xff, 0xa1, 0xf2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xfffffffff0010001", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -268369919}, exp: []byte{0xdb, 0xff, 0x9f, 0x92, 0x3b, 0x0, 0xbe, 0xf2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xffe0000", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 268304384}, exp: []byte{0xdb, 0xff, 0xa1, 0xd2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xfffffffff0020000", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -268304384}, exp: []byte{0xfb, 0xff, 0x9f, 0x92, 0x5b, 0x0, 0xbe, 0xf2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xe00000e", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 234881038}, exp: []byte{0xdb, 0x1, 0x80, 0xd2, 0x1b, 0xc0, 0xa1, 0xf2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xfffffffff1fffff2", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -234881038}, exp: []byte{0xbb, 0x1, 0x80, 0x92, 0xfb, 0x3f, 0xbe, 0xf2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x80010000", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 2147549184}, exp: []byte{0x3b, 0x0, 0xb0, 0xd2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xffffffff7fff0000", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -2147549184}, exp: []byte{0xfb, 0xff, 0x9f, 0x92, 0xfb, 0xff, 0xaf, 0xf2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x10002", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 65538}, exp: []byte{0xde, 0xb, 0x0, 0x91, 0xde, 0x43, 0x40, 0x91}}, - {name: "ADD/dst=R30/0xfffffffffffefffe", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -65538}, exp: []byte{0x3b, 0x0, 0x80, 0x92, 0xdb, 0xff, 0xbf, 0xf2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x100000000", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 4294967296}, exp: []byte{0x3b, 0x0, 0xc0, 0xd2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xffffffff00000000", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -4294967296}, exp: []byte{0xfb, 0x7f, 0x60, 0xb2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x400000000", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 17179869184}, exp: []byte{0x9b, 0x0, 0xc0, 0xd2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xfffffffc00000000", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -17179869184}, exp: []byte{0xfb, 0x77, 0x5e, 0xb2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x10000000000", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 1099511627776}, exp: []byte{0x1b, 0x20, 0xc0, 0xd2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xffffff0000000000", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -1099511627776}, exp: []byte{0xfb, 0x5f, 0x58, 0xb2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x100000001", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 4294967297}, exp: []byte{0xfb, 0x3, 0x0, 0xb2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xfffffffeffffffff", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -4294967297}, exp: []byte{0x3b, 0x0, 0xc0, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x400000001", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 17179869185}, exp: []byte{0x3b, 0x0, 0x80, 0xd2, 0x9b, 0x0, 0xc0, 0xf2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xfffffffbffffffff", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -17179869185}, exp: []byte{0x9b, 0x0, 0xc0, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x10000000001", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 1099511627777}, exp: []byte{0x3b, 0x0, 0x80, 0xd2, 0x1b, 0x20, 0xc0, 0xf2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xfffffeffffffffff", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -1099511627777}, exp: []byte{0x1b, 0x20, 0xc0, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xffffffff", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 4294967295}, exp: []byte{0xfb, 0x7f, 0x40, 0xb2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xffffffff00000001", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -4294967295}, exp: []byte{0xfb, 0x83, 0x60, 0xb2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x3ffffffff", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 17179869183}, exp: []byte{0xfb, 0x87, 0x40, 0xb2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xfffffffc00000001", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -17179869183}, exp: []byte{0xfb, 0x7b, 0x5e, 0xb2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xffffffffff", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 1099511627775}, exp: []byte{0xfb, 0x9f, 0x40, 0xb2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xffffff0000000001", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -1099511627775}, exp: []byte{0xfb, 0x63, 0x58, 0xb2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x10000000f", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 4294967311}, exp: []byte{0xfb, 0x1, 0x80, 0xd2, 0x3b, 0x0, 0xc0, 0xf2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xfffffffefffffff1", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -4294967311}, exp: []byte{0xdb, 0x1, 0x80, 0x92, 0xdb, 0xff, 0xdf, 0xf2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x40000000f", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 17179869199}, exp: []byte{0xfb, 0x1, 0x80, 0xd2, 0x9b, 0x0, 0xc0, 0xf2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xfffffffbfffffff1", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -17179869199}, exp: []byte{0xdb, 0x1, 0x80, 0x92, 0x7b, 0xff, 0xdf, 0xf2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x1000000000f", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 1099511627791}, exp: []byte{0xfb, 0x1, 0x80, 0xd2, 0x1b, 0x20, 0xc0, 0xf2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xfffffefffffffff1", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -1099511627791}, exp: []byte{0xdb, 0x1, 0x80, 0x92, 0xfb, 0xdf, 0xdf, 0xf2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xfffffff1", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 4294967281}, exp: []byte{0x3b, 0xfe, 0x9f, 0xd2, 0xfb, 0xff, 0xbf, 0xf2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xffffffff0000000f", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -4294967281}, exp: []byte{0xfb, 0x8f, 0x60, 0xb2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x3fffffff1", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 17179869169}, exp: []byte{0x3b, 0xfe, 0x9f, 0xd2, 0xfb, 0xff, 0xbf, 0xf2, 0x7b, 0x0, 0xc0, 0xf2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xfffffffc0000000f", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -17179869169}, exp: []byte{0xfb, 0x87, 0x5e, 0xb2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xfffffffff1", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 1099511627761}, exp: []byte{0x3b, 0xfe, 0x9f, 0xd2, 0xfb, 0xff, 0xbf, 0xf2, 0xfb, 0x1f, 0xc0, 0xf2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xffffff000000000f", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -1099511627761}, exp: []byte{0xfb, 0x6f, 0x58, 0xb2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x7fffffffffffffff", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 9223372036854775807}, exp: []byte{0x1b, 0x0, 0xf0, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x8000000000000001", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -9223372036854775807}, exp: []byte{0xfb, 0x7, 0x41, 0xb2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x8000000000000000", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -9223372036854775808}, exp: []byte{0x1b, 0x0, 0xf0, 0xd2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x8000000000000000", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -9223372036854775808}, exp: []byte{0x1b, 0x0, 0xf0, 0xd2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x40000001", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 1073741825}, exp: []byte{0x3b, 0x0, 0x80, 0xd2, 0x1b, 0x0, 0xa8, 0xf2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xffffffffbfffffff", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -1073741825}, exp: []byte{0x1b, 0x0, 0xa8, 0x92, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x7000000010000000", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 8070450532516364288}, exp: []byte{0x1b, 0x0, 0xa2, 0xd2, 0x1b, 0x0, 0xee, 0xf2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x8ffffffff0000000", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -8070450532516364288}, exp: []byte{0x1b, 0x0, 0xbe, 0xd2, 0xfb, 0xff, 0xdf, 0xf2, 0xfb, 0xff, 0xf1, 0xf2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x7000000100000000", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 8070450536542896128}, exp: []byte{0x3b, 0x0, 0xc0, 0xd2, 0x1b, 0x0, 0xee, 0xf2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x8fffffff00000000", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -8070450536542896128}, exp: []byte{0xfb, 0xff, 0xdf, 0xd2, 0xfb, 0xff, 0xf1, 0xf2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x7000100000000000", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 8070468124433973248}, exp: []byte{0x1b, 0x0, 0xc2, 0xd2, 0x1b, 0x0, 0xee, 0xf2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x8ffff00000000000", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -8070468124433973248}, exp: []byte{0x1b, 0x0, 0xde, 0xd2, 0xfb, 0xff, 0xf1, 0xf2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x154b4", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 87220}, exp: []byte{0xde, 0xd3, 0x12, 0x91, 0xde, 0x57, 0x40, 0x91}}, - {name: "ADD/dst=R30/0xfffffffffffeab4c", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -87220}, exp: []byte{0x7b, 0x96, 0x8a, 0x92, 0xdb, 0xff, 0xbf, 0xf2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x40008", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 262152}, exp: []byte{0xde, 0x23, 0x0, 0x91, 0xde, 0x3, 0x41, 0x91}}, - {name: "ADD/dst=R30/0xfffffffffffbfff8", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -262152}, exp: []byte{0xfb, 0x0, 0x80, 0x92, 0x7b, 0xff, 0xbf, 0xf2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xffff0000c466361f", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -281471681677793}, exp: []byte{0xfb, 0xc3, 0x86, 0xd2, 0xdb, 0x8c, 0xb8, 0xf2, 0xfb, 0xff, 0xff, 0xf2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xffff3b99c9e1", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 281471681677793}, exp: []byte{0x3b, 0x3c, 0x99, 0xd2, 0x3b, 0x73, 0xa7, 0xf2, 0xfb, 0xff, 0xdf, 0xf2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xc465c9ff", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 3295005183}, exp: []byte{0xfb, 0x3f, 0x99, 0xd2, 0xbb, 0x8c, 0xb8, 0xf2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xffffffff3b9a3601", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -3295005183}, exp: []byte{0xdb, 0x3f, 0x99, 0x92, 0x5b, 0x73, 0xa7, 0xf2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x89705f4136b4a598", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -8543223759426509416}, exp: []byte{0x1b, 0xb3, 0x94, 0xd2, 0x9b, 0xd6, 0xa6, 0xf2, 0x3b, 0xe8, 0xcb, 0xf2, 0x1b, 0x2e, 0xf1, 0xf2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x768fa0bec94b5a68", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 8543223759426509416}, exp: []byte{0x1b, 0x4d, 0x8b, 0xd2, 0x7b, 0x29, 0xb9, 0xf2, 0xdb, 0x17, 0xd4, 0xf2, 0xfb, 0xd1, 0xee, 0xf2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xffffffffc4653600", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -1000000000}, exp: []byte{0xfb, 0x3f, 0x99, 0x92, 0xbb, 0x8c, 0xb8, 0xf2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0x3b9aca00", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 1000000000}, exp: []byte{0x1b, 0x40, 0x99, 0xd2, 0x5b, 0x73, 0xa7, 0xf2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xffffff", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: 16777215}, exp: []byte{0xfb, 0x5f, 0x40, 0xb2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADD/dst=R30/0xffffffffff000001", n: &nodeImpl{instruction: ADD, dstReg: RegR30, srcConst: -16777215}, exp: []byte{0xfb, 0xa3, 0x68, 0xb2, 0xde, 0x3, 0x1b, 0x8b}}, - {name: "ADDS/dst=R30/0x1", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 1}, exp: []byte{0xde, 0x7, 0x0, 0xb1}}, - {name: "ADDS/dst=R30/0xffffffffffffffff", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -1}, exp: []byte{0x1b, 0x0, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xfff", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 4095}, exp: []byte{0xde, 0xff, 0x3f, 0xb1}}, - {name: "ADDS/dst=R30/0xfffffffffffff001", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -4095}, exp: []byte{0xdb, 0xff, 0x81, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xfff000", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 16773120}, exp: []byte{0xde, 0xff, 0x7f, 0xb1}}, - {name: "ADDS/dst=R30/0xffffffffff001000", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -16773120}, exp: []byte{0xfb, 0xff, 0x9d, 0x92, 0x1b, 0xe0, 0xbf, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x7b000", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 503808}, exp: []byte{0xde, 0xef, 0x41, 0xb1}}, - {name: "ADDS/dst=R30/0xfffffffffff85000", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -503808}, exp: []byte{0xfb, 0xff, 0x95, 0x92, 0x1b, 0xff, 0xbf, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x8001", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 32769}, exp: []byte{0x3b, 0x0, 0x90, 0xd2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xffffffffffff7fff", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -32769}, exp: []byte{0x1b, 0x0, 0x90, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x80010000", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 2147549184}, exp: []byte{0x3b, 0x0, 0xb0, 0xd2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xffffffff7fff0000", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -2147549184}, exp: []byte{0xfb, 0xff, 0x9f, 0x92, 0xfb, 0xff, 0xaf, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x800100000000", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 140741783322624}, exp: []byte{0x3b, 0x0, 0xd0, 0xd2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xffff7fff00000000", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -140741783322624}, exp: []byte{0xfb, 0xff, 0xcf, 0xd2, 0xfb, 0xff, 0xff, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xffffffffffff", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 281474976710655}, exp: []byte{0xfb, 0xff, 0xff, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xffff000000000001", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -281474976710655}, exp: []byte{0xfb, 0x43, 0x50, 0xb2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xffff0000ffffffff", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -281470681743361}, exp: []byte{0xfb, 0xff, 0xdf, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xffff00000001", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 281470681743361}, exp: []byte{0x3b, 0x0, 0x80, 0xd2, 0xfb, 0xff, 0xdf, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xffffffff80000001", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -2147483647}, exp: []byte{0xfb, 0x87, 0x61, 0xb2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x7fffffff", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 2147483647}, exp: []byte{0xfb, 0x7b, 0x40, 0xb2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xffff00000000ffff", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -281474976645121}, exp: []byte{0xfb, 0x7f, 0x50, 0xb2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xffffffff0001", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 281474976645121}, exp: []byte{0xdb, 0xff, 0x9f, 0x92, 0x1b, 0x0, 0xe0, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x100001", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 1048577}, exp: []byte{0x3b, 0x0, 0x80, 0xd2, 0x1b, 0x2, 0xa0, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xffffffffffefffff", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -1048577}, exp: []byte{0x1b, 0x2, 0xa0, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xfffff", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 1048575}, exp: []byte{0xfb, 0x4f, 0x40, 0xb2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xfffffffffff00001", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -1048575}, exp: []byte{0xfb, 0xb3, 0x6c, 0xb2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x800001", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 8388609}, exp: []byte{0x3b, 0x0, 0x80, 0xd2, 0x1b, 0x10, 0xa0, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xffffffffff7fffff", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -8388609}, exp: []byte{0x1b, 0x10, 0xa0, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x40000001", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 1073741825}, exp: []byte{0x3b, 0x0, 0x80, 0xd2, 0x1b, 0x0, 0xa8, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xffffffffbfffffff", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -1073741825}, exp: []byte{0x1b, 0x0, 0xa8, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x2", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 2}, exp: []byte{0xde, 0xb, 0x0, 0xb1}}, - {name: "ADDS/dst=R30/0xfffffffffffffffe", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -2}, exp: []byte{0x3b, 0x0, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x3", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 3}, exp: []byte{0xde, 0xf, 0x0, 0xb1}}, - {name: "ADDS/dst=R30/0xfffffffffffffffd", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -3}, exp: []byte{0x5b, 0x0, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x1", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 1}, exp: []byte{0xde, 0x7, 0x0, 0xb1}}, - {name: "ADDS/dst=R30/0xffffffffffffffff", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -1}, exp: []byte{0x1b, 0x0, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x11", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 17}, exp: []byte{0xde, 0x47, 0x0, 0xb1}}, - {name: "ADDS/dst=R30/0xffffffffffffffef", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -17}, exp: []byte{0x1b, 0x2, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x4", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 4}, exp: []byte{0xde, 0x13, 0x0, 0xb1}}, - {name: "ADDS/dst=R30/0xfffffffffffffffc", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -4}, exp: []byte{0x7b, 0x0, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x5", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 5}, exp: []byte{0xde, 0x17, 0x0, 0xb1}}, - {name: "ADDS/dst=R30/0xfffffffffffffffb", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -5}, exp: []byte{0x9b, 0x0, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x3", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 3}, exp: []byte{0xde, 0xf, 0x0, 0xb1}}, - {name: "ADDS/dst=R30/0xfffffffffffffffd", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -3}, exp: []byte{0x5b, 0x0, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x13", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 19}, exp: []byte{0xde, 0x4f, 0x0, 0xb1}}, - {name: "ADDS/dst=R30/0xffffffffffffffed", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -19}, exp: []byte{0x5b, 0x2, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x8", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 8}, exp: []byte{0xde, 0x23, 0x0, 0xb1}}, - {name: "ADDS/dst=R30/0xfffffffffffffff8", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -8}, exp: []byte{0xfb, 0x0, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x9", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 9}, exp: []byte{0xde, 0x27, 0x0, 0xb1}}, - {name: "ADDS/dst=R30/0xfffffffffffffff7", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -9}, exp: []byte{0x1b, 0x1, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x7", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 7}, exp: []byte{0xde, 0x1f, 0x0, 0xb1}}, - {name: "ADDS/dst=R30/0xfffffffffffffff9", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -7}, exp: []byte{0xdb, 0x0, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x17", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 23}, exp: []byte{0xde, 0x5f, 0x0, 0xb1}}, - {name: "ADDS/dst=R30/0xffffffffffffffe9", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -23}, exp: []byte{0xdb, 0x2, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x10", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 16}, exp: []byte{0xde, 0x43, 0x0, 0xb1}}, - {name: "ADDS/dst=R30/0xfffffffffffffff0", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -16}, exp: []byte{0xfb, 0x1, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x11", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 17}, exp: []byte{0xde, 0x47, 0x0, 0xb1}}, - {name: "ADDS/dst=R30/0xffffffffffffffef", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -17}, exp: []byte{0x1b, 0x2, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xf", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 15}, exp: []byte{0xde, 0x3f, 0x0, 0xb1}}, - {name: "ADDS/dst=R30/0xfffffffffffffff1", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -15}, exp: []byte{0xdb, 0x1, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x1f", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 31}, exp: []byte{0xde, 0x7f, 0x0, 0xb1}}, - {name: "ADDS/dst=R30/0xffffffffffffffe1", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -31}, exp: []byte{0xdb, 0x3, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x20", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 32}, exp: []byte{0xde, 0x83, 0x0, 0xb1}}, - {name: "ADDS/dst=R30/0xffffffffffffffe0", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -32}, exp: []byte{0xfb, 0x3, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x21", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 33}, exp: []byte{0xde, 0x87, 0x0, 0xb1}}, - {name: "ADDS/dst=R30/0xffffffffffffffdf", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -33}, exp: []byte{0x1b, 0x4, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x1f", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 31}, exp: []byte{0xde, 0x7f, 0x0, 0xb1}}, - {name: "ADDS/dst=R30/0xffffffffffffffe1", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -31}, exp: []byte{0xdb, 0x3, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x2f", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 47}, exp: []byte{0xde, 0xbf, 0x0, 0xb1}}, - {name: "ADDS/dst=R30/0xffffffffffffffd1", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -47}, exp: []byte{0xdb, 0x5, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x40", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 64}, exp: []byte{0xde, 0x3, 0x1, 0xb1}}, - {name: "ADDS/dst=R30/0xffffffffffffffc0", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -64}, exp: []byte{0xfb, 0x7, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x41", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 65}, exp: []byte{0xde, 0x7, 0x1, 0xb1}}, - {name: "ADDS/dst=R30/0xffffffffffffffbf", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -65}, exp: []byte{0x1b, 0x8, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x3f", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 63}, exp: []byte{0xde, 0xff, 0x0, 0xb1}}, - {name: "ADDS/dst=R30/0xffffffffffffffc1", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -63}, exp: []byte{0xdb, 0x7, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x4f", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 79}, exp: []byte{0xde, 0x3f, 0x1, 0xb1}}, - {name: "ADDS/dst=R30/0xffffffffffffffb1", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -79}, exp: []byte{0xdb, 0x9, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x1ffe", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 8190}, exp: []byte{0xdb, 0xff, 0x83, 0xd2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xffffffffffffe002", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -8190}, exp: []byte{0xbb, 0xff, 0x83, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x1ffd", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 8189}, exp: []byte{0xbb, 0xff, 0x83, 0xd2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xffffffffffffe003", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -8189}, exp: []byte{0x9b, 0xff, 0x83, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x1fff", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 8191}, exp: []byte{0xfb, 0xff, 0x83, 0xd2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xffffffffffffe001", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -8191}, exp: []byte{0xdb, 0xff, 0x83, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x0", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 0}, exp: []byte{0xde, 0x3, 0x1f, 0xab}}, - {name: "ADDS/dst=R30/0x1", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 1}, exp: []byte{0xde, 0x7, 0x0, 0xb1}}, - {name: "ADDS/dst=R30/0xffffffffffffffff", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -1}, exp: []byte{0x1b, 0x0, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xffffffffffffffff", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -1}, exp: []byte{0x1b, 0x0, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x1", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 1}, exp: []byte{0xde, 0x7, 0x0, 0xb1}}, - {name: "ADDS/dst=R30/0x2", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 2}, exp: []byte{0xde, 0xb, 0x0, 0xb1}}, - {name: "ADDS/dst=R30/0xfffffffffffffffe", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -2}, exp: []byte{0x3b, 0x0, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x3", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 3}, exp: []byte{0xde, 0xf, 0x0, 0xb1}}, - {name: "ADDS/dst=R30/0xfffffffffffffffd", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -3}, exp: []byte{0x5b, 0x0, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xa", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 10}, exp: []byte{0xde, 0x2b, 0x0, 0xb1}}, - {name: "ADDS/dst=R30/0xfffffffffffffff6", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -10}, exp: []byte{0x3b, 0x1, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xfffffffffffffff6", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -10}, exp: []byte{0x3b, 0x1, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xa", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 10}, exp: []byte{0xde, 0x2b, 0x0, 0xb1}}, - {name: "ADDS/dst=R30/0x7b", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 123}, exp: []byte{0xde, 0xef, 0x1, 0xb1}}, - {name: "ADDS/dst=R30/0xffffffffffffff85", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -123}, exp: []byte{0x5b, 0xf, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xffffffffffffff85", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -123}, exp: []byte{0x5b, 0xf, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x7b", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 123}, exp: []byte{0xde, 0xef, 0x1, 0xb1}}, - {name: "ADDS/dst=R30/0x7fff", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 32767}, exp: []byte{0xfb, 0xff, 0x8f, 0xd2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xffffffffffff8001", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -32767}, exp: []byte{0xdb, 0xff, 0x8f, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x7fffffff", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 2147483647}, exp: []byte{0xfb, 0x7b, 0x40, 0xb2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xffffffff80000001", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -2147483647}, exp: []byte{0xfb, 0x87, 0x61, 0xb2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xffffffff", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 4294967295}, exp: []byte{0xfb, 0x7f, 0x40, 0xb2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xffffffff00000001", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -4294967295}, exp: []byte{0xfb, 0x83, 0x60, 0xb2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x4002", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 16386}, exp: []byte{0x5b, 0x0, 0x88, 0xd2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xffffffffffffbffe", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -16386}, exp: []byte{0x3b, 0x0, 0x88, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xffff0000", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 4294901760}, exp: []byte{0xfb, 0xff, 0xbf, 0xd2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xffffffff00010000", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -4294901760}, exp: []byte{0xfb, 0xff, 0x9f, 0x92, 0x3b, 0x0, 0xa0, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xffff0001", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 4294901761}, exp: []byte{0x3b, 0x0, 0x80, 0xd2, 0xfb, 0xff, 0xbf, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xffffffff0000ffff", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -4294901761}, exp: []byte{0xfb, 0xff, 0xbf, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xf00000f", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 251658255}, exp: []byte{0xfb, 0x1, 0x80, 0xd2, 0x1b, 0xe0, 0xa1, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xfffffffff0fffff1", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -251658255}, exp: []byte{0xdb, 0x1, 0x80, 0x92, 0xfb, 0x1f, 0xbe, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x7ffe", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 32766}, exp: []byte{0xdb, 0xff, 0x8f, 0xd2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xffffffffffff8002", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -32766}, exp: []byte{0xbb, 0xff, 0x8f, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x7ffffffe", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 2147483646}, exp: []byte{0xfb, 0x77, 0x7f, 0xb2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xffffffff80000002", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -2147483646}, exp: []byte{0xbb, 0xff, 0x9f, 0x92, 0x1b, 0x0, 0xb0, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xfffffffe", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 4294967294}, exp: []byte{0xfb, 0x7b, 0x7f, 0xb2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xffffffff00000002", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -4294967294}, exp: []byte{0xbb, 0xff, 0x9f, 0x92, 0x1b, 0x0, 0xa0, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x4001", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 16385}, exp: []byte{0x3b, 0x0, 0x88, 0xd2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xffffffffffffbfff", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -16385}, exp: []byte{0x1b, 0x0, 0x88, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xfffeffff", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 4294901759}, exp: []byte{0xfb, 0xff, 0x9f, 0xd2, 0xdb, 0xff, 0xbf, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xffffffff00010001", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -4294901759}, exp: []byte{0xdb, 0xff, 0x9f, 0x92, 0x3b, 0x0, 0xa0, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xffff0000", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 4294901760}, exp: []byte{0xfb, 0xff, 0xbf, 0xd2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xffffffff00010000", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -4294901760}, exp: []byte{0xfb, 0xff, 0x9f, 0x92, 0x3b, 0x0, 0xa0, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xf00000e", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 251658254}, exp: []byte{0xdb, 0x1, 0x80, 0xd2, 0x1b, 0xe0, 0xa1, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xfffffffff0fffff2", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -251658254}, exp: []byte{0xbb, 0x1, 0x80, 0x92, 0xfb, 0x1f, 0xbe, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x8000", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 32768}, exp: []byte{0xde, 0x23, 0x40, 0xb1}}, - {name: "ADDS/dst=R30/0xffffffffffff8000", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -32768}, exp: []byte{0xfb, 0xff, 0x8f, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x4009", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 16393}, exp: []byte{0x3b, 0x1, 0x88, 0xd2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xffffffffffffbff7", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -16393}, exp: []byte{0x1b, 0x1, 0x88, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xffeffff", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 268369919}, exp: []byte{0xfb, 0xff, 0x9f, 0xd2, 0xdb, 0xff, 0xa1, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xfffffffff0010001", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -268369919}, exp: []byte{0xdb, 0xff, 0x9f, 0x92, 0x3b, 0x0, 0xbe, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xffe0000", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 268304384}, exp: []byte{0xdb, 0xff, 0xa1, 0xd2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xfffffffff0020000", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -268304384}, exp: []byte{0xfb, 0xff, 0x9f, 0x92, 0x5b, 0x0, 0xbe, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xe00000e", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 234881038}, exp: []byte{0xdb, 0x1, 0x80, 0xd2, 0x1b, 0xc0, 0xa1, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xfffffffff1fffff2", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -234881038}, exp: []byte{0xbb, 0x1, 0x80, 0x92, 0xfb, 0x3f, 0xbe, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x80010000", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 2147549184}, exp: []byte{0x3b, 0x0, 0xb0, 0xd2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xffffffff7fff0000", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -2147549184}, exp: []byte{0xfb, 0xff, 0x9f, 0x92, 0xfb, 0xff, 0xaf, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x10002", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 65538}, exp: []byte{0x5b, 0x0, 0x80, 0xd2, 0x3b, 0x0, 0xa0, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xfffffffffffefffe", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -65538}, exp: []byte{0x3b, 0x0, 0x80, 0x92, 0xdb, 0xff, 0xbf, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x100000000", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 4294967296}, exp: []byte{0x3b, 0x0, 0xc0, 0xd2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xffffffff00000000", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -4294967296}, exp: []byte{0xfb, 0x7f, 0x60, 0xb2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x400000000", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 17179869184}, exp: []byte{0x9b, 0x0, 0xc0, 0xd2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xfffffffc00000000", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -17179869184}, exp: []byte{0xfb, 0x77, 0x5e, 0xb2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x10000000000", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 1099511627776}, exp: []byte{0x1b, 0x20, 0xc0, 0xd2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xffffff0000000000", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -1099511627776}, exp: []byte{0xfb, 0x5f, 0x58, 0xb2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x100000001", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 4294967297}, exp: []byte{0xfb, 0x3, 0x0, 0xb2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xfffffffeffffffff", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -4294967297}, exp: []byte{0x3b, 0x0, 0xc0, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x400000001", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 17179869185}, exp: []byte{0x3b, 0x0, 0x80, 0xd2, 0x9b, 0x0, 0xc0, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xfffffffbffffffff", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -17179869185}, exp: []byte{0x9b, 0x0, 0xc0, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x10000000001", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 1099511627777}, exp: []byte{0x3b, 0x0, 0x80, 0xd2, 0x1b, 0x20, 0xc0, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xfffffeffffffffff", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -1099511627777}, exp: []byte{0x1b, 0x20, 0xc0, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xffffffff", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 4294967295}, exp: []byte{0xfb, 0x7f, 0x40, 0xb2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xffffffff00000001", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -4294967295}, exp: []byte{0xfb, 0x83, 0x60, 0xb2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x3ffffffff", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 17179869183}, exp: []byte{0xfb, 0x87, 0x40, 0xb2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xfffffffc00000001", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -17179869183}, exp: []byte{0xfb, 0x7b, 0x5e, 0xb2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xffffffffff", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 1099511627775}, exp: []byte{0xfb, 0x9f, 0x40, 0xb2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xffffff0000000001", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -1099511627775}, exp: []byte{0xfb, 0x63, 0x58, 0xb2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x10000000f", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 4294967311}, exp: []byte{0xfb, 0x1, 0x80, 0xd2, 0x3b, 0x0, 0xc0, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xfffffffefffffff1", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -4294967311}, exp: []byte{0xdb, 0x1, 0x80, 0x92, 0xdb, 0xff, 0xdf, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x40000000f", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 17179869199}, exp: []byte{0xfb, 0x1, 0x80, 0xd2, 0x9b, 0x0, 0xc0, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xfffffffbfffffff1", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -17179869199}, exp: []byte{0xdb, 0x1, 0x80, 0x92, 0x7b, 0xff, 0xdf, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x1000000000f", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 1099511627791}, exp: []byte{0xfb, 0x1, 0x80, 0xd2, 0x1b, 0x20, 0xc0, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xfffffefffffffff1", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -1099511627791}, exp: []byte{0xdb, 0x1, 0x80, 0x92, 0xfb, 0xdf, 0xdf, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xfffffff1", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 4294967281}, exp: []byte{0x3b, 0xfe, 0x9f, 0xd2, 0xfb, 0xff, 0xbf, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xffffffff0000000f", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -4294967281}, exp: []byte{0xfb, 0x8f, 0x60, 0xb2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x3fffffff1", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 17179869169}, exp: []byte{0x3b, 0xfe, 0x9f, 0xd2, 0xfb, 0xff, 0xbf, 0xf2, 0x7b, 0x0, 0xc0, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xfffffffc0000000f", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -17179869169}, exp: []byte{0xfb, 0x87, 0x5e, 0xb2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xfffffffff1", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 1099511627761}, exp: []byte{0x3b, 0xfe, 0x9f, 0xd2, 0xfb, 0xff, 0xbf, 0xf2, 0xfb, 0x1f, 0xc0, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xffffff000000000f", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -1099511627761}, exp: []byte{0xfb, 0x6f, 0x58, 0xb2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x7fffffffffffffff", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 9223372036854775807}, exp: []byte{0x1b, 0x0, 0xf0, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x8000000000000001", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -9223372036854775807}, exp: []byte{0xfb, 0x7, 0x41, 0xb2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x8000000000000000", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -9223372036854775808}, exp: []byte{0x1b, 0x0, 0xf0, 0xd2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x8000000000000000", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -9223372036854775808}, exp: []byte{0x1b, 0x0, 0xf0, 0xd2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x40000001", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 1073741825}, exp: []byte{0x3b, 0x0, 0x80, 0xd2, 0x1b, 0x0, 0xa8, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xffffffffbfffffff", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -1073741825}, exp: []byte{0x1b, 0x0, 0xa8, 0x92, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x7000000010000000", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 8070450532516364288}, exp: []byte{0x1b, 0x0, 0xa2, 0xd2, 0x1b, 0x0, 0xee, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x8ffffffff0000000", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -8070450532516364288}, exp: []byte{0x1b, 0x0, 0xbe, 0xd2, 0xfb, 0xff, 0xdf, 0xf2, 0xfb, 0xff, 0xf1, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x7000000100000000", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 8070450536542896128}, exp: []byte{0x3b, 0x0, 0xc0, 0xd2, 0x1b, 0x0, 0xee, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x8fffffff00000000", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -8070450536542896128}, exp: []byte{0xfb, 0xff, 0xdf, 0xd2, 0xfb, 0xff, 0xf1, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x7000100000000000", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 8070468124433973248}, exp: []byte{0x1b, 0x0, 0xc2, 0xd2, 0x1b, 0x0, 0xee, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x8ffff00000000000", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -8070468124433973248}, exp: []byte{0x1b, 0x0, 0xde, 0xd2, 0xfb, 0xff, 0xf1, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x154b4", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 87220}, exp: []byte{0x9b, 0x96, 0x8a, 0xd2, 0x3b, 0x0, 0xa0, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xfffffffffffeab4c", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -87220}, exp: []byte{0x7b, 0x96, 0x8a, 0x92, 0xdb, 0xff, 0xbf, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x40008", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 262152}, exp: []byte{0x1b, 0x1, 0x80, 0xd2, 0x9b, 0x0, 0xa0, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xfffffffffffbfff8", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -262152}, exp: []byte{0xfb, 0x0, 0x80, 0x92, 0x7b, 0xff, 0xbf, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xffff0000c466361f", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -281471681677793}, exp: []byte{0xfb, 0xc3, 0x86, 0xd2, 0xdb, 0x8c, 0xb8, 0xf2, 0xfb, 0xff, 0xff, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xffff3b99c9e1", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 281471681677793}, exp: []byte{0x3b, 0x3c, 0x99, 0xd2, 0x3b, 0x73, 0xa7, 0xf2, 0xfb, 0xff, 0xdf, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xc465c9ff", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 3295005183}, exp: []byte{0xfb, 0x3f, 0x99, 0xd2, 0xbb, 0x8c, 0xb8, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xffffffff3b9a3601", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -3295005183}, exp: []byte{0xdb, 0x3f, 0x99, 0x92, 0x5b, 0x73, 0xa7, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x89705f4136b4a598", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -8543223759426509416}, exp: []byte{0x1b, 0xb3, 0x94, 0xd2, 0x9b, 0xd6, 0xa6, 0xf2, 0x3b, 0xe8, 0xcb, 0xf2, 0x1b, 0x2e, 0xf1, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x768fa0bec94b5a68", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 8543223759426509416}, exp: []byte{0x1b, 0x4d, 0x8b, 0xd2, 0x7b, 0x29, 0xb9, 0xf2, 0xdb, 0x17, 0xd4, 0xf2, 0xfb, 0xd1, 0xee, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xffffffffc4653600", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -1000000000}, exp: []byte{0xfb, 0x3f, 0x99, 0x92, 0xbb, 0x8c, 0xb8, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0x3b9aca00", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 1000000000}, exp: []byte{0x1b, 0x40, 0x99, 0xd2, 0x5b, 0x73, 0xa7, 0xf2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xffffff", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: 16777215}, exp: []byte{0xfb, 0x5f, 0x40, 0xb2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "ADDS/dst=R30/0xffffffffff000001", n: &nodeImpl{instruction: ADDS, dstReg: RegR30, srcConst: -16777215}, exp: []byte{0xfb, 0xa3, 0x68, 0xb2, 0xde, 0x3, 0x1b, 0xab}}, - {name: "SUB/dst=R30/0x1", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 1}, exp: []byte{0xde, 0x7, 0x0, 0xd1}}, - {name: "SUB/dst=R30/0xffffffffffffffff", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -1}, exp: []byte{0x1b, 0x0, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xfff", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 4095}, exp: []byte{0xde, 0xff, 0x3f, 0xd1}}, - {name: "SUB/dst=R30/0xfffffffffffff001", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -4095}, exp: []byte{0xdb, 0xff, 0x81, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xfff000", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 16773120}, exp: []byte{0xde, 0xff, 0x7f, 0xd1}}, - {name: "SUB/dst=R30/0xffffffffff001000", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -16773120}, exp: []byte{0xfb, 0xff, 0x9d, 0x92, 0x1b, 0xe0, 0xbf, 0xf2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x7b000", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 503808}, exp: []byte{0xde, 0xef, 0x41, 0xd1}}, - {name: "SUB/dst=R30/0xfffffffffff85000", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -503808}, exp: []byte{0xfb, 0xff, 0x95, 0x92, 0x1b, 0xff, 0xbf, 0xf2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x8001", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 32769}, exp: []byte{0x3b, 0x0, 0x90, 0xd2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xffffffffffff7fff", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -32769}, exp: []byte{0x1b, 0x0, 0x90, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x80010000", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 2147549184}, exp: []byte{0x3b, 0x0, 0xb0, 0xd2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xffffffff7fff0000", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -2147549184}, exp: []byte{0xfb, 0xff, 0x9f, 0x92, 0xfb, 0xff, 0xaf, 0xf2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x800100000000", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 140741783322624}, exp: []byte{0x3b, 0x0, 0xd0, 0xd2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xffff7fff00000000", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -140741783322624}, exp: []byte{0xfb, 0xff, 0xcf, 0xd2, 0xfb, 0xff, 0xff, 0xf2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xffffffffffff", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 281474976710655}, exp: []byte{0xfb, 0xff, 0xff, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xffff000000000001", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -281474976710655}, exp: []byte{0xfb, 0x43, 0x50, 0xb2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xffff0000ffffffff", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -281470681743361}, exp: []byte{0xfb, 0xff, 0xdf, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xffff00000001", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 281470681743361}, exp: []byte{0x3b, 0x0, 0x80, 0xd2, 0xfb, 0xff, 0xdf, 0xf2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xffffffff80000001", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -2147483647}, exp: []byte{0xfb, 0x87, 0x61, 0xb2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x7fffffff", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 2147483647}, exp: []byte{0xfb, 0x7b, 0x40, 0xb2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xffff00000000ffff", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -281474976645121}, exp: []byte{0xfb, 0x7f, 0x50, 0xb2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xffffffff0001", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 281474976645121}, exp: []byte{0xdb, 0xff, 0x9f, 0x92, 0x1b, 0x0, 0xe0, 0xf2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x100001", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 1048577}, exp: []byte{0xde, 0x7, 0x0, 0xd1, 0xde, 0x3, 0x44, 0xd1}}, - {name: "SUB/dst=R30/0xffffffffffefffff", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -1048577}, exp: []byte{0x1b, 0x2, 0xa0, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xfffff", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 1048575}, exp: []byte{0xfb, 0x4f, 0x40, 0xb2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xfffffffffff00001", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -1048575}, exp: []byte{0xfb, 0xb3, 0x6c, 0xb2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x800001", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 8388609}, exp: []byte{0xde, 0x7, 0x0, 0xd1, 0xde, 0x3, 0x60, 0xd1}}, - {name: "SUB/dst=R30/0xffffffffff7fffff", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -8388609}, exp: []byte{0x1b, 0x10, 0xa0, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x40000001", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 1073741825}, exp: []byte{0x3b, 0x0, 0x80, 0xd2, 0x1b, 0x0, 0xa8, 0xf2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xffffffffbfffffff", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -1073741825}, exp: []byte{0x1b, 0x0, 0xa8, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x2", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 2}, exp: []byte{0xde, 0xb, 0x0, 0xd1}}, - {name: "SUB/dst=R30/0xfffffffffffffffe", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -2}, exp: []byte{0x3b, 0x0, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x3", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 3}, exp: []byte{0xde, 0xf, 0x0, 0xd1}}, - {name: "SUB/dst=R30/0xfffffffffffffffd", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -3}, exp: []byte{0x5b, 0x0, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x1", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 1}, exp: []byte{0xde, 0x7, 0x0, 0xd1}}, - {name: "SUB/dst=R30/0xffffffffffffffff", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -1}, exp: []byte{0x1b, 0x0, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x11", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 17}, exp: []byte{0xde, 0x47, 0x0, 0xd1}}, - {name: "SUB/dst=R30/0xffffffffffffffef", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -17}, exp: []byte{0x1b, 0x2, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x4", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 4}, exp: []byte{0xde, 0x13, 0x0, 0xd1}}, - {name: "SUB/dst=R30/0xfffffffffffffffc", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -4}, exp: []byte{0x7b, 0x0, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x5", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 5}, exp: []byte{0xde, 0x17, 0x0, 0xd1}}, - {name: "SUB/dst=R30/0xfffffffffffffffb", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -5}, exp: []byte{0x9b, 0x0, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x3", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 3}, exp: []byte{0xde, 0xf, 0x0, 0xd1}}, - {name: "SUB/dst=R30/0xfffffffffffffffd", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -3}, exp: []byte{0x5b, 0x0, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x13", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 19}, exp: []byte{0xde, 0x4f, 0x0, 0xd1}}, - {name: "SUB/dst=R30/0xffffffffffffffed", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -19}, exp: []byte{0x5b, 0x2, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x8", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 8}, exp: []byte{0xde, 0x23, 0x0, 0xd1}}, - {name: "SUB/dst=R30/0xfffffffffffffff8", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -8}, exp: []byte{0xfb, 0x0, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x9", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 9}, exp: []byte{0xde, 0x27, 0x0, 0xd1}}, - {name: "SUB/dst=R30/0xfffffffffffffff7", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -9}, exp: []byte{0x1b, 0x1, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x7", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 7}, exp: []byte{0xde, 0x1f, 0x0, 0xd1}}, - {name: "SUB/dst=R30/0xfffffffffffffff9", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -7}, exp: []byte{0xdb, 0x0, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x17", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 23}, exp: []byte{0xde, 0x5f, 0x0, 0xd1}}, - {name: "SUB/dst=R30/0xffffffffffffffe9", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -23}, exp: []byte{0xdb, 0x2, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x10", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 16}, exp: []byte{0xde, 0x43, 0x0, 0xd1}}, - {name: "SUB/dst=R30/0xfffffffffffffff0", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -16}, exp: []byte{0xfb, 0x1, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x11", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 17}, exp: []byte{0xde, 0x47, 0x0, 0xd1}}, - {name: "SUB/dst=R30/0xffffffffffffffef", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -17}, exp: []byte{0x1b, 0x2, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xf", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 15}, exp: []byte{0xde, 0x3f, 0x0, 0xd1}}, - {name: "SUB/dst=R30/0xfffffffffffffff1", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -15}, exp: []byte{0xdb, 0x1, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x1f", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 31}, exp: []byte{0xde, 0x7f, 0x0, 0xd1}}, - {name: "SUB/dst=R30/0xffffffffffffffe1", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -31}, exp: []byte{0xdb, 0x3, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x20", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 32}, exp: []byte{0xde, 0x83, 0x0, 0xd1}}, - {name: "SUB/dst=R30/0xffffffffffffffe0", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -32}, exp: []byte{0xfb, 0x3, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x21", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 33}, exp: []byte{0xde, 0x87, 0x0, 0xd1}}, - {name: "SUB/dst=R30/0xffffffffffffffdf", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -33}, exp: []byte{0x1b, 0x4, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x1f", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 31}, exp: []byte{0xde, 0x7f, 0x0, 0xd1}}, - {name: "SUB/dst=R30/0xffffffffffffffe1", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -31}, exp: []byte{0xdb, 0x3, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x2f", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 47}, exp: []byte{0xde, 0xbf, 0x0, 0xd1}}, - {name: "SUB/dst=R30/0xffffffffffffffd1", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -47}, exp: []byte{0xdb, 0x5, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x40", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 64}, exp: []byte{0xde, 0x3, 0x1, 0xd1}}, - {name: "SUB/dst=R30/0xffffffffffffffc0", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -64}, exp: []byte{0xfb, 0x7, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x41", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 65}, exp: []byte{0xde, 0x7, 0x1, 0xd1}}, - {name: "SUB/dst=R30/0xffffffffffffffbf", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -65}, exp: []byte{0x1b, 0x8, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x3f", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 63}, exp: []byte{0xde, 0xff, 0x0, 0xd1}}, - {name: "SUB/dst=R30/0xffffffffffffffc1", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -63}, exp: []byte{0xdb, 0x7, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x4f", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 79}, exp: []byte{0xde, 0x3f, 0x1, 0xd1}}, - {name: "SUB/dst=R30/0xffffffffffffffb1", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -79}, exp: []byte{0xdb, 0x9, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x1ffe", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 8190}, exp: []byte{0xdb, 0xff, 0x83, 0xd2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xffffffffffffe002", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -8190}, exp: []byte{0xbb, 0xff, 0x83, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x1ffd", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 8189}, exp: []byte{0xbb, 0xff, 0x83, 0xd2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xffffffffffffe003", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -8189}, exp: []byte{0x9b, 0xff, 0x83, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x1fff", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 8191}, exp: []byte{0xfb, 0xff, 0x83, 0xd2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xffffffffffffe001", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -8191}, exp: []byte{0xdb, 0xff, 0x83, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x0", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 0}, exp: []byte{0xde, 0x3, 0x1f, 0xcb}}, - {name: "SUB/dst=R30/0x1", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 1}, exp: []byte{0xde, 0x7, 0x0, 0xd1}}, - {name: "SUB/dst=R30/0xffffffffffffffff", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -1}, exp: []byte{0x1b, 0x0, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xffffffffffffffff", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -1}, exp: []byte{0x1b, 0x0, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x1", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 1}, exp: []byte{0xde, 0x7, 0x0, 0xd1}}, - {name: "SUB/dst=R30/0x2", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 2}, exp: []byte{0xde, 0xb, 0x0, 0xd1}}, - {name: "SUB/dst=R30/0xfffffffffffffffe", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -2}, exp: []byte{0x3b, 0x0, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x3", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 3}, exp: []byte{0xde, 0xf, 0x0, 0xd1}}, - {name: "SUB/dst=R30/0xfffffffffffffffd", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -3}, exp: []byte{0x5b, 0x0, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xa", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 10}, exp: []byte{0xde, 0x2b, 0x0, 0xd1}}, - {name: "SUB/dst=R30/0xfffffffffffffff6", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -10}, exp: []byte{0x3b, 0x1, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xfffffffffffffff6", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -10}, exp: []byte{0x3b, 0x1, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xa", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 10}, exp: []byte{0xde, 0x2b, 0x0, 0xd1}}, - {name: "SUB/dst=R30/0x7b", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 123}, exp: []byte{0xde, 0xef, 0x1, 0xd1}}, - {name: "SUB/dst=R30/0xffffffffffffff85", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -123}, exp: []byte{0x5b, 0xf, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xffffffffffffff85", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -123}, exp: []byte{0x5b, 0xf, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x7b", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 123}, exp: []byte{0xde, 0xef, 0x1, 0xd1}}, - {name: "SUB/dst=R30/0x7fff", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 32767}, exp: []byte{0xfb, 0xff, 0x8f, 0xd2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xffffffffffff8001", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -32767}, exp: []byte{0xdb, 0xff, 0x8f, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x7fffffff", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 2147483647}, exp: []byte{0xfb, 0x7b, 0x40, 0xb2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xffffffff80000001", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -2147483647}, exp: []byte{0xfb, 0x87, 0x61, 0xb2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xffffffff", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 4294967295}, exp: []byte{0xfb, 0x7f, 0x40, 0xb2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xffffffff00000001", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -4294967295}, exp: []byte{0xfb, 0x83, 0x60, 0xb2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x4002", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 16386}, exp: []byte{0x5b, 0x0, 0x88, 0xd2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xffffffffffffbffe", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -16386}, exp: []byte{0x3b, 0x0, 0x88, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xffff0000", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 4294901760}, exp: []byte{0xfb, 0xff, 0xbf, 0xd2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xffffffff00010000", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -4294901760}, exp: []byte{0xfb, 0xff, 0x9f, 0x92, 0x3b, 0x0, 0xa0, 0xf2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xffff0001", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 4294901761}, exp: []byte{0x3b, 0x0, 0x80, 0xd2, 0xfb, 0xff, 0xbf, 0xf2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xffffffff0000ffff", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -4294901761}, exp: []byte{0xfb, 0xff, 0xbf, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xf00000f", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 251658255}, exp: []byte{0xfb, 0x1, 0x80, 0xd2, 0x1b, 0xe0, 0xa1, 0xf2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xfffffffff0fffff1", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -251658255}, exp: []byte{0xdb, 0x1, 0x80, 0x92, 0xfb, 0x1f, 0xbe, 0xf2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x7ffe", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 32766}, exp: []byte{0xdb, 0xff, 0x8f, 0xd2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xffffffffffff8002", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -32766}, exp: []byte{0xbb, 0xff, 0x8f, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x7ffffffe", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 2147483646}, exp: []byte{0xfb, 0x77, 0x7f, 0xb2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xffffffff80000002", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -2147483646}, exp: []byte{0xbb, 0xff, 0x9f, 0x92, 0x1b, 0x0, 0xb0, 0xf2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xfffffffe", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 4294967294}, exp: []byte{0xfb, 0x7b, 0x7f, 0xb2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xffffffff00000002", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -4294967294}, exp: []byte{0xbb, 0xff, 0x9f, 0x92, 0x1b, 0x0, 0xa0, 0xf2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x4001", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 16385}, exp: []byte{0x3b, 0x0, 0x88, 0xd2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xffffffffffffbfff", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -16385}, exp: []byte{0x1b, 0x0, 0x88, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xfffeffff", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 4294901759}, exp: []byte{0xfb, 0xff, 0x9f, 0xd2, 0xdb, 0xff, 0xbf, 0xf2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xffffffff00010001", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -4294901759}, exp: []byte{0xdb, 0xff, 0x9f, 0x92, 0x3b, 0x0, 0xa0, 0xf2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xffff0000", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 4294901760}, exp: []byte{0xfb, 0xff, 0xbf, 0xd2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xffffffff00010000", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -4294901760}, exp: []byte{0xfb, 0xff, 0x9f, 0x92, 0x3b, 0x0, 0xa0, 0xf2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xf00000e", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 251658254}, exp: []byte{0xdb, 0x1, 0x80, 0xd2, 0x1b, 0xe0, 0xa1, 0xf2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xfffffffff0fffff2", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -251658254}, exp: []byte{0xbb, 0x1, 0x80, 0x92, 0xfb, 0x1f, 0xbe, 0xf2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x8000", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 32768}, exp: []byte{0xde, 0x23, 0x40, 0xd1}}, - {name: "SUB/dst=R30/0xffffffffffff8000", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -32768}, exp: []byte{0xfb, 0xff, 0x8f, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x4009", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 16393}, exp: []byte{0x3b, 0x1, 0x88, 0xd2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xffffffffffffbff7", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -16393}, exp: []byte{0x1b, 0x1, 0x88, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xffeffff", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 268369919}, exp: []byte{0xfb, 0xff, 0x9f, 0xd2, 0xdb, 0xff, 0xa1, 0xf2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xfffffffff0010001", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -268369919}, exp: []byte{0xdb, 0xff, 0x9f, 0x92, 0x3b, 0x0, 0xbe, 0xf2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xffe0000", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 268304384}, exp: []byte{0xdb, 0xff, 0xa1, 0xd2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xfffffffff0020000", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -268304384}, exp: []byte{0xfb, 0xff, 0x9f, 0x92, 0x5b, 0x0, 0xbe, 0xf2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xe00000e", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 234881038}, exp: []byte{0xdb, 0x1, 0x80, 0xd2, 0x1b, 0xc0, 0xa1, 0xf2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xfffffffff1fffff2", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -234881038}, exp: []byte{0xbb, 0x1, 0x80, 0x92, 0xfb, 0x3f, 0xbe, 0xf2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x80010000", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 2147549184}, exp: []byte{0x3b, 0x0, 0xb0, 0xd2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xffffffff7fff0000", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -2147549184}, exp: []byte{0xfb, 0xff, 0x9f, 0x92, 0xfb, 0xff, 0xaf, 0xf2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x10002", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 65538}, exp: []byte{0xde, 0xb, 0x0, 0xd1, 0xde, 0x43, 0x40, 0xd1}}, - {name: "SUB/dst=R30/0xfffffffffffefffe", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -65538}, exp: []byte{0x3b, 0x0, 0x80, 0x92, 0xdb, 0xff, 0xbf, 0xf2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x100000000", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 4294967296}, exp: []byte{0x3b, 0x0, 0xc0, 0xd2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xffffffff00000000", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -4294967296}, exp: []byte{0xfb, 0x7f, 0x60, 0xb2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x400000000", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 17179869184}, exp: []byte{0x9b, 0x0, 0xc0, 0xd2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xfffffffc00000000", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -17179869184}, exp: []byte{0xfb, 0x77, 0x5e, 0xb2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x10000000000", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 1099511627776}, exp: []byte{0x1b, 0x20, 0xc0, 0xd2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xffffff0000000000", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -1099511627776}, exp: []byte{0xfb, 0x5f, 0x58, 0xb2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x100000001", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 4294967297}, exp: []byte{0xfb, 0x3, 0x0, 0xb2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xfffffffeffffffff", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -4294967297}, exp: []byte{0x3b, 0x0, 0xc0, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x400000001", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 17179869185}, exp: []byte{0x3b, 0x0, 0x80, 0xd2, 0x9b, 0x0, 0xc0, 0xf2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xfffffffbffffffff", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -17179869185}, exp: []byte{0x9b, 0x0, 0xc0, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x10000000001", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 1099511627777}, exp: []byte{0x3b, 0x0, 0x80, 0xd2, 0x1b, 0x20, 0xc0, 0xf2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xfffffeffffffffff", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -1099511627777}, exp: []byte{0x1b, 0x20, 0xc0, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xffffffff", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 4294967295}, exp: []byte{0xfb, 0x7f, 0x40, 0xb2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xffffffff00000001", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -4294967295}, exp: []byte{0xfb, 0x83, 0x60, 0xb2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x3ffffffff", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 17179869183}, exp: []byte{0xfb, 0x87, 0x40, 0xb2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xfffffffc00000001", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -17179869183}, exp: []byte{0xfb, 0x7b, 0x5e, 0xb2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xffffffffff", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 1099511627775}, exp: []byte{0xfb, 0x9f, 0x40, 0xb2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xffffff0000000001", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -1099511627775}, exp: []byte{0xfb, 0x63, 0x58, 0xb2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x10000000f", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 4294967311}, exp: []byte{0xfb, 0x1, 0x80, 0xd2, 0x3b, 0x0, 0xc0, 0xf2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xfffffffefffffff1", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -4294967311}, exp: []byte{0xdb, 0x1, 0x80, 0x92, 0xdb, 0xff, 0xdf, 0xf2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x40000000f", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 17179869199}, exp: []byte{0xfb, 0x1, 0x80, 0xd2, 0x9b, 0x0, 0xc0, 0xf2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xfffffffbfffffff1", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -17179869199}, exp: []byte{0xdb, 0x1, 0x80, 0x92, 0x7b, 0xff, 0xdf, 0xf2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x1000000000f", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 1099511627791}, exp: []byte{0xfb, 0x1, 0x80, 0xd2, 0x1b, 0x20, 0xc0, 0xf2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xfffffefffffffff1", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -1099511627791}, exp: []byte{0xdb, 0x1, 0x80, 0x92, 0xfb, 0xdf, 0xdf, 0xf2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xfffffff1", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 4294967281}, exp: []byte{0x3b, 0xfe, 0x9f, 0xd2, 0xfb, 0xff, 0xbf, 0xf2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xffffffff0000000f", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -4294967281}, exp: []byte{0xfb, 0x8f, 0x60, 0xb2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x3fffffff1", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 17179869169}, exp: []byte{0x3b, 0xfe, 0x9f, 0xd2, 0xfb, 0xff, 0xbf, 0xf2, 0x7b, 0x0, 0xc0, 0xf2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xfffffffc0000000f", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -17179869169}, exp: []byte{0xfb, 0x87, 0x5e, 0xb2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xfffffffff1", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 1099511627761}, exp: []byte{0x3b, 0xfe, 0x9f, 0xd2, 0xfb, 0xff, 0xbf, 0xf2, 0xfb, 0x1f, 0xc0, 0xf2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xffffff000000000f", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -1099511627761}, exp: []byte{0xfb, 0x6f, 0x58, 0xb2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x7fffffffffffffff", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 9223372036854775807}, exp: []byte{0x1b, 0x0, 0xf0, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x8000000000000001", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -9223372036854775807}, exp: []byte{0xfb, 0x7, 0x41, 0xb2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x8000000000000000", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -9223372036854775808}, exp: []byte{0x1b, 0x0, 0xf0, 0xd2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x8000000000000000", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -9223372036854775808}, exp: []byte{0x1b, 0x0, 0xf0, 0xd2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x40000001", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 1073741825}, exp: []byte{0x3b, 0x0, 0x80, 0xd2, 0x1b, 0x0, 0xa8, 0xf2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xffffffffbfffffff", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -1073741825}, exp: []byte{0x1b, 0x0, 0xa8, 0x92, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x7000000010000000", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 8070450532516364288}, exp: []byte{0x1b, 0x0, 0xa2, 0xd2, 0x1b, 0x0, 0xee, 0xf2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x8ffffffff0000000", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -8070450532516364288}, exp: []byte{0x1b, 0x0, 0xbe, 0xd2, 0xfb, 0xff, 0xdf, 0xf2, 0xfb, 0xff, 0xf1, 0xf2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x7000000100000000", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 8070450536542896128}, exp: []byte{0x3b, 0x0, 0xc0, 0xd2, 0x1b, 0x0, 0xee, 0xf2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x8fffffff00000000", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -8070450536542896128}, exp: []byte{0xfb, 0xff, 0xdf, 0xd2, 0xfb, 0xff, 0xf1, 0xf2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x7000100000000000", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 8070468124433973248}, exp: []byte{0x1b, 0x0, 0xc2, 0xd2, 0x1b, 0x0, 0xee, 0xf2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x8ffff00000000000", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -8070468124433973248}, exp: []byte{0x1b, 0x0, 0xde, 0xd2, 0xfb, 0xff, 0xf1, 0xf2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x154b4", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 87220}, exp: []byte{0xde, 0xd3, 0x12, 0xd1, 0xde, 0x57, 0x40, 0xd1}}, - {name: "SUB/dst=R30/0xfffffffffffeab4c", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -87220}, exp: []byte{0x7b, 0x96, 0x8a, 0x92, 0xdb, 0xff, 0xbf, 0xf2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x40008", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 262152}, exp: []byte{0xde, 0x23, 0x0, 0xd1, 0xde, 0x3, 0x41, 0xd1}}, - {name: "SUB/dst=R30/0xfffffffffffbfff8", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -262152}, exp: []byte{0xfb, 0x0, 0x80, 0x92, 0x7b, 0xff, 0xbf, 0xf2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xffff0000c466361f", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -281471681677793}, exp: []byte{0xfb, 0xc3, 0x86, 0xd2, 0xdb, 0x8c, 0xb8, 0xf2, 0xfb, 0xff, 0xff, 0xf2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xffff3b99c9e1", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 281471681677793}, exp: []byte{0x3b, 0x3c, 0x99, 0xd2, 0x3b, 0x73, 0xa7, 0xf2, 0xfb, 0xff, 0xdf, 0xf2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xc465c9ff", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 3295005183}, exp: []byte{0xfb, 0x3f, 0x99, 0xd2, 0xbb, 0x8c, 0xb8, 0xf2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xffffffff3b9a3601", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -3295005183}, exp: []byte{0xdb, 0x3f, 0x99, 0x92, 0x5b, 0x73, 0xa7, 0xf2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x89705f4136b4a598", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -8543223759426509416}, exp: []byte{0x1b, 0xb3, 0x94, 0xd2, 0x9b, 0xd6, 0xa6, 0xf2, 0x3b, 0xe8, 0xcb, 0xf2, 0x1b, 0x2e, 0xf1, 0xf2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x768fa0bec94b5a68", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 8543223759426509416}, exp: []byte{0x1b, 0x4d, 0x8b, 0xd2, 0x7b, 0x29, 0xb9, 0xf2, 0xdb, 0x17, 0xd4, 0xf2, 0xfb, 0xd1, 0xee, 0xf2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xffffffffc4653600", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -1000000000}, exp: []byte{0xfb, 0x3f, 0x99, 0x92, 0xbb, 0x8c, 0xb8, 0xf2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0x3b9aca00", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 1000000000}, exp: []byte{0x1b, 0x40, 0x99, 0xd2, 0x5b, 0x73, 0xa7, 0xf2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xffffff", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: 16777215}, exp: []byte{0xfb, 0x5f, 0x40, 0xb2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUB/dst=R30/0xffffffffff000001", n: &nodeImpl{instruction: SUB, dstReg: RegR30, srcConst: -16777215}, exp: []byte{0xfb, 0xa3, 0x68, 0xb2, 0xde, 0x3, 0x1b, 0xcb}}, - {name: "SUBS/dst=R30/0x1", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 1}, exp: []byte{0xde, 0x7, 0x0, 0xf1}}, - {name: "SUBS/dst=R30/0xffffffffffffffff", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -1}, exp: []byte{0x1b, 0x0, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xfff", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 4095}, exp: []byte{0xde, 0xff, 0x3f, 0xf1}}, - {name: "SUBS/dst=R30/0xfffffffffffff001", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -4095}, exp: []byte{0xdb, 0xff, 0x81, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xfff000", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 16773120}, exp: []byte{0xde, 0xff, 0x7f, 0xf1}}, - {name: "SUBS/dst=R30/0xffffffffff001000", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -16773120}, exp: []byte{0xfb, 0xff, 0x9d, 0x92, 0x1b, 0xe0, 0xbf, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x7b000", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 503808}, exp: []byte{0xde, 0xef, 0x41, 0xf1}}, - {name: "SUBS/dst=R30/0xfffffffffff85000", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -503808}, exp: []byte{0xfb, 0xff, 0x95, 0x92, 0x1b, 0xff, 0xbf, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x8001", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 32769}, exp: []byte{0x3b, 0x0, 0x90, 0xd2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xffffffffffff7fff", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -32769}, exp: []byte{0x1b, 0x0, 0x90, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x80010000", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 2147549184}, exp: []byte{0x3b, 0x0, 0xb0, 0xd2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xffffffff7fff0000", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -2147549184}, exp: []byte{0xfb, 0xff, 0x9f, 0x92, 0xfb, 0xff, 0xaf, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x800100000000", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 140741783322624}, exp: []byte{0x3b, 0x0, 0xd0, 0xd2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xffff7fff00000000", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -140741783322624}, exp: []byte{0xfb, 0xff, 0xcf, 0xd2, 0xfb, 0xff, 0xff, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xffffffffffff", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 281474976710655}, exp: []byte{0xfb, 0xff, 0xff, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xffff000000000001", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -281474976710655}, exp: []byte{0xfb, 0x43, 0x50, 0xb2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xffff0000ffffffff", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -281470681743361}, exp: []byte{0xfb, 0xff, 0xdf, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xffff00000001", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 281470681743361}, exp: []byte{0x3b, 0x0, 0x80, 0xd2, 0xfb, 0xff, 0xdf, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xffffffff80000001", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -2147483647}, exp: []byte{0xfb, 0x87, 0x61, 0xb2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x7fffffff", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 2147483647}, exp: []byte{0xfb, 0x7b, 0x40, 0xb2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xffff00000000ffff", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -281474976645121}, exp: []byte{0xfb, 0x7f, 0x50, 0xb2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xffffffff0001", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 281474976645121}, exp: []byte{0xdb, 0xff, 0x9f, 0x92, 0x1b, 0x0, 0xe0, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x100001", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 1048577}, exp: []byte{0x3b, 0x0, 0x80, 0xd2, 0x1b, 0x2, 0xa0, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xffffffffffefffff", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -1048577}, exp: []byte{0x1b, 0x2, 0xa0, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xfffff", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 1048575}, exp: []byte{0xfb, 0x4f, 0x40, 0xb2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xfffffffffff00001", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -1048575}, exp: []byte{0xfb, 0xb3, 0x6c, 0xb2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x800001", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 8388609}, exp: []byte{0x3b, 0x0, 0x80, 0xd2, 0x1b, 0x10, 0xa0, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xffffffffff7fffff", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -8388609}, exp: []byte{0x1b, 0x10, 0xa0, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x40000001", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 1073741825}, exp: []byte{0x3b, 0x0, 0x80, 0xd2, 0x1b, 0x0, 0xa8, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xffffffffbfffffff", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -1073741825}, exp: []byte{0x1b, 0x0, 0xa8, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x2", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 2}, exp: []byte{0xde, 0xb, 0x0, 0xf1}}, - {name: "SUBS/dst=R30/0xfffffffffffffffe", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -2}, exp: []byte{0x3b, 0x0, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x3", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 3}, exp: []byte{0xde, 0xf, 0x0, 0xf1}}, - {name: "SUBS/dst=R30/0xfffffffffffffffd", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -3}, exp: []byte{0x5b, 0x0, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x1", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 1}, exp: []byte{0xde, 0x7, 0x0, 0xf1}}, - {name: "SUBS/dst=R30/0xffffffffffffffff", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -1}, exp: []byte{0x1b, 0x0, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x11", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 17}, exp: []byte{0xde, 0x47, 0x0, 0xf1}}, - {name: "SUBS/dst=R30/0xffffffffffffffef", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -17}, exp: []byte{0x1b, 0x2, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x4", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 4}, exp: []byte{0xde, 0x13, 0x0, 0xf1}}, - {name: "SUBS/dst=R30/0xfffffffffffffffc", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -4}, exp: []byte{0x7b, 0x0, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x5", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 5}, exp: []byte{0xde, 0x17, 0x0, 0xf1}}, - {name: "SUBS/dst=R30/0xfffffffffffffffb", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -5}, exp: []byte{0x9b, 0x0, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x3", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 3}, exp: []byte{0xde, 0xf, 0x0, 0xf1}}, - {name: "SUBS/dst=R30/0xfffffffffffffffd", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -3}, exp: []byte{0x5b, 0x0, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x13", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 19}, exp: []byte{0xde, 0x4f, 0x0, 0xf1}}, - {name: "SUBS/dst=R30/0xffffffffffffffed", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -19}, exp: []byte{0x5b, 0x2, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x8", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 8}, exp: []byte{0xde, 0x23, 0x0, 0xf1}}, - {name: "SUBS/dst=R30/0xfffffffffffffff8", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -8}, exp: []byte{0xfb, 0x0, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x9", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 9}, exp: []byte{0xde, 0x27, 0x0, 0xf1}}, - {name: "SUBS/dst=R30/0xfffffffffffffff7", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -9}, exp: []byte{0x1b, 0x1, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x7", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 7}, exp: []byte{0xde, 0x1f, 0x0, 0xf1}}, - {name: "SUBS/dst=R30/0xfffffffffffffff9", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -7}, exp: []byte{0xdb, 0x0, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x17", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 23}, exp: []byte{0xde, 0x5f, 0x0, 0xf1}}, - {name: "SUBS/dst=R30/0xffffffffffffffe9", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -23}, exp: []byte{0xdb, 0x2, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x10", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 16}, exp: []byte{0xde, 0x43, 0x0, 0xf1}}, - {name: "SUBS/dst=R30/0xfffffffffffffff0", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -16}, exp: []byte{0xfb, 0x1, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x11", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 17}, exp: []byte{0xde, 0x47, 0x0, 0xf1}}, - {name: "SUBS/dst=R30/0xffffffffffffffef", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -17}, exp: []byte{0x1b, 0x2, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xf", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 15}, exp: []byte{0xde, 0x3f, 0x0, 0xf1}}, - {name: "SUBS/dst=R30/0xfffffffffffffff1", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -15}, exp: []byte{0xdb, 0x1, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x1f", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 31}, exp: []byte{0xde, 0x7f, 0x0, 0xf1}}, - {name: "SUBS/dst=R30/0xffffffffffffffe1", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -31}, exp: []byte{0xdb, 0x3, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x20", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 32}, exp: []byte{0xde, 0x83, 0x0, 0xf1}}, - {name: "SUBS/dst=R30/0xffffffffffffffe0", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -32}, exp: []byte{0xfb, 0x3, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x21", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 33}, exp: []byte{0xde, 0x87, 0x0, 0xf1}}, - {name: "SUBS/dst=R30/0xffffffffffffffdf", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -33}, exp: []byte{0x1b, 0x4, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x1f", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 31}, exp: []byte{0xde, 0x7f, 0x0, 0xf1}}, - {name: "SUBS/dst=R30/0xffffffffffffffe1", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -31}, exp: []byte{0xdb, 0x3, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x2f", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 47}, exp: []byte{0xde, 0xbf, 0x0, 0xf1}}, - {name: "SUBS/dst=R30/0xffffffffffffffd1", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -47}, exp: []byte{0xdb, 0x5, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x40", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 64}, exp: []byte{0xde, 0x3, 0x1, 0xf1}}, - {name: "SUBS/dst=R30/0xffffffffffffffc0", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -64}, exp: []byte{0xfb, 0x7, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x41", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 65}, exp: []byte{0xde, 0x7, 0x1, 0xf1}}, - {name: "SUBS/dst=R30/0xffffffffffffffbf", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -65}, exp: []byte{0x1b, 0x8, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x3f", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 63}, exp: []byte{0xde, 0xff, 0x0, 0xf1}}, - {name: "SUBS/dst=R30/0xffffffffffffffc1", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -63}, exp: []byte{0xdb, 0x7, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x4f", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 79}, exp: []byte{0xde, 0x3f, 0x1, 0xf1}}, - {name: "SUBS/dst=R30/0xffffffffffffffb1", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -79}, exp: []byte{0xdb, 0x9, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x1ffe", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 8190}, exp: []byte{0xdb, 0xff, 0x83, 0xd2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xffffffffffffe002", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -8190}, exp: []byte{0xbb, 0xff, 0x83, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x1ffd", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 8189}, exp: []byte{0xbb, 0xff, 0x83, 0xd2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xffffffffffffe003", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -8189}, exp: []byte{0x9b, 0xff, 0x83, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x1fff", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 8191}, exp: []byte{0xfb, 0xff, 0x83, 0xd2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xffffffffffffe001", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -8191}, exp: []byte{0xdb, 0xff, 0x83, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x0", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 0}, exp: []byte{0xde, 0x3, 0x1f, 0xeb}}, - {name: "SUBS/dst=R30/0x1", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 1}, exp: []byte{0xde, 0x7, 0x0, 0xf1}}, - {name: "SUBS/dst=R30/0xffffffffffffffff", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -1}, exp: []byte{0x1b, 0x0, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xffffffffffffffff", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -1}, exp: []byte{0x1b, 0x0, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x1", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 1}, exp: []byte{0xde, 0x7, 0x0, 0xf1}}, - {name: "SUBS/dst=R30/0x2", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 2}, exp: []byte{0xde, 0xb, 0x0, 0xf1}}, - {name: "SUBS/dst=R30/0xfffffffffffffffe", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -2}, exp: []byte{0x3b, 0x0, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x3", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 3}, exp: []byte{0xde, 0xf, 0x0, 0xf1}}, - {name: "SUBS/dst=R30/0xfffffffffffffffd", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -3}, exp: []byte{0x5b, 0x0, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xa", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 10}, exp: []byte{0xde, 0x2b, 0x0, 0xf1}}, - {name: "SUBS/dst=R30/0xfffffffffffffff6", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -10}, exp: []byte{0x3b, 0x1, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xfffffffffffffff6", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -10}, exp: []byte{0x3b, 0x1, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xa", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 10}, exp: []byte{0xde, 0x2b, 0x0, 0xf1}}, - {name: "SUBS/dst=R30/0x7b", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 123}, exp: []byte{0xde, 0xef, 0x1, 0xf1}}, - {name: "SUBS/dst=R30/0xffffffffffffff85", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -123}, exp: []byte{0x5b, 0xf, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xffffffffffffff85", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -123}, exp: []byte{0x5b, 0xf, 0x80, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x7b", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 123}, exp: []byte{0xde, 0xef, 0x1, 0xf1}}, - {name: "SUBS/dst=R30/0x7fff", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 32767}, exp: []byte{0xfb, 0xff, 0x8f, 0xd2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xffffffffffff8001", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -32767}, exp: []byte{0xdb, 0xff, 0x8f, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x7fffffff", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 2147483647}, exp: []byte{0xfb, 0x7b, 0x40, 0xb2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xffffffff80000001", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -2147483647}, exp: []byte{0xfb, 0x87, 0x61, 0xb2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xffffffff", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 4294967295}, exp: []byte{0xfb, 0x7f, 0x40, 0xb2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xffffffff00000001", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -4294967295}, exp: []byte{0xfb, 0x83, 0x60, 0xb2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x4002", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 16386}, exp: []byte{0x5b, 0x0, 0x88, 0xd2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xffffffffffffbffe", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -16386}, exp: []byte{0x3b, 0x0, 0x88, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xffff0000", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 4294901760}, exp: []byte{0xfb, 0xff, 0xbf, 0xd2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xffffffff00010000", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -4294901760}, exp: []byte{0xfb, 0xff, 0x9f, 0x92, 0x3b, 0x0, 0xa0, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xffff0001", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 4294901761}, exp: []byte{0x3b, 0x0, 0x80, 0xd2, 0xfb, 0xff, 0xbf, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xffffffff0000ffff", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -4294901761}, exp: []byte{0xfb, 0xff, 0xbf, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xf00000f", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 251658255}, exp: []byte{0xfb, 0x1, 0x80, 0xd2, 0x1b, 0xe0, 0xa1, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xfffffffff0fffff1", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -251658255}, exp: []byte{0xdb, 0x1, 0x80, 0x92, 0xfb, 0x1f, 0xbe, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x7ffe", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 32766}, exp: []byte{0xdb, 0xff, 0x8f, 0xd2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xffffffffffff8002", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -32766}, exp: []byte{0xbb, 0xff, 0x8f, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x7ffffffe", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 2147483646}, exp: []byte{0xfb, 0x77, 0x7f, 0xb2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xffffffff80000002", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -2147483646}, exp: []byte{0xbb, 0xff, 0x9f, 0x92, 0x1b, 0x0, 0xb0, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xfffffffe", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 4294967294}, exp: []byte{0xfb, 0x7b, 0x7f, 0xb2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xffffffff00000002", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -4294967294}, exp: []byte{0xbb, 0xff, 0x9f, 0x92, 0x1b, 0x0, 0xa0, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x4001", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 16385}, exp: []byte{0x3b, 0x0, 0x88, 0xd2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xffffffffffffbfff", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -16385}, exp: []byte{0x1b, 0x0, 0x88, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xfffeffff", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 4294901759}, exp: []byte{0xfb, 0xff, 0x9f, 0xd2, 0xdb, 0xff, 0xbf, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xffffffff00010001", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -4294901759}, exp: []byte{0xdb, 0xff, 0x9f, 0x92, 0x3b, 0x0, 0xa0, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xffff0000", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 4294901760}, exp: []byte{0xfb, 0xff, 0xbf, 0xd2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xffffffff00010000", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -4294901760}, exp: []byte{0xfb, 0xff, 0x9f, 0x92, 0x3b, 0x0, 0xa0, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xf00000e", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 251658254}, exp: []byte{0xdb, 0x1, 0x80, 0xd2, 0x1b, 0xe0, 0xa1, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xfffffffff0fffff2", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -251658254}, exp: []byte{0xbb, 0x1, 0x80, 0x92, 0xfb, 0x1f, 0xbe, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x8000", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 32768}, exp: []byte{0xde, 0x23, 0x40, 0xf1}}, - {name: "SUBS/dst=R30/0xffffffffffff8000", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -32768}, exp: []byte{0xfb, 0xff, 0x8f, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x4009", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 16393}, exp: []byte{0x3b, 0x1, 0x88, 0xd2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xffffffffffffbff7", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -16393}, exp: []byte{0x1b, 0x1, 0x88, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xffeffff", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 268369919}, exp: []byte{0xfb, 0xff, 0x9f, 0xd2, 0xdb, 0xff, 0xa1, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xfffffffff0010001", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -268369919}, exp: []byte{0xdb, 0xff, 0x9f, 0x92, 0x3b, 0x0, 0xbe, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xffe0000", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 268304384}, exp: []byte{0xdb, 0xff, 0xa1, 0xd2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xfffffffff0020000", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -268304384}, exp: []byte{0xfb, 0xff, 0x9f, 0x92, 0x5b, 0x0, 0xbe, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xe00000e", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 234881038}, exp: []byte{0xdb, 0x1, 0x80, 0xd2, 0x1b, 0xc0, 0xa1, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xfffffffff1fffff2", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -234881038}, exp: []byte{0xbb, 0x1, 0x80, 0x92, 0xfb, 0x3f, 0xbe, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x80010000", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 2147549184}, exp: []byte{0x3b, 0x0, 0xb0, 0xd2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xffffffff7fff0000", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -2147549184}, exp: []byte{0xfb, 0xff, 0x9f, 0x92, 0xfb, 0xff, 0xaf, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x10002", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 65538}, exp: []byte{0x5b, 0x0, 0x80, 0xd2, 0x3b, 0x0, 0xa0, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xfffffffffffefffe", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -65538}, exp: []byte{0x3b, 0x0, 0x80, 0x92, 0xdb, 0xff, 0xbf, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x100000000", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 4294967296}, exp: []byte{0x3b, 0x0, 0xc0, 0xd2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xffffffff00000000", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -4294967296}, exp: []byte{0xfb, 0x7f, 0x60, 0xb2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x400000000", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 17179869184}, exp: []byte{0x9b, 0x0, 0xc0, 0xd2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xfffffffc00000000", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -17179869184}, exp: []byte{0xfb, 0x77, 0x5e, 0xb2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x10000000000", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 1099511627776}, exp: []byte{0x1b, 0x20, 0xc0, 0xd2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xffffff0000000000", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -1099511627776}, exp: []byte{0xfb, 0x5f, 0x58, 0xb2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x100000001", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 4294967297}, exp: []byte{0xfb, 0x3, 0x0, 0xb2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xfffffffeffffffff", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -4294967297}, exp: []byte{0x3b, 0x0, 0xc0, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x400000001", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 17179869185}, exp: []byte{0x3b, 0x0, 0x80, 0xd2, 0x9b, 0x0, 0xc0, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xfffffffbffffffff", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -17179869185}, exp: []byte{0x9b, 0x0, 0xc0, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x10000000001", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 1099511627777}, exp: []byte{0x3b, 0x0, 0x80, 0xd2, 0x1b, 0x20, 0xc0, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xfffffeffffffffff", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -1099511627777}, exp: []byte{0x1b, 0x20, 0xc0, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xffffffff", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 4294967295}, exp: []byte{0xfb, 0x7f, 0x40, 0xb2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xffffffff00000001", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -4294967295}, exp: []byte{0xfb, 0x83, 0x60, 0xb2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x3ffffffff", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 17179869183}, exp: []byte{0xfb, 0x87, 0x40, 0xb2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xfffffffc00000001", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -17179869183}, exp: []byte{0xfb, 0x7b, 0x5e, 0xb2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xffffffffff", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 1099511627775}, exp: []byte{0xfb, 0x9f, 0x40, 0xb2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xffffff0000000001", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -1099511627775}, exp: []byte{0xfb, 0x63, 0x58, 0xb2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x10000000f", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 4294967311}, exp: []byte{0xfb, 0x1, 0x80, 0xd2, 0x3b, 0x0, 0xc0, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xfffffffefffffff1", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -4294967311}, exp: []byte{0xdb, 0x1, 0x80, 0x92, 0xdb, 0xff, 0xdf, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x40000000f", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 17179869199}, exp: []byte{0xfb, 0x1, 0x80, 0xd2, 0x9b, 0x0, 0xc0, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xfffffffbfffffff1", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -17179869199}, exp: []byte{0xdb, 0x1, 0x80, 0x92, 0x7b, 0xff, 0xdf, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x1000000000f", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 1099511627791}, exp: []byte{0xfb, 0x1, 0x80, 0xd2, 0x1b, 0x20, 0xc0, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xfffffefffffffff1", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -1099511627791}, exp: []byte{0xdb, 0x1, 0x80, 0x92, 0xfb, 0xdf, 0xdf, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xfffffff1", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 4294967281}, exp: []byte{0x3b, 0xfe, 0x9f, 0xd2, 0xfb, 0xff, 0xbf, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xffffffff0000000f", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -4294967281}, exp: []byte{0xfb, 0x8f, 0x60, 0xb2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x3fffffff1", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 17179869169}, exp: []byte{0x3b, 0xfe, 0x9f, 0xd2, 0xfb, 0xff, 0xbf, 0xf2, 0x7b, 0x0, 0xc0, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xfffffffc0000000f", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -17179869169}, exp: []byte{0xfb, 0x87, 0x5e, 0xb2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xfffffffff1", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 1099511627761}, exp: []byte{0x3b, 0xfe, 0x9f, 0xd2, 0xfb, 0xff, 0xbf, 0xf2, 0xfb, 0x1f, 0xc0, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xffffff000000000f", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -1099511627761}, exp: []byte{0xfb, 0x6f, 0x58, 0xb2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x7fffffffffffffff", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 9223372036854775807}, exp: []byte{0x1b, 0x0, 0xf0, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x8000000000000001", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -9223372036854775807}, exp: []byte{0xfb, 0x7, 0x41, 0xb2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x8000000000000000", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -9223372036854775808}, exp: []byte{0x1b, 0x0, 0xf0, 0xd2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x8000000000000000", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -9223372036854775808}, exp: []byte{0x1b, 0x0, 0xf0, 0xd2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x40000001", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 1073741825}, exp: []byte{0x3b, 0x0, 0x80, 0xd2, 0x1b, 0x0, 0xa8, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xffffffffbfffffff", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -1073741825}, exp: []byte{0x1b, 0x0, 0xa8, 0x92, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x7000000010000000", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 8070450532516364288}, exp: []byte{0x1b, 0x0, 0xa2, 0xd2, 0x1b, 0x0, 0xee, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x8ffffffff0000000", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -8070450532516364288}, exp: []byte{0x1b, 0x0, 0xbe, 0xd2, 0xfb, 0xff, 0xdf, 0xf2, 0xfb, 0xff, 0xf1, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x7000000100000000", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 8070450536542896128}, exp: []byte{0x3b, 0x0, 0xc0, 0xd2, 0x1b, 0x0, 0xee, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x8fffffff00000000", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -8070450536542896128}, exp: []byte{0xfb, 0xff, 0xdf, 0xd2, 0xfb, 0xff, 0xf1, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x7000100000000000", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 8070468124433973248}, exp: []byte{0x1b, 0x0, 0xc2, 0xd2, 0x1b, 0x0, 0xee, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x8ffff00000000000", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -8070468124433973248}, exp: []byte{0x1b, 0x0, 0xde, 0xd2, 0xfb, 0xff, 0xf1, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x154b4", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 87220}, exp: []byte{0x9b, 0x96, 0x8a, 0xd2, 0x3b, 0x0, 0xa0, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xfffffffffffeab4c", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -87220}, exp: []byte{0x7b, 0x96, 0x8a, 0x92, 0xdb, 0xff, 0xbf, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x40008", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 262152}, exp: []byte{0x1b, 0x1, 0x80, 0xd2, 0x9b, 0x0, 0xa0, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xfffffffffffbfff8", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -262152}, exp: []byte{0xfb, 0x0, 0x80, 0x92, 0x7b, 0xff, 0xbf, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xffff0000c466361f", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -281471681677793}, exp: []byte{0xfb, 0xc3, 0x86, 0xd2, 0xdb, 0x8c, 0xb8, 0xf2, 0xfb, 0xff, 0xff, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xffff3b99c9e1", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 281471681677793}, exp: []byte{0x3b, 0x3c, 0x99, 0xd2, 0x3b, 0x73, 0xa7, 0xf2, 0xfb, 0xff, 0xdf, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xc465c9ff", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 3295005183}, exp: []byte{0xfb, 0x3f, 0x99, 0xd2, 0xbb, 0x8c, 0xb8, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xffffffff3b9a3601", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -3295005183}, exp: []byte{0xdb, 0x3f, 0x99, 0x92, 0x5b, 0x73, 0xa7, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x89705f4136b4a598", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -8543223759426509416}, exp: []byte{0x1b, 0xb3, 0x94, 0xd2, 0x9b, 0xd6, 0xa6, 0xf2, 0x3b, 0xe8, 0xcb, 0xf2, 0x1b, 0x2e, 0xf1, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x768fa0bec94b5a68", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 8543223759426509416}, exp: []byte{0x1b, 0x4d, 0x8b, 0xd2, 0x7b, 0x29, 0xb9, 0xf2, 0xdb, 0x17, 0xd4, 0xf2, 0xfb, 0xd1, 0xee, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xffffffffc4653600", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -1000000000}, exp: []byte{0xfb, 0x3f, 0x99, 0x92, 0xbb, 0x8c, 0xb8, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0x3b9aca00", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 1000000000}, exp: []byte{0x1b, 0x40, 0x99, 0xd2, 0x5b, 0x73, 0xa7, 0xf2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xffffff", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: 16777215}, exp: []byte{0xfb, 0x5f, 0x40, 0xb2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "SUBS/dst=R30/0xffffffffff000001", n: &nodeImpl{instruction: SUBS, dstReg: RegR30, srcConst: -16777215}, exp: []byte{0xfb, 0xa3, 0x68, 0xb2, 0xde, 0x3, 0x1b, 0xeb}}, - {name: "MOVW/dst=R30/0x2", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 2}, exp: []byte{0xfe, 0x3, 0x1f, 0x32}}, - {name: "MOVW/dst=R30/0xfffffffffffffffe", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -2}, exp: []byte{0x3e, 0x0, 0x80, 0x12}}, - {name: "MOVW/dst=R30/0x3", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 3}, exp: []byte{0xfe, 0x7, 0x0, 0x32}}, - {name: "MOVW/dst=R30/0xfffffffffffffffd", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -3}, exp: []byte{0x5e, 0x0, 0x80, 0x12}}, - {name: "MOVW/dst=R30/0x1", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 1}, exp: []byte{0xfe, 0x3, 0x0, 0x32}}, - {name: "MOVW/dst=R30/0xffffffffffffffff", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -1}, exp: []byte{0x1e, 0x0, 0x80, 0x12}}, - {name: "MOVW/dst=R30/0x11", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 17}, exp: []byte{0x3e, 0x2, 0x80, 0x52}}, - {name: "MOVW/dst=R30/0xffffffffffffffef", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -17}, exp: []byte{0x1e, 0x2, 0x80, 0x12}}, - {name: "MOVW/dst=R30/0x4", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 4}, exp: []byte{0xfe, 0x3, 0x1e, 0x32}}, - {name: "MOVW/dst=R30/0xfffffffffffffffc", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -4}, exp: []byte{0x7e, 0x0, 0x80, 0x12}}, - {name: "MOVW/dst=R30/0x5", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 5}, exp: []byte{0xbe, 0x0, 0x80, 0x52}}, - {name: "MOVW/dst=R30/0xfffffffffffffffb", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -5}, exp: []byte{0x9e, 0x0, 0x80, 0x12}}, - {name: "MOVW/dst=R30/0x3", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 3}, exp: []byte{0xfe, 0x7, 0x0, 0x32}}, - {name: "MOVW/dst=R30/0xfffffffffffffffd", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -3}, exp: []byte{0x5e, 0x0, 0x80, 0x12}}, - {name: "MOVW/dst=R30/0x13", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 19}, exp: []byte{0x7e, 0x2, 0x80, 0x52}}, - {name: "MOVW/dst=R30/0xffffffffffffffed", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -19}, exp: []byte{0x5e, 0x2, 0x80, 0x12}}, - {name: "MOVW/dst=R30/0x8", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 8}, exp: []byte{0xfe, 0x3, 0x1d, 0x32}}, - {name: "MOVW/dst=R30/0xfffffffffffffff8", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -8}, exp: []byte{0xfe, 0x0, 0x80, 0x12}}, - {name: "MOVW/dst=R30/0x9", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 9}, exp: []byte{0x3e, 0x1, 0x80, 0x52}}, - {name: "MOVW/dst=R30/0xfffffffffffffff7", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -9}, exp: []byte{0x1e, 0x1, 0x80, 0x12}}, - {name: "MOVW/dst=R30/0x7", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 7}, exp: []byte{0xfe, 0xb, 0x0, 0x32}}, - {name: "MOVW/dst=R30/0xfffffffffffffff9", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -7}, exp: []byte{0xde, 0x0, 0x80, 0x12}}, - {name: "MOVW/dst=R30/0x17", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 23}, exp: []byte{0xfe, 0x2, 0x80, 0x52}}, - {name: "MOVW/dst=R30/0xffffffffffffffe9", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -23}, exp: []byte{0xde, 0x2, 0x80, 0x12}}, - {name: "MOVW/dst=R30/0x10", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 16}, exp: []byte{0xfe, 0x3, 0x1c, 0x32}}, - {name: "MOVW/dst=R30/0xfffffffffffffff0", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -16}, exp: []byte{0xfe, 0x1, 0x80, 0x12}}, - {name: "MOVW/dst=R30/0x11", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 17}, exp: []byte{0x3e, 0x2, 0x80, 0x52}}, - {name: "MOVW/dst=R30/0xffffffffffffffef", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -17}, exp: []byte{0x1e, 0x2, 0x80, 0x12}}, - {name: "MOVW/dst=R30/0xf", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 15}, exp: []byte{0xfe, 0xf, 0x0, 0x32}}, - {name: "MOVW/dst=R30/0xfffffffffffffff1", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -15}, exp: []byte{0xde, 0x1, 0x80, 0x12}}, - {name: "MOVW/dst=R30/0x1f", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 31}, exp: []byte{0xfe, 0x13, 0x0, 0x32}}, - {name: "MOVW/dst=R30/0xffffffffffffffe1", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -31}, exp: []byte{0xde, 0x3, 0x80, 0x12}}, - {name: "MOVW/dst=R30/0x20", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 32}, exp: []byte{0xfe, 0x3, 0x1b, 0x32}}, - {name: "MOVW/dst=R30/0xffffffffffffffe0", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -32}, exp: []byte{0xfe, 0x3, 0x80, 0x12}}, - {name: "MOVW/dst=R30/0x21", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 33}, exp: []byte{0x3e, 0x4, 0x80, 0x52}}, - {name: "MOVW/dst=R30/0xffffffffffffffdf", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -33}, exp: []byte{0x1e, 0x4, 0x80, 0x12}}, - {name: "MOVW/dst=R30/0x1f", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 31}, exp: []byte{0xfe, 0x13, 0x0, 0x32}}, - {name: "MOVW/dst=R30/0xffffffffffffffe1", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -31}, exp: []byte{0xde, 0x3, 0x80, 0x12}}, - {name: "MOVW/dst=R30/0x2f", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 47}, exp: []byte{0xfe, 0x5, 0x80, 0x52}}, - {name: "MOVW/dst=R30/0xffffffffffffffd1", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -47}, exp: []byte{0xde, 0x5, 0x80, 0x12}}, - {name: "MOVW/dst=R30/0x40", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 64}, exp: []byte{0xfe, 0x3, 0x1a, 0x32}}, - {name: "MOVW/dst=R30/0xffffffffffffffc0", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -64}, exp: []byte{0xfe, 0x7, 0x80, 0x12}}, - {name: "MOVW/dst=R30/0x41", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 65}, exp: []byte{0x3e, 0x8, 0x80, 0x52}}, - {name: "MOVW/dst=R30/0xffffffffffffffbf", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -65}, exp: []byte{0x1e, 0x8, 0x80, 0x12}}, - {name: "MOVW/dst=R30/0x3f", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 63}, exp: []byte{0xfe, 0x17, 0x0, 0x32}}, - {name: "MOVW/dst=R30/0xffffffffffffffc1", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -63}, exp: []byte{0xde, 0x7, 0x80, 0x12}}, - {name: "MOVW/dst=R30/0x4f", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 79}, exp: []byte{0xfe, 0x9, 0x80, 0x52}}, - {name: "MOVW/dst=R30/0xffffffffffffffb1", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -79}, exp: []byte{0xde, 0x9, 0x80, 0x12}}, - {name: "MOVW/dst=R30/0x1ffe", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 8190}, exp: []byte{0xde, 0xff, 0x83, 0x52}}, - {name: "MOVW/dst=R30/0xffffffffffffe002", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -8190}, exp: []byte{0xbe, 0xff, 0x83, 0x12}}, - {name: "MOVW/dst=R30/0x1ffd", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 8189}, exp: []byte{0xbe, 0xff, 0x83, 0x52}}, - {name: "MOVW/dst=R30/0xffffffffffffe003", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -8189}, exp: []byte{0x9e, 0xff, 0x83, 0x12}}, - {name: "MOVW/dst=R30/0x1fff", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 8191}, exp: []byte{0xfe, 0xff, 0x83, 0x52}}, - {name: "MOVW/dst=R30/0xffffffffffffe001", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -8191}, exp: []byte{0xde, 0xff, 0x83, 0x12}}, - {name: "MOVW/dst=R30/0x0", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 0}, exp: []byte{0xfe, 0x3, 0x1f, 0x2a}}, - {name: "MOVW/dst=R30/0x1", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 1}, exp: []byte{0xfe, 0x3, 0x0, 0x32}}, - {name: "MOVW/dst=R30/0xffffffffffffffff", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -1}, exp: []byte{0x1e, 0x0, 0x80, 0x12}}, - {name: "MOVW/dst=R30/0xffffffffffffffff", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -1}, exp: []byte{0x1e, 0x0, 0x80, 0x12}}, - {name: "MOVW/dst=R30/0x1", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 1}, exp: []byte{0xfe, 0x3, 0x0, 0x32}}, - {name: "MOVW/dst=R30/0x2", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 2}, exp: []byte{0xfe, 0x3, 0x1f, 0x32}}, - {name: "MOVW/dst=R30/0xfffffffffffffffe", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -2}, exp: []byte{0x3e, 0x0, 0x80, 0x12}}, - {name: "MOVW/dst=R30/0x3", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 3}, exp: []byte{0xfe, 0x7, 0x0, 0x32}}, - {name: "MOVW/dst=R30/0xfffffffffffffffd", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -3}, exp: []byte{0x5e, 0x0, 0x80, 0x12}}, - {name: "MOVW/dst=R30/0xa", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 10}, exp: []byte{0x5e, 0x1, 0x80, 0x52}}, - {name: "MOVW/dst=R30/0xfffffffffffffff6", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -10}, exp: []byte{0x3e, 0x1, 0x80, 0x12}}, - {name: "MOVW/dst=R30/0xfffffffffffffff6", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -10}, exp: []byte{0x3e, 0x1, 0x80, 0x12}}, - {name: "MOVW/dst=R30/0xa", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 10}, exp: []byte{0x5e, 0x1, 0x80, 0x52}}, - {name: "MOVW/dst=R30/0x7b", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 123}, exp: []byte{0x7e, 0xf, 0x80, 0x52}}, - {name: "MOVW/dst=R30/0xffffffffffffff85", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -123}, exp: []byte{0x5e, 0xf, 0x80, 0x12}}, - {name: "MOVW/dst=R30/0xffffffffffffff85", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -123}, exp: []byte{0x5e, 0xf, 0x80, 0x12}}, - {name: "MOVW/dst=R30/0x7b", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 123}, exp: []byte{0x7e, 0xf, 0x80, 0x52}}, - {name: "MOVW/dst=R30/0x7fff", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 32767}, exp: []byte{0xfe, 0xff, 0x8f, 0x52}}, - {name: "MOVW/dst=R30/0xffffffffffff8001", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -32767}, exp: []byte{0xde, 0xff, 0x8f, 0x12}}, - {name: "MOVW/dst=R30/0x7fffffff", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 2147483647}, exp: []byte{0x1e, 0x0, 0xb0, 0x12}}, - {name: "MOVW/dst=R30/0xffffffff80000001", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -2147483647}, exp: []byte{0xfe, 0x87, 0x1, 0x32}}, - {name: "MOVW/dst=R30/0xffffffff", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 4294967295}, exp: []byte{0x1e, 0x0, 0x80, 0x12}}, - {name: "MOVW/dst=R30/0xffffffff00000001", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -4294967295}, exp: []byte{0xfe, 0x83, 0x0, 0x32}}, - {name: "MOVW/dst=R30/0x4002", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 16386}, exp: []byte{0x5e, 0x0, 0x88, 0x52}}, - {name: "MOVW/dst=R30/0xffffffffffffbffe", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -16386}, exp: []byte{0x3e, 0x0, 0x88, 0x12}}, - {name: "MOVW/dst=R30/0xffff0000", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 4294901760}, exp: []byte{0xfe, 0xff, 0xbf, 0x52}}, - {name: "MOVW/dst=R30/0xffffffff00010000", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -4294901760}, exp: []byte{0x3e, 0x0, 0xa0, 0x52}}, - {name: "MOVW/dst=R30/0xffff0001", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 4294901761}, exp: []byte{0xde, 0xff, 0x9f, 0x12}}, - {name: "MOVW/dst=R30/0xffffffff0000ffff", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -4294901761}, exp: []byte{0xfe, 0xff, 0x9f, 0x52}}, - {name: "MOVW/dst=R30/0xf00000f", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 251658255}, exp: []byte{0xfe, 0x1, 0x80, 0x52, 0x1e, 0xe0, 0xa1, 0x72}}, - {name: "MOVW/dst=R30/0xfffffffff0fffff1", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -251658255}, exp: []byte{0x3e, 0xfe, 0x9f, 0x52, 0xfe, 0x1f, 0xbe, 0x72}}, - {name: "MOVW/dst=R30/0x7ffe", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 32766}, exp: []byte{0xde, 0xff, 0x8f, 0x52}}, - {name: "MOVW/dst=R30/0xffffffffffff8002", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -32766}, exp: []byte{0xbe, 0xff, 0x8f, 0x12}}, - {name: "MOVW/dst=R30/0x7ffffffe", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 2147483646}, exp: []byte{0xfe, 0x77, 0x1f, 0x32}}, - {name: "MOVW/dst=R30/0xffffffff80000002", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -2147483646}, exp: []byte{0x5e, 0x0, 0x80, 0x52, 0x1e, 0x0, 0xb0, 0x72}}, - {name: "MOVW/dst=R30/0xfffffffe", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 4294967294}, exp: []byte{0x3e, 0x0, 0x80, 0x12}}, - {name: "MOVW/dst=R30/0xffffffff00000002", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -4294967294}, exp: []byte{0x5e, 0x0, 0x80, 0x52}}, - {name: "MOVW/dst=R30/0x4001", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 16385}, exp: []byte{0x3e, 0x0, 0x88, 0x52}}, - {name: "MOVW/dst=R30/0xffffffffffffbfff", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -16385}, exp: []byte{0x1e, 0x0, 0x88, 0x12}}, - {name: "MOVW/dst=R30/0xfffeffff", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 4294901759}, exp: []byte{0x3e, 0x0, 0xa0, 0x12}}, - {name: "MOVW/dst=R30/0xffffffff00010001", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -4294901759}, exp: []byte{0x3e, 0x0, 0x80, 0x52, 0x3e, 0x0, 0xa0, 0x72}}, - {name: "MOVW/dst=R30/0xffff0000", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 4294901760}, exp: []byte{0xfe, 0xff, 0xbf, 0x52}}, - {name: "MOVW/dst=R30/0xffffffff00010000", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -4294901760}, exp: []byte{0x3e, 0x0, 0xa0, 0x52}}, - {name: "MOVW/dst=R30/0xf00000e", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 251658254}, exp: []byte{0xde, 0x1, 0x80, 0x52, 0x1e, 0xe0, 0xa1, 0x72}}, - {name: "MOVW/dst=R30/0xfffffffff0fffff2", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -251658254}, exp: []byte{0x5e, 0xfe, 0x9f, 0x52, 0xfe, 0x1f, 0xbe, 0x72}}, - {name: "MOVW/dst=R30/0x8000", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 32768}, exp: []byte{0xfe, 0x3, 0x11, 0x32}}, - {name: "MOVW/dst=R30/0xffffffffffff8000", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -32768}, exp: []byte{0xfe, 0xff, 0x8f, 0x12}}, - {name: "MOVW/dst=R30/0x4009", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 16393}, exp: []byte{0x3e, 0x1, 0x88, 0x52}}, - {name: "MOVW/dst=R30/0xffffffffffffbff7", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -16393}, exp: []byte{0x1e, 0x1, 0x88, 0x12}}, - {name: "MOVW/dst=R30/0xffeffff", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 268369919}, exp: []byte{0x3e, 0x0, 0xbe, 0x12}}, - {name: "MOVW/dst=R30/0xfffffffff0010001", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -268369919}, exp: []byte{0x3e, 0x0, 0x80, 0x52, 0x3e, 0x0, 0xbe, 0x72}}, - {name: "MOVW/dst=R30/0xffe0000", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 268304384}, exp: []byte{0xde, 0xff, 0xa1, 0x52}}, - {name: "MOVW/dst=R30/0xfffffffff0020000", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -268304384}, exp: []byte{0x5e, 0x0, 0xbe, 0x52}}, - {name: "MOVW/dst=R30/0xe00000e", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 234881038}, exp: []byte{0xde, 0x1, 0x80, 0x52, 0x1e, 0xc0, 0xa1, 0x72}}, - {name: "MOVW/dst=R30/0xfffffffff1fffff2", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -234881038}, exp: []byte{0x5e, 0xfe, 0x9f, 0x52, 0xfe, 0x3f, 0xbe, 0x72}}, - {name: "MOVW/dst=R30/0x80010000", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 2147549184}, exp: []byte{0x3e, 0x0, 0xb0, 0x52}}, - {name: "MOVW/dst=R30/0xffffffff7fff0000", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -2147549184}, exp: []byte{0xfe, 0xff, 0xaf, 0x52}}, - {name: "MOVW/dst=R30/0x10002", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 65538}, exp: []byte{0x5e, 0x0, 0x80, 0x52, 0x3e, 0x0, 0xa0, 0x72}}, - {name: "MOVW/dst=R30/0xfffffffffffefffe", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -65538}, exp: []byte{0xde, 0xff, 0x9f, 0x52, 0xde, 0xff, 0xbf, 0x72}}, - {name: "MOVW/dst=R30/0x40000000", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 1073741824}, exp: []byte{0x1e, 0x0, 0xa8, 0x52}}, - {name: "MOVW/dst=R30/0xffffffffc0000000", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -1073741824}, exp: []byte{0x1e, 0x0, 0xb8, 0x52}}, - {name: "MOVW/dst=R30/0x40000001", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 1073741825}, exp: []byte{0x3e, 0x0, 0x80, 0x52, 0x1e, 0x0, 0xa8, 0x72}}, - {name: "MOVW/dst=R30/0xffffffffbfffffff", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -1073741825}, exp: []byte{0x1e, 0x0, 0xa8, 0x12}}, - {name: "MOVW/dst=R30/0x3fffffff", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 1073741823}, exp: []byte{0x1e, 0x0, 0xb8, 0x12}}, - {name: "MOVW/dst=R30/0xffffffffc0000001", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -1073741823}, exp: []byte{0xfe, 0x8b, 0x2, 0x32}}, - {name: "MOVW/dst=R30/0x4000000f", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 1073741839}, exp: []byte{0xfe, 0x1, 0x80, 0x52, 0x1e, 0x0, 0xa8, 0x72}}, - {name: "MOVW/dst=R30/0xffffffffbffffff1", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -1073741839}, exp: []byte{0x3e, 0xfe, 0x9f, 0x52, 0xfe, 0xff, 0xb7, 0x72}}, - {name: "MOVW/dst=R30/0x3ffffff1", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 1073741809}, exp: []byte{0x3e, 0xfe, 0x9f, 0x52, 0xfe, 0xff, 0xa7, 0x72}}, - {name: "MOVW/dst=R30/0xffffffffc000000f", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -1073741809}, exp: []byte{0xfe, 0x97, 0x2, 0x32}}, - {name: "MOVW/dst=R30/0x7fffffffffffffff", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 9223372036854775807}, exp: []byte{0x1e, 0x0, 0x80, 0x12}}, - {name: "MOVW/dst=R30/0x8000000000000001", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -9223372036854775807}, exp: []byte{0xfe, 0x7, 0x1, 0x32}}, - {name: "MOVW/dst=R30/0xffffffffc0000000", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: -1073741824}, exp: []byte{0x1e, 0x0, 0xb8, 0x52}}, - {name: "MOVW/dst=R30/0x40000000", n: &nodeImpl{instruction: MOVW, dstReg: RegR30, srcConst: 1073741824}, exp: []byte{0x1e, 0x0, 0xa8, 0x52}}, - {name: "MOVD/dst=R30/0x1", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 1}, exp: []byte{0xfe, 0x3, 0x40, 0xb2}}, - {name: "MOVD/dst=R30/0xffffffffffffffff", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -1}, exp: []byte{0x1e, 0x0, 0x80, 0x92}}, - {name: "MOVD/dst=R30/0xfff", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 4095}, exp: []byte{0xfe, 0x2f, 0x40, 0xb2}}, - {name: "MOVD/dst=R30/0xfffffffffffff001", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -4095}, exp: []byte{0xde, 0xff, 0x81, 0x92}}, - {name: "MOVD/dst=R30/0xfff000", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 16773120}, exp: []byte{0xfe, 0x2f, 0x74, 0xb2}}, - {name: "MOVD/dst=R30/0xffffffffff001000", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -16773120}, exp: []byte{0xfe, 0xff, 0x9d, 0x92, 0x1e, 0xe0, 0xbf, 0xf2}}, - {name: "MOVD/dst=R30/0x7b000", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 503808}, exp: []byte{0x1e, 0x0, 0x96, 0xd2, 0xfe, 0x0, 0xa0, 0xf2}}, - {name: "MOVD/dst=R30/0xfffffffffff85000", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -503808}, exp: []byte{0xfe, 0xff, 0x95, 0x92, 0x1e, 0xff, 0xbf, 0xf2}}, - {name: "MOVD/dst=R30/0x8001", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 32769}, exp: []byte{0x3e, 0x0, 0x90, 0xd2}}, - {name: "MOVD/dst=R30/0xffffffffffff7fff", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -32769}, exp: []byte{0x1e, 0x0, 0x90, 0x92}}, - {name: "MOVD/dst=R30/0x80010000", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 2147549184}, exp: []byte{0x3e, 0x0, 0xb0, 0xd2}}, - {name: "MOVD/dst=R30/0xffffffff7fff0000", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -2147549184}, exp: []byte{0xfe, 0xff, 0x9f, 0x92, 0xfe, 0xff, 0xaf, 0xf2}}, - {name: "MOVD/dst=R30/0x800100000000", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 140741783322624}, exp: []byte{0x3e, 0x0, 0xd0, 0xd2}}, - {name: "MOVD/dst=R30/0xffff7fff00000000", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -140741783322624}, exp: []byte{0xfe, 0xff, 0xcf, 0xd2, 0xfe, 0xff, 0xff, 0xf2}}, - {name: "MOVD/dst=R30/0xffffffffffff", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 281474976710655}, exp: []byte{0xfe, 0xff, 0xff, 0x92}}, - {name: "MOVD/dst=R30/0xffff000000000001", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -281474976710655}, exp: []byte{0xfe, 0x43, 0x50, 0xb2}}, - {name: "MOVD/dst=R30/0xffff0000ffffffff", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -281470681743361}, exp: []byte{0xfe, 0xff, 0xdf, 0x92}}, - {name: "MOVD/dst=R30/0xffff00000001", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 281470681743361}, exp: []byte{0x3e, 0x0, 0x80, 0xd2, 0xfe, 0xff, 0xdf, 0xf2}}, - {name: "MOVD/dst=R30/0xffffffff80000001", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -2147483647}, exp: []byte{0xfe, 0x87, 0x61, 0xb2}}, - {name: "MOVD/dst=R30/0x7fffffff", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 2147483647}, exp: []byte{0xfe, 0x7b, 0x40, 0xb2}}, - {name: "MOVD/dst=R30/0xffff00000000ffff", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -281474976645121}, exp: []byte{0xfe, 0x7f, 0x50, 0xb2}}, - {name: "MOVD/dst=R30/0xffffffff0001", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 281474976645121}, exp: []byte{0xde, 0xff, 0x9f, 0x92, 0x1e, 0x0, 0xe0, 0xf2}}, - {name: "MOVD/dst=R30/0x100001", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 1048577}, exp: []byte{0x3e, 0x0, 0x80, 0xd2, 0x1e, 0x2, 0xa0, 0xf2}}, - {name: "MOVD/dst=R30/0xffffffffffefffff", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -1048577}, exp: []byte{0x1e, 0x2, 0xa0, 0x92}}, - {name: "MOVD/dst=R30/0xfffff", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 1048575}, exp: []byte{0xfe, 0x4f, 0x40, 0xb2}}, - {name: "MOVD/dst=R30/0xfffffffffff00001", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -1048575}, exp: []byte{0xfe, 0xb3, 0x6c, 0xb2}}, - {name: "MOVD/dst=R30/0x800001", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 8388609}, exp: []byte{0x3e, 0x0, 0x80, 0xd2, 0x1e, 0x10, 0xa0, 0xf2}}, - {name: "MOVD/dst=R30/0xffffffffff7fffff", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -8388609}, exp: []byte{0x1e, 0x10, 0xa0, 0x92}}, - {name: "MOVD/dst=R30/0x40000001", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 1073741825}, exp: []byte{0x3e, 0x0, 0x80, 0xd2, 0x1e, 0x0, 0xa8, 0xf2}}, - {name: "MOVD/dst=R30/0xffffffffbfffffff", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -1073741825}, exp: []byte{0x1e, 0x0, 0xa8, 0x92}}, - {name: "MOVD/dst=R30/0x2", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 2}, exp: []byte{0xfe, 0x3, 0x7f, 0xb2}}, - {name: "MOVD/dst=R30/0xfffffffffffffffe", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -2}, exp: []byte{0x3e, 0x0, 0x80, 0x92}}, - {name: "MOVD/dst=R30/0x3", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 3}, exp: []byte{0xfe, 0x7, 0x40, 0xb2}}, - {name: "MOVD/dst=R30/0xfffffffffffffffd", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -3}, exp: []byte{0x5e, 0x0, 0x80, 0x92}}, - {name: "MOVD/dst=R30/0x1", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 1}, exp: []byte{0xfe, 0x3, 0x40, 0xb2}}, - {name: "MOVD/dst=R30/0xffffffffffffffff", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -1}, exp: []byte{0x1e, 0x0, 0x80, 0x92}}, - {name: "MOVD/dst=R30/0x11", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 17}, exp: []byte{0x3e, 0x2, 0x80, 0xd2}}, - {name: "MOVD/dst=R30/0xffffffffffffffef", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -17}, exp: []byte{0x1e, 0x2, 0x80, 0x92}}, - {name: "MOVD/dst=R30/0x4", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 4}, exp: []byte{0xfe, 0x3, 0x7e, 0xb2}}, - {name: "MOVD/dst=R30/0xfffffffffffffffc", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -4}, exp: []byte{0x7e, 0x0, 0x80, 0x92}}, - {name: "MOVD/dst=R30/0x5", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 5}, exp: []byte{0xbe, 0x0, 0x80, 0xd2}}, - {name: "MOVD/dst=R30/0xfffffffffffffffb", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -5}, exp: []byte{0x9e, 0x0, 0x80, 0x92}}, - {name: "MOVD/dst=R30/0x3", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 3}, exp: []byte{0xfe, 0x7, 0x40, 0xb2}}, - {name: "MOVD/dst=R30/0xfffffffffffffffd", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -3}, exp: []byte{0x5e, 0x0, 0x80, 0x92}}, - {name: "MOVD/dst=R30/0x13", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 19}, exp: []byte{0x7e, 0x2, 0x80, 0xd2}}, - {name: "MOVD/dst=R30/0xffffffffffffffed", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -19}, exp: []byte{0x5e, 0x2, 0x80, 0x92}}, - {name: "MOVD/dst=R30/0x8", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 8}, exp: []byte{0xfe, 0x3, 0x7d, 0xb2}}, - {name: "MOVD/dst=R30/0xfffffffffffffff8", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -8}, exp: []byte{0xfe, 0x0, 0x80, 0x92}}, - {name: "MOVD/dst=R30/0x9", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 9}, exp: []byte{0x3e, 0x1, 0x80, 0xd2}}, - {name: "MOVD/dst=R30/0xfffffffffffffff7", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -9}, exp: []byte{0x1e, 0x1, 0x80, 0x92}}, - {name: "MOVD/dst=R30/0x7", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 7}, exp: []byte{0xfe, 0xb, 0x40, 0xb2}}, - {name: "MOVD/dst=R30/0xfffffffffffffff9", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -7}, exp: []byte{0xde, 0x0, 0x80, 0x92}}, - {name: "MOVD/dst=R30/0x17", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 23}, exp: []byte{0xfe, 0x2, 0x80, 0xd2}}, - {name: "MOVD/dst=R30/0xffffffffffffffe9", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -23}, exp: []byte{0xde, 0x2, 0x80, 0x92}}, - {name: "MOVD/dst=R30/0x10", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 16}, exp: []byte{0xfe, 0x3, 0x7c, 0xb2}}, - {name: "MOVD/dst=R30/0xfffffffffffffff0", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -16}, exp: []byte{0xfe, 0x1, 0x80, 0x92}}, - {name: "MOVD/dst=R30/0x11", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 17}, exp: []byte{0x3e, 0x2, 0x80, 0xd2}}, - {name: "MOVD/dst=R30/0xffffffffffffffef", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -17}, exp: []byte{0x1e, 0x2, 0x80, 0x92}}, - {name: "MOVD/dst=R30/0xf", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 15}, exp: []byte{0xfe, 0xf, 0x40, 0xb2}}, - {name: "MOVD/dst=R30/0xfffffffffffffff1", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -15}, exp: []byte{0xde, 0x1, 0x80, 0x92}}, - {name: "MOVD/dst=R30/0x1f", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 31}, exp: []byte{0xfe, 0x13, 0x40, 0xb2}}, - {name: "MOVD/dst=R30/0xffffffffffffffe1", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -31}, exp: []byte{0xde, 0x3, 0x80, 0x92}}, - {name: "MOVD/dst=R30/0x20", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 32}, exp: []byte{0xfe, 0x3, 0x7b, 0xb2}}, - {name: "MOVD/dst=R30/0xffffffffffffffe0", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -32}, exp: []byte{0xfe, 0x3, 0x80, 0x92}}, - {name: "MOVD/dst=R30/0x21", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 33}, exp: []byte{0x3e, 0x4, 0x80, 0xd2}}, - {name: "MOVD/dst=R30/0xffffffffffffffdf", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -33}, exp: []byte{0x1e, 0x4, 0x80, 0x92}}, - {name: "MOVD/dst=R30/0x1f", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 31}, exp: []byte{0xfe, 0x13, 0x40, 0xb2}}, - {name: "MOVD/dst=R30/0xffffffffffffffe1", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -31}, exp: []byte{0xde, 0x3, 0x80, 0x92}}, - {name: "MOVD/dst=R30/0x2f", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 47}, exp: []byte{0xfe, 0x5, 0x80, 0xd2}}, - {name: "MOVD/dst=R30/0xffffffffffffffd1", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -47}, exp: []byte{0xde, 0x5, 0x80, 0x92}}, - {name: "MOVD/dst=R30/0x40", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 64}, exp: []byte{0xfe, 0x3, 0x7a, 0xb2}}, - {name: "MOVD/dst=R30/0xffffffffffffffc0", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -64}, exp: []byte{0xfe, 0x7, 0x80, 0x92}}, - {name: "MOVD/dst=R30/0x41", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 65}, exp: []byte{0x3e, 0x8, 0x80, 0xd2}}, - {name: "MOVD/dst=R30/0xffffffffffffffbf", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -65}, exp: []byte{0x1e, 0x8, 0x80, 0x92}}, - {name: "MOVD/dst=R30/0x3f", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 63}, exp: []byte{0xfe, 0x17, 0x40, 0xb2}}, - {name: "MOVD/dst=R30/0xffffffffffffffc1", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -63}, exp: []byte{0xde, 0x7, 0x80, 0x92}}, - {name: "MOVD/dst=R30/0x4f", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 79}, exp: []byte{0xfe, 0x9, 0x80, 0xd2}}, - {name: "MOVD/dst=R30/0xffffffffffffffb1", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -79}, exp: []byte{0xde, 0x9, 0x80, 0x92}}, - {name: "MOVD/dst=R30/0x1ffe", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 8190}, exp: []byte{0xde, 0xff, 0x83, 0xd2}}, - {name: "MOVD/dst=R30/0xffffffffffffe002", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -8190}, exp: []byte{0xbe, 0xff, 0x83, 0x92}}, - {name: "MOVD/dst=R30/0x1ffd", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 8189}, exp: []byte{0xbe, 0xff, 0x83, 0xd2}}, - {name: "MOVD/dst=R30/0xffffffffffffe003", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -8189}, exp: []byte{0x9e, 0xff, 0x83, 0x92}}, - {name: "MOVD/dst=R30/0x1fff", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 8191}, exp: []byte{0xfe, 0xff, 0x83, 0xd2}}, - {name: "MOVD/dst=R30/0xffffffffffffe001", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -8191}, exp: []byte{0xde, 0xff, 0x83, 0x92}}, - {name: "MOVD/dst=R30/0x0", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 0}, exp: []byte{0x1e, 0x0, 0x80, 0xd2}}, - {name: "MOVD/dst=R30/0x1", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 1}, exp: []byte{0xfe, 0x3, 0x40, 0xb2}}, - {name: "MOVD/dst=R30/0xffffffffffffffff", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -1}, exp: []byte{0x1e, 0x0, 0x80, 0x92}}, - {name: "MOVD/dst=R30/0xffffffffffffffff", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -1}, exp: []byte{0x1e, 0x0, 0x80, 0x92}}, - {name: "MOVD/dst=R30/0x1", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 1}, exp: []byte{0xfe, 0x3, 0x40, 0xb2}}, - {name: "MOVD/dst=R30/0x2", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 2}, exp: []byte{0xfe, 0x3, 0x7f, 0xb2}}, - {name: "MOVD/dst=R30/0xfffffffffffffffe", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -2}, exp: []byte{0x3e, 0x0, 0x80, 0x92}}, - {name: "MOVD/dst=R30/0x3", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 3}, exp: []byte{0xfe, 0x7, 0x40, 0xb2}}, - {name: "MOVD/dst=R30/0xfffffffffffffffd", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -3}, exp: []byte{0x5e, 0x0, 0x80, 0x92}}, - {name: "MOVD/dst=R30/0xa", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 10}, exp: []byte{0x5e, 0x1, 0x80, 0xd2}}, - {name: "MOVD/dst=R30/0xfffffffffffffff6", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -10}, exp: []byte{0x3e, 0x1, 0x80, 0x92}}, - {name: "MOVD/dst=R30/0xfffffffffffffff6", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -10}, exp: []byte{0x3e, 0x1, 0x80, 0x92}}, - {name: "MOVD/dst=R30/0xa", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 10}, exp: []byte{0x5e, 0x1, 0x80, 0xd2}}, - {name: "MOVD/dst=R30/0x7b", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 123}, exp: []byte{0x7e, 0xf, 0x80, 0xd2}}, - {name: "MOVD/dst=R30/0xffffffffffffff85", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -123}, exp: []byte{0x5e, 0xf, 0x80, 0x92}}, - {name: "MOVD/dst=R30/0xffffffffffffff85", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -123}, exp: []byte{0x5e, 0xf, 0x80, 0x92}}, - {name: "MOVD/dst=R30/0x7b", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 123}, exp: []byte{0x7e, 0xf, 0x80, 0xd2}}, - {name: "MOVD/dst=R30/0x7fff", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 32767}, exp: []byte{0xfe, 0xff, 0x8f, 0xd2}}, - {name: "MOVD/dst=R30/0xffffffffffff8001", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -32767}, exp: []byte{0xde, 0xff, 0x8f, 0x92}}, - {name: "MOVD/dst=R30/0x7fffffff", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 2147483647}, exp: []byte{0xfe, 0x7b, 0x40, 0xb2}}, - {name: "MOVD/dst=R30/0xffffffff80000001", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -2147483647}, exp: []byte{0xfe, 0x87, 0x61, 0xb2}}, - {name: "MOVD/dst=R30/0xffffffff", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 4294967295}, exp: []byte{0xfe, 0x7f, 0x40, 0xb2}}, - {name: "MOVD/dst=R30/0xffffffff00000001", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -4294967295}, exp: []byte{0xfe, 0x83, 0x60, 0xb2}}, - {name: "MOVD/dst=R30/0x4002", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 16386}, exp: []byte{0x5e, 0x0, 0x88, 0xd2}}, - {name: "MOVD/dst=R30/0xffffffffffffbffe", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -16386}, exp: []byte{0x3e, 0x0, 0x88, 0x92}}, - {name: "MOVD/dst=R30/0xffff0000", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 4294901760}, exp: []byte{0xfe, 0xff, 0xbf, 0xd2}}, - {name: "MOVD/dst=R30/0xffffffff00010000", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -4294901760}, exp: []byte{0xfe, 0xff, 0x9f, 0x92, 0x3e, 0x0, 0xa0, 0xf2}}, - {name: "MOVD/dst=R30/0xffff0001", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 4294901761}, exp: []byte{0x3e, 0x0, 0x80, 0xd2, 0xfe, 0xff, 0xbf, 0xf2}}, - {name: "MOVD/dst=R30/0xffffffff0000ffff", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -4294901761}, exp: []byte{0xfe, 0xff, 0xbf, 0x92}}, - {name: "MOVD/dst=R30/0xf00000f", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 251658255}, exp: []byte{0xfe, 0x1, 0x80, 0xd2, 0x1e, 0xe0, 0xa1, 0xf2}}, - {name: "MOVD/dst=R30/0xfffffffff0fffff1", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -251658255}, exp: []byte{0xde, 0x1, 0x80, 0x92, 0xfe, 0x1f, 0xbe, 0xf2}}, - {name: "MOVD/dst=R30/0x7ffe", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 32766}, exp: []byte{0xde, 0xff, 0x8f, 0xd2}}, - {name: "MOVD/dst=R30/0xffffffffffff8002", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -32766}, exp: []byte{0xbe, 0xff, 0x8f, 0x92}}, - {name: "MOVD/dst=R30/0x7ffffffe", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 2147483646}, exp: []byte{0xfe, 0x77, 0x7f, 0xb2}}, - {name: "MOVD/dst=R30/0xffffffff80000002", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -2147483646}, exp: []byte{0xbe, 0xff, 0x9f, 0x92, 0x1e, 0x0, 0xb0, 0xf2}}, - {name: "MOVD/dst=R30/0xfffffffe", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 4294967294}, exp: []byte{0xfe, 0x7b, 0x7f, 0xb2}}, - {name: "MOVD/dst=R30/0xffffffff00000002", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -4294967294}, exp: []byte{0xbe, 0xff, 0x9f, 0x92, 0x1e, 0x0, 0xa0, 0xf2}}, - {name: "MOVD/dst=R30/0x4001", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 16385}, exp: []byte{0x3e, 0x0, 0x88, 0xd2}}, - {name: "MOVD/dst=R30/0xffffffffffffbfff", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -16385}, exp: []byte{0x1e, 0x0, 0x88, 0x92}}, - {name: "MOVD/dst=R30/0xfffeffff", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 4294901759}, exp: []byte{0xfe, 0xff, 0x9f, 0xd2, 0xde, 0xff, 0xbf, 0xf2}}, - {name: "MOVD/dst=R30/0xffffffff00010001", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -4294901759}, exp: []byte{0xde, 0xff, 0x9f, 0x92, 0x3e, 0x0, 0xa0, 0xf2}}, - {name: "MOVD/dst=R30/0xffff0000", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 4294901760}, exp: []byte{0xfe, 0xff, 0xbf, 0xd2}}, - {name: "MOVD/dst=R30/0xffffffff00010000", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -4294901760}, exp: []byte{0xfe, 0xff, 0x9f, 0x92, 0x3e, 0x0, 0xa0, 0xf2}}, - {name: "MOVD/dst=R30/0xf00000e", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 251658254}, exp: []byte{0xde, 0x1, 0x80, 0xd2, 0x1e, 0xe0, 0xa1, 0xf2}}, - {name: "MOVD/dst=R30/0xfffffffff0fffff2", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -251658254}, exp: []byte{0xbe, 0x1, 0x80, 0x92, 0xfe, 0x1f, 0xbe, 0xf2}}, - {name: "MOVD/dst=R30/0x8000", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 32768}, exp: []byte{0xfe, 0x3, 0x71, 0xb2}}, - {name: "MOVD/dst=R30/0xffffffffffff8000", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -32768}, exp: []byte{0xfe, 0xff, 0x8f, 0x92}}, - {name: "MOVD/dst=R30/0x4009", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 16393}, exp: []byte{0x3e, 0x1, 0x88, 0xd2}}, - {name: "MOVD/dst=R30/0xffffffffffffbff7", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -16393}, exp: []byte{0x1e, 0x1, 0x88, 0x92}}, - {name: "MOVD/dst=R30/0xffeffff", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 268369919}, exp: []byte{0xfe, 0xff, 0x9f, 0xd2, 0xde, 0xff, 0xa1, 0xf2}}, - {name: "MOVD/dst=R30/0xfffffffff0010001", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -268369919}, exp: []byte{0xde, 0xff, 0x9f, 0x92, 0x3e, 0x0, 0xbe, 0xf2}}, - {name: "MOVD/dst=R30/0xffe0000", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 268304384}, exp: []byte{0xde, 0xff, 0xa1, 0xd2}}, - {name: "MOVD/dst=R30/0xfffffffff0020000", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -268304384}, exp: []byte{0xfe, 0xff, 0x9f, 0x92, 0x5e, 0x0, 0xbe, 0xf2}}, - {name: "MOVD/dst=R30/0xe00000e", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 234881038}, exp: []byte{0xde, 0x1, 0x80, 0xd2, 0x1e, 0xc0, 0xa1, 0xf2}}, - {name: "MOVD/dst=R30/0xfffffffff1fffff2", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -234881038}, exp: []byte{0xbe, 0x1, 0x80, 0x92, 0xfe, 0x3f, 0xbe, 0xf2}}, - {name: "MOVD/dst=R30/0x80010000", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 2147549184}, exp: []byte{0x3e, 0x0, 0xb0, 0xd2}}, - {name: "MOVD/dst=R30/0xffffffff7fff0000", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -2147549184}, exp: []byte{0xfe, 0xff, 0x9f, 0x92, 0xfe, 0xff, 0xaf, 0xf2}}, - {name: "MOVD/dst=R30/0x10002", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 65538}, exp: []byte{0x5e, 0x0, 0x80, 0xd2, 0x3e, 0x0, 0xa0, 0xf2}}, - {name: "MOVD/dst=R30/0xfffffffffffefffe", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -65538}, exp: []byte{0x3e, 0x0, 0x80, 0x92, 0xde, 0xff, 0xbf, 0xf2}}, - {name: "MOVD/dst=R30/0x100000000", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 4294967296}, exp: []byte{0x3e, 0x0, 0xc0, 0xd2}}, - {name: "MOVD/dst=R30/0xffffffff00000000", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -4294967296}, exp: []byte{0xfe, 0x7f, 0x60, 0xb2}}, - {name: "MOVD/dst=R30/0x400000000", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 17179869184}, exp: []byte{0x9e, 0x0, 0xc0, 0xd2}}, - {name: "MOVD/dst=R30/0xfffffffc00000000", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -17179869184}, exp: []byte{0xfe, 0x77, 0x5e, 0xb2}}, - {name: "MOVD/dst=R30/0x10000000000", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 1099511627776}, exp: []byte{0x1e, 0x20, 0xc0, 0xd2}}, - {name: "MOVD/dst=R30/0xffffff0000000000", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -1099511627776}, exp: []byte{0xfe, 0x5f, 0x58, 0xb2}}, - {name: "MOVD/dst=R30/0x100000001", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 4294967297}, exp: []byte{0xfe, 0x3, 0x0, 0xb2}}, - {name: "MOVD/dst=R30/0xfffffffeffffffff", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -4294967297}, exp: []byte{0x3e, 0x0, 0xc0, 0x92}}, - {name: "MOVD/dst=R30/0x400000001", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 17179869185}, exp: []byte{0x3e, 0x0, 0x80, 0xd2, 0x9e, 0x0, 0xc0, 0xf2}}, - {name: "MOVD/dst=R30/0xfffffffbffffffff", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -17179869185}, exp: []byte{0x9e, 0x0, 0xc0, 0x92}}, - {name: "MOVD/dst=R30/0x10000000001", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 1099511627777}, exp: []byte{0x3e, 0x0, 0x80, 0xd2, 0x1e, 0x20, 0xc0, 0xf2}}, - {name: "MOVD/dst=R30/0xfffffeffffffffff", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -1099511627777}, exp: []byte{0x1e, 0x20, 0xc0, 0x92}}, - {name: "MOVD/dst=R30/0xffffffff", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 4294967295}, exp: []byte{0xfe, 0x7f, 0x40, 0xb2}}, - {name: "MOVD/dst=R30/0xffffffff00000001", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -4294967295}, exp: []byte{0xfe, 0x83, 0x60, 0xb2}}, - {name: "MOVD/dst=R30/0x3ffffffff", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 17179869183}, exp: []byte{0xfe, 0x87, 0x40, 0xb2}}, - {name: "MOVD/dst=R30/0xfffffffc00000001", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -17179869183}, exp: []byte{0xfe, 0x7b, 0x5e, 0xb2}}, - {name: "MOVD/dst=R30/0xffffffffff", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 1099511627775}, exp: []byte{0xfe, 0x9f, 0x40, 0xb2}}, - {name: "MOVD/dst=R30/0xffffff0000000001", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -1099511627775}, exp: []byte{0xfe, 0x63, 0x58, 0xb2}}, - {name: "MOVD/dst=R30/0x10000000f", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 4294967311}, exp: []byte{0xfe, 0x1, 0x80, 0xd2, 0x3e, 0x0, 0xc0, 0xf2}}, - {name: "MOVD/dst=R30/0xfffffffefffffff1", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -4294967311}, exp: []byte{0xde, 0x1, 0x80, 0x92, 0xde, 0xff, 0xdf, 0xf2}}, - {name: "MOVD/dst=R30/0x40000000f", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 17179869199}, exp: []byte{0xfe, 0x1, 0x80, 0xd2, 0x9e, 0x0, 0xc0, 0xf2}}, - {name: "MOVD/dst=R30/0xfffffffbfffffff1", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -17179869199}, exp: []byte{0xde, 0x1, 0x80, 0x92, 0x7e, 0xff, 0xdf, 0xf2}}, - {name: "MOVD/dst=R30/0x1000000000f", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 1099511627791}, exp: []byte{0xfe, 0x1, 0x80, 0xd2, 0x1e, 0x20, 0xc0, 0xf2}}, - {name: "MOVD/dst=R30/0xfffffefffffffff1", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -1099511627791}, exp: []byte{0xde, 0x1, 0x80, 0x92, 0xfe, 0xdf, 0xdf, 0xf2}}, - {name: "MOVD/dst=R30/0xfffffff1", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 4294967281}, exp: []byte{0x3e, 0xfe, 0x9f, 0xd2, 0xfe, 0xff, 0xbf, 0xf2}}, - {name: "MOVD/dst=R30/0xffffffff0000000f", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -4294967281}, exp: []byte{0xfe, 0x8f, 0x60, 0xb2}}, - {name: "MOVD/dst=R30/0x3fffffff1", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 17179869169}, exp: []byte{0x3e, 0xfe, 0x9f, 0xd2, 0xfe, 0xff, 0xbf, 0xf2, 0x7e, 0x0, 0xc0, 0xf2}}, - {name: "MOVD/dst=R30/0xfffffffc0000000f", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -17179869169}, exp: []byte{0xfe, 0x87, 0x5e, 0xb2}}, - {name: "MOVD/dst=R30/0xfffffffff1", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 1099511627761}, exp: []byte{0x3e, 0xfe, 0x9f, 0xd2, 0xfe, 0xff, 0xbf, 0xf2, 0xfe, 0x1f, 0xc0, 0xf2}}, - {name: "MOVD/dst=R30/0xffffff000000000f", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -1099511627761}, exp: []byte{0xfe, 0x6f, 0x58, 0xb2}}, - {name: "MOVD/dst=R30/0x7fffffffffffffff", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 9223372036854775807}, exp: []byte{0x1e, 0x0, 0xf0, 0x92}}, - {name: "MOVD/dst=R30/0x8000000000000001", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -9223372036854775807}, exp: []byte{0xfe, 0x7, 0x41, 0xb2}}, - {name: "MOVD/dst=R30/0x8000000000000000", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -9223372036854775808}, exp: []byte{0x1e, 0x0, 0xf0, 0xd2}}, - {name: "MOVD/dst=R30/0x8000000000000000", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -9223372036854775808}, exp: []byte{0x1e, 0x0, 0xf0, 0xd2}}, - {name: "MOVD/dst=R30/0x40000001", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 1073741825}, exp: []byte{0x3e, 0x0, 0x80, 0xd2, 0x1e, 0x0, 0xa8, 0xf2}}, - {name: "MOVD/dst=R30/0xffffffffbfffffff", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -1073741825}, exp: []byte{0x1e, 0x0, 0xa8, 0x92}}, - {name: "MOVD/dst=R30/0x7000000010000000", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 8070450532516364288}, exp: []byte{0x1e, 0x0, 0xa2, 0xd2, 0x1e, 0x0, 0xee, 0xf2}}, - {name: "MOVD/dst=R30/0x8ffffffff0000000", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -8070450532516364288}, exp: []byte{0x1e, 0x0, 0xbe, 0xd2, 0xfe, 0xff, 0xdf, 0xf2, 0xfe, 0xff, 0xf1, 0xf2}}, - {name: "MOVD/dst=R30/0x7000000100000000", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 8070450536542896128}, exp: []byte{0x3e, 0x0, 0xc0, 0xd2, 0x1e, 0x0, 0xee, 0xf2}}, - {name: "MOVD/dst=R30/0x8fffffff00000000", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -8070450536542896128}, exp: []byte{0xfe, 0xff, 0xdf, 0xd2, 0xfe, 0xff, 0xf1, 0xf2}}, - {name: "MOVD/dst=R30/0x7000100000000000", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 8070468124433973248}, exp: []byte{0x1e, 0x0, 0xc2, 0xd2, 0x1e, 0x0, 0xee, 0xf2}}, - {name: "MOVD/dst=R30/0x8ffff00000000000", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -8070468124433973248}, exp: []byte{0x1e, 0x0, 0xde, 0xd2, 0xfe, 0xff, 0xf1, 0xf2}}, - {name: "MOVD/dst=R30/0x154b4", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 87220}, exp: []byte{0x9e, 0x96, 0x8a, 0xd2, 0x3e, 0x0, 0xa0, 0xf2}}, - {name: "MOVD/dst=R30/0xfffffffffffeab4c", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -87220}, exp: []byte{0x7e, 0x96, 0x8a, 0x92, 0xde, 0xff, 0xbf, 0xf2}}, - {name: "MOVD/dst=R30/0x40008", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 262152}, exp: []byte{0x1e, 0x1, 0x80, 0xd2, 0x9e, 0x0, 0xa0, 0xf2}}, - {name: "MOVD/dst=R30/0xfffffffffffbfff8", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -262152}, exp: []byte{0xfe, 0x0, 0x80, 0x92, 0x7e, 0xff, 0xbf, 0xf2}}, - {name: "MOVD/dst=R30/0xffff0000c466361f", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -281471681677793}, exp: []byte{0xfe, 0xc3, 0x86, 0xd2, 0xde, 0x8c, 0xb8, 0xf2, 0xfe, 0xff, 0xff, 0xf2}}, - {name: "MOVD/dst=R30/0xffff3b99c9e1", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 281471681677793}, exp: []byte{0x3e, 0x3c, 0x99, 0xd2, 0x3e, 0x73, 0xa7, 0xf2, 0xfe, 0xff, 0xdf, 0xf2}}, - {name: "MOVD/dst=R30/0xc465c9ff", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 3295005183}, exp: []byte{0xfe, 0x3f, 0x99, 0xd2, 0xbe, 0x8c, 0xb8, 0xf2}}, - {name: "MOVD/dst=R30/0xffffffff3b9a3601", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -3295005183}, exp: []byte{0xde, 0x3f, 0x99, 0x92, 0x5e, 0x73, 0xa7, 0xf2}}, - {name: "MOVD/dst=R30/0x89705f4136b4a598", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -8543223759426509416}, exp: []byte{0x1e, 0xb3, 0x94, 0xd2, 0x9e, 0xd6, 0xa6, 0xf2, 0x3e, 0xe8, 0xcb, 0xf2, 0x1e, 0x2e, 0xf1, 0xf2}}, - {name: "MOVD/dst=R30/0x768fa0bec94b5a68", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 8543223759426509416}, exp: []byte{0x1e, 0x4d, 0x8b, 0xd2, 0x7e, 0x29, 0xb9, 0xf2, 0xde, 0x17, 0xd4, 0xf2, 0xfe, 0xd1, 0xee, 0xf2}}, - {name: "MOVD/dst=R30/0xffffffffc4653600", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -1000000000}, exp: []byte{0xfe, 0x3f, 0x99, 0x92, 0xbe, 0x8c, 0xb8, 0xf2}}, - {name: "MOVD/dst=R30/0x3b9aca00", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 1000000000}, exp: []byte{0x1e, 0x40, 0x99, 0xd2, 0x5e, 0x73, 0xa7, 0xf2}}, - {name: "MOVD/dst=R30/0xffffff", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: 16777215}, exp: []byte{0xfe, 0x5f, 0x40, 0xb2}}, - {name: "MOVD/dst=R30/0xffffffffff000001", n: &nodeImpl{instruction: MOVD, dstReg: RegR30, srcConst: -16777215}, exp: []byte{0xfe, 0xa3, 0x68, 0xb2}}, - {name: "LSL/dst=R30/0x1", n: &nodeImpl{instruction: LSL, dstReg: RegR30, srcConst: 1}, exp: []byte{0xde, 0xfb, 0x7f, 0xd3}}, - {name: "LSL/dst=R30/0x2", n: &nodeImpl{instruction: LSL, dstReg: RegR30, srcConst: 2}, exp: []byte{0xde, 0xf7, 0x7e, 0xd3}}, - {name: "LSL/dst=R30/0x4", n: &nodeImpl{instruction: LSL, dstReg: RegR30, srcConst: 4}, exp: []byte{0xde, 0xef, 0x7c, 0xd3}}, - {name: "LSL/dst=R30/0x10", n: &nodeImpl{instruction: LSL, dstReg: RegR30, srcConst: 16}, exp: []byte{0xde, 0xbf, 0x70, 0xd3}}, - {name: "LSL/dst=R30/0x1f", n: &nodeImpl{instruction: LSL, dstReg: RegR30, srcConst: 31}, exp: []byte{0xde, 0x83, 0x61, 0xd3}}, - {name: "LSL/dst=R30/0x20", n: &nodeImpl{instruction: LSL, dstReg: RegR30, srcConst: 32}, exp: []byte{0xde, 0x7f, 0x60, 0xd3}}, - {name: "LSL/dst=R30/0x3f", n: &nodeImpl{instruction: LSL, dstReg: RegR30, srcConst: 63}, exp: []byte{0xde, 0x3, 0x41, 0xd3}}, - {name: "LSR/dst=R30/0x1", n: &nodeImpl{instruction: LSR, dstReg: RegR30, srcConst: 1}, exp: []byte{0xde, 0xff, 0x41, 0xd3}}, - {name: "LSR/dst=R30/0x2", n: &nodeImpl{instruction: LSR, dstReg: RegR30, srcConst: 2}, exp: []byte{0xde, 0xff, 0x42, 0xd3}}, - {name: "LSR/dst=R30/0x4", n: &nodeImpl{instruction: LSR, dstReg: RegR30, srcConst: 4}, exp: []byte{0xde, 0xff, 0x44, 0xd3}}, - {name: "LSR/dst=R30/0x10", n: &nodeImpl{instruction: LSR, dstReg: RegR30, srcConst: 16}, exp: []byte{0xde, 0xff, 0x50, 0xd3}}, - {name: "LSR/dst=R30/0x1f", n: &nodeImpl{instruction: LSR, dstReg: RegR30, srcConst: 31}, exp: []byte{0xde, 0xff, 0x5f, 0xd3}}, - {name: "LSR/dst=R30/0x20", n: &nodeImpl{instruction: LSR, dstReg: RegR30, srcConst: 32}, exp: []byte{0xde, 0xff, 0x60, 0xd3}}, - {name: "LSR/dst=R30/0x3f", n: &nodeImpl{instruction: LSR, dstReg: RegR30, srcConst: 63}, exp: []byte{0xde, 0xff, 0x7f, 0xd3}}, - } - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - for _, tt := range tests { - tc := tt - t.Run(tc.name, func(t *testing.T) { - a := NewAssembler(RegR27) - buf := code.NextCodeSection() - err := a.encodeConstToRegister(buf, tc.n) - require.NoError(t, err) - - err = a.Assemble(buf) - require.NoError(t, err) - - actual := buf.Bytes() - require.Equal(t, tc.exp, actual, hex.EncodeToString(actual)) - }) - } -} diff --git a/internal/asm/arm64/impl_3_test.go b/internal/asm/arm64/impl_3_test.go deleted file mode 100644 index 652f230e16..0000000000 --- a/internal/asm/arm64/impl_3_test.go +++ /dev/null @@ -1,1930 +0,0 @@ -package arm64 - -import ( - "encoding/hex" - "testing" - - "github.com/tetratelabs/wazero/internal/asm" - "github.com/tetratelabs/wazero/internal/testing/require" -) - -func TestAssemblerImpl_EncodeTwoRegistersToRegister(t *testing.T) { - t.Run("error", func(t *testing.T) { - tests := []struct { - n *nodeImpl - expErr string - }{ - { - n: &nodeImpl{ - instruction: ADR, types: operandTypesTwoRegistersToRegister, - srcReg: RegR0, srcReg2: RegR0, dstReg: RegR0, - }, - expErr: "ADR is unsupported for TwoRegistersToRegister type", - }, - } - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - for _, tt := range tests { - tc := tt - a := NewAssembler(asm.NilRegister) - buf := code.NextCodeSection() - err := a.encodeTwoRegistersToRegister(buf, tc.n) - require.EqualError(t, err, tc.expErr) - } - }) - - tests := []struct { - name string - exp []byte - inst asm.Instruction - src asm.Register - src2 asm.Register - dst asm.Register - }{ - {name: "src=RZR,src2=RZR,dst=RZR", inst: AND, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0x8a}}, - {name: "src=RZR,src2=RZR,dst=R10", inst: AND, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1f, 0x8a}}, - {name: "src=RZR,src2=RZR,dst=R30", inst: AND, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1f, 0x8a}}, - {name: "src=RZR,src2=R10,dst=RZR", inst: AND, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x1f, 0x8a}}, - {name: "src=RZR,src2=R10,dst=R10", inst: AND, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1f, 0x8a}}, - {name: "src=RZR,src2=R10,dst=R30", inst: AND, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x1f, 0x8a}}, - {name: "src=RZR,src2=R30,dst=RZR", inst: AND, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x1f, 0x8a}}, - {name: "src=RZR,src2=R30,dst=R10", inst: AND, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x1f, 0x8a}}, - {name: "src=RZR,src2=R30,dst=R30", inst: AND, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1f, 0x8a}}, - {name: "src=R10,src2=RZR,dst=RZR", inst: AND, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0xa, 0x8a}}, - {name: "src=R10,src2=RZR,dst=R10", inst: AND, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0xa, 0x8a}}, - {name: "src=R10,src2=RZR,dst=R30", inst: AND, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0xa, 0x8a}}, - {name: "src=R10,src2=R10,dst=RZR", inst: AND, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0xa, 0x8a}}, - {name: "src=R10,src2=R10,dst=R10", inst: AND, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0xa, 0x8a}}, - {name: "src=R10,src2=R10,dst=R30", inst: AND, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0xa, 0x8a}}, - {name: "src=R10,src2=R30,dst=RZR", inst: AND, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0xa, 0x8a}}, - {name: "src=R10,src2=R30,dst=R10", inst: AND, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0xa, 0x8a}}, - {name: "src=R10,src2=R30,dst=R30", inst: AND, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0xa, 0x8a}}, - {name: "src=R30,src2=RZR,dst=RZR", inst: AND, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1e, 0x8a}}, - {name: "src=R30,src2=RZR,dst=R10", inst: AND, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1e, 0x8a}}, - {name: "src=R30,src2=RZR,dst=R30", inst: AND, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1e, 0x8a}}, - {name: "src=R30,src2=R10,dst=RZR", inst: AND, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x1e, 0x8a}}, - {name: "src=R30,src2=R10,dst=R10", inst: AND, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1e, 0x8a}}, - {name: "src=R30,src2=R10,dst=R30", inst: AND, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x1e, 0x8a}}, - {name: "src=R30,src2=R30,dst=RZR", inst: AND, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x1e, 0x8a}}, - {name: "src=R30,src2=R30,dst=R10", inst: AND, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x1e, 0x8a}}, - {name: "src=R30,src2=R30,dst=R30", inst: AND, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1e, 0x8a}}, - {name: "src=RZR,src2=RZR,dst=RZR", inst: ANDW, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0xa}}, - {name: "src=RZR,src2=RZR,dst=R10", inst: ANDW, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1f, 0xa}}, - {name: "src=RZR,src2=RZR,dst=R30", inst: ANDW, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1f, 0xa}}, - {name: "src=RZR,src2=R10,dst=RZR", inst: ANDW, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x1f, 0xa}}, - {name: "src=RZR,src2=R10,dst=R10", inst: ANDW, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1f, 0xa}}, - {name: "src=RZR,src2=R10,dst=R30", inst: ANDW, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x1f, 0xa}}, - {name: "src=RZR,src2=R30,dst=RZR", inst: ANDW, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x1f, 0xa}}, - {name: "src=RZR,src2=R30,dst=R10", inst: ANDW, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x1f, 0xa}}, - {name: "src=RZR,src2=R30,dst=R30", inst: ANDW, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1f, 0xa}}, - {name: "src=R10,src2=RZR,dst=RZR", inst: ANDW, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0xa, 0xa}}, - {name: "src=R10,src2=RZR,dst=R10", inst: ANDW, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0xa, 0xa}}, - {name: "src=R10,src2=RZR,dst=R30", inst: ANDW, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0xa, 0xa}}, - {name: "src=R10,src2=R10,dst=RZR", inst: ANDW, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0xa, 0xa}}, - {name: "src=R10,src2=R10,dst=R10", inst: ANDW, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0xa, 0xa}}, - {name: "src=R10,src2=R10,dst=R30", inst: ANDW, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0xa, 0xa}}, - {name: "src=R10,src2=R30,dst=RZR", inst: ANDW, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0xa, 0xa}}, - {name: "src=R10,src2=R30,dst=R10", inst: ANDW, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0xa, 0xa}}, - {name: "src=R10,src2=R30,dst=R30", inst: ANDW, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0xa, 0xa}}, - {name: "src=R30,src2=RZR,dst=RZR", inst: ANDW, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1e, 0xa}}, - {name: "src=R30,src2=RZR,dst=R10", inst: ANDW, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1e, 0xa}}, - {name: "src=R30,src2=RZR,dst=R30", inst: ANDW, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1e, 0xa}}, - {name: "src=R30,src2=R10,dst=RZR", inst: ANDW, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x1e, 0xa}}, - {name: "src=R30,src2=R10,dst=R10", inst: ANDW, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1e, 0xa}}, - {name: "src=R30,src2=R10,dst=R30", inst: ANDW, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x1e, 0xa}}, - {name: "src=R30,src2=R30,dst=RZR", inst: ANDW, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x1e, 0xa}}, - {name: "src=R30,src2=R30,dst=R10", inst: ANDW, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x1e, 0xa}}, - {name: "src=R30,src2=R30,dst=R30", inst: ANDW, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1e, 0xa}}, - {name: "src=RZR,src2=RZR,dst=RZR", inst: ORR, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0xaa}}, - {name: "src=RZR,src2=RZR,dst=R10", inst: ORR, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1f, 0xaa}}, - {name: "src=RZR,src2=RZR,dst=R30", inst: ORR, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1f, 0xaa}}, - {name: "src=RZR,src2=R10,dst=RZR", inst: ORR, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x1f, 0xaa}}, - {name: "src=RZR,src2=R10,dst=R10", inst: ORR, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1f, 0xaa}}, - {name: "src=RZR,src2=R10,dst=R30", inst: ORR, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x1f, 0xaa}}, - {name: "src=RZR,src2=R30,dst=RZR", inst: ORR, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x1f, 0xaa}}, - {name: "src=RZR,src2=R30,dst=R10", inst: ORR, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x1f, 0xaa}}, - {name: "src=RZR,src2=R30,dst=R30", inst: ORR, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1f, 0xaa}}, - {name: "src=R10,src2=RZR,dst=RZR", inst: ORR, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0xa, 0xaa}}, - {name: "src=R10,src2=RZR,dst=R10", inst: ORR, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0xa, 0xaa}}, - {name: "src=R10,src2=RZR,dst=R30", inst: ORR, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0xa, 0xaa}}, - {name: "src=R10,src2=R10,dst=RZR", inst: ORR, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0xa, 0xaa}}, - {name: "src=R10,src2=R10,dst=R10", inst: ORR, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0xa, 0xaa}}, - {name: "src=R10,src2=R10,dst=R30", inst: ORR, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0xa, 0xaa}}, - {name: "src=R10,src2=R30,dst=RZR", inst: ORR, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0xa, 0xaa}}, - {name: "src=R10,src2=R30,dst=R10", inst: ORR, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0xa, 0xaa}}, - {name: "src=R10,src2=R30,dst=R30", inst: ORR, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0xa, 0xaa}}, - {name: "src=R30,src2=RZR,dst=RZR", inst: ORR, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1e, 0xaa}}, - {name: "src=R30,src2=RZR,dst=R10", inst: ORR, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1e, 0xaa}}, - {name: "src=R30,src2=RZR,dst=R30", inst: ORR, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1e, 0xaa}}, - {name: "src=R30,src2=R10,dst=RZR", inst: ORR, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x1e, 0xaa}}, - {name: "src=R30,src2=R10,dst=R10", inst: ORR, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1e, 0xaa}}, - {name: "src=R30,src2=R10,dst=R30", inst: ORR, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x1e, 0xaa}}, - {name: "src=R30,src2=R30,dst=RZR", inst: ORR, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x1e, 0xaa}}, - {name: "src=R30,src2=R30,dst=R10", inst: ORR, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x1e, 0xaa}}, - {name: "src=R30,src2=R30,dst=R30", inst: ORR, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1e, 0xaa}}, - {name: "src=RZR,src2=RZR,dst=RZR", inst: ORRW, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0x2a}}, - {name: "src=RZR,src2=RZR,dst=R10", inst: ORRW, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1f, 0x2a}}, - {name: "src=RZR,src2=RZR,dst=R30", inst: ORRW, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1f, 0x2a}}, - {name: "src=RZR,src2=R10,dst=RZR", inst: ORRW, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x1f, 0x2a}}, - {name: "src=RZR,src2=R10,dst=R10", inst: ORRW, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1f, 0x2a}}, - {name: "src=RZR,src2=R10,dst=R30", inst: ORRW, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x1f, 0x2a}}, - {name: "src=RZR,src2=R30,dst=RZR", inst: ORRW, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x1f, 0x2a}}, - {name: "src=RZR,src2=R30,dst=R10", inst: ORRW, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x1f, 0x2a}}, - {name: "src=RZR,src2=R30,dst=R30", inst: ORRW, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1f, 0x2a}}, - {name: "src=R10,src2=RZR,dst=RZR", inst: ORRW, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0xa, 0x2a}}, - {name: "src=R10,src2=RZR,dst=R10", inst: ORRW, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0xa, 0x2a}}, - {name: "src=R10,src2=RZR,dst=R30", inst: ORRW, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0xa, 0x2a}}, - {name: "src=R10,src2=R10,dst=RZR", inst: ORRW, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0xa, 0x2a}}, - {name: "src=R10,src2=R10,dst=R10", inst: ORRW, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0xa, 0x2a}}, - {name: "src=R10,src2=R10,dst=R30", inst: ORRW, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0xa, 0x2a}}, - {name: "src=R10,src2=R30,dst=RZR", inst: ORRW, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0xa, 0x2a}}, - {name: "src=R10,src2=R30,dst=R10", inst: ORRW, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0xa, 0x2a}}, - {name: "src=R10,src2=R30,dst=R30", inst: ORRW, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0xa, 0x2a}}, - {name: "src=R30,src2=RZR,dst=RZR", inst: ORRW, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1e, 0x2a}}, - {name: "src=R30,src2=RZR,dst=R10", inst: ORRW, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1e, 0x2a}}, - {name: "src=R30,src2=RZR,dst=R30", inst: ORRW, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1e, 0x2a}}, - {name: "src=R30,src2=R10,dst=RZR", inst: ORRW, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x1e, 0x2a}}, - {name: "src=R30,src2=R10,dst=R10", inst: ORRW, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1e, 0x2a}}, - {name: "src=R30,src2=R10,dst=R30", inst: ORRW, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x1e, 0x2a}}, - {name: "src=R30,src2=R30,dst=RZR", inst: ORRW, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x1e, 0x2a}}, - {name: "src=R30,src2=R30,dst=R10", inst: ORRW, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x1e, 0x2a}}, - {name: "src=R30,src2=R30,dst=R30", inst: ORRW, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1e, 0x2a}}, - {name: "mvn xzr, xzr", inst: ORN, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x3f, 0xaa}}, - {name: "mvn x10, xzr", inst: ORN, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x3f, 0xaa}}, - {name: "mvn x30, xzr", inst: ORN, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x3f, 0xaa}}, - {name: "orn xzr, x10, xzr", inst: ORN, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x3f, 0xaa}}, - {name: "orn x10, x10, xzr", inst: ORN, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x3f, 0xaa}}, - {name: "orn x30, x10, xzr", inst: ORN, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x3f, 0xaa}}, - {name: "orn xzr, x30, xzr", inst: ORN, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x3f, 0xaa}}, - {name: "orn x10, x30, xzr", inst: ORN, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x3f, 0xaa}}, - {name: "orn x30, x30, xzr", inst: ORN, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x3f, 0xaa}}, - {name: "mvn xzr, x10", inst: ORN, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x2a, 0xaa}}, - {name: "mvn x10, x10", inst: ORN, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x2a, 0xaa}}, - {name: "mvn x30, x10", inst: ORN, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x2a, 0xaa}}, - {name: "orn xzr, x10, x10", inst: ORN, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x2a, 0xaa}}, - {name: "orn x10, x10, x10", inst: ORN, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x2a, 0xaa}}, - {name: "orn x30, x10, x10", inst: ORN, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x2a, 0xaa}}, - {name: "orn x30, x10, x10", inst: ORN, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x2a, 0xaa}}, - {name: "orn x10, x30, x10", inst: ORN, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x2a, 0xaa}}, - {name: "orn x30, x30, x10", inst: ORN, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x2a, 0xaa}}, - {name: "mvn xzr, x30", inst: ORN, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x3e, 0xaa}}, - {name: "mvn x10, x30", inst: ORN, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x3e, 0xaa}}, - {name: "mvn x30, x30", inst: ORN, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x3e, 0xaa}}, - {name: "orn xzr, x10, x30", inst: ORN, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x3e, 0xaa}}, - {name: "orn x10, x10, x30", inst: ORN, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x3e, 0xaa}}, - {name: "orn x30, x10, x30", inst: ORN, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x3e, 0xaa}}, - {name: "orn xzr, x30, x30", inst: ORN, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x3e, 0xaa}}, - {name: "orn x10, x30, x30", inst: ORN, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x3e, 0xaa}}, - {name: "orn x30, x30, x30", inst: ORN, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x3e, 0xaa}}, - {name: "mvn wzr, wzr", inst: ORNW, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x3f, 0x2a}}, - {name: "mvn w10, wzr", inst: ORNW, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x3f, 0x2a}}, - {name: "mvn w30, wzr", inst: ORNW, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x3f, 0x2a}}, - {name: "orn wzr, w10, wzr", inst: ORNW, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x3f, 0x2a}}, - {name: "orn w10, w10, wzr", inst: ORNW, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x3f, 0x2a}}, - {name: "orn w30, w10, wzr", inst: ORNW, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x3f, 0x2a}}, - {name: "orn wzr, w30, wzr", inst: ORNW, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x3f, 0x2a}}, - {name: "orn w10, w30, wzr", inst: ORNW, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x3f, 0x2a}}, - {name: "orn w30, w30, wzr", inst: ORNW, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x3f, 0x2a}}, - {name: "mvn wzr, w10", inst: ORNW, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x2a, 0x2a}}, - {name: "mvn w10, w10", inst: ORNW, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x2a, 0x2a}}, - {name: "mvn w30, w10", inst: ORNW, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x2a, 0x2a}}, - {name: "orn wzr, w10, w10", inst: ORNW, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x2a, 0x2a}}, - {name: "orn w10, w10, w10", inst: ORNW, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x2a, 0x2a}}, - {name: "orn w30, w10, w10", inst: ORNW, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x2a, 0x2a}}, - {name: "orn w30, w10, w10", inst: ORNW, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x2a, 0x2a}}, - {name: "orn w10, w30, w10", inst: ORNW, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x2a, 0x2a}}, - {name: "orn w30, w30, w10", inst: ORNW, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x2a, 0x2a}}, - {name: "mvn wzr, w30", inst: ORNW, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x3e, 0x2a}}, - {name: "mvn w10, w30", inst: ORNW, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x3e, 0x2a}}, - {name: "mvn w30, w30", inst: ORNW, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x3e, 0x2a}}, - {name: "orn wzr, w10, w30", inst: ORNW, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x3e, 0x2a}}, - {name: "orn w10, w10, w30", inst: ORNW, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x3e, 0x2a}}, - {name: "orn w30, w10, w30", inst: ORNW, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x3e, 0x2a}}, - {name: "orn wzr, w30, w30", inst: ORNW, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x3e, 0x2a}}, - {name: "orn w10, w30, w30", inst: ORNW, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x3e, 0x2a}}, - {name: "orn w30, w30, w30", inst: ORNW, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x3e, 0x2a}}, - {name: "src=RZR,src2=RZR,dst=RZR", inst: EOR, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0xca}}, - {name: "src=RZR,src2=RZR,dst=R10", inst: EOR, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1f, 0xca}}, - {name: "src=RZR,src2=RZR,dst=R30", inst: EOR, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1f, 0xca}}, - {name: "src=RZR,src2=R10,dst=RZR", inst: EOR, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x1f, 0xca}}, - {name: "src=RZR,src2=R10,dst=R10", inst: EOR, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1f, 0xca}}, - {name: "src=RZR,src2=R10,dst=R30", inst: EOR, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x1f, 0xca}}, - {name: "src=RZR,src2=R30,dst=RZR", inst: EOR, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x1f, 0xca}}, - {name: "src=RZR,src2=R30,dst=R10", inst: EOR, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x1f, 0xca}}, - {name: "src=RZR,src2=R30,dst=R30", inst: EOR, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1f, 0xca}}, - {name: "src=R10,src2=RZR,dst=RZR", inst: EOR, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0xa, 0xca}}, - {name: "src=R10,src2=RZR,dst=R10", inst: EOR, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0xa, 0xca}}, - {name: "src=R10,src2=RZR,dst=R30", inst: EOR, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0xa, 0xca}}, - {name: "src=R10,src2=R10,dst=RZR", inst: EOR, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0xa, 0xca}}, - {name: "src=R10,src2=R10,dst=R10", inst: EOR, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0xa, 0xca}}, - {name: "src=R10,src2=R10,dst=R30", inst: EOR, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0xa, 0xca}}, - {name: "src=R10,src2=R30,dst=RZR", inst: EOR, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0xa, 0xca}}, - {name: "src=R10,src2=R30,dst=R10", inst: EOR, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0xa, 0xca}}, - {name: "src=R10,src2=R30,dst=R30", inst: EOR, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0xa, 0xca}}, - {name: "src=R30,src2=RZR,dst=RZR", inst: EOR, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1e, 0xca}}, - {name: "src=R30,src2=RZR,dst=R10", inst: EOR, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1e, 0xca}}, - {name: "src=R30,src2=RZR,dst=R30", inst: EOR, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1e, 0xca}}, - {name: "src=R30,src2=R10,dst=RZR", inst: EOR, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x1e, 0xca}}, - {name: "src=R30,src2=R10,dst=R10", inst: EOR, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1e, 0xca}}, - {name: "src=R30,src2=R10,dst=R30", inst: EOR, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x1e, 0xca}}, - {name: "src=R30,src2=R30,dst=RZR", inst: EOR, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x1e, 0xca}}, - {name: "src=R30,src2=R30,dst=R10", inst: EOR, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x1e, 0xca}}, - {name: "src=R30,src2=R30,dst=R30", inst: EOR, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1e, 0xca}}, - {name: "src=RZR,src2=RZR,dst=RZR", inst: EORW, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0x4a}}, - {name: "src=RZR,src2=RZR,dst=R10", inst: EORW, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1f, 0x4a}}, - {name: "src=RZR,src2=RZR,dst=R30", inst: EORW, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1f, 0x4a}}, - {name: "src=RZR,src2=R10,dst=RZR", inst: EORW, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x1f, 0x4a}}, - {name: "src=RZR,src2=R10,dst=R10", inst: EORW, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1f, 0x4a}}, - {name: "src=RZR,src2=R10,dst=R30", inst: EORW, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x1f, 0x4a}}, - {name: "src=RZR,src2=R30,dst=RZR", inst: EORW, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x1f, 0x4a}}, - {name: "src=RZR,src2=R30,dst=R10", inst: EORW, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x1f, 0x4a}}, - {name: "src=RZR,src2=R30,dst=R30", inst: EORW, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1f, 0x4a}}, - {name: "src=R10,src2=RZR,dst=RZR", inst: EORW, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0xa, 0x4a}}, - {name: "src=R10,src2=RZR,dst=R10", inst: EORW, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0xa, 0x4a}}, - {name: "src=R10,src2=RZR,dst=R30", inst: EORW, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0xa, 0x4a}}, - {name: "src=R10,src2=R10,dst=RZR", inst: EORW, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0xa, 0x4a}}, - {name: "src=R10,src2=R10,dst=R10", inst: EORW, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0xa, 0x4a}}, - {name: "src=R10,src2=R10,dst=R30", inst: EORW, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0xa, 0x4a}}, - {name: "src=R10,src2=R30,dst=RZR", inst: EORW, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0xa, 0x4a}}, - {name: "src=R10,src2=R30,dst=R10", inst: EORW, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0xa, 0x4a}}, - {name: "src=R10,src2=R30,dst=R30", inst: EORW, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0xa, 0x4a}}, - {name: "src=R30,src2=RZR,dst=RZR", inst: EORW, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1e, 0x4a}}, - {name: "src=R30,src2=RZR,dst=R10", inst: EORW, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1e, 0x4a}}, - {name: "src=R30,src2=RZR,dst=R30", inst: EORW, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1e, 0x4a}}, - {name: "src=R30,src2=R10,dst=RZR", inst: EORW, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x1e, 0x4a}}, - {name: "src=R30,src2=R10,dst=R10", inst: EORW, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1e, 0x4a}}, - {name: "src=R30,src2=R10,dst=R30", inst: EORW, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x1e, 0x4a}}, - {name: "src=R30,src2=R30,dst=RZR", inst: EORW, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x1e, 0x4a}}, - {name: "src=R30,src2=R30,dst=R10", inst: EORW, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x1e, 0x4a}}, - {name: "src=R30,src2=R30,dst=R30", inst: EORW, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1e, 0x4a}}, - {name: "src=RZR,src2=RZR,dst=RZR", inst: ASR, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x2b, 0xdf, 0x9a}}, - {name: "src=RZR,src2=RZR,dst=R10", inst: ASR, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x2b, 0xdf, 0x9a}}, - {name: "src=RZR,src2=RZR,dst=R30", inst: ASR, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x2b, 0xdf, 0x9a}}, - {name: "src=RZR,src2=R10,dst=RZR", inst: ASR, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x29, 0xdf, 0x9a}}, - {name: "src=RZR,src2=R10,dst=R10", inst: ASR, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x29, 0xdf, 0x9a}}, - {name: "src=RZR,src2=R10,dst=R30", inst: ASR, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x29, 0xdf, 0x9a}}, - {name: "src=RZR,src2=R30,dst=RZR", inst: ASR, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x2b, 0xdf, 0x9a}}, - {name: "src=RZR,src2=R30,dst=R10", inst: ASR, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x2b, 0xdf, 0x9a}}, - {name: "src=RZR,src2=R30,dst=R30", inst: ASR, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x2b, 0xdf, 0x9a}}, - {name: "src=R10,src2=RZR,dst=RZR", inst: ASR, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x2b, 0xca, 0x9a}}, - {name: "src=R10,src2=RZR,dst=R10", inst: ASR, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x2b, 0xca, 0x9a}}, - {name: "src=R10,src2=RZR,dst=R30", inst: ASR, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x2b, 0xca, 0x9a}}, - {name: "src=R10,src2=R10,dst=RZR", inst: ASR, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x29, 0xca, 0x9a}}, - {name: "src=R10,src2=R10,dst=R10", inst: ASR, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x29, 0xca, 0x9a}}, - {name: "src=R10,src2=R10,dst=R30", inst: ASR, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x29, 0xca, 0x9a}}, - {name: "src=R10,src2=R30,dst=RZR", inst: ASR, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x2b, 0xca, 0x9a}}, - {name: "src=R10,src2=R30,dst=R10", inst: ASR, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x2b, 0xca, 0x9a}}, - {name: "src=R10,src2=R30,dst=R30", inst: ASR, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x2b, 0xca, 0x9a}}, - {name: "src=R30,src2=RZR,dst=RZR", inst: ASR, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x2b, 0xde, 0x9a}}, - {name: "src=R30,src2=RZR,dst=R10", inst: ASR, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x2b, 0xde, 0x9a}}, - {name: "src=R30,src2=RZR,dst=R30", inst: ASR, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x2b, 0xde, 0x9a}}, - {name: "src=R30,src2=R10,dst=RZR", inst: ASR, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x29, 0xde, 0x9a}}, - {name: "src=R30,src2=R10,dst=R10", inst: ASR, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x29, 0xde, 0x9a}}, - {name: "src=R30,src2=R10,dst=R30", inst: ASR, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x29, 0xde, 0x9a}}, - {name: "src=R30,src2=R30,dst=RZR", inst: ASR, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x2b, 0xde, 0x9a}}, - {name: "src=R30,src2=R30,dst=R10", inst: ASR, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x2b, 0xde, 0x9a}}, - {name: "src=R30,src2=R30,dst=R30", inst: ASR, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x2b, 0xde, 0x9a}}, - {name: "src=RZR,src2=RZR,dst=RZR", inst: ASRW, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x2b, 0xdf, 0x1a}}, - {name: "src=RZR,src2=RZR,dst=R10", inst: ASRW, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x2b, 0xdf, 0x1a}}, - {name: "src=RZR,src2=RZR,dst=R30", inst: ASRW, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x2b, 0xdf, 0x1a}}, - {name: "src=RZR,src2=R10,dst=RZR", inst: ASRW, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x29, 0xdf, 0x1a}}, - {name: "src=RZR,src2=R10,dst=R10", inst: ASRW, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x29, 0xdf, 0x1a}}, - {name: "src=RZR,src2=R10,dst=R30", inst: ASRW, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x29, 0xdf, 0x1a}}, - {name: "src=RZR,src2=R30,dst=RZR", inst: ASRW, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x2b, 0xdf, 0x1a}}, - {name: "src=RZR,src2=R30,dst=R10", inst: ASRW, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x2b, 0xdf, 0x1a}}, - {name: "src=RZR,src2=R30,dst=R30", inst: ASRW, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x2b, 0xdf, 0x1a}}, - {name: "src=R10,src2=RZR,dst=RZR", inst: ASRW, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x2b, 0xca, 0x1a}}, - {name: "src=R10,src2=RZR,dst=R10", inst: ASRW, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x2b, 0xca, 0x1a}}, - {name: "src=R10,src2=RZR,dst=R30", inst: ASRW, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x2b, 0xca, 0x1a}}, - {name: "src=R10,src2=R10,dst=RZR", inst: ASRW, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x29, 0xca, 0x1a}}, - {name: "src=R10,src2=R10,dst=R10", inst: ASRW, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x29, 0xca, 0x1a}}, - {name: "src=R10,src2=R10,dst=R30", inst: ASRW, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x29, 0xca, 0x1a}}, - {name: "src=R10,src2=R30,dst=RZR", inst: ASRW, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x2b, 0xca, 0x1a}}, - {name: "src=R10,src2=R30,dst=R10", inst: ASRW, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x2b, 0xca, 0x1a}}, - {name: "src=R10,src2=R30,dst=R30", inst: ASRW, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x2b, 0xca, 0x1a}}, - {name: "src=R30,src2=RZR,dst=RZR", inst: ASRW, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x2b, 0xde, 0x1a}}, - {name: "src=R30,src2=RZR,dst=R10", inst: ASRW, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x2b, 0xde, 0x1a}}, - {name: "src=R30,src2=RZR,dst=R30", inst: ASRW, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x2b, 0xde, 0x1a}}, - {name: "src=R30,src2=R10,dst=RZR", inst: ASRW, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x29, 0xde, 0x1a}}, - {name: "src=R30,src2=R10,dst=R10", inst: ASRW, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x29, 0xde, 0x1a}}, - {name: "src=R30,src2=R10,dst=R30", inst: ASRW, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x29, 0xde, 0x1a}}, - {name: "src=R30,src2=R30,dst=RZR", inst: ASRW, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x2b, 0xde, 0x1a}}, - {name: "src=R30,src2=R30,dst=R10", inst: ASRW, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x2b, 0xde, 0x1a}}, - {name: "src=R30,src2=R30,dst=R30", inst: ASRW, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x2b, 0xde, 0x1a}}, - {name: "src=RZR,src2=RZR,dst=RZR", inst: LSL, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x23, 0xdf, 0x9a}}, - {name: "src=RZR,src2=RZR,dst=R10", inst: LSL, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x23, 0xdf, 0x9a}}, - {name: "src=RZR,src2=RZR,dst=R30", inst: LSL, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x23, 0xdf, 0x9a}}, - {name: "src=RZR,src2=R10,dst=RZR", inst: LSL, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x21, 0xdf, 0x9a}}, - {name: "src=RZR,src2=R10,dst=R10", inst: LSL, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x21, 0xdf, 0x9a}}, - {name: "src=RZR,src2=R10,dst=R30", inst: LSL, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x21, 0xdf, 0x9a}}, - {name: "src=RZR,src2=R30,dst=RZR", inst: LSL, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x23, 0xdf, 0x9a}}, - {name: "src=RZR,src2=R30,dst=R10", inst: LSL, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x23, 0xdf, 0x9a}}, - {name: "src=RZR,src2=R30,dst=R30", inst: LSL, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x23, 0xdf, 0x9a}}, - {name: "src=R10,src2=RZR,dst=RZR", inst: LSL, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x23, 0xca, 0x9a}}, - {name: "src=R10,src2=RZR,dst=R10", inst: LSL, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x23, 0xca, 0x9a}}, - {name: "src=R10,src2=RZR,dst=R30", inst: LSL, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x23, 0xca, 0x9a}}, - {name: "src=R10,src2=R10,dst=RZR", inst: LSL, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x21, 0xca, 0x9a}}, - {name: "src=R10,src2=R10,dst=R10", inst: LSL, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x21, 0xca, 0x9a}}, - {name: "src=R10,src2=R10,dst=R30", inst: LSL, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x21, 0xca, 0x9a}}, - {name: "src=R10,src2=R30,dst=RZR", inst: LSL, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x23, 0xca, 0x9a}}, - {name: "src=R10,src2=R30,dst=R10", inst: LSL, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x23, 0xca, 0x9a}}, - {name: "src=R10,src2=R30,dst=R30", inst: LSL, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x23, 0xca, 0x9a}}, - {name: "src=R30,src2=RZR,dst=RZR", inst: LSL, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x23, 0xde, 0x9a}}, - {name: "src=R30,src2=RZR,dst=R10", inst: LSL, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x23, 0xde, 0x9a}}, - {name: "src=R30,src2=RZR,dst=R30", inst: LSL, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x23, 0xde, 0x9a}}, - {name: "src=R30,src2=R10,dst=RZR", inst: LSL, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x21, 0xde, 0x9a}}, - {name: "src=R30,src2=R10,dst=R10", inst: LSL, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x21, 0xde, 0x9a}}, - {name: "src=R30,src2=R10,dst=R30", inst: LSL, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x21, 0xde, 0x9a}}, - {name: "src=R30,src2=R30,dst=RZR", inst: LSL, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x23, 0xde, 0x9a}}, - {name: "src=R30,src2=R30,dst=R10", inst: LSL, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x23, 0xde, 0x9a}}, - {name: "src=R30,src2=R30,dst=R30", inst: LSL, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x23, 0xde, 0x9a}}, - {name: "src=RZR,src2=RZR,dst=RZR", inst: LSLW, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x23, 0xdf, 0x1a}}, - {name: "src=RZR,src2=RZR,dst=R10", inst: LSLW, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x23, 0xdf, 0x1a}}, - {name: "src=RZR,src2=RZR,dst=R30", inst: LSLW, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x23, 0xdf, 0x1a}}, - {name: "src=RZR,src2=R10,dst=RZR", inst: LSLW, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x21, 0xdf, 0x1a}}, - {name: "src=RZR,src2=R10,dst=R10", inst: LSLW, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x21, 0xdf, 0x1a}}, - {name: "src=RZR,src2=R10,dst=R30", inst: LSLW, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x21, 0xdf, 0x1a}}, - {name: "src=RZR,src2=R30,dst=RZR", inst: LSLW, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x23, 0xdf, 0x1a}}, - {name: "src=RZR,src2=R30,dst=R10", inst: LSLW, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x23, 0xdf, 0x1a}}, - {name: "src=RZR,src2=R30,dst=R30", inst: LSLW, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x23, 0xdf, 0x1a}}, - {name: "src=R10,src2=RZR,dst=RZR", inst: LSLW, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x23, 0xca, 0x1a}}, - {name: "src=R10,src2=RZR,dst=R10", inst: LSLW, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x23, 0xca, 0x1a}}, - {name: "src=R10,src2=RZR,dst=R30", inst: LSLW, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x23, 0xca, 0x1a}}, - {name: "src=R10,src2=R10,dst=RZR", inst: LSLW, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x21, 0xca, 0x1a}}, - {name: "src=R10,src2=R10,dst=R10", inst: LSLW, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x21, 0xca, 0x1a}}, - {name: "src=R10,src2=R10,dst=R30", inst: LSLW, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x21, 0xca, 0x1a}}, - {name: "src=R10,src2=R30,dst=RZR", inst: LSLW, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x23, 0xca, 0x1a}}, - {name: "src=R10,src2=R30,dst=R10", inst: LSLW, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x23, 0xca, 0x1a}}, - {name: "src=R10,src2=R30,dst=R30", inst: LSLW, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x23, 0xca, 0x1a}}, - {name: "src=R30,src2=RZR,dst=RZR", inst: LSLW, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x23, 0xde, 0x1a}}, - {name: "src=R30,src2=RZR,dst=R10", inst: LSLW, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x23, 0xde, 0x1a}}, - {name: "src=R30,src2=RZR,dst=R30", inst: LSLW, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x23, 0xde, 0x1a}}, - {name: "src=R30,src2=R10,dst=RZR", inst: LSLW, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x21, 0xde, 0x1a}}, - {name: "src=R30,src2=R10,dst=R10", inst: LSLW, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x21, 0xde, 0x1a}}, - {name: "src=R30,src2=R10,dst=R30", inst: LSLW, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x21, 0xde, 0x1a}}, - {name: "src=R30,src2=R30,dst=RZR", inst: LSLW, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x23, 0xde, 0x1a}}, - {name: "src=R30,src2=R30,dst=R10", inst: LSLW, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x23, 0xde, 0x1a}}, - {name: "src=R30,src2=R30,dst=R30", inst: LSLW, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x23, 0xde, 0x1a}}, - {name: "src=RZR,src2=RZR,dst=RZR", inst: LSR, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x27, 0xdf, 0x9a}}, - {name: "src=RZR,src2=RZR,dst=R10", inst: LSR, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x27, 0xdf, 0x9a}}, - {name: "src=RZR,src2=RZR,dst=R30", inst: LSR, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x27, 0xdf, 0x9a}}, - {name: "src=RZR,src2=R10,dst=RZR", inst: LSR, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x25, 0xdf, 0x9a}}, - {name: "src=RZR,src2=R10,dst=R10", inst: LSR, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x25, 0xdf, 0x9a}}, - {name: "src=RZR,src2=R10,dst=R30", inst: LSR, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x25, 0xdf, 0x9a}}, - {name: "src=RZR,src2=R30,dst=RZR", inst: LSR, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x27, 0xdf, 0x9a}}, - {name: "src=RZR,src2=R30,dst=R10", inst: LSR, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x27, 0xdf, 0x9a}}, - {name: "src=RZR,src2=R30,dst=R30", inst: LSR, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x27, 0xdf, 0x9a}}, - {name: "src=R10,src2=RZR,dst=RZR", inst: LSR, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x27, 0xca, 0x9a}}, - {name: "src=R10,src2=RZR,dst=R10", inst: LSR, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x27, 0xca, 0x9a}}, - {name: "src=R10,src2=RZR,dst=R30", inst: LSR, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x27, 0xca, 0x9a}}, - {name: "src=R10,src2=R10,dst=RZR", inst: LSR, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x25, 0xca, 0x9a}}, - {name: "src=R10,src2=R10,dst=R10", inst: LSR, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x25, 0xca, 0x9a}}, - {name: "src=R10,src2=R10,dst=R30", inst: LSR, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x25, 0xca, 0x9a}}, - {name: "src=R10,src2=R30,dst=RZR", inst: LSR, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x27, 0xca, 0x9a}}, - {name: "src=R10,src2=R30,dst=R10", inst: LSR, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x27, 0xca, 0x9a}}, - {name: "src=R10,src2=R30,dst=R30", inst: LSR, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x27, 0xca, 0x9a}}, - {name: "src=R30,src2=RZR,dst=RZR", inst: LSR, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x27, 0xde, 0x9a}}, - {name: "src=R30,src2=RZR,dst=R10", inst: LSR, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x27, 0xde, 0x9a}}, - {name: "src=R30,src2=RZR,dst=R30", inst: LSR, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x27, 0xde, 0x9a}}, - {name: "src=R30,src2=R10,dst=RZR", inst: LSR, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x25, 0xde, 0x9a}}, - {name: "src=R30,src2=R10,dst=R10", inst: LSR, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x25, 0xde, 0x9a}}, - {name: "src=R30,src2=R10,dst=R30", inst: LSR, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x25, 0xde, 0x9a}}, - {name: "src=R30,src2=R30,dst=RZR", inst: LSR, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x27, 0xde, 0x9a}}, - {name: "src=R30,src2=R30,dst=R10", inst: LSR, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x27, 0xde, 0x9a}}, - {name: "src=R30,src2=R30,dst=R30", inst: LSR, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x27, 0xde, 0x9a}}, - {name: "src=RZR,src2=RZR,dst=RZR", inst: LSRW, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x27, 0xdf, 0x1a}}, - {name: "src=RZR,src2=RZR,dst=R10", inst: LSRW, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x27, 0xdf, 0x1a}}, - {name: "src=RZR,src2=RZR,dst=R30", inst: LSRW, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x27, 0xdf, 0x1a}}, - {name: "src=RZR,src2=R10,dst=RZR", inst: LSRW, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x25, 0xdf, 0x1a}}, - {name: "src=RZR,src2=R10,dst=R10", inst: LSRW, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x25, 0xdf, 0x1a}}, - {name: "src=RZR,src2=R10,dst=R30", inst: LSRW, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x25, 0xdf, 0x1a}}, - {name: "src=RZR,src2=R30,dst=RZR", inst: LSRW, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x27, 0xdf, 0x1a}}, - {name: "src=RZR,src2=R30,dst=R10", inst: LSRW, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x27, 0xdf, 0x1a}}, - {name: "src=RZR,src2=R30,dst=R30", inst: LSRW, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x27, 0xdf, 0x1a}}, - {name: "src=R10,src2=RZR,dst=RZR", inst: LSRW, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x27, 0xca, 0x1a}}, - {name: "src=R10,src2=RZR,dst=R10", inst: LSRW, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x27, 0xca, 0x1a}}, - {name: "src=R10,src2=RZR,dst=R30", inst: LSRW, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x27, 0xca, 0x1a}}, - {name: "src=R10,src2=R10,dst=RZR", inst: LSRW, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x25, 0xca, 0x1a}}, - {name: "src=R10,src2=R10,dst=R10", inst: LSRW, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x25, 0xca, 0x1a}}, - {name: "src=R10,src2=R10,dst=R30", inst: LSRW, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x25, 0xca, 0x1a}}, - {name: "src=R10,src2=R30,dst=RZR", inst: LSRW, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x27, 0xca, 0x1a}}, - {name: "src=R10,src2=R30,dst=R10", inst: LSRW, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x27, 0xca, 0x1a}}, - {name: "src=R10,src2=R30,dst=R30", inst: LSRW, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x27, 0xca, 0x1a}}, - {name: "src=R30,src2=RZR,dst=RZR", inst: LSRW, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x27, 0xde, 0x1a}}, - {name: "src=R30,src2=RZR,dst=R10", inst: LSRW, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x27, 0xde, 0x1a}}, - {name: "src=R30,src2=RZR,dst=R30", inst: LSRW, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x27, 0xde, 0x1a}}, - {name: "src=R30,src2=R10,dst=RZR", inst: LSRW, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x25, 0xde, 0x1a}}, - {name: "src=R30,src2=R10,dst=R10", inst: LSRW, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x25, 0xde, 0x1a}}, - {name: "src=R30,src2=R10,dst=R30", inst: LSRW, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x25, 0xde, 0x1a}}, - {name: "src=R30,src2=R30,dst=RZR", inst: LSRW, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x27, 0xde, 0x1a}}, - {name: "src=R30,src2=R30,dst=R10", inst: LSRW, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x27, 0xde, 0x1a}}, - {name: "src=R30,src2=R30,dst=R30", inst: LSRW, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x27, 0xde, 0x1a}}, - {name: "src=RZR,src2=RZR,dst=RZR", inst: ROR, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x2f, 0xdf, 0x9a}}, - {name: "src=RZR,src2=RZR,dst=R10", inst: ROR, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x2f, 0xdf, 0x9a}}, - {name: "src=RZR,src2=RZR,dst=R30", inst: ROR, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x2f, 0xdf, 0x9a}}, - {name: "src=RZR,src2=R10,dst=RZR", inst: ROR, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x2d, 0xdf, 0x9a}}, - {name: "src=RZR,src2=R10,dst=R10", inst: ROR, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x2d, 0xdf, 0x9a}}, - {name: "src=RZR,src2=R10,dst=R30", inst: ROR, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x2d, 0xdf, 0x9a}}, - {name: "src=RZR,src2=R30,dst=RZR", inst: ROR, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x2f, 0xdf, 0x9a}}, - {name: "src=RZR,src2=R30,dst=R10", inst: ROR, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x2f, 0xdf, 0x9a}}, - {name: "src=RZR,src2=R30,dst=R30", inst: ROR, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x2f, 0xdf, 0x9a}}, - {name: "src=R10,src2=RZR,dst=RZR", inst: ROR, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x2f, 0xca, 0x9a}}, - {name: "src=R10,src2=RZR,dst=R10", inst: ROR, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x2f, 0xca, 0x9a}}, - {name: "src=R10,src2=RZR,dst=R30", inst: ROR, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x2f, 0xca, 0x9a}}, - {name: "src=R10,src2=R10,dst=RZR", inst: ROR, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x2d, 0xca, 0x9a}}, - {name: "src=R10,src2=R10,dst=R10", inst: ROR, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x2d, 0xca, 0x9a}}, - {name: "src=R10,src2=R10,dst=R30", inst: ROR, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x2d, 0xca, 0x9a}}, - {name: "src=R10,src2=R30,dst=RZR", inst: ROR, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x2f, 0xca, 0x9a}}, - {name: "src=R10,src2=R30,dst=R10", inst: ROR, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x2f, 0xca, 0x9a}}, - {name: "src=R10,src2=R30,dst=R30", inst: ROR, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x2f, 0xca, 0x9a}}, - {name: "src=R30,src2=RZR,dst=RZR", inst: ROR, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x2f, 0xde, 0x9a}}, - {name: "src=R30,src2=RZR,dst=R10", inst: ROR, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x2f, 0xde, 0x9a}}, - {name: "src=R30,src2=RZR,dst=R30", inst: ROR, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x2f, 0xde, 0x9a}}, - {name: "src=R30,src2=R10,dst=RZR", inst: ROR, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x2d, 0xde, 0x9a}}, - {name: "src=R30,src2=R10,dst=R10", inst: ROR, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x2d, 0xde, 0x9a}}, - {name: "src=R30,src2=R10,dst=R30", inst: ROR, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x2d, 0xde, 0x9a}}, - {name: "src=R30,src2=R30,dst=RZR", inst: ROR, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x2f, 0xde, 0x9a}}, - {name: "src=R30,src2=R30,dst=R10", inst: ROR, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x2f, 0xde, 0x9a}}, - {name: "src=R30,src2=R30,dst=R30", inst: ROR, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x2f, 0xde, 0x9a}}, - {name: "src=RZR,src2=RZR,dst=RZR", inst: RORW, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x2f, 0xdf, 0x1a}}, - {name: "src=RZR,src2=RZR,dst=R10", inst: RORW, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x2f, 0xdf, 0x1a}}, - {name: "src=RZR,src2=RZR,dst=R30", inst: RORW, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x2f, 0xdf, 0x1a}}, - {name: "src=RZR,src2=R10,dst=RZR", inst: RORW, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x2d, 0xdf, 0x1a}}, - {name: "src=RZR,src2=R10,dst=R10", inst: RORW, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x2d, 0xdf, 0x1a}}, - {name: "src=RZR,src2=R10,dst=R30", inst: RORW, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x2d, 0xdf, 0x1a}}, - {name: "src=RZR,src2=R30,dst=RZR", inst: RORW, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x2f, 0xdf, 0x1a}}, - {name: "src=RZR,src2=R30,dst=R10", inst: RORW, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x2f, 0xdf, 0x1a}}, - {name: "src=RZR,src2=R30,dst=R30", inst: RORW, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x2f, 0xdf, 0x1a}}, - {name: "src=R10,src2=RZR,dst=RZR", inst: RORW, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x2f, 0xca, 0x1a}}, - {name: "src=R10,src2=RZR,dst=R10", inst: RORW, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x2f, 0xca, 0x1a}}, - {name: "src=R10,src2=RZR,dst=R30", inst: RORW, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x2f, 0xca, 0x1a}}, - {name: "src=R10,src2=R10,dst=RZR", inst: RORW, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x2d, 0xca, 0x1a}}, - {name: "src=R10,src2=R10,dst=R10", inst: RORW, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x2d, 0xca, 0x1a}}, - {name: "src=R10,src2=R10,dst=R30", inst: RORW, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x2d, 0xca, 0x1a}}, - {name: "src=R10,src2=R30,dst=RZR", inst: RORW, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x2f, 0xca, 0x1a}}, - {name: "src=R10,src2=R30,dst=R10", inst: RORW, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x2f, 0xca, 0x1a}}, - {name: "src=R10,src2=R30,dst=R30", inst: RORW, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x2f, 0xca, 0x1a}}, - {name: "src=R30,src2=RZR,dst=RZR", inst: RORW, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x2f, 0xde, 0x1a}}, - {name: "src=R30,src2=RZR,dst=R10", inst: RORW, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x2f, 0xde, 0x1a}}, - {name: "src=R30,src2=RZR,dst=R30", inst: RORW, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x2f, 0xde, 0x1a}}, - {name: "src=R30,src2=R10,dst=RZR", inst: RORW, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x2d, 0xde, 0x1a}}, - {name: "src=R30,src2=R10,dst=R10", inst: RORW, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x2d, 0xde, 0x1a}}, - {name: "src=R30,src2=R10,dst=R30", inst: RORW, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x2d, 0xde, 0x1a}}, - {name: "src=R30,src2=R30,dst=RZR", inst: RORW, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x2f, 0xde, 0x1a}}, - {name: "src=R30,src2=R30,dst=R10", inst: RORW, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x2f, 0xde, 0x1a}}, - {name: "src=R30,src2=R30,dst=R30", inst: RORW, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x2f, 0xde, 0x1a}}, - {name: "src=RZR,src2=RZR,dst=RZR", inst: SDIV, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xf, 0xdf, 0x9a}}, - {name: "src=RZR,src2=RZR,dst=R10", inst: SDIV, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0xf, 0xdf, 0x9a}}, - {name: "src=RZR,src2=RZR,dst=R30", inst: SDIV, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0xf, 0xdf, 0x9a}}, - {name: "src=RZR,src2=R10,dst=RZR", inst: SDIV, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0xd, 0xdf, 0x9a}}, - {name: "src=RZR,src2=R10,dst=R10", inst: SDIV, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0xd, 0xdf, 0x9a}}, - {name: "src=RZR,src2=R10,dst=R30", inst: SDIV, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0xd, 0xdf, 0x9a}}, - {name: "src=RZR,src2=R30,dst=RZR", inst: SDIV, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0xf, 0xdf, 0x9a}}, - {name: "src=RZR,src2=R30,dst=R10", inst: SDIV, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0xf, 0xdf, 0x9a}}, - {name: "src=RZR,src2=R30,dst=R30", inst: SDIV, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0xf, 0xdf, 0x9a}}, - {name: "src=R10,src2=RZR,dst=RZR", inst: SDIV, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xf, 0xca, 0x9a}}, - {name: "src=R10,src2=RZR,dst=R10", inst: SDIV, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0xf, 0xca, 0x9a}}, - {name: "src=R10,src2=RZR,dst=R30", inst: SDIV, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0xf, 0xca, 0x9a}}, - {name: "src=R10,src2=R10,dst=RZR", inst: SDIV, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0xd, 0xca, 0x9a}}, - {name: "src=R10,src2=R10,dst=R10", inst: SDIV, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0xd, 0xca, 0x9a}}, - {name: "src=R10,src2=R10,dst=R30", inst: SDIV, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0xd, 0xca, 0x9a}}, - {name: "src=R10,src2=R30,dst=RZR", inst: SDIV, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0xf, 0xca, 0x9a}}, - {name: "src=R10,src2=R30,dst=R10", inst: SDIV, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0xf, 0xca, 0x9a}}, - {name: "src=R10,src2=R30,dst=R30", inst: SDIV, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0xf, 0xca, 0x9a}}, - {name: "src=R30,src2=RZR,dst=RZR", inst: SDIV, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xf, 0xde, 0x9a}}, - {name: "src=R30,src2=RZR,dst=R10", inst: SDIV, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0xf, 0xde, 0x9a}}, - {name: "src=R30,src2=RZR,dst=R30", inst: SDIV, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0xf, 0xde, 0x9a}}, - {name: "src=R30,src2=R10,dst=RZR", inst: SDIV, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0xd, 0xde, 0x9a}}, - {name: "src=R30,src2=R10,dst=R10", inst: SDIV, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0xd, 0xde, 0x9a}}, - {name: "src=R30,src2=R10,dst=R30", inst: SDIV, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0xd, 0xde, 0x9a}}, - {name: "src=R30,src2=R30,dst=RZR", inst: SDIV, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0xf, 0xde, 0x9a}}, - {name: "src=R30,src2=R30,dst=R10", inst: SDIV, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0xf, 0xde, 0x9a}}, - {name: "src=R30,src2=R30,dst=R30", inst: SDIV, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0xf, 0xde, 0x9a}}, - {name: "src=RZR,src2=RZR,dst=RZR", inst: SDIVW, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xf, 0xdf, 0x1a}}, - {name: "src=RZR,src2=RZR,dst=R10", inst: SDIVW, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0xf, 0xdf, 0x1a}}, - {name: "src=RZR,src2=RZR,dst=R30", inst: SDIVW, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0xf, 0xdf, 0x1a}}, - {name: "src=RZR,src2=R10,dst=RZR", inst: SDIVW, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0xd, 0xdf, 0x1a}}, - {name: "src=RZR,src2=R10,dst=R10", inst: SDIVW, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0xd, 0xdf, 0x1a}}, - {name: "src=RZR,src2=R10,dst=R30", inst: SDIVW, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0xd, 0xdf, 0x1a}}, - {name: "src=RZR,src2=R30,dst=RZR", inst: SDIVW, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0xf, 0xdf, 0x1a}}, - {name: "src=RZR,src2=R30,dst=R10", inst: SDIVW, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0xf, 0xdf, 0x1a}}, - {name: "src=RZR,src2=R30,dst=R30", inst: SDIVW, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0xf, 0xdf, 0x1a}}, - {name: "src=R10,src2=RZR,dst=RZR", inst: SDIVW, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xf, 0xca, 0x1a}}, - {name: "src=R10,src2=RZR,dst=R10", inst: SDIVW, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0xf, 0xca, 0x1a}}, - {name: "src=R10,src2=RZR,dst=R30", inst: SDIVW, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0xf, 0xca, 0x1a}}, - {name: "src=R10,src2=R10,dst=RZR", inst: SDIVW, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0xd, 0xca, 0x1a}}, - {name: "src=R10,src2=R10,dst=R10", inst: SDIVW, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0xd, 0xca, 0x1a}}, - {name: "src=R10,src2=R10,dst=R30", inst: SDIVW, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0xd, 0xca, 0x1a}}, - {name: "src=R10,src2=R30,dst=RZR", inst: SDIVW, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0xf, 0xca, 0x1a}}, - {name: "src=R10,src2=R30,dst=R10", inst: SDIVW, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0xf, 0xca, 0x1a}}, - {name: "src=R10,src2=R30,dst=R30", inst: SDIVW, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0xf, 0xca, 0x1a}}, - {name: "src=R30,src2=RZR,dst=RZR", inst: SDIVW, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xf, 0xde, 0x1a}}, - {name: "src=R30,src2=RZR,dst=R10", inst: SDIVW, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0xf, 0xde, 0x1a}}, - {name: "src=R30,src2=RZR,dst=R30", inst: SDIVW, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0xf, 0xde, 0x1a}}, - {name: "src=R30,src2=R10,dst=RZR", inst: SDIVW, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0xd, 0xde, 0x1a}}, - {name: "src=R30,src2=R10,dst=R10", inst: SDIVW, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0xd, 0xde, 0x1a}}, - {name: "src=R30,src2=R10,dst=R30", inst: SDIVW, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0xd, 0xde, 0x1a}}, - {name: "src=R30,src2=R30,dst=RZR", inst: SDIVW, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0xf, 0xde, 0x1a}}, - {name: "src=R30,src2=R30,dst=R10", inst: SDIVW, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0xf, 0xde, 0x1a}}, - {name: "src=R30,src2=R30,dst=R30", inst: SDIVW, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0xf, 0xde, 0x1a}}, - {name: "src=RZR,src2=RZR,dst=RZR", inst: UDIV, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xb, 0xdf, 0x9a}}, - {name: "src=RZR,src2=RZR,dst=R10", inst: UDIV, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0xb, 0xdf, 0x9a}}, - {name: "src=RZR,src2=RZR,dst=R30", inst: UDIV, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0xb, 0xdf, 0x9a}}, - {name: "src=RZR,src2=R10,dst=RZR", inst: UDIV, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x9, 0xdf, 0x9a}}, - {name: "src=RZR,src2=R10,dst=R10", inst: UDIV, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x9, 0xdf, 0x9a}}, - {name: "src=RZR,src2=R10,dst=R30", inst: UDIV, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x9, 0xdf, 0x9a}}, - {name: "src=RZR,src2=R30,dst=RZR", inst: UDIV, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0xb, 0xdf, 0x9a}}, - {name: "src=RZR,src2=R30,dst=R10", inst: UDIV, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0xb, 0xdf, 0x9a}}, - {name: "src=RZR,src2=R30,dst=R30", inst: UDIV, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0xb, 0xdf, 0x9a}}, - {name: "src=R10,src2=RZR,dst=RZR", inst: UDIV, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xb, 0xca, 0x9a}}, - {name: "src=R10,src2=RZR,dst=R10", inst: UDIV, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0xb, 0xca, 0x9a}}, - {name: "src=R10,src2=RZR,dst=R30", inst: UDIV, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0xb, 0xca, 0x9a}}, - {name: "src=R10,src2=R10,dst=RZR", inst: UDIV, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x9, 0xca, 0x9a}}, - {name: "src=R10,src2=R10,dst=R10", inst: UDIV, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x9, 0xca, 0x9a}}, - {name: "src=R10,src2=R10,dst=R30", inst: UDIV, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x9, 0xca, 0x9a}}, - {name: "src=R10,src2=R30,dst=RZR", inst: UDIV, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0xb, 0xca, 0x9a}}, - {name: "src=R10,src2=R30,dst=R10", inst: UDIV, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0xb, 0xca, 0x9a}}, - {name: "src=R10,src2=R30,dst=R30", inst: UDIV, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0xb, 0xca, 0x9a}}, - {name: "src=R30,src2=RZR,dst=RZR", inst: UDIV, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xb, 0xde, 0x9a}}, - {name: "src=R30,src2=RZR,dst=R10", inst: UDIV, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0xb, 0xde, 0x9a}}, - {name: "src=R30,src2=RZR,dst=R30", inst: UDIV, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0xb, 0xde, 0x9a}}, - {name: "src=R30,src2=R10,dst=RZR", inst: UDIV, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x9, 0xde, 0x9a}}, - {name: "src=R30,src2=R10,dst=R10", inst: UDIV, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x9, 0xde, 0x9a}}, - {name: "src=R30,src2=R10,dst=R30", inst: UDIV, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x9, 0xde, 0x9a}}, - {name: "src=R30,src2=R30,dst=RZR", inst: UDIV, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0xb, 0xde, 0x9a}}, - {name: "src=R30,src2=R30,dst=R10", inst: UDIV, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0xb, 0xde, 0x9a}}, - {name: "src=R30,src2=R30,dst=R30", inst: UDIV, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0xb, 0xde, 0x9a}}, - {name: "src=RZR,src2=RZR,dst=RZR", inst: UDIVW, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xb, 0xdf, 0x1a}}, - {name: "src=RZR,src2=RZR,dst=R10", inst: UDIVW, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0xb, 0xdf, 0x1a}}, - {name: "src=RZR,src2=RZR,dst=R30", inst: UDIVW, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0xb, 0xdf, 0x1a}}, - {name: "src=RZR,src2=R10,dst=RZR", inst: UDIVW, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x9, 0xdf, 0x1a}}, - {name: "src=RZR,src2=R10,dst=R10", inst: UDIVW, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x9, 0xdf, 0x1a}}, - {name: "src=RZR,src2=R10,dst=R30", inst: UDIVW, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x9, 0xdf, 0x1a}}, - {name: "src=RZR,src2=R30,dst=RZR", inst: UDIVW, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0xb, 0xdf, 0x1a}}, - {name: "src=RZR,src2=R30,dst=R10", inst: UDIVW, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0xb, 0xdf, 0x1a}}, - {name: "src=RZR,src2=R30,dst=R30", inst: UDIVW, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0xb, 0xdf, 0x1a}}, - {name: "src=R10,src2=RZR,dst=RZR", inst: UDIVW, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xb, 0xca, 0x1a}}, - {name: "src=R10,src2=RZR,dst=R10", inst: UDIVW, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0xb, 0xca, 0x1a}}, - {name: "src=R10,src2=RZR,dst=R30", inst: UDIVW, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0xb, 0xca, 0x1a}}, - {name: "src=R10,src2=R10,dst=RZR", inst: UDIVW, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x9, 0xca, 0x1a}}, - {name: "src=R10,src2=R10,dst=R10", inst: UDIVW, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x9, 0xca, 0x1a}}, - {name: "src=R10,src2=R10,dst=R30", inst: UDIVW, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x9, 0xca, 0x1a}}, - {name: "src=R10,src2=R30,dst=RZR", inst: UDIVW, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0xb, 0xca, 0x1a}}, - {name: "src=R10,src2=R30,dst=R10", inst: UDIVW, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0xb, 0xca, 0x1a}}, - {name: "src=R10,src2=R30,dst=R30", inst: UDIVW, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0xb, 0xca, 0x1a}}, - {name: "src=R30,src2=RZR,dst=RZR", inst: UDIVW, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xb, 0xde, 0x1a}}, - {name: "src=R30,src2=RZR,dst=R10", inst: UDIVW, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0xb, 0xde, 0x1a}}, - {name: "src=R30,src2=RZR,dst=R30", inst: UDIVW, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0xb, 0xde, 0x1a}}, - {name: "src=R30,src2=R10,dst=RZR", inst: UDIVW, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x9, 0xde, 0x1a}}, - {name: "src=R30,src2=R10,dst=R10", inst: UDIVW, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x9, 0xde, 0x1a}}, - {name: "src=R30,src2=R10,dst=R30", inst: UDIVW, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x9, 0xde, 0x1a}}, - {name: "src=R30,src2=R30,dst=RZR", inst: UDIVW, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0xb, 0xde, 0x1a}}, - {name: "src=R30,src2=R30,dst=R10", inst: UDIVW, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0xb, 0xde, 0x1a}}, - {name: "src=R30,src2=R30,dst=R30", inst: UDIVW, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0xb, 0xde, 0x1a}}, - {name: "src=RZR,src2=RZR,dst=RZR", inst: SUB, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0xcb}}, - {name: "src=RZR,src2=RZR,dst=R10", inst: SUB, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1f, 0xcb}}, - {name: "src=RZR,src2=RZR,dst=R30", inst: SUB, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1f, 0xcb}}, - {name: "src=RZR,src2=R10,dst=RZR", inst: SUB, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x1f, 0xcb}}, - {name: "src=RZR,src2=R10,dst=R10", inst: SUB, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1f, 0xcb}}, - {name: "src=RZR,src2=R10,dst=R30", inst: SUB, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x1f, 0xcb}}, - {name: "src=RZR,src2=R30,dst=RZR", inst: SUB, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x1f, 0xcb}}, - {name: "src=RZR,src2=R30,dst=R10", inst: SUB, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x1f, 0xcb}}, - {name: "src=RZR,src2=R30,dst=R30", inst: SUB, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1f, 0xcb}}, - {name: "src=R10,src2=RZR,dst=RZR", inst: SUB, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0xa, 0xcb}}, - {name: "src=R10,src2=RZR,dst=R10", inst: SUB, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0xa, 0xcb}}, - {name: "src=R10,src2=RZR,dst=R30", inst: SUB, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0xa, 0xcb}}, - {name: "src=R10,src2=R10,dst=RZR", inst: SUB, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0xa, 0xcb}}, - {name: "src=R10,src2=R10,dst=R10", inst: SUB, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0xa, 0xcb}}, - {name: "src=R10,src2=R10,dst=R30", inst: SUB, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0xa, 0xcb}}, - {name: "src=R10,src2=R30,dst=RZR", inst: SUB, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0xa, 0xcb}}, - {name: "src=R10,src2=R30,dst=R10", inst: SUB, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0xa, 0xcb}}, - {name: "src=R10,src2=R30,dst=R30", inst: SUB, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0xa, 0xcb}}, - {name: "src=R30,src2=RZR,dst=RZR", inst: SUB, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1e, 0xcb}}, - {name: "src=R30,src2=RZR,dst=R10", inst: SUB, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1e, 0xcb}}, - {name: "src=R30,src2=RZR,dst=R30", inst: SUB, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1e, 0xcb}}, - {name: "src=R30,src2=R10,dst=RZR", inst: SUB, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x1e, 0xcb}}, - {name: "src=R30,src2=R10,dst=R10", inst: SUB, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1e, 0xcb}}, - {name: "src=R30,src2=R10,dst=R30", inst: SUB, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x1e, 0xcb}}, - {name: "src=R30,src2=R30,dst=RZR", inst: SUB, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x1e, 0xcb}}, - {name: "src=R30,src2=R30,dst=R10", inst: SUB, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x1e, 0xcb}}, - {name: "src=R30,src2=R30,dst=R30", inst: SUB, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1e, 0xcb}}, - {name: "src=RZR,src2=RZR,dst=RZR", inst: SUBW, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0x4b}}, - {name: "src=RZR,src2=RZR,dst=R10", inst: SUBW, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1f, 0x4b}}, - {name: "src=RZR,src2=RZR,dst=R30", inst: SUBW, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1f, 0x4b}}, - {name: "src=RZR,src2=R10,dst=RZR", inst: SUBW, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x1f, 0x4b}}, - {name: "src=RZR,src2=R10,dst=R10", inst: SUBW, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1f, 0x4b}}, - {name: "src=RZR,src2=R10,dst=R30", inst: SUBW, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x1f, 0x4b}}, - {name: "src=RZR,src2=R30,dst=RZR", inst: SUBW, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x1f, 0x4b}}, - {name: "src=RZR,src2=R30,dst=R10", inst: SUBW, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x1f, 0x4b}}, - {name: "src=RZR,src2=R30,dst=R30", inst: SUBW, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1f, 0x4b}}, - {name: "src=R10,src2=RZR,dst=RZR", inst: SUBW, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0xa, 0x4b}}, - {name: "src=R10,src2=RZR,dst=R10", inst: SUBW, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0xa, 0x4b}}, - {name: "src=R10,src2=RZR,dst=R30", inst: SUBW, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0xa, 0x4b}}, - {name: "src=R10,src2=R10,dst=RZR", inst: SUBW, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0xa, 0x4b}}, - {name: "src=R10,src2=R10,dst=R10", inst: SUBW, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0xa, 0x4b}}, - {name: "src=R10,src2=R10,dst=R30", inst: SUBW, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0xa, 0x4b}}, - {name: "src=R10,src2=R30,dst=RZR", inst: SUBW, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0xa, 0x4b}}, - {name: "src=R10,src2=R30,dst=R10", inst: SUBW, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0xa, 0x4b}}, - {name: "src=R10,src2=R30,dst=R30", inst: SUBW, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0xa, 0x4b}}, - {name: "src=R30,src2=RZR,dst=RZR", inst: SUBW, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1e, 0x4b}}, - {name: "src=R30,src2=RZR,dst=R10", inst: SUBW, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1e, 0x4b}}, - {name: "src=R30,src2=RZR,dst=R30", inst: SUBW, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1e, 0x4b}}, - {name: "src=R30,src2=R10,dst=RZR", inst: SUBW, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x1e, 0x4b}}, - {name: "src=R30,src2=R10,dst=R10", inst: SUBW, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1e, 0x4b}}, - {name: "src=R30,src2=R10,dst=R30", inst: SUBW, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x1e, 0x4b}}, - {name: "src=R30,src2=R30,dst=RZR", inst: SUBW, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x1e, 0x4b}}, - {name: "src=R30,src2=R30,dst=R10", inst: SUBW, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x1e, 0x4b}}, - {name: "src=R30,src2=R30,dst=R30", inst: SUBW, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1e, 0x4b}}, - {name: "ldaddal xzr, xzr, [sp]", inst: LDADDALD, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0xff, 0xf8}}, - {name: "ldaddal xzr, x10, [sp]", inst: LDADDALD, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0xff, 0xf8}}, - {name: "ldaddal xzr, x30, [sp]", inst: LDADDALD, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0xff, 0xf8}}, - {name: "ldaddal xzr, xzr, [x10]", inst: LDADDALD, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0xff, 0xf8}}, - {name: "ldaddal xzr, x10, [x10]", inst: LDADDALD, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0xff, 0xf8}}, - {name: "ldaddal xzr, x30, [x10]", inst: LDADDALD, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0xff, 0xf8}}, - {name: "ldaddal xzr, xzr, [x30]", inst: LDADDALD, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0xff, 0xf8}}, - {name: "ldaddal xzr, x10, [x30]", inst: LDADDALD, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0xff, 0xf8}}, - {name: "ldaddal xzr, x30, [x30]", inst: LDADDALD, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0xff, 0xf8}}, - {name: "ldaddal x10, xzr, [sp]", inst: LDADDALD, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0xea, 0xf8}}, - {name: "ldaddal x10, x10, [sp]", inst: LDADDALD, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0xea, 0xf8}}, - {name: "ldaddal x10, x30, [sp]", inst: LDADDALD, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0xea, 0xf8}}, - {name: "ldaddal x10, xzr, [x10]", inst: LDADDALD, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0xea, 0xf8}}, - {name: "ldaddal x10, x10, [x10]", inst: LDADDALD, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0xea, 0xf8}}, - {name: "ldaddal x10, x30, [x10]", inst: LDADDALD, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0xea, 0xf8}}, - {name: "ldaddal x10, xzr, [x30]", inst: LDADDALD, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0xea, 0xf8}}, - {name: "ldaddal x10, x10, [x30]", inst: LDADDALD, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0xea, 0xf8}}, - {name: "ldaddal x10, x30, [x30]", inst: LDADDALD, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0xea, 0xf8}}, - {name: "ldaddal x30, xzr, [sp]", inst: LDADDALD, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0xfe, 0xf8}}, - {name: "ldaddal x30, x10, [sp]", inst: LDADDALD, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0xfe, 0xf8}}, - {name: "ldaddal x30, x30, [sp]", inst: LDADDALD, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0xfe, 0xf8}}, - {name: "ldaddal x30, xzr, [x10]", inst: LDADDALD, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0xfe, 0xf8}}, - {name: "ldaddal x30, x10, [x10]", inst: LDADDALD, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0xfe, 0xf8}}, - {name: "ldaddal x30, x30, [x10]", inst: LDADDALD, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0xfe, 0xf8}}, - {name: "ldaddal x30, xzr, [x30]", inst: LDADDALD, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0xfe, 0xf8}}, - {name: "ldaddal x30, x10, [x30]", inst: LDADDALD, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0xfe, 0xf8}}, - {name: "ldaddal x30, x30, [x30]", inst: LDADDALD, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0xfe, 0xf8}}, - {name: "ldaddal wzr, wzr, [sp]", inst: LDADDALW, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0xff, 0xb8}}, - {name: "ldaddal wzr, w10, [sp]", inst: LDADDALW, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0xff, 0xb8}}, - {name: "ldaddal wzr, w30, [sp]", inst: LDADDALW, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0xff, 0xb8}}, - {name: "ldaddal wzr, wzr, [x10]", inst: LDADDALW, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0xff, 0xb8}}, - {name: "ldaddal wzr, w10, [x10]", inst: LDADDALW, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0xff, 0xb8}}, - {name: "ldaddal wzr, w30, [x10]", inst: LDADDALW, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0xff, 0xb8}}, - {name: "ldaddal wzr, wzr, [x30]", inst: LDADDALW, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0xff, 0xb8}}, - {name: "ldaddal wzr, w10, [x30]", inst: LDADDALW, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0xff, 0xb8}}, - {name: "ldaddal wzr, w30, [x30]", inst: LDADDALW, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0xff, 0xb8}}, - {name: "ldaddal w10, wzr, [sp]", inst: LDADDALW, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0xea, 0xb8}}, - {name: "ldaddal w10, w10, [sp]", inst: LDADDALW, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0xea, 0xb8}}, - {name: "ldaddal w10, w30, [sp]", inst: LDADDALW, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0xea, 0xb8}}, - {name: "ldaddal w10, wzr, [x10]", inst: LDADDALW, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0xea, 0xb8}}, - {name: "ldaddal w10, w10, [x10]", inst: LDADDALW, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0xea, 0xb8}}, - {name: "ldaddal w10, w30, [x10]", inst: LDADDALW, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0xea, 0xb8}}, - {name: "ldaddal w10, wzr, [x30]", inst: LDADDALW, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0xea, 0xb8}}, - {name: "ldaddal w10, w10, [x30]", inst: LDADDALW, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0xea, 0xb8}}, - {name: "ldaddal w10, w30, [x30]", inst: LDADDALW, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0xea, 0xb8}}, - {name: "ldaddal w30, wzr, [sp]", inst: LDADDALW, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0xfe, 0xb8}}, - {name: "ldaddal w30, w10, [sp]", inst: LDADDALW, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0xfe, 0xb8}}, - {name: "ldaddal w30, w30, [sp]", inst: LDADDALW, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0xfe, 0xb8}}, - {name: "ldaddal w30, wzr, [x10]", inst: LDADDALW, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0xfe, 0xb8}}, - {name: "ldaddal w30, w10, [x10]", inst: LDADDALW, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0xfe, 0xb8}}, - {name: "ldaddal w30, w30, [x10]", inst: LDADDALW, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0xfe, 0xb8}}, - {name: "ldaddal w30, wzr, [x30]", inst: LDADDALW, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0xfe, 0xb8}}, - {name: "ldaddal w30, w10, [x30]", inst: LDADDALW, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0xfe, 0xb8}}, - {name: "ldaddal w30, w30, [x30]", inst: LDADDALW, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0xfe, 0xb8}}, - {name: "ldaddalh wzr, wzr, [sp]", inst: LDADDALH, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0xff, 0x78}}, - {name: "ldaddalh wzr, w10, [sp]", inst: LDADDALH, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0xff, 0x78}}, - {name: "ldaddalh wzr, w30, [sp]", inst: LDADDALH, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0xff, 0x78}}, - {name: "ldaddalh wzr, wzr, [x10]", inst: LDADDALH, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0xff, 0x78}}, - {name: "ldaddalh wzr, w10, [x10]", inst: LDADDALH, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0xff, 0x78}}, - {name: "ldaddalh wzr, w30, [x10]", inst: LDADDALH, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0xff, 0x78}}, - {name: "ldaddalh wzr, wzr, [x30]", inst: LDADDALH, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0xff, 0x78}}, - {name: "ldaddalh wzr, w10, [x30]", inst: LDADDALH, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0xff, 0x78}}, - {name: "ldaddalh wzr, w30, [x30]", inst: LDADDALH, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0xff, 0x78}}, - {name: "ldaddalh w10, wzr, [sp]", inst: LDADDALH, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0xea, 0x78}}, - {name: "ldaddalh w10, w10, [sp]", inst: LDADDALH, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0xea, 0x78}}, - {name: "ldaddalh w10, w30, [sp]", inst: LDADDALH, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0xea, 0x78}}, - {name: "ldaddalh w10, wzr, [x10]", inst: LDADDALH, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0xea, 0x78}}, - {name: "ldaddalh w10, w10, [x10]", inst: LDADDALH, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0xea, 0x78}}, - {name: "ldaddalh w10, w30, [x10]", inst: LDADDALH, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0xea, 0x78}}, - {name: "ldaddalh w10, wzr, [x30]", inst: LDADDALH, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0xea, 0x78}}, - {name: "ldaddalh w10, w10, [x30]", inst: LDADDALH, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0xea, 0x78}}, - {name: "ldaddalh w10, w30, [x30]", inst: LDADDALH, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0xea, 0x78}}, - {name: "ldaddalh w30, wzr, [sp]", inst: LDADDALH, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0xfe, 0x78}}, - {name: "ldaddalh w30, w10, [sp]", inst: LDADDALH, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0xfe, 0x78}}, - {name: "ldaddalh w30, w30, [sp]", inst: LDADDALH, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0xfe, 0x78}}, - {name: "ldaddalh w30, wzr, [x10]", inst: LDADDALH, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0xfe, 0x78}}, - {name: "ldaddalh w30, w10, [x10]", inst: LDADDALH, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0xfe, 0x78}}, - {name: "ldaddalh w30, w30, [x10]", inst: LDADDALH, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0xfe, 0x78}}, - {name: "ldaddalh w30, wzr, [x30]", inst: LDADDALH, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0xfe, 0x78}}, - {name: "ldaddalh w30, w10, [x30]", inst: LDADDALH, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0xfe, 0x78}}, - {name: "ldaddalh w30, w30, [x30]", inst: LDADDALH, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0xfe, 0x78}}, - {name: "ldaddalb wzr, wzr, [sp]", inst: LDADDALB, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0xff, 0x38}}, - {name: "ldaddalb wzr, w10, [sp]", inst: LDADDALB, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0xff, 0x38}}, - {name: "ldaddalb wzr, w30, [sp]", inst: LDADDALB, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0xff, 0x38}}, - {name: "ldaddalb wzr, wzr, [x10]", inst: LDADDALB, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0xff, 0x38}}, - {name: "ldaddalb wzr, w10, [x10]", inst: LDADDALB, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0xff, 0x38}}, - {name: "ldaddalb wzr, w30, [x10]", inst: LDADDALB, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0xff, 0x38}}, - {name: "ldaddalb wzr, wzr, [x30]", inst: LDADDALB, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0xff, 0x38}}, - {name: "ldaddalb wzr, w10, [x30]", inst: LDADDALB, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0xff, 0x38}}, - {name: "ldaddalb wzr, w30, [x30]", inst: LDADDALB, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0xff, 0x38}}, - {name: "ldaddalb w10, wzr, [sp]", inst: LDADDALB, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0xea, 0x38}}, - {name: "ldaddalb w10, w10, [sp]", inst: LDADDALB, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0xea, 0x38}}, - {name: "ldaddalb w10, w30, [sp]", inst: LDADDALB, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0xea, 0x38}}, - {name: "ldaddalb w10, wzr, [x10]", inst: LDADDALB, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0xea, 0x38}}, - {name: "ldaddalb w10, w10, [x10]", inst: LDADDALB, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0xea, 0x38}}, - {name: "ldaddalb w10, w30, [x10]", inst: LDADDALB, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0xea, 0x38}}, - {name: "ldaddalb w10, wzr, [x30]", inst: LDADDALB, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0xea, 0x38}}, - {name: "ldaddalb w10, w10, [x30]", inst: LDADDALB, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0xea, 0x38}}, - {name: "ldaddalb w10, w30, [x30]", inst: LDADDALB, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0xea, 0x38}}, - {name: "ldaddalb w30, wzr, [sp]", inst: LDADDALB, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0xfe, 0x38}}, - {name: "ldaddalb w30, w10, [sp]", inst: LDADDALB, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0xfe, 0x38}}, - {name: "ldaddalb w30, w30, [sp]", inst: LDADDALB, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0xfe, 0x38}}, - {name: "ldaddalb w30, wzr, [x10]", inst: LDADDALB, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0xfe, 0x38}}, - {name: "ldaddalb w30, w10, [x10]", inst: LDADDALB, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0xfe, 0x38}}, - {name: "ldaddalb w30, w30, [x10]", inst: LDADDALB, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0xfe, 0x38}}, - {name: "ldaddalb w30, wzr, [x30]", inst: LDADDALB, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0xfe, 0x38}}, - {name: "ldaddalb w30, w10, [x30]", inst: LDADDALB, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0xfe, 0x38}}, - {name: "ldaddalb w30, w30, [x30]", inst: LDADDALB, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0xfe, 0x38}}, - {name: "ldclral xzr, xzr, [sp]", inst: LDCLRALD, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x13, 0xff, 0xf8}}, - {name: "ldclral xzr, x10, [sp]", inst: LDCLRALD, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x13, 0xff, 0xf8}}, - {name: "ldclral xzr, x30, [sp]", inst: LDCLRALD, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x13, 0xff, 0xf8}}, - {name: "ldclral xzr, xzr, [x10]", inst: LDCLRALD, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x11, 0xff, 0xf8}}, - {name: "ldclral xzr, x10, [x10]", inst: LDCLRALD, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x11, 0xff, 0xf8}}, - {name: "ldclral xzr, x30, [x10]", inst: LDCLRALD, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x11, 0xff, 0xf8}}, - {name: "ldclral xzr, xzr, [x30]", inst: LDCLRALD, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x13, 0xff, 0xf8}}, - {name: "ldclral xzr, x10, [x30]", inst: LDCLRALD, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x13, 0xff, 0xf8}}, - {name: "ldclral xzr, x30, [x30]", inst: LDCLRALD, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x13, 0xff, 0xf8}}, - {name: "ldclral x10, xzr, [sp]", inst: LDCLRALD, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x13, 0xea, 0xf8}}, - {name: "ldclral x10, x10, [sp]", inst: LDCLRALD, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x13, 0xea, 0xf8}}, - {name: "ldclral x10, x30, [sp]", inst: LDCLRALD, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x13, 0xea, 0xf8}}, - {name: "ldclral x10, xzr, [x10]", inst: LDCLRALD, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x11, 0xea, 0xf8}}, - {name: "ldclral x10, x10, [x10]", inst: LDCLRALD, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x11, 0xea, 0xf8}}, - {name: "ldclral x10, x30, [x10]", inst: LDCLRALD, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x11, 0xea, 0xf8}}, - {name: "ldclral x10, xzr, [x30]", inst: LDCLRALD, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x13, 0xea, 0xf8}}, - {name: "ldclral x10, x10, [x30]", inst: LDCLRALD, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x13, 0xea, 0xf8}}, - {name: "ldclral x10, x30, [x30]", inst: LDCLRALD, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x13, 0xea, 0xf8}}, - {name: "ldclral x30, xzr, [sp]", inst: LDCLRALD, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x13, 0xfe, 0xf8}}, - {name: "ldclral x30, x10, [sp]", inst: LDCLRALD, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x13, 0xfe, 0xf8}}, - {name: "ldclral x30, x30, [sp]", inst: LDCLRALD, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x13, 0xfe, 0xf8}}, - {name: "ldclral x30, xzr, [x10]", inst: LDCLRALD, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x11, 0xfe, 0xf8}}, - {name: "ldclral x30, x10, [x10]", inst: LDCLRALD, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x11, 0xfe, 0xf8}}, - {name: "ldclral x30, x30, [x10]", inst: LDCLRALD, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x11, 0xfe, 0xf8}}, - {name: "ldclral x30, xzr, [x30]", inst: LDCLRALD, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x13, 0xfe, 0xf8}}, - {name: "ldclral x30, x10, [x30]", inst: LDCLRALD, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x13, 0xfe, 0xf8}}, - {name: "ldclral x30, x30, [x30]", inst: LDCLRALD, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x13, 0xfe, 0xf8}}, - {name: "ldclral wzr, wzr, [sp]", inst: LDCLRALW, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x13, 0xff, 0xb8}}, - {name: "ldclral wzr, w10, [sp]", inst: LDCLRALW, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x13, 0xff, 0xb8}}, - {name: "ldclral wzr, w30, [sp]", inst: LDCLRALW, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x13, 0xff, 0xb8}}, - {name: "ldclral wzr, wzr, [x10]", inst: LDCLRALW, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x11, 0xff, 0xb8}}, - {name: "ldclral wzr, w10, [x10]", inst: LDCLRALW, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x11, 0xff, 0xb8}}, - {name: "ldclral wzr, w30, [x10]", inst: LDCLRALW, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x11, 0xff, 0xb8}}, - {name: "ldclral wzr, wzr, [x30]", inst: LDCLRALW, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x13, 0xff, 0xb8}}, - {name: "ldclral wzr, w10, [x30]", inst: LDCLRALW, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x13, 0xff, 0xb8}}, - {name: "ldclral wzr, w30, [x30]", inst: LDCLRALW, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x13, 0xff, 0xb8}}, - {name: "ldclral w10, wzr, [sp]", inst: LDCLRALW, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x13, 0xea, 0xb8}}, - {name: "ldclral w10, w10, [sp]", inst: LDCLRALW, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x13, 0xea, 0xb8}}, - {name: "ldclral w10, w30, [sp]", inst: LDCLRALW, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x13, 0xea, 0xb8}}, - {name: "ldclral w10, wzr, [x10]", inst: LDCLRALW, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x11, 0xea, 0xb8}}, - {name: "ldclral w10, w10, [x10]", inst: LDCLRALW, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x11, 0xea, 0xb8}}, - {name: "ldclral w10, w30, [x10]", inst: LDCLRALW, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x11, 0xea, 0xb8}}, - {name: "ldclral w10, wzr, [x30]", inst: LDCLRALW, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x13, 0xea, 0xb8}}, - {name: "ldclral w10, w10, [x30]", inst: LDCLRALW, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x13, 0xea, 0xb8}}, - {name: "ldclral w10, w30, [x30]", inst: LDCLRALW, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x13, 0xea, 0xb8}}, - {name: "ldclral w30, wzr, [sp]", inst: LDCLRALW, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x13, 0xfe, 0xb8}}, - {name: "ldclral w30, w10, [sp]", inst: LDCLRALW, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x13, 0xfe, 0xb8}}, - {name: "ldclral w30, w30, [sp]", inst: LDCLRALW, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x13, 0xfe, 0xb8}}, - {name: "ldclral w30, wzr, [x10]", inst: LDCLRALW, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x11, 0xfe, 0xb8}}, - {name: "ldclral w30, w10, [x10]", inst: LDCLRALW, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x11, 0xfe, 0xb8}}, - {name: "ldclral w30, w30, [x10]", inst: LDCLRALW, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x11, 0xfe, 0xb8}}, - {name: "ldclral w30, wzr, [x30]", inst: LDCLRALW, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x13, 0xfe, 0xb8}}, - {name: "ldclral w30, w10, [x30]", inst: LDCLRALW, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x13, 0xfe, 0xb8}}, - {name: "ldclral w30, w30, [x30]", inst: LDCLRALW, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x13, 0xfe, 0xb8}}, - {name: "ldclralh wzr, wzr, [sp]", inst: LDCLRALH, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x13, 0xff, 0x78}}, - {name: "ldclralh wzr, w10, [sp]", inst: LDCLRALH, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x13, 0xff, 0x78}}, - {name: "ldclralh wzr, w30, [sp]", inst: LDCLRALH, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x13, 0xff, 0x78}}, - {name: "ldclralh wzr, wzr, [x10]", inst: LDCLRALH, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x11, 0xff, 0x78}}, - {name: "ldclralh wzr, w10, [x10]", inst: LDCLRALH, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x11, 0xff, 0x78}}, - {name: "ldclralh wzr, w30, [x10]", inst: LDCLRALH, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x11, 0xff, 0x78}}, - {name: "ldclralh wzr, wzr, [x30]", inst: LDCLRALH, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x13, 0xff, 0x78}}, - {name: "ldclralh wzr, w10, [x30]", inst: LDCLRALH, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x13, 0xff, 0x78}}, - {name: "ldclralh wzr, w30, [x30]", inst: LDCLRALH, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x13, 0xff, 0x78}}, - {name: "ldclralh w10, wzr, [sp]", inst: LDCLRALH, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x13, 0xea, 0x78}}, - {name: "ldclralh w10, w10, [sp]", inst: LDCLRALH, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x13, 0xea, 0x78}}, - {name: "ldclralh w10, w30, [sp]", inst: LDCLRALH, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x13, 0xea, 0x78}}, - {name: "ldclralh w10, wzr, [x10]", inst: LDCLRALH, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x11, 0xea, 0x78}}, - {name: "ldclralh w10, w10, [x10]", inst: LDCLRALH, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x11, 0xea, 0x78}}, - {name: "ldclralh w10, w30, [x10]", inst: LDCLRALH, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x11, 0xea, 0x78}}, - {name: "ldclralh w10, wzr, [x30]", inst: LDCLRALH, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x13, 0xea, 0x78}}, - {name: "ldclralh w10, w10, [x30]", inst: LDCLRALH, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x13, 0xea, 0x78}}, - {name: "ldclralh w10, w30, [x30]", inst: LDCLRALH, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x13, 0xea, 0x78}}, - {name: "ldclralh w30, wzr, [sp]", inst: LDCLRALH, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x13, 0xfe, 0x78}}, - {name: "ldclralh w30, w10, [sp]", inst: LDCLRALH, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x13, 0xfe, 0x78}}, - {name: "ldclralh w30, w30, [sp]", inst: LDCLRALH, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x13, 0xfe, 0x78}}, - {name: "ldclralh w30, wzr, [x10]", inst: LDCLRALH, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x11, 0xfe, 0x78}}, - {name: "ldclralh w30, w10, [x10]", inst: LDCLRALH, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x11, 0xfe, 0x78}}, - {name: "ldclralh w30, w30, [x10]", inst: LDCLRALH, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x11, 0xfe, 0x78}}, - {name: "ldclralh w30, wzr, [x30]", inst: LDCLRALH, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x13, 0xfe, 0x78}}, - {name: "ldclralh w30, w10, [x30]", inst: LDCLRALH, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x13, 0xfe, 0x78}}, - {name: "ldclralh w30, w30, [x30]", inst: LDCLRALH, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x13, 0xfe, 0x78}}, - {name: "ldclralb wzr, wzr, [sp]", inst: LDCLRALB, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x13, 0xff, 0x38}}, - {name: "ldclralb wzr, w10, [sp]", inst: LDCLRALB, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x13, 0xff, 0x38}}, - {name: "ldclralb wzr, w30, [sp]", inst: LDCLRALB, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x13, 0xff, 0x38}}, - {name: "ldclralb wzr, wzr, [x10]", inst: LDCLRALB, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x11, 0xff, 0x38}}, - {name: "ldclralb wzr, w10, [x10]", inst: LDCLRALB, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x11, 0xff, 0x38}}, - {name: "ldclralb wzr, w30, [x10]", inst: LDCLRALB, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x11, 0xff, 0x38}}, - {name: "ldclralb wzr, wzr, [x30]", inst: LDCLRALB, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x13, 0xff, 0x38}}, - {name: "ldclralb wzr, w10, [x30]", inst: LDCLRALB, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x13, 0xff, 0x38}}, - {name: "ldclralb wzr, w30, [x30]", inst: LDCLRALB, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x13, 0xff, 0x38}}, - {name: "ldclralb w10, wzr, [sp]", inst: LDCLRALB, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x13, 0xea, 0x38}}, - {name: "ldclralb w10, w10, [sp]", inst: LDCLRALB, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x13, 0xea, 0x38}}, - {name: "ldclralb w10, w30, [sp]", inst: LDCLRALB, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x13, 0xea, 0x38}}, - {name: "ldclralb w10, wzr, [x10]", inst: LDCLRALB, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x11, 0xea, 0x38}}, - {name: "ldclralb w10, w10, [x10]", inst: LDCLRALB, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x11, 0xea, 0x38}}, - {name: "ldclralb w10, w30, [x10]", inst: LDCLRALB, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x11, 0xea, 0x38}}, - {name: "ldclralb w10, wzr, [x30]", inst: LDCLRALB, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x13, 0xea, 0x38}}, - {name: "ldclralb w10, w10, [x30]", inst: LDCLRALB, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x13, 0xea, 0x38}}, - {name: "ldclralb w10, w30, [x30]", inst: LDCLRALB, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x13, 0xea, 0x38}}, - {name: "ldclralb w30, wzr, [sp]", inst: LDCLRALB, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x13, 0xfe, 0x38}}, - {name: "ldclralb w30, w10, [sp]", inst: LDCLRALB, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x13, 0xfe, 0x38}}, - {name: "ldclralb w30, w30, [sp]", inst: LDCLRALB, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x13, 0xfe, 0x38}}, - {name: "ldclralb w30, wzr, [x10]", inst: LDCLRALB, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x11, 0xfe, 0x38}}, - {name: "ldclralb w30, w10, [x10]", inst: LDCLRALB, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x11, 0xfe, 0x38}}, - {name: "ldclralb w30, w30, [x10]", inst: LDCLRALB, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x11, 0xfe, 0x38}}, - {name: "ldclralb w30, wzr, [x30]", inst: LDCLRALB, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x13, 0xfe, 0x38}}, - {name: "ldclralb w30, w10, [x30]", inst: LDCLRALB, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x13, 0xfe, 0x38}}, - {name: "ldclralb w30, w30, [x30]", inst: LDCLRALB, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x13, 0xfe, 0x38}}, - {name: "ldsetal xzr, xzr, [sp]", inst: LDSETALD, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x33, 0xff, 0xf8}}, - {name: "ldsetal xzr, x10, [sp]", inst: LDSETALD, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x33, 0xff, 0xf8}}, - {name: "ldsetal xzr, x30, [sp]", inst: LDSETALD, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x33, 0xff, 0xf8}}, - {name: "ldsetal xzr, xzr, [x10]", inst: LDSETALD, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x31, 0xff, 0xf8}}, - {name: "ldsetal xzr, x10, [x10]", inst: LDSETALD, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x31, 0xff, 0xf8}}, - {name: "ldsetal xzr, x30, [x10]", inst: LDSETALD, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x31, 0xff, 0xf8}}, - {name: "ldsetal xzr, xzr, [x30]", inst: LDSETALD, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x33, 0xff, 0xf8}}, - {name: "ldsetal xzr, x10, [x30]", inst: LDSETALD, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x33, 0xff, 0xf8}}, - {name: "ldsetal xzr, x30, [x30]", inst: LDSETALD, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x33, 0xff, 0xf8}}, - {name: "ldsetal x10, xzr, [sp]", inst: LDSETALD, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x33, 0xea, 0xf8}}, - {name: "ldsetal x10, x10, [sp]", inst: LDSETALD, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x33, 0xea, 0xf8}}, - {name: "ldsetal x10, x30, [sp]", inst: LDSETALD, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x33, 0xea, 0xf8}}, - {name: "ldsetal x10, xzr, [x10]", inst: LDSETALD, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x31, 0xea, 0xf8}}, - {name: "ldsetal x10, x10, [x10]", inst: LDSETALD, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x31, 0xea, 0xf8}}, - {name: "ldsetal x10, x30, [x10]", inst: LDSETALD, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x31, 0xea, 0xf8}}, - {name: "ldsetal x10, xzr, [x30]", inst: LDSETALD, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x33, 0xea, 0xf8}}, - {name: "ldsetal x10, x10, [x30]", inst: LDSETALD, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x33, 0xea, 0xf8}}, - {name: "ldsetal x10, x30, [x30]", inst: LDSETALD, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x33, 0xea, 0xf8}}, - {name: "ldsetal x30, xzr, [sp]", inst: LDSETALD, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x33, 0xfe, 0xf8}}, - {name: "ldsetal x30, x10, [sp]", inst: LDSETALD, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x33, 0xfe, 0xf8}}, - {name: "ldsetal x30, x30, [sp]", inst: LDSETALD, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x33, 0xfe, 0xf8}}, - {name: "ldsetal x30, xzr, [x10]", inst: LDSETALD, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x31, 0xfe, 0xf8}}, - {name: "ldsetal x30, x10, [x10]", inst: LDSETALD, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x31, 0xfe, 0xf8}}, - {name: "ldsetal x30, x30, [x10]", inst: LDSETALD, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x31, 0xfe, 0xf8}}, - {name: "ldsetal x30, xzr, [x30]", inst: LDSETALD, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x33, 0xfe, 0xf8}}, - {name: "ldsetal x30, x10, [x30]", inst: LDSETALD, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x33, 0xfe, 0xf8}}, - {name: "ldsetal x30, x30, [x30]", inst: LDSETALD, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x33, 0xfe, 0xf8}}, - {name: "ldsetal wzr, wzr, [sp]", inst: LDSETALW, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x33, 0xff, 0xb8}}, - {name: "ldsetal wzr, w10, [sp]", inst: LDSETALW, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x33, 0xff, 0xb8}}, - {name: "ldsetal wzr, w30, [sp]", inst: LDSETALW, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x33, 0xff, 0xb8}}, - {name: "ldsetal wzr, wzr, [x10]", inst: LDSETALW, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x31, 0xff, 0xb8}}, - {name: "ldsetal wzr, w10, [x10]", inst: LDSETALW, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x31, 0xff, 0xb8}}, - {name: "ldsetal wzr, w30, [x10]", inst: LDSETALW, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x31, 0xff, 0xb8}}, - {name: "ldsetal wzr, wzr, [x30]", inst: LDSETALW, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x33, 0xff, 0xb8}}, - {name: "ldsetal wzr, w10, [x30]", inst: LDSETALW, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x33, 0xff, 0xb8}}, - {name: "ldsetal wzr, w30, [x30]", inst: LDSETALW, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x33, 0xff, 0xb8}}, - {name: "ldsetal w10, wzr, [sp]", inst: LDSETALW, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x33, 0xea, 0xb8}}, - {name: "ldsetal w10, w10, [sp]", inst: LDSETALW, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x33, 0xea, 0xb8}}, - {name: "ldsetal w10, w30, [sp]", inst: LDSETALW, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x33, 0xea, 0xb8}}, - {name: "ldsetal w10, wzr, [x10]", inst: LDSETALW, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x31, 0xea, 0xb8}}, - {name: "ldsetal w10, w10, [x10]", inst: LDSETALW, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x31, 0xea, 0xb8}}, - {name: "ldsetal w10, w30, [x10]", inst: LDSETALW, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x31, 0xea, 0xb8}}, - {name: "ldsetal w10, wzr, [x30]", inst: LDSETALW, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x33, 0xea, 0xb8}}, - {name: "ldsetal w10, w10, [x30]", inst: LDSETALW, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x33, 0xea, 0xb8}}, - {name: "ldsetal w10, w30, [x30]", inst: LDSETALW, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x33, 0xea, 0xb8}}, - {name: "ldsetal w30, wzr, [sp]", inst: LDSETALW, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x33, 0xfe, 0xb8}}, - {name: "ldsetal w30, w10, [sp]", inst: LDSETALW, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x33, 0xfe, 0xb8}}, - {name: "ldsetal w30, w30, [sp]", inst: LDSETALW, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x33, 0xfe, 0xb8}}, - {name: "ldsetal w30, wzr, [x10]", inst: LDSETALW, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x31, 0xfe, 0xb8}}, - {name: "ldsetal w30, w10, [x10]", inst: LDSETALW, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x31, 0xfe, 0xb8}}, - {name: "ldsetal w30, w30, [x10]", inst: LDSETALW, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x31, 0xfe, 0xb8}}, - {name: "ldsetal w30, wzr, [x30]", inst: LDSETALW, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x33, 0xfe, 0xb8}}, - {name: "ldsetal w30, w10, [x30]", inst: LDSETALW, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x33, 0xfe, 0xb8}}, - {name: "ldsetal w30, w30, [x30]", inst: LDSETALW, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x33, 0xfe, 0xb8}}, - {name: "ldsetalh wzr, wzr, [sp]", inst: LDSETALH, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x33, 0xff, 0x78}}, - {name: "ldsetalh wzr, w10, [sp]", inst: LDSETALH, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x33, 0xff, 0x78}}, - {name: "ldsetalh wzr, w30, [sp]", inst: LDSETALH, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x33, 0xff, 0x78}}, - {name: "ldsetalh wzr, wzr, [x10]", inst: LDSETALH, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x31, 0xff, 0x78}}, - {name: "ldsetalh wzr, w10, [x10]", inst: LDSETALH, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x31, 0xff, 0x78}}, - {name: "ldsetalh wzr, w30, [x10]", inst: LDSETALH, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x31, 0xff, 0x78}}, - {name: "ldsetalh wzr, wzr, [x30]", inst: LDSETALH, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x33, 0xff, 0x78}}, - {name: "ldsetalh wzr, w10, [x30]", inst: LDSETALH, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x33, 0xff, 0x78}}, - {name: "ldsetalh wzr, w30, [x30]", inst: LDSETALH, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x33, 0xff, 0x78}}, - {name: "ldsetalh w10, wzr, [sp]", inst: LDSETALH, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x33, 0xea, 0x78}}, - {name: "ldsetalh w10, w10, [sp]", inst: LDSETALH, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x33, 0xea, 0x78}}, - {name: "ldsetalh w10, w30, [sp]", inst: LDSETALH, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x33, 0xea, 0x78}}, - {name: "ldsetalh w10, wzr, [x10]", inst: LDSETALH, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x31, 0xea, 0x78}}, - {name: "ldsetalh w10, w10, [x10]", inst: LDSETALH, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x31, 0xea, 0x78}}, - {name: "ldsetalh w10, w30, [x10]", inst: LDSETALH, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x31, 0xea, 0x78}}, - {name: "ldsetalh w10, wzr, [x30]", inst: LDSETALH, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x33, 0xea, 0x78}}, - {name: "ldsetalh w10, w10, [x30]", inst: LDSETALH, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x33, 0xea, 0x78}}, - {name: "ldsetalh w10, w30, [x30]", inst: LDSETALH, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x33, 0xea, 0x78}}, - {name: "ldsetalh w30, wzr, [sp]", inst: LDSETALH, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x33, 0xfe, 0x78}}, - {name: "ldsetalh w30, w10, [sp]", inst: LDSETALH, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x33, 0xfe, 0x78}}, - {name: "ldsetalh w30, w30, [sp]", inst: LDSETALH, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x33, 0xfe, 0x78}}, - {name: "ldsetalh w30, wzr, [x10]", inst: LDSETALH, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x31, 0xfe, 0x78}}, - {name: "ldsetalh w30, w10, [x10]", inst: LDSETALH, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x31, 0xfe, 0x78}}, - {name: "ldsetalh w30, w30, [x10]", inst: LDSETALH, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x31, 0xfe, 0x78}}, - {name: "ldsetalh w30, wzr, [x30]", inst: LDSETALH, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x33, 0xfe, 0x78}}, - {name: "ldsetalh w30, w10, [x30]", inst: LDSETALH, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x33, 0xfe, 0x78}}, - {name: "ldsetalh w30, w30, [x30]", inst: LDSETALH, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x33, 0xfe, 0x78}}, - {name: "ldsetalb wzr, wzr, [sp]", inst: LDSETALB, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x33, 0xff, 0x38}}, - {name: "ldsetalb wzr, w10, [sp]", inst: LDSETALB, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x33, 0xff, 0x38}}, - {name: "ldsetalb wzr, w30, [sp]", inst: LDSETALB, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x33, 0xff, 0x38}}, - {name: "ldsetalb wzr, wzr, [x10]", inst: LDSETALB, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x31, 0xff, 0x38}}, - {name: "ldsetalb wzr, w10, [x10]", inst: LDSETALB, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x31, 0xff, 0x38}}, - {name: "ldsetalb wzr, w30, [x10]", inst: LDSETALB, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x31, 0xff, 0x38}}, - {name: "ldsetalb wzr, wzr, [x30]", inst: LDSETALB, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x33, 0xff, 0x38}}, - {name: "ldsetalb wzr, w10, [x30]", inst: LDSETALB, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x33, 0xff, 0x38}}, - {name: "ldsetalb wzr, w30, [x30]", inst: LDSETALB, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x33, 0xff, 0x38}}, - {name: "ldsetalb w10, wzr, [sp]", inst: LDSETALB, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x33, 0xea, 0x38}}, - {name: "ldsetalb w10, w10, [sp]", inst: LDSETALB, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x33, 0xea, 0x38}}, - {name: "ldsetalb w10, w30, [sp]", inst: LDSETALB, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x33, 0xea, 0x38}}, - {name: "ldsetalb w10, wzr, [x10]", inst: LDSETALB, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x31, 0xea, 0x38}}, - {name: "ldsetalb w10, w10, [x10]", inst: LDSETALB, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x31, 0xea, 0x38}}, - {name: "ldsetalb w10, w30, [x10]", inst: LDSETALB, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x31, 0xea, 0x38}}, - {name: "ldsetalb w10, wzr, [x30]", inst: LDSETALB, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x33, 0xea, 0x38}}, - {name: "ldsetalb w10, w10, [x30]", inst: LDSETALB, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x33, 0xea, 0x38}}, - {name: "ldsetalb w10, w30, [x30]", inst: LDSETALB, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x33, 0xea, 0x38}}, - {name: "ldsetalb w30, wzr, [sp]", inst: LDSETALB, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x33, 0xfe, 0x38}}, - {name: "ldsetalb w30, w10, [sp]", inst: LDSETALB, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x33, 0xfe, 0x38}}, - {name: "ldsetalb w30, w30, [sp]", inst: LDSETALB, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x33, 0xfe, 0x38}}, - {name: "ldsetalb w30, wzr, [x10]", inst: LDSETALB, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x31, 0xfe, 0x38}}, - {name: "ldsetalb w30, w10, [x10]", inst: LDSETALB, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x31, 0xfe, 0x38}}, - {name: "ldsetalb w30, w30, [x10]", inst: LDSETALB, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x31, 0xfe, 0x38}}, - {name: "ldsetalb w30, wzr, [x30]", inst: LDSETALB, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x33, 0xfe, 0x38}}, - {name: "ldsetalb w30, w10, [x30]", inst: LDSETALB, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x33, 0xfe, 0x38}}, - {name: "ldsetalb w30, w30, [x30]", inst: LDSETALB, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x33, 0xfe, 0x38}}, - {name: "ldeoral xzr, xzr, [sp]", inst: LDEORALD, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x23, 0xff, 0xf8}}, - {name: "ldeoral xzr, x10, [sp]", inst: LDEORALD, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x23, 0xff, 0xf8}}, - {name: "ldeoral xzr, x30, [sp]", inst: LDEORALD, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x23, 0xff, 0xf8}}, - {name: "ldeoral xzr, xzr, [x10]", inst: LDEORALD, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x21, 0xff, 0xf8}}, - {name: "ldeoral xzr, x10, [x10]", inst: LDEORALD, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x21, 0xff, 0xf8}}, - {name: "ldeoral xzr, x30, [x10]", inst: LDEORALD, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x21, 0xff, 0xf8}}, - {name: "ldeoral xzr, xzr, [x30]", inst: LDEORALD, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x23, 0xff, 0xf8}}, - {name: "ldeoral xzr, x10, [x30]", inst: LDEORALD, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x23, 0xff, 0xf8}}, - {name: "ldeoral xzr, x30, [x30]", inst: LDEORALD, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x23, 0xff, 0xf8}}, - {name: "ldeoral x10, xzr, [sp]", inst: LDEORALD, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x23, 0xea, 0xf8}}, - {name: "ldeoral x10, x10, [sp]", inst: LDEORALD, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x23, 0xea, 0xf8}}, - {name: "ldeoral x10, x30, [sp]", inst: LDEORALD, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x23, 0xea, 0xf8}}, - {name: "ldeoral x10, xzr, [x10]", inst: LDEORALD, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x21, 0xea, 0xf8}}, - {name: "ldeoral x10, x10, [x10]", inst: LDEORALD, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x21, 0xea, 0xf8}}, - {name: "ldeoral x10, x30, [x10]", inst: LDEORALD, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x21, 0xea, 0xf8}}, - {name: "ldeoral x10, xzr, [x30]", inst: LDEORALD, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x23, 0xea, 0xf8}}, - {name: "ldeoral x10, x10, [x30]", inst: LDEORALD, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x23, 0xea, 0xf8}}, - {name: "ldeoral x10, x30, [x30]", inst: LDEORALD, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x23, 0xea, 0xf8}}, - {name: "ldeoral x30, xzr, [sp]", inst: LDEORALD, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x23, 0xfe, 0xf8}}, - {name: "ldeoral x30, x10, [sp]", inst: LDEORALD, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x23, 0xfe, 0xf8}}, - {name: "ldeoral x30, x30, [sp]", inst: LDEORALD, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x23, 0xfe, 0xf8}}, - {name: "ldeoral x30, xzr, [x10]", inst: LDEORALD, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x21, 0xfe, 0xf8}}, - {name: "ldeoral x30, x10, [x10]", inst: LDEORALD, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x21, 0xfe, 0xf8}}, - {name: "ldeoral x30, x30, [x10]", inst: LDEORALD, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x21, 0xfe, 0xf8}}, - {name: "ldeoral x30, xzr, [x30]", inst: LDEORALD, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x23, 0xfe, 0xf8}}, - {name: "ldeoral x30, x10, [x30]", inst: LDEORALD, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x23, 0xfe, 0xf8}}, - {name: "ldeoral x30, x30, [x30]", inst: LDEORALD, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x23, 0xfe, 0xf8}}, - {name: "ldeoral wzr, wzr, [sp]", inst: LDEORALW, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x23, 0xff, 0xb8}}, - {name: "ldeoral wzr, w10, [sp]", inst: LDEORALW, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x23, 0xff, 0xb8}}, - {name: "ldeoral wzr, w30, [sp]", inst: LDEORALW, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x23, 0xff, 0xb8}}, - {name: "ldeoral wzr, wzr, [x10]", inst: LDEORALW, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x21, 0xff, 0xb8}}, - {name: "ldeoral wzr, w10, [x10]", inst: LDEORALW, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x21, 0xff, 0xb8}}, - {name: "ldeoral wzr, w30, [x10]", inst: LDEORALW, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x21, 0xff, 0xb8}}, - {name: "ldeoral wzr, wzr, [x30]", inst: LDEORALW, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x23, 0xff, 0xb8}}, - {name: "ldeoral wzr, w10, [x30]", inst: LDEORALW, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x23, 0xff, 0xb8}}, - {name: "ldeoral wzr, w30, [x30]", inst: LDEORALW, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x23, 0xff, 0xb8}}, - {name: "ldeoral w10, wzr, [sp]", inst: LDEORALW, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x23, 0xea, 0xb8}}, - {name: "ldeoral w10, w10, [sp]", inst: LDEORALW, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x23, 0xea, 0xb8}}, - {name: "ldeoral w10, w30, [sp]", inst: LDEORALW, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x23, 0xea, 0xb8}}, - {name: "ldeoral w10, wzr, [x10]", inst: LDEORALW, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x21, 0xea, 0xb8}}, - {name: "ldeoral w10, w10, [x10]", inst: LDEORALW, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x21, 0xea, 0xb8}}, - {name: "ldeoral w10, w30, [x10]", inst: LDEORALW, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x21, 0xea, 0xb8}}, - {name: "ldeoral w10, wzr, [x30]", inst: LDEORALW, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x23, 0xea, 0xb8}}, - {name: "ldeoral w10, w10, [x30]", inst: LDEORALW, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x23, 0xea, 0xb8}}, - {name: "ldeoral w10, w30, [x30]", inst: LDEORALW, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x23, 0xea, 0xb8}}, - {name: "ldeoral w30, wzr, [sp]", inst: LDEORALW, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x23, 0xfe, 0xb8}}, - {name: "ldeoral w30, w10, [sp]", inst: LDEORALW, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x23, 0xfe, 0xb8}}, - {name: "ldeoral w30, w30, [sp]", inst: LDEORALW, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x23, 0xfe, 0xb8}}, - {name: "ldeoral w30, wzr, [x10]", inst: LDEORALW, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x21, 0xfe, 0xb8}}, - {name: "ldeoral w30, w10, [x10]", inst: LDEORALW, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x21, 0xfe, 0xb8}}, - {name: "ldeoral w30, w30, [x10]", inst: LDEORALW, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x21, 0xfe, 0xb8}}, - {name: "ldeoral w30, wzr, [x30]", inst: LDEORALW, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x23, 0xfe, 0xb8}}, - {name: "ldeoral w30, w10, [x30]", inst: LDEORALW, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x23, 0xfe, 0xb8}}, - {name: "ldeoral w30, w30, [x30]", inst: LDEORALW, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x23, 0xfe, 0xb8}}, - {name: "ldeoralh wzr, wzr, [sp]", inst: LDEORALH, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x23, 0xff, 0x78}}, - {name: "ldeoralh wzr, w10, [sp]", inst: LDEORALH, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x23, 0xff, 0x78}}, - {name: "ldeoralh wzr, w30, [sp]", inst: LDEORALH, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x23, 0xff, 0x78}}, - {name: "ldeoralh wzr, wzr, [x10]", inst: LDEORALH, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x21, 0xff, 0x78}}, - {name: "ldeoralh wzr, w10, [x10]", inst: LDEORALH, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x21, 0xff, 0x78}}, - {name: "ldeoralh wzr, w30, [x10]", inst: LDEORALH, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x21, 0xff, 0x78}}, - {name: "ldeoralh wzr, wzr, [x30]", inst: LDEORALH, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x23, 0xff, 0x78}}, - {name: "ldeoralh wzr, w10, [x30]", inst: LDEORALH, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x23, 0xff, 0x78}}, - {name: "ldeoralh wzr, w30, [x30]", inst: LDEORALH, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x23, 0xff, 0x78}}, - {name: "ldeoralh w10, wzr, [sp]", inst: LDEORALH, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x23, 0xea, 0x78}}, - {name: "ldeoralh w10, w10, [sp]", inst: LDEORALH, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x23, 0xea, 0x78}}, - {name: "ldeoralh w10, w30, [sp]", inst: LDEORALH, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x23, 0xea, 0x78}}, - {name: "ldeoralh w10, wzr, [x10]", inst: LDEORALH, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x21, 0xea, 0x78}}, - {name: "ldeoralh w10, w10, [x10]", inst: LDEORALH, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x21, 0xea, 0x78}}, - {name: "ldeoralh w10, w30, [x10]", inst: LDEORALH, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x21, 0xea, 0x78}}, - {name: "ldeoralh w10, wzr, [x30]", inst: LDEORALH, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x23, 0xea, 0x78}}, - {name: "ldeoralh w10, w10, [x30]", inst: LDEORALH, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x23, 0xea, 0x78}}, - {name: "ldeoralh w10, w30, [x30]", inst: LDEORALH, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x23, 0xea, 0x78}}, - {name: "ldeoralh w30, wzr, [sp]", inst: LDEORALH, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x23, 0xfe, 0x78}}, - {name: "ldeoralh w30, w10, [sp]", inst: LDEORALH, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x23, 0xfe, 0x78}}, - {name: "ldeoralh w30, w30, [sp]", inst: LDEORALH, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x23, 0xfe, 0x78}}, - {name: "ldeoralh w30, wzr, [x10]", inst: LDEORALH, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x21, 0xfe, 0x78}}, - {name: "ldeoralh w30, w10, [x10]", inst: LDEORALH, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x21, 0xfe, 0x78}}, - {name: "ldeoralh w30, w30, [x10]", inst: LDEORALH, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x21, 0xfe, 0x78}}, - {name: "ldeoralh w30, wzr, [x30]", inst: LDEORALH, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x23, 0xfe, 0x78}}, - {name: "ldeoralh w30, w10, [x30]", inst: LDEORALH, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x23, 0xfe, 0x78}}, - {name: "ldeoralh w30, w30, [x30]", inst: LDEORALH, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x23, 0xfe, 0x78}}, - {name: "ldeoralb wzr, wzr, [sp]", inst: LDEORALB, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x23, 0xff, 0x38}}, - {name: "ldeoralb wzr, w10, [sp]", inst: LDEORALB, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x23, 0xff, 0x38}}, - {name: "ldeoralb wzr, w30, [sp]", inst: LDEORALB, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x23, 0xff, 0x38}}, - {name: "ldeoralb wzr, wzr, [x10]", inst: LDEORALB, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x21, 0xff, 0x38}}, - {name: "ldeoralb wzr, w10, [x10]", inst: LDEORALB, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x21, 0xff, 0x38}}, - {name: "ldeoralb wzr, w30, [x10]", inst: LDEORALB, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x21, 0xff, 0x38}}, - {name: "ldeoralb wzr, wzr, [x30]", inst: LDEORALB, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x23, 0xff, 0x38}}, - {name: "ldeoralb wzr, w10, [x30]", inst: LDEORALB, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x23, 0xff, 0x38}}, - {name: "ldeoralb wzr, w30, [x30]", inst: LDEORALB, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x23, 0xff, 0x38}}, - {name: "ldeoralb w10, wzr, [sp]", inst: LDEORALB, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x23, 0xea, 0x38}}, - {name: "ldeoralb w10, w10, [sp]", inst: LDEORALB, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x23, 0xea, 0x38}}, - {name: "ldeoralb w10, w30, [sp]", inst: LDEORALB, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x23, 0xea, 0x38}}, - {name: "ldeoralb w10, wzr, [x10]", inst: LDEORALB, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x21, 0xea, 0x38}}, - {name: "ldeoralb w10, w10, [x10]", inst: LDEORALB, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x21, 0xea, 0x38}}, - {name: "ldeoralb w10, w30, [x10]", inst: LDEORALB, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x21, 0xea, 0x38}}, - {name: "ldeoralb w10, wzr, [x30]", inst: LDEORALB, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x23, 0xea, 0x38}}, - {name: "ldeoralb w10, w10, [x30]", inst: LDEORALB, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x23, 0xea, 0x38}}, - {name: "ldeoralb w10, w30, [x30]", inst: LDEORALB, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x23, 0xea, 0x38}}, - {name: "ldeoralb w30, wzr, [sp]", inst: LDEORALB, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x23, 0xfe, 0x38}}, - {name: "ldeoralb w30, w10, [sp]", inst: LDEORALB, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x23, 0xfe, 0x38}}, - {name: "ldeoralb w30, w30, [sp]", inst: LDEORALB, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x23, 0xfe, 0x38}}, - {name: "ldeoralb w30, wzr, [x10]", inst: LDEORALB, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x21, 0xfe, 0x38}}, - {name: "ldeoralb w30, w10, [x10]", inst: LDEORALB, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x21, 0xfe, 0x38}}, - {name: "ldeoralb w30, w30, [x10]", inst: LDEORALB, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x21, 0xfe, 0x38}}, - {name: "ldeoralb w30, wzr, [x30]", inst: LDEORALB, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x23, 0xfe, 0x38}}, - {name: "ldeoralb w30, w10, [x30]", inst: LDEORALB, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x23, 0xfe, 0x38}}, - {name: "ldeoralb w30, w30, [x30]", inst: LDEORALB, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x23, 0xfe, 0x38}}, - {name: "swpal xzr, xzr, [sp]", inst: SWPALD, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x83, 0xff, 0xf8}}, - {name: "swpal xzr, x10, [sp]", inst: SWPALD, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x83, 0xff, 0xf8}}, - {name: "swpal xzr, x30, [sp]", inst: SWPALD, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x83, 0xff, 0xf8}}, - {name: "swpal xzr, xzr, [x10]", inst: SWPALD, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x81, 0xff, 0xf8}}, - {name: "swpal xzr, x10, [x10]", inst: SWPALD, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x81, 0xff, 0xf8}}, - {name: "swpal xzr, x30, [x10]", inst: SWPALD, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x81, 0xff, 0xf8}}, - {name: "swpal xzr, xzr, [x30]", inst: SWPALD, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x83, 0xff, 0xf8}}, - {name: "swpal xzr, x10, [x30]", inst: SWPALD, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x83, 0xff, 0xf8}}, - {name: "swpal xzr, x30, [x30]", inst: SWPALD, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x83, 0xff, 0xf8}}, - {name: "swpal x10, xzr, [sp]", inst: SWPALD, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x83, 0xea, 0xf8}}, - {name: "swpal x10, x10, [sp]", inst: SWPALD, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x83, 0xea, 0xf8}}, - {name: "swpal x10, x30, [sp]", inst: SWPALD, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x83, 0xea, 0xf8}}, - {name: "swpal x10, xzr, [x10]", inst: SWPALD, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x81, 0xea, 0xf8}}, - {name: "swpal x10, x10, [x10]", inst: SWPALD, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x81, 0xea, 0xf8}}, - {name: "swpal x10, x30, [x10]", inst: SWPALD, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x81, 0xea, 0xf8}}, - {name: "swpal x10, xzr, [x30]", inst: SWPALD, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x83, 0xea, 0xf8}}, - {name: "swpal x10, x10, [x30]", inst: SWPALD, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x83, 0xea, 0xf8}}, - {name: "swpal x10, x30, [x30]", inst: SWPALD, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x83, 0xea, 0xf8}}, - {name: "swpal x30, xzr, [sp]", inst: SWPALD, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x83, 0xfe, 0xf8}}, - {name: "swpal x30, x10, [sp]", inst: SWPALD, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x83, 0xfe, 0xf8}}, - {name: "swpal x30, x30, [sp]", inst: SWPALD, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x83, 0xfe, 0xf8}}, - {name: "swpal x30, xzr, [x10]", inst: SWPALD, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x81, 0xfe, 0xf8}}, - {name: "swpal x30, x10, [x10]", inst: SWPALD, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x81, 0xfe, 0xf8}}, - {name: "swpal x30, x30, [x10]", inst: SWPALD, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x81, 0xfe, 0xf8}}, - {name: "swpal x30, xzr, [x30]", inst: SWPALD, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x83, 0xfe, 0xf8}}, - {name: "swpal x30, x10, [x30]", inst: SWPALD, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x83, 0xfe, 0xf8}}, - {name: "swpal x30, x30, [x30]", inst: SWPALD, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x83, 0xfe, 0xf8}}, - {name: "swpal wzr, wzr, [sp]", inst: SWPALW, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x83, 0xff, 0xb8}}, - {name: "swpal wzr, w10, [sp]", inst: SWPALW, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x83, 0xff, 0xb8}}, - {name: "swpal wzr, w30, [sp]", inst: SWPALW, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x83, 0xff, 0xb8}}, - {name: "swpal wzr, wzr, [x10]", inst: SWPALW, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x81, 0xff, 0xb8}}, - {name: "swpal wzr, w10, [x10]", inst: SWPALW, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x81, 0xff, 0xb8}}, - {name: "swpal wzr, w30, [x10]", inst: SWPALW, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x81, 0xff, 0xb8}}, - {name: "swpal wzr, wzr, [x30]", inst: SWPALW, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x83, 0xff, 0xb8}}, - {name: "swpal wzr, w10, [x30]", inst: SWPALW, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x83, 0xff, 0xb8}}, - {name: "swpal wzr, w30, [x30]", inst: SWPALW, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x83, 0xff, 0xb8}}, - {name: "swpal w10, wzr, [sp]", inst: SWPALW, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x83, 0xea, 0xb8}}, - {name: "swpal w10, w10, [sp]", inst: SWPALW, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x83, 0xea, 0xb8}}, - {name: "swpal w10, w30, [sp]", inst: SWPALW, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x83, 0xea, 0xb8}}, - {name: "swpal w10, wzr, [x10]", inst: SWPALW, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x81, 0xea, 0xb8}}, - {name: "swpal w10, w10, [x10]", inst: SWPALW, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x81, 0xea, 0xb8}}, - {name: "swpal w10, w30, [x10]", inst: SWPALW, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x81, 0xea, 0xb8}}, - {name: "swpal w10, wzr, [x30]", inst: SWPALW, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x83, 0xea, 0xb8}}, - {name: "swpal w10, w10, [x30]", inst: SWPALW, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x83, 0xea, 0xb8}}, - {name: "swpal w10, w30, [x30]", inst: SWPALW, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x83, 0xea, 0xb8}}, - {name: "swpal w30, wzr, [sp]", inst: SWPALW, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x83, 0xfe, 0xb8}}, - {name: "swpal w30, w10, [sp]", inst: SWPALW, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x83, 0xfe, 0xb8}}, - {name: "swpal w30, w30, [sp]", inst: SWPALW, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x83, 0xfe, 0xb8}}, - {name: "swpal w30, wzr, [x10]", inst: SWPALW, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x81, 0xfe, 0xb8}}, - {name: "swpal w30, w10, [x10]", inst: SWPALW, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x81, 0xfe, 0xb8}}, - {name: "swpal w30, w30, [x10]", inst: SWPALW, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x81, 0xfe, 0xb8}}, - {name: "swpal w30, wzr, [x30]", inst: SWPALW, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x83, 0xfe, 0xb8}}, - {name: "swpal w30, w10, [x30]", inst: SWPALW, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x83, 0xfe, 0xb8}}, - {name: "swpal w30, w30, [x30]", inst: SWPALW, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x83, 0xfe, 0xb8}}, - {name: "swpalh wzr, wzr, [sp]", inst: SWPALH, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x83, 0xff, 0x78}}, - {name: "swpalh wzr, w10, [sp]", inst: SWPALH, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x83, 0xff, 0x78}}, - {name: "swpalh wzr, w30, [sp]", inst: SWPALH, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x83, 0xff, 0x78}}, - {name: "swpalh wzr, wzr, [x10]", inst: SWPALH, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x81, 0xff, 0x78}}, - {name: "swpalh wzr, w10, [x10]", inst: SWPALH, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x81, 0xff, 0x78}}, - {name: "swpalh wzr, w30, [x10]", inst: SWPALH, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x81, 0xff, 0x78}}, - {name: "swpalh wzr, wzr, [x30]", inst: SWPALH, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x83, 0xff, 0x78}}, - {name: "swpalh wzr, w10, [x30]", inst: SWPALH, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x83, 0xff, 0x78}}, - {name: "swpalh wzr, w30, [x30]", inst: SWPALH, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x83, 0xff, 0x78}}, - {name: "swpalh w10, wzr, [sp]", inst: SWPALH, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x83, 0xea, 0x78}}, - {name: "swpalh w10, w10, [sp]", inst: SWPALH, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x83, 0xea, 0x78}}, - {name: "swpalh w10, w30, [sp]", inst: SWPALH, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x83, 0xea, 0x78}}, - {name: "swpalh w10, wzr, [x10]", inst: SWPALH, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x81, 0xea, 0x78}}, - {name: "swpalh w10, w10, [x10]", inst: SWPALH, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x81, 0xea, 0x78}}, - {name: "swpalh w10, w30, [x10]", inst: SWPALH, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x81, 0xea, 0x78}}, - {name: "swpalh w10, wzr, [x30]", inst: SWPALH, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x83, 0xea, 0x78}}, - {name: "swpalh w10, w10, [x30]", inst: SWPALH, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x83, 0xea, 0x78}}, - {name: "swpalh w10, w30, [x30]", inst: SWPALH, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x83, 0xea, 0x78}}, - {name: "swpalh w30, wzr, [sp]", inst: SWPALH, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x83, 0xfe, 0x78}}, - {name: "swpalh w30, w10, [sp]", inst: SWPALH, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x83, 0xfe, 0x78}}, - {name: "swpalh w30, w30, [sp]", inst: SWPALH, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x83, 0xfe, 0x78}}, - {name: "swpalh w30, wzr, [x10]", inst: SWPALH, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x81, 0xfe, 0x78}}, - {name: "swpalh w30, w10, [x10]", inst: SWPALH, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x81, 0xfe, 0x78}}, - {name: "swpalh w30, w30, [x10]", inst: SWPALH, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x81, 0xfe, 0x78}}, - {name: "swpalh w30, wzr, [x30]", inst: SWPALH, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x83, 0xfe, 0x78}}, - {name: "swpalh w30, w10, [x30]", inst: SWPALH, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x83, 0xfe, 0x78}}, - {name: "swpalh w30, w30, [x30]", inst: SWPALH, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x83, 0xfe, 0x78}}, - {name: "swpalb wzr, wzr, [sp]", inst: SWPALB, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x83, 0xff, 0x38}}, - {name: "swpalb wzr, w10, [sp]", inst: SWPALB, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x83, 0xff, 0x38}}, - {name: "swpalb wzr, w30, [sp]", inst: SWPALB, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x83, 0xff, 0x38}}, - {name: "swpalb wzr, wzr, [x10]", inst: SWPALB, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x81, 0xff, 0x38}}, - {name: "swpalb wzr, w10, [x10]", inst: SWPALB, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x81, 0xff, 0x38}}, - {name: "swpalb wzr, w30, [x10]", inst: SWPALB, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x81, 0xff, 0x38}}, - {name: "swpalb wzr, wzr, [x30]", inst: SWPALB, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x83, 0xff, 0x38}}, - {name: "swpalb wzr, w10, [x30]", inst: SWPALB, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x83, 0xff, 0x38}}, - {name: "swpalb wzr, w30, [x30]", inst: SWPALB, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x83, 0xff, 0x38}}, - {name: "swpalb w10, wzr, [sp]", inst: SWPALB, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x83, 0xea, 0x38}}, - {name: "swpalb w10, w10, [sp]", inst: SWPALB, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x83, 0xea, 0x38}}, - {name: "swpalb w10, w30, [sp]", inst: SWPALB, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x83, 0xea, 0x38}}, - {name: "swpalb w10, wzr, [x10]", inst: SWPALB, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x81, 0xea, 0x38}}, - {name: "swpalb w10, w10, [x10]", inst: SWPALB, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x81, 0xea, 0x38}}, - {name: "swpalb w10, w30, [x10]", inst: SWPALB, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x81, 0xea, 0x38}}, - {name: "swpalb w10, wzr, [x30]", inst: SWPALB, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x83, 0xea, 0x38}}, - {name: "swpalb w10, w10, [x30]", inst: SWPALB, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x83, 0xea, 0x38}}, - {name: "swpalb w10, w30, [x30]", inst: SWPALB, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x83, 0xea, 0x38}}, - {name: "swpalb w30, wzr, [sp]", inst: SWPALB, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x83, 0xfe, 0x38}}, - {name: "swpalb w30, w10, [sp]", inst: SWPALB, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x83, 0xfe, 0x38}}, - {name: "swpalb w30, w30, [sp]", inst: SWPALB, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x83, 0xfe, 0x38}}, - {name: "swpalb w30, wzr, [x10]", inst: SWPALB, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x81, 0xfe, 0x38}}, - {name: "swpalb w30, w10, [x10]", inst: SWPALB, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x81, 0xfe, 0x38}}, - {name: "swpalb w30, w30, [x10]", inst: SWPALB, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x81, 0xfe, 0x38}}, - {name: "swpalb w30, wzr, [x30]", inst: SWPALB, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x83, 0xfe, 0x38}}, - {name: "swpalb w30, w10, [x30]", inst: SWPALB, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x83, 0xfe, 0x38}}, - {name: "swpalb w30, w30, [x30]", inst: SWPALB, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x83, 0xfe, 0x38}}, - {name: "casal xzr, xzr, [sp]", inst: CASALD, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xff, 0xff, 0xc8}}, - {name: "casal xzr, x10, [sp]", inst: CASALD, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0xff, 0xff, 0xc8}}, - {name: "casal xzr, x30, [sp]", inst: CASALD, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0xff, 0xff, 0xc8}}, - {name: "casal xzr, xzr, [x10]", inst: CASALD, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0xfd, 0xff, 0xc8}}, - {name: "casal xzr, x10, [x10]", inst: CASALD, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0xfd, 0xff, 0xc8}}, - {name: "casal xzr, x30, [x10]", inst: CASALD, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0xfd, 0xff, 0xc8}}, - {name: "casal xzr, xzr, [x30]", inst: CASALD, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0xff, 0xff, 0xc8}}, - {name: "casal xzr, x10, [x30]", inst: CASALD, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0xff, 0xff, 0xc8}}, - {name: "casal xzr, x30, [x30]", inst: CASALD, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0xff, 0xff, 0xc8}}, - {name: "casal x10, xzr, [sp]", inst: CASALD, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xff, 0xea, 0xc8}}, - {name: "casal x10, x10, [sp]", inst: CASALD, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0xff, 0xea, 0xc8}}, - {name: "casal x10, x30, [sp]", inst: CASALD, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0xff, 0xea, 0xc8}}, - {name: "casal x10, xzr, [x10]", inst: CASALD, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0xfd, 0xea, 0xc8}}, - {name: "casal x10, x10, [x10]", inst: CASALD, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0xfd, 0xea, 0xc8}}, - {name: "casal x10, x30, [x10]", inst: CASALD, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0xfd, 0xea, 0xc8}}, - {name: "casal x10, xzr, [x30]", inst: CASALD, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0xff, 0xea, 0xc8}}, - {name: "casal x10, x10, [x30]", inst: CASALD, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0xff, 0xea, 0xc8}}, - {name: "casal x10, x30, [x30]", inst: CASALD, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0xff, 0xea, 0xc8}}, - {name: "casal x30, xzr, [sp]", inst: CASALD, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xff, 0xfe, 0xc8}}, - {name: "casal x30, x10, [sp]", inst: CASALD, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0xff, 0xfe, 0xc8}}, - {name: "casal x30, x30, [sp]", inst: CASALD, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0xff, 0xfe, 0xc8}}, - {name: "casal x30, xzr, [x10]", inst: CASALD, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0xfd, 0xfe, 0xc8}}, - {name: "casal x30, x10, [x10]", inst: CASALD, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0xfd, 0xfe, 0xc8}}, - {name: "casal x30, x30, [x10]", inst: CASALD, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0xfd, 0xfe, 0xc8}}, - {name: "casal x30, xzr, [x30]", inst: CASALD, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0xff, 0xfe, 0xc8}}, - {name: "casal x30, x10, [x30]", inst: CASALD, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0xff, 0xfe, 0xc8}}, - {name: "casal x30, x30, [x30]", inst: CASALD, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0xff, 0xfe, 0xc8}}, - {name: "casal wzr, wzr, [sp]", inst: CASALW, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xff, 0xff, 0x88}}, - {name: "casal wzr, w10, [sp]", inst: CASALW, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0xff, 0xff, 0x88}}, - {name: "casal wzr, w30, [sp]", inst: CASALW, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0xff, 0xff, 0x88}}, - {name: "casal wzr, wzr, [x10]", inst: CASALW, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0xfd, 0xff, 0x88}}, - {name: "casal wzr, w10, [x10]", inst: CASALW, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0xfd, 0xff, 0x88}}, - {name: "casal wzr, w30, [x10]", inst: CASALW, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0xfd, 0xff, 0x88}}, - {name: "casal wzr, wzr, [x30]", inst: CASALW, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0xff, 0xff, 0x88}}, - {name: "casal wzr, w10, [x30]", inst: CASALW, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0xff, 0xff, 0x88}}, - {name: "casal wzr, w30, [x30]", inst: CASALW, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0xff, 0xff, 0x88}}, - {name: "casal w10, wzr, [sp]", inst: CASALW, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xff, 0xea, 0x88}}, - {name: "casal w10, w10, [sp]", inst: CASALW, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0xff, 0xea, 0x88}}, - {name: "casal w10, w30, [sp]", inst: CASALW, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0xff, 0xea, 0x88}}, - {name: "casal w10, wzr, [x10]", inst: CASALW, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0xfd, 0xea, 0x88}}, - {name: "casal w10, w10, [x10]", inst: CASALW, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0xfd, 0xea, 0x88}}, - {name: "casal w10, w30, [x10]", inst: CASALW, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0xfd, 0xea, 0x88}}, - {name: "casal w10, wzr, [x30]", inst: CASALW, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0xff, 0xea, 0x88}}, - {name: "casal w10, w10, [x30]", inst: CASALW, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0xff, 0xea, 0x88}}, - {name: "casal w10, w30, [x30]", inst: CASALW, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0xff, 0xea, 0x88}}, - {name: "casal w30, wzr, [sp]", inst: CASALW, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xff, 0xfe, 0x88}}, - {name: "casal w30, w10, [sp]", inst: CASALW, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0xff, 0xfe, 0x88}}, - {name: "casal w30, w30, [sp]", inst: CASALW, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0xff, 0xfe, 0x88}}, - {name: "casal w30, wzr, [x10]", inst: CASALW, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0xfd, 0xfe, 0x88}}, - {name: "casal w30, w10, [x10]", inst: CASALW, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0xfd, 0xfe, 0x88}}, - {name: "casal w30, w30, [x10]", inst: CASALW, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0xfd, 0xfe, 0x88}}, - {name: "casal w30, wzr, [x30]", inst: CASALW, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0xff, 0xfe, 0x88}}, - {name: "casal w30, w10, [x30]", inst: CASALW, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0xff, 0xfe, 0x88}}, - {name: "casal w30, w30, [x30]", inst: CASALW, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0xff, 0xfe, 0x88}}, - {name: "casalh wzr, wzr, [sp]", inst: CASALH, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xff, 0xff, 0x48}}, - {name: "casalh wzr, w10, [sp]", inst: CASALH, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0xff, 0xff, 0x48}}, - {name: "casalh wzr, w30, [sp]", inst: CASALH, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0xff, 0xff, 0x48}}, - {name: "casalh wzr, wzr, [x10]", inst: CASALH, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0xfd, 0xff, 0x48}}, - {name: "casalh wzr, w10, [x10]", inst: CASALH, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0xfd, 0xff, 0x48}}, - {name: "casalh wzr, w30, [x10]", inst: CASALH, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0xfd, 0xff, 0x48}}, - {name: "casalh wzr, wzr, [x30]", inst: CASALH, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0xff, 0xff, 0x48}}, - {name: "casalh wzr, w10, [x30]", inst: CASALH, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0xff, 0xff, 0x48}}, - {name: "casalh wzr, w30, [x30]", inst: CASALH, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0xff, 0xff, 0x48}}, - {name: "casalh w10, wzr, [sp]", inst: CASALH, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xff, 0xea, 0x48}}, - {name: "casalh w10, w10, [sp]", inst: CASALH, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0xff, 0xea, 0x48}}, - {name: "casalh w10, w30, [sp]", inst: CASALH, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0xff, 0xea, 0x48}}, - {name: "casalh w10, wzr, [x10]", inst: CASALH, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0xfd, 0xea, 0x48}}, - {name: "casalh w10, w10, [x10]", inst: CASALH, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0xfd, 0xea, 0x48}}, - {name: "casalh w10, w30, [x10]", inst: CASALH, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0xfd, 0xea, 0x48}}, - {name: "casalh w10, wzr, [x30]", inst: CASALH, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0xff, 0xea, 0x48}}, - {name: "casalh w10, w10, [x30]", inst: CASALH, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0xff, 0xea, 0x48}}, - {name: "casalh w10, w30, [x30]", inst: CASALH, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0xff, 0xea, 0x48}}, - {name: "casalh w30, wzr, [sp]", inst: CASALH, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xff, 0xfe, 0x48}}, - {name: "casalh w30, w10, [sp]", inst: CASALH, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0xff, 0xfe, 0x48}}, - {name: "casalh w30, w30, [sp]", inst: CASALH, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0xff, 0xfe, 0x48}}, - {name: "casalh w30, wzr, [x10]", inst: CASALH, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0xfd, 0xfe, 0x48}}, - {name: "casalh w30, w10, [x10]", inst: CASALH, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0xfd, 0xfe, 0x48}}, - {name: "casalh w30, w30, [x10]", inst: CASALH, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0xfd, 0xfe, 0x48}}, - {name: "casalh w30, wzr, [x30]", inst: CASALH, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0xff, 0xfe, 0x48}}, - {name: "casalh w30, w10, [x30]", inst: CASALH, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0xff, 0xfe, 0x48}}, - {name: "casalh w30, w30, [x30]", inst: CASALH, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0xff, 0xfe, 0x48}}, - {name: "casalb wzr, wzr, [sp]", inst: CASALB, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xff, 0xff, 0x8}}, - {name: "casalb wzr, w10, [sp]", inst: CASALB, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0xff, 0xff, 0x8}}, - {name: "casalb wzr, w30, [sp]", inst: CASALB, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0xff, 0xff, 0x8}}, - {name: "casalb wzr, wzr, [x10]", inst: CASALB, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0xfd, 0xff, 0x8}}, - {name: "casalb wzr, w10, [x10]", inst: CASALB, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0xfd, 0xff, 0x8}}, - {name: "casalb wzr, w30, [x10]", inst: CASALB, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0xfd, 0xff, 0x8}}, - {name: "casalb wzr, wzr, [x30]", inst: CASALB, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0xff, 0xff, 0x8}}, - {name: "casalb wzr, w10, [x30]", inst: CASALB, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0xff, 0xff, 0x8}}, - {name: "casalb wzr, w30, [x30]", inst: CASALB, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0xff, 0xff, 0x8}}, - {name: "casalb w10, wzr, [sp]", inst: CASALB, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xff, 0xea, 0x8}}, - {name: "casalb w10, w10, [sp]", inst: CASALB, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0xff, 0xea, 0x8}}, - {name: "casalb w10, w30, [sp]", inst: CASALB, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0xff, 0xea, 0x8}}, - {name: "casalb w10, wzr, [x10]", inst: CASALB, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0xfd, 0xea, 0x8}}, - {name: "casalb w10, w10, [x10]", inst: CASALB, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0xfd, 0xea, 0x8}}, - {name: "casalb w10, w30, [x10]", inst: CASALB, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0xfd, 0xea, 0x8}}, - {name: "casalb w10, wzr, [x30]", inst: CASALB, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0xff, 0xea, 0x8}}, - {name: "casalb w10, w10, [x30]", inst: CASALB, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0xff, 0xea, 0x8}}, - {name: "casalb w10, w30, [x30]", inst: CASALB, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0xff, 0xea, 0x8}}, - {name: "casalb w30, wzr, [sp]", inst: CASALB, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xff, 0xfe, 0x8}}, - {name: "casalb w30, w10, [sp]", inst: CASALB, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0xff, 0xfe, 0x8}}, - {name: "casalb w30, w30, [sp]", inst: CASALB, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0xff, 0xfe, 0x8}}, - {name: "casalb w30, wzr, [x10]", inst: CASALB, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0xfd, 0xfe, 0x8}}, - {name: "casalb w30, w10, [x10]", inst: CASALB, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0xfd, 0xfe, 0x8}}, - {name: "casalb w30, w30, [x10]", inst: CASALB, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0xfd, 0xfe, 0x8}}, - {name: "casalb w30, wzr, [x30]", inst: CASALB, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0xff, 0xfe, 0x8}}, - {name: "casalb w30, w10, [x30]", inst: CASALB, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0xff, 0xfe, 0x8}}, - {name: "casalb w30, w30, [x30]", inst: CASALB, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0xff, 0xfe, 0x8}}, - {name: "src=V0,src2=V0,dst=V0", inst: FSUBD, src: RegV0, src2: RegV0, dst: RegV0, exp: []byte{0x0, 0x38, 0x60, 0x1e}}, - {name: "src=V0,src2=V0,dst=V31", inst: FSUBD, src: RegV0, src2: RegV0, dst: RegV31, exp: []byte{0x1f, 0x38, 0x60, 0x1e}}, - {name: "src=V0,src2=V31,dst=V0", inst: FSUBD, src: RegV0, src2: RegV31, dst: RegV0, exp: []byte{0xe0, 0x3b, 0x60, 0x1e}}, - {name: "src=V0,src2=V31,dst=V31", inst: FSUBD, src: RegV0, src2: RegV31, dst: RegV31, exp: []byte{0xff, 0x3b, 0x60, 0x1e}}, - {name: "src=V31,src2=V0,dst=V0", inst: FSUBD, src: RegV31, src2: RegV0, dst: RegV0, exp: []byte{0x0, 0x38, 0x7f, 0x1e}}, - {name: "src=V31,src2=V0,dst=V31", inst: FSUBD, src: RegV31, src2: RegV0, dst: RegV31, exp: []byte{0x1f, 0x38, 0x7f, 0x1e}}, - {name: "src=V31,src2=V31,dst=V0", inst: FSUBD, src: RegV31, src2: RegV31, dst: RegV0, exp: []byte{0xe0, 0x3b, 0x7f, 0x1e}}, - {name: "src=V31,src2=V31,dst=V31", inst: FSUBD, src: RegV31, src2: RegV31, dst: RegV31, exp: []byte{0xff, 0x3b, 0x7f, 0x1e}}, - {name: "src=V0,src2=V0,dst=V0", inst: FSUBS, src: RegV0, src2: RegV0, dst: RegV0, exp: []byte{0x0, 0x38, 0x20, 0x1e}}, - {name: "src=V0,src2=V0,dst=V31", inst: FSUBS, src: RegV0, src2: RegV0, dst: RegV31, exp: []byte{0x1f, 0x38, 0x20, 0x1e}}, - {name: "src=V0,src2=V31,dst=V0", inst: FSUBS, src: RegV0, src2: RegV31, dst: RegV0, exp: []byte{0xe0, 0x3b, 0x20, 0x1e}}, - {name: "src=V0,src2=V31,dst=V31", inst: FSUBS, src: RegV0, src2: RegV31, dst: RegV31, exp: []byte{0xff, 0x3b, 0x20, 0x1e}}, - {name: "src=V31,src2=V0,dst=V0", inst: FSUBS, src: RegV31, src2: RegV0, dst: RegV0, exp: []byte{0x0, 0x38, 0x3f, 0x1e}}, - {name: "src=V31,src2=V0,dst=V31", inst: FSUBS, src: RegV31, src2: RegV0, dst: RegV31, exp: []byte{0x1f, 0x38, 0x3f, 0x1e}}, - {name: "src=V31,src2=V31,dst=V0", inst: FSUBS, src: RegV31, src2: RegV31, dst: RegV0, exp: []byte{0xe0, 0x3b, 0x3f, 0x1e}}, - {name: "src=V31,src2=V31,dst=V31", inst: FSUBS, src: RegV31, src2: RegV31, dst: RegV31, exp: []byte{0xff, 0x3b, 0x3f, 0x1e}}, - } - - for _, tc := range tests { - t.Run(tc.name, func(t *testing.T) { - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - a := NewAssembler(asm.NilRegister) - buf := code.NextCodeSection() - err := a.encodeTwoRegistersToRegister(buf, &nodeImpl{instruction: tc.inst, srcReg: tc.src, srcReg2: tc.src2, dstReg: tc.dst}) - require.NoError(t, err) - - actual := buf.Bytes() - require.Equal(t, tc.exp, actual[:4]) - }) - } -} - -func TestAssemblerImpl_EncodeRegisterAndConstToNone(t *testing.T) { - t.Run("error", func(t *testing.T) { - tests := []struct { - n *nodeImpl - expErr string - }{ - { - n: &nodeImpl{ - instruction: ADR, types: operandTypesRegisterAndConstToNone, - srcReg: RegR0, srcReg2: RegR0, dstReg: RegR0, - }, - expErr: "ADR is unsupported for RegisterAndConstToNone type", - }, - { - n: &nodeImpl{ - instruction: CMP, types: operandTypesRegisterAndConstToNone, - srcReg: RegR0, srcConst: 12345, - }, - expErr: "immediate for CMP must fit in 0 to 4095 but got 12345", - }, - { - n: &nodeImpl{ - instruction: CMP, types: operandTypesRegisterAndConstToNone, - srcReg: RegRZR, srcConst: 123, - }, - expErr: "zero register is not supported for CMP (immediate)", - }, - } - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - for _, tt := range tests { - tc := tt - a := NewAssembler(asm.NilRegister) - buf := code.NextCodeSection() - err := a.encodeRegisterAndConstToNone(buf, tc.n) - require.EqualError(t, err, tc.expErr) - } - }) - - tests := []struct { - name string - exp []byte - c int64 - inst asm.Instruction - reg asm.Register - }{ - {name: "R1, 0", inst: CMP, reg: RegR1, c: 0, exp: []byte{0x3f, 0x0, 0x0, 0xf1}}, - {name: "R1, 10", inst: CMP, reg: RegR1, c: 10, exp: []byte{0x3f, 0x28, 0x0, 0xf1}}, - {name: "R1, 100", inst: CMP, reg: RegR1, c: 100, exp: []byte{0x3f, 0x90, 0x1, 0xf1}}, - {name: "R1, 300", inst: CMP, reg: RegR1, c: 300, exp: []byte{0x3f, 0xb0, 0x4, 0xf1}}, - {name: "R1, 4095", inst: CMP, reg: RegR1, c: 4095, exp: []byte{0x3f, 0xfc, 0x3f, 0xf1}}, - {name: "R10, 0", inst: CMP, reg: RegR10, c: 0, exp: []byte{0x5f, 0x1, 0x0, 0xf1}}, - {name: "R10, 10", inst: CMP, reg: RegR10, c: 10, exp: []byte{0x5f, 0x29, 0x0, 0xf1}}, - {name: "R10, 100", inst: CMP, reg: RegR10, c: 100, exp: []byte{0x5f, 0x91, 0x1, 0xf1}}, - {name: "R10, 300", inst: CMP, reg: RegR10, c: 300, exp: []byte{0x5f, 0xb1, 0x4, 0xf1}}, - {name: "R10, 4095", inst: CMP, reg: RegR10, c: 4095, exp: []byte{0x5f, 0xfd, 0x3f, 0xf1}}, - {name: "R30, 0", inst: CMP, reg: RegR30, c: 0, exp: []byte{0xdf, 0x3, 0x0, 0xf1}}, - {name: "R30, 10", inst: CMP, reg: RegR30, c: 10, exp: []byte{0xdf, 0x2b, 0x0, 0xf1}}, - {name: "R30, 100", inst: CMP, reg: RegR30, c: 100, exp: []byte{0xdf, 0x93, 0x1, 0xf1}}, - {name: "R30, 300", inst: CMP, reg: RegR30, c: 300, exp: []byte{0xdf, 0xb3, 0x4, 0xf1}}, - {name: "R30, 4095", inst: CMP, reg: RegR30, c: 4095, exp: []byte{0xdf, 0xff, 0x3f, 0xf1}}, - } - - for _, tc := range tests { - t.Run(tc.name, func(t *testing.T) { - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - a := NewAssembler(asm.NilRegister) - buf := code.NextCodeSection() - err := a.encodeRegisterAndConstToNone(buf, &nodeImpl{instruction: tc.inst, srcReg: tc.reg, srcConst: tc.c}) - require.NoError(t, err) - - actual := buf.Bytes() - require.Equal(t, tc.exp, actual[:4]) - }) - } -} - -func TestAssemblerImpl_EncodeRegisterToRegister(t *testing.T) { - t.Run("error", func(t *testing.T) { - tests := []struct { - n *nodeImpl - expErr string - }{ - { - n: &nodeImpl{ - instruction: ADR, types: operandTypesRegisterToRegister, - srcReg: RegR0, srcReg2: RegR0, dstReg: RegR0, - }, - expErr: "ADR is unsupported for RegisterToRegister type", - }, - } - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - for _, tt := range tests { - tc := tt - a := NewAssembler(asm.NilRegister) - buf := code.NextCodeSection() - err := a.encodeRegisterToRegister(buf, tc.n) - require.EqualError(t, err, tc.expErr) - } - }) - - tests := []struct { - name string - exp []byte - inst asm.Instruction - src asm.Register - dst asm.Register - }{ - {name: "MOV/src=RegSP,dst=R10", inst: MOVD, src: RegSP, dst: RegR10, exp: []byte{0xea, 0x3, 0x0, 0x91}}, - {name: "MOV/src=RegSP,dst=R30", inst: MOVD, src: RegSP, dst: RegR30, exp: []byte{0xfe, 0x3, 0x0, 0x91}}, - {name: "MOV/src=R10,dst=RegSP", inst: MOVD, src: RegR10, dst: RegSP, exp: []byte{0x5f, 0x1, 0x0, 0x91}}, - {name: "MOV/src=R10,dst=R10", inst: MOVD, src: RegR30, dst: RegSP, exp: []byte{0xdf, 0x3, 0x0, 0x91}}, - {name: "MOV/src=R10,dst=RegSP", inst: MOVD, src: RegSP, dst: RegSP, exp: []byte{0xff, 0x3, 0x0, 0x91}}, - {name: "ADD/src=RZR,dst=RZR", inst: ADD, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0x8b}}, - {name: "ADD/src=RZR,dst=R10", inst: ADD, src: RegRZR, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1f, 0x8b}}, - {name: "ADD/src=RZR,dst=R30", inst: ADD, src: RegRZR, dst: RegR30, exp: []byte{0xde, 0x3, 0x1f, 0x8b}}, - {name: "ADD/src=R10,dst=RZR", inst: ADD, src: RegR10, dst: RegRZR, exp: []byte{0xff, 0x3, 0xa, 0x8b}}, - {name: "ADD/src=R10,dst=R10", inst: ADD, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0xa, 0x8b}}, - {name: "ADD/src=R10,dst=R30", inst: ADD, src: RegR10, dst: RegR30, exp: []byte{0xde, 0x3, 0xa, 0x8b}}, - {name: "ADD/src=R30,dst=RZR", inst: ADD, src: RegR30, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1e, 0x8b}}, - {name: "ADD/src=R30,dst=R10", inst: ADD, src: RegR30, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1e, 0x8b}}, - {name: "ADD/src=R30,dst=R30", inst: ADD, src: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1e, 0x8b}}, - {name: "ADDW/src=RZR,dst=RZR", inst: ADDW, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0xb}}, - {name: "ADDW/src=RZR,dst=R10", inst: ADDW, src: RegRZR, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1f, 0xb}}, - {name: "ADDW/src=RZR,dst=R30", inst: ADDW, src: RegRZR, dst: RegR30, exp: []byte{0xde, 0x3, 0x1f, 0xb}}, - {name: "ADDW/src=R10,dst=RZR", inst: ADDW, src: RegR10, dst: RegRZR, exp: []byte{0xff, 0x3, 0xa, 0xb}}, - {name: "ADDW/src=R10,dst=R10", inst: ADDW, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0xa, 0xb}}, - {name: "ADDW/src=R10,dst=R30", inst: ADDW, src: RegR10, dst: RegR30, exp: []byte{0xde, 0x3, 0xa, 0xb}}, - {name: "ADDW/src=R30,dst=RZR", inst: ADDW, src: RegR30, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1e, 0xb}}, - {name: "ADDW/src=R30,dst=R10", inst: ADDW, src: RegR30, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1e, 0xb}}, - {name: "ADDW/src=R30,dst=R30", inst: ADDW, src: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1e, 0xb}}, - {name: "SUB/src=RZR,dst=RZR", inst: SUB, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0xcb}}, - {name: "SUB/src=RZR,dst=R10", inst: SUB, src: RegRZR, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1f, 0xcb}}, - {name: "SUB/src=RZR,dst=R30", inst: SUB, src: RegRZR, dst: RegR30, exp: []byte{0xde, 0x3, 0x1f, 0xcb}}, - {name: "SUB/src=R10,dst=RZR", inst: SUB, src: RegR10, dst: RegRZR, exp: []byte{0xff, 0x3, 0xa, 0xcb}}, - {name: "SUB/src=R10,dst=R10", inst: SUB, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0xa, 0xcb}}, - {name: "SUB/src=R10,dst=R30", inst: SUB, src: RegR10, dst: RegR30, exp: []byte{0xde, 0x3, 0xa, 0xcb}}, - {name: "SUB/src=R30,dst=RZR", inst: SUB, src: RegR30, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1e, 0xcb}}, - {name: "SUB/src=R30,dst=R10", inst: SUB, src: RegR30, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1e, 0xcb}}, - {name: "SUB/src=R30,dst=R30", inst: SUB, src: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1e, 0xcb}}, - {name: "CLZ/src=RZR,dst=RZR", inst: CLZ, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x13, 0xc0, 0xda}}, - {name: "CLZ/src=RZR,dst=R10", inst: CLZ, src: RegRZR, dst: RegR10, exp: []byte{0xea, 0x13, 0xc0, 0xda}}, - {name: "CLZ/src=RZR,dst=R30", inst: CLZ, src: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x13, 0xc0, 0xda}}, - {name: "CLZ/src=R10,dst=RZR", inst: CLZ, src: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x11, 0xc0, 0xda}}, - {name: "CLZ/src=R10,dst=R10", inst: CLZ, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0x11, 0xc0, 0xda}}, - {name: "CLZ/src=R10,dst=R30", inst: CLZ, src: RegR10, dst: RegR30, exp: []byte{0x5e, 0x11, 0xc0, 0xda}}, - {name: "CLZ/src=R30,dst=RZR", inst: CLZ, src: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x13, 0xc0, 0xda}}, - {name: "CLZ/src=R30,dst=R10", inst: CLZ, src: RegR30, dst: RegR10, exp: []byte{0xca, 0x13, 0xc0, 0xda}}, - {name: "CLZ/src=R30,dst=R30", inst: CLZ, src: RegR30, dst: RegR30, exp: []byte{0xde, 0x13, 0xc0, 0xda}}, - {name: "CLZW/src=RZR,dst=RZR", inst: CLZW, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x13, 0xc0, 0x5a}}, - {name: "CLZW/src=RZR,dst=R10", inst: CLZW, src: RegRZR, dst: RegR10, exp: []byte{0xea, 0x13, 0xc0, 0x5a}}, - {name: "CLZW/src=RZR,dst=R30", inst: CLZW, src: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x13, 0xc0, 0x5a}}, - {name: "CLZW/src=R10,dst=RZR", inst: CLZW, src: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x11, 0xc0, 0x5a}}, - {name: "CLZW/src=R10,dst=R10", inst: CLZW, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0x11, 0xc0, 0x5a}}, - {name: "CLZW/src=R10,dst=R30", inst: CLZW, src: RegR10, dst: RegR30, exp: []byte{0x5e, 0x11, 0xc0, 0x5a}}, - {name: "CLZW/src=R30,dst=RZR", inst: CLZW, src: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x13, 0xc0, 0x5a}}, - {name: "CLZW/src=R30,dst=R10", inst: CLZW, src: RegR30, dst: RegR10, exp: []byte{0xca, 0x13, 0xc0, 0x5a}}, - {name: "CLZW/src=R30,dst=R30", inst: CLZW, src: RegR30, dst: RegR30, exp: []byte{0xde, 0x13, 0xc0, 0x5a}}, - {name: "CSET/src=COND_EQ,dst=RZR", inst: CSET, src: RegCondEQ, dst: RegRZR, exp: []byte{0xff, 0x17, 0x9f, 0x9a}}, - {name: "CSET/src=COND_EQ,dst=R10", inst: CSET, src: RegCondEQ, dst: RegR10, exp: []byte{0xea, 0x17, 0x9f, 0x9a}}, - {name: "CSET/src=COND_EQ,dst=R30", inst: CSET, src: RegCondEQ, dst: RegR30, exp: []byte{0xfe, 0x17, 0x9f, 0x9a}}, - {name: "CSET/src=COND_NE,dst=RZR", inst: CSET, src: RegCondNE, dst: RegRZR, exp: []byte{0xff, 0x7, 0x9f, 0x9a}}, - {name: "CSET/src=COND_NE,dst=R10", inst: CSET, src: RegCondNE, dst: RegR10, exp: []byte{0xea, 0x7, 0x9f, 0x9a}}, - {name: "CSET/src=COND_NE,dst=R30", inst: CSET, src: RegCondNE, dst: RegR30, exp: []byte{0xfe, 0x7, 0x9f, 0x9a}}, - {name: "CSET/src=COND_HS,dst=RZR", inst: CSET, src: RegCondHS, dst: RegRZR, exp: []byte{0xff, 0x37, 0x9f, 0x9a}}, - {name: "CSET/src=COND_HS,dst=R10", inst: CSET, src: RegCondHS, dst: RegR10, exp: []byte{0xea, 0x37, 0x9f, 0x9a}}, - {name: "CSET/src=COND_HS,dst=R30", inst: CSET, src: RegCondHS, dst: RegR30, exp: []byte{0xfe, 0x37, 0x9f, 0x9a}}, - {name: "CSET/src=COND_LO,dst=RZR", inst: CSET, src: RegCondLO, dst: RegRZR, exp: []byte{0xff, 0x27, 0x9f, 0x9a}}, - {name: "CSET/src=COND_LO,dst=R10", inst: CSET, src: RegCondLO, dst: RegR10, exp: []byte{0xea, 0x27, 0x9f, 0x9a}}, - {name: "CSET/src=COND_LO,dst=R30", inst: CSET, src: RegCondLO, dst: RegR30, exp: []byte{0xfe, 0x27, 0x9f, 0x9a}}, - {name: "CSET/src=COND_MI,dst=RZR", inst: CSET, src: RegCondMI, dst: RegRZR, exp: []byte{0xff, 0x57, 0x9f, 0x9a}}, - {name: "CSET/src=COND_MI,dst=R10", inst: CSET, src: RegCondMI, dst: RegR10, exp: []byte{0xea, 0x57, 0x9f, 0x9a}}, - {name: "CSET/src=COND_MI,dst=R30", inst: CSET, src: RegCondMI, dst: RegR30, exp: []byte{0xfe, 0x57, 0x9f, 0x9a}}, - {name: "CSET/src=COND_PL,dst=RZR", inst: CSET, src: RegCondPL, dst: RegRZR, exp: []byte{0xff, 0x47, 0x9f, 0x9a}}, - {name: "CSET/src=COND_PL,dst=R10", inst: CSET, src: RegCondPL, dst: RegR10, exp: []byte{0xea, 0x47, 0x9f, 0x9a}}, - {name: "CSET/src=COND_PL,dst=R30", inst: CSET, src: RegCondPL, dst: RegR30, exp: []byte{0xfe, 0x47, 0x9f, 0x9a}}, - {name: "CSET/src=COND_VS,dst=RZR", inst: CSET, src: RegCondVS, dst: RegRZR, exp: []byte{0xff, 0x77, 0x9f, 0x9a}}, - {name: "CSET/src=COND_VS,dst=R10", inst: CSET, src: RegCondVS, dst: RegR10, exp: []byte{0xea, 0x77, 0x9f, 0x9a}}, - {name: "CSET/src=COND_VS,dst=R30", inst: CSET, src: RegCondVS, dst: RegR30, exp: []byte{0xfe, 0x77, 0x9f, 0x9a}}, - {name: "CSET/src=COND_VC,dst=RZR", inst: CSET, src: RegCondVC, dst: RegRZR, exp: []byte{0xff, 0x67, 0x9f, 0x9a}}, - {name: "CSET/src=COND_VC,dst=R10", inst: CSET, src: RegCondVC, dst: RegR10, exp: []byte{0xea, 0x67, 0x9f, 0x9a}}, - {name: "CSET/src=COND_VC,dst=R30", inst: CSET, src: RegCondVC, dst: RegR30, exp: []byte{0xfe, 0x67, 0x9f, 0x9a}}, - {name: "CSET/src=COND_HI,dst=RZR", inst: CSET, src: RegCondHI, dst: RegRZR, exp: []byte{0xff, 0x97, 0x9f, 0x9a}}, - {name: "CSET/src=COND_HI,dst=R10", inst: CSET, src: RegCondHI, dst: RegR10, exp: []byte{0xea, 0x97, 0x9f, 0x9a}}, - {name: "CSET/src=COND_HI,dst=R30", inst: CSET, src: RegCondHI, dst: RegR30, exp: []byte{0xfe, 0x97, 0x9f, 0x9a}}, - {name: "CSET/src=COND_LS,dst=RZR", inst: CSET, src: RegCondLS, dst: RegRZR, exp: []byte{0xff, 0x87, 0x9f, 0x9a}}, - {name: "CSET/src=COND_LS,dst=R10", inst: CSET, src: RegCondLS, dst: RegR10, exp: []byte{0xea, 0x87, 0x9f, 0x9a}}, - {name: "CSET/src=COND_LS,dst=R30", inst: CSET, src: RegCondLS, dst: RegR30, exp: []byte{0xfe, 0x87, 0x9f, 0x9a}}, - {name: "CSET/src=COND_GE,dst=RZR", inst: CSET, src: RegCondGE, dst: RegRZR, exp: []byte{0xff, 0xb7, 0x9f, 0x9a}}, - {name: "CSET/src=COND_GE,dst=R10", inst: CSET, src: RegCondGE, dst: RegR10, exp: []byte{0xea, 0xb7, 0x9f, 0x9a}}, - {name: "CSET/src=COND_GE,dst=R30", inst: CSET, src: RegCondGE, dst: RegR30, exp: []byte{0xfe, 0xb7, 0x9f, 0x9a}}, - {name: "CSET/src=COND_LT,dst=RZR", inst: CSET, src: RegCondLT, dst: RegRZR, exp: []byte{0xff, 0xa7, 0x9f, 0x9a}}, - {name: "CSET/src=COND_LT,dst=R10", inst: CSET, src: RegCondLT, dst: RegR10, exp: []byte{0xea, 0xa7, 0x9f, 0x9a}}, - {name: "CSET/src=COND_LT,dst=R30", inst: CSET, src: RegCondLT, dst: RegR30, exp: []byte{0xfe, 0xa7, 0x9f, 0x9a}}, - {name: "CSET/src=COND_GT,dst=RZR", inst: CSET, src: RegCondGT, dst: RegRZR, exp: []byte{0xff, 0xd7, 0x9f, 0x9a}}, - {name: "CSET/src=COND_GT,dst=R10", inst: CSET, src: RegCondGT, dst: RegR10, exp: []byte{0xea, 0xd7, 0x9f, 0x9a}}, - {name: "CSET/src=COND_GT,dst=R30", inst: CSET, src: RegCondGT, dst: RegR30, exp: []byte{0xfe, 0xd7, 0x9f, 0x9a}}, - {name: "CSET/src=COND_LE,dst=RZR", inst: CSET, src: RegCondLE, dst: RegRZR, exp: []byte{0xff, 0xc7, 0x9f, 0x9a}}, - {name: "CSET/src=COND_LE,dst=R10", inst: CSET, src: RegCondLE, dst: RegR10, exp: []byte{0xea, 0xc7, 0x9f, 0x9a}}, - {name: "CSET/src=COND_LE,dst=R30", inst: CSET, src: RegCondLE, dst: RegR30, exp: []byte{0xfe, 0xc7, 0x9f, 0x9a}}, - {name: "CSET/src=COND_AL,dst=RZR", inst: CSET, src: RegCondAL, dst: RegRZR, exp: []byte{0xff, 0xf7, 0x9f, 0x9a}}, - {name: "CSET/src=COND_AL,dst=R10", inst: CSET, src: RegCondAL, dst: RegR10, exp: []byte{0xea, 0xf7, 0x9f, 0x9a}}, - {name: "CSET/src=COND_AL,dst=R30", inst: CSET, src: RegCondAL, dst: RegR30, exp: []byte{0xfe, 0xf7, 0x9f, 0x9a}}, - {name: "CSET/src=COND_NV,dst=RZR", inst: CSET, src: RegCondNV, dst: RegRZR, exp: []byte{0xff, 0xe7, 0x9f, 0x9a}}, - {name: "CSET/src=COND_NV,dst=R10", inst: CSET, src: RegCondNV, dst: RegR10, exp: []byte{0xea, 0xe7, 0x9f, 0x9a}}, - {name: "CSET/src=COND_NV,dst=R30", inst: CSET, src: RegCondNV, dst: RegR30, exp: []byte{0xfe, 0xe7, 0x9f, 0x9a}}, - {name: "FABSS/src=V0,dst=V0", inst: FABSS, src: RegV0, dst: RegV0, exp: []byte{0x0, 0xc0, 0x20, 0x1e}}, - {name: "FABSS/src=V0,dst=V31", inst: FABSS, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0xc0, 0x20, 0x1e}}, - {name: "FABSS/src=V31,dst=V0", inst: FABSS, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0xc3, 0x20, 0x1e}}, - {name: "FABSS/src=V31,dst=V31", inst: FABSS, src: RegV31, dst: RegV31, exp: []byte{0xff, 0xc3, 0x20, 0x1e}}, - {name: "FABSD/src=V0,dst=V0", inst: FABSD, src: RegV0, dst: RegV0, exp: []byte{0x0, 0xc0, 0x60, 0x1e}}, - {name: "FABSD/src=V0,dst=V31", inst: FABSD, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0xc0, 0x60, 0x1e}}, - {name: "FABSD/src=V31,dst=V0", inst: FABSD, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0xc3, 0x60, 0x1e}}, - {name: "FABSD/src=V31,dst=V31", inst: FABSD, src: RegV31, dst: RegV31, exp: []byte{0xff, 0xc3, 0x60, 0x1e}}, - {name: "FNEGS/src=V0,dst=V0", inst: FNEGS, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x40, 0x21, 0x1e}}, - {name: "FNEGS/src=V0,dst=V31", inst: FNEGS, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0x40, 0x21, 0x1e}}, - {name: "FNEGS/src=V31,dst=V0", inst: FNEGS, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0x43, 0x21, 0x1e}}, - {name: "FNEGS/src=V31,dst=V31", inst: FNEGS, src: RegV31, dst: RegV31, exp: []byte{0xff, 0x43, 0x21, 0x1e}}, - {name: "FNEGD/src=V0,dst=V0", inst: FNEGD, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x40, 0x61, 0x1e}}, - {name: "FNEGD/src=V0,dst=V31", inst: FNEGD, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0x40, 0x61, 0x1e}}, - {name: "FNEGD/src=V31,dst=V0", inst: FNEGD, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0x43, 0x61, 0x1e}}, - {name: "FNEGD/src=V31,dst=V31", inst: FNEGD, src: RegV31, dst: RegV31, exp: []byte{0xff, 0x43, 0x61, 0x1e}}, - {name: "FSQRTD/src=V0,dst=V0", inst: FSQRTD, src: RegV0, dst: RegV0, exp: []byte{0x0, 0xc0, 0x61, 0x1e}}, - {name: "FSQRTD/src=V0,dst=V31", inst: FSQRTD, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0xc0, 0x61, 0x1e}}, - {name: "FSQRTD/src=V31,dst=V0", inst: FSQRTD, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0xc3, 0x61, 0x1e}}, - {name: "FSQRTD/src=V31,dst=V31", inst: FSQRTD, src: RegV31, dst: RegV31, exp: []byte{0xff, 0xc3, 0x61, 0x1e}}, - {name: "FSQRTS/src=V0,dst=V0", inst: FSQRTS, src: RegV0, dst: RegV0, exp: []byte{0x0, 0xc0, 0x21, 0x1e}}, - {name: "FSQRTS/src=V0,dst=V31", inst: FSQRTS, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0xc0, 0x21, 0x1e}}, - {name: "FSQRTS/src=V31,dst=V0", inst: FSQRTS, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0xc3, 0x21, 0x1e}}, - {name: "FSQRTS/src=V31,dst=V31", inst: FSQRTS, src: RegV31, dst: RegV31, exp: []byte{0xff, 0xc3, 0x21, 0x1e}}, - {name: "FCVTDS/src=V0,dst=V0", inst: FCVTDS, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x40, 0x62, 0x1e}}, - {name: "FCVTDS/src=V0,dst=V31", inst: FCVTDS, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0x40, 0x62, 0x1e}}, - {name: "FCVTDS/src=V31,dst=V0", inst: FCVTDS, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0x43, 0x62, 0x1e}}, - {name: "FCVTDS/src=V31,dst=V31", inst: FCVTDS, src: RegV31, dst: RegV31, exp: []byte{0xff, 0x43, 0x62, 0x1e}}, - {name: "FCVTSD/src=V0,dst=V0", inst: FCVTSD, src: RegV0, dst: RegV0, exp: []byte{0x0, 0xc0, 0x22, 0x1e}}, - {name: "FCVTSD/src=V0,dst=V31", inst: FCVTSD, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0xc0, 0x22, 0x1e}}, - {name: "FCVTSD/src=V31,dst=V0", inst: FCVTSD, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0xc3, 0x22, 0x1e}}, - {name: "FCVTSD/src=V31,dst=V31", inst: FCVTSD, src: RegV31, dst: RegV31, exp: []byte{0xff, 0xc3, 0x22, 0x1e}}, - {name: "FRINTMD/src=V0,dst=V0", inst: FRINTMD, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x40, 0x65, 0x1e}}, - {name: "FRINTMD/src=V0,dst=V31", inst: FRINTMD, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0x40, 0x65, 0x1e}}, - {name: "FRINTMD/src=V31,dst=V0", inst: FRINTMD, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0x43, 0x65, 0x1e}}, - {name: "FRINTMD/src=V31,dst=V31", inst: FRINTMD, src: RegV31, dst: RegV31, exp: []byte{0xff, 0x43, 0x65, 0x1e}}, - {name: "FRINTMS/src=V0,dst=V0", inst: FRINTMS, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x40, 0x25, 0x1e}}, - {name: "FRINTMS/src=V0,dst=V31", inst: FRINTMS, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0x40, 0x25, 0x1e}}, - {name: "FRINTMS/src=V31,dst=V0", inst: FRINTMS, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0x43, 0x25, 0x1e}}, - {name: "FRINTMS/src=V31,dst=V31", inst: FRINTMS, src: RegV31, dst: RegV31, exp: []byte{0xff, 0x43, 0x25, 0x1e}}, - {name: "FRINTND/src=V0,dst=V0", inst: FRINTND, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x40, 0x64, 0x1e}}, - {name: "FRINTND/src=V0,dst=V31", inst: FRINTND, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0x40, 0x64, 0x1e}}, - {name: "FRINTND/src=V31,dst=V0", inst: FRINTND, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0x43, 0x64, 0x1e}}, - {name: "FRINTND/src=V31,dst=V31", inst: FRINTND, src: RegV31, dst: RegV31, exp: []byte{0xff, 0x43, 0x64, 0x1e}}, - {name: "FRINTNS/src=V0,dst=V0", inst: FRINTNS, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x40, 0x24, 0x1e}}, - {name: "FRINTNS/src=V0,dst=V31", inst: FRINTNS, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0x40, 0x24, 0x1e}}, - {name: "FRINTNS/src=V31,dst=V0", inst: FRINTNS, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0x43, 0x24, 0x1e}}, - {name: "FRINTNS/src=V31,dst=V31", inst: FRINTNS, src: RegV31, dst: RegV31, exp: []byte{0xff, 0x43, 0x24, 0x1e}}, - {name: "FRINTPD/src=V0,dst=V0", inst: FRINTPD, src: RegV0, dst: RegV0, exp: []byte{0x0, 0xc0, 0x64, 0x1e}}, - {name: "FRINTPD/src=V0,dst=V31", inst: FRINTPD, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0xc0, 0x64, 0x1e}}, - {name: "FRINTPD/src=V31,dst=V0", inst: FRINTPD, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0xc3, 0x64, 0x1e}}, - {name: "FRINTPD/src=V31,dst=V31", inst: FRINTPD, src: RegV31, dst: RegV31, exp: []byte{0xff, 0xc3, 0x64, 0x1e}}, - {name: "FRINTPS/src=V0,dst=V0", inst: FRINTPS, src: RegV0, dst: RegV0, exp: []byte{0x0, 0xc0, 0x24, 0x1e}}, - {name: "FRINTPS/src=V0,dst=V31", inst: FRINTPS, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0xc0, 0x24, 0x1e}}, - {name: "FRINTPS/src=V31,dst=V0", inst: FRINTPS, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0xc3, 0x24, 0x1e}}, - {name: "FRINTPS/src=V31,dst=V31", inst: FRINTPS, src: RegV31, dst: RegV31, exp: []byte{0xff, 0xc3, 0x24, 0x1e}}, - {name: "FRINTZD/src=V0,dst=V0", inst: FRINTZD, src: RegV0, dst: RegV0, exp: []byte{0x0, 0xc0, 0x65, 0x1e}}, - {name: "FRINTZD/src=V0,dst=V31", inst: FRINTZD, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0xc0, 0x65, 0x1e}}, - {name: "FRINTZD/src=V31,dst=V0", inst: FRINTZD, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0xc3, 0x65, 0x1e}}, - {name: "FRINTZD/src=V31,dst=V31", inst: FRINTZD, src: RegV31, dst: RegV31, exp: []byte{0xff, 0xc3, 0x65, 0x1e}}, - {name: "FRINTZS/src=V0,dst=V0", inst: FRINTZS, src: RegV0, dst: RegV0, exp: []byte{0x0, 0xc0, 0x25, 0x1e}}, - {name: "FRINTZS/src=V0,dst=V31", inst: FRINTZS, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0xc0, 0x25, 0x1e}}, - {name: "FRINTZS/src=V31,dst=V0", inst: FRINTZS, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0xc3, 0x25, 0x1e}}, - {name: "FRINTZS/src=V31,dst=V31", inst: FRINTZS, src: RegV31, dst: RegV31, exp: []byte{0xff, 0xc3, 0x25, 0x1e}}, - {name: "FDIVS/src=V0,dst=V0", inst: FDIVS, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x18, 0x20, 0x1e}}, - {name: "FDIVS/src=V0,dst=V31", inst: FDIVS, src: RegV0, dst: RegV31, exp: []byte{0xff, 0x1b, 0x20, 0x1e}}, - {name: "FDIVS/src=V31,dst=V0", inst: FDIVS, src: RegV31, dst: RegV0, exp: []byte{0x0, 0x18, 0x3f, 0x1e}}, - {name: "FDIVS/src=V31,dst=V31", inst: FDIVS, src: RegV31, dst: RegV31, exp: []byte{0xff, 0x1b, 0x3f, 0x1e}}, - {name: "FDIVD/src=V0,dst=V0", inst: FDIVD, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x18, 0x60, 0x1e}}, - {name: "FDIVD/src=V0,dst=V31", inst: FDIVD, src: RegV0, dst: RegV31, exp: []byte{0xff, 0x1b, 0x60, 0x1e}}, - {name: "FDIVD/src=V31,dst=V0", inst: FDIVD, src: RegV31, dst: RegV0, exp: []byte{0x0, 0x18, 0x7f, 0x1e}}, - {name: "FDIVD/src=V31,dst=V31", inst: FDIVD, src: RegV31, dst: RegV31, exp: []byte{0xff, 0x1b, 0x7f, 0x1e}}, - {name: "FMAXD/src=V0,dst=V0", inst: FMAXD, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x48, 0x60, 0x1e}}, - {name: "FMAXD/src=V0,dst=V31", inst: FMAXD, src: RegV0, dst: RegV31, exp: []byte{0xff, 0x4b, 0x60, 0x1e}}, - {name: "FMAXD/src=V31,dst=V0", inst: FMAXD, src: RegV31, dst: RegV0, exp: []byte{0x0, 0x48, 0x7f, 0x1e}}, - {name: "FMAXD/src=V31,dst=V31", inst: FMAXD, src: RegV31, dst: RegV31, exp: []byte{0xff, 0x4b, 0x7f, 0x1e}}, - {name: "FMAXS/src=V0,dst=V0", inst: FMAXS, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x48, 0x20, 0x1e}}, - {name: "FMAXS/src=V0,dst=V31", inst: FMAXS, src: RegV0, dst: RegV31, exp: []byte{0xff, 0x4b, 0x20, 0x1e}}, - {name: "FMAXS/src=V31,dst=V0", inst: FMAXS, src: RegV31, dst: RegV0, exp: []byte{0x0, 0x48, 0x3f, 0x1e}}, - {name: "FMAXS/src=V31,dst=V31", inst: FMAXS, src: RegV31, dst: RegV31, exp: []byte{0xff, 0x4b, 0x3f, 0x1e}}, - {name: "FMIND/src=V0,dst=V0", inst: FMIND, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x58, 0x60, 0x1e}}, - {name: "FMIND/src=V0,dst=V31", inst: FMIND, src: RegV0, dst: RegV31, exp: []byte{0xff, 0x5b, 0x60, 0x1e}}, - {name: "FMIND/src=V31,dst=V0", inst: FMIND, src: RegV31, dst: RegV0, exp: []byte{0x0, 0x58, 0x7f, 0x1e}}, - {name: "FMIND/src=V31,dst=V31", inst: FMIND, src: RegV31, dst: RegV31, exp: []byte{0xff, 0x5b, 0x7f, 0x1e}}, - {name: "FMINS/src=V0,dst=V0", inst: FMINS, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x58, 0x20, 0x1e}}, - {name: "FMINS/src=V0,dst=V31", inst: FMINS, src: RegV0, dst: RegV31, exp: []byte{0xff, 0x5b, 0x20, 0x1e}}, - {name: "FMINS/src=V31,dst=V0", inst: FMINS, src: RegV31, dst: RegV0, exp: []byte{0x0, 0x58, 0x3f, 0x1e}}, - {name: "FMINS/src=V31,dst=V31", inst: FMINS, src: RegV31, dst: RegV31, exp: []byte{0xff, 0x5b, 0x3f, 0x1e}}, - {name: "FMULS/src=V0,dst=V0", inst: FMULS, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x8, 0x20, 0x1e}}, - {name: "FMULS/src=V0,dst=V31", inst: FMULS, src: RegV0, dst: RegV31, exp: []byte{0xff, 0xb, 0x20, 0x1e}}, - {name: "FMULS/src=V31,dst=V0", inst: FMULS, src: RegV31, dst: RegV0, exp: []byte{0x0, 0x8, 0x3f, 0x1e}}, - {name: "FMULS/src=V31,dst=V31", inst: FMULS, src: RegV31, dst: RegV31, exp: []byte{0xff, 0xb, 0x3f, 0x1e}}, - {name: "FMULD/src=V0,dst=V0", inst: FMULD, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x8, 0x60, 0x1e}}, - {name: "FMULD/src=V0,dst=V31", inst: FMULD, src: RegV0, dst: RegV31, exp: []byte{0xff, 0xb, 0x60, 0x1e}}, - {name: "FMULD/src=V31,dst=V0", inst: FMULD, src: RegV31, dst: RegV0, exp: []byte{0x0, 0x8, 0x7f, 0x1e}}, - {name: "FMULD/src=V31,dst=V31", inst: FMULD, src: RegV31, dst: RegV31, exp: []byte{0xff, 0xb, 0x7f, 0x1e}}, - {name: "FADDD/src=V0,dst=V0", inst: FADDD, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x28, 0x60, 0x1e}}, - {name: "FADDD/src=V0,dst=V31", inst: FADDD, src: RegV0, dst: RegV31, exp: []byte{0xff, 0x2b, 0x60, 0x1e}}, - {name: "FADDD/src=V31,dst=V0", inst: FADDD, src: RegV31, dst: RegV0, exp: []byte{0x0, 0x28, 0x7f, 0x1e}}, - {name: "FADDD/src=V31,dst=V31", inst: FADDD, src: RegV31, dst: RegV31, exp: []byte{0xff, 0x2b, 0x7f, 0x1e}}, - {name: "FADDS/src=V0,dst=V0", inst: FADDS, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x28, 0x20, 0x1e}}, - {name: "FADDS/src=V0,dst=V31", inst: FADDS, src: RegV0, dst: RegV31, exp: []byte{0xff, 0x2b, 0x20, 0x1e}}, - {name: "FADDS/src=V31,dst=V0", inst: FADDS, src: RegV31, dst: RegV0, exp: []byte{0x0, 0x28, 0x3f, 0x1e}}, - {name: "FADDS/src=V31,dst=V31", inst: FADDS, src: RegV31, dst: RegV31, exp: []byte{0xff, 0x2b, 0x3f, 0x1e}}, - {name: "FCVTZSD/src=V0,dst=RZR", inst: FCVTZSD, src: RegV0, dst: RegRZR, exp: []byte{0x1f, 0x0, 0x78, 0x9e}}, - {name: "FCVTZSD/src=V0,dst=R10", inst: FCVTZSD, src: RegV0, dst: RegR10, exp: []byte{0xa, 0x0, 0x78, 0x9e}}, - {name: "FCVTZSD/src=V0,dst=R30", inst: FCVTZSD, src: RegV0, dst: RegR30, exp: []byte{0x1e, 0x0, 0x78, 0x9e}}, - {name: "FCVTZSD/src=V31,dst=RZR", inst: FCVTZSD, src: RegV31, dst: RegRZR, exp: []byte{0xff, 0x3, 0x78, 0x9e}}, - {name: "FCVTZSD/src=V31,dst=R10", inst: FCVTZSD, src: RegV31, dst: RegR10, exp: []byte{0xea, 0x3, 0x78, 0x9e}}, - {name: "FCVTZSD/src=V31,dst=R30", inst: FCVTZSD, src: RegV31, dst: RegR30, exp: []byte{0xfe, 0x3, 0x78, 0x9e}}, - {name: "FCVTZSDW/src=V0,dst=RZR", inst: FCVTZSDW, src: RegV0, dst: RegRZR, exp: []byte{0x1f, 0x0, 0x78, 0x1e}}, - {name: "FCVTZSDW/src=V0,dst=R10", inst: FCVTZSDW, src: RegV0, dst: RegR10, exp: []byte{0xa, 0x0, 0x78, 0x1e}}, - {name: "FCVTZSDW/src=V0,dst=R30", inst: FCVTZSDW, src: RegV0, dst: RegR30, exp: []byte{0x1e, 0x0, 0x78, 0x1e}}, - {name: "FCVTZSDW/src=V31,dst=RZR", inst: FCVTZSDW, src: RegV31, dst: RegRZR, exp: []byte{0xff, 0x3, 0x78, 0x1e}}, - {name: "FCVTZSDW/src=V31,dst=R10", inst: FCVTZSDW, src: RegV31, dst: RegR10, exp: []byte{0xea, 0x3, 0x78, 0x1e}}, - {name: "FCVTZSDW/src=V31,dst=R30", inst: FCVTZSDW, src: RegV31, dst: RegR30, exp: []byte{0xfe, 0x3, 0x78, 0x1e}}, - {name: "FCVTZSS/src=V0,dst=RZR", inst: FCVTZSS, src: RegV0, dst: RegRZR, exp: []byte{0x1f, 0x0, 0x38, 0x9e}}, - {name: "FCVTZSS/src=V0,dst=R10", inst: FCVTZSS, src: RegV0, dst: RegR10, exp: []byte{0xa, 0x0, 0x38, 0x9e}}, - {name: "FCVTZSS/src=V0,dst=R30", inst: FCVTZSS, src: RegV0, dst: RegR30, exp: []byte{0x1e, 0x0, 0x38, 0x9e}}, - {name: "FCVTZSS/src=V31,dst=RZR", inst: FCVTZSS, src: RegV31, dst: RegRZR, exp: []byte{0xff, 0x3, 0x38, 0x9e}}, - {name: "FCVTZSS/src=V31,dst=R10", inst: FCVTZSS, src: RegV31, dst: RegR10, exp: []byte{0xea, 0x3, 0x38, 0x9e}}, - {name: "FCVTZSS/src=V31,dst=R30", inst: FCVTZSS, src: RegV31, dst: RegR30, exp: []byte{0xfe, 0x3, 0x38, 0x9e}}, - {name: "FCVTZSSW/src=V0,dst=RZR", inst: FCVTZSSW, src: RegV0, dst: RegRZR, exp: []byte{0x1f, 0x0, 0x38, 0x1e}}, - {name: "FCVTZSSW/src=V0,dst=R10", inst: FCVTZSSW, src: RegV0, dst: RegR10, exp: []byte{0xa, 0x0, 0x38, 0x1e}}, - {name: "FCVTZSSW/src=V0,dst=R30", inst: FCVTZSSW, src: RegV0, dst: RegR30, exp: []byte{0x1e, 0x0, 0x38, 0x1e}}, - {name: "FCVTZSSW/src=V31,dst=RZR", inst: FCVTZSSW, src: RegV31, dst: RegRZR, exp: []byte{0xff, 0x3, 0x38, 0x1e}}, - {name: "FCVTZSSW/src=V31,dst=R10", inst: FCVTZSSW, src: RegV31, dst: RegR10, exp: []byte{0xea, 0x3, 0x38, 0x1e}}, - {name: "FCVTZSSW/src=V31,dst=R30", inst: FCVTZSSW, src: RegV31, dst: RegR30, exp: []byte{0xfe, 0x3, 0x38, 0x1e}}, - {name: "FCVTZUD/src=V0,dst=RZR", inst: FCVTZUD, src: RegV0, dst: RegRZR, exp: []byte{0x1f, 0x0, 0x79, 0x9e}}, - {name: "FCVTZUD/src=V0,dst=R10", inst: FCVTZUD, src: RegV0, dst: RegR10, exp: []byte{0xa, 0x0, 0x79, 0x9e}}, - {name: "FCVTZUD/src=V0,dst=R30", inst: FCVTZUD, src: RegV0, dst: RegR30, exp: []byte{0x1e, 0x0, 0x79, 0x9e}}, - {name: "FCVTZUD/src=V31,dst=RZR", inst: FCVTZUD, src: RegV31, dst: RegRZR, exp: []byte{0xff, 0x3, 0x79, 0x9e}}, - {name: "FCVTZUD/src=V31,dst=R10", inst: FCVTZUD, src: RegV31, dst: RegR10, exp: []byte{0xea, 0x3, 0x79, 0x9e}}, - {name: "FCVTZUD/src=V31,dst=R30", inst: FCVTZUD, src: RegV31, dst: RegR30, exp: []byte{0xfe, 0x3, 0x79, 0x9e}}, - {name: "FCVTZUDW/src=V0,dst=RZR", inst: FCVTZUDW, src: RegV0, dst: RegRZR, exp: []byte{0x1f, 0x0, 0x79, 0x1e}}, - {name: "FCVTZUDW/src=V0,dst=R10", inst: FCVTZUDW, src: RegV0, dst: RegR10, exp: []byte{0xa, 0x0, 0x79, 0x1e}}, - {name: "FCVTZUDW/src=V0,dst=R30", inst: FCVTZUDW, src: RegV0, dst: RegR30, exp: []byte{0x1e, 0x0, 0x79, 0x1e}}, - {name: "FCVTZUDW/src=V31,dst=RZR", inst: FCVTZUDW, src: RegV31, dst: RegRZR, exp: []byte{0xff, 0x3, 0x79, 0x1e}}, - {name: "FCVTZUDW/src=V31,dst=R10", inst: FCVTZUDW, src: RegV31, dst: RegR10, exp: []byte{0xea, 0x3, 0x79, 0x1e}}, - {name: "FCVTZUDW/src=V31,dst=R30", inst: FCVTZUDW, src: RegV31, dst: RegR30, exp: []byte{0xfe, 0x3, 0x79, 0x1e}}, - {name: "FCVTZUS/src=V0,dst=RZR", inst: FCVTZUS, src: RegV0, dst: RegRZR, exp: []byte{0x1f, 0x0, 0x39, 0x9e}}, - {name: "FCVTZUS/src=V0,dst=R10", inst: FCVTZUS, src: RegV0, dst: RegR10, exp: []byte{0xa, 0x0, 0x39, 0x9e}}, - {name: "FCVTZUS/src=V0,dst=R30", inst: FCVTZUS, src: RegV0, dst: RegR30, exp: []byte{0x1e, 0x0, 0x39, 0x9e}}, - {name: "FCVTZUS/src=V31,dst=RZR", inst: FCVTZUS, src: RegV31, dst: RegRZR, exp: []byte{0xff, 0x3, 0x39, 0x9e}}, - {name: "FCVTZUS/src=V31,dst=R10", inst: FCVTZUS, src: RegV31, dst: RegR10, exp: []byte{0xea, 0x3, 0x39, 0x9e}}, - {name: "FCVTZUS/src=V31,dst=R30", inst: FCVTZUS, src: RegV31, dst: RegR30, exp: []byte{0xfe, 0x3, 0x39, 0x9e}}, - {name: "FCVTZUSW/src=V0,dst=RZR", inst: FCVTZUSW, src: RegV0, dst: RegRZR, exp: []byte{0x1f, 0x0, 0x39, 0x1e}}, - {name: "FCVTZUSW/src=V0,dst=R10", inst: FCVTZUSW, src: RegV0, dst: RegR10, exp: []byte{0xa, 0x0, 0x39, 0x1e}}, - {name: "FCVTZUSW/src=V0,dst=R30", inst: FCVTZUSW, src: RegV0, dst: RegR30, exp: []byte{0x1e, 0x0, 0x39, 0x1e}}, - {name: "FCVTZUSW/src=V31,dst=RZR", inst: FCVTZUSW, src: RegV31, dst: RegRZR, exp: []byte{0xff, 0x3, 0x39, 0x1e}}, - {name: "FCVTZUSW/src=V31,dst=R10", inst: FCVTZUSW, src: RegV31, dst: RegR10, exp: []byte{0xea, 0x3, 0x39, 0x1e}}, - {name: "FCVTZUSW/src=V31,dst=R30", inst: FCVTZUSW, src: RegV31, dst: RegR30, exp: []byte{0xfe, 0x3, 0x39, 0x1e}}, - {name: "FMOVD/src=V0,dst=V0", inst: FMOVD, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x40, 0x60, 0x1e}}, - {name: "FMOVD/src=V0,dst=V31", inst: FMOVD, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0x40, 0x60, 0x1e}}, - {name: "FMOVD/src=V31,dst=V0", inst: FMOVD, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0x43, 0x60, 0x1e}}, - {name: "FMOVD/src=V31,dst=V31", inst: FMOVD, src: RegV31, dst: RegV31, exp: []byte{0xff, 0x43, 0x60, 0x1e}}, - {name: "FMOVS/src=V0,dst=V0", inst: FMOVS, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x40, 0x20, 0x1e}}, - {name: "FMOVS/src=V0,dst=V31", inst: FMOVS, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0x40, 0x20, 0x1e}}, - {name: "FMOVS/src=V31,dst=V0", inst: FMOVS, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0x43, 0x20, 0x1e}}, - {name: "FMOVS/src=V31,dst=V31", inst: FMOVS, src: RegV31, dst: RegV31, exp: []byte{0xff, 0x43, 0x20, 0x1e}}, - {name: "FMOVD/src=RZR,dst=V0", inst: FMOVD, src: RegRZR, dst: RegV0, exp: []byte{0xe0, 0x3, 0x67, 0x9e}}, - {name: "FMOVD/src=RZR,dst=V31", inst: FMOVD, src: RegRZR, dst: RegV31, exp: []byte{0xff, 0x3, 0x67, 0x9e}}, - {name: "FMOVD/src=R10,dst=V0", inst: FMOVD, src: RegR10, dst: RegV0, exp: []byte{0x40, 0x1, 0x67, 0x9e}}, - {name: "FMOVD/src=R10,dst=V31", inst: FMOVD, src: RegR10, dst: RegV31, exp: []byte{0x5f, 0x1, 0x67, 0x9e}}, - {name: "FMOVD/src=R30,dst=V0", inst: FMOVD, src: RegR30, dst: RegV0, exp: []byte{0xc0, 0x3, 0x67, 0x9e}}, - {name: "FMOVD/src=R30,dst=V31", inst: FMOVD, src: RegR30, dst: RegV31, exp: []byte{0xdf, 0x3, 0x67, 0x9e}}, - {name: "FMOVS/src=RZR,dst=V0", inst: FMOVS, src: RegRZR, dst: RegV0, exp: []byte{0xe0, 0x3, 0x27, 0x1e}}, - {name: "FMOVS/src=RZR,dst=V31", inst: FMOVS, src: RegRZR, dst: RegV31, exp: []byte{0xff, 0x3, 0x27, 0x1e}}, - {name: "FMOVS/src=R10,dst=V0", inst: FMOVS, src: RegR10, dst: RegV0, exp: []byte{0x40, 0x1, 0x27, 0x1e}}, - {name: "FMOVS/src=R10,dst=V31", inst: FMOVS, src: RegR10, dst: RegV31, exp: []byte{0x5f, 0x1, 0x27, 0x1e}}, - {name: "FMOVS/src=R30,dst=V0", inst: FMOVS, src: RegR30, dst: RegV0, exp: []byte{0xc0, 0x3, 0x27, 0x1e}}, - {name: "FMOVS/src=R30,dst=V31", inst: FMOVS, src: RegR30, dst: RegV31, exp: []byte{0xdf, 0x3, 0x27, 0x1e}}, - {name: "FMOVD/src=V0,dst=RZR", inst: FMOVD, src: RegV0, dst: RegRZR, exp: []byte{0x1f, 0x0, 0x66, 0x9e}}, - {name: "FMOVD/src=V0,dst=R10", inst: FMOVD, src: RegV0, dst: RegR10, exp: []byte{0xa, 0x0, 0x66, 0x9e}}, - {name: "FMOVD/src=V0,dst=R30", inst: FMOVD, src: RegV0, dst: RegR30, exp: []byte{0x1e, 0x0, 0x66, 0x9e}}, - {name: "FMOVD/src=V31,dst=RZR", inst: FMOVD, src: RegV31, dst: RegRZR, exp: []byte{0xff, 0x3, 0x66, 0x9e}}, - {name: "FMOVD/src=V31,dst=R10", inst: FMOVD, src: RegV31, dst: RegR10, exp: []byte{0xea, 0x3, 0x66, 0x9e}}, - {name: "FMOVD/src=V31,dst=R30", inst: FMOVD, src: RegV31, dst: RegR30, exp: []byte{0xfe, 0x3, 0x66, 0x9e}}, - {name: "FMOVS/src=V0,dst=RZR", inst: FMOVS, src: RegV0, dst: RegRZR, exp: []byte{0x1f, 0x0, 0x26, 0x1e}}, - {name: "FMOVS/src=V0,dst=R10", inst: FMOVS, src: RegV0, dst: RegR10, exp: []byte{0xa, 0x0, 0x26, 0x1e}}, - {name: "FMOVS/src=V0,dst=R30", inst: FMOVS, src: RegV0, dst: RegR30, exp: []byte{0x1e, 0x0, 0x26, 0x1e}}, - {name: "FMOVS/src=V31,dst=RZR", inst: FMOVS, src: RegV31, dst: RegRZR, exp: []byte{0xff, 0x3, 0x26, 0x1e}}, - {name: "FMOVS/src=V31,dst=R10", inst: FMOVS, src: RegV31, dst: RegR10, exp: []byte{0xea, 0x3, 0x26, 0x1e}}, - {name: "FMOVS/src=V31,dst=R30", inst: FMOVS, src: RegV31, dst: RegR30, exp: []byte{0xfe, 0x3, 0x26, 0x1e}}, - {name: "MOVD/src=RZR,dst=R10", inst: MOVD, src: RegRZR, dst: RegR10, exp: []byte{0xa, 0x0, 0x80, 0xd2}}, - {name: "MOVD/src=RZR,dst=R30", inst: MOVD, src: RegRZR, dst: RegR30, exp: []byte{0x1e, 0x0, 0x80, 0xd2}}, - {name: "MOVD/src=R10,dst=R10", inst: MOVD, src: RegR10, dst: RegR10, exp: []byte{0xea, 0x3, 0xa, 0xaa}}, - {name: "MOVD/src=R10,dst=R30", inst: MOVD, src: RegR10, dst: RegR30, exp: []byte{0xfe, 0x3, 0xa, 0xaa}}, - {name: "MOVD/src=R30,dst=R10", inst: MOVD, src: RegR30, dst: RegR10, exp: []byte{0xea, 0x3, 0x1e, 0xaa}}, - {name: "MOVD/src=R30,dst=R30", inst: MOVD, src: RegR30, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1e, 0xaa}}, - {name: "MRS/src=FPSR,dst=RZR", inst: MRS, src: RegFPSR, dst: RegRZR, exp: []byte{0x3f, 0x44, 0x3b, 0xd5}}, - {name: "MRS/src=FPSR,dst=R10", inst: MRS, src: RegFPSR, dst: RegR10, exp: []byte{0x2a, 0x44, 0x3b, 0xd5}}, - {name: "MRS/src=FPSR,dst=R30", inst: MRS, src: RegFPSR, dst: RegR30, exp: []byte{0x3e, 0x44, 0x3b, 0xd5}}, - {name: "MSR/src=RZR,dst=FPSR", inst: MSR, src: RegRZR, dst: RegFPSR, exp: []byte{0x3f, 0x44, 0x1b, 0xd5}}, - {name: "MSR/src=R10,dst=FPSR", inst: MSR, src: RegR10, dst: RegFPSR, exp: []byte{0x2a, 0x44, 0x1b, 0xd5}}, - {name: "MSR/src=R30,dst=FPSR", inst: MSR, src: RegR30, dst: RegFPSR, exp: []byte{0x3e, 0x44, 0x1b, 0xd5}}, - {name: "MUL/src=RZR,dst=RZR", inst: MUL, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x7f, 0x1f, 0x9b}}, - {name: "MUL/src=RZR,dst=R10", inst: MUL, src: RegRZR, dst: RegR10, exp: []byte{0x4a, 0x7d, 0x1f, 0x9b}}, - {name: "MUL/src=RZR,dst=R30", inst: MUL, src: RegRZR, dst: RegR30, exp: []byte{0xde, 0x7f, 0x1f, 0x9b}}, - {name: "MUL/src=R10,dst=RZR", inst: MUL, src: RegR10, dst: RegRZR, exp: []byte{0xff, 0x7f, 0xa, 0x9b}}, - {name: "MUL/src=R10,dst=R10", inst: MUL, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0x7d, 0xa, 0x9b}}, - {name: "MUL/src=R10,dst=R30", inst: MUL, src: RegR10, dst: RegR30, exp: []byte{0xde, 0x7f, 0xa, 0x9b}}, - {name: "MUL/src=R30,dst=RZR", inst: MUL, src: RegR30, dst: RegRZR, exp: []byte{0xff, 0x7f, 0x1e, 0x9b}}, - {name: "MUL/src=R30,dst=R10", inst: MUL, src: RegR30, dst: RegR10, exp: []byte{0x4a, 0x7d, 0x1e, 0x9b}}, - {name: "MUL/src=R30,dst=R30", inst: MUL, src: RegR30, dst: RegR30, exp: []byte{0xde, 0x7f, 0x1e, 0x9b}}, - {name: "MULW/src=RZR,dst=RZR", inst: MULW, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x7f, 0x1f, 0x1b}}, - {name: "MULW/src=RZR,dst=R10", inst: MULW, src: RegRZR, dst: RegR10, exp: []byte{0x4a, 0x7d, 0x1f, 0x1b}}, - {name: "MULW/src=RZR,dst=R30", inst: MULW, src: RegRZR, dst: RegR30, exp: []byte{0xde, 0x7f, 0x1f, 0x1b}}, - {name: "MULW/src=R10,dst=RZR", inst: MULW, src: RegR10, dst: RegRZR, exp: []byte{0xff, 0x7f, 0xa, 0x1b}}, - {name: "MULW/src=R10,dst=R10", inst: MULW, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0x7d, 0xa, 0x1b}}, - {name: "MULW/src=R10,dst=R30", inst: MULW, src: RegR10, dst: RegR30, exp: []byte{0xde, 0x7f, 0xa, 0x1b}}, - {name: "MULW/src=R30,dst=RZR", inst: MULW, src: RegR30, dst: RegRZR, exp: []byte{0xff, 0x7f, 0x1e, 0x1b}}, - {name: "MULW/src=R30,dst=R10", inst: MULW, src: RegR30, dst: RegR10, exp: []byte{0x4a, 0x7d, 0x1e, 0x1b}}, - {name: "MULW/src=R30,dst=R30", inst: MULW, src: RegR30, dst: RegR30, exp: []byte{0xde, 0x7f, 0x1e, 0x1b}}, - {name: "NEG/src=RZR,dst=RZR", inst: NEG, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0xcb}}, - {name: "NEG/src=RZR,dst=R10", inst: NEG, src: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1f, 0xcb}}, - {name: "NEG/src=RZR,dst=R30", inst: NEG, src: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1f, 0xcb}}, - {name: "NEG/src=R10,dst=RZR", inst: NEG, src: RegR10, dst: RegRZR, exp: []byte{0xff, 0x3, 0xa, 0xcb}}, - {name: "NEG/src=R10,dst=R10", inst: NEG, src: RegR10, dst: RegR10, exp: []byte{0xea, 0x3, 0xa, 0xcb}}, - {name: "NEG/src=R10,dst=R30", inst: NEG, src: RegR10, dst: RegR30, exp: []byte{0xfe, 0x3, 0xa, 0xcb}}, - {name: "NEG/src=R30,dst=RZR", inst: NEG, src: RegR30, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1e, 0xcb}}, - {name: "NEG/src=R30,dst=R10", inst: NEG, src: RegR30, dst: RegR10, exp: []byte{0xea, 0x3, 0x1e, 0xcb}}, - {name: "NEG/src=R30,dst=R30", inst: NEG, src: RegR30, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1e, 0xcb}}, - {name: "NEGW/src=RZR,dst=RZR", inst: NEGW, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0x4b}}, - {name: "NEGW/src=RZR,dst=R10", inst: NEGW, src: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1f, 0x4b}}, - {name: "NEGW/src=RZR,dst=R30", inst: NEGW, src: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1f, 0x4b}}, - {name: "NEGW/src=R10,dst=RZR", inst: NEGW, src: RegR10, dst: RegRZR, exp: []byte{0xff, 0x3, 0xa, 0x4b}}, - {name: "NEGW/src=R10,dst=R10", inst: NEGW, src: RegR10, dst: RegR10, exp: []byte{0xea, 0x3, 0xa, 0x4b}}, - {name: "NEGW/src=R10,dst=R30", inst: NEGW, src: RegR10, dst: RegR30, exp: []byte{0xfe, 0x3, 0xa, 0x4b}}, - {name: "NEGW/src=R30,dst=RZR", inst: NEGW, src: RegR30, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1e, 0x4b}}, - {name: "NEGW/src=R30,dst=R10", inst: NEGW, src: RegR30, dst: RegR10, exp: []byte{0xea, 0x3, 0x1e, 0x4b}}, - {name: "NEGW/src=R30,dst=R30", inst: NEGW, src: RegR30, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1e, 0x4b}}, - {name: "RBIT/src=RZR,dst=RZR", inst: RBIT, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0xc0, 0xda}}, - {name: "RBIT/src=RZR,dst=R10", inst: RBIT, src: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0xc0, 0xda}}, - {name: "RBIT/src=RZR,dst=R30", inst: RBIT, src: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0xc0, 0xda}}, - {name: "RBIT/src=R10,dst=RZR", inst: RBIT, src: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0xc0, 0xda}}, - {name: "RBIT/src=R10,dst=R10", inst: RBIT, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0xc0, 0xda}}, - {name: "RBIT/src=R10,dst=R30", inst: RBIT, src: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0xc0, 0xda}}, - {name: "RBIT/src=R30,dst=RZR", inst: RBIT, src: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0xc0, 0xda}}, - {name: "RBIT/src=R30,dst=R10", inst: RBIT, src: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0xc0, 0xda}}, - {name: "RBIT/src=R30,dst=R30", inst: RBIT, src: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0xc0, 0xda}}, - {name: "RBITW/src=RZR,dst=RZR", inst: RBITW, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0xc0, 0x5a}}, - {name: "RBITW/src=RZR,dst=R10", inst: RBITW, src: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0xc0, 0x5a}}, - {name: "RBITW/src=RZR,dst=R30", inst: RBITW, src: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0xc0, 0x5a}}, - {name: "RBITW/src=R10,dst=RZR", inst: RBITW, src: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0xc0, 0x5a}}, - {name: "RBITW/src=R10,dst=R10", inst: RBITW, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0xc0, 0x5a}}, - {name: "RBITW/src=R10,dst=R30", inst: RBITW, src: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0xc0, 0x5a}}, - {name: "RBITW/src=R30,dst=RZR", inst: RBITW, src: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0xc0, 0x5a}}, - {name: "RBITW/src=R30,dst=R10", inst: RBITW, src: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0xc0, 0x5a}}, - {name: "RBITW/src=R30,dst=R30", inst: RBITW, src: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0xc0, 0x5a}}, - {name: "SDIV/src=RZR,dst=RZR", inst: SDIV, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xf, 0xdf, 0x9a}}, - {name: "SDIV/src=RZR,dst=R10", inst: SDIV, src: RegRZR, dst: RegR10, exp: []byte{0x4a, 0xd, 0xdf, 0x9a}}, - {name: "SDIV/src=RZR,dst=R30", inst: SDIV, src: RegRZR, dst: RegR30, exp: []byte{0xde, 0xf, 0xdf, 0x9a}}, - {name: "SDIV/src=R10,dst=RZR", inst: SDIV, src: RegR10, dst: RegRZR, exp: []byte{0xff, 0xf, 0xca, 0x9a}}, - {name: "SDIV/src=R10,dst=R10", inst: SDIV, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0xd, 0xca, 0x9a}}, - {name: "SDIV/src=R10,dst=R30", inst: SDIV, src: RegR10, dst: RegR30, exp: []byte{0xde, 0xf, 0xca, 0x9a}}, - {name: "SDIV/src=R30,dst=RZR", inst: SDIV, src: RegR30, dst: RegRZR, exp: []byte{0xff, 0xf, 0xde, 0x9a}}, - {name: "SDIV/src=R30,dst=R10", inst: SDIV, src: RegR30, dst: RegR10, exp: []byte{0x4a, 0xd, 0xde, 0x9a}}, - {name: "SDIV/src=R30,dst=R30", inst: SDIV, src: RegR30, dst: RegR30, exp: []byte{0xde, 0xf, 0xde, 0x9a}}, - {name: "SDIVW/src=RZR,dst=RZR", inst: SDIVW, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xf, 0xdf, 0x1a}}, - {name: "SDIVW/src=RZR,dst=R10", inst: SDIVW, src: RegRZR, dst: RegR10, exp: []byte{0x4a, 0xd, 0xdf, 0x1a}}, - {name: "SDIVW/src=RZR,dst=R30", inst: SDIVW, src: RegRZR, dst: RegR30, exp: []byte{0xde, 0xf, 0xdf, 0x1a}}, - {name: "SDIVW/src=R10,dst=RZR", inst: SDIVW, src: RegR10, dst: RegRZR, exp: []byte{0xff, 0xf, 0xca, 0x1a}}, - {name: "SDIVW/src=R10,dst=R10", inst: SDIVW, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0xd, 0xca, 0x1a}}, - {name: "SDIVW/src=R10,dst=R30", inst: SDIVW, src: RegR10, dst: RegR30, exp: []byte{0xde, 0xf, 0xca, 0x1a}}, - {name: "SDIVW/src=R30,dst=RZR", inst: SDIVW, src: RegR30, dst: RegRZR, exp: []byte{0xff, 0xf, 0xde, 0x1a}}, - {name: "SDIVW/src=R30,dst=R10", inst: SDIVW, src: RegR30, dst: RegR10, exp: []byte{0x4a, 0xd, 0xde, 0x1a}}, - {name: "SDIVW/src=R30,dst=R30", inst: SDIVW, src: RegR30, dst: RegR30, exp: []byte{0xde, 0xf, 0xde, 0x1a}}, - {name: "UDIV/src=RZR,dst=RZR", inst: UDIV, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xb, 0xdf, 0x9a}}, - {name: "UDIV/src=RZR,dst=R10", inst: UDIV, src: RegRZR, dst: RegR10, exp: []byte{0x4a, 0x9, 0xdf, 0x9a}}, - {name: "UDIV/src=RZR,dst=R30", inst: UDIV, src: RegRZR, dst: RegR30, exp: []byte{0xde, 0xb, 0xdf, 0x9a}}, - {name: "UDIV/src=R10,dst=RZR", inst: UDIV, src: RegR10, dst: RegRZR, exp: []byte{0xff, 0xb, 0xca, 0x9a}}, - {name: "UDIV/src=R10,dst=R10", inst: UDIV, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0x9, 0xca, 0x9a}}, - {name: "UDIV/src=R10,dst=R30", inst: UDIV, src: RegR10, dst: RegR30, exp: []byte{0xde, 0xb, 0xca, 0x9a}}, - {name: "UDIV/src=R30,dst=RZR", inst: UDIV, src: RegR30, dst: RegRZR, exp: []byte{0xff, 0xb, 0xde, 0x9a}}, - {name: "UDIV/src=R30,dst=R10", inst: UDIV, src: RegR30, dst: RegR10, exp: []byte{0x4a, 0x9, 0xde, 0x9a}}, - {name: "UDIV/src=R30,dst=R30", inst: UDIV, src: RegR30, dst: RegR30, exp: []byte{0xde, 0xb, 0xde, 0x9a}}, - {name: "UDIVW/src=RZR,dst=RZR", inst: UDIVW, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xb, 0xdf, 0x1a}}, - {name: "UDIVW/src=RZR,dst=R10", inst: UDIVW, src: RegRZR, dst: RegR10, exp: []byte{0x4a, 0x9, 0xdf, 0x1a}}, - {name: "UDIVW/src=RZR,dst=R30", inst: UDIVW, src: RegRZR, dst: RegR30, exp: []byte{0xde, 0xb, 0xdf, 0x1a}}, - {name: "UDIVW/src=R10,dst=RZR", inst: UDIVW, src: RegR10, dst: RegRZR, exp: []byte{0xff, 0xb, 0xca, 0x1a}}, - {name: "UDIVW/src=R10,dst=R10", inst: UDIVW, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0x9, 0xca, 0x1a}}, - {name: "UDIVW/src=R10,dst=R30", inst: UDIVW, src: RegR10, dst: RegR30, exp: []byte{0xde, 0xb, 0xca, 0x1a}}, - {name: "UDIVW/src=R30,dst=RZR", inst: UDIVW, src: RegR30, dst: RegRZR, exp: []byte{0xff, 0xb, 0xde, 0x1a}}, - {name: "UDIVW/src=R30,dst=R10", inst: UDIVW, src: RegR30, dst: RegR10, exp: []byte{0x4a, 0x9, 0xde, 0x1a}}, - {name: "UDIVW/src=R30,dst=R30", inst: UDIVW, src: RegR30, dst: RegR30, exp: []byte{0xde, 0xb, 0xde, 0x1a}}, - {name: "SCVTFD/src=RZR,dst=V0", inst: SCVTFD, src: RegRZR, dst: RegV0, exp: []byte{0xe0, 0x3, 0x62, 0x9e}}, - {name: "SCVTFD/src=RZR,dst=V31", inst: SCVTFD, src: RegRZR, dst: RegV31, exp: []byte{0xff, 0x3, 0x62, 0x9e}}, - {name: "SCVTFD/src=R10,dst=V0", inst: SCVTFD, src: RegR10, dst: RegV0, exp: []byte{0x40, 0x1, 0x62, 0x9e}}, - {name: "SCVTFD/src=R10,dst=V31", inst: SCVTFD, src: RegR10, dst: RegV31, exp: []byte{0x5f, 0x1, 0x62, 0x9e}}, - {name: "SCVTFD/src=R30,dst=V0", inst: SCVTFD, src: RegR30, dst: RegV0, exp: []byte{0xc0, 0x3, 0x62, 0x9e}}, - {name: "SCVTFD/src=R30,dst=V31", inst: SCVTFD, src: RegR30, dst: RegV31, exp: []byte{0xdf, 0x3, 0x62, 0x9e}}, - {name: "SCVTFWD/src=RZR,dst=V0", inst: SCVTFWD, src: RegRZR, dst: RegV0, exp: []byte{0xe0, 0x3, 0x62, 0x1e}}, - {name: "SCVTFWD/src=RZR,dst=V31", inst: SCVTFWD, src: RegRZR, dst: RegV31, exp: []byte{0xff, 0x3, 0x62, 0x1e}}, - {name: "SCVTFWD/src=R10,dst=V0", inst: SCVTFWD, src: RegR10, dst: RegV0, exp: []byte{0x40, 0x1, 0x62, 0x1e}}, - {name: "SCVTFWD/src=R10,dst=V31", inst: SCVTFWD, src: RegR10, dst: RegV31, exp: []byte{0x5f, 0x1, 0x62, 0x1e}}, - {name: "SCVTFWD/src=R30,dst=V0", inst: SCVTFWD, src: RegR30, dst: RegV0, exp: []byte{0xc0, 0x3, 0x62, 0x1e}}, - {name: "SCVTFWD/src=R30,dst=V31", inst: SCVTFWD, src: RegR30, dst: RegV31, exp: []byte{0xdf, 0x3, 0x62, 0x1e}}, - {name: "SCVTFS/src=RZR,dst=V0", inst: SCVTFS, src: RegRZR, dst: RegV0, exp: []byte{0xe0, 0x3, 0x22, 0x9e}}, - {name: "SCVTFS/src=RZR,dst=V31", inst: SCVTFS, src: RegRZR, dst: RegV31, exp: []byte{0xff, 0x3, 0x22, 0x9e}}, - {name: "SCVTFS/src=R10,dst=V0", inst: SCVTFS, src: RegR10, dst: RegV0, exp: []byte{0x40, 0x1, 0x22, 0x9e}}, - {name: "SCVTFS/src=R10,dst=V31", inst: SCVTFS, src: RegR10, dst: RegV31, exp: []byte{0x5f, 0x1, 0x22, 0x9e}}, - {name: "SCVTFS/src=R30,dst=V0", inst: SCVTFS, src: RegR30, dst: RegV0, exp: []byte{0xc0, 0x3, 0x22, 0x9e}}, - {name: "SCVTFS/src=R30,dst=V31", inst: SCVTFS, src: RegR30, dst: RegV31, exp: []byte{0xdf, 0x3, 0x22, 0x9e}}, - {name: "SCVTFWS/src=RZR,dst=V0", inst: SCVTFWS, src: RegRZR, dst: RegV0, exp: []byte{0xe0, 0x3, 0x22, 0x1e}}, - {name: "SCVTFWS/src=RZR,dst=V31", inst: SCVTFWS, src: RegRZR, dst: RegV31, exp: []byte{0xff, 0x3, 0x22, 0x1e}}, - {name: "SCVTFWS/src=R10,dst=V0", inst: SCVTFWS, src: RegR10, dst: RegV0, exp: []byte{0x40, 0x1, 0x22, 0x1e}}, - {name: "SCVTFWS/src=R10,dst=V31", inst: SCVTFWS, src: RegR10, dst: RegV31, exp: []byte{0x5f, 0x1, 0x22, 0x1e}}, - {name: "SCVTFWS/src=R30,dst=V0", inst: SCVTFWS, src: RegR30, dst: RegV0, exp: []byte{0xc0, 0x3, 0x22, 0x1e}}, - {name: "SCVTFWS/src=R30,dst=V31", inst: SCVTFWS, src: RegR30, dst: RegV31, exp: []byte{0xdf, 0x3, 0x22, 0x1e}}, - {name: "UCVTFD/src=RZR,dst=V0", inst: UCVTFD, src: RegRZR, dst: RegV0, exp: []byte{0xe0, 0x3, 0x63, 0x9e}}, - {name: "UCVTFD/src=RZR,dst=V31", inst: UCVTFD, src: RegRZR, dst: RegV31, exp: []byte{0xff, 0x3, 0x63, 0x9e}}, - {name: "UCVTFD/src=R10,dst=V0", inst: UCVTFD, src: RegR10, dst: RegV0, exp: []byte{0x40, 0x1, 0x63, 0x9e}}, - {name: "UCVTFD/src=R10,dst=V31", inst: UCVTFD, src: RegR10, dst: RegV31, exp: []byte{0x5f, 0x1, 0x63, 0x9e}}, - {name: "UCVTFD/src=R30,dst=V0", inst: UCVTFD, src: RegR30, dst: RegV0, exp: []byte{0xc0, 0x3, 0x63, 0x9e}}, - {name: "UCVTFD/src=R30,dst=V31", inst: UCVTFD, src: RegR30, dst: RegV31, exp: []byte{0xdf, 0x3, 0x63, 0x9e}}, - {name: "UCVTFWD/src=RZR,dst=V0", inst: UCVTFWD, src: RegRZR, dst: RegV0, exp: []byte{0xe0, 0x3, 0x63, 0x1e}}, - {name: "UCVTFWD/src=RZR,dst=V31", inst: UCVTFWD, src: RegRZR, dst: RegV31, exp: []byte{0xff, 0x3, 0x63, 0x1e}}, - {name: "UCVTFWD/src=R10,dst=V0", inst: UCVTFWD, src: RegR10, dst: RegV0, exp: []byte{0x40, 0x1, 0x63, 0x1e}}, - {name: "UCVTFWD/src=R10,dst=V31", inst: UCVTFWD, src: RegR10, dst: RegV31, exp: []byte{0x5f, 0x1, 0x63, 0x1e}}, - {name: "UCVTFWD/src=R30,dst=V0", inst: UCVTFWD, src: RegR30, dst: RegV0, exp: []byte{0xc0, 0x3, 0x63, 0x1e}}, - {name: "UCVTFWD/src=R30,dst=V31", inst: UCVTFWD, src: RegR30, dst: RegV31, exp: []byte{0xdf, 0x3, 0x63, 0x1e}}, - {name: "UCVTFS/src=RZR,dst=V0", inst: UCVTFS, src: RegRZR, dst: RegV0, exp: []byte{0xe0, 0x3, 0x23, 0x9e}}, - {name: "UCVTFS/src=RZR,dst=V31", inst: UCVTFS, src: RegRZR, dst: RegV31, exp: []byte{0xff, 0x3, 0x23, 0x9e}}, - {name: "UCVTFS/src=R10,dst=V0", inst: UCVTFS, src: RegR10, dst: RegV0, exp: []byte{0x40, 0x1, 0x23, 0x9e}}, - {name: "UCVTFS/src=R10,dst=V31", inst: UCVTFS, src: RegR10, dst: RegV31, exp: []byte{0x5f, 0x1, 0x23, 0x9e}}, - {name: "UCVTFS/src=R30,dst=V0", inst: UCVTFS, src: RegR30, dst: RegV0, exp: []byte{0xc0, 0x3, 0x23, 0x9e}}, - {name: "UCVTFS/src=R30,dst=V31", inst: UCVTFS, src: RegR30, dst: RegV31, exp: []byte{0xdf, 0x3, 0x23, 0x9e}}, - {name: "UCVTFWS/src=RZR,dst=V0", inst: UCVTFWS, src: RegRZR, dst: RegV0, exp: []byte{0xe0, 0x3, 0x23, 0x1e}}, - {name: "UCVTFWS/src=RZR,dst=V31", inst: UCVTFWS, src: RegRZR, dst: RegV31, exp: []byte{0xff, 0x3, 0x23, 0x1e}}, - {name: "UCVTFWS/src=R10,dst=V0", inst: UCVTFWS, src: RegR10, dst: RegV0, exp: []byte{0x40, 0x1, 0x23, 0x1e}}, - {name: "UCVTFWS/src=R10,dst=V31", inst: UCVTFWS, src: RegR10, dst: RegV31, exp: []byte{0x5f, 0x1, 0x23, 0x1e}}, - {name: "UCVTFWS/src=R30,dst=V0", inst: UCVTFWS, src: RegR30, dst: RegV0, exp: []byte{0xc0, 0x3, 0x23, 0x1e}}, - {name: "UCVTFWS/src=R30,dst=V31", inst: UCVTFWS, src: RegR30, dst: RegV31, exp: []byte{0xdf, 0x3, 0x23, 0x1e}}, - {name: "SXTB/src=RZR,dst=RZR", inst: SXTB, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0x2a}}, - {name: "SXTB/src=RZR,dst=R10", inst: SXTB, src: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1f, 0x2a}}, - {name: "SXTB/src=RZR,dst=R30", inst: SXTB, src: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1f, 0x2a}}, - {name: "SXTB/src=R10,dst=RZR", inst: SXTB, src: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1d, 0x40, 0x93}}, - {name: "SXTB/src=R10,dst=R10", inst: SXTB, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1d, 0x40, 0x93}}, - {name: "SXTB/src=R10,dst=R30", inst: SXTB, src: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1d, 0x40, 0x93}}, - {name: "SXTB/src=R30,dst=RZR", inst: SXTB, src: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x1f, 0x40, 0x93}}, - {name: "SXTB/src=R30,dst=R10", inst: SXTB, src: RegR30, dst: RegR10, exp: []byte{0xca, 0x1f, 0x40, 0x93}}, - {name: "SXTB/src=R30,dst=R30", inst: SXTB, src: RegR30, dst: RegR30, exp: []byte{0xde, 0x1f, 0x40, 0x93}}, - {name: "SXTBW/src=RZR,dst=RZR", inst: SXTBW, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0x2a}}, - {name: "SXTBW/src=RZR,dst=R10", inst: SXTBW, src: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1f, 0x2a}}, - {name: "SXTBW/src=RZR,dst=R30", inst: SXTBW, src: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1f, 0x2a}}, - {name: "SXTBW/src=R10,dst=RZR", inst: SXTBW, src: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1d, 0x0, 0x13}}, - {name: "SXTBW/src=R10,dst=R10", inst: SXTBW, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1d, 0x0, 0x13}}, - {name: "SXTBW/src=R10,dst=R30", inst: SXTBW, src: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1d, 0x0, 0x13}}, - {name: "SXTBW/src=R30,dst=RZR", inst: SXTBW, src: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x1f, 0x0, 0x13}}, - {name: "SXTBW/src=R30,dst=R10", inst: SXTBW, src: RegR30, dst: RegR10, exp: []byte{0xca, 0x1f, 0x0, 0x13}}, - {name: "SXTBW/src=R30,dst=R30", inst: SXTBW, src: RegR30, dst: RegR30, exp: []byte{0xde, 0x1f, 0x0, 0x13}}, - {name: "SXTH/src=RZR,dst=RZR", inst: SXTH, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0x2a}}, - {name: "SXTH/src=RZR,dst=R10", inst: SXTH, src: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1f, 0x2a}}, - {name: "SXTH/src=RZR,dst=R30", inst: SXTH, src: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1f, 0x2a}}, - {name: "SXTH/src=R10,dst=RZR", inst: SXTH, src: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x3d, 0x40, 0x93}}, - {name: "SXTH/src=R10,dst=R10", inst: SXTH, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0x3d, 0x40, 0x93}}, - {name: "SXTH/src=R10,dst=R30", inst: SXTH, src: RegR10, dst: RegR30, exp: []byte{0x5e, 0x3d, 0x40, 0x93}}, - {name: "SXTH/src=R30,dst=RZR", inst: SXTH, src: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3f, 0x40, 0x93}}, - {name: "SXTH/src=R30,dst=R10", inst: SXTH, src: RegR30, dst: RegR10, exp: []byte{0xca, 0x3f, 0x40, 0x93}}, - {name: "SXTH/src=R30,dst=R30", inst: SXTH, src: RegR30, dst: RegR30, exp: []byte{0xde, 0x3f, 0x40, 0x93}}, - {name: "SXTHW/src=RZR,dst=RZR", inst: SXTHW, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0x2a}}, - {name: "SXTHW/src=RZR,dst=R10", inst: SXTHW, src: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1f, 0x2a}}, - {name: "SXTHW/src=RZR,dst=R30", inst: SXTHW, src: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1f, 0x2a}}, - {name: "SXTHW/src=R10,dst=RZR", inst: SXTHW, src: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x3d, 0x0, 0x13}}, - {name: "SXTHW/src=R10,dst=R10", inst: SXTHW, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0x3d, 0x0, 0x13}}, - {name: "SXTHW/src=R10,dst=R30", inst: SXTHW, src: RegR10, dst: RegR30, exp: []byte{0x5e, 0x3d, 0x0, 0x13}}, - {name: "SXTHW/src=R30,dst=RZR", inst: SXTHW, src: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3f, 0x0, 0x13}}, - {name: "SXTHW/src=R30,dst=R10", inst: SXTHW, src: RegR30, dst: RegR10, exp: []byte{0xca, 0x3f, 0x0, 0x13}}, - {name: "SXTHW/src=R30,dst=R30", inst: SXTHW, src: RegR30, dst: RegR30, exp: []byte{0xde, 0x3f, 0x0, 0x13}}, - {name: "SXTW/src=RZR,dst=RZR", inst: SXTW, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0x2a}}, - {name: "SXTW/src=RZR,dst=R10", inst: SXTW, src: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1f, 0x2a}}, - {name: "SXTW/src=RZR,dst=R30", inst: SXTW, src: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1f, 0x2a}}, - {name: "SXTW/src=R10,dst=RZR", inst: SXTW, src: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x7d, 0x40, 0x93}}, - {name: "SXTW/src=R10,dst=R10", inst: SXTW, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0x7d, 0x40, 0x93}}, - {name: "SXTW/src=R10,dst=R30", inst: SXTW, src: RegR10, dst: RegR30, exp: []byte{0x5e, 0x7d, 0x40, 0x93}}, - {name: "SXTW/src=R30,dst=RZR", inst: SXTW, src: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x7f, 0x40, 0x93}}, - {name: "SXTW/src=R30,dst=R10", inst: SXTW, src: RegR30, dst: RegR10, exp: []byte{0xca, 0x7f, 0x40, 0x93}}, - {name: "SXTW/src=R30,dst=R30", inst: SXTW, src: RegR30, dst: RegR30, exp: []byte{0xde, 0x7f, 0x40, 0x93}}, - } - - for _, tc := range tests { - t.Run(tc.name, func(t *testing.T) { - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - a := NewAssembler(asm.NilRegister) - buf := code.NextCodeSection() - err := a.encodeRegisterToRegister(buf, &nodeImpl{instruction: tc.inst, srcReg: tc.src, dstReg: tc.dst}) - require.NoError(t, err) - - actual := buf.Bytes() - require.Equal(t, tc.exp, actual[:4], hex.EncodeToString(actual[:4])) - }) - } -} diff --git a/internal/asm/arm64/impl_4_test.go b/internal/asm/arm64/impl_4_test.go deleted file mode 100644 index d73e28d12c..0000000000 --- a/internal/asm/arm64/impl_4_test.go +++ /dev/null @@ -1,803 +0,0 @@ -package arm64 - -import ( - "encoding/hex" - "fmt" - "math" - "testing" - - "github.com/tetratelabs/wazero/internal/asm" - "github.com/tetratelabs/wazero/internal/testing/require" -) - -func TestAssemblerImpl_encodeJumpToRegister(t *testing.T) { - t.Run("error", func(t *testing.T) { - tests := []struct { - n *nodeImpl - expErr string - }{ - { - n: &nodeImpl{instruction: ADD, types: operandTypesNoneToRegister}, - expErr: "ADD is unsupported for NoneToRegister type", - }, - { - n: &nodeImpl{instruction: RET, dstReg: asm.NilRegister}, - expErr: "invalid destination register: nil is not integer", - }, - { - n: &nodeImpl{instruction: RET, dstReg: RegV0}, - expErr: "invalid destination register: V0 is not integer", - }, - } - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - for _, tt := range tests { - tc := tt - a := NewAssembler(asm.NilRegister) - buf := code.NextCodeSection() - err := a.encodeJumpToRegister(buf, tc.n) - require.EqualError(t, err, tc.expErr) - } - }) - - tests := []struct { - name string - expHex string - inst asm.Instruction - reg asm.Register - }{ - { - name: "B", - inst: B, - reg: RegR0, - expHex: "00001fd6", - }, - { - name: "B", - inst: B, - reg: RegR5, - expHex: "a0001fd6", - }, - { - name: "B", - inst: B, - reg: RegR30, - expHex: "c0031fd6", - }, - { - name: "RET", - inst: RET, - reg: RegR0, - expHex: "00005fd6", - }, - { - name: "RET", - inst: RET, - reg: RegR5, - expHex: "a0005fd6", - }, - { - name: "RET", - inst: RET, - reg: RegR30, - expHex: "c0035fd6", - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - a := NewAssembler(asm.NilRegister) - buf := code.NextCodeSection() - err := a.encodeJumpToRegister(buf, &nodeImpl{instruction: tc.inst, dstReg: tc.reg}) - require.NoError(t, err) - - actual := buf.Bytes() - require.Equal(t, tc.expHex, hex.EncodeToString(actual)) - }) - } -} - -func TestAssemblerImpl_EncodeMemoryToRegister(t *testing.T) { - t.Run("error", func(t *testing.T) { - tests := []struct { - n *nodeImpl - expErr string - }{ - { - n: &nodeImpl{instruction: SUB, types: operandTypesMemoryToRegister}, - expErr: "SUB is unsupported for MemoryToRegister type", - }, - } - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - for _, tt := range tests { - tc := tt - a := NewAssembler(asm.NilRegister) - buf := code.NextCodeSection() - err := a.encodeMemoryToRegister(buf, tc.n) - require.EqualError(t, err, tc.expErr) - } - }) - - tests := []struct { - name string - n *nodeImpl - exp []byte - }{ - {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0xffffffffffffffff", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: -1, dstReg: RegR11}, exp: []byte{0xab, 0xf0, 0x5f, 0xf8}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0x0", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: 0, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x40, 0xf9}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0x1", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: 1, dstReg: RegR11}, exp: []byte{0xab, 0x10, 0x40, 0xf8}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0x2", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: 2, dstReg: RegR11}, exp: []byte{0xab, 0x20, 0x40, 0xf8}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: -2, dstReg: RegR11}, exp: []byte{0xab, 0xe0, 0x5f, 0xf8}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0xf", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: 15, dstReg: RegR11}, exp: []byte{0xab, 0xf0, 0x40, 0xf8}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: -15, dstReg: RegR11}, exp: []byte{0xab, 0x10, 0x5f, 0xf8}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0x10", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: 16, dstReg: RegR11}, exp: []byte{0xab, 0x8, 0x40, 0xf9}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0xf", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: 15, dstReg: RegR11}, exp: []byte{0xab, 0xf0, 0x40, 0xf8}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0x11", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: 17, dstReg: RegR11}, exp: []byte{0xab, 0x10, 0x41, 0xf8}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0xffffffffffffff80", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: -128, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x58, 0xf8}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0xffffffffffffff00", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: -256, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x50, 0xf8}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0x50", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: 80, dstReg: RegR11}, exp: []byte{0xab, 0x28, 0x40, 0xf9}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0xffffffffffffff80", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: -128, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x58, 0xf8}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0xff", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: 255, dstReg: RegR11}, exp: []byte{0xab, 0xf0, 0x4f, 0xf8}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0x1000", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: 4096, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x48, 0xf9}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0x2000", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: 8192, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x50, 0xf9}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0x7ff8", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: 32760, dstReg: RegR11}, exp: []byte{0xab, 0xfc, 0x7f, 0xf9}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0xfff0", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: 65520, dstReg: RegR11}, exp: []byte{0xbb, 0x20, 0x40, 0x91, 0x6b, 0xfb, 0x7f, 0xf9}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0xffe8", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: 65512, dstReg: RegR11}, exp: []byte{0xbb, 0x20, 0x40, 0x91, 0x6b, 0xf7, 0x7f, 0xf9}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0xffe0", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: 65504, dstReg: RegR11}, exp: []byte{0xbb, 0x20, 0x40, 0x91, 0x6b, 0xf3, 0x7f, 0xf9}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0x8000000", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: 134217728, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0x7b, 0xf8}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0x40000000", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: 1073741824, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0x7b, 0xf8}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0x40000008", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: 1073741832, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0x7b, 0xf8}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0x3ffffff8", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: 1073741816, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0x7b, 0xf8}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0x40000010", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: 1073741840, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0x7b, 0xf8}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0x3ffffff0", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: 1073741808, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0x7b, 0xf8}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0x7ffffff8", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: 2147483640, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0x7b, 0xf8}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0x10000004", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: 268435460, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0x7b, 0xf8}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0x100008", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: 1048584, dstReg: RegR11}, exp: []byte{0xbb, 0x0, 0x44, 0x91, 0x6b, 0x7, 0x40, 0xf9}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=0xffff8", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcConst: 1048568, dstReg: RegR11}, exp: []byte{0xbb, 0xe0, 0x43, 0x91, 0x6b, 0xff, 0x7f, 0xf9}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R5,offset=RegR8", n: &nodeImpl{instruction: LDRD, srcReg: RegR5, srcReg2: RegR8, dstReg: RegR11}, exp: []byte{0xab, 0x68, 0x68, 0xf8}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0xffffffffffffffff", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: -1, dstReg: RegR11}, exp: []byte{0xcb, 0xf3, 0x5f, 0xf8}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0x0", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: 0, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x40, 0xf9}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0x1", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: 1, dstReg: RegR11}, exp: []byte{0xcb, 0x13, 0x40, 0xf8}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0x2", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: 2, dstReg: RegR11}, exp: []byte{0xcb, 0x23, 0x40, 0xf8}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: -2, dstReg: RegR11}, exp: []byte{0xcb, 0xe3, 0x5f, 0xf8}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0xf", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: 15, dstReg: RegR11}, exp: []byte{0xcb, 0xf3, 0x40, 0xf8}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: -15, dstReg: RegR11}, exp: []byte{0xcb, 0x13, 0x5f, 0xf8}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0x10", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: 16, dstReg: RegR11}, exp: []byte{0xcb, 0xb, 0x40, 0xf9}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0xf", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: 15, dstReg: RegR11}, exp: []byte{0xcb, 0xf3, 0x40, 0xf8}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0x11", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: 17, dstReg: RegR11}, exp: []byte{0xcb, 0x13, 0x41, 0xf8}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: -128, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x58, 0xf8}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0xffffffffffffff00", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: -256, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x50, 0xf8}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0x50", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: 80, dstReg: RegR11}, exp: []byte{0xcb, 0x2b, 0x40, 0xf9}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: -128, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x58, 0xf8}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0xff", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: 255, dstReg: RegR11}, exp: []byte{0xcb, 0xf3, 0x4f, 0xf8}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0x1000", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: 4096, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x48, 0xf9}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0x2000", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: 8192, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x50, 0xf9}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0x7ff8", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: 32760, dstReg: RegR11}, exp: []byte{0xcb, 0xff, 0x7f, 0xf9}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0xfff0", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: 65520, dstReg: RegR11}, exp: []byte{0xdb, 0x23, 0x40, 0x91, 0x6b, 0xfb, 0x7f, 0xf9}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0xffe8", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: 65512, dstReg: RegR11}, exp: []byte{0xdb, 0x23, 0x40, 0x91, 0x6b, 0xf7, 0x7f, 0xf9}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0xffe0", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: 65504, dstReg: RegR11}, exp: []byte{0xdb, 0x23, 0x40, 0x91, 0x6b, 0xf3, 0x7f, 0xf9}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0x8000000", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: 134217728, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0x7b, 0xf8}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0x40000000", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: 1073741824, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0x7b, 0xf8}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0x40000008", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: 1073741832, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0x7b, 0xf8}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0x3ffffff8", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: 1073741816, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0x7b, 0xf8}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0x40000010", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: 1073741840, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0x7b, 0xf8}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0x3ffffff0", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: 1073741808, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0x7b, 0xf8}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0x7ffffff8", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: 2147483640, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0x7b, 0xf8}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0x10000004", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: 268435460, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0x7b, 0xf8}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0x100008", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: 1048584, dstReg: RegR11}, exp: []byte{0xdb, 0x3, 0x44, 0x91, 0x6b, 0x7, 0x40, 0xf9}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=0xffff8", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcConst: 1048568, dstReg: RegR11}, exp: []byte{0xdb, 0xe3, 0x43, 0x91, 0x6b, 0xff, 0x7f, 0xf9}}, - {name: "LDRD/RegisterOffset/dst=R11,base=R30,offset=RegR8", n: &nodeImpl{instruction: LDRD, srcReg: RegR30, srcReg2: RegR8, dstReg: RegR11}, exp: []byte{0xcb, 0x6b, 0x68, 0xf8}}, - {name: "LDRW/RegisterOffset/dst=R11,base=R5,offset=0xffffffffffffffff", n: &nodeImpl{instruction: LDRW, srcReg: RegR5, srcConst: -1, dstReg: RegR11}, exp: []byte{0xab, 0xf0, 0x5f, 0xb8}}, - {name: "LDRW/RegisterOffset/dst=R11,base=R5,offset=0x0", n: &nodeImpl{instruction: LDRW, srcReg: RegR5, srcConst: 0, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x40, 0xb9}}, - {name: "LDRW/RegisterOffset/dst=R11,base=R5,offset=0x1", n: &nodeImpl{instruction: LDRW, srcReg: RegR5, srcConst: 1, dstReg: RegR11}, exp: []byte{0xab, 0x10, 0x40, 0xb8}}, - {name: "LDRW/RegisterOffset/dst=R11,base=R5,offset=0x2", n: &nodeImpl{instruction: LDRW, srcReg: RegR5, srcConst: 2, dstReg: RegR11}, exp: []byte{0xab, 0x20, 0x40, 0xb8}}, - {name: "LDRW/RegisterOffset/dst=R11,base=R5,offsetReg=R12", n: &nodeImpl{instruction: LDRW, srcReg: RegR5, srcReg2: RegR12, dstReg: RegR11}, exp: []byte{0xab, 0x68, 0x6c, 0xb8}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0xffffffffffffffff", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: -1, dstReg: RegR11}, exp: []byte{0xab, 0xf0, 0x9f, 0xb8}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0x0", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: 0, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x80, 0xb9}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0x1", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: 1, dstReg: RegR11}, exp: []byte{0xab, 0x10, 0x80, 0xb8}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0x2", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: 2, dstReg: RegR11}, exp: []byte{0xab, 0x20, 0x80, 0xb8}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: -2, dstReg: RegR11}, exp: []byte{0xab, 0xe0, 0x9f, 0xb8}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0xf", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: 15, dstReg: RegR11}, exp: []byte{0xab, 0xf0, 0x80, 0xb8}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: -15, dstReg: RegR11}, exp: []byte{0xab, 0x10, 0x9f, 0xb8}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0x10", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: 16, dstReg: RegR11}, exp: []byte{0xab, 0x10, 0x80, 0xb9}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0xf", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: 15, dstReg: RegR11}, exp: []byte{0xab, 0xf0, 0x80, 0xb8}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0x11", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: 17, dstReg: RegR11}, exp: []byte{0xab, 0x10, 0x81, 0xb8}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0xffffffffffffff80", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: -128, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x98, 0xb8}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0xffffffffffffff00", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: -256, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x90, 0xb8}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0x50", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: 80, dstReg: RegR11}, exp: []byte{0xab, 0x50, 0x80, 0xb9}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0xffffffffffffff80", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: -128, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x98, 0xb8}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0xff", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: 255, dstReg: RegR11}, exp: []byte{0xab, 0xf0, 0x8f, 0xb8}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0x1000", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: 4096, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x90, 0xb9}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0x2000", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: 8192, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0xa0, 0xb9}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0x7ff8", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: 32760, dstReg: RegR11}, exp: []byte{0xbb, 0x10, 0x40, 0x91, 0x6b, 0xfb, 0xbf, 0xb9}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0xfff0", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: 65520, dstReg: RegR11}, exp: []byte{0xbb, 0x30, 0x40, 0x91, 0x6b, 0xf3, 0xbf, 0xb9}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0xffe8", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: 65512, dstReg: RegR11}, exp: []byte{0xbb, 0x30, 0x40, 0x91, 0x6b, 0xeb, 0xbf, 0xb9}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0xffe0", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: 65504, dstReg: RegR11}, exp: []byte{0xbb, 0x30, 0x40, 0x91, 0x6b, 0xe3, 0xbf, 0xb9}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0x8000000", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: 134217728, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0xbb, 0xb8}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0x40000000", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: 1073741824, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0xbb, 0xb8}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0x40000008", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: 1073741832, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0xbb, 0xb8}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0x3ffffff8", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: 1073741816, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0xbb, 0xb8}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0x40000010", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: 1073741840, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0xbb, 0xb8}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0x3ffffff0", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: 1073741808, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0xbb, 0xb8}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0x7ffffff8", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: 2147483640, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0xbb, 0xb8}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0x10000004", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: 268435460, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0xbb, 0xb8}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0x100008", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: 1048584, dstReg: RegR11}, exp: []byte{0xbb, 0x0, 0x44, 0x91, 0x6b, 0xb, 0x80, 0xb9}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=0xffff8", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcConst: 1048568, dstReg: RegR11}, exp: []byte{0xbb, 0xf0, 0x43, 0x91, 0x6b, 0xfb, 0xbf, 0xb9}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R5,offset=RegR8", n: &nodeImpl{instruction: LDRSW, srcReg: RegR5, srcReg2: RegR8, dstReg: RegR11}, exp: []byte{0xab, 0x68, 0xa8, 0xb8}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0xffffffffffffffff", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: -1, dstReg: RegR11}, exp: []byte{0xcb, 0xf3, 0x9f, 0xb8}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0x0", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: 0, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x80, 0xb9}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0x1", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: 1, dstReg: RegR11}, exp: []byte{0xcb, 0x13, 0x80, 0xb8}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0x2", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: 2, dstReg: RegR11}, exp: []byte{0xcb, 0x23, 0x80, 0xb8}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: -2, dstReg: RegR11}, exp: []byte{0xcb, 0xe3, 0x9f, 0xb8}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0xf", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: 15, dstReg: RegR11}, exp: []byte{0xcb, 0xf3, 0x80, 0xb8}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: -15, dstReg: RegR11}, exp: []byte{0xcb, 0x13, 0x9f, 0xb8}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0x10", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: 16, dstReg: RegR11}, exp: []byte{0xcb, 0x13, 0x80, 0xb9}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0xf", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: 15, dstReg: RegR11}, exp: []byte{0xcb, 0xf3, 0x80, 0xb8}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0x11", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: 17, dstReg: RegR11}, exp: []byte{0xcb, 0x13, 0x81, 0xb8}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: -128, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x98, 0xb8}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0xffffffffffffff00", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: -256, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x90, 0xb8}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0x50", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: 80, dstReg: RegR11}, exp: []byte{0xcb, 0x53, 0x80, 0xb9}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: -128, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x98, 0xb8}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0xff", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: 255, dstReg: RegR11}, exp: []byte{0xcb, 0xf3, 0x8f, 0xb8}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0x1000", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: 4096, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x90, 0xb9}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0x2000", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: 8192, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0xa0, 0xb9}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0x7ff8", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: 32760, dstReg: RegR11}, exp: []byte{0xdb, 0x13, 0x40, 0x91, 0x6b, 0xfb, 0xbf, 0xb9}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0xfff0", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: 65520, dstReg: RegR11}, exp: []byte{0xdb, 0x33, 0x40, 0x91, 0x6b, 0xf3, 0xbf, 0xb9}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0xffe8", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: 65512, dstReg: RegR11}, exp: []byte{0xdb, 0x33, 0x40, 0x91, 0x6b, 0xeb, 0xbf, 0xb9}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0xffe0", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: 65504, dstReg: RegR11}, exp: []byte{0xdb, 0x33, 0x40, 0x91, 0x6b, 0xe3, 0xbf, 0xb9}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0x8000000", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: 134217728, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0xbb, 0xb8}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0x40000000", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: 1073741824, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0xbb, 0xb8}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0x40000008", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: 1073741832, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0xbb, 0xb8}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0x3ffffff8", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: 1073741816, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0xbb, 0xb8}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0x40000010", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: 1073741840, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0xbb, 0xb8}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0x3ffffff0", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: 1073741808, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0xbb, 0xb8}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0x7ffffff8", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: 2147483640, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0xbb, 0xb8}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0x10000004", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: 268435460, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0xbb, 0xb8}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0x100008", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: 1048584, dstReg: RegR11}, exp: []byte{0xdb, 0x3, 0x44, 0x91, 0x6b, 0xb, 0x80, 0xb9}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=0xffff8", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcConst: 1048568, dstReg: RegR11}, exp: []byte{0xdb, 0xf3, 0x43, 0x91, 0x6b, 0xfb, 0xbf, 0xb9}}, - {name: "LDRSW/RegisterOffset/dst=R11,base=R30,offset=RegR8", n: &nodeImpl{instruction: LDRSW, srcReg: RegR30, srcReg2: RegR8, dstReg: RegR11}, exp: []byte{0xcb, 0x6b, 0xa8, 0xb8}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0xffffffffffffffff", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: -1, dstReg: RegR11}, exp: []byte{0xab, 0xf0, 0x9f, 0x78}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0x0", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: 0, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x80, 0x79}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0x1", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: 1, dstReg: RegR11}, exp: []byte{0xab, 0x10, 0x80, 0x78}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0x2", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: 2, dstReg: RegR11}, exp: []byte{0xab, 0x4, 0x80, 0x79}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: -2, dstReg: RegR11}, exp: []byte{0xab, 0xe0, 0x9f, 0x78}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0xf", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: 15, dstReg: RegR11}, exp: []byte{0xab, 0xf0, 0x80, 0x78}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: -15, dstReg: RegR11}, exp: []byte{0xab, 0x10, 0x9f, 0x78}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0x10", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: 16, dstReg: RegR11}, exp: []byte{0xab, 0x20, 0x80, 0x79}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0xf", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: 15, dstReg: RegR11}, exp: []byte{0xab, 0xf0, 0x80, 0x78}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0x11", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: 17, dstReg: RegR11}, exp: []byte{0xab, 0x10, 0x81, 0x78}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0xffffffffffffff80", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: -128, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x98, 0x78}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0xffffffffffffff00", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: -256, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x90, 0x78}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0x50", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: 80, dstReg: RegR11}, exp: []byte{0xab, 0xa0, 0x80, 0x79}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0xffffffffffffff80", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: -128, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x98, 0x78}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0xff", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: 255, dstReg: RegR11}, exp: []byte{0xab, 0xf0, 0x8f, 0x78}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0x1000", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: 4096, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0xa0, 0x79}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0x2000", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: 8192, dstReg: RegR11}, exp: []byte{0xbb, 0x8, 0x40, 0x91, 0x6b, 0x3, 0x80, 0x79}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0x7ff8", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: 32760, dstReg: RegR11}, exp: []byte{0xbb, 0x18, 0x40, 0x91, 0x6b, 0xf3, 0xbf, 0x79}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0xfff0", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: 65520, dstReg: RegR11}, exp: []byte{0xbb, 0x38, 0x40, 0x91, 0x6b, 0xe3, 0xbf, 0x79}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0xffe8", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: 65512, dstReg: RegR11}, exp: []byte{0xbb, 0x38, 0x40, 0x91, 0x6b, 0xd3, 0xbf, 0x79}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0xffe0", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: 65504, dstReg: RegR11}, exp: []byte{0xbb, 0x38, 0x40, 0x91, 0x6b, 0xc3, 0xbf, 0x79}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0x8000000", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: 134217728, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0xbb, 0x78}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0x40000000", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: 1073741824, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0xbb, 0x78}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0x40000008", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: 1073741832, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0xbb, 0x78}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0x3ffffff8", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: 1073741816, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0xbb, 0x78}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0x40000010", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: 1073741840, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0xbb, 0x78}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0x3ffffff0", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: 1073741808, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0xbb, 0x78}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0x7ffffff8", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: 2147483640, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0xbb, 0x78}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0x10000004", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: 268435460, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0xbb, 0x78}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0x100008", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: 1048584, dstReg: RegR11}, exp: []byte{0xbb, 0x0, 0x44, 0x91, 0x6b, 0x13, 0x80, 0x79}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=0xffff8", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcConst: 1048568, dstReg: RegR11}, exp: []byte{0xbb, 0xf8, 0x43, 0x91, 0x6b, 0xf3, 0xbf, 0x79}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R5,offset=RegR8", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR5, srcReg2: RegR8, dstReg: RegR11}, exp: []byte{0xab, 0x68, 0xa8, 0x78}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0xffffffffffffffff", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: -1, dstReg: RegR11}, exp: []byte{0xcb, 0xf3, 0x9f, 0x78}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0x0", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: 0, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x80, 0x79}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0x1", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: 1, dstReg: RegR11}, exp: []byte{0xcb, 0x13, 0x80, 0x78}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0x2", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: 2, dstReg: RegR11}, exp: []byte{0xcb, 0x7, 0x80, 0x79}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: -2, dstReg: RegR11}, exp: []byte{0xcb, 0xe3, 0x9f, 0x78}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0xf", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: 15, dstReg: RegR11}, exp: []byte{0xcb, 0xf3, 0x80, 0x78}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: -15, dstReg: RegR11}, exp: []byte{0xcb, 0x13, 0x9f, 0x78}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0x10", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: 16, dstReg: RegR11}, exp: []byte{0xcb, 0x23, 0x80, 0x79}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0xf", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: 15, dstReg: RegR11}, exp: []byte{0xcb, 0xf3, 0x80, 0x78}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0x11", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: 17, dstReg: RegR11}, exp: []byte{0xcb, 0x13, 0x81, 0x78}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: -128, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x98, 0x78}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0xffffffffffffff00", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: -256, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x90, 0x78}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0x50", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: 80, dstReg: RegR11}, exp: []byte{0xcb, 0xa3, 0x80, 0x79}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: -128, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x98, 0x78}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0xff", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: 255, dstReg: RegR11}, exp: []byte{0xcb, 0xf3, 0x8f, 0x78}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0x1000", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: 4096, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0xa0, 0x79}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0x2000", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: 8192, dstReg: RegR11}, exp: []byte{0xdb, 0xb, 0x40, 0x91, 0x6b, 0x3, 0x80, 0x79}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0x7ff8", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: 32760, dstReg: RegR11}, exp: []byte{0xdb, 0x1b, 0x40, 0x91, 0x6b, 0xf3, 0xbf, 0x79}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0xfff0", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: 65520, dstReg: RegR11}, exp: []byte{0xdb, 0x3b, 0x40, 0x91, 0x6b, 0xe3, 0xbf, 0x79}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0xffe8", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: 65512, dstReg: RegR11}, exp: []byte{0xdb, 0x3b, 0x40, 0x91, 0x6b, 0xd3, 0xbf, 0x79}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0xffe0", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: 65504, dstReg: RegR11}, exp: []byte{0xdb, 0x3b, 0x40, 0x91, 0x6b, 0xc3, 0xbf, 0x79}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0x8000000", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: 134217728, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0xbb, 0x78}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0x40000000", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: 1073741824, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0xbb, 0x78}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0x40000008", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: 1073741832, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0xbb, 0x78}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0x3ffffff8", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: 1073741816, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0xbb, 0x78}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0x40000010", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: 1073741840, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0xbb, 0x78}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0x3ffffff0", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: 1073741808, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0xbb, 0x78}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0x7ffffff8", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: 2147483640, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0xbb, 0x78}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0x10000004", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: 268435460, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0xbb, 0x78}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0x100008", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: 1048584, dstReg: RegR11}, exp: []byte{0xdb, 0x3, 0x44, 0x91, 0x6b, 0x13, 0x80, 0x79}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=0xffff8", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcConst: 1048568, dstReg: RegR11}, exp: []byte{0xdb, 0xfb, 0x43, 0x91, 0x6b, 0xf3, 0xbf, 0x79}}, - {name: "LDRSHD/RegisterOffset/dst=R11,base=R30,offset=RegR8", n: &nodeImpl{instruction: LDRSHD, srcReg: RegR30, srcReg2: RegR8, dstReg: RegR11}, exp: []byte{0xcb, 0x6b, 0xa8, 0x78}}, - {name: "LDRSHW/RegisterOffset/dst=R11,base=R5,offset=0xffffffffffffffff", n: &nodeImpl{instruction: LDRSHW, srcReg: RegR5, srcConst: -1, dstReg: RegR11}, exp: []byte{0xab, 0xf0, 0xdf, 0x78}}, - {name: "LDRSHW/RegisterOffset/dst=R11,base=R5,offset=0x0", n: &nodeImpl{instruction: LDRSHW, srcReg: RegR5, srcConst: 0, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0xc0, 0x79}}, - {name: "LDRSHW/RegisterOffset/dst=R11,base=R5,offset=0x1", n: &nodeImpl{instruction: LDRSHW, srcReg: RegR5, srcConst: 1, dstReg: RegR11}, exp: []byte{0xab, 0x10, 0xc0, 0x78}}, - {name: "LDRSHW/RegisterOffset/dst=R11,base=R5,offset=0x2", n: &nodeImpl{instruction: LDRSHW, srcReg: RegR5, srcConst: 2, dstReg: RegR11}, exp: []byte{0xab, 0x4, 0xc0, 0x79}}, - {name: "LDRSHW/RegisterOffset/dst=R11,base=R5,offsetReg=R12", n: &nodeImpl{instruction: LDRSHW, srcReg: RegR5, srcReg2: RegR12, dstReg: RegR11}, exp: []byte{0xab, 0x68, 0xec, 0x78}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0xffffffffffffffff", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: -1, dstReg: RegR11}, exp: []byte{0xab, 0xf0, 0x5f, 0x78}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0x0", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: 0, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x40, 0x79}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0x1", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: 1, dstReg: RegR11}, exp: []byte{0xab, 0x10, 0x40, 0x78}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0x2", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: 2, dstReg: RegR11}, exp: []byte{0xab, 0x4, 0x40, 0x79}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: -2, dstReg: RegR11}, exp: []byte{0xab, 0xe0, 0x5f, 0x78}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0xf", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: 15, dstReg: RegR11}, exp: []byte{0xab, 0xf0, 0x40, 0x78}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: -15, dstReg: RegR11}, exp: []byte{0xab, 0x10, 0x5f, 0x78}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0x10", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: 16, dstReg: RegR11}, exp: []byte{0xab, 0x20, 0x40, 0x79}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0xf", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: 15, dstReg: RegR11}, exp: []byte{0xab, 0xf0, 0x40, 0x78}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0x11", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: 17, dstReg: RegR11}, exp: []byte{0xab, 0x10, 0x41, 0x78}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0xffffffffffffff80", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: -128, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x58, 0x78}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0xffffffffffffff00", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: -256, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x50, 0x78}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0x50", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: 80, dstReg: RegR11}, exp: []byte{0xab, 0xa0, 0x40, 0x79}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0xffffffffffffff80", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: -128, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x58, 0x78}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0xff", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: 255, dstReg: RegR11}, exp: []byte{0xab, 0xf0, 0x4f, 0x78}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0x1000", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: 4096, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x60, 0x79}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0x2000", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: 8192, dstReg: RegR11}, exp: []byte{0xbb, 0x8, 0x40, 0x91, 0x6b, 0x3, 0x40, 0x79}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0x7ff8", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: 32760, dstReg: RegR11}, exp: []byte{0xbb, 0x18, 0x40, 0x91, 0x6b, 0xf3, 0x7f, 0x79}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0xfff0", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: 65520, dstReg: RegR11}, exp: []byte{0xbb, 0x38, 0x40, 0x91, 0x6b, 0xe3, 0x7f, 0x79}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0xffe8", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: 65512, dstReg: RegR11}, exp: []byte{0xbb, 0x38, 0x40, 0x91, 0x6b, 0xd3, 0x7f, 0x79}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0xffe0", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: 65504, dstReg: RegR11}, exp: []byte{0xbb, 0x38, 0x40, 0x91, 0x6b, 0xc3, 0x7f, 0x79}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0x8000000", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: 134217728, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0x7b, 0x78}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0x40000000", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: 1073741824, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0x7b, 0x78}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0x40000008", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: 1073741832, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0x7b, 0x78}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0x3ffffff8", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: 1073741816, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0x7b, 0x78}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0x40000010", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: 1073741840, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0x7b, 0x78}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0x3ffffff0", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: 1073741808, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0x7b, 0x78}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0x7ffffff8", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: 2147483640, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0x7b, 0x78}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0x10000004", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: 268435460, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0x7b, 0x78}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0x100008", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: 1048584, dstReg: RegR11}, exp: []byte{0xbb, 0x0, 0x44, 0x91, 0x6b, 0x13, 0x40, 0x79}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=0xffff8", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcConst: 1048568, dstReg: RegR11}, exp: []byte{0xbb, 0xf8, 0x43, 0x91, 0x6b, 0xf3, 0x7f, 0x79}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R5,offset=RegR8", n: &nodeImpl{instruction: LDRH, srcReg: RegR5, srcReg2: RegR8, dstReg: RegR11}, exp: []byte{0xab, 0x68, 0x68, 0x78}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0xffffffffffffffff", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: -1, dstReg: RegR11}, exp: []byte{0xcb, 0xf3, 0x5f, 0x78}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0x0", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: 0, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x40, 0x79}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0x1", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: 1, dstReg: RegR11}, exp: []byte{0xcb, 0x13, 0x40, 0x78}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0x2", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: 2, dstReg: RegR11}, exp: []byte{0xcb, 0x7, 0x40, 0x79}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: -2, dstReg: RegR11}, exp: []byte{0xcb, 0xe3, 0x5f, 0x78}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0xf", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: 15, dstReg: RegR11}, exp: []byte{0xcb, 0xf3, 0x40, 0x78}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: -15, dstReg: RegR11}, exp: []byte{0xcb, 0x13, 0x5f, 0x78}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0x10", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: 16, dstReg: RegR11}, exp: []byte{0xcb, 0x23, 0x40, 0x79}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0xf", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: 15, dstReg: RegR11}, exp: []byte{0xcb, 0xf3, 0x40, 0x78}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0x11", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: 17, dstReg: RegR11}, exp: []byte{0xcb, 0x13, 0x41, 0x78}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: -128, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x58, 0x78}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0xffffffffffffff00", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: -256, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x50, 0x78}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0x50", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: 80, dstReg: RegR11}, exp: []byte{0xcb, 0xa3, 0x40, 0x79}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: -128, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x58, 0x78}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0xff", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: 255, dstReg: RegR11}, exp: []byte{0xcb, 0xf3, 0x4f, 0x78}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0x1000", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: 4096, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x60, 0x79}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0x2000", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: 8192, dstReg: RegR11}, exp: []byte{0xdb, 0xb, 0x40, 0x91, 0x6b, 0x3, 0x40, 0x79}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0x7ff8", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: 32760, dstReg: RegR11}, exp: []byte{0xdb, 0x1b, 0x40, 0x91, 0x6b, 0xf3, 0x7f, 0x79}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0xfff0", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: 65520, dstReg: RegR11}, exp: []byte{0xdb, 0x3b, 0x40, 0x91, 0x6b, 0xe3, 0x7f, 0x79}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0xffe8", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: 65512, dstReg: RegR11}, exp: []byte{0xdb, 0x3b, 0x40, 0x91, 0x6b, 0xd3, 0x7f, 0x79}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0xffe0", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: 65504, dstReg: RegR11}, exp: []byte{0xdb, 0x3b, 0x40, 0x91, 0x6b, 0xc3, 0x7f, 0x79}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0x8000000", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: 134217728, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0x7b, 0x78}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0x40000000", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: 1073741824, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0x7b, 0x78}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0x40000008", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: 1073741832, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0x7b, 0x78}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0x3ffffff8", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: 1073741816, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0x7b, 0x78}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0x40000010", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: 1073741840, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0x7b, 0x78}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0x3ffffff0", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: 1073741808, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0x7b, 0x78}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0x7ffffff8", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: 2147483640, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0x7b, 0x78}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0x10000004", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: 268435460, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0x7b, 0x78}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0x100008", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: 1048584, dstReg: RegR11}, exp: []byte{0xdb, 0x3, 0x44, 0x91, 0x6b, 0x13, 0x40, 0x79}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=0xffff8", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcConst: 1048568, dstReg: RegR11}, exp: []byte{0xdb, 0xfb, 0x43, 0x91, 0x6b, 0xf3, 0x7f, 0x79}}, - {name: "LDRH/RegisterOffset/dst=R11,base=R30,offset=RegR8", n: &nodeImpl{instruction: LDRH, srcReg: RegR30, srcReg2: RegR8, dstReg: RegR11}, exp: []byte{0xcb, 0x6b, 0x68, 0x78}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0xffffffffffffffff", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: -1, dstReg: RegR11}, exp: []byte{0xab, 0xf0, 0x9f, 0x38}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0x0", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: 0, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x80, 0x39}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0x1", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: 1, dstReg: RegR11}, exp: []byte{0xab, 0x4, 0x80, 0x39}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0x2", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: 2, dstReg: RegR11}, exp: []byte{0xab, 0x8, 0x80, 0x39}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: -2, dstReg: RegR11}, exp: []byte{0xab, 0xe0, 0x9f, 0x38}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0xf", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: 15, dstReg: RegR11}, exp: []byte{0xab, 0x3c, 0x80, 0x39}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: -15, dstReg: RegR11}, exp: []byte{0xab, 0x10, 0x9f, 0x38}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0x10", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: 16, dstReg: RegR11}, exp: []byte{0xab, 0x40, 0x80, 0x39}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0xf", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: 15, dstReg: RegR11}, exp: []byte{0xab, 0x3c, 0x80, 0x39}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0x11", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: 17, dstReg: RegR11}, exp: []byte{0xab, 0x44, 0x80, 0x39}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0xffffffffffffff80", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: -128, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x98, 0x38}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0xffffffffffffff00", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: -256, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x90, 0x38}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0x50", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: 80, dstReg: RegR11}, exp: []byte{0xab, 0x40, 0x81, 0x39}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0xffffffffffffff80", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: -128, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x98, 0x38}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0xff", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: 255, dstReg: RegR11}, exp: []byte{0xab, 0xfc, 0x83, 0x39}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0x1000", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: 4096, dstReg: RegR11}, exp: []byte{0xbb, 0x4, 0x40, 0x91, 0x6b, 0x3, 0x80, 0x39}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0x2000", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: 8192, dstReg: RegR11}, exp: []byte{0xbb, 0x8, 0x40, 0x91, 0x6b, 0x3, 0x80, 0x39}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0x7ff8", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: 32760, dstReg: RegR11}, exp: []byte{0xbb, 0x1c, 0x40, 0x91, 0x6b, 0xe3, 0xbf, 0x39}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0xfff0", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: 65520, dstReg: RegR11}, exp: []byte{0xbb, 0x3c, 0x40, 0x91, 0x6b, 0xc3, 0xbf, 0x39}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0xffe8", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: 65512, dstReg: RegR11}, exp: []byte{0xbb, 0x3c, 0x40, 0x91, 0x6b, 0xa3, 0xbf, 0x39}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0xffe0", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: 65504, dstReg: RegR11}, exp: []byte{0xbb, 0x3c, 0x40, 0x91, 0x6b, 0x83, 0xbf, 0x39}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0x8000000", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: 134217728, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0xbb, 0x38}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0x40000000", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: 1073741824, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0xbb, 0x38}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0x40000008", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: 1073741832, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0xbb, 0x38}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0x3ffffff8", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: 1073741816, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0xbb, 0x38}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0x40000010", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: 1073741840, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0xbb, 0x38}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0x3ffffff0", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: 1073741808, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0xbb, 0x38}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0x7ffffff8", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: 2147483640, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0xbb, 0x38}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0x10000004", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: 268435460, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0xbb, 0x38}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0x100008", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: 1048584, dstReg: RegR11}, exp: []byte{0xbb, 0x0, 0x44, 0x91, 0x6b, 0x23, 0x80, 0x39}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=0xffff8", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcConst: 1048568, dstReg: RegR11}, exp: []byte{0xbb, 0xfc, 0x43, 0x91, 0x6b, 0xe3, 0xbf, 0x39}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R5,offset=RegR8", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR5, srcReg2: RegR8, dstReg: RegR11}, exp: []byte{0xab, 0x68, 0xa8, 0x38}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0xffffffffffffffff", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: -1, dstReg: RegR11}, exp: []byte{0xcb, 0xf3, 0x9f, 0x38}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0x0", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: 0, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x80, 0x39}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0x1", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: 1, dstReg: RegR11}, exp: []byte{0xcb, 0x7, 0x80, 0x39}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0x2", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: 2, dstReg: RegR11}, exp: []byte{0xcb, 0xb, 0x80, 0x39}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: -2, dstReg: RegR11}, exp: []byte{0xcb, 0xe3, 0x9f, 0x38}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0xf", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: 15, dstReg: RegR11}, exp: []byte{0xcb, 0x3f, 0x80, 0x39}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: -15, dstReg: RegR11}, exp: []byte{0xcb, 0x13, 0x9f, 0x38}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0x10", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: 16, dstReg: RegR11}, exp: []byte{0xcb, 0x43, 0x80, 0x39}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0xf", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: 15, dstReg: RegR11}, exp: []byte{0xcb, 0x3f, 0x80, 0x39}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0x11", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: 17, dstReg: RegR11}, exp: []byte{0xcb, 0x47, 0x80, 0x39}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: -128, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x98, 0x38}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0xffffffffffffff00", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: -256, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x90, 0x38}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0x50", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: 80, dstReg: RegR11}, exp: []byte{0xcb, 0x43, 0x81, 0x39}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: -128, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x98, 0x38}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0xff", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: 255, dstReg: RegR11}, exp: []byte{0xcb, 0xff, 0x83, 0x39}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0x1000", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: 4096, dstReg: RegR11}, exp: []byte{0xdb, 0x7, 0x40, 0x91, 0x6b, 0x3, 0x80, 0x39}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0x2000", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: 8192, dstReg: RegR11}, exp: []byte{0xdb, 0xb, 0x40, 0x91, 0x6b, 0x3, 0x80, 0x39}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0x7ff8", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: 32760, dstReg: RegR11}, exp: []byte{0xdb, 0x1f, 0x40, 0x91, 0x6b, 0xe3, 0xbf, 0x39}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0xfff0", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: 65520, dstReg: RegR11}, exp: []byte{0xdb, 0x3f, 0x40, 0x91, 0x6b, 0xc3, 0xbf, 0x39}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0xffe8", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: 65512, dstReg: RegR11}, exp: []byte{0xdb, 0x3f, 0x40, 0x91, 0x6b, 0xa3, 0xbf, 0x39}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0xffe0", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: 65504, dstReg: RegR11}, exp: []byte{0xdb, 0x3f, 0x40, 0x91, 0x6b, 0x83, 0xbf, 0x39}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0x8000000", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: 134217728, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0xbb, 0x38}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0x40000000", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: 1073741824, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0xbb, 0x38}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0x40000008", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: 1073741832, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0xbb, 0x38}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0x3ffffff8", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: 1073741816, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0xbb, 0x38}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0x40000010", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: 1073741840, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0xbb, 0x38}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0x3ffffff0", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: 1073741808, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0xbb, 0x38}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0x7ffffff8", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: 2147483640, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0xbb, 0x38}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0x10000004", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: 268435460, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0xbb, 0x38}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0x100008", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: 1048584, dstReg: RegR11}, exp: []byte{0xdb, 0x3, 0x44, 0x91, 0x6b, 0x23, 0x80, 0x39}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=0xffff8", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcConst: 1048568, dstReg: RegR11}, exp: []byte{0xdb, 0xff, 0x43, 0x91, 0x6b, 0xe3, 0xbf, 0x39}}, - {name: "LDRSBD/RegisterOffset/dst=R11,base=R30,offset=RegR8", n: &nodeImpl{instruction: LDRSBD, srcReg: RegR30, srcReg2: RegR8, dstReg: RegR11}, exp: []byte{0xcb, 0x6b, 0xa8, 0x38}}, - {name: "LDRSBW/RegisterOffset/dst=R11,base=R5,offset=0x0", n: &nodeImpl{instruction: LDRSBW, srcReg: RegR5, srcConst: 0, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0xc0, 0x39}}, - {name: "LDRSBW/RegisterOffset/dst=R11,base=R5,offset=0x1", n: &nodeImpl{instruction: LDRSBW, srcReg: RegR5, srcConst: 1, dstReg: RegR11}, exp: []byte{0xab, 0x4, 0xc0, 0x39}}, - {name: "LDRSBW/RegisterOffset/dst=R11,base=R5,offset=0x2", n: &nodeImpl{instruction: LDRSBW, srcReg: RegR5, srcConst: 2, dstReg: RegR11}, exp: []byte{0xab, 0x8, 0xc0, 0x39}}, - {name: "LDRSBW/RegisterOffset/dst=R11,base=R5,offsetReg=R12", n: &nodeImpl{instruction: LDRSBW, srcReg: RegR5, srcReg2: RegR12, dstReg: RegR11}, exp: []byte{0xab, 0x68, 0xec, 0x38}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0xffffffffffffffff", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: -1, dstReg: RegR11}, exp: []byte{0xab, 0xf0, 0x5f, 0x38}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0x0", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: 0, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x40, 0x39}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0x1", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: 1, dstReg: RegR11}, exp: []byte{0xab, 0x4, 0x40, 0x39}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0x2", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: 2, dstReg: RegR11}, exp: []byte{0xab, 0x8, 0x40, 0x39}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: -2, dstReg: RegR11}, exp: []byte{0xab, 0xe0, 0x5f, 0x38}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0xf", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: 15, dstReg: RegR11}, exp: []byte{0xab, 0x3c, 0x40, 0x39}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: -15, dstReg: RegR11}, exp: []byte{0xab, 0x10, 0x5f, 0x38}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0x10", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: 16, dstReg: RegR11}, exp: []byte{0xab, 0x40, 0x40, 0x39}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0xf", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: 15, dstReg: RegR11}, exp: []byte{0xab, 0x3c, 0x40, 0x39}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0x11", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: 17, dstReg: RegR11}, exp: []byte{0xab, 0x44, 0x40, 0x39}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0xffffffffffffff80", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: -128, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x58, 0x38}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0xffffffffffffff00", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: -256, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x50, 0x38}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0x50", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: 80, dstReg: RegR11}, exp: []byte{0xab, 0x40, 0x41, 0x39}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0xffffffffffffff80", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: -128, dstReg: RegR11}, exp: []byte{0xab, 0x0, 0x58, 0x38}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0xff", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: 255, dstReg: RegR11}, exp: []byte{0xab, 0xfc, 0x43, 0x39}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0x1000", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: 4096, dstReg: RegR11}, exp: []byte{0xbb, 0x4, 0x40, 0x91, 0x6b, 0x3, 0x40, 0x39}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0x2000", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: 8192, dstReg: RegR11}, exp: []byte{0xbb, 0x8, 0x40, 0x91, 0x6b, 0x3, 0x40, 0x39}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0x7ff8", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: 32760, dstReg: RegR11}, exp: []byte{0xbb, 0x1c, 0x40, 0x91, 0x6b, 0xe3, 0x7f, 0x39}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0xfff0", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: 65520, dstReg: RegR11}, exp: []byte{0xbb, 0x3c, 0x40, 0x91, 0x6b, 0xc3, 0x7f, 0x39}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0xffe8", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: 65512, dstReg: RegR11}, exp: []byte{0xbb, 0x3c, 0x40, 0x91, 0x6b, 0xa3, 0x7f, 0x39}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0xffe0", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: 65504, dstReg: RegR11}, exp: []byte{0xbb, 0x3c, 0x40, 0x91, 0x6b, 0x83, 0x7f, 0x39}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0x8000000", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: 134217728, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0x7b, 0x38}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0x40000000", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: 1073741824, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0x7b, 0x38}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0x40000008", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: 1073741832, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0x7b, 0x38}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0x3ffffff8", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: 1073741816, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0x7b, 0x38}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0x40000010", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: 1073741840, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0x7b, 0x38}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0x3ffffff0", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: 1073741808, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0x7b, 0x38}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0x7ffffff8", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: 2147483640, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0x7b, 0x38}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0x10000004", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: 268435460, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xab, 0x68, 0x7b, 0x38}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0x100008", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: 1048584, dstReg: RegR11}, exp: []byte{0xbb, 0x0, 0x44, 0x91, 0x6b, 0x23, 0x40, 0x39}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=0xffff8", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcConst: 1048568, dstReg: RegR11}, exp: []byte{0xbb, 0xfc, 0x43, 0x91, 0x6b, 0xe3, 0x7f, 0x39}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R5,offset=RegR8", n: &nodeImpl{instruction: LDRB, srcReg: RegR5, srcReg2: RegR8, dstReg: RegR11}, exp: []byte{0xab, 0x68, 0x68, 0x38}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0xffffffffffffffff", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: -1, dstReg: RegR11}, exp: []byte{0xcb, 0xf3, 0x5f, 0x38}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0x0", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: 0, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x40, 0x39}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0x1", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: 1, dstReg: RegR11}, exp: []byte{0xcb, 0x7, 0x40, 0x39}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0x2", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: 2, dstReg: RegR11}, exp: []byte{0xcb, 0xb, 0x40, 0x39}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: -2, dstReg: RegR11}, exp: []byte{0xcb, 0xe3, 0x5f, 0x38}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0xf", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: 15, dstReg: RegR11}, exp: []byte{0xcb, 0x3f, 0x40, 0x39}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: -15, dstReg: RegR11}, exp: []byte{0xcb, 0x13, 0x5f, 0x38}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0x10", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: 16, dstReg: RegR11}, exp: []byte{0xcb, 0x43, 0x40, 0x39}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0xf", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: 15, dstReg: RegR11}, exp: []byte{0xcb, 0x3f, 0x40, 0x39}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0x11", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: 17, dstReg: RegR11}, exp: []byte{0xcb, 0x47, 0x40, 0x39}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: -128, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x58, 0x38}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0xffffffffffffff00", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: -256, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x50, 0x38}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0x50", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: 80, dstReg: RegR11}, exp: []byte{0xcb, 0x43, 0x41, 0x39}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: -128, dstReg: RegR11}, exp: []byte{0xcb, 0x3, 0x58, 0x38}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0xff", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: 255, dstReg: RegR11}, exp: []byte{0xcb, 0xff, 0x43, 0x39}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0x1000", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: 4096, dstReg: RegR11}, exp: []byte{0xdb, 0x7, 0x40, 0x91, 0x6b, 0x3, 0x40, 0x39}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0x2000", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: 8192, dstReg: RegR11}, exp: []byte{0xdb, 0xb, 0x40, 0x91, 0x6b, 0x3, 0x40, 0x39}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0x7ff8", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: 32760, dstReg: RegR11}, exp: []byte{0xdb, 0x1f, 0x40, 0x91, 0x6b, 0xe3, 0x7f, 0x39}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0xfff0", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: 65520, dstReg: RegR11}, exp: []byte{0xdb, 0x3f, 0x40, 0x91, 0x6b, 0xc3, 0x7f, 0x39}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0xffe8", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: 65512, dstReg: RegR11}, exp: []byte{0xdb, 0x3f, 0x40, 0x91, 0x6b, 0xa3, 0x7f, 0x39}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0xffe0", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: 65504, dstReg: RegR11}, exp: []byte{0xdb, 0x3f, 0x40, 0x91, 0x6b, 0x83, 0x7f, 0x39}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0x8000000", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: 134217728, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0x7b, 0x38}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0x40000000", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: 1073741824, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0x7b, 0x38}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0x40000008", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: 1073741832, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0x7b, 0x38}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0x3ffffff8", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: 1073741816, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0x7b, 0x38}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0x40000010", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: 1073741840, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0x7b, 0x38}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0x3ffffff0", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: 1073741808, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0x7b, 0x38}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0x7ffffff8", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: 2147483640, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0x7b, 0x38}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0x10000004", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: 268435460, dstReg: RegR11}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xcb, 0x6b, 0x7b, 0x38}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0x100008", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: 1048584, dstReg: RegR11}, exp: []byte{0xdb, 0x3, 0x44, 0x91, 0x6b, 0x23, 0x40, 0x39}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=0xffff8", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcConst: 1048568, dstReg: RegR11}, exp: []byte{0xdb, 0xff, 0x43, 0x91, 0x6b, 0xe3, 0x7f, 0x39}}, - {name: "LDRB/RegisterOffset/dst=R11,base=R30,offset=RegR8", n: &nodeImpl{instruction: LDRB, srcReg: RegR30, srcReg2: RegR8, dstReg: RegR11}, exp: []byte{0xcb, 0x6b, 0x68, 0x38}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0xffffffffffffffff", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: -1, dstReg: RegV30}, exp: []byte{0xbe, 0xf0, 0x5f, 0xfc}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0x0", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: 0, dstReg: RegV30}, exp: []byte{0xbe, 0x0, 0x40, 0xfd}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0x1", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: 1, dstReg: RegV30}, exp: []byte{0xbe, 0x10, 0x40, 0xfc}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0x2", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: 2, dstReg: RegV30}, exp: []byte{0xbe, 0x20, 0x40, 0xfc}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: -2, dstReg: RegV30}, exp: []byte{0xbe, 0xe0, 0x5f, 0xfc}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0xf", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: 15, dstReg: RegV30}, exp: []byte{0xbe, 0xf0, 0x40, 0xfc}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: -15, dstReg: RegV30}, exp: []byte{0xbe, 0x10, 0x5f, 0xfc}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0x10", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: 16, dstReg: RegV30}, exp: []byte{0xbe, 0x8, 0x40, 0xfd}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0xf", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: 15, dstReg: RegV30}, exp: []byte{0xbe, 0xf0, 0x40, 0xfc}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0x11", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: 17, dstReg: RegV30}, exp: []byte{0xbe, 0x10, 0x41, 0xfc}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: -128, dstReg: RegV30}, exp: []byte{0xbe, 0x0, 0x58, 0xfc}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0xffffffffffffff00", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: -256, dstReg: RegV30}, exp: []byte{0xbe, 0x0, 0x50, 0xfc}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0x50", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: 80, dstReg: RegV30}, exp: []byte{0xbe, 0x28, 0x40, 0xfd}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: -128, dstReg: RegV30}, exp: []byte{0xbe, 0x0, 0x58, 0xfc}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0xff", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: 255, dstReg: RegV30}, exp: []byte{0xbe, 0xf0, 0x4f, 0xfc}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0x1000", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: 4096, dstReg: RegV30}, exp: []byte{0xbe, 0x0, 0x48, 0xfd}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0x2000", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: 8192, dstReg: RegV30}, exp: []byte{0xbe, 0x0, 0x50, 0xfd}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0x7ff8", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: 32760, dstReg: RegV30}, exp: []byte{0xbe, 0xfc, 0x7f, 0xfd}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0xfff0", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: 65520, dstReg: RegV30}, exp: []byte{0xbb, 0x20, 0x40, 0x91, 0x7e, 0xfb, 0x7f, 0xfd}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0xffe8", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: 65512, dstReg: RegV30}, exp: []byte{0xbb, 0x20, 0x40, 0x91, 0x7e, 0xf7, 0x7f, 0xfd}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0xffe0", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: 65504, dstReg: RegV30}, exp: []byte{0xbb, 0x20, 0x40, 0x91, 0x7e, 0xf3, 0x7f, 0xfd}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0x8000000", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: 134217728, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xbe, 0x68, 0x7b, 0xfc}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0x40000000", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: 1073741824, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xbe, 0x68, 0x7b, 0xfc}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0x40000008", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: 1073741832, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xbe, 0x68, 0x7b, 0xfc}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0x3ffffff8", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: 1073741816, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xbe, 0x68, 0x7b, 0xfc}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0x40000010", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: 1073741840, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xbe, 0x68, 0x7b, 0xfc}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0x3ffffff0", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: 1073741808, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xbe, 0x68, 0x7b, 0xfc}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0x7ffffff8", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: 2147483640, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xbe, 0x68, 0x7b, 0xfc}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0x10000004", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: 268435460, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xbe, 0x68, 0x7b, 0xfc}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0x100008", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: 1048584, dstReg: RegV30}, exp: []byte{0xbb, 0x0, 0x44, 0x91, 0x7e, 0x7, 0x40, 0xfd}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=0xffff8", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcConst: 1048568, dstReg: RegV30}, exp: []byte{0xbb, 0xe0, 0x43, 0x91, 0x7e, 0xff, 0x7f, 0xfd}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R5,offset=RegR8", n: &nodeImpl{instruction: FLDRD, srcReg: RegR5, srcReg2: RegR8, dstReg: RegV30}, exp: []byte{0xbe, 0x68, 0x68, 0xfc}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0xffffffffffffffff", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: -1, dstReg: RegV30}, exp: []byte{0xde, 0xf3, 0x5f, 0xfc}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0x0", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: 0, dstReg: RegV30}, exp: []byte{0xde, 0x3, 0x40, 0xfd}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0x1", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: 1, dstReg: RegV30}, exp: []byte{0xde, 0x13, 0x40, 0xfc}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0x2", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: 2, dstReg: RegV30}, exp: []byte{0xde, 0x23, 0x40, 0xfc}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: -2, dstReg: RegV30}, exp: []byte{0xde, 0xe3, 0x5f, 0xfc}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0xf", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: 15, dstReg: RegV30}, exp: []byte{0xde, 0xf3, 0x40, 0xfc}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: -15, dstReg: RegV30}, exp: []byte{0xde, 0x13, 0x5f, 0xfc}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0x10", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: 16, dstReg: RegV30}, exp: []byte{0xde, 0xb, 0x40, 0xfd}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0xf", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: 15, dstReg: RegV30}, exp: []byte{0xde, 0xf3, 0x40, 0xfc}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0x11", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: 17, dstReg: RegV30}, exp: []byte{0xde, 0x13, 0x41, 0xfc}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: -128, dstReg: RegV30}, exp: []byte{0xde, 0x3, 0x58, 0xfc}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0xffffffffffffff00", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: -256, dstReg: RegV30}, exp: []byte{0xde, 0x3, 0x50, 0xfc}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0x50", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: 80, dstReg: RegV30}, exp: []byte{0xde, 0x2b, 0x40, 0xfd}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: -128, dstReg: RegV30}, exp: []byte{0xde, 0x3, 0x58, 0xfc}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0xff", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: 255, dstReg: RegV30}, exp: []byte{0xde, 0xf3, 0x4f, 0xfc}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0x1000", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: 4096, dstReg: RegV30}, exp: []byte{0xde, 0x3, 0x48, 0xfd}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0x2000", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: 8192, dstReg: RegV30}, exp: []byte{0xde, 0x3, 0x50, 0xfd}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0x7ff8", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: 32760, dstReg: RegV30}, exp: []byte{0xde, 0xff, 0x7f, 0xfd}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0xfff0", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: 65520, dstReg: RegV30}, exp: []byte{0xdb, 0x23, 0x40, 0x91, 0x7e, 0xfb, 0x7f, 0xfd}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0xffe8", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: 65512, dstReg: RegV30}, exp: []byte{0xdb, 0x23, 0x40, 0x91, 0x7e, 0xf7, 0x7f, 0xfd}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0xffe0", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: 65504, dstReg: RegV30}, exp: []byte{0xdb, 0x23, 0x40, 0x91, 0x7e, 0xf3, 0x7f, 0xfd}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0x8000000", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: 134217728, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x7b, 0xfc}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0x40000000", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: 1073741824, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x7b, 0xfc}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0x40000008", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: 1073741832, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x7b, 0xfc}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0x3ffffff8", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: 1073741816, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x7b, 0xfc}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0x40000010", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: 1073741840, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x7b, 0xfc}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0x3ffffff0", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: 1073741808, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x7b, 0xfc}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0x7ffffff8", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: 2147483640, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x7b, 0xfc}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0x10000004", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: 268435460, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x7b, 0xfc}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0x100008", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: 1048584, dstReg: RegV30}, exp: []byte{0xdb, 0x3, 0x44, 0x91, 0x7e, 0x7, 0x40, 0xfd}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=0xffff8", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcConst: 1048568, dstReg: RegV30}, exp: []byte{0xdb, 0xe3, 0x43, 0x91, 0x7e, 0xff, 0x7f, 0xfd}}, - {name: "FLDRD/RegisterOffset/dst=V30,base=R30,offset=RegR8", n: &nodeImpl{instruction: FLDRD, srcReg: RegR30, srcReg2: RegR8, dstReg: RegV30}, exp: []byte{0xde, 0x6b, 0x68, 0xfc}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0xffffffffffffffff", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: -1, dstReg: RegV30}, exp: []byte{0xbe, 0xf0, 0x5f, 0xbc}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0x0", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: 0, dstReg: RegV30}, exp: []byte{0xbe, 0x0, 0x40, 0xbd}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0x1", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: 1, dstReg: RegV30}, exp: []byte{0xbe, 0x10, 0x40, 0xbc}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0x2", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: 2, dstReg: RegV30}, exp: []byte{0xbe, 0x20, 0x40, 0xbc}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: -2, dstReg: RegV30}, exp: []byte{0xbe, 0xe0, 0x5f, 0xbc}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0xf", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: 15, dstReg: RegV30}, exp: []byte{0xbe, 0xf0, 0x40, 0xbc}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: -15, dstReg: RegV30}, exp: []byte{0xbe, 0x10, 0x5f, 0xbc}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0x10", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: 16, dstReg: RegV30}, exp: []byte{0xbe, 0x10, 0x40, 0xbd}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0xf", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: 15, dstReg: RegV30}, exp: []byte{0xbe, 0xf0, 0x40, 0xbc}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0x11", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: 17, dstReg: RegV30}, exp: []byte{0xbe, 0x10, 0x41, 0xbc}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: -128, dstReg: RegV30}, exp: []byte{0xbe, 0x0, 0x58, 0xbc}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0xffffffffffffff00", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: -256, dstReg: RegV30}, exp: []byte{0xbe, 0x0, 0x50, 0xbc}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0x50", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: 80, dstReg: RegV30}, exp: []byte{0xbe, 0x50, 0x40, 0xbd}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: -128, dstReg: RegV30}, exp: []byte{0xbe, 0x0, 0x58, 0xbc}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0xff", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: 255, dstReg: RegV30}, exp: []byte{0xbe, 0xf0, 0x4f, 0xbc}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0x1000", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: 4096, dstReg: RegV30}, exp: []byte{0xbe, 0x0, 0x50, 0xbd}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0x2000", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: 8192, dstReg: RegV30}, exp: []byte{0xbe, 0x0, 0x60, 0xbd}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0x7ff8", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: 32760, dstReg: RegV30}, exp: []byte{0xbb, 0x10, 0x40, 0x91, 0x7e, 0xfb, 0x7f, 0xbd}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0xfff0", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: 65520, dstReg: RegV30}, exp: []byte{0xbb, 0x30, 0x40, 0x91, 0x7e, 0xf3, 0x7f, 0xbd}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0xffe8", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: 65512, dstReg: RegV30}, exp: []byte{0xbb, 0x30, 0x40, 0x91, 0x7e, 0xeb, 0x7f, 0xbd}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0xffe0", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: 65504, dstReg: RegV30}, exp: []byte{0xbb, 0x30, 0x40, 0x91, 0x7e, 0xe3, 0x7f, 0xbd}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0x8000000", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: 134217728, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xbe, 0x68, 0x7b, 0xbc}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0x40000000", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: 1073741824, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xbe, 0x68, 0x7b, 0xbc}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0x40000008", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: 1073741832, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xbe, 0x68, 0x7b, 0xbc}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0x3ffffff8", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: 1073741816, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xbe, 0x68, 0x7b, 0xbc}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0x40000010", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: 1073741840, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xbe, 0x68, 0x7b, 0xbc}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0x3ffffff0", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: 1073741808, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xbe, 0x68, 0x7b, 0xbc}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0x7ffffff8", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: 2147483640, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xbe, 0x68, 0x7b, 0xbc}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0x10000004", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: 268435460, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xbe, 0x68, 0x7b, 0xbc}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0x100008", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: 1048584, dstReg: RegV30}, exp: []byte{0xbb, 0x0, 0x44, 0x91, 0x7e, 0xb, 0x40, 0xbd}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=0xffff8", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcConst: 1048568, dstReg: RegV30}, exp: []byte{0xbb, 0xf0, 0x43, 0x91, 0x7e, 0xfb, 0x7f, 0xbd}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R5,offset=RegR8", n: &nodeImpl{instruction: FLDRS, srcReg: RegR5, srcReg2: RegR8, dstReg: RegV30}, exp: []byte{0xbe, 0x68, 0x68, 0xbc}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0xffffffffffffffff", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: -1, dstReg: RegV30}, exp: []byte{0xde, 0xf3, 0x5f, 0xbc}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0x0", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: 0, dstReg: RegV30}, exp: []byte{0xde, 0x3, 0x40, 0xbd}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0x1", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: 1, dstReg: RegV30}, exp: []byte{0xde, 0x13, 0x40, 0xbc}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0x2", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: 2, dstReg: RegV30}, exp: []byte{0xde, 0x23, 0x40, 0xbc}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: -2, dstReg: RegV30}, exp: []byte{0xde, 0xe3, 0x5f, 0xbc}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0xf", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: 15, dstReg: RegV30}, exp: []byte{0xde, 0xf3, 0x40, 0xbc}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: -15, dstReg: RegV30}, exp: []byte{0xde, 0x13, 0x5f, 0xbc}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0x10", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: 16, dstReg: RegV30}, exp: []byte{0xde, 0x13, 0x40, 0xbd}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0xf", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: 15, dstReg: RegV30}, exp: []byte{0xde, 0xf3, 0x40, 0xbc}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0x11", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: 17, dstReg: RegV30}, exp: []byte{0xde, 0x13, 0x41, 0xbc}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: -128, dstReg: RegV30}, exp: []byte{0xde, 0x3, 0x58, 0xbc}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0xffffffffffffff00", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: -256, dstReg: RegV30}, exp: []byte{0xde, 0x3, 0x50, 0xbc}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0x50", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: 80, dstReg: RegV30}, exp: []byte{0xde, 0x53, 0x40, 0xbd}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: -128, dstReg: RegV30}, exp: []byte{0xde, 0x3, 0x58, 0xbc}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0xff", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: 255, dstReg: RegV30}, exp: []byte{0xde, 0xf3, 0x4f, 0xbc}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0x1000", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: 4096, dstReg: RegV30}, exp: []byte{0xde, 0x3, 0x50, 0xbd}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0x2000", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: 8192, dstReg: RegV30}, exp: []byte{0xde, 0x3, 0x60, 0xbd}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0x7ff8", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: 32760, dstReg: RegV30}, exp: []byte{0xdb, 0x13, 0x40, 0x91, 0x7e, 0xfb, 0x7f, 0xbd}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0xfff0", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: 65520, dstReg: RegV30}, exp: []byte{0xdb, 0x33, 0x40, 0x91, 0x7e, 0xf3, 0x7f, 0xbd}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0xffe8", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: 65512, dstReg: RegV30}, exp: []byte{0xdb, 0x33, 0x40, 0x91, 0x7e, 0xeb, 0x7f, 0xbd}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0xffe0", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: 65504, dstReg: RegV30}, exp: []byte{0xdb, 0x33, 0x40, 0x91, 0x7e, 0xe3, 0x7f, 0xbd}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0x8000000", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: 134217728, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x7b, 0xbc}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0x40000000", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: 1073741824, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x7b, 0xbc}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0x40000008", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: 1073741832, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x7b, 0xbc}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0x3ffffff8", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: 1073741816, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x7b, 0xbc}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0x40000010", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: 1073741840, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x7b, 0xbc}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0x3ffffff0", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: 1073741808, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x7b, 0xbc}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0x7ffffff8", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: 2147483640, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x7b, 0xbc}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0x10000004", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: 268435460, dstReg: RegV30}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x7b, 0xbc}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0x100008", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: 1048584, dstReg: RegV30}, exp: []byte{0xdb, 0x3, 0x44, 0x91, 0x7e, 0xb, 0x40, 0xbd}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=0xffff8", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcConst: 1048568, dstReg: RegV30}, exp: []byte{0xdb, 0xf3, 0x43, 0x91, 0x7e, 0xfb, 0x7f, 0xbd}}, - {name: "FLDRS/RegisterOffset/dst=V30,base=R30,offset=RegR8", n: &nodeImpl{instruction: FLDRS, srcReg: RegR30, srcReg2: RegR8, dstReg: RegV30}, exp: []byte{0xde, 0x6b, 0x68, 0xbc}}, - {name: "ldar x11, [x5]", n: &nodeImpl{instruction: LDARD, srcReg: RegR5, dstReg: RegR11}, exp: []byte{0xab, 0xfc, 0xdf, 0xc8}}, - {name: "ldar x11, [x30]", n: &nodeImpl{instruction: LDARD, srcReg: RegR30, dstReg: RegR11}, exp: []byte{0xcb, 0xff, 0xdf, 0xc8}}, - {name: "ldar w11, [x5]", n: &nodeImpl{instruction: LDARW, srcReg: RegR5, dstReg: RegR11}, exp: []byte{0xab, 0xfc, 0xdf, 0x88}}, - {name: "ldar w11, [x30]", n: &nodeImpl{instruction: LDARW, srcReg: RegR30, dstReg: RegR11}, exp: []byte{0xcb, 0xff, 0xdf, 0x88}}, - {name: "ldarh w11, [x5]", n: &nodeImpl{instruction: LDARH, srcReg: RegR5, dstReg: RegR11}, exp: []byte{0xab, 0xfc, 0xdf, 0x48}}, - {name: "ldarh w11, [x30]", n: &nodeImpl{instruction: LDARH, srcReg: RegR30, dstReg: RegR11}, exp: []byte{0xcb, 0xff, 0xdf, 0x48}}, - {name: "ldarb w11, [x5]", n: &nodeImpl{instruction: LDARB, srcReg: RegR5, dstReg: RegR11}, exp: []byte{0xab, 0xfc, 0xdf, 0x8}}, - {name: "ldarb w11, [x30]", n: &nodeImpl{instruction: LDARB, srcReg: RegR30, dstReg: RegR11}, exp: []byte{0xcb, 0xff, 0xdf, 0x8}}, - } - - for _, tc := range tests { - t.Run(tc.name, func(t *testing.T) { - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - a := NewAssembler(RegR27) - buf := code.NextCodeSection() - err := a.encodeMemoryToRegister(buf, tc.n) - require.NoError(t, err) - - err = a.Assemble(buf) - require.NoError(t, err) - - actual := buf.Bytes() - require.Equal(t, tc.exp, actual, hex.EncodeToString(actual)) - }) - } -} - -func TestAssemblerImpl_encodeReadInstructionAddress(t *testing.T) { - t.Run("ok", func(t *testing.T) { - tests := []struct { - name string - expADRInstructionBytes []byte - numDummyInstructions int - }{ - { - name: "< 8-bit offset", - numDummyInstructions: 1, - expADRInstructionBytes: []byte{0x77, 0x0, 0x0, 0x10}, - }, - { - name: "> 8-bit offset", - numDummyInstructions: 5000, - expADRInstructionBytes: []byte{0x57, 0x71, 0x2, 0x10}, - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - const targetBeforeInstruction, dstReg = RET, RegR23 - a := NewAssembler(asm.NilRegister) - - a.CompileReadInstructionAddress(dstReg, targetBeforeInstruction) - adrInst := a.current - for i := 0; i < tc.numDummyInstructions; i++ { - a.CompileJumpToRegister(B, RegR5) - } - a.CompileJumpToRegister(targetBeforeInstruction, RegR25) - a.CompileConstToRegister(MOVD, 0x3e8, RegR10) // Target. - target := a.current - - buf := code.NextCodeSection() - err := a.Assemble(buf) - require.NoError(t, err) - // The binary should start with ADR instruction. - actual := buf.Bytes() - require.Equal(t, tc.expADRInstructionBytes, actual[:4], hex.EncodeToString(actual)) - // Then, follow the dummy B instructions. - pos := 4 - for i := 0; i < tc.numDummyInstructions; i++ { - require.Equal(t, - // A0 00 1F D6 br x5 - []byte{0xa0, 0x0, 0x1f, 0xd6}, - actual[pos:pos+4], hex.EncodeToString(actual)) - pos += 4 - } - // And targetBeforeInstruction follows: "20 03 5F D6 ret x25" - require.Equal(t, []byte{0x20, 0x03, 0x5F, 0xd6}, - actual[pos:pos+4], hex.EncodeToString(actual)) - - // After that, we end with the target instruction "movz x10, #0x3e8" - pos += 4 - require.Equal(t, []byte{0xa, 0x7d, 0x80, 0xd2}, - actual[pos:pos+4], hex.EncodeToString(actual)) - - require.Equal(t, uint64(4+tc.numDummyInstructions*4+4), - target.offsetInBinary-adrInst.offsetInBinary) - }) - } - }) - - t.Run("not found", func(t *testing.T) { - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - a := NewAssembler(asm.NilRegister) - a.CompileReadInstructionAddress(RegR27, NOP) - a.CompileConstToRegister(MOVD, 1000, RegR10) - - buf := code.NextCodeSection() - err := a.Assemble(buf) - require.EqualError(t, err, "BUG: target instruction NOP not found for ADR") - }) - t.Run("offset too large", func(t *testing.T) { - for _, offset := range []int64{ - 1 << 20, - -(1 << 20) - 1, - math.MaxInt64, math.MinInt64, - } { - u64 := uint64(offset) - t.Run(fmt.Sprintf("offset=%#b", u64), func(t *testing.T) { - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - a := NewAssembler(asm.NilRegister) - a.CompileReadInstructionAddress(RegR27, RET) - a.CompileJumpToRegister(RET, RegR25) - a.CompileConstToRegister(MOVD, 1000, RegR10) - - buf := code.NextCodeSection() - - for n := a.root; n != nil; n = n.next { - n.offsetInBinary = uint64(buf.Len()) - - err := a.encodeNode(buf, n) - require.NoError(t, err) - } - - targetNode := a.current - targetNode.offsetInBinary = u64 - - n := a.adrInstructionNodes[0] - err := a.finalizeADRInstructionNode(nil, n) - require.EqualError(t, err, fmt.Sprintf("BUG: too large offset for ADR: %#x", u64)) - }) - } - }) -} diff --git a/internal/asm/arm64/impl_5_test.go b/internal/asm/arm64/impl_5_test.go deleted file mode 100644 index 28f511903b..0000000000 --- a/internal/asm/arm64/impl_5_test.go +++ /dev/null @@ -1,844 +0,0 @@ -package arm64 - -import ( - "testing" - - "github.com/tetratelabs/wazero/internal/asm" - "github.com/tetratelabs/wazero/internal/testing/require" -) - -func TestAssemblerImpl_EncodeRegisterToMemory(t *testing.T) { - t.Run("error", func(t *testing.T) { - tests := []struct { - n *nodeImpl - expErr string - }{ - { - n: &nodeImpl{instruction: ADR, types: operandTypesRegisterToMemory}, - expErr: "ADR is unsupported for RegisterToMemory type", - }, - } - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - for _, tt := range tests { - tc := tt - a := NewAssembler(asm.NilRegister) - buf := code.NextCodeSection() - err := a.encodeRegisterToMemory(buf, tc.n) - require.EqualError(t, err, tc.expErr) - } - }) - - tests := []struct { - name string - n *nodeImpl - exp []byte - }{ - {name: "STRD/ConstOffset/src=R0,base=R0,offset=0xffffffffffffffff", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: -1}, exp: []byte{0x0, 0xf0, 0x1f, 0xf8}}, - {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x0", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 0}, exp: []byte{0x0, 0x0, 0x0, 0xf9}}, - {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x1", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 1}, exp: []byte{0x0, 0x10, 0x0, 0xf8}}, - {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x2", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 2}, exp: []byte{0x0, 0x20, 0x0, 0xf8}}, - {name: "STRD/ConstOffset/src=R0,base=R0,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: -2}, exp: []byte{0x0, 0xe0, 0x1f, 0xf8}}, - {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x4", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 4}, exp: []byte{0x0, 0x40, 0x0, 0xf8}}, - {name: "STRD/ConstOffset/src=R0,base=R0,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: -4}, exp: []byte{0x0, 0xc0, 0x1f, 0xf8}}, - {name: "STRD/ConstOffset/src=R0,base=R0,offset=0xf", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 15}, exp: []byte{0x0, 0xf0, 0x0, 0xf8}}, - {name: "STRD/ConstOffset/src=R0,base=R0,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: -15}, exp: []byte{0x0, 0x10, 0x1f, 0xf8}}, - {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x10", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 16}, exp: []byte{0x0, 0x8, 0x0, 0xf9}}, - {name: "STRD/ConstOffset/src=R0,base=R0,offset=0xf", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 15}, exp: []byte{0x0, 0xf0, 0x0, 0xf8}}, - {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x11", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 17}, exp: []byte{0x0, 0x10, 0x1, 0xf8}}, - {name: "STRD/ConstOffset/src=R0,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: -128}, exp: []byte{0x0, 0x0, 0x18, 0xf8}}, - {name: "STRD/ConstOffset/src=R0,base=R0,offset=0xffffffffffffff00", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: -256}, exp: []byte{0x0, 0x0, 0x10, 0xf8}}, - {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x50", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 80}, exp: []byte{0x0, 0x28, 0x0, 0xf9}}, - {name: "STRD/ConstOffset/src=R0,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: -128}, exp: []byte{0x0, 0x0, 0x18, 0xf8}}, - {name: "STRD/ConstOffset/src=R0,base=R0,offset=0xff", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 255}, exp: []byte{0x0, 0xf0, 0xf, 0xf8}}, - {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x1000", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 4096}, exp: []byte{0x0, 0x0, 0x8, 0xf9}}, - {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x2000", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 8192}, exp: []byte{0x0, 0x0, 0x10, 0xf9}}, - {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x7ff8", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 32760}, exp: []byte{0x0, 0xfc, 0x3f, 0xf9}}, - {name: "STRD/ConstOffset/src=R0,base=R0,offset=0xfff0", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 65520}, exp: []byte{0x1b, 0x20, 0x40, 0x91, 0x60, 0xfb, 0x3f, 0xf9}}, - {name: "STRD/ConstOffset/src=R0,base=R0,offset=0xffe8", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 65512}, exp: []byte{0x1b, 0x20, 0x40, 0x91, 0x60, 0xf7, 0x3f, 0xf9}}, - {name: "STRD/ConstOffset/src=R0,base=R0,offset=0xffe0", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 65504}, exp: []byte{0x1b, 0x20, 0x40, 0x91, 0x60, 0xf3, 0x3f, 0xf9}}, - {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x8000000", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xf8}}, - {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x40000000", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xf8}}, - {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x40000008", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xf8}}, - {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x3ffffff8", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xf8}}, - {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x40000010", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xf8}}, - {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x3ffffff0", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xf8}}, - {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x7ffffff8", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xf8}}, - {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x10000004", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xf8}}, - {name: "STRD/RegisterOffset/src=R0,base=R0,offset=RegR8", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstReg2: RegR8}, exp: []byte{0x0, 0x68, 0x28, 0xf8}}, - {name: "STRD/ConstOffset/src=R0,base=R30,offset=0xffffffffffffffff", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: -1}, exp: []byte{0xc0, 0xf3, 0x1f, 0xf8}}, - {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x0", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 0}, exp: []byte{0xc0, 0x3, 0x0, 0xf9}}, - {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x1", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 1}, exp: []byte{0xc0, 0x13, 0x0, 0xf8}}, - {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x2", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 2}, exp: []byte{0xc0, 0x23, 0x0, 0xf8}}, - {name: "STRD/ConstOffset/src=R0,base=R30,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: -2}, exp: []byte{0xc0, 0xe3, 0x1f, 0xf8}}, - {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x4", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 4}, exp: []byte{0xc0, 0x43, 0x0, 0xf8}}, - {name: "STRD/ConstOffset/src=R0,base=R30,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: -4}, exp: []byte{0xc0, 0xc3, 0x1f, 0xf8}}, - {name: "STRD/ConstOffset/src=R0,base=R30,offset=0xf", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 15}, exp: []byte{0xc0, 0xf3, 0x0, 0xf8}}, - {name: "STRD/ConstOffset/src=R0,base=R30,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: -15}, exp: []byte{0xc0, 0x13, 0x1f, 0xf8}}, - {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x10", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 16}, exp: []byte{0xc0, 0xb, 0x0, 0xf9}}, - {name: "STRD/ConstOffset/src=R0,base=R30,offset=0xf", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 15}, exp: []byte{0xc0, 0xf3, 0x0, 0xf8}}, - {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x11", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 17}, exp: []byte{0xc0, 0x13, 0x1, 0xf8}}, - {name: "STRD/ConstOffset/src=R0,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: -128}, exp: []byte{0xc0, 0x3, 0x18, 0xf8}}, - {name: "STRD/ConstOffset/src=R0,base=R30,offset=0xffffffffffffff00", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: -256}, exp: []byte{0xc0, 0x3, 0x10, 0xf8}}, - {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x50", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 80}, exp: []byte{0xc0, 0x2b, 0x0, 0xf9}}, - {name: "STRD/ConstOffset/src=R0,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: -128}, exp: []byte{0xc0, 0x3, 0x18, 0xf8}}, - {name: "STRD/ConstOffset/src=R0,base=R30,offset=0xff", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 255}, exp: []byte{0xc0, 0xf3, 0xf, 0xf8}}, - {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x1000", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 4096}, exp: []byte{0xc0, 0x3, 0x8, 0xf9}}, - {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x2000", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 8192}, exp: []byte{0xc0, 0x3, 0x10, 0xf9}}, - {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x7ff8", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 32760}, exp: []byte{0xc0, 0xff, 0x3f, 0xf9}}, - {name: "STRD/ConstOffset/src=R0,base=R30,offset=0xfff0", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 65520}, exp: []byte{0xdb, 0x23, 0x40, 0x91, 0x60, 0xfb, 0x3f, 0xf9}}, - {name: "STRD/ConstOffset/src=R0,base=R30,offset=0xffe8", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 65512}, exp: []byte{0xdb, 0x23, 0x40, 0x91, 0x60, 0xf7, 0x3f, 0xf9}}, - {name: "STRD/ConstOffset/src=R0,base=R30,offset=0xffe0", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 65504}, exp: []byte{0xdb, 0x23, 0x40, 0x91, 0x60, 0xf3, 0x3f, 0xf9}}, - {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x8000000", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xf8}}, - {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x40000000", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xf8}}, - {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x40000008", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xf8}}, - {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x3ffffff8", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xf8}}, - {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x40000010", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xf8}}, - {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x3ffffff0", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xf8}}, - {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x7ffffff8", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xf8}}, - {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x10000004", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xf8}}, - {name: "STRD/RegisterOffset/src=R0,base=R30,offset=RegR8", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstReg2: RegR8}, exp: []byte{0xc0, 0x6b, 0x28, 0xf8}}, - {name: "STRD/ConstOffset/src=R30,base=R0,offset=0xffffffffffffffff", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: -1}, exp: []byte{0x1e, 0xf0, 0x1f, 0xf8}}, - {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x0", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 0}, exp: []byte{0x1e, 0x0, 0x0, 0xf9}}, - {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x1", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 1}, exp: []byte{0x1e, 0x10, 0x0, 0xf8}}, - {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x2", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 2}, exp: []byte{0x1e, 0x20, 0x0, 0xf8}}, - {name: "STRD/ConstOffset/src=R30,base=R0,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: -2}, exp: []byte{0x1e, 0xe0, 0x1f, 0xf8}}, - {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x4", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 4}, exp: []byte{0x1e, 0x40, 0x0, 0xf8}}, - {name: "STRD/ConstOffset/src=R30,base=R0,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: -4}, exp: []byte{0x1e, 0xc0, 0x1f, 0xf8}}, - {name: "STRD/ConstOffset/src=R30,base=R0,offset=0xf", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 15}, exp: []byte{0x1e, 0xf0, 0x0, 0xf8}}, - {name: "STRD/ConstOffset/src=R30,base=R0,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: -15}, exp: []byte{0x1e, 0x10, 0x1f, 0xf8}}, - {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x10", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 16}, exp: []byte{0x1e, 0x8, 0x0, 0xf9}}, - {name: "STRD/ConstOffset/src=R30,base=R0,offset=0xf", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 15}, exp: []byte{0x1e, 0xf0, 0x0, 0xf8}}, - {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x11", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 17}, exp: []byte{0x1e, 0x10, 0x1, 0xf8}}, - {name: "STRD/ConstOffset/src=R30,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: -128}, exp: []byte{0x1e, 0x0, 0x18, 0xf8}}, - {name: "STRD/ConstOffset/src=R30,base=R0,offset=0xffffffffffffff00", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: -256}, exp: []byte{0x1e, 0x0, 0x10, 0xf8}}, - {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x50", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 80}, exp: []byte{0x1e, 0x28, 0x0, 0xf9}}, - {name: "STRD/ConstOffset/src=R30,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: -128}, exp: []byte{0x1e, 0x0, 0x18, 0xf8}}, - {name: "STRD/ConstOffset/src=R30,base=R0,offset=0xff", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 255}, exp: []byte{0x1e, 0xf0, 0xf, 0xf8}}, - {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x1000", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 4096}, exp: []byte{0x1e, 0x0, 0x8, 0xf9}}, - {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x2000", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 8192}, exp: []byte{0x1e, 0x0, 0x10, 0xf9}}, - {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x7ff8", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 32760}, exp: []byte{0x1e, 0xfc, 0x3f, 0xf9}}, - {name: "STRD/ConstOffset/src=R30,base=R0,offset=0xfff0", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 65520}, exp: []byte{0x1b, 0x20, 0x40, 0x91, 0x7e, 0xfb, 0x3f, 0xf9}}, - {name: "STRD/ConstOffset/src=R30,base=R0,offset=0xffe8", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 65512}, exp: []byte{0x1b, 0x20, 0x40, 0x91, 0x7e, 0xf7, 0x3f, 0xf9}}, - {name: "STRD/ConstOffset/src=R30,base=R0,offset=0xffe0", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 65504}, exp: []byte{0x1b, 0x20, 0x40, 0x91, 0x7e, 0xf3, 0x3f, 0xf9}}, - {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x8000000", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xf8}}, - {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x40000000", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xf8}}, - {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x40000008", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xf8}}, - {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x3ffffff8", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xf8}}, - {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x40000010", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xf8}}, - {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x3ffffff0", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xf8}}, - {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x7ffffff8", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xf8}}, - {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x10000004", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xf8}}, - {name: "STRD/RegisterOffset/src=R30,base=R0,offset=RegR8", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstReg2: RegR8}, exp: []byte{0x1e, 0x68, 0x28, 0xf8}}, - {name: "STRD/ConstOffset/src=R30,base=R30,offset=0xffffffffffffffff", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: -1}, exp: []byte{0xde, 0xf3, 0x1f, 0xf8}}, - {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x0", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 0}, exp: []byte{0xde, 0x3, 0x0, 0xf9}}, - {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x1", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 1}, exp: []byte{0xde, 0x13, 0x0, 0xf8}}, - {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x2", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 2}, exp: []byte{0xde, 0x23, 0x0, 0xf8}}, - {name: "STRD/ConstOffset/src=R30,base=R30,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: -2}, exp: []byte{0xde, 0xe3, 0x1f, 0xf8}}, - {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x4", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 4}, exp: []byte{0xde, 0x43, 0x0, 0xf8}}, - {name: "STRD/ConstOffset/src=R30,base=R30,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: -4}, exp: []byte{0xde, 0xc3, 0x1f, 0xf8}}, - {name: "STRD/ConstOffset/src=R30,base=R30,offset=0xf", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 15}, exp: []byte{0xde, 0xf3, 0x0, 0xf8}}, - {name: "STRD/ConstOffset/src=R30,base=R30,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: -15}, exp: []byte{0xde, 0x13, 0x1f, 0xf8}}, - {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x10", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 16}, exp: []byte{0xde, 0xb, 0x0, 0xf9}}, - {name: "STRD/ConstOffset/src=R30,base=R30,offset=0xf", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 15}, exp: []byte{0xde, 0xf3, 0x0, 0xf8}}, - {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x11", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 17}, exp: []byte{0xde, 0x13, 0x1, 0xf8}}, - {name: "STRD/ConstOffset/src=R30,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: -128}, exp: []byte{0xde, 0x3, 0x18, 0xf8}}, - {name: "STRD/ConstOffset/src=R30,base=R30,offset=0xffffffffffffff00", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: -256}, exp: []byte{0xde, 0x3, 0x10, 0xf8}}, - {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x50", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 80}, exp: []byte{0xde, 0x2b, 0x0, 0xf9}}, - {name: "STRD/ConstOffset/src=R30,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: -128}, exp: []byte{0xde, 0x3, 0x18, 0xf8}}, - {name: "STRD/ConstOffset/src=R30,base=R30,offset=0xff", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 255}, exp: []byte{0xde, 0xf3, 0xf, 0xf8}}, - {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x1000", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 4096}, exp: []byte{0xde, 0x3, 0x8, 0xf9}}, - {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x2000", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 8192}, exp: []byte{0xde, 0x3, 0x10, 0xf9}}, - {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x7ff8", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 32760}, exp: []byte{0xde, 0xff, 0x3f, 0xf9}}, - {name: "STRD/ConstOffset/src=R30,base=R30,offset=0xfff0", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 65520}, exp: []byte{0xdb, 0x23, 0x40, 0x91, 0x7e, 0xfb, 0x3f, 0xf9}}, - {name: "STRD/ConstOffset/src=R30,base=R30,offset=0xffe8", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 65512}, exp: []byte{0xdb, 0x23, 0x40, 0x91, 0x7e, 0xf7, 0x3f, 0xf9}}, - {name: "STRD/ConstOffset/src=R30,base=R30,offset=0xffe0", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 65504}, exp: []byte{0xdb, 0x23, 0x40, 0x91, 0x7e, 0xf3, 0x3f, 0xf9}}, - {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x8000000", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xf8}}, - {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x40000000", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xf8}}, - {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x40000008", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xf8}}, - {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x3ffffff8", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xf8}}, - {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x40000010", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xf8}}, - {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x3ffffff0", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xf8}}, - {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x7ffffff8", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xf8}}, - {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x10000004", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xf8}}, - {name: "STRD/RegisterOffset/src=R30,base=R30,offset=RegR8", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstReg2: RegR8}, exp: []byte{0xde, 0x6b, 0x28, 0xf8}}, - {name: "STRW/ConstOffset/src=R0,base=R0,offset=0xffffffffffffffff", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: -1}, exp: []byte{0x0, 0xf0, 0x1f, 0xb8}}, - {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x0", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 0}, exp: []byte{0x0, 0x0, 0x0, 0xb9}}, - {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x1", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 1}, exp: []byte{0x0, 0x10, 0x0, 0xb8}}, - {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x2", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 2}, exp: []byte{0x0, 0x20, 0x0, 0xb8}}, - {name: "STRW/ConstOffset/src=R0,base=R0,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: -2}, exp: []byte{0x0, 0xe0, 0x1f, 0xb8}}, - {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x4", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 4}, exp: []byte{0x0, 0x4, 0x0, 0xb9}}, - {name: "STRW/ConstOffset/src=R0,base=R0,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: -4}, exp: []byte{0x0, 0xc0, 0x1f, 0xb8}}, - {name: "STRW/ConstOffset/src=R0,base=R0,offset=0xf", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 15}, exp: []byte{0x0, 0xf0, 0x0, 0xb8}}, - {name: "STRW/ConstOffset/src=R0,base=R0,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: -15}, exp: []byte{0x0, 0x10, 0x1f, 0xb8}}, - {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x10", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 16}, exp: []byte{0x0, 0x10, 0x0, 0xb9}}, - {name: "STRW/ConstOffset/src=R0,base=R0,offset=0xf", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 15}, exp: []byte{0x0, 0xf0, 0x0, 0xb8}}, - {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x11", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 17}, exp: []byte{0x0, 0x10, 0x1, 0xb8}}, - {name: "STRW/ConstOffset/src=R0,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: -128}, exp: []byte{0x0, 0x0, 0x18, 0xb8}}, - {name: "STRW/ConstOffset/src=R0,base=R0,offset=0xffffffffffffff00", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: -256}, exp: []byte{0x0, 0x0, 0x10, 0xb8}}, - {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x50", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 80}, exp: []byte{0x0, 0x50, 0x0, 0xb9}}, - {name: "STRW/ConstOffset/src=R0,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: -128}, exp: []byte{0x0, 0x0, 0x18, 0xb8}}, - {name: "STRW/ConstOffset/src=R0,base=R0,offset=0xff", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 255}, exp: []byte{0x0, 0xf0, 0xf, 0xb8}}, - {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x1000", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 4096}, exp: []byte{0x0, 0x0, 0x10, 0xb9}}, - {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x2000", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 8192}, exp: []byte{0x0, 0x0, 0x20, 0xb9}}, - {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x7ff8", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 32760}, exp: []byte{0x1b, 0x10, 0x40, 0x91, 0x60, 0xfb, 0x3f, 0xb9}}, - {name: "STRW/ConstOffset/src=R0,base=R0,offset=0xfff0", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 65520}, exp: []byte{0x1b, 0x30, 0x40, 0x91, 0x60, 0xf3, 0x3f, 0xb9}}, - {name: "STRW/ConstOffset/src=R0,base=R0,offset=0xffe8", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 65512}, exp: []byte{0x1b, 0x30, 0x40, 0x91, 0x60, 0xeb, 0x3f, 0xb9}}, - {name: "STRW/ConstOffset/src=R0,base=R0,offset=0xffe0", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 65504}, exp: []byte{0x1b, 0x30, 0x40, 0x91, 0x60, 0xe3, 0x3f, 0xb9}}, - {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x8000000", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xb8}}, - {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x40000000", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xb8}}, - {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x40000008", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xb8}}, - {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x3ffffff8", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xb8}}, - {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x40000010", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xb8}}, - {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x3ffffff0", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xb8}}, - {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x7ffffff8", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xb8}}, - {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x10000004", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xb8}}, - {name: "STRW/RegisterOffset/src=R0,base=R0,offset=RegR8", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstReg2: RegR8}, exp: []byte{0x0, 0x68, 0x28, 0xb8}}, - {name: "STRW/ConstOffset/src=R0,base=R30,offset=0xffffffffffffffff", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: -1}, exp: []byte{0xc0, 0xf3, 0x1f, 0xb8}}, - {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x0", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 0}, exp: []byte{0xc0, 0x3, 0x0, 0xb9}}, - {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x1", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 1}, exp: []byte{0xc0, 0x13, 0x0, 0xb8}}, - {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x2", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 2}, exp: []byte{0xc0, 0x23, 0x0, 0xb8}}, - {name: "STRW/ConstOffset/src=R0,base=R30,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: -2}, exp: []byte{0xc0, 0xe3, 0x1f, 0xb8}}, - {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x4", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 4}, exp: []byte{0xc0, 0x7, 0x0, 0xb9}}, - {name: "STRW/ConstOffset/src=R0,base=R30,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: -4}, exp: []byte{0xc0, 0xc3, 0x1f, 0xb8}}, - {name: "STRW/ConstOffset/src=R0,base=R30,offset=0xf", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 15}, exp: []byte{0xc0, 0xf3, 0x0, 0xb8}}, - {name: "STRW/ConstOffset/src=R0,base=R30,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: -15}, exp: []byte{0xc0, 0x13, 0x1f, 0xb8}}, - {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x10", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 16}, exp: []byte{0xc0, 0x13, 0x0, 0xb9}}, - {name: "STRW/ConstOffset/src=R0,base=R30,offset=0xf", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 15}, exp: []byte{0xc0, 0xf3, 0x0, 0xb8}}, - {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x11", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 17}, exp: []byte{0xc0, 0x13, 0x1, 0xb8}}, - {name: "STRW/ConstOffset/src=R0,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: -128}, exp: []byte{0xc0, 0x3, 0x18, 0xb8}}, - {name: "STRW/ConstOffset/src=R0,base=R30,offset=0xffffffffffffff00", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: -256}, exp: []byte{0xc0, 0x3, 0x10, 0xb8}}, - {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x50", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 80}, exp: []byte{0xc0, 0x53, 0x0, 0xb9}}, - {name: "STRW/ConstOffset/src=R0,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: -128}, exp: []byte{0xc0, 0x3, 0x18, 0xb8}}, - {name: "STRW/ConstOffset/src=R0,base=R30,offset=0xff", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 255}, exp: []byte{0xc0, 0xf3, 0xf, 0xb8}}, - {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x1000", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 4096}, exp: []byte{0xc0, 0x3, 0x10, 0xb9}}, - {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x2000", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 8192}, exp: []byte{0xc0, 0x3, 0x20, 0xb9}}, - {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x7ff8", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 32760}, exp: []byte{0xdb, 0x13, 0x40, 0x91, 0x60, 0xfb, 0x3f, 0xb9}}, - {name: "STRW/ConstOffset/src=R0,base=R30,offset=0xfff0", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 65520}, exp: []byte{0xdb, 0x33, 0x40, 0x91, 0x60, 0xf3, 0x3f, 0xb9}}, - {name: "STRW/ConstOffset/src=R0,base=R30,offset=0xffe8", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 65512}, exp: []byte{0xdb, 0x33, 0x40, 0x91, 0x60, 0xeb, 0x3f, 0xb9}}, - {name: "STRW/ConstOffset/src=R0,base=R30,offset=0xffe0", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 65504}, exp: []byte{0xdb, 0x33, 0x40, 0x91, 0x60, 0xe3, 0x3f, 0xb9}}, - {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x8000000", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xb8}}, - {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x40000000", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xb8}}, - {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x40000008", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xb8}}, - {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x3ffffff8", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xb8}}, - {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x40000010", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xb8}}, - {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x3ffffff0", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xb8}}, - {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x7ffffff8", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xb8}}, - {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x10000004", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xb8}}, - {name: "STRW/RegisterOffset/src=R0,base=R30,offset=RegR8", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstReg2: RegR8}, exp: []byte{0xc0, 0x6b, 0x28, 0xb8}}, - {name: "STRW/ConstOffset/src=R30,base=R0,offset=0xffffffffffffffff", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: -1}, exp: []byte{0x1e, 0xf0, 0x1f, 0xb8}}, - {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x0", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 0}, exp: []byte{0x1e, 0x0, 0x0, 0xb9}}, - {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x1", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 1}, exp: []byte{0x1e, 0x10, 0x0, 0xb8}}, - {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x2", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 2}, exp: []byte{0x1e, 0x20, 0x0, 0xb8}}, - {name: "STRW/ConstOffset/src=R30,base=R0,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: -2}, exp: []byte{0x1e, 0xe0, 0x1f, 0xb8}}, - {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x4", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 4}, exp: []byte{0x1e, 0x4, 0x0, 0xb9}}, - {name: "STRW/ConstOffset/src=R30,base=R0,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: -4}, exp: []byte{0x1e, 0xc0, 0x1f, 0xb8}}, - {name: "STRW/ConstOffset/src=R30,base=R0,offset=0xf", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 15}, exp: []byte{0x1e, 0xf0, 0x0, 0xb8}}, - {name: "STRW/ConstOffset/src=R30,base=R0,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: -15}, exp: []byte{0x1e, 0x10, 0x1f, 0xb8}}, - {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x10", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 16}, exp: []byte{0x1e, 0x10, 0x0, 0xb9}}, - {name: "STRW/ConstOffset/src=R30,base=R0,offset=0xf", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 15}, exp: []byte{0x1e, 0xf0, 0x0, 0xb8}}, - {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x11", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 17}, exp: []byte{0x1e, 0x10, 0x1, 0xb8}}, - {name: "STRW/ConstOffset/src=R30,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: -128}, exp: []byte{0x1e, 0x0, 0x18, 0xb8}}, - {name: "STRW/ConstOffset/src=R30,base=R0,offset=0xffffffffffffff00", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: -256}, exp: []byte{0x1e, 0x0, 0x10, 0xb8}}, - {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x50", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 80}, exp: []byte{0x1e, 0x50, 0x0, 0xb9}}, - {name: "STRW/ConstOffset/src=R30,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: -128}, exp: []byte{0x1e, 0x0, 0x18, 0xb8}}, - {name: "STRW/ConstOffset/src=R30,base=R0,offset=0xff", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 255}, exp: []byte{0x1e, 0xf0, 0xf, 0xb8}}, - {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x1000", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 4096}, exp: []byte{0x1e, 0x0, 0x10, 0xb9}}, - {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x2000", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 8192}, exp: []byte{0x1e, 0x0, 0x20, 0xb9}}, - {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x7ff8", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 32760}, exp: []byte{0x1b, 0x10, 0x40, 0x91, 0x7e, 0xfb, 0x3f, 0xb9}}, - {name: "STRW/ConstOffset/src=R30,base=R0,offset=0xfff0", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 65520}, exp: []byte{0x1b, 0x30, 0x40, 0x91, 0x7e, 0xf3, 0x3f, 0xb9}}, - {name: "STRW/ConstOffset/src=R30,base=R0,offset=0xffe8", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 65512}, exp: []byte{0x1b, 0x30, 0x40, 0x91, 0x7e, 0xeb, 0x3f, 0xb9}}, - {name: "STRW/ConstOffset/src=R30,base=R0,offset=0xffe0", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 65504}, exp: []byte{0x1b, 0x30, 0x40, 0x91, 0x7e, 0xe3, 0x3f, 0xb9}}, - {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x8000000", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xb8}}, - {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x40000000", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xb8}}, - {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x40000008", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xb8}}, - {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x3ffffff8", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xb8}}, - {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x40000010", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xb8}}, - {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x3ffffff0", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xb8}}, - {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x7ffffff8", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xb8}}, - {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x10000004", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xb8}}, - {name: "STRW/RegisterOffset/src=R30,base=R0,offset=RegR8", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstReg2: RegR8}, exp: []byte{0x1e, 0x68, 0x28, 0xb8}}, - {name: "STRW/ConstOffset/src=R30,base=R30,offset=0xffffffffffffffff", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: -1}, exp: []byte{0xde, 0xf3, 0x1f, 0xb8}}, - {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x0", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 0}, exp: []byte{0xde, 0x3, 0x0, 0xb9}}, - {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x1", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 1}, exp: []byte{0xde, 0x13, 0x0, 0xb8}}, - {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x2", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 2}, exp: []byte{0xde, 0x23, 0x0, 0xb8}}, - {name: "STRW/ConstOffset/src=R30,base=R30,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: -2}, exp: []byte{0xde, 0xe3, 0x1f, 0xb8}}, - {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x4", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 4}, exp: []byte{0xde, 0x7, 0x0, 0xb9}}, - {name: "STRW/ConstOffset/src=R30,base=R30,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: -4}, exp: []byte{0xde, 0xc3, 0x1f, 0xb8}}, - {name: "STRW/ConstOffset/src=R30,base=R30,offset=0xf", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 15}, exp: []byte{0xde, 0xf3, 0x0, 0xb8}}, - {name: "STRW/ConstOffset/src=R30,base=R30,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: -15}, exp: []byte{0xde, 0x13, 0x1f, 0xb8}}, - {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x10", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 16}, exp: []byte{0xde, 0x13, 0x0, 0xb9}}, - {name: "STRW/ConstOffset/src=R30,base=R30,offset=0xf", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 15}, exp: []byte{0xde, 0xf3, 0x0, 0xb8}}, - {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x11", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 17}, exp: []byte{0xde, 0x13, 0x1, 0xb8}}, - {name: "STRW/ConstOffset/src=R30,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: -128}, exp: []byte{0xde, 0x3, 0x18, 0xb8}}, - {name: "STRW/ConstOffset/src=R30,base=R30,offset=0xffffffffffffff00", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: -256}, exp: []byte{0xde, 0x3, 0x10, 0xb8}}, - {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x50", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 80}, exp: []byte{0xde, 0x53, 0x0, 0xb9}}, - {name: "STRW/ConstOffset/src=R30,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: -128}, exp: []byte{0xde, 0x3, 0x18, 0xb8}}, - {name: "STRW/ConstOffset/src=R30,base=R30,offset=0xff", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 255}, exp: []byte{0xde, 0xf3, 0xf, 0xb8}}, - {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x1000", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 4096}, exp: []byte{0xde, 0x3, 0x10, 0xb9}}, - {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x2000", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 8192}, exp: []byte{0xde, 0x3, 0x20, 0xb9}}, - {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x7ff8", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 32760}, exp: []byte{0xdb, 0x13, 0x40, 0x91, 0x7e, 0xfb, 0x3f, 0xb9}}, - {name: "STRW/ConstOffset/src=R30,base=R30,offset=0xfff0", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 65520}, exp: []byte{0xdb, 0x33, 0x40, 0x91, 0x7e, 0xf3, 0x3f, 0xb9}}, - {name: "STRW/ConstOffset/src=R30,base=R30,offset=0xffe8", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 65512}, exp: []byte{0xdb, 0x33, 0x40, 0x91, 0x7e, 0xeb, 0x3f, 0xb9}}, - {name: "STRW/ConstOffset/src=R30,base=R30,offset=0xffe0", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 65504}, exp: []byte{0xdb, 0x33, 0x40, 0x91, 0x7e, 0xe3, 0x3f, 0xb9}}, - {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x8000000", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xb8}}, - {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x40000000", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xb8}}, - {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x40000008", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xb8}}, - {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x3ffffff8", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xb8}}, - {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x40000010", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xb8}}, - {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x3ffffff0", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xb8}}, - {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x7ffffff8", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xb8}}, - {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x10000004", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xb8}}, - {name: "STRW/RegisterOffset/src=R30,base=R30,offset=RegR8", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstReg2: RegR8}, exp: []byte{0xde, 0x6b, 0x28, 0xb8}}, - {name: "STRH/ConstOffset/src=R0,base=R0,offset=0xffffffffffffffff", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: -1}, exp: []byte{0x0, 0xf0, 0x1f, 0x78}}, - {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x0", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 0}, exp: []byte{0x0, 0x0, 0x0, 0x79}}, - {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x1", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 1}, exp: []byte{0x0, 0x10, 0x0, 0x78}}, - {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x2", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 2}, exp: []byte{0x0, 0x4, 0x0, 0x79}}, - {name: "STRH/ConstOffset/src=R0,base=R0,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: -2}, exp: []byte{0x0, 0xe0, 0x1f, 0x78}}, - {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x4", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 4}, exp: []byte{0x0, 0x8, 0x0, 0x79}}, - {name: "STRH/ConstOffset/src=R0,base=R0,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: -4}, exp: []byte{0x0, 0xc0, 0x1f, 0x78}}, - {name: "STRH/ConstOffset/src=R0,base=R0,offset=0xf", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 15}, exp: []byte{0x0, 0xf0, 0x0, 0x78}}, - {name: "STRH/ConstOffset/src=R0,base=R0,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: -15}, exp: []byte{0x0, 0x10, 0x1f, 0x78}}, - {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x10", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 16}, exp: []byte{0x0, 0x20, 0x0, 0x79}}, - {name: "STRH/ConstOffset/src=R0,base=R0,offset=0xf", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 15}, exp: []byte{0x0, 0xf0, 0x0, 0x78}}, - {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x11", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 17}, exp: []byte{0x0, 0x10, 0x1, 0x78}}, - {name: "STRH/ConstOffset/src=R0,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: -128}, exp: []byte{0x0, 0x0, 0x18, 0x78}}, - {name: "STRH/ConstOffset/src=R0,base=R0,offset=0xffffffffffffff00", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: -256}, exp: []byte{0x0, 0x0, 0x10, 0x78}}, - {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x50", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 80}, exp: []byte{0x0, 0xa0, 0x0, 0x79}}, - {name: "STRH/ConstOffset/src=R0,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: -128}, exp: []byte{0x0, 0x0, 0x18, 0x78}}, - {name: "STRH/ConstOffset/src=R0,base=R0,offset=0xff", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 255}, exp: []byte{0x0, 0xf0, 0xf, 0x78}}, - {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x1000", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 4096}, exp: []byte{0x0, 0x0, 0x20, 0x79}}, - {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x2000", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 8192}, exp: []byte{0x1b, 0x8, 0x40, 0x91, 0x60, 0x3, 0x0, 0x79}}, - {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x7ff8", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 32760}, exp: []byte{0x1b, 0x18, 0x40, 0x91, 0x60, 0xf3, 0x3f, 0x79}}, - {name: "STRH/ConstOffset/src=R0,base=R0,offset=0xfff0", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 65520}, exp: []byte{0x1b, 0x38, 0x40, 0x91, 0x60, 0xe3, 0x3f, 0x79}}, - {name: "STRH/ConstOffset/src=R0,base=R0,offset=0xffe8", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 65512}, exp: []byte{0x1b, 0x38, 0x40, 0x91, 0x60, 0xd3, 0x3f, 0x79}}, - {name: "STRH/ConstOffset/src=R0,base=R0,offset=0xffe0", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 65504}, exp: []byte{0x1b, 0x38, 0x40, 0x91, 0x60, 0xc3, 0x3f, 0x79}}, - {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x8000000", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0x78}}, - {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x40000000", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0x78}}, - {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x40000008", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0x78}}, - {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x3ffffff8", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0x78}}, - {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x40000010", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0x78}}, - {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x3ffffff0", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0x78}}, - {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x7ffffff8", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0x78}}, - {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x10000004", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0x78}}, - {name: "STRH/RegisterOffset/src=R0,base=R0,offset=RegR8", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstReg2: RegR8}, exp: []byte{0x0, 0x68, 0x28, 0x78}}, - {name: "STRH/ConstOffset/src=R0,base=R30,offset=0xffffffffffffffff", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: -1}, exp: []byte{0xc0, 0xf3, 0x1f, 0x78}}, - {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x0", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 0}, exp: []byte{0xc0, 0x3, 0x0, 0x79}}, - {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x1", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 1}, exp: []byte{0xc0, 0x13, 0x0, 0x78}}, - {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x2", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 2}, exp: []byte{0xc0, 0x7, 0x0, 0x79}}, - {name: "STRH/ConstOffset/src=R0,base=R30,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: -2}, exp: []byte{0xc0, 0xe3, 0x1f, 0x78}}, - {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x4", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 4}, exp: []byte{0xc0, 0xb, 0x0, 0x79}}, - {name: "STRH/ConstOffset/src=R0,base=R30,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: -4}, exp: []byte{0xc0, 0xc3, 0x1f, 0x78}}, - {name: "STRH/ConstOffset/src=R0,base=R30,offset=0xf", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 15}, exp: []byte{0xc0, 0xf3, 0x0, 0x78}}, - {name: "STRH/ConstOffset/src=R0,base=R30,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: -15}, exp: []byte{0xc0, 0x13, 0x1f, 0x78}}, - {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x10", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 16}, exp: []byte{0xc0, 0x23, 0x0, 0x79}}, - {name: "STRH/ConstOffset/src=R0,base=R30,offset=0xf", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 15}, exp: []byte{0xc0, 0xf3, 0x0, 0x78}}, - {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x11", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 17}, exp: []byte{0xc0, 0x13, 0x1, 0x78}}, - {name: "STRH/ConstOffset/src=R0,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: -128}, exp: []byte{0xc0, 0x3, 0x18, 0x78}}, - {name: "STRH/ConstOffset/src=R0,base=R30,offset=0xffffffffffffff00", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: -256}, exp: []byte{0xc0, 0x3, 0x10, 0x78}}, - {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x50", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 80}, exp: []byte{0xc0, 0xa3, 0x0, 0x79}}, - {name: "STRH/ConstOffset/src=R0,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: -128}, exp: []byte{0xc0, 0x3, 0x18, 0x78}}, - {name: "STRH/ConstOffset/src=R0,base=R30,offset=0xff", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 255}, exp: []byte{0xc0, 0xf3, 0xf, 0x78}}, - {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x1000", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 4096}, exp: []byte{0xc0, 0x3, 0x20, 0x79}}, - {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x2000", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 8192}, exp: []byte{0xdb, 0xb, 0x40, 0x91, 0x60, 0x3, 0x0, 0x79}}, - {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x7ff8", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 32760}, exp: []byte{0xdb, 0x1b, 0x40, 0x91, 0x60, 0xf3, 0x3f, 0x79}}, - {name: "STRH/ConstOffset/src=R0,base=R30,offset=0xfff0", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 65520}, exp: []byte{0xdb, 0x3b, 0x40, 0x91, 0x60, 0xe3, 0x3f, 0x79}}, - {name: "STRH/ConstOffset/src=R0,base=R30,offset=0xffe8", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 65512}, exp: []byte{0xdb, 0x3b, 0x40, 0x91, 0x60, 0xd3, 0x3f, 0x79}}, - {name: "STRH/ConstOffset/src=R0,base=R30,offset=0xffe0", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 65504}, exp: []byte{0xdb, 0x3b, 0x40, 0x91, 0x60, 0xc3, 0x3f, 0x79}}, - {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x8000000", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0x78}}, - {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x40000000", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0x78}}, - {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x40000008", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0x78}}, - {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x3ffffff8", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0x78}}, - {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x40000010", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0x78}}, - {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x3ffffff0", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0x78}}, - {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x7ffffff8", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0x78}}, - {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x10000004", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0x78}}, - {name: "STRH/RegisterOffset/src=R0,base=R30,offset=RegR8", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstReg2: RegR8}, exp: []byte{0xc0, 0x6b, 0x28, 0x78}}, - {name: "STRH/ConstOffset/src=R30,base=R0,offset=0xffffffffffffffff", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: -1}, exp: []byte{0x1e, 0xf0, 0x1f, 0x78}}, - {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x0", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 0}, exp: []byte{0x1e, 0x0, 0x0, 0x79}}, - {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x1", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 1}, exp: []byte{0x1e, 0x10, 0x0, 0x78}}, - {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x2", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 2}, exp: []byte{0x1e, 0x4, 0x0, 0x79}}, - {name: "STRH/ConstOffset/src=R30,base=R0,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: -2}, exp: []byte{0x1e, 0xe0, 0x1f, 0x78}}, - {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x4", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 4}, exp: []byte{0x1e, 0x8, 0x0, 0x79}}, - {name: "STRH/ConstOffset/src=R30,base=R0,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: -4}, exp: []byte{0x1e, 0xc0, 0x1f, 0x78}}, - {name: "STRH/ConstOffset/src=R30,base=R0,offset=0xf", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 15}, exp: []byte{0x1e, 0xf0, 0x0, 0x78}}, - {name: "STRH/ConstOffset/src=R30,base=R0,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: -15}, exp: []byte{0x1e, 0x10, 0x1f, 0x78}}, - {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x10", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 16}, exp: []byte{0x1e, 0x20, 0x0, 0x79}}, - {name: "STRH/ConstOffset/src=R30,base=R0,offset=0xf", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 15}, exp: []byte{0x1e, 0xf0, 0x0, 0x78}}, - {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x11", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 17}, exp: []byte{0x1e, 0x10, 0x1, 0x78}}, - {name: "STRH/ConstOffset/src=R30,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: -128}, exp: []byte{0x1e, 0x0, 0x18, 0x78}}, - {name: "STRH/ConstOffset/src=R30,base=R0,offset=0xffffffffffffff00", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: -256}, exp: []byte{0x1e, 0x0, 0x10, 0x78}}, - {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x50", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 80}, exp: []byte{0x1e, 0xa0, 0x0, 0x79}}, - {name: "STRH/ConstOffset/src=R30,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: -128}, exp: []byte{0x1e, 0x0, 0x18, 0x78}}, - {name: "STRH/ConstOffset/src=R30,base=R0,offset=0xff", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 255}, exp: []byte{0x1e, 0xf0, 0xf, 0x78}}, - {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x1000", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 4096}, exp: []byte{0x1e, 0x0, 0x20, 0x79}}, - {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x2000", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 8192}, exp: []byte{0x1b, 0x8, 0x40, 0x91, 0x7e, 0x3, 0x0, 0x79}}, - {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x7ff8", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 32760}, exp: []byte{0x1b, 0x18, 0x40, 0x91, 0x7e, 0xf3, 0x3f, 0x79}}, - {name: "STRH/ConstOffset/src=R30,base=R0,offset=0xfff0", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 65520}, exp: []byte{0x1b, 0x38, 0x40, 0x91, 0x7e, 0xe3, 0x3f, 0x79}}, - {name: "STRH/ConstOffset/src=R30,base=R0,offset=0xffe8", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 65512}, exp: []byte{0x1b, 0x38, 0x40, 0x91, 0x7e, 0xd3, 0x3f, 0x79}}, - {name: "STRH/ConstOffset/src=R30,base=R0,offset=0xffe0", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 65504}, exp: []byte{0x1b, 0x38, 0x40, 0x91, 0x7e, 0xc3, 0x3f, 0x79}}, - {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x8000000", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0x78}}, - {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x40000000", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0x78}}, - {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x40000008", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0x78}}, - {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x3ffffff8", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0x78}}, - {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x40000010", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0x78}}, - {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x3ffffff0", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0x78}}, - {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x7ffffff8", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0x78}}, - {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x10000004", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0x78}}, - {name: "STRH/RegisterOffset/src=R30,base=R0,offset=RegR8", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstReg2: RegR8}, exp: []byte{0x1e, 0x68, 0x28, 0x78}}, - {name: "STRH/ConstOffset/src=R30,base=R30,offset=0xffffffffffffffff", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: -1}, exp: []byte{0xde, 0xf3, 0x1f, 0x78}}, - {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x0", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 0}, exp: []byte{0xde, 0x3, 0x0, 0x79}}, - {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x1", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 1}, exp: []byte{0xde, 0x13, 0x0, 0x78}}, - {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x2", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 2}, exp: []byte{0xde, 0x7, 0x0, 0x79}}, - {name: "STRH/ConstOffset/src=R30,base=R30,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: -2}, exp: []byte{0xde, 0xe3, 0x1f, 0x78}}, - {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x4", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 4}, exp: []byte{0xde, 0xb, 0x0, 0x79}}, - {name: "STRH/ConstOffset/src=R30,base=R30,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: -4}, exp: []byte{0xde, 0xc3, 0x1f, 0x78}}, - {name: "STRH/ConstOffset/src=R30,base=R30,offset=0xf", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 15}, exp: []byte{0xde, 0xf3, 0x0, 0x78}}, - {name: "STRH/ConstOffset/src=R30,base=R30,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: -15}, exp: []byte{0xde, 0x13, 0x1f, 0x78}}, - {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x10", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 16}, exp: []byte{0xde, 0x23, 0x0, 0x79}}, - {name: "STRH/ConstOffset/src=R30,base=R30,offset=0xf", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 15}, exp: []byte{0xde, 0xf3, 0x0, 0x78}}, - {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x11", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 17}, exp: []byte{0xde, 0x13, 0x1, 0x78}}, - {name: "STRH/ConstOffset/src=R30,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: -128}, exp: []byte{0xde, 0x3, 0x18, 0x78}}, - {name: "STRH/ConstOffset/src=R30,base=R30,offset=0xffffffffffffff00", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: -256}, exp: []byte{0xde, 0x3, 0x10, 0x78}}, - {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x50", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 80}, exp: []byte{0xde, 0xa3, 0x0, 0x79}}, - {name: "STRH/ConstOffset/src=R30,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: -128}, exp: []byte{0xde, 0x3, 0x18, 0x78}}, - {name: "STRH/ConstOffset/src=R30,base=R30,offset=0xff", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 255}, exp: []byte{0xde, 0xf3, 0xf, 0x78}}, - {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x1000", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 4096}, exp: []byte{0xde, 0x3, 0x20, 0x79}}, - {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x2000", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 8192}, exp: []byte{0xdb, 0xb, 0x40, 0x91, 0x7e, 0x3, 0x0, 0x79}}, - {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x7ff8", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 32760}, exp: []byte{0xdb, 0x1b, 0x40, 0x91, 0x7e, 0xf3, 0x3f, 0x79}}, - {name: "STRH/ConstOffset/src=R30,base=R30,offset=0xfff0", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 65520}, exp: []byte{0xdb, 0x3b, 0x40, 0x91, 0x7e, 0xe3, 0x3f, 0x79}}, - {name: "STRH/ConstOffset/src=R30,base=R30,offset=0xffe8", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 65512}, exp: []byte{0xdb, 0x3b, 0x40, 0x91, 0x7e, 0xd3, 0x3f, 0x79}}, - {name: "STRH/ConstOffset/src=R30,base=R30,offset=0xffe0", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 65504}, exp: []byte{0xdb, 0x3b, 0x40, 0x91, 0x7e, 0xc3, 0x3f, 0x79}}, - {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x8000000", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0x78}}, - {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x40000000", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0x78}}, - {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x40000008", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0x78}}, - {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x3ffffff8", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0x78}}, - {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x40000010", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0x78}}, - {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x3ffffff0", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0x78}}, - {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x7ffffff8", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0x78}}, - {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x10000004", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0x78}}, - {name: "STRH/RegisterOffset/src=R30,base=R30,offset=RegR8", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstReg2: RegR8}, exp: []byte{0xde, 0x6b, 0x28, 0x78}}, - {name: "STRB/ConstOffset/src=R0,base=R0,offset=0xffffffffffffffff", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: -1}, exp: []byte{0x0, 0xf0, 0x1f, 0x38}}, - {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x0", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 0}, exp: []byte{0x0, 0x0, 0x0, 0x39}}, - {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x1", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 1}, exp: []byte{0x0, 0x4, 0x0, 0x39}}, - {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x2", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 2}, exp: []byte{0x0, 0x8, 0x0, 0x39}}, - {name: "STRB/ConstOffset/src=R0,base=R0,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: -2}, exp: []byte{0x0, 0xe0, 0x1f, 0x38}}, - {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x4", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 4}, exp: []byte{0x0, 0x10, 0x0, 0x39}}, - {name: "STRB/ConstOffset/src=R0,base=R0,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: -4}, exp: []byte{0x0, 0xc0, 0x1f, 0x38}}, - {name: "STRB/ConstOffset/src=R0,base=R0,offset=0xf", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 15}, exp: []byte{0x0, 0x3c, 0x0, 0x39}}, - {name: "STRB/ConstOffset/src=R0,base=R0,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: -15}, exp: []byte{0x0, 0x10, 0x1f, 0x38}}, - {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x10", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 16}, exp: []byte{0x0, 0x40, 0x0, 0x39}}, - {name: "STRB/ConstOffset/src=R0,base=R0,offset=0xf", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 15}, exp: []byte{0x0, 0x3c, 0x0, 0x39}}, - {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x11", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 17}, exp: []byte{0x0, 0x44, 0x0, 0x39}}, - {name: "STRB/ConstOffset/src=R0,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: -128}, exp: []byte{0x0, 0x0, 0x18, 0x38}}, - {name: "STRB/ConstOffset/src=R0,base=R0,offset=0xffffffffffffff00", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: -256}, exp: []byte{0x0, 0x0, 0x10, 0x38}}, - {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x50", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 80}, exp: []byte{0x0, 0x40, 0x1, 0x39}}, - {name: "STRB/ConstOffset/src=R0,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: -128}, exp: []byte{0x0, 0x0, 0x18, 0x38}}, - {name: "STRB/ConstOffset/src=R0,base=R0,offset=0xff", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 255}, exp: []byte{0x0, 0xfc, 0x3, 0x39}}, - {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x1000", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 4096}, exp: []byte{0x1b, 0x4, 0x40, 0x91, 0x60, 0x3, 0x0, 0x39}}, - {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x2000", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 8192}, exp: []byte{0x1b, 0x8, 0x40, 0x91, 0x60, 0x3, 0x0, 0x39}}, - {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x7ff8", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 32760}, exp: []byte{0x1b, 0x1c, 0x40, 0x91, 0x60, 0xe3, 0x3f, 0x39}}, - {name: "STRB/ConstOffset/src=R0,base=R0,offset=0xfff0", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 65520}, exp: []byte{0x1b, 0x3c, 0x40, 0x91, 0x60, 0xc3, 0x3f, 0x39}}, - {name: "STRB/ConstOffset/src=R0,base=R0,offset=0xffe8", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 65512}, exp: []byte{0x1b, 0x3c, 0x40, 0x91, 0x60, 0xa3, 0x3f, 0x39}}, - {name: "STRB/ConstOffset/src=R0,base=R0,offset=0xffe0", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 65504}, exp: []byte{0x1b, 0x3c, 0x40, 0x91, 0x60, 0x83, 0x3f, 0x39}}, - {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x8000000", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0x38}}, - {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x40000000", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0x38}}, - {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x40000008", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0x38}}, - {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x3ffffff8", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0x38}}, - {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x40000010", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0x38}}, - {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x3ffffff0", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0x38}}, - {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x7ffffff8", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0x38}}, - {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x10000004", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0x38}}, - {name: "STRB/RegisterOffset/src=R0,base=R0,offset=RegR8", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstReg2: RegR8}, exp: []byte{0x0, 0x68, 0x28, 0x38}}, - {name: "STRB/ConstOffset/src=R0,base=R30,offset=0xffffffffffffffff", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: -1}, exp: []byte{0xc0, 0xf3, 0x1f, 0x38}}, - {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x0", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 0}, exp: []byte{0xc0, 0x3, 0x0, 0x39}}, - {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x1", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 1}, exp: []byte{0xc0, 0x7, 0x0, 0x39}}, - {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x2", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 2}, exp: []byte{0xc0, 0xb, 0x0, 0x39}}, - {name: "STRB/ConstOffset/src=R0,base=R30,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: -2}, exp: []byte{0xc0, 0xe3, 0x1f, 0x38}}, - {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x4", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 4}, exp: []byte{0xc0, 0x13, 0x0, 0x39}}, - {name: "STRB/ConstOffset/src=R0,base=R30,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: -4}, exp: []byte{0xc0, 0xc3, 0x1f, 0x38}}, - {name: "STRB/ConstOffset/src=R0,base=R30,offset=0xf", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 15}, exp: []byte{0xc0, 0x3f, 0x0, 0x39}}, - {name: "STRB/ConstOffset/src=R0,base=R30,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: -15}, exp: []byte{0xc0, 0x13, 0x1f, 0x38}}, - {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x10", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 16}, exp: []byte{0xc0, 0x43, 0x0, 0x39}}, - {name: "STRB/ConstOffset/src=R0,base=R30,offset=0xf", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 15}, exp: []byte{0xc0, 0x3f, 0x0, 0x39}}, - {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x11", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 17}, exp: []byte{0xc0, 0x47, 0x0, 0x39}}, - {name: "STRB/ConstOffset/src=R0,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: -128}, exp: []byte{0xc0, 0x3, 0x18, 0x38}}, - {name: "STRB/ConstOffset/src=R0,base=R30,offset=0xffffffffffffff00", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: -256}, exp: []byte{0xc0, 0x3, 0x10, 0x38}}, - {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x50", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 80}, exp: []byte{0xc0, 0x43, 0x1, 0x39}}, - {name: "STRB/ConstOffset/src=R0,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: -128}, exp: []byte{0xc0, 0x3, 0x18, 0x38}}, - {name: "STRB/ConstOffset/src=R0,base=R30,offset=0xff", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 255}, exp: []byte{0xc0, 0xff, 0x3, 0x39}}, - {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x1000", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 4096}, exp: []byte{0xdb, 0x7, 0x40, 0x91, 0x60, 0x3, 0x0, 0x39}}, - {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x2000", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 8192}, exp: []byte{0xdb, 0xb, 0x40, 0x91, 0x60, 0x3, 0x0, 0x39}}, - {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x7ff8", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 32760}, exp: []byte{0xdb, 0x1f, 0x40, 0x91, 0x60, 0xe3, 0x3f, 0x39}}, - {name: "STRB/ConstOffset/src=R0,base=R30,offset=0xfff0", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 65520}, exp: []byte{0xdb, 0x3f, 0x40, 0x91, 0x60, 0xc3, 0x3f, 0x39}}, - {name: "STRB/ConstOffset/src=R0,base=R30,offset=0xffe8", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 65512}, exp: []byte{0xdb, 0x3f, 0x40, 0x91, 0x60, 0xa3, 0x3f, 0x39}}, - {name: "STRB/ConstOffset/src=R0,base=R30,offset=0xffe0", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 65504}, exp: []byte{0xdb, 0x3f, 0x40, 0x91, 0x60, 0x83, 0x3f, 0x39}}, - {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x8000000", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0x38}}, - {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x40000000", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0x38}}, - {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x40000008", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0x38}}, - {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x3ffffff8", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0x38}}, - {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x40000010", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0x38}}, - {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x3ffffff0", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0x38}}, - {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x7ffffff8", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0x38}}, - {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x10000004", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0x38}}, - {name: "STRB/RegisterOffset/src=R0,base=R30,offset=RegR8", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstReg2: RegR8}, exp: []byte{0xc0, 0x6b, 0x28, 0x38}}, - {name: "STRB/ConstOffset/src=R30,base=R0,offset=0xffffffffffffffff", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: -1}, exp: []byte{0x1e, 0xf0, 0x1f, 0x38}}, - {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x0", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 0}, exp: []byte{0x1e, 0x0, 0x0, 0x39}}, - {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x1", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 1}, exp: []byte{0x1e, 0x4, 0x0, 0x39}}, - {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x2", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 2}, exp: []byte{0x1e, 0x8, 0x0, 0x39}}, - {name: "STRB/ConstOffset/src=R30,base=R0,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: -2}, exp: []byte{0x1e, 0xe0, 0x1f, 0x38}}, - {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x4", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 4}, exp: []byte{0x1e, 0x10, 0x0, 0x39}}, - {name: "STRB/ConstOffset/src=R30,base=R0,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: -4}, exp: []byte{0x1e, 0xc0, 0x1f, 0x38}}, - {name: "STRB/ConstOffset/src=R30,base=R0,offset=0xf", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 15}, exp: []byte{0x1e, 0x3c, 0x0, 0x39}}, - {name: "STRB/ConstOffset/src=R30,base=R0,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: -15}, exp: []byte{0x1e, 0x10, 0x1f, 0x38}}, - {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x10", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 16}, exp: []byte{0x1e, 0x40, 0x0, 0x39}}, - {name: "STRB/ConstOffset/src=R30,base=R0,offset=0xf", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 15}, exp: []byte{0x1e, 0x3c, 0x0, 0x39}}, - {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x11", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 17}, exp: []byte{0x1e, 0x44, 0x0, 0x39}}, - {name: "STRB/ConstOffset/src=R30,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: -128}, exp: []byte{0x1e, 0x0, 0x18, 0x38}}, - {name: "STRB/ConstOffset/src=R30,base=R0,offset=0xffffffffffffff00", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: -256}, exp: []byte{0x1e, 0x0, 0x10, 0x38}}, - {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x50", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 80}, exp: []byte{0x1e, 0x40, 0x1, 0x39}}, - {name: "STRB/ConstOffset/src=R30,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: -128}, exp: []byte{0x1e, 0x0, 0x18, 0x38}}, - {name: "STRB/ConstOffset/src=R30,base=R0,offset=0xff", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 255}, exp: []byte{0x1e, 0xfc, 0x3, 0x39}}, - {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x1000", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 4096}, exp: []byte{0x1b, 0x4, 0x40, 0x91, 0x7e, 0x3, 0x0, 0x39}}, - {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x2000", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 8192}, exp: []byte{0x1b, 0x8, 0x40, 0x91, 0x7e, 0x3, 0x0, 0x39}}, - {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x7ff8", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 32760}, exp: []byte{0x1b, 0x1c, 0x40, 0x91, 0x7e, 0xe3, 0x3f, 0x39}}, - {name: "STRB/ConstOffset/src=R30,base=R0,offset=0xfff0", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 65520}, exp: []byte{0x1b, 0x3c, 0x40, 0x91, 0x7e, 0xc3, 0x3f, 0x39}}, - {name: "STRB/ConstOffset/src=R30,base=R0,offset=0xffe8", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 65512}, exp: []byte{0x1b, 0x3c, 0x40, 0x91, 0x7e, 0xa3, 0x3f, 0x39}}, - {name: "STRB/ConstOffset/src=R30,base=R0,offset=0xffe0", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 65504}, exp: []byte{0x1b, 0x3c, 0x40, 0x91, 0x7e, 0x83, 0x3f, 0x39}}, - {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x8000000", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0x38}}, - {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x40000000", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0x38}}, - {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x40000008", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0x38}}, - {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x3ffffff8", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0x38}}, - {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x40000010", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0x38}}, - {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x3ffffff0", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0x38}}, - {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x7ffffff8", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0x38}}, - {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x10000004", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0x38}}, - {name: "STRB/RegisterOffset/src=R30,base=R0,offset=RegR8", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstReg2: RegR8}, exp: []byte{0x1e, 0x68, 0x28, 0x38}}, - {name: "STRB/ConstOffset/src=R30,base=R30,offset=0xffffffffffffffff", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: -1}, exp: []byte{0xde, 0xf3, 0x1f, 0x38}}, - {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x0", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 0}, exp: []byte{0xde, 0x3, 0x0, 0x39}}, - {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x1", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 1}, exp: []byte{0xde, 0x7, 0x0, 0x39}}, - {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x2", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 2}, exp: []byte{0xde, 0xb, 0x0, 0x39}}, - {name: "STRB/ConstOffset/src=R30,base=R30,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: -2}, exp: []byte{0xde, 0xe3, 0x1f, 0x38}}, - {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x4", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 4}, exp: []byte{0xde, 0x13, 0x0, 0x39}}, - {name: "STRB/ConstOffset/src=R30,base=R30,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: -4}, exp: []byte{0xde, 0xc3, 0x1f, 0x38}}, - {name: "STRB/ConstOffset/src=R30,base=R30,offset=0xf", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 15}, exp: []byte{0xde, 0x3f, 0x0, 0x39}}, - {name: "STRB/ConstOffset/src=R30,base=R30,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: -15}, exp: []byte{0xde, 0x13, 0x1f, 0x38}}, - {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x10", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 16}, exp: []byte{0xde, 0x43, 0x0, 0x39}}, - {name: "STRB/ConstOffset/src=R30,base=R30,offset=0xf", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 15}, exp: []byte{0xde, 0x3f, 0x0, 0x39}}, - {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x11", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 17}, exp: []byte{0xde, 0x47, 0x0, 0x39}}, - {name: "STRB/ConstOffset/src=R30,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: -128}, exp: []byte{0xde, 0x3, 0x18, 0x38}}, - {name: "STRB/ConstOffset/src=R30,base=R30,offset=0xffffffffffffff00", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: -256}, exp: []byte{0xde, 0x3, 0x10, 0x38}}, - {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x50", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 80}, exp: []byte{0xde, 0x43, 0x1, 0x39}}, - {name: "STRB/ConstOffset/src=R30,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: -128}, exp: []byte{0xde, 0x3, 0x18, 0x38}}, - {name: "STRB/ConstOffset/src=R30,base=R30,offset=0xff", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 255}, exp: []byte{0xde, 0xff, 0x3, 0x39}}, - {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x1000", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 4096}, exp: []byte{0xdb, 0x7, 0x40, 0x91, 0x7e, 0x3, 0x0, 0x39}}, - {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x2000", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 8192}, exp: []byte{0xdb, 0xb, 0x40, 0x91, 0x7e, 0x3, 0x0, 0x39}}, - {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x7ff8", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 32760}, exp: []byte{0xdb, 0x1f, 0x40, 0x91, 0x7e, 0xe3, 0x3f, 0x39}}, - {name: "STRB/ConstOffset/src=R30,base=R30,offset=0xfff0", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 65520}, exp: []byte{0xdb, 0x3f, 0x40, 0x91, 0x7e, 0xc3, 0x3f, 0x39}}, - {name: "STRB/ConstOffset/src=R30,base=R30,offset=0xffe8", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 65512}, exp: []byte{0xdb, 0x3f, 0x40, 0x91, 0x7e, 0xa3, 0x3f, 0x39}}, - {name: "STRB/ConstOffset/src=R30,base=R30,offset=0xffe0", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 65504}, exp: []byte{0xdb, 0x3f, 0x40, 0x91, 0x7e, 0x83, 0x3f, 0x39}}, - {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x8000000", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0x38}}, - {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x40000000", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0x38}}, - {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x40000008", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0x38}}, - {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x3ffffff8", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0x38}}, - {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x40000010", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0x38}}, - {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x3ffffff0", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0x38}}, - {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x7ffffff8", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0x38}}, - {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x10000004", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0x38}}, - {name: "STRB/RegisterOffset/src=R30,base=R30,offset=RegR8", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstReg2: RegR8}, exp: []byte{0xde, 0x6b, 0x28, 0x38}}, - {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0xffffffffffffffff", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: -1}, exp: []byte{0x0, 0xf0, 0x1f, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x0", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 0}, exp: []byte{0x0, 0x0, 0x0, 0xfd}}, - {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x1", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 1}, exp: []byte{0x0, 0x10, 0x0, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x2", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 2}, exp: []byte{0x0, 0x20, 0x0, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: -2}, exp: []byte{0x0, 0xe0, 0x1f, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x4", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 4}, exp: []byte{0x0, 0x40, 0x0, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: -4}, exp: []byte{0x0, 0xc0, 0x1f, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0xf", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 15}, exp: []byte{0x0, 0xf0, 0x0, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: -15}, exp: []byte{0x0, 0x10, 0x1f, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x10", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 16}, exp: []byte{0x0, 0x8, 0x0, 0xfd}}, - {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0xf", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 15}, exp: []byte{0x0, 0xf0, 0x0, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x11", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 17}, exp: []byte{0x0, 0x10, 0x1, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: -128}, exp: []byte{0x0, 0x0, 0x18, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0xffffffffffffff00", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: -256}, exp: []byte{0x0, 0x0, 0x10, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x50", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 80}, exp: []byte{0x0, 0x28, 0x0, 0xfd}}, - {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: -128}, exp: []byte{0x0, 0x0, 0x18, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0xff", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 255}, exp: []byte{0x0, 0xf0, 0xf, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x1000", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 4096}, exp: []byte{0x0, 0x0, 0x8, 0xfd}}, - {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x2000", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 8192}, exp: []byte{0x0, 0x0, 0x10, 0xfd}}, - {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x7ff8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 32760}, exp: []byte{0x0, 0xfc, 0x3f, 0xfd}}, - {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0xfff0", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 65520}, exp: []byte{0x1b, 0x20, 0x40, 0x91, 0x60, 0xfb, 0x3f, 0xfd}}, - {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0xffe8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 65512}, exp: []byte{0x1b, 0x20, 0x40, 0x91, 0x60, 0xf7, 0x3f, 0xfd}}, - {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0xffe0", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 65504}, exp: []byte{0x1b, 0x20, 0x40, 0x91, 0x60, 0xf3, 0x3f, 0xfd}}, - {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x8000000", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x40000000", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x40000008", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x3ffffff8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x40000010", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x3ffffff0", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x7ffffff8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x10000004", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xfc}}, - {name: "FSTRD/RegisterOffset/src=V0,base=R0,offset=RegR8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstReg2: RegR8}, exp: []byte{0x0, 0x68, 0x28, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0xffffffffffffffff", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: -1}, exp: []byte{0xc0, 0xf3, 0x1f, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x0", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 0}, exp: []byte{0xc0, 0x3, 0x0, 0xfd}}, - {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x1", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 1}, exp: []byte{0xc0, 0x13, 0x0, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x2", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 2}, exp: []byte{0xc0, 0x23, 0x0, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: -2}, exp: []byte{0xc0, 0xe3, 0x1f, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x4", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 4}, exp: []byte{0xc0, 0x43, 0x0, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: -4}, exp: []byte{0xc0, 0xc3, 0x1f, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0xf", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 15}, exp: []byte{0xc0, 0xf3, 0x0, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: -15}, exp: []byte{0xc0, 0x13, 0x1f, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x10", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 16}, exp: []byte{0xc0, 0xb, 0x0, 0xfd}}, - {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0xf", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 15}, exp: []byte{0xc0, 0xf3, 0x0, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x11", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 17}, exp: []byte{0xc0, 0x13, 0x1, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: -128}, exp: []byte{0xc0, 0x3, 0x18, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0xffffffffffffff00", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: -256}, exp: []byte{0xc0, 0x3, 0x10, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x50", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 80}, exp: []byte{0xc0, 0x2b, 0x0, 0xfd}}, - {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: -128}, exp: []byte{0xc0, 0x3, 0x18, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0xff", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 255}, exp: []byte{0xc0, 0xf3, 0xf, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x1000", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 4096}, exp: []byte{0xc0, 0x3, 0x8, 0xfd}}, - {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x2000", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 8192}, exp: []byte{0xc0, 0x3, 0x10, 0xfd}}, - {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x7ff8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 32760}, exp: []byte{0xc0, 0xff, 0x3f, 0xfd}}, - {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0xfff0", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 65520}, exp: []byte{0xdb, 0x23, 0x40, 0x91, 0x60, 0xfb, 0x3f, 0xfd}}, - {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0xffe8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 65512}, exp: []byte{0xdb, 0x23, 0x40, 0x91, 0x60, 0xf7, 0x3f, 0xfd}}, - {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0xffe0", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 65504}, exp: []byte{0xdb, 0x23, 0x40, 0x91, 0x60, 0xf3, 0x3f, 0xfd}}, - {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x8000000", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x40000000", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x40000008", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x3ffffff8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x40000010", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x3ffffff0", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x7ffffff8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x10000004", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xfc}}, - {name: "FSTRD/RegisterOffset/src=V0,base=R30,offset=RegR8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstReg2: RegR8}, exp: []byte{0xc0, 0x6b, 0x28, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0xffffffffffffffff", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: -1}, exp: []byte{0x1e, 0xf0, 0x1f, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x0", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 0}, exp: []byte{0x1e, 0x0, 0x0, 0xfd}}, - {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x1", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 1}, exp: []byte{0x1e, 0x10, 0x0, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x2", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 2}, exp: []byte{0x1e, 0x20, 0x0, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: -2}, exp: []byte{0x1e, 0xe0, 0x1f, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x4", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 4}, exp: []byte{0x1e, 0x40, 0x0, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: -4}, exp: []byte{0x1e, 0xc0, 0x1f, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0xf", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 15}, exp: []byte{0x1e, 0xf0, 0x0, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: -15}, exp: []byte{0x1e, 0x10, 0x1f, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x10", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 16}, exp: []byte{0x1e, 0x8, 0x0, 0xfd}}, - {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0xf", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 15}, exp: []byte{0x1e, 0xf0, 0x0, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x11", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 17}, exp: []byte{0x1e, 0x10, 0x1, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: -128}, exp: []byte{0x1e, 0x0, 0x18, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0xffffffffffffff00", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: -256}, exp: []byte{0x1e, 0x0, 0x10, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x50", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 80}, exp: []byte{0x1e, 0x28, 0x0, 0xfd}}, - {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: -128}, exp: []byte{0x1e, 0x0, 0x18, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0xff", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 255}, exp: []byte{0x1e, 0xf0, 0xf, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x1000", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 4096}, exp: []byte{0x1e, 0x0, 0x8, 0xfd}}, - {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x2000", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 8192}, exp: []byte{0x1e, 0x0, 0x10, 0xfd}}, - {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x7ff8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 32760}, exp: []byte{0x1e, 0xfc, 0x3f, 0xfd}}, - {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0xfff0", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 65520}, exp: []byte{0x1b, 0x20, 0x40, 0x91, 0x7e, 0xfb, 0x3f, 0xfd}}, - {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0xffe8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 65512}, exp: []byte{0x1b, 0x20, 0x40, 0x91, 0x7e, 0xf7, 0x3f, 0xfd}}, - {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0xffe0", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 65504}, exp: []byte{0x1b, 0x20, 0x40, 0x91, 0x7e, 0xf3, 0x3f, 0xfd}}, - {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x8000000", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x40000000", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x40000008", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x3ffffff8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x40000010", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x3ffffff0", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x7ffffff8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x10000004", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xfc}}, - {name: "FSTRD/RegisterOffset/src=V30,base=R0,offset=RegR8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstReg2: RegR8}, exp: []byte{0x1e, 0x68, 0x28, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0xffffffffffffffff", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: -1}, exp: []byte{0xde, 0xf3, 0x1f, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x0", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 0}, exp: []byte{0xde, 0x3, 0x0, 0xfd}}, - {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x1", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 1}, exp: []byte{0xde, 0x13, 0x0, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x2", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 2}, exp: []byte{0xde, 0x23, 0x0, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: -2}, exp: []byte{0xde, 0xe3, 0x1f, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x4", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 4}, exp: []byte{0xde, 0x43, 0x0, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: -4}, exp: []byte{0xde, 0xc3, 0x1f, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0xf", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 15}, exp: []byte{0xde, 0xf3, 0x0, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: -15}, exp: []byte{0xde, 0x13, 0x1f, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x10", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 16}, exp: []byte{0xde, 0xb, 0x0, 0xfd}}, - {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0xf", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 15}, exp: []byte{0xde, 0xf3, 0x0, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x11", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 17}, exp: []byte{0xde, 0x13, 0x1, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: -128}, exp: []byte{0xde, 0x3, 0x18, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0xffffffffffffff00", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: -256}, exp: []byte{0xde, 0x3, 0x10, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x50", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 80}, exp: []byte{0xde, 0x2b, 0x0, 0xfd}}, - {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: -128}, exp: []byte{0xde, 0x3, 0x18, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0xff", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 255}, exp: []byte{0xde, 0xf3, 0xf, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x1000", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 4096}, exp: []byte{0xde, 0x3, 0x8, 0xfd}}, - {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x2000", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 8192}, exp: []byte{0xde, 0x3, 0x10, 0xfd}}, - {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x7ff8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 32760}, exp: []byte{0xde, 0xff, 0x3f, 0xfd}}, - {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0xfff0", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 65520}, exp: []byte{0xdb, 0x23, 0x40, 0x91, 0x7e, 0xfb, 0x3f, 0xfd}}, - {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0xffe8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 65512}, exp: []byte{0xdb, 0x23, 0x40, 0x91, 0x7e, 0xf7, 0x3f, 0xfd}}, - {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0xffe0", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 65504}, exp: []byte{0xdb, 0x23, 0x40, 0x91, 0x7e, 0xf3, 0x3f, 0xfd}}, - {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x8000000", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x40000000", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x40000008", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x3ffffff8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x40000010", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x3ffffff0", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x7ffffff8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xfc}}, - {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x10000004", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xfc}}, - {name: "FSTRD/RegisterOffset/src=V30,base=R30,offset=RegR8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstReg2: RegR8}, exp: []byte{0xde, 0x6b, 0x28, 0xfc}}, - {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0xffffffffffffffff", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: -1}, exp: []byte{0x0, 0xf0, 0x1f, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x0", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 0}, exp: []byte{0x0, 0x0, 0x0, 0xbd}}, - {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x1", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 1}, exp: []byte{0x0, 0x10, 0x0, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x2", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 2}, exp: []byte{0x0, 0x20, 0x0, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: -2}, exp: []byte{0x0, 0xe0, 0x1f, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x4", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 4}, exp: []byte{0x0, 0x4, 0x0, 0xbd}}, - {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: -4}, exp: []byte{0x0, 0xc0, 0x1f, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0xf", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 15}, exp: []byte{0x0, 0xf0, 0x0, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: -15}, exp: []byte{0x0, 0x10, 0x1f, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x10", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 16}, exp: []byte{0x0, 0x10, 0x0, 0xbd}}, - {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0xf", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 15}, exp: []byte{0x0, 0xf0, 0x0, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x11", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 17}, exp: []byte{0x0, 0x10, 0x1, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: -128}, exp: []byte{0x0, 0x0, 0x18, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0xffffffffffffff00", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: -256}, exp: []byte{0x0, 0x0, 0x10, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x50", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 80}, exp: []byte{0x0, 0x50, 0x0, 0xbd}}, - {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: -128}, exp: []byte{0x0, 0x0, 0x18, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0xff", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 255}, exp: []byte{0x0, 0xf0, 0xf, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x1000", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 4096}, exp: []byte{0x0, 0x0, 0x10, 0xbd}}, - {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x2000", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 8192}, exp: []byte{0x0, 0x0, 0x20, 0xbd}}, - {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x7ff8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 32760}, exp: []byte{0x1b, 0x10, 0x40, 0x91, 0x60, 0xfb, 0x3f, 0xbd}}, - {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0xfff0", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 65520}, exp: []byte{0x1b, 0x30, 0x40, 0x91, 0x60, 0xf3, 0x3f, 0xbd}}, - {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0xffe8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 65512}, exp: []byte{0x1b, 0x30, 0x40, 0x91, 0x60, 0xeb, 0x3f, 0xbd}}, - {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0xffe0", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 65504}, exp: []byte{0x1b, 0x30, 0x40, 0x91, 0x60, 0xe3, 0x3f, 0xbd}}, - {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x8000000", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x40000000", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x40000008", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x3ffffff8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x40000010", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x3ffffff0", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x7ffffff8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x10000004", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xbc}}, - {name: "FSTRS/RegisterOffset/src=V0,base=R0,offset=RegR8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstReg2: RegR8}, exp: []byte{0x0, 0x68, 0x28, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0xffffffffffffffff", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: -1}, exp: []byte{0xc0, 0xf3, 0x1f, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x0", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 0}, exp: []byte{0xc0, 0x3, 0x0, 0xbd}}, - {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x1", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 1}, exp: []byte{0xc0, 0x13, 0x0, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x2", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 2}, exp: []byte{0xc0, 0x23, 0x0, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: -2}, exp: []byte{0xc0, 0xe3, 0x1f, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x4", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 4}, exp: []byte{0xc0, 0x7, 0x0, 0xbd}}, - {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: -4}, exp: []byte{0xc0, 0xc3, 0x1f, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0xf", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 15}, exp: []byte{0xc0, 0xf3, 0x0, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: -15}, exp: []byte{0xc0, 0x13, 0x1f, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x10", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 16}, exp: []byte{0xc0, 0x13, 0x0, 0xbd}}, - {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0xf", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 15}, exp: []byte{0xc0, 0xf3, 0x0, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x11", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 17}, exp: []byte{0xc0, 0x13, 0x1, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: -128}, exp: []byte{0xc0, 0x3, 0x18, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0xffffffffffffff00", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: -256}, exp: []byte{0xc0, 0x3, 0x10, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x50", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 80}, exp: []byte{0xc0, 0x53, 0x0, 0xbd}}, - {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: -128}, exp: []byte{0xc0, 0x3, 0x18, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0xff", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 255}, exp: []byte{0xc0, 0xf3, 0xf, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x1000", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 4096}, exp: []byte{0xc0, 0x3, 0x10, 0xbd}}, - {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x2000", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 8192}, exp: []byte{0xc0, 0x3, 0x20, 0xbd}}, - {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x7ff8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 32760}, exp: []byte{0xdb, 0x13, 0x40, 0x91, 0x60, 0xfb, 0x3f, 0xbd}}, - {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0xfff0", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 65520}, exp: []byte{0xdb, 0x33, 0x40, 0x91, 0x60, 0xf3, 0x3f, 0xbd}}, - {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0xffe8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 65512}, exp: []byte{0xdb, 0x33, 0x40, 0x91, 0x60, 0xeb, 0x3f, 0xbd}}, - {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0xffe0", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 65504}, exp: []byte{0xdb, 0x33, 0x40, 0x91, 0x60, 0xe3, 0x3f, 0xbd}}, - {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x8000000", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x40000000", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x40000008", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x3ffffff8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x40000010", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x3ffffff0", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x7ffffff8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x10000004", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xbc}}, - {name: "FSTRS/RegisterOffset/src=V0,base=R30,offset=RegR8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstReg2: RegR8}, exp: []byte{0xc0, 0x6b, 0x28, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0xffffffffffffffff", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: -1}, exp: []byte{0x1e, 0xf0, 0x1f, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x0", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 0}, exp: []byte{0x1e, 0x0, 0x0, 0xbd}}, - {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x1", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 1}, exp: []byte{0x1e, 0x10, 0x0, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x2", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 2}, exp: []byte{0x1e, 0x20, 0x0, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: -2}, exp: []byte{0x1e, 0xe0, 0x1f, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x4", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 4}, exp: []byte{0x1e, 0x4, 0x0, 0xbd}}, - {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: -4}, exp: []byte{0x1e, 0xc0, 0x1f, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0xf", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 15}, exp: []byte{0x1e, 0xf0, 0x0, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: -15}, exp: []byte{0x1e, 0x10, 0x1f, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x10", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 16}, exp: []byte{0x1e, 0x10, 0x0, 0xbd}}, - {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0xf", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 15}, exp: []byte{0x1e, 0xf0, 0x0, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x11", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 17}, exp: []byte{0x1e, 0x10, 0x1, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: -128}, exp: []byte{0x1e, 0x0, 0x18, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0xffffffffffffff00", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: -256}, exp: []byte{0x1e, 0x0, 0x10, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x50", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 80}, exp: []byte{0x1e, 0x50, 0x0, 0xbd}}, - {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: -128}, exp: []byte{0x1e, 0x0, 0x18, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0xff", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 255}, exp: []byte{0x1e, 0xf0, 0xf, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x1000", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 4096}, exp: []byte{0x1e, 0x0, 0x10, 0xbd}}, - {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x2000", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 8192}, exp: []byte{0x1e, 0x0, 0x20, 0xbd}}, - {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x7ff8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 32760}, exp: []byte{0x1b, 0x10, 0x40, 0x91, 0x7e, 0xfb, 0x3f, 0xbd}}, - {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0xfff0", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 65520}, exp: []byte{0x1b, 0x30, 0x40, 0x91, 0x7e, 0xf3, 0x3f, 0xbd}}, - {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0xffe8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 65512}, exp: []byte{0x1b, 0x30, 0x40, 0x91, 0x7e, 0xeb, 0x3f, 0xbd}}, - {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0xffe0", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 65504}, exp: []byte{0x1b, 0x30, 0x40, 0x91, 0x7e, 0xe3, 0x3f, 0xbd}}, - {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x8000000", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x40000000", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x40000008", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x3ffffff8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x40000010", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x3ffffff0", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x7ffffff8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x10000004", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xbc}}, - {name: "FSTRS/RegisterOffset/src=V30,base=R0,offset=RegR8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstReg2: RegR8}, exp: []byte{0x1e, 0x68, 0x28, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0xffffffffffffffff", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: -1}, exp: []byte{0xde, 0xf3, 0x1f, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x0", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 0}, exp: []byte{0xde, 0x3, 0x0, 0xbd}}, - {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x1", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 1}, exp: []byte{0xde, 0x13, 0x0, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x2", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 2}, exp: []byte{0xde, 0x23, 0x0, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: -2}, exp: []byte{0xde, 0xe3, 0x1f, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x4", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 4}, exp: []byte{0xde, 0x7, 0x0, 0xbd}}, - {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: -4}, exp: []byte{0xde, 0xc3, 0x1f, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0xf", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 15}, exp: []byte{0xde, 0xf3, 0x0, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: -15}, exp: []byte{0xde, 0x13, 0x1f, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x10", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 16}, exp: []byte{0xde, 0x13, 0x0, 0xbd}}, - {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0xf", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 15}, exp: []byte{0xde, 0xf3, 0x0, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x11", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 17}, exp: []byte{0xde, 0x13, 0x1, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: -128}, exp: []byte{0xde, 0x3, 0x18, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0xffffffffffffff00", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: -256}, exp: []byte{0xde, 0x3, 0x10, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x50", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 80}, exp: []byte{0xde, 0x53, 0x0, 0xbd}}, - {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: -128}, exp: []byte{0xde, 0x3, 0x18, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0xff", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 255}, exp: []byte{0xde, 0xf3, 0xf, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x1000", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 4096}, exp: []byte{0xde, 0x3, 0x10, 0xbd}}, - {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x2000", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 8192}, exp: []byte{0xde, 0x3, 0x20, 0xbd}}, - {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x7ff8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 32760}, exp: []byte{0xdb, 0x13, 0x40, 0x91, 0x7e, 0xfb, 0x3f, 0xbd}}, - {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0xfff0", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 65520}, exp: []byte{0xdb, 0x33, 0x40, 0x91, 0x7e, 0xf3, 0x3f, 0xbd}}, - {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0xffe8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 65512}, exp: []byte{0xdb, 0x33, 0x40, 0x91, 0x7e, 0xeb, 0x3f, 0xbd}}, - {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0xffe0", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 65504}, exp: []byte{0xdb, 0x33, 0x40, 0x91, 0x7e, 0xe3, 0x3f, 0xbd}}, - {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x8000000", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x40000000", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x40000008", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x3ffffff8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x40000010", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x3ffffff0", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x7ffffff8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xbc}}, - {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x10000004", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xbc}}, - {name: "FSTRS/RegisterOffset/src=V30,base=R30,offset=RegR8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstReg2: RegR8}, exp: []byte{0xde, 0x6b, 0x28, 0xbc}}, - {name: "stlr x0, [x0]", n: &nodeImpl{instruction: STLRD, srcReg: RegR0, dstReg: RegR0}, exp: []byte{0x0, 0xfc, 0x9f, 0xc8}}, - {name: "stlr x0, [x30]", n: &nodeImpl{instruction: STLRD, srcReg: RegR0, dstReg: RegR30}, exp: []byte{0xc0, 0xff, 0x9f, 0xc8}}, - {name: "stlr x30, [x0]", n: &nodeImpl{instruction: STLRD, srcReg: RegR30, dstReg: RegR0}, exp: []byte{0x1e, 0xfc, 0x9f, 0xc8}}, - {name: "stlr x30, [x30]", n: &nodeImpl{instruction: STLRD, srcReg: RegR30, dstReg: RegR30}, exp: []byte{0xde, 0xff, 0x9f, 0xc8}}, - {name: "stlr w0, [x0]", n: &nodeImpl{instruction: STLRW, srcReg: RegR0, dstReg: RegR0}, exp: []byte{0x0, 0xfc, 0x9f, 0x88}}, - {name: "stlr w0, [x30]", n: &nodeImpl{instruction: STLRW, srcReg: RegR0, dstReg: RegR30}, exp: []byte{0xc0, 0xff, 0x9f, 0x88}}, - {name: "stlr w30, [x0]", n: &nodeImpl{instruction: STLRW, srcReg: RegR30, dstReg: RegR0}, exp: []byte{0x1e, 0xfc, 0x9f, 0x88}}, - {name: "stlr w30, [x30]", n: &nodeImpl{instruction: STLRW, srcReg: RegR30, dstReg: RegR30}, exp: []byte{0xde, 0xff, 0x9f, 0x88}}, - {name: "stlrh w0, [x0]", n: &nodeImpl{instruction: STLRH, srcReg: RegR0, dstReg: RegR0}, exp: []byte{0x0, 0xfc, 0x9f, 0x48}}, - {name: "stlrh w0, [x30]", n: &nodeImpl{instruction: STLRH, srcReg: RegR0, dstReg: RegR30}, exp: []byte{0xc0, 0xff, 0x9f, 0x48}}, - {name: "stlrh w30, [x0]", n: &nodeImpl{instruction: STLRH, srcReg: RegR30, dstReg: RegR0}, exp: []byte{0x1e, 0xfc, 0x9f, 0x48}}, - {name: "stlrh w30, [x30]", n: &nodeImpl{instruction: STLRH, srcReg: RegR30, dstReg: RegR30}, exp: []byte{0xde, 0xff, 0x9f, 0x48}}, - {name: "stlrb w0, [x0]", n: &nodeImpl{instruction: STLRB, srcReg: RegR0, dstReg: RegR0}, exp: []byte{0x0, 0xfc, 0x9f, 0x8}}, - {name: "stlrb w0, [x30]", n: &nodeImpl{instruction: STLRB, srcReg: RegR0, dstReg: RegR30}, exp: []byte{0xc0, 0xff, 0x9f, 0x8}}, - {name: "stlrb w30, [x0]", n: &nodeImpl{instruction: STLRB, srcReg: RegR30, dstReg: RegR0}, exp: []byte{0x1e, 0xfc, 0x9f, 0x8}}, - {name: "stlrb w30, [x30]", n: &nodeImpl{instruction: STLRB, srcReg: RegR30, dstReg: RegR30}, exp: []byte{0xde, 0xff, 0x9f, 0x8}}, - } - - for _, tc := range tests { - t.Run(tc.name, func(t *testing.T) { - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - a := NewAssembler(RegR27) - tc.n.types = operandTypesRegisterToMemory - - buf := code.NextCodeSection() - err := a.encodeRegisterToMemory(buf, tc.n) - require.NoError(t, err) - - err = a.Assemble(buf) - require.NoError(t, err) - - actual := buf.Bytes() - require.Equal(t, tc.exp, actual) - }) - } -} diff --git a/internal/asm/arm64/impl_6_test.go b/internal/asm/arm64/impl_6_test.go deleted file mode 100644 index 3157af101a..0000000000 --- a/internal/asm/arm64/impl_6_test.go +++ /dev/null @@ -1,414 +0,0 @@ -package arm64 - -import ( - "encoding/hex" - "fmt" - "testing" - - "github.com/tetratelabs/wazero/internal/asm" - "github.com/tetratelabs/wazero/internal/testing/require" -) - -func TestAssemblerImpl_EncodeRelativeJump(t *testing.T) { - // We only test positive limits, since the negative limits require a reverse branch. - // Testing reverse branches would require many megabytes in the code section, making - // the test unwieldy. - t.Run("offset limits", func(t *testing.T) { - tests := []struct { - name string - inst asm.Instruction - offset uint64 - }{ - { - name: "B maxSignedInt26*4", - inst: B, - offset: uint64(maxSignedInt26 * 4), - }, - { - name: "BCONDEQ maxSignedInt19*4", - inst: BCONDEQ, - offset: uint64(maxSignedInt19 * 4), - }, - } - - for _, tt := range tests { - tc := tt - t.Run(tc.name, func(t *testing.T) { - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - a := NewAssembler(asm.NilRegister) - n := &nodeImpl{instruction: tc.inst, types: operandTypesNoneToBranch, offsetInBinary: 0, jumpTarget: &nodeImpl{offsetInBinary: tc.offset}} - - buf := code.NextCodeSection() - err := a.encodeRelativeBranch(buf, n) - require.NoError(t, err) - - err = a.Assemble(buf) - require.NoError(t, err) - }) - } - }) - - t.Run("error", func(t *testing.T) { - tests := []struct { - n *nodeImpl - expErr string - }{ - { - n: &nodeImpl{instruction: B, types: operandTypesNoneToBranch}, - expErr: "branch target must be set for B", - }, - { - n: &nodeImpl{instruction: SUB, types: operandTypesNoneToBranch}, - expErr: "SUB is unsupported for NoneToBranch type", - }, - { - n: &nodeImpl{instruction: B, types: operandTypesNoneToBranch, offsetInBinary: 0, jumpTarget: &nodeImpl{offsetInBinary: uint64(maxSignedInt26)*4 + 4}}, - expErr: fmt.Sprintf("relative jump offset %d/4 must be within %d and %d", maxSignedInt26*4+4, minSignedInt26, maxSignedInt26), - }, - { - n: &nodeImpl{instruction: BCONDEQ, types: operandTypesNoneToBranch, offsetInBinary: 0, jumpTarget: &nodeImpl{offsetInBinary: uint64(maxSignedInt19)*4 + 4}}, - expErr: fmt.Sprintf("BUG: relative jump offset %d/4(=%d) must be within %d and %d", maxSignedInt19*4+4, maxSignedInt19+1, minSignedInt19, maxSignedInt19), - }, - } - - for _, tt := range tests { - tc := tt - t.Run(tc.expErr, func(t *testing.T) { - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - a := NewAssembler(asm.NilRegister) - - buf := code.NextCodeSection() - err := a.encodeRelativeBranch(buf, tc.n) - if err != nil { - require.EqualError(t, err, tc.expErr) - } else { - err = a.Assemble(buf) - require.EqualError(t, err, tc.expErr) - } - }) - } - }) - - tests := []struct { - name string - expHex string - instructionsInPreamble int - instructionsBeforeBranch int - instructionsAfterBranch int - inst asm.Instruction - forward bool - }{ - {name: "B/forward=true(before=0,after=10)", inst: B, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 0, instructionsAfterBranch: 10, expHex: "0b0000140a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "B/forward=true(before=10,after=10)", inst: B, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 10, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20b0000140a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "B/forward=true(before=10,after=10)", inst: B, forward: true, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20b0000140a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "B/foward=false(before=0,after=0)", inst: B, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 0, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d200000014"}, - {name: "B/foward=false(before=10,after=0)", inst: B, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2f6ffff17"}, - {name: "B/foward=false(before=10,after=10)", inst: B, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2f6ffff170a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "B/forward=true(before=0,after=100)", inst: B, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 0, instructionsAfterBranch: 100, expHex: "650000140a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "B/forward=true(before=100,after=10)", inst: B, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 100, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20b0000140a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "B/forward=true(before=100,after=100)", inst: B, forward: true, instructionsInPreamble: 123, instructionsBeforeBranch: 100, instructionsAfterBranch: 100, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2650000140a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "B/foward=false(before=0,after=0)", inst: B, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 0, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d200000014"}, - {name: "B/foward=false(before=100,after=0)", inst: B, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 100, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d29cffff17"}, - {name: "B/foward=false(before=10,after=100)", inst: B, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 100, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2f6ffff170a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "B/forward=true(before=0,after=1234)", inst: B, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 0, instructionsAfterBranch: 1234, expHex: "d30400140a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "B/forward=true(before=1234,after=124)", inst: B, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 1234, instructionsAfterBranch: 124, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d27d0000140a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "B/forward=true(before=14,after=1234)", inst: B, forward: true, instructionsInPreamble: 123, instructionsBeforeBranch: 14, instructionsAfterBranch: 1234, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2d30400140a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "B/foward=false(before=0,after=0)", inst: B, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 0, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d200000014"}, - {name: "B/foward=false(before=123,after=0)", inst: B, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 123, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d285ffff17"}, - {name: "B/foward=false(before=10,after=123)", inst: B, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 123, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2f6ffff170a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDEQ/forward=true(before=0,after=10)", inst: BCONDEQ, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 0, instructionsAfterBranch: 10, expHex: "600100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDEQ/forward=true(before=10,after=10)", inst: BCONDEQ, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 10, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2600100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDEQ/forward=true(before=10,after=10)", inst: BCONDEQ, forward: true, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2600100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDEQ/foward=false(before=0,after=0)", inst: BCONDEQ, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 0, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d200000054"}, - {name: "BCONDEQ/foward=false(before=10,after=0)", inst: BCONDEQ, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2c0feff54"}, - {name: "BCONDEQ/foward=false(before=10,after=10)", inst: BCONDEQ, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2c0feff540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDEQ/forward=true(before=0,after=100)", inst: BCONDEQ, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 0, instructionsAfterBranch: 100, expHex: "a00c00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDEQ/forward=true(before=100,after=10)", inst: BCONDEQ, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 100, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2600100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDEQ/forward=true(before=100,after=100)", inst: BCONDEQ, forward: true, instructionsInPreamble: 123, instructionsBeforeBranch: 100, instructionsAfterBranch: 100, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2a00c00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDEQ/foward=false(before=0,after=0)", inst: BCONDEQ, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 0, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d200000054"}, - {name: "BCONDEQ/foward=false(before=100,after=0)", inst: BCONDEQ, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 100, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d280f3ff54"}, - {name: "BCONDEQ/foward=false(before=10,after=100)", inst: BCONDEQ, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 100, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2c0feff540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDEQ/forward=true(before=0,after=1234)", inst: BCONDEQ, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 0, instructionsAfterBranch: 1234, expHex: "609a00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDEQ/forward=true(before=1234,after=124)", inst: BCONDEQ, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 1234, instructionsAfterBranch: 124, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2a00f00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDEQ/forward=true(before=14,after=1234)", inst: BCONDEQ, forward: true, instructionsInPreamble: 123, instructionsBeforeBranch: 14, instructionsAfterBranch: 1234, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2609a00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDEQ/foward=false(before=0,after=0)", inst: BCONDEQ, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 0, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d200000054"}, - {name: "BCONDEQ/foward=false(before=123,after=0)", inst: BCONDEQ, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 123, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2a0f0ff54"}, - {name: "BCONDEQ/foward=false(before=10,after=123)", inst: BCONDEQ, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 123, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2c0feff540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDGE/forward=true(before=0,after=10)", inst: BCONDGE, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 0, instructionsAfterBranch: 10, expHex: "6a0100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDGE/forward=true(before=10,after=10)", inst: BCONDGE, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 10, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d26a0100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDGE/forward=true(before=10,after=10)", inst: BCONDGE, forward: true, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d26a0100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDGE/foward=false(before=0,after=0)", inst: BCONDGE, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 0, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a000054"}, - {name: "BCONDGE/foward=false(before=10,after=0)", inst: BCONDGE, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2cafeff54"}, - {name: "BCONDGE/foward=false(before=10,after=10)", inst: BCONDGE, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2cafeff540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDGE/forward=true(before=0,after=100)", inst: BCONDGE, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 0, instructionsAfterBranch: 100, expHex: "aa0c00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDGE/forward=true(before=100,after=10)", inst: BCONDGE, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 100, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d26a0100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDGE/forward=true(before=100,after=100)", inst: BCONDGE, forward: true, instructionsInPreamble: 123, instructionsBeforeBranch: 100, instructionsAfterBranch: 100, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2aa0c00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDGE/foward=false(before=0,after=0)", inst: BCONDGE, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 0, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a000054"}, - {name: "BCONDGE/foward=false(before=100,after=0)", inst: BCONDGE, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 100, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d28af3ff54"}, - {name: "BCONDGE/foward=false(before=10,after=100)", inst: BCONDGE, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 100, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2cafeff540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDGE/forward=true(before=0,after=1234)", inst: BCONDGE, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 0, instructionsAfterBranch: 1234, expHex: "6a9a00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDGE/forward=true(before=1234,after=124)", inst: BCONDGE, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 1234, instructionsAfterBranch: 124, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2aa0f00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDGE/forward=true(before=14,after=1234)", inst: BCONDGE, forward: true, instructionsInPreamble: 123, instructionsBeforeBranch: 14, instructionsAfterBranch: 1234, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d26a9a00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDGE/foward=false(before=0,after=0)", inst: BCONDGE, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 0, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a000054"}, - {name: "BCONDGE/foward=false(before=123,after=0)", inst: BCONDGE, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 123, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2aaf0ff54"}, - {name: "BCONDGE/foward=false(before=10,after=123)", inst: BCONDGE, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 123, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2cafeff540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDGT/forward=true(before=0,after=10)", inst: BCONDGT, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 0, instructionsAfterBranch: 10, expHex: "6c0100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDGT/forward=true(before=10,after=10)", inst: BCONDGT, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 10, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d26c0100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDGT/forward=true(before=10,after=10)", inst: BCONDGT, forward: true, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d26c0100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDGT/foward=false(before=0,after=0)", inst: BCONDGT, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 0, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20c000054"}, - {name: "BCONDGT/foward=false(before=10,after=0)", inst: BCONDGT, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2ccfeff54"}, - {name: "BCONDGT/foward=false(before=10,after=10)", inst: BCONDGT, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2ccfeff540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDGT/forward=true(before=0,after=100)", inst: BCONDGT, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 0, instructionsAfterBranch: 100, expHex: "ac0c00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDGT/forward=true(before=100,after=10)", inst: BCONDGT, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 100, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d26c0100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDGT/forward=true(before=100,after=100)", inst: BCONDGT, forward: true, instructionsInPreamble: 123, instructionsBeforeBranch: 100, instructionsAfterBranch: 100, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2ac0c00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDGT/foward=false(before=0,after=0)", inst: BCONDGT, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 0, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20c000054"}, - {name: "BCONDGT/foward=false(before=100,after=0)", inst: BCONDGT, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 100, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d28cf3ff54"}, - {name: "BCONDGT/foward=false(before=10,after=100)", inst: BCONDGT, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 100, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2ccfeff540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDGT/forward=true(before=0,after=1234)", inst: BCONDGT, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 0, instructionsAfterBranch: 1234, expHex: "6c9a00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDGT/forward=true(before=1234,after=124)", inst: BCONDGT, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 1234, instructionsAfterBranch: 124, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2ac0f00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDGT/forward=true(before=14,after=1234)", inst: BCONDGT, forward: true, instructionsInPreamble: 123, instructionsBeforeBranch: 14, instructionsAfterBranch: 1234, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d26c9a00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDGT/foward=false(before=0,after=0)", inst: BCONDGT, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 0, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20c000054"}, - {name: "BCONDGT/foward=false(before=123,after=0)", inst: BCONDGT, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 123, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2acf0ff54"}, - {name: "BCONDGT/foward=false(before=10,after=123)", inst: BCONDGT, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 123, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2ccfeff540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDHI/forward=true(before=0,after=10)", inst: BCONDHI, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 0, instructionsAfterBranch: 10, expHex: "680100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDHI/forward=true(before=10,after=10)", inst: BCONDHI, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 10, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2680100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDHI/forward=true(before=10,after=10)", inst: BCONDHI, forward: true, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2680100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDHI/foward=false(before=0,after=0)", inst: BCONDHI, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 0, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d208000054"}, - {name: "BCONDHI/foward=false(before=10,after=0)", inst: BCONDHI, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2c8feff54"}, - {name: "BCONDHI/foward=false(before=10,after=10)", inst: BCONDHI, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2c8feff540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDHI/forward=true(before=0,after=100)", inst: BCONDHI, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 0, instructionsAfterBranch: 100, expHex: "a80c00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDHI/forward=true(before=100,after=10)", inst: BCONDHI, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 100, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2680100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDHI/forward=true(before=100,after=100)", inst: BCONDHI, forward: true, instructionsInPreamble: 123, instructionsBeforeBranch: 100, instructionsAfterBranch: 100, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2a80c00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDHI/foward=false(before=0,after=0)", inst: BCONDHI, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 0, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d208000054"}, - {name: "BCONDHI/foward=false(before=100,after=0)", inst: BCONDHI, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 100, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d288f3ff54"}, - {name: "BCONDHI/foward=false(before=10,after=100)", inst: BCONDHI, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 100, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2c8feff540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDHI/forward=true(before=0,after=1234)", inst: BCONDHI, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 0, instructionsAfterBranch: 1234, expHex: "689a00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDHI/forward=true(before=1234,after=124)", inst: BCONDHI, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 1234, instructionsAfterBranch: 124, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2a80f00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDHI/forward=true(before=14,after=1234)", inst: BCONDHI, forward: true, instructionsInPreamble: 123, instructionsBeforeBranch: 14, instructionsAfterBranch: 1234, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2689a00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDHI/foward=false(before=0,after=0)", inst: BCONDHI, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 0, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d208000054"}, - {name: "BCONDHI/foward=false(before=123,after=0)", inst: BCONDHI, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 123, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2a8f0ff54"}, - {name: "BCONDHI/foward=false(before=10,after=123)", inst: BCONDHI, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 123, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2c8feff540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDHS/forward=true(before=0,after=10)", inst: BCONDHS, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 0, instructionsAfterBranch: 10, expHex: "620100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDHS/forward=true(before=10,after=10)", inst: BCONDHS, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 10, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2620100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDHS/forward=true(before=10,after=10)", inst: BCONDHS, forward: true, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2620100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDHS/foward=false(before=0,after=0)", inst: BCONDHS, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 0, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d202000054"}, - {name: "BCONDHS/foward=false(before=10,after=0)", inst: BCONDHS, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2c2feff54"}, - {name: "BCONDHS/foward=false(before=10,after=10)", inst: BCONDHS, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2c2feff540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDHS/forward=true(before=0,after=100)", inst: BCONDHS, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 0, instructionsAfterBranch: 100, expHex: "a20c00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDHS/forward=true(before=100,after=10)", inst: BCONDHS, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 100, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2620100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDHS/forward=true(before=100,after=100)", inst: BCONDHS, forward: true, instructionsInPreamble: 123, instructionsBeforeBranch: 100, instructionsAfterBranch: 100, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2a20c00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDHS/foward=false(before=0,after=0)", inst: BCONDHS, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 0, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d202000054"}, - {name: "BCONDHS/foward=false(before=100,after=0)", inst: BCONDHS, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 100, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d282f3ff54"}, - {name: "BCONDHS/foward=false(before=10,after=100)", inst: BCONDHS, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 100, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2c2feff540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDHS/forward=true(before=0,after=1234)", inst: BCONDHS, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 0, instructionsAfterBranch: 1234, expHex: "629a00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDHS/forward=true(before=1234,after=124)", inst: BCONDHS, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 1234, instructionsAfterBranch: 124, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2a20f00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDHS/forward=true(before=14,after=1234)", inst: BCONDHS, forward: true, instructionsInPreamble: 123, instructionsBeforeBranch: 14, instructionsAfterBranch: 1234, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2629a00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDHS/foward=false(before=0,after=0)", inst: BCONDHS, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 0, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d202000054"}, - {name: "BCONDHS/foward=false(before=123,after=0)", inst: BCONDHS, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 123, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2a2f0ff54"}, - {name: "BCONDHS/foward=false(before=10,after=123)", inst: BCONDHS, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 123, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2c2feff540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDLE/forward=true(before=0,after=10)", inst: BCONDLE, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 0, instructionsAfterBranch: 10, expHex: "6d0100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDLE/forward=true(before=10,after=10)", inst: BCONDLE, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 10, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d26d0100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDLE/forward=true(before=10,after=10)", inst: BCONDLE, forward: true, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d26d0100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDLE/foward=false(before=0,after=0)", inst: BCONDLE, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 0, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20d000054"}, - {name: "BCONDLE/foward=false(before=10,after=0)", inst: BCONDLE, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2cdfeff54"}, - {name: "BCONDLE/foward=false(before=10,after=10)", inst: BCONDLE, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2cdfeff540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDLE/forward=true(before=0,after=100)", inst: BCONDLE, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 0, instructionsAfterBranch: 100, expHex: "ad0c00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDLE/forward=true(before=100,after=10)", inst: BCONDLE, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 100, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d26d0100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDLE/forward=true(before=100,after=100)", inst: BCONDLE, forward: true, instructionsInPreamble: 123, instructionsBeforeBranch: 100, instructionsAfterBranch: 100, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2ad0c00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDLE/foward=false(before=0,after=0)", inst: BCONDLE, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 0, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20d000054"}, - {name: "BCONDLE/foward=false(before=100,after=0)", inst: BCONDLE, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 100, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d28df3ff54"}, - {name: "BCONDLE/foward=false(before=10,after=100)", inst: BCONDLE, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 100, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2cdfeff540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDLE/forward=true(before=0,after=1234)", inst: BCONDLE, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 0, instructionsAfterBranch: 1234, expHex: "6d9a00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDLE/forward=true(before=1234,after=124)", inst: BCONDLE, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 1234, instructionsAfterBranch: 124, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2ad0f00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDLE/forward=true(before=14,after=1234)", inst: BCONDLE, forward: true, instructionsInPreamble: 123, instructionsBeforeBranch: 14, instructionsAfterBranch: 1234, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d26d9a00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDLE/foward=false(before=0,after=0)", inst: BCONDLE, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 0, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20d000054"}, - {name: "BCONDLE/foward=false(before=123,after=0)", inst: BCONDLE, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 123, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2adf0ff54"}, - {name: "BCONDLE/foward=false(before=10,after=123)", inst: BCONDLE, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 123, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2cdfeff540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDLO/forward=true(before=0,after=10)", inst: BCONDLO, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 0, instructionsAfterBranch: 10, expHex: "630100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDLO/forward=true(before=10,after=10)", inst: BCONDLO, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 10, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2630100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDLO/forward=true(before=10,after=10)", inst: BCONDLO, forward: true, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2630100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDLO/foward=false(before=0,after=0)", inst: BCONDLO, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 0, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d203000054"}, - {name: "BCONDLO/foward=false(before=10,after=0)", inst: BCONDLO, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2c3feff54"}, - {name: "BCONDLO/foward=false(before=10,after=10)", inst: BCONDLO, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2c3feff540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDLO/forward=true(before=0,after=100)", inst: BCONDLO, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 0, instructionsAfterBranch: 100, expHex: "a30c00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDLO/forward=true(before=100,after=10)", inst: BCONDLO, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 100, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2630100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDLO/forward=true(before=100,after=100)", inst: BCONDLO, forward: true, instructionsInPreamble: 123, instructionsBeforeBranch: 100, instructionsAfterBranch: 100, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2a30c00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDLO/foward=false(before=0,after=0)", inst: BCONDLO, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 0, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d203000054"}, - {name: "BCONDLO/foward=false(before=100,after=0)", inst: BCONDLO, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 100, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d283f3ff54"}, - {name: "BCONDLO/foward=false(before=10,after=100)", inst: BCONDLO, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 100, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2c3feff540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDLO/forward=true(before=0,after=1234)", inst: BCONDLO, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 0, instructionsAfterBranch: 1234, expHex: "639a00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDLO/forward=true(before=1234,after=124)", inst: BCONDLO, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 1234, instructionsAfterBranch: 124, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2a30f00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDLO/forward=true(before=14,after=1234)", inst: BCONDLO, forward: true, instructionsInPreamble: 123, instructionsBeforeBranch: 14, instructionsAfterBranch: 1234, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2639a00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDLO/foward=false(before=0,after=0)", inst: BCONDLO, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 0, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d203000054"}, - {name: "BCONDLO/foward=false(before=123,after=0)", inst: BCONDLO, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 123, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2a3f0ff54"}, - {name: "BCONDLO/foward=false(before=10,after=123)", inst: BCONDLO, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 123, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2c3feff540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDLS/forward=true(before=0,after=10)", inst: BCONDLS, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 0, instructionsAfterBranch: 10, expHex: "690100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDLS/forward=true(before=10,after=10)", inst: BCONDLS, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 10, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2690100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDLS/forward=true(before=10,after=10)", inst: BCONDLS, forward: true, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2690100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDLS/foward=false(before=0,after=0)", inst: BCONDLS, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 0, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d209000054"}, - {name: "BCONDLS/foward=false(before=10,after=0)", inst: BCONDLS, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2c9feff54"}, - {name: "BCONDLS/foward=false(before=10,after=10)", inst: BCONDLS, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2c9feff540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDLS/forward=true(before=0,after=100)", inst: BCONDLS, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 0, instructionsAfterBranch: 100, expHex: "a90c00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDLS/forward=true(before=100,after=10)", inst: BCONDLS, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 100, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2690100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDLS/forward=true(before=100,after=100)", inst: BCONDLS, forward: true, instructionsInPreamble: 123, instructionsBeforeBranch: 100, instructionsAfterBranch: 100, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2a90c00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDLS/foward=false(before=0,after=0)", inst: BCONDLS, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 0, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d209000054"}, - {name: "BCONDLS/foward=false(before=100,after=0)", inst: BCONDLS, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 100, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d289f3ff54"}, - {name: "BCONDLS/foward=false(before=10,after=100)", inst: BCONDLS, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 100, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2c9feff540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDLS/forward=true(before=0,after=1234)", inst: BCONDLS, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 0, instructionsAfterBranch: 1234, expHex: "699a00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDLS/forward=true(before=1234,after=124)", inst: BCONDLS, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 1234, instructionsAfterBranch: 124, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2a90f00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDLS/forward=true(before=14,after=1234)", inst: BCONDLS, forward: true, instructionsInPreamble: 123, instructionsBeforeBranch: 14, instructionsAfterBranch: 1234, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2699a00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDLS/foward=false(before=0,after=0)", inst: BCONDLS, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 0, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d209000054"}, - {name: "BCONDLS/foward=false(before=123,after=0)", inst: BCONDLS, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 123, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2a9f0ff54"}, - {name: "BCONDLS/foward=false(before=10,after=123)", inst: BCONDLS, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 123, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2c9feff540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDLT/forward=true(before=0,after=10)", inst: BCONDLT, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 0, instructionsAfterBranch: 10, expHex: "6b0100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDLT/forward=true(before=10,after=10)", inst: BCONDLT, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 10, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d26b0100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDLT/forward=true(before=10,after=10)", inst: BCONDLT, forward: true, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d26b0100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDLT/foward=false(before=0,after=0)", inst: BCONDLT, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 0, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20b000054"}, - {name: "BCONDLT/foward=false(before=10,after=0)", inst: BCONDLT, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2cbfeff54"}, - {name: "BCONDLT/foward=false(before=10,after=10)", inst: BCONDLT, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2cbfeff540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDLT/forward=true(before=0,after=100)", inst: BCONDLT, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 0, instructionsAfterBranch: 100, expHex: "ab0c00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDLT/forward=true(before=100,after=10)", inst: BCONDLT, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 100, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d26b0100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDLT/forward=true(before=100,after=100)", inst: BCONDLT, forward: true, instructionsInPreamble: 123, instructionsBeforeBranch: 100, instructionsAfterBranch: 100, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2ab0c00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDLT/foward=false(before=0,after=0)", inst: BCONDLT, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 0, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20b000054"}, - {name: "BCONDLT/foward=false(before=100,after=0)", inst: BCONDLT, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 100, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d28bf3ff54"}, - {name: "BCONDLT/foward=false(before=10,after=100)", inst: BCONDLT, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 100, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2cbfeff540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDLT/forward=true(before=0,after=1234)", inst: BCONDLT, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 0, instructionsAfterBranch: 1234, expHex: "6b9a00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDLT/forward=true(before=1234,after=124)", inst: BCONDLT, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 1234, instructionsAfterBranch: 124, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2ab0f00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDLT/forward=true(before=14,after=1234)", inst: BCONDLT, forward: true, instructionsInPreamble: 123, instructionsBeforeBranch: 14, instructionsAfterBranch: 1234, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d26b9a00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDLT/foward=false(before=0,after=0)", inst: BCONDLT, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 0, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20b000054"}, - {name: "BCONDLT/foward=false(before=123,after=0)", inst: BCONDLT, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 123, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2abf0ff54"}, - {name: "BCONDLT/foward=false(before=10,after=123)", inst: BCONDLT, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 123, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2cbfeff540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDMI/forward=true(before=0,after=10)", inst: BCONDMI, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 0, instructionsAfterBranch: 10, expHex: "640100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDMI/forward=true(before=10,after=10)", inst: BCONDMI, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 10, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2640100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDMI/forward=true(before=10,after=10)", inst: BCONDMI, forward: true, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2640100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDMI/foward=false(before=0,after=0)", inst: BCONDMI, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 0, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d204000054"}, - {name: "BCONDMI/foward=false(before=10,after=0)", inst: BCONDMI, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2c4feff54"}, - {name: "BCONDMI/foward=false(before=10,after=10)", inst: BCONDMI, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2c4feff540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDMI/forward=true(before=0,after=100)", inst: BCONDMI, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 0, instructionsAfterBranch: 100, expHex: "a40c00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDMI/forward=true(before=100,after=10)", inst: BCONDMI, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 100, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2640100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDMI/forward=true(before=100,after=100)", inst: BCONDMI, forward: true, instructionsInPreamble: 123, instructionsBeforeBranch: 100, instructionsAfterBranch: 100, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2a40c00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDMI/foward=false(before=0,after=0)", inst: BCONDMI, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 0, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d204000054"}, - {name: "BCONDMI/foward=false(before=100,after=0)", inst: BCONDMI, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 100, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d284f3ff54"}, - {name: "BCONDMI/foward=false(before=10,after=100)", inst: BCONDMI, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 100, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2c4feff540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDMI/forward=true(before=0,after=1234)", inst: BCONDMI, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 0, instructionsAfterBranch: 1234, expHex: "649a00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDMI/forward=true(before=1234,after=124)", inst: BCONDMI, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 1234, instructionsAfterBranch: 124, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2a40f00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDMI/forward=true(before=14,after=1234)", inst: BCONDMI, forward: true, instructionsInPreamble: 123, instructionsBeforeBranch: 14, instructionsAfterBranch: 1234, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2649a00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDMI/foward=false(before=0,after=0)", inst: BCONDMI, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 0, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d204000054"}, - {name: "BCONDMI/foward=false(before=123,after=0)", inst: BCONDMI, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 123, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2a4f0ff54"}, - {name: "BCONDMI/foward=false(before=10,after=123)", inst: BCONDMI, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 123, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2c4feff540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDNE/forward=true(before=0,after=10)", inst: BCONDNE, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 0, instructionsAfterBranch: 10, expHex: "610100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDNE/forward=true(before=10,after=10)", inst: BCONDNE, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 10, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2610100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDNE/forward=true(before=10,after=10)", inst: BCONDNE, forward: true, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2610100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDNE/foward=false(before=0,after=0)", inst: BCONDNE, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 0, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d201000054"}, - {name: "BCONDNE/foward=false(before=10,after=0)", inst: BCONDNE, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2c1feff54"}, - {name: "BCONDNE/foward=false(before=10,after=10)", inst: BCONDNE, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2c1feff540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDNE/forward=true(before=0,after=100)", inst: BCONDNE, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 0, instructionsAfterBranch: 100, expHex: "a10c00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDNE/forward=true(before=100,after=10)", inst: BCONDNE, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 100, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2610100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDNE/forward=true(before=100,after=100)", inst: BCONDNE, forward: true, instructionsInPreamble: 123, instructionsBeforeBranch: 100, instructionsAfterBranch: 100, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2a10c00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDNE/foward=false(before=0,after=0)", inst: BCONDNE, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 0, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d201000054"}, - {name: "BCONDNE/foward=false(before=100,after=0)", inst: BCONDNE, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 100, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d281f3ff54"}, - {name: "BCONDNE/foward=false(before=10,after=100)", inst: BCONDNE, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 100, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2c1feff540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDNE/forward=true(before=0,after=1234)", inst: BCONDNE, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 0, instructionsAfterBranch: 1234, expHex: "619a00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDNE/forward=true(before=1234,after=124)", inst: BCONDNE, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 1234, instructionsAfterBranch: 124, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2a10f00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDNE/forward=true(before=14,after=1234)", inst: BCONDNE, forward: true, instructionsInPreamble: 123, instructionsBeforeBranch: 14, instructionsAfterBranch: 1234, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2619a00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDNE/foward=false(before=0,after=0)", inst: BCONDNE, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 0, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d201000054"}, - {name: "BCONDNE/foward=false(before=123,after=0)", inst: BCONDNE, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 123, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2a1f0ff54"}, - {name: "BCONDNE/foward=false(before=10,after=123)", inst: BCONDNE, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 123, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2c1feff540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDVS/forward=true(before=0,after=10)", inst: BCONDVS, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 0, instructionsAfterBranch: 10, expHex: "660100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDVS/forward=true(before=10,after=10)", inst: BCONDVS, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 10, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2660100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDVS/forward=true(before=10,after=10)", inst: BCONDVS, forward: true, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2660100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDVS/foward=false(before=0,after=0)", inst: BCONDVS, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 0, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d206000054"}, - {name: "BCONDVS/foward=false(before=10,after=0)", inst: BCONDVS, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2c6feff54"}, - {name: "BCONDVS/foward=false(before=10,after=10)", inst: BCONDVS, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2c6feff540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDVS/forward=true(before=0,after=100)", inst: BCONDVS, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 0, instructionsAfterBranch: 100, expHex: "a60c00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDVS/forward=true(before=100,after=10)", inst: BCONDVS, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 100, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2660100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDVS/forward=true(before=100,after=100)", inst: BCONDVS, forward: true, instructionsInPreamble: 123, instructionsBeforeBranch: 100, instructionsAfterBranch: 100, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2a60c00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDVS/foward=false(before=0,after=0)", inst: BCONDVS, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 0, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d206000054"}, - {name: "BCONDVS/foward=false(before=100,after=0)", inst: BCONDVS, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 100, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d286f3ff54"}, - {name: "BCONDVS/foward=false(before=10,after=100)", inst: BCONDVS, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 100, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2c6feff540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDVS/forward=true(before=0,after=1234)", inst: BCONDVS, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 0, instructionsAfterBranch: 1234, expHex: "669a00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDVS/forward=true(before=1234,after=124)", inst: BCONDVS, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 1234, instructionsAfterBranch: 124, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2a60f00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDVS/forward=true(before=14,after=1234)", inst: BCONDVS, forward: true, instructionsInPreamble: 123, instructionsBeforeBranch: 14, instructionsAfterBranch: 1234, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2669a00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDVS/foward=false(before=0,after=0)", inst: BCONDVS, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 0, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d206000054"}, - {name: "BCONDVS/foward=false(before=123,after=0)", inst: BCONDVS, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 123, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2a6f0ff54"}, - {name: "BCONDVS/foward=false(before=10,after=123)", inst: BCONDVS, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 123, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2c6feff540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - - {name: "BCONDVC/forward=true(before=0,after=10)", inst: BCONDVC, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 0, instructionsAfterBranch: 10, expHex: "670100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDVC/forward=true(before=10,after=10)", inst: BCONDVC, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 10, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2670100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDVC/forward=true(before=10,after=10)", inst: BCONDVC, forward: true, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2670100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDVC/foward=false(before=0,after=0)", inst: BCONDVC, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 0, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d207000054"}, - {name: "BCONDVC/foward=false(before=10,after=0)", inst: BCONDVC, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2c7feff54"}, - {name: "BCONDVC/foward=false(before=10,after=10)", inst: BCONDVC, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2c7feff540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDVC/forward=true(before=0,after=100)", inst: BCONDVC, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 0, instructionsAfterBranch: 100, expHex: "a70c00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDVC/forward=true(before=100,after=10)", inst: BCONDVC, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 100, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2670100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDVC/forward=true(before=100,after=100)", inst: BCONDVC, forward: true, instructionsInPreamble: 123, instructionsBeforeBranch: 100, instructionsAfterBranch: 100, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2a70c00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDVC/foward=false(before=0,after=0)", inst: BCONDVC, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 0, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d207000054"}, - {name: "BCONDVC/foward=false(before=100,after=0)", inst: BCONDVC, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 100, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d287f3ff54"}, - {name: "BCONDVC/foward=false(before=10,after=100)", inst: BCONDVC, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 100, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2c7feff540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDVC/forward=true(before=0,after=1234)", inst: BCONDVC, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 0, instructionsAfterBranch: 1234, expHex: "679a00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDVC/forward=true(before=1234,after=124)", inst: BCONDVC, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 1234, instructionsAfterBranch: 124, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2a70f00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDVC/forward=true(before=14,after=1234)", inst: BCONDVC, forward: true, instructionsInPreamble: 123, instructionsBeforeBranch: 14, instructionsAfterBranch: 1234, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2679a00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDVC/foward=false(before=0,after=0)", inst: BCONDVC, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 0, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d207000054"}, - {name: "BCONDVC/foward=false(before=123,after=0)", inst: BCONDVC, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 123, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2a7f0ff54"}, - {name: "BCONDVC/foward=false(before=10,after=123)", inst: BCONDVC, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 123, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2c7feff540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - - {name: "BCONDPL/forward=true(before=0,after=10)", inst: BCONDPL, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 0, instructionsAfterBranch: 10, expHex: "650100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDPL/forward=true(before=10,after=10)", inst: BCONDPL, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 10, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2650100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDPL/forward=true(before=10,after=10)", inst: BCONDPL, forward: true, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2650100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDPL/foward=false(before=0,after=0)", inst: BCONDPL, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 0, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d205000054"}, - {name: "BCONDPL/foward=false(before=10,after=0)", inst: BCONDPL, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2c5feff54"}, - {name: "BCONDPL/foward=false(before=10,after=10)", inst: BCONDPL, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2c5feff540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDPL/forward=true(before=0,after=100)", inst: BCONDPL, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 0, instructionsAfterBranch: 100, expHex: "a50c00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDPL/forward=true(before=100,after=10)", inst: BCONDPL, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 100, instructionsAfterBranch: 10, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2650100540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDPL/forward=true(before=100,after=100)", inst: BCONDPL, forward: true, instructionsInPreamble: 123, instructionsBeforeBranch: 100, instructionsAfterBranch: 100, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2a50c00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDPL/foward=false(before=0,after=0)", inst: BCONDPL, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 0, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d205000054"}, - {name: "BCONDPL/foward=false(before=100,after=0)", inst: BCONDPL, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 100, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d285f3ff54"}, - {name: "BCONDPL/foward=false(before=10,after=100)", inst: BCONDPL, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 100, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2c5feff540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDPL/forward=true(before=0,after=1234)", inst: BCONDPL, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 0, instructionsAfterBranch: 1234, expHex: "659a00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDPL/forward=true(before=1234,after=124)", inst: BCONDPL, forward: true, instructionsInPreamble: 0, instructionsBeforeBranch: 1234, instructionsAfterBranch: 124, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2a50f00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDPL/forward=true(before=14,after=1234)", inst: BCONDPL, forward: true, instructionsInPreamble: 123, instructionsBeforeBranch: 14, instructionsAfterBranch: 1234, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2659a00540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - {name: "BCONDPL/foward=false(before=0,after=0)", inst: BCONDPL, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 0, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d205000054"}, - {name: "BCONDPL/foward=false(before=123,after=0)", inst: BCONDPL, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 123, instructionsAfterBranch: 0, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2a5f0ff54"}, - {name: "BCONDPL/foward=false(before=10,after=123)", inst: BCONDPL, forward: false, instructionsInPreamble: 123, instructionsBeforeBranch: 10, instructionsAfterBranch: 123, expHex: "0a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2c5feff540a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d20a7d80d2"}, - } - - for _, tt := range tests { - tc := tt - t.Run(tc.name, func(t *testing.T) { - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - a := NewAssembler(asm.NilRegister) - - for i := 0; i < tc.instructionsInPreamble; i++ { - a.CompileConstToRegister(MOVD, 1000, RegR10) - } - backwardTarget := a.CompileStandAlone(NOP) - for i := 0; i < tc.instructionsBeforeBranch; i++ { - a.CompileConstToRegister(MOVD, 1000, RegR10) - } - br := a.CompileJump(tc.inst) - for i := 0; i < tc.instructionsAfterBranch; i++ { - a.CompileConstToRegister(MOVD, 1000, RegR10) - } - fowardTarget := a.CompileStandAlone(NOP) - - if tc.forward { - br.AssignJumpTarget(fowardTarget) - } else { - br.AssignJumpTarget(backwardTarget) - } - - buf := code.NextCodeSection() - err := a.Assemble(buf) - require.NoError(t, err) - - actual := buf.Bytes() - require.Equal(t, tc.expHex, hex.EncodeToString(actual)) - }) - } -} diff --git a/internal/asm/assembler.go b/internal/asm/assembler.go deleted file mode 100644 index dd34f78633..0000000000 --- a/internal/asm/assembler.go +++ /dev/null @@ -1,209 +0,0 @@ -package asm - -import ( - "fmt" - "math" -) - -// Register represents architecture-specific registers. -type Register byte - -// NilRegister is the only architecture-independent register, and -// can be used to indicate that no register is specified. -const NilRegister Register = 0 - -// Instruction represents architecture-specific instructions. -type Instruction uint16 // to accommodate the high cardinality of vector ops - -// ConditionalRegisterState represents architecture-specific conditional -// register's states. -type ConditionalRegisterState byte - -// ConditionalRegisterStateUnset is the only architecture-independent conditional state, and -// can be used to indicate that no conditional state is specified. -const ConditionalRegisterStateUnset ConditionalRegisterState = 0 - -// Node represents a node in the linked list of assembled operations. -type Node interface { - fmt.Stringer - - // AssignJumpTarget assigns the given target node as the destination of - // jump instruction for this Node. - AssignJumpTarget(target Node) - - // AssignDestinationConstant assigns the given constant as the destination - // of the instruction for this node. - AssignDestinationConstant(value ConstantValue) - - // AssignSourceConstant assigns the given constant as the source - // of the instruction for this node. - AssignSourceConstant(value ConstantValue) - - // OffsetInBinary returns the offset of this node in the assembled binary. - OffsetInBinary() NodeOffsetInBinary -} - -// NodeOffsetInBinary represents an offset of this node in the final binary. -type NodeOffsetInBinary = uint64 - -// ConstantValue represents a constant value used in an instruction. -type ConstantValue = int64 - -// StaticConst represents an arbitrary constant bytes which are pooled and emitted by assembler into the binary. -// These constants can be referenced by instructions. -type StaticConst struct { - // offsetFinalizedCallbacks holds callbacks which are called when .OffsetInBinary is finalized by assembler implementation. - offsetFinalizedCallbacks []func(offsetOfConstInBinary uint64) - - Raw []byte - // OffsetInBinary is the offset of this static const in the result binary. - OffsetInBinary uint64 -} - -// NewStaticConst returns the pointer to the new NewStaticConst for given bytes. -func NewStaticConst(raw []byte) *StaticConst { - return &StaticConst{Raw: raw} -} - -// AddOffsetFinalizedCallback adds a callback into offsetFinalizedCallbacks. -func (s *StaticConst) AddOffsetFinalizedCallback(cb func(offsetOfConstInBinary uint64)) { - s.offsetFinalizedCallbacks = append(s.offsetFinalizedCallbacks, cb) -} - -// SetOffsetInBinary finalizes the offset of this StaticConst, and invokes callbacks. -func (s *StaticConst) SetOffsetInBinary(offset uint64) { - s.OffsetInBinary = offset - for _, cb := range s.offsetFinalizedCallbacks { - cb(offset) - } -} - -// StaticConstPool holds a bulk of StaticConst which are yet to be emitted into the binary. -type StaticConstPool struct { - // addedConsts is used to deduplicate the consts to reduce the final size of binary. - // Note: we can use map on .consts field and remove this field, - // but we have the separate field for deduplication in order to have deterministic assembling behavior. - addedConsts map[*StaticConst]struct{} - - Consts []*StaticConst - // FirstUseOffsetInBinary holds the offset of the first instruction which accesses this const pool . - FirstUseOffsetInBinary NodeOffsetInBinary - // PoolSizeInBytes is the current size of the pool in bytes. - PoolSizeInBytes int -} - -func NewStaticConstPool() StaticConstPool { - return StaticConstPool{addedConsts: map[*StaticConst]struct{}{}, FirstUseOffsetInBinary: math.MaxUint64} -} - -// Reset resets the *StaticConstPool for reuse. -func (p *StaticConstPool) Reset() { - for _, c := range p.Consts { - delete(p.addedConsts, c) - } - // Reuse the slice to avoid re-allocations. - p.Consts = p.Consts[:0] - p.PoolSizeInBytes = 0 - p.FirstUseOffsetInBinary = math.MaxUint64 -} - -// Empty returns true if StaticConstPool is empty. -func (p *StaticConstPool) Empty() bool { - return p.FirstUseOffsetInBinary == math.MaxUint64 -} - -// AddConst adds a *StaticConst into the pool if it's not already added. -func (p *StaticConstPool) AddConst(c *StaticConst, useOffset NodeOffsetInBinary) { - if _, ok := p.addedConsts[c]; ok { - return - } - - if p.Empty() { - p.FirstUseOffsetInBinary = useOffset - } - - c.offsetFinalizedCallbacks = c.offsetFinalizedCallbacks[:0] - - p.Consts = append(p.Consts, c) - p.PoolSizeInBytes += len(c.Raw) - p.addedConsts[c] = struct{}{} -} - -// AssemblerBase is the common interface for assemblers among multiple architectures. -// -// Note: some of them can be implemented in an arch-independent way, but not all can be -// implemented as such. However, we intentionally put such arch-dependant methods here -// in order to provide the common documentation interface. -type AssemblerBase interface { - // Reset resets the state of Assembler implementation and mark it ready for - // the compilation of the new function compilation. - Reset() - - // Assemble produces the final binary for the assembled operations. - Assemble(Buffer) error - - // SetJumpTargetOnNext instructs the assembler that the next node must be - // assigned to the given node's jump destination. - SetJumpTargetOnNext(node Node) - - // BuildJumpTable calculates the offsets between the first instruction `initialInstructions[0]` - // and others (e.g. initialInstructions[3]), and wrote the calculated offsets into pre-allocated - // `table` StaticConst in little endian. - BuildJumpTable(table *StaticConst, initialInstructions []Node) - - // AllocateNOP allocates Node for NOP instruction. - AllocateNOP() Node - - // Add appends the given `Node` in the assembled linked list. - Add(Node) - - // CompileStandAlone adds an instruction to take no arguments. - CompileStandAlone(instruction Instruction) Node - - // CompileConstToRegister adds an instruction where source operand is `value` as constant and destination is `destinationReg` register. - CompileConstToRegister(instruction Instruction, value ConstantValue, destinationReg Register) Node - - // CompileRegisterToRegister adds an instruction where source and destination operands are registers. - CompileRegisterToRegister(instruction Instruction, from, to Register) - - // CompileMemoryToRegister adds an instruction where source operands is the memory address specified by `sourceBaseReg+sourceOffsetConst` - // and the destination is `destinationReg` register. - CompileMemoryToRegister( - instruction Instruction, - sourceBaseReg Register, - sourceOffsetConst ConstantValue, - destinationReg Register, - ) - - // CompileRegisterToMemory adds an instruction where source operand is `sourceRegister` register and the destination is the - // memory address specified by `destinationBaseRegister+destinationOffsetConst`. - CompileRegisterToMemory( - instruction Instruction, - sourceRegister Register, - destinationBaseRegister Register, - destinationOffsetConst ConstantValue, - ) - - // CompileJump adds jump-type instruction and returns the corresponding Node in the assembled linked list. - CompileJump(jmpInstruction Instruction) Node - - // CompileJumpToRegister adds jump-type instruction whose destination is the memory address specified by `reg` register. - CompileJumpToRegister(jmpInstruction Instruction, reg Register) - - // CompileReadInstructionAddress adds an ADR instruction to set the absolute address of "target instruction" - // into destinationRegister. "target instruction" is specified by beforeTargetInst argument and - // the target is determined by "the instruction right after beforeTargetInst type". - // - // For example, if `beforeTargetInst == RET` and we have the instruction sequence like - // `ADR -> X -> Y -> ... -> RET -> MOV`, then the `ADR` instruction emitted by this function set the absolute - // address of `MOV` instruction into the destination register. - CompileReadInstructionAddress(destinationRegister Register, beforeAcquisitionTargetInstruction Instruction) -} - -// JumpTableMaximumOffset represents the limit on the size of jump table in bytes. -// When users try loading an extremely large WebAssembly binary which contains a br_table -// statement with approximately 4294967296 (2^32) targets. Realistically speaking, that kind of binary -// could result in more than ten gigabytes of native compiled code where we have to care about -// huge stacks whose height might exceed 32-bit range, and such huge stack doesn't work with the -// current implementation. -const JumpTableMaximumOffset = math.MaxUint32 diff --git a/internal/asm/assembler_test.go b/internal/asm/assembler_test.go deleted file mode 100644 index 779937676e..0000000000 --- a/internal/asm/assembler_test.go +++ /dev/null @@ -1,46 +0,0 @@ -package asm - -import ( - "testing" - - "github.com/tetratelabs/wazero/internal/testing/require" -) - -func TestNewStaticConstPool(t *testing.T) { - p := NewStaticConstPool() - require.NotNil(t, p.addedConsts) -} - -func TestStaticConst_AddOffsetFinalizedCallback(t *testing.T) { - p := NewStaticConstPool() - const firstUseOffset uint64 = 100 - - // Add first const. - c := NewStaticConst([]byte{1}) - p.AddConst(c, firstUseOffset) - require.Equal(t, firstUseOffset, p.FirstUseOffsetInBinary) - require.Equal(t, 1, len(p.Consts)) - require.Equal(t, 1, len(p.addedConsts)) - - // Adding the same *StaticConst doesn't affect the state. - p.AddConst(c, firstUseOffset+10000) - require.Equal(t, firstUseOffset, p.FirstUseOffsetInBinary) - require.Equal(t, 1, len(p.Consts)) - require.Equal(t, 1, len(p.addedConsts)) - - // Add another const. - c2 := NewStaticConst([]byte{1, 2}) - p.AddConst(c2, firstUseOffset+100) - require.Equal(t, firstUseOffset, p.FirstUseOffsetInBinary) // first use doesn't change! - require.Equal(t, 2, len(p.Consts)) - require.Equal(t, 2, len(p.addedConsts)) -} - -func TestStaticConst_SetOffsetInBinary(t *testing.T) { - sc := NewStaticConst([]byte{1}) - const offset uint64 = 100 - sc.AddOffsetFinalizedCallback(func(offsetOfConstInBinary uint64) { - require.Equal(t, offset, offsetOfConstInBinary) - }) - sc.SetOffsetInBinary(offset) -} diff --git a/internal/asm/buffer.go b/internal/asm/buffer.go deleted file mode 100644 index 0476c380ea..0000000000 --- a/internal/asm/buffer.go +++ /dev/null @@ -1,235 +0,0 @@ -package asm - -import ( - "encoding/binary" - "fmt" - "unsafe" - - "github.com/tetratelabs/wazero/internal/platform" -) - -var zero [16]byte - -// CodeSegment represents a memory mapped segment where native CPU instructions -// are written. -// -// To construct code segments, the program must call Next to obtain a buffer -// view capable of writing data at the end of the segment. Next must be called -// before generating the code of a function because it aligns the next write on -// 16 bytes. -// -// Instances of CodeSegment hold references to memory which is NOT managed by -// the garbage collector and therefore must be released *manually* by calling -// their Unmap method to prevent memory leaks. -// -// The zero value is a valid, empty code segment, equivalent to being -// constructed by calling NewCodeSegment(nil). -type CodeSegment struct { - code []byte - size int -} - -// NewCodeSegment constructs a CodeSegment value from a byte slice. -// -// No validation is made that the byte slice is a memory mapped region which can -// be unmapped on Close. -func NewCodeSegment(code []byte) *CodeSegment { - return &CodeSegment{code: code, size: len(code)} -} - -// Map allocates a memory mapping of the given size to the code segment. -// -// Note that programs only need to use this method to initialize the code -// segment to a specific content (e.g. when loading pre-compiled code from a -// file), otherwise the backing memory mapping is allocated on demand when code -// is written to the code segment via Buffers returned by calls to Next. -// -// The method errors is the segment is already backed by a memory mapping. -func (seg *CodeSegment) Map(size int) error { - if seg.code != nil { - return fmt.Errorf("code segment already initialized to memory mapping of size %d", len(seg.code)) - } - b, err := platform.MmapCodeSegment(size) - if err != nil { - return err - } - seg.code = b - seg.size = size - return nil -} - -// Close unmaps the underlying memory region held by the code segment, clearing -// its state back to an empty code segment. -// -// The value is still usable after unmapping its memory, a new memory area can -// be allocated by calling Map or writing to the segment. -func (seg *CodeSegment) Unmap() error { - if seg.code != nil { - if err := platform.MunmapCodeSegment(seg.code[:cap(seg.code)]); err != nil { - return err - } - seg.code = nil - seg.size = 0 - } - return nil -} - -// Addr returns the address of the beginning of the code segment as a uintptr. -func (seg *CodeSegment) Addr() uintptr { - if len(seg.code) > 0 { - return uintptr(unsafe.Pointer(&seg.code[0])) - } - return 0 -} - -// Size returns the size of code segment, which is less or equal to the length -// of the byte slice returned by Len or Bytes. -func (seg *CodeSegment) Size() uintptr { - return uintptr(seg.size) -} - -// Len returns the length of the byte slice referencing the memory mapping of -// the code segment. -func (seg *CodeSegment) Len() int { - return len(seg.code) -} - -// Bytes returns a byte slice to the memory mapping of the code segment. -// -// The returned slice remains valid until more bytes are written to a buffer -// of the code segment, or Unmap is called. -func (seg *CodeSegment) Bytes() []byte { - return seg.code -} - -// Next returns a buffer pointed at the end of the code segment to support -// writing more code instructions to it. -// -// Buffers are passed by value, but they hold a reference to the code segment -// that they were created from. -func (seg *CodeSegment) NextCodeSection() Buffer { - // Align 16-bytes boundary. - seg.AppendBytes(zero[:seg.size&15]) - return Buffer{CodeSegment: seg, off: seg.size} -} - -// Append appends n bytes to the code segment, returning a slice to the appended -// memory region. -// -// The underlying code segment may be reallocated if it was too short to hold -// n more bytes, which invalidates any addresses previously returned by calls -// to Addr. -func (seg *CodeSegment) Append(n int) []byte { - seg.size += n - if seg.size > len(seg.code) { - seg.growToSize() - } - return seg.code[seg.size-n:] -} - -// AppendByte appends a single byte to the code segment. -// -// The underlying code segment may be reallocated if it was too short to hold -// one more byte, which invalidates any addresses previously returned by calls -// to Addr. -func (seg *CodeSegment) AppendByte(b byte) { - seg.size++ - if seg.size > len(seg.code) { - seg.growToSize() - } - seg.code[seg.size-1] = b -} - -// AppendBytes appends a copy of b to the code segment. -// -// The underlying code segment may be reallocated if it was too short to hold -// len(b) more bytes, which invalidates any addresses previously returned by -// calls to Addr. -func (seg *CodeSegment) AppendBytes(b []byte) { - copy(seg.Append(len(b)), b) -} - -// AppendUint32 appends a 32 bits integer to the code segment. -// -// The underlying code segment may be reallocated if it was too short to hold -// four more bytes, which invalidates any addresses previously returned by calls -// to Addr. -func (seg *CodeSegment) AppendUint32(u uint32) { - seg.size += 4 - if seg.size > len(seg.code) { - seg.growToSize() - } - // This can be replaced by an unsafe operation to assign the uint32, which - // keeps the function cost below the inlining threshold. However, it did not - // show any improvements in arm64 benchmarks so we retained this safer code. - binary.LittleEndian.PutUint32(seg.code[seg.size-4:], u) -} - -// growMode grows the code segment so that another section can be added to it. -// -// The method is marked go:noinline so that it doesn't get inline in Append, -// and AppendByte, which keeps the inlining score of those methods low enough -// that they can be inlined at the call sites. -// -//go:noinline -func (seg *CodeSegment) growToSize() { - seg.Grow(0) -} - -// Grow ensure that the capacity of the code segment is large enough to hold n -// more bytes. -// -// The underlying code segment may be reallocated if it was too short, which -// invalidates any addresses previously returned by calls to Addr. -func (seg *CodeSegment) Grow(n int) { - size := len(seg.code) - want := seg.size + n - if size >= want { - return - } - if size == 0 { - size = 65536 - } - for size < want { - size *= 2 - } - b, err := platform.RemapCodeSegment(seg.code, size) - if err != nil { - // The only reason for growing the buffer to error is if we run - // out of memory, so panic for now as it greatly simplifies error - // handling to assume writing to the buffer would never fail. - panic(err) - } - seg.code = b -} - -// Buffer is a reference type representing a section beginning at the end of a -// code segment where new instructions can be written. -type Buffer struct { - *CodeSegment - off int -} - -func (buf Buffer) Cap() int { - return len(buf.code) - buf.off -} - -func (buf Buffer) Len() int { - return buf.size - buf.off -} - -func (buf Buffer) Bytes() []byte { - return buf.code[buf.off:buf.size:buf.size] -} - -func (buf Buffer) Reset() { - buf.size = buf.off -} - -func (buf Buffer) Truncate(n int) { - buf.size = buf.off + n -} - -func (buf Buffer) Append4Bytes(a, b, c, d byte) { - buf.AppendUint32(uint32(a) | uint32(b)<<8 | uint32(c)<<16 | uint32(d)<<24) -} diff --git a/internal/asm/buffer_test.go b/internal/asm/buffer_test.go deleted file mode 100644 index 153101b880..0000000000 --- a/internal/asm/buffer_test.go +++ /dev/null @@ -1,119 +0,0 @@ -package asm_test - -import ( - "testing" - "unsafe" - - "github.com/tetratelabs/wazero/internal/asm" - "github.com/tetratelabs/wazero/internal/testing/require" -) - -func TestCodeSegmentZeroValue(t *testing.T) { - withCodeSegment(t, func(code *asm.CodeSegment) { - require.Equal(t, uintptr(0), code.Addr()) - require.Equal(t, uintptr(0), code.Size()) - require.Equal(t, 0, code.Len()) - require.Equal(t, ([]byte)(nil), code.Bytes()) - - buf := code.NextCodeSection() - require.Equal(t, 0, buf.Cap()) - require.Equal(t, 0, buf.Len()) - require.Equal(t, ([]byte)(nil), buf.Bytes()) - }) -} - -func TestCodeSegmentMapUnmap(t *testing.T) { - withCodeSegment(t, func(code *asm.CodeSegment) { - const size = 4096 - require.NoError(t, code.Map(size)) - require.NotEqual(t, uintptr(0), code.Addr()) - require.Equal(t, uintptr(size), code.Size()) - require.Equal(t, size, code.Len()) - require.NotEqual(t, ([]byte)(nil), code.Bytes()) - - for i := 0; i < 3; i++ { - require.NoError(t, code.Unmap()) - require.Equal(t, uintptr(0), code.Addr()) - require.Equal(t, uintptr(0), code.Size()) - require.Equal(t, 0, code.Len()) - require.Equal(t, ([]byte)(nil), code.Bytes()) - } - }) -} - -func TestBufferAppendByte(t *testing.T) { - withBuffer(t, func(buf asm.Buffer) { - data := []byte("Hello World!") - - for i, c := range data { - buf.AppendByte(c) - require.NotEqual(t, 0, buf.Cap()) - require.Equal(t, i+1, buf.Len()) - require.Equal(t, data[:i+1], buf.Bytes()) - } - }) -} - -func TestBufferAppendBytes(t *testing.T) { - withBuffer(t, func(buf asm.Buffer) { - buf.AppendBytes([]byte("Hello World!")) - require.NotEqual(t, 0, buf.Cap()) - require.Equal(t, 12, buf.Len()) - require.Equal(t, []byte("Hello World!"), buf.Bytes()) - }) -} - -func TestBufferAppendUint32(t *testing.T) { - withBuffer(t, func(buf asm.Buffer) { - values := []uint32{0, 1, 2, 3, 4, 5, 6, 7, 8, 9} - bytes := unsafe.Slice(*(**byte)(unsafe.Pointer(&values)), 4*len(values)) - - for i, v := range values { - buf.AppendUint32(v) - require.NotEqual(t, 0, buf.Cap()) - require.Equal(t, 4*(i+1), buf.Len()) - require.Equal(t, bytes[:4*(i+1)], buf.Bytes()) - } - }) -} - -func TestBufferReset(t *testing.T) { - withBuffer(t, func(buf asm.Buffer) { - buf.AppendBytes([]byte("Hello World!")) - require.NotEqual(t, 0, buf.Cap()) - require.Equal(t, 12, buf.Len()) - require.Equal(t, []byte("Hello World!"), buf.Bytes()) - - buf.Reset() - require.Equal(t, 0, buf.Len()) - require.Equal(t, []byte{}, buf.Bytes()) - }) -} - -func TestBufferTruncate(t *testing.T) { - withBuffer(t, func(buf asm.Buffer) { - buf.AppendBytes([]byte("Hello World!")) - require.NotEqual(t, 0, buf.Cap()) - require.Equal(t, 12, buf.Len()) - require.Equal(t, []byte("Hello World!"), buf.Bytes()) - - buf.Truncate(5) - require.Equal(t, 5, buf.Len()) - require.Equal(t, []byte("Hello"), buf.Bytes()) - }) -} - -func withCodeSegment(t *testing.T, f func(*asm.CodeSegment)) { - code := asm.NewCodeSegment(nil) - defer func() { require.NoError(t, code.Unmap()) }() - f(code) -} - -func withBuffer(t *testing.T, f func(asm.Buffer)) { - withCodeSegment(t, func(code *asm.CodeSegment) { - // Repeat the test multiple times to ensure that Next works as expected. - for i := 0; i < 10; i++ { - f(code.NextCodeSection()) - } - }) -} diff --git a/internal/asm/impl.go b/internal/asm/impl.go deleted file mode 100644 index 6c54816378..0000000000 --- a/internal/asm/impl.go +++ /dev/null @@ -1,59 +0,0 @@ -package asm - -import ( - "encoding/binary" - "fmt" -) - -// BaseAssemblerImpl includes code common to all architectures. -// -// Note: When possible, add code here instead of in architecture-specific files to reduce drift: -// As this is internal, exporting symbols only to reduce duplication is ok. -type BaseAssemblerImpl struct { - // SetBranchTargetOnNextNodes holds branch kind instructions (BR, conditional BR, etc.) - // where we want to set the next coming instruction as the destination of these BR instructions. - SetBranchTargetOnNextNodes []Node - - // JumpTableEntries holds the information to build jump tables. - JumpTableEntries []JumpTableEntry -} - -// JumpTableEntry is the necessary data to build a jump table. -// This is exported for testing purpose. -type JumpTableEntry struct { - t *StaticConst - labelInitialInstructions []Node -} - -// SetJumpTargetOnNext implements AssemblerBase.SetJumpTargetOnNext -func (a *BaseAssemblerImpl) SetJumpTargetOnNext(node Node) { - a.SetBranchTargetOnNextNodes = append(a.SetBranchTargetOnNextNodes, node) -} - -// BuildJumpTable implements AssemblerBase.BuildJumpTable -func (a *BaseAssemblerImpl) BuildJumpTable(table *StaticConst, labelInitialInstructions []Node) { - a.JumpTableEntries = append(a.JumpTableEntries, JumpTableEntry{ - t: table, - labelInitialInstructions: labelInitialInstructions, - }) -} - -// FinalizeJumpTableEntry finalizes the build tables inside the given code. -func (a *BaseAssemblerImpl) FinalizeJumpTableEntry(code []byte) (err error) { - for i := range a.JumpTableEntries { - ent := &a.JumpTableEntries[i] - labelInitialInstructions := ent.labelInitialInstructions - table := ent.t - // Compile the offset table for each target. - base := labelInitialInstructions[0].OffsetInBinary() - for i, nop := range labelInitialInstructions { - if nop.OffsetInBinary()-base >= JumpTableMaximumOffset { - return fmt.Errorf("too large br_table") - } - // We store the offset from the beginning of the L0's initial instruction. - binary.LittleEndian.PutUint32(code[table.OffsetInBinary+uint64(i*4):table.OffsetInBinary+uint64((i+1)*4)], - uint32(nop.OffsetInBinary())-uint32(base)) - } - } - return -} diff --git a/internal/engine/compiler/RATIONALE.md b/internal/engine/compiler/RATIONALE.md deleted file mode 100644 index 9cb7513e38..0000000000 --- a/internal/engine/compiler/RATIONALE.md +++ /dev/null @@ -1,112 +0,0 @@ -# Compiler engine - -This package implements the Compiler engine for WebAssembly *purely written in Go*. -In this README, we describe the background, technical difficulties and some design choices. - -## General limitations on pure Go Compiler engines - -In Go program, each Goroutine manages its own stack, and each item on Goroutine -stack is managed by Go runtime for garbage collection, etc. - -These impose some difficulties on compiler engine purely written in Go because -we *cannot* use native push/pop instructions to save/restore temporary -variables spilling from registers. This results in making it impossible for us -to invoke Go functions from compiled native codes with the native `call` -instruction since it involves stack manipulations. - -*TODO: maybe it is possible to hack the runtime to make it possible to achieve -function calls with `call`.* - -## How to generate native codes - -wazero uses its own assembler, implemented from scratch in the -[`internal/asm`](../../asm/) package. The primary rationale are wazero's zero -dependency policy, and to enable concurrent compilation (a feature the -WebAssembly binary format optimizes for). - -Before this, wazero used [`twitchyliquid64/golang-asm`](https://github.com/twitchyliquid64/golang-asm). -However, this was not only a dependency (one of our goals is to have zero -dependencies), but also a large one (several megabytes added to the binary). -Moreover, any copy of golang-asm is not thread-safe, so can't be used for -concurrent compilation (See [#233](https://github.com/tetratelabs/wazero/issues/233)). - -The assembled native codes are represented as `[]byte` and the slice region is -marked as executable via mmap system call. - -## How to enter native codes - -Assuming that we have a native code as `[]byte`, it is straightforward to enter -the native code region via Go assembly code. In this package, we have the -function without body called `nativecall` - -```go -func nativecall(codeSegment, engine, memory uintptr) -``` - -where we pass `codeSegment uintptr` as a first argument. This pointer is to the -first instruction to be executed. The pointer can be easily derived from -`[]byte` via `unsafe.Pointer`: - -```go -code := []byte{} -/* ...Compilation ...*/ -codeSegment := uintptr(unsafe.Pointer(&code[0])) -nativecall(codeSegment, ...) -``` - -And `nativecall` is actually implemented in [arch_amd64.s](./arch_amd64.s) -as a convenience layer to comply with the Go's official calling convention. -We delegate the task to jump into the code segment to the Go assembler code. - - -## Why it's safe to execute runtime-generated machine codes against async Goroutine preemption - -Goroutine preemption is the mechanism of the Go runtime to switch goroutines contexts on an OS thread. -There are two types of preemption: cooperative preemption and async preemption. The former happens, for example, -when making a function call, and it is not an issue for our runtime-generated functions as they do not make -direct function calls to Go-implemented functions. On the other hand, the latter, async preemption, can be problematic -since it tries to interrupt the execution of Goroutine at any point of function, and manipulates CPU register states. - -Fortunately, our runtime-generated machine codes do not need to take the async preemption into account. -All the assembly codes are entered via the trampoline implemented as Go Assembler Function (e.g. [arch_amd64.s](./arch_amd64.s)), -and as of Go 1.20, these assembler functions are considered as _unsafe_ for async preemption: -- https://github.com/golang/go/blob/go1.20rc1/src/runtime/preempt.go#L406-L407 -- https://github.com/golang/go/blob/9f0234214473dfb785a5ad84a8fc62a6a395cbc3/src/runtime/traceback.go#L227 - -From the Go runtime point of view, the execution of runtime-generated machine codes is considered as a part of -that trampoline function. Therefore, runtime-generated machine code is also correctly considered unsafe for async preemption. - -## Why context cancellation is handled in Go code rather than native code - -Since [wazero v1.0.0-pre.9](https://github.com/tetratelabs/wazero/releases/tag/v1.0.0-pre.9), the runtime -supports integration with Go contexts to interrupt execution after a timeout, or in response to explicit cancellation. -This support is internally implemented as a special opcode `builtinFunctionCheckExitCode` that triggers the execution of -a Go function (`ModuleInstance.FailIfClosed`) that atomically checks a sentinel value at strategic points in the code -(e.g. [within loops][checkexitcode_loop]). - -[It _is indeed_ possible to check the sentinel value directly, without leaving the native world][native_check], thus sparing some cycles; -however, because native code never preempts (see section above), this may lead to a state where the other goroutines -never get the chance to run, and thus never get the chance to set the sentinel value; effectively preventing -cancellation from taking place. - -[checkexitcode_loop]: https://github.com/tetratelabs/wazero/blob/86444c67a37dbf9e693ae5b365901f64968d9025/internal/wazeroir/compiler.go#L467-L476 -[native_check]: https://github.com/tetratelabs/wazero/issues/1409 - -## Source Offset Mapping - -When translating code from WebAssembly to the wazero IR, and compiling to native -binary, wazero keeps track of two indexes to correlate native program counters -to the original source offset that they were generated from. - -Source offset maps are useful for debugging, but holding indexes in memory for -all instructions can have a significant overhead. To reduce the memory footprint -of the compiled modules, wazero uses data structures inspired by -[frame-of-reference and delta encoding][FOR]. - -Because wazero does not reorder instructions, the source offsets are naturally -sorted during compilation, and the distance between two consecutive offsets is -usually small. Encoding deltas instead of the absolute values allows most of -the indexes to store offsets with an overhead of 8 bits per instruction, instead -of recording 64 bits integers for absolute code positions. - -[FOR]: https://lemire.me/blog/2012/02/08/effective-compression-using-frame-of-reference-and-delta-coding/ diff --git a/internal/engine/compiler/arch.go b/internal/engine/compiler/arch.go deleted file mode 100644 index 81b9efc3a7..0000000000 --- a/internal/engine/compiler/arch.go +++ /dev/null @@ -1,19 +0,0 @@ -package compiler - -import ( - "github.com/tetratelabs/wazero/internal/asm" - "github.com/tetratelabs/wazero/internal/wasm" -) - -// newArchContext returns a new archContext which is architecture-specific type to be embedded in callEngine. -// This must be initialized in init() function in architecture-specific arch_*.go file which is guarded by build tag. -var newArchContext func() archContext - -// nativecall is used by callEngine.execWasmFunction and the entrypoint to enter the compiled native code. -// codeSegment is the pointer to the initial instruction of the compiled native code. -// -// Note: this is implemented in per-arch Go assembler file. For example, arch_amd64.s implements this for amd64. -func nativecall(codeSegment uintptr, ce *callEngine, moduleInstanceAddress *wasm.ModuleInstance) - -// registerNameFn is used for debugging purpose to have register symbols in the string of runtimeValueLocation. -var registerNameFn func(register asm.Register) string diff --git a/internal/engine/compiler/arch_amd64.go b/internal/engine/compiler/arch_amd64.go deleted file mode 100644 index b09a1cab25..0000000000 --- a/internal/engine/compiler/arch_amd64.go +++ /dev/null @@ -1,35 +0,0 @@ -package compiler - -import ( - "github.com/tetratelabs/wazero/internal/asm" - "github.com/tetratelabs/wazero/internal/asm/amd64" -) - -// init initializes variables for the amd64 architecture -func init() { - newArchContext = newArchContextImpl - registerNameFn = amd64.RegisterName - unreservedGeneralPurposeRegisters = amd64UnreservedGeneralPurposeRegisters - unreservedVectorRegisters = amd64UnreservedVectorRegisters -} - -// archContext is embedded in callEngine in order to store architecture-specific data. -// For amd64, this is empty. -type archContext struct{} - -// newArchContextImpl implements newArchContext for amd64 architecture. -func newArchContextImpl() (ret archContext) { return } - -// newCompiler returns a new compiler interface which can be used to compile the given function instance. -// Note: ir param can be nil for host functions. -func newCompiler() compiler { - return newAmd64Compiler() -} - -func registerMaskShift(r asm.Register) int { - return int(r - amd64.RegAX) -} - -func registerFromMaskShift(s int) asm.Register { - return amd64.RegAX + asm.Register(s) -} diff --git a/internal/engine/compiler/arch_amd64.s b/internal/engine/compiler/arch_amd64.s deleted file mode 100644 index 5224d398be..0000000000 --- a/internal/engine/compiler/arch_amd64.s +++ /dev/null @@ -1,9 +0,0 @@ -#include "funcdata.h" -#include "textflag.h" - -// nativecall(codeSegment, ce, moduleInstanceAddress) -TEXT ·nativecall(SB), NOSPLIT|NOFRAME, $0-24 - MOVQ ce+8(FP), R13 // Load the address of *callEngine. into amd64ReservedRegisterForCallEngine. - MOVQ moduleInstanceAddress+16(FP), R12 // Load the address of *wasm.ModuleInstance into amd64CallingConventionModuleInstanceAddressRegister. - MOVQ codeSegment+0(FP), AX // Load the address of native code. - JMP AX // Jump to native code. diff --git a/internal/engine/compiler/arch_arm64.go b/internal/engine/compiler/arch_arm64.go deleted file mode 100644 index 4262da6129..0000000000 --- a/internal/engine/compiler/arch_arm64.go +++ /dev/null @@ -1,70 +0,0 @@ -package compiler - -import ( - "math" - - "github.com/tetratelabs/wazero/internal/asm" - "github.com/tetratelabs/wazero/internal/asm/arm64" -) - -// init initializes variables for the arm64 architecture -func init() { - newArchContext = newArchContextImpl - registerNameFn = arm64.RegisterName - unreservedGeneralPurposeRegisters = arm64UnreservedGeneralPurposeRegisters - unreservedVectorRegisters = arm64UnreservedVectorRegisters -} - -// archContext is embedded in callEngine in order to store architecture-specific data. -type archContext struct { - // compilerCallReturnAddress holds the absolute return address for nativecall. - // The value is set whenever nativecall is executed and done in compiler_arm64.s - // Native code can return to the ce.execWasmFunction's main loop back by - // executing "ret" instruction with this value. See arm64Compiler.exit. - // Note: this is only used by Compiler code so mark this as nolint. - compilerCallReturnAddress uint64 //nolint - - // Loading large constants in arm64 is a bit costly, so we place the following - // consts on callEngine struct so that we can quickly access them during various operations. - - // minimum32BitSignedInt is used for overflow check for 32-bit signed division. - // Note: this can be obtained by moving $1 and doing left-shift with 31, but it is - // slower than directly loading from this location. - minimum32BitSignedInt int32 - // Note: this can be obtained by moving $1 and doing left-shift with 63, but it is - // slower than directly loading from this location. - // minimum64BitSignedInt is used for overflow check for 64-bit signed division. - minimum64BitSignedInt int64 -} - -// newArchContextImpl implements newArchContext for amd64 architecture. -func newArchContextImpl() archContext { - return archContext{ - minimum32BitSignedInt: math.MinInt32, - minimum64BitSignedInt: math.MinInt64, - } -} - -// newCompiler returns a new compiler interface which can be used to compile the given function instance. -// Note: ir param can be nil for host functions. -func newCompiler() compiler { - return newArm64Compiler() -} - -func registerMaskShift(r asm.Register) (ret int) { - ret = int(r - arm64.RegR0) - if r > arm64.RegSP { - // Skips arm64.RegSP which is not a real register. - ret-- - } - return -} - -func registerFromMaskShift(s int) asm.Register { - if s < 32 { - return arm64.RegR0 + asm.Register(s) - } else { - // Skips arm64.RegSP which is not a real register. - return arm64.RegR0 + asm.Register(s) + 1 - } -} diff --git a/internal/engine/compiler/arch_arm64.s b/internal/engine/compiler/arch_arm64.s deleted file mode 100644 index bec947286b..0000000000 --- a/internal/engine/compiler/arch_arm64.s +++ /dev/null @@ -1,21 +0,0 @@ -#include "funcdata.h" -#include "textflag.h" - -// nativecall(codeSegment, ce, moduleInstanceAddress) -TEXT ·nativecall(SB), NOSPLIT|NOFRAME, $0-24 - // Load the address of *callEngine into arm64ReservedRegisterForCallEngine. - MOVD ce+8(FP), R0 - - // In arm64, return address is stored in R30 after jumping into the code. - // We save the return address value into archContext.compilerReturnAddress in Engine. - // Note that the const 144 drifts after editting Engine or archContext struct. See TestArchContextOffsetInEngine. - MOVD R30, 144(R0) - - // Load the address of *wasm.ModuleInstance into arm64CallingConventionModuleInstanceAddressRegister. - MOVD moduleInstanceAddress+16(FP), R29 - - // Load the address of native code. - MOVD codeSegment+0(FP), R1 - - // Jump to native code. - JMP (R1) diff --git a/internal/engine/compiler/arch_arm64_test.go b/internal/engine/compiler/arch_arm64_test.go deleted file mode 100644 index 170ace6499..0000000000 --- a/internal/engine/compiler/arch_arm64_test.go +++ /dev/null @@ -1,15 +0,0 @@ -package compiler - -import ( - "testing" - "unsafe" - - "github.com/tetratelabs/wazero/internal/testing/require" -) - -func TestArchContextOffsetInArm64Engine(t *testing.T) { - var ctx callEngine - require.Equal(t, int(unsafe.Offsetof(ctx.compilerCallReturnAddress)), arm64CallEngineArchContextCompilerCallReturnAddressOffset, "fix consts in compiler_arm64.s") - require.Equal(t, int(unsafe.Offsetof(ctx.minimum32BitSignedInt)), arm64CallEngineArchContextMinimum32BitSignedIntOffset) - require.Equal(t, int(unsafe.Offsetof(ctx.minimum64BitSignedInt)), arm64CallEngineArchContextMinimum64BitSignedIntOffset) -} diff --git a/internal/engine/compiler/arch_other.go b/internal/engine/compiler/arch_other.go deleted file mode 100644 index e53ac8dffa..0000000000 --- a/internal/engine/compiler/arch_other.go +++ /dev/null @@ -1,26 +0,0 @@ -//go:build !amd64 && !arm64 - -package compiler - -import ( - "fmt" - "runtime" - - "github.com/tetratelabs/wazero/internal/asm" -) - -// archContext is empty on an unsupported architecture. -type archContext struct{} - -// newCompiler panics with an unsupported error. -func newCompiler() compiler { - panic(fmt.Sprintf("unsupported GOARCH %s", runtime.GOARCH)) -} - -func registerMaskShift(r asm.Register) (ret int) { - panic(fmt.Sprintf("unsupported GOARCH %s", runtime.GOARCH)) -} - -func registerFromMaskShift(s int) asm.Register { - panic(fmt.Sprintf("unsupported GOARCH %s", runtime.GOARCH)) -} diff --git a/internal/engine/compiler/arch_other.s b/internal/engine/compiler/arch_other.s deleted file mode 100644 index ad057fbb2b..0000000000 --- a/internal/engine/compiler/arch_other.s +++ /dev/null @@ -1,3 +0,0 @@ -//go:build !arm64 && !amd64 - -TEXT ·nativecall(SB), $0-16 diff --git a/internal/engine/compiler/compiler.go b/internal/engine/compiler/compiler.go deleted file mode 100644 index 3593df7bb9..0000000000 --- a/internal/engine/compiler/compiler.go +++ /dev/null @@ -1,366 +0,0 @@ -package compiler - -import ( - "github.com/tetratelabs/wazero/internal/asm" - "github.com/tetratelabs/wazero/internal/wasm" - "github.com/tetratelabs/wazero/internal/wazeroir" -) - -// compiler is the interface of architecture-specific native code compiler, -// and this is responsible for compiling native code for all wazeroir operations. -type compiler interface { - Init(functionType *wasm.FunctionType, ir *wazeroir.CompilationResult, withListener bool) - - // String is for debugging purpose. - String() string - // compilePreamble is called before compiling any wazeroir operation. - // This is used, for example, to initialize the reserved registers, etc. - compilePreamble() error - // compile generates the native code into buf. - // stackPointerCeil is the max stack pointer that the target function would reach. - compile(buf asm.Buffer) (stackPointerCeil uint64, err error) - // compileGoHostFunction adds the trampoline code from which native code can jump into the Go-defined host function. - // TODO: maybe we wouldn't need to have trampoline for host functions. - compileGoDefinedHostFunction() error - // compileLabel notify compilers of the beginning of a label. - // Return true if the compiler decided to skip the entire label. - // See wazeroir.NewOperationLabel - compileLabel(o *wazeroir.UnionOperation) (skipThisLabel bool) - // compileUnreachable adds instruction to perform wazeroir.OperationUnreachable. - compileUnreachable() error - // compileSet adds instruction to perform wazeroir.OperationSet. - compileSet(o *wazeroir.UnionOperation) error - // compileGlobalGet adds instructions to perform wazeroir.OperationGlobalGet. - compileGlobalGet(o *wazeroir.UnionOperation) error - // compileGlobalSet adds instructions to perform wazeroir.OperationGlobalSet. - compileGlobalSet(o *wazeroir.UnionOperation) error - // compileBr adds instructions to perform wazeroir.NewOperationBr. - compileBr(o *wazeroir.UnionOperation) error - // compileBrIf adds instructions to perform wazeroir.NewOperationBrIf. - compileBrIf(o *wazeroir.UnionOperation) error - // compileBrTable adds instructions to perform wazeroir.NewOperationBrTable. - compileBrTable(o *wazeroir.UnionOperation) error - // compileCall adds instructions to perform wazeroir.OperationCall. - compileCall(o *wazeroir.UnionOperation) error - // compileCallIndirect adds instructions to perform wazeroir.OperationCallIndirect. - compileCallIndirect(o *wazeroir.UnionOperation) error - // compileDrop adds instructions to perform wazeroir.NewOperationDrop. - compileDrop(o *wazeroir.UnionOperation) error - // compileSelect adds instructions to perform wazeroir.OperationSelect. - compileSelect(o *wazeroir.UnionOperation) error - // compilePick adds instructions to perform wazeroir.OperationPick. - compilePick(o *wazeroir.UnionOperation) error - // compileAdd adds instructions to perform wazeroir.OperationAdd. - compileAdd(o *wazeroir.UnionOperation) error - // compileSub adds instructions to perform wazeroir.OperationSub. - compileSub(o *wazeroir.UnionOperation) error - // compileMul adds instructions to perform wazeroir.OperationMul. - compileMul(o *wazeroir.UnionOperation) error - // compileClz adds instructions to perform wazeroir.OperationClz. - compileClz(o *wazeroir.UnionOperation) error - // compileCtz adds instructions to perform wazeroir.OperationCtz. - compileCtz(o *wazeroir.UnionOperation) error - // compilePopcnt adds instructions to perform wazeroir.OperationPopcnt. - compilePopcnt(o *wazeroir.UnionOperation) error - // compileDiv adds instructions to perform wazeroir.OperationDiv. - compileDiv(o *wazeroir.UnionOperation) error - // compileRem adds instructions to perform wazeroir.OperationRem. - compileRem(o *wazeroir.UnionOperation) error - // compileAnd adds instructions to perform wazeroir.OperationAnd. - compileAnd(o *wazeroir.UnionOperation) error - // compileOr adds instructions to perform wazeroir.OperationOr. - compileOr(o *wazeroir.UnionOperation) error - // compileXor adds instructions to perform wazeroir.OperationXor. - compileXor(o *wazeroir.UnionOperation) error - // compileShl adds instructions to perform wazeroir.OperationShl. - compileShl(o *wazeroir.UnionOperation) error - // compileShr adds instructions to perform wazeroir.OperationShr. - compileShr(o *wazeroir.UnionOperation) error - // compileRotl adds instructions to perform wazeroir.OperationRotl. - compileRotl(o *wazeroir.UnionOperation) error - // compileRotr adds instructions to perform wazeroir.OperationRotr. - compileRotr(o *wazeroir.UnionOperation) error - // compileNeg adds instructions to perform wazeroir.OperationAbs. - compileAbs(o *wazeroir.UnionOperation) error - // compileNeg adds instructions to perform wazeroir.OperationNeg. - compileNeg(o *wazeroir.UnionOperation) error - // compileCeil adds instructions to perform wazeroir.OperationCeil. - compileCeil(o *wazeroir.UnionOperation) error - // compileFloor adds instructions to perform wazeroir.OperationFloor. - compileFloor(o *wazeroir.UnionOperation) error - // compileTrunc adds instructions to perform wazeroir.OperationTrunc. - compileTrunc(o *wazeroir.UnionOperation) error - // compileNearest adds instructions to perform wazeroir.OperationNearest. - compileNearest(o *wazeroir.UnionOperation) error - // compileSqrt adds instructions perform wazeroir.OperationSqrt. - compileSqrt(o *wazeroir.UnionOperation) error - // compileMin adds instructions perform wazeroir.OperationMin. - compileMin(o *wazeroir.UnionOperation) error - // compileMax adds instructions perform wazeroir.OperationMax. - compileMax(o *wazeroir.UnionOperation) error - // compileCopysign adds instructions to perform wazeroir.OperationCopysign. - compileCopysign(o *wazeroir.UnionOperation) error - // compileI32WrapFromI64 adds instructions to perform wazeroir.OperationI32WrapFromI64. - compileI32WrapFromI64() error - // compileITruncFromF adds instructions to perform wazeroir.NewOperationITruncFromF. - compileITruncFromF(o *wazeroir.UnionOperation) error - // compileFConvertFromI adds instructions to perform wazeroir.NewOperationFConvertFromI. - compileFConvertFromI(o *wazeroir.UnionOperation) error - // compileF32DemoteFromF64 adds instructions to perform wazeroir.OperationF32DemoteFromF64. - compileF32DemoteFromF64() error - // compileF64PromoteFromF32 adds instructions to perform wazeroir.OperationF64PromoteFromF32. - compileF64PromoteFromF32() error - // compileI32ReinterpretFromF32 adds instructions to perform wazeroir.OperationI32ReinterpretFromF32. - compileI32ReinterpretFromF32() error - // compileI64ReinterpretFromF64 adds instructions to perform wazeroir.OperationI64ReinterpretFromF64. - compileI64ReinterpretFromF64() error - // compileF32ReinterpretFromI32 adds instructions to perform wazeroir.OperationF32ReinterpretFromI32. - compileF32ReinterpretFromI32() error - // compileF64ReinterpretFromI64 adds instructions to perform wazeroir.OperationF64ReinterpretFromI64. - compileF64ReinterpretFromI64() error - // compileExtend adds instructions to perform wazeroir.NewOperationExtend. - compileExtend(o *wazeroir.UnionOperation) error - // compileEq adds instructions to perform wazeroir.OperationEq. - compileEq(o *wazeroir.UnionOperation) error - // compileEq adds instructions to perform wazeroir.OperationNe. - compileNe(o *wazeroir.UnionOperation) error - // compileEq adds instructions to perform wazeroir.OperationEqz. - compileEqz(o *wazeroir.UnionOperation) error - // compileLt adds instructions to perform wazeroir.OperationLt. - compileLt(o *wazeroir.UnionOperation) error - // compileGt adds instructions to perform wazeroir.OperationGt. - compileGt(o *wazeroir.UnionOperation) error - // compileLe adds instructions to perform wazeroir.OperationLe. - compileLe(o *wazeroir.UnionOperation) error - // compileLe adds instructions to perform wazeroir.OperationGe. - compileGe(o *wazeroir.UnionOperation) error - // compileLoad adds instructions to perform wazeroir.OperationLoad. - compileLoad(o *wazeroir.UnionOperation) error - // compileLoad8 adds instructions to perform wazeroir.OperationLoad8. - compileLoad8(o *wazeroir.UnionOperation) error - // compileLoad16 adds instructions to perform wazeroir.OperationLoad16. - compileLoad16(o *wazeroir.UnionOperation) error - // compileLoad32 adds instructions to perform wazeroir.OperationLoad32. - compileLoad32(o *wazeroir.UnionOperation) error - // compileStore adds instructions to perform wazeroir.OperationStore. - compileStore(o *wazeroir.UnionOperation) error - // compileStore8 adds instructions to perform wazeroir.OperationStore8. - compileStore8(o *wazeroir.UnionOperation) error - // compileStore16 adds instructions to perform wazeroir.OperationStore16. - compileStore16(o *wazeroir.UnionOperation) error - // compileStore32 adds instructions to perform wazeroir.OperationStore32. - compileStore32(o *wazeroir.UnionOperation) error - // compileMemorySize adds instruction to perform wazeroir.OperationMemoryGrow. - compileMemoryGrow() error - // compileMemorySize adds instruction to perform wazeroir.OperationMemorySize. - compileMemorySize() error - // compileConstI32 adds instruction to perform wazeroir.NewOperationConstI32. - compileConstI32(o *wazeroir.UnionOperation) error - // compileConstI64 adds instruction to perform wazeroir.NewOperationConstI64. - compileConstI64(o *wazeroir.UnionOperation) error - // compileConstF32 adds instruction to perform wazeroir.NewOperationConstF32. - compileConstF32(o *wazeroir.UnionOperation) error - // compileConstF64 adds instruction to perform wazeroir.NewOperationConstF64. - compileConstF64(o *wazeroir.UnionOperation) error - // compileSignExtend32From8 adds instructions to perform wazeroir.OperationSignExtend32From8. - compileSignExtend32From8() error - // compileSignExtend32From16 adds instructions to perform wazeroir.OperationSignExtend32From16. - compileSignExtend32From16() error - // compileSignExtend64From8 adds instructions to perform wazeroir.OperationSignExtend64From8. - compileSignExtend64From8() error - // compileSignExtend64From16 adds instructions to perform wazeroir.OperationSignExtend64From16. - compileSignExtend64From16() error - // compileSignExtend64From32 adds instructions to perform wazeroir.OperationSignExtend64From32. - compileSignExtend64From32() error - // compileMemoryInit adds instructions to perform wazeroir.NewOperationMemoryInit. - compileMemoryInit(*wazeroir.UnionOperation) error - // compileDataDrop adds instructions to perform wazeroir.NewOperationDataDrop. - compileDataDrop(*wazeroir.UnionOperation) error - // compileMemoryCopy adds instructions to perform wazeroir.OperationMemoryCopy. - compileMemoryCopy() error - // compileMemoryFill adds instructions to perform wazeroir.OperationMemoryFill. - compileMemoryFill() error - // compileTableInit adds instructions to perform wazeroir.NewOperationTableInit. - compileTableInit(*wazeroir.UnionOperation) error - // compileTableCopy adds instructions to perform wazeroir.NewOperationTableCopy. - compileTableCopy(*wazeroir.UnionOperation) error - // compileElemDrop adds instructions to perform wazeroir.NewOperationElemDrop. - compileElemDrop(*wazeroir.UnionOperation) error - // compileRefFunc adds instructions to perform wazeroir.NewOperationRefFunc. - compileRefFunc(*wazeroir.UnionOperation) error - // compileTableGet adds instructions to perform wazeroir.NewOperationTableGet. - compileTableGet(*wazeroir.UnionOperation) error - // compileTableSet adds instructions to perform wazeroir.NewOperationTableSet. - compileTableSet(*wazeroir.UnionOperation) error - // compileTableGrow adds instructions to perform wazeroir.NewOperationTableGrow. - compileTableGrow(*wazeroir.UnionOperation) error - // compileTableSize adds instructions to perform wazeroir.NewOperationTableSize. - compileTableSize(*wazeroir.UnionOperation) error - // compileTableFill adds instructions to perform wazeroir.NewOperationTableFill. - compileTableFill(*wazeroir.UnionOperation) error - // compileV128Const adds instructions to perform wazeroir.NewOperationV128Const. - compileV128Const(*wazeroir.UnionOperation) error - // compileV128Add adds instructions to perform wazeroir.OperationV128Add. - compileV128Add(o *wazeroir.UnionOperation) error - // compileV128Sub adds instructions to perform wazeroir.OperationV128Sub. - compileV128Sub(o *wazeroir.UnionOperation) error - // compileV128Load adds instructions to perform wazeroir.OperationV128Load. - compileV128Load(o *wazeroir.UnionOperation) error - // compileV128LoadLane adds instructions to perform wazeroir.OperationV128LoadLane. - compileV128LoadLane(o *wazeroir.UnionOperation) error - // compileV128Store adds instructions to perform wazeroir.NewOperationV128Store. - compileV128Store(o *wazeroir.UnionOperation) error - // compileV128StoreLane adds instructions to perform wazeroir.NewOperationV128StoreLane. - compileV128StoreLane(o *wazeroir.UnionOperation) error - // compileV128ExtractLane adds instructions to perform wazeroir.NewOperationV128ExtractLane. - compileV128ExtractLane(o *wazeroir.UnionOperation) error - // compileV128ReplaceLane adds instructions to perform wazeroir.NewOperationV128ReplaceLane. - compileV128ReplaceLane(o *wazeroir.UnionOperation) error - // compileV128Splat adds instructions to perform wazeroir.NewOperationV128Splat. - compileV128Splat(o *wazeroir.UnionOperation) error - // compileV128Shuffle adds instructions to perform wazeroir.NewOperationV128Shuffle. - compileV128Shuffle(o *wazeroir.UnionOperation) error - // compileV128Swizzle adds instructions to perform wazeroir.OperationV128Swizzle. - compileV128Swizzle(o *wazeroir.UnionOperation) error - // compileV128AnyTrue adds instructions to perform wazeroir.OperationV128AnyTrue. - compileV128AnyTrue(o *wazeroir.UnionOperation) error - // compileV128AllTrue adds instructions to perform wazeroir.NewOperationV128AllTrue. - compileV128AllTrue(o *wazeroir.UnionOperation) error - // compileV128BitMask adds instructions to perform wazeroir.NewOperationV128BitMask. - compileV128BitMask(*wazeroir.UnionOperation) error - // compileV128And adds instructions to perform wazeroir.OperationV128And. - compileV128And(*wazeroir.UnionOperation) error - // compileV128Not adds instructions to perform wazeroir.OperationV128Not. - compileV128Not(*wazeroir.UnionOperation) error - // compileV128Or adds instructions to perform wazeroir.OperationV128Or. - compileV128Or(*wazeroir.UnionOperation) error - // compileV128Xor adds instructions to perform wazeroir.OperationV128Xor. - compileV128Xor(*wazeroir.UnionOperation) error - // compileV128Bitselect adds instructions to perform wazeroir.OperationV128Bitselect. - compileV128Bitselect(*wazeroir.UnionOperation) error - // compileV128AndNot adds instructions to perform wazeroir.OperationV128AndNot. - compileV128AndNot(*wazeroir.UnionOperation) error - // compileV128Shr adds instructions to perform wazeroir.NewOperationV128Shr. - compileV128Shr(*wazeroir.UnionOperation) error - // compileV128Shl adds instructions to perform wazeroir.NewOperationV128Shl. - compileV128Shl(*wazeroir.UnionOperation) error - // compileV128Cmp adds instructions to perform wazeroir.NewOperationV128Cmp. - compileV128Cmp(*wazeroir.UnionOperation) error - // compileV128AddSat adds instructions to perform wazeroir.NewOperationV128AddSat. - compileV128AddSat(*wazeroir.UnionOperation) error - // compileV128SubSat adds instructions to perform wazeroir.NewOperationV128SubSat. - compileV128SubSat(*wazeroir.UnionOperation) error - // compileV128Mul adds instructions to perform wazeroir.NewOperationV128Mul. - compileV128Mul(*wazeroir.UnionOperation) error - // compileV128Div adds instructions to perform wazeroir.NewOperationV128Div. - compileV128Div(*wazeroir.UnionOperation) error - // compileV128Neg adds instructions to perform wazeroir.NewOperationV128Neg. - compileV128Neg(*wazeroir.UnionOperation) error - // compileV128Sqrt adds instructions to perform wazeroir.NewOperationV128Sqrt. - compileV128Sqrt(*wazeroir.UnionOperation) error - // compileV128Abs adds instructions to perform wazeroir.NewOperationV128Abs. - compileV128Abs(*wazeroir.UnionOperation) error - // compileV128Popcnt adds instructions to perform wazeroir.NewOperationV128Popcnt. - compileV128Popcnt(*wazeroir.UnionOperation) error - // compileV128Min adds instructions to perform wazeroir.NewOperationV128Min. - compileV128Min(*wazeroir.UnionOperation) error - // compileV128Max adds instructions to perform wazeroir.NewOperationV128Max. - compileV128Max(*wazeroir.UnionOperation) error - // compileV128AvgrU adds instructions to perform wazeroir.NewOperationV128AvgrU. - compileV128AvgrU(*wazeroir.UnionOperation) error - // compileV128Pmin adds instructions to perform wazeroir.NewOperationV128Pmin. - compileV128Pmin(*wazeroir.UnionOperation) error - // compileV128Pmax adds instructions to perform wazeroir.NewOperationV128Pmax. - compileV128Pmax(*wazeroir.UnionOperation) error - // compileV128Ceil adds instructions to perform wazeroir.NewOperationV128Ceil. - compileV128Ceil(*wazeroir.UnionOperation) error - // compileV128Floor adds instructions to perform wazeroir.NewOperationV128Floor. - compileV128Floor(*wazeroir.UnionOperation) error - // compileV128Trunc adds instructions to perform wazeroir.NewOperationV128Trunc. - compileV128Trunc(*wazeroir.UnionOperation) error - // compileV128Nearest adds instructions to perform wazeroir.NewOperationV128Nearest. - compileV128Nearest(*wazeroir.UnionOperation) error - // compileV128Extend adds instructions to perform wazeroir.NewOperationV128Extend. - compileV128Extend(*wazeroir.UnionOperation) error - // compileV128ExtMul adds instructions to perform wazeroir.NewOperationV128ExtMul. - compileV128ExtMul(*wazeroir.UnionOperation) error - // compileV128Q15mulrSatS adds instructions to perform wazeroir.OperationV128Q15mulrSatS. - compileV128Q15mulrSatS(*wazeroir.UnionOperation) error - // compileV128ExtAddPairwise adds instructions to perform wazeroir.NewOperationV128ExtAddPairwise. - compileV128ExtAddPairwise(o *wazeroir.UnionOperation) error - // compileV128FloatPromote adds instructions to perform wazeroir.OperationV128FloatPromote. - compileV128FloatPromote(o *wazeroir.UnionOperation) error - // compileV128FloatDemote adds instructions to perform wazeroir.OperationV128FloatDemote. - compileV128FloatDemote(o *wazeroir.UnionOperation) error - // compileV128FConvertFromI adds instructions to perform wazeroir.NewOperationV128FConvertFromI. - compileV128FConvertFromI(o *wazeroir.UnionOperation) error - // compileV128Dot adds instructions to perform wazeroir.OperationV128Dot. - compileV128Dot(o *wazeroir.UnionOperation) error - // compileV128Narrow adds instructions to perform wazeroir.NewOperationV128Narrow. - compileV128Narrow(o *wazeroir.UnionOperation) error - // compileV128ITruncSatFromF adds instructions to perform wazeroir.NewOperationV128ITruncSatFromF. - compileV128ITruncSatFromF(o *wazeroir.UnionOperation) error - - // compileAtomicLoad adds instructions to perform wazeroir.NewOperationAtomicLoad. - compileAtomicLoad(o *wazeroir.UnionOperation) error - // compileAtomicLoad8 adds instructions to perform wazeroir.NewOperationAtomicLoad8. - compileAtomicLoad8(o *wazeroir.UnionOperation) error - // compileAtomicLoad16 adds instructions to perform wazeroir.NewOperationAtomicLoad16. - compileAtomicLoad16(o *wazeroir.UnionOperation) error - // compileAtomicStore adds instructions to perform wazeroir.NewOperationAtomicStore. - compileAtomicStore(o *wazeroir.UnionOperation) error - // compileAtomicStore8 adds instructions to perform wazeroir.NewOperationAtomicStore8. - compileAtomicStore8(o *wazeroir.UnionOperation) error - // compileAtomicStore16 adds instructions to perform wazeroir.NewOperationAtomicStore16. - compileAtomicStore16(o *wazeroir.UnionOperation) error - // compileAtomicRMW adds instructions to perform wazeroir.NewOperationAtomicRMW. - compileAtomicRMW(o *wazeroir.UnionOperation) error - // compileAtomicRMW8 adds instructions to perform wazeroir.NewOperationAtomicRMW8. - compileAtomicRMW8(o *wazeroir.UnionOperation) error - // compileAtomicRMW16 adds instructions to perform wazeroir.NewOperationAtomicRMW16. - compileAtomicRMW16(o *wazeroir.UnionOperation) error - // compileAtomicRMWCmpxchg adds instructions to perform wazeroir.NewOperationAtomicRMWCmpxchg. - compileAtomicRMWCmpxchg(o *wazeroir.UnionOperation) error - // compileAtomicRMW8Cmpxchg adds instructions to perform wazeroir.NewOperationAtomicRMW8Cmpxchg. - compileAtomicRMW8Cmpxchg(o *wazeroir.UnionOperation) error - // compileAtomicRMW16Cmpxchg adds instructions to perform wazeroir.NewOperationAtomicRMW16Cmpxchg. - compileAtomicRMW16Cmpxchg(o *wazeroir.UnionOperation) error - // compileAtomicMemoryWait adds instructions to perform wazeroir.NewOperationAtomicMemoryWait. - compileAtomicMemoryWait(o *wazeroir.UnionOperation) error - // compileAtomicMemoryNotify adds instructions to perform wazeroir.NewOperationAtomicMemoryNotify. - compileAtomicMemoryNotify(o *wazeroir.UnionOperation) error - // compileAtomicFence adds instructions to perform wazeroir.NewOperationAtomicFence - compileAtomicFence(o *wazeroir.UnionOperation) error - - // compileBuiltinFunctionCheckExitCode adds instructions to perform wazeroir.OperationBuiltinFunctionCheckExitCode. - compileBuiltinFunctionCheckExitCode() error - - // compileReleaseRegisterToStack adds instructions to write the value on a register back to memory stack region. - compileReleaseRegisterToStack(loc *runtimeValueLocation) - // compileLoadValueOnStackToRegister adds instructions to load the value located on the stack to the assigned register. - compileLoadValueOnStackToRegister(loc *runtimeValueLocation) - - // maybeCompileMoveTopConditionalToGeneralPurposeRegister moves the top value on the stack - // if the value is located on a conditional register. - // - // This is usually called at the beginning of methods on compiler interface where we possibly - // compile instructions without saving the conditional register value. - // The compileXXX functions without calling this function is saving the conditional - // value to the stack or register by invoking compileEnsureOnRegister for the top. - maybeCompileMoveTopConditionalToGeneralPurposeRegister() error - // allocateRegister returns an unused register of the given type. The register will be taken - // either from the free register pool or by stealing a used register. - // - // Note: resulting registers will not be marked as used so the call site should - // mark it used if necessary. - allocateRegister(t registerType) (reg asm.Register, err error) - // runtimeValueLocationStack returns the current runtimeValueLocationStack of the compiler implementation. - runtimeValueLocationStack() *runtimeValueLocationStack - // pushRuntimeValueLocationOnRegister pushes a new runtimeValueLocation on a register `reg` and of the type `vt`. - pushRuntimeValueLocationOnRegister(reg asm.Register, vt runtimeValueType) (ret *runtimeValueLocation) - // pushRuntimeValueLocationOnRegister pushes a new vector value's runtimeValueLocation on a register `reg`. - pushVectorRuntimeValueLocationOnRegister(reg asm.Register) (lowerBitsLocation *runtimeValueLocation) - // compileNOP compiles NOP instruction and returns the corresponding asm.Node in the assembled native code. - // This is used to emit DWARF based stack traces. - compileNOP() asm.Node -} diff --git a/internal/engine/compiler/compiler_bench_test.go b/internal/engine/compiler/compiler_bench_test.go deleted file mode 100644 index 8022a63e9a..0000000000 --- a/internal/engine/compiler/compiler_bench_test.go +++ /dev/null @@ -1,137 +0,0 @@ -package compiler - -import ( - "bytes" - "fmt" - "testing" - "unsafe" - - "github.com/tetratelabs/wazero/internal/asm" - "github.com/tetratelabs/wazero/internal/testing/require" - "github.com/tetratelabs/wazero/internal/wasm" - "github.com/tetratelabs/wazero/internal/wazeroir" -) - -func BenchmarkCompiler_compileMemoryCopy(b *testing.B) { - sizes := []uint32{5, 17, 128, 10000, 64000} - - for _, size := range sizes { - for _, overlap := range []bool{false, true} { - b.Run(fmt.Sprintf("%v-%v", size, overlap), func(b *testing.B) { - env := newCompilerEnvironment() - buf := asm.CodeSegment{} - defer func() { - require.NoError(b, buf.Unmap()) - }() - - mem := env.memory() - testMem := make([]byte, len(mem)) - for i := 0; i < len(mem); i++ { - mem[i] = byte(i) - testMem[i] = byte(i) - } - - compiler := newCompiler() - compiler.Init(&wasm.FunctionType{}, &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}, false) - err := compiler.compilePreamble() - require.NoError(b, err) - - var destOffset, sourceOffset uint32 - if !overlap { - destOffset, sourceOffset = 1, 777 - } else { - destOffset, sourceOffset = 777, 1 - } - - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(destOffset))) - require.NoError(b, err) - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(sourceOffset))) - require.NoError(b, err) - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(size))) - require.NoError(b, err) - err = compiler.compileMemoryCopy() - require.NoError(b, err) - err = compiler.(compilerImpl).compileReturnFunction() - - require.NoError(b, err) - _, err = compiler.compile(buf.NextCodeSection()) - require.NoError(b, err) - - env.execBench(b, buf.Bytes()) - - for i := 0; i < b.N; i += 1 { - copy(testMem[destOffset:destOffset+size], testMem[sourceOffset:sourceOffset+size]) - } - - if !bytes.Equal(mem, testMem) { - b.FailNow() - } - }) - } - } -} - -func BenchmarkCompiler_compileMemoryFill(b *testing.B) { - sizes := []uint32{5, 17, 128, 10000, 64000} - - for _, size := range sizes { - b.Run(fmt.Sprintf("%v", size), func(b *testing.B) { - env := newCompilerEnvironment() - buf := asm.CodeSegment{} - defer func() { - require.NoError(b, buf.Unmap()) - }() - - compiler := newCompiler() - compiler.Init(&wasm.FunctionType{}, &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}, false) - - var startOffset uint32 = 100 - var value uint8 = 5 - - err := compiler.compilePreamble() - require.NoError(b, err) - - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(startOffset))) - require.NoError(b, err) - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(uint32(value)))) - require.NoError(b, err) - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(size))) - require.NoError(b, err) - err = compiler.compileMemoryFill() - require.NoError(b, err) - err = compiler.(compilerImpl).compileReturnFunction() - require.NoError(b, err) - _, err = compiler.compile(buf.NextCodeSection()) - require.NoError(b, err) - - mem := env.memory() - testMem := make([]byte, len(mem)) - for i := 0; i < len(mem); i++ { - mem[i] = byte(i) - testMem[i] = byte(i) - } - - env.execBench(b, buf.Bytes()) - - for i := startOffset; i < startOffset+size; i++ { - testMem[i] = value - } - - for i := 0; i < len(mem); i++ { - require.Equal(b, mem[i], testMem[i], "mem != %d at offset %d", value, i) - } - }) - } -} - -func (j *compilerEnv) execBench(b *testing.B, codeSegment []byte) { - executable := requireExecutable(codeSegment) - b.StartTimer() - for i := 0; i < b.N; i++ { - nativecall( - uintptr(unsafe.Pointer(&executable[0])), - j.ce, j.moduleInstance, - ) - } - b.StopTimer() -} diff --git a/internal/engine/compiler/compiler_conditional_save_test.go b/internal/engine/compiler/compiler_conditional_save_test.go deleted file mode 100644 index 94869ae8fb..0000000000 --- a/internal/engine/compiler/compiler_conditional_save_test.go +++ /dev/null @@ -1,67 +0,0 @@ -package compiler - -import ( - "testing" - - "github.com/tetratelabs/wazero/internal/asm" - "github.com/tetratelabs/wazero/internal/testing/require" - "github.com/tetratelabs/wazero/internal/wasm" - "github.com/tetratelabs/wazero/internal/wazeroir" -) - -// TestCompiler_conditional_value_saving ensure that saving conditional register works correctly even if there's -// no free registers available. -func TestCompiler_conditional_value_saving(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, nil) - err := compiler.compilePreamble() - require.NoError(t, err) - - // Place the f32 local. - err = compiler.compileConstF32(operationPtr(wazeroir.NewOperationConstF32(1.0))) - require.NoError(t, err) - - // Generate constants to occupy all the unreserved GP registers. - for i := 0; i < len(unreservedGeneralPurposeRegisters); i++ { - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(100))) - require.NoError(t, err) - } - - // Pick the f32 floating point local (1.0) twice. - // Note that the f32 (function local variable in general) is placed above the call frame. - err = compiler.compilePick(operationPtr(wazeroir.NewOperationPick(int(compiler.runtimeValueLocationStack().sp-1-callFrameDataSizeInUint64), false))) - - require.NoError(t, err) - err = compiler.compilePick(operationPtr(wazeroir.NewOperationPick(int(compiler.runtimeValueLocationStack().sp-1-callFrameDataSizeInUint64), false))) - - require.NoError(t, err) - // Generate conditional flag via floating point comparisons. - err = compiler.compileLe(operationPtr(wazeroir.NewOperationLe(wazeroir.SignedTypeFloat32))) - require.NoError(t, err) - - // Ensures that we have conditional value at top of stack. - l := compiler.runtimeValueLocationStack().peek() - require.True(t, l.onConditionalRegister()) - - // Ensures that no free registers are available. - _, ok := compiler.runtimeValueLocationStack().takeFreeRegister(registerTypeGeneralPurpose) - require.False(t, ok) - - // We should be able to use the conditional value (an i32 value in Wasm) as an operand for, say, i32.add. - err = compiler.compileAdd(operationPtr(wazeroir.NewOperationAdd(wazeroir.UnsignedTypeI32))) - require.NoError(t, err) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - // expect 101 = 100(== the integer const) + 1 (== flag value == the result of (1.0 <= 1.0)) - require.Equal(t, uint32(101), env.stackTopAsUint32()) -} diff --git a/internal/engine/compiler/compiler_controlflow_test.go b/internal/engine/compiler/compiler_controlflow_test.go deleted file mode 100644 index 132a25ecb4..0000000000 --- a/internal/engine/compiler/compiler_controlflow_test.go +++ /dev/null @@ -1,943 +0,0 @@ -package compiler - -import ( - "fmt" - "testing" - "unsafe" - - "github.com/tetratelabs/wazero/internal/asm" - "github.com/tetratelabs/wazero/internal/testing/require" - "github.com/tetratelabs/wazero/internal/wasm" - "github.com/tetratelabs/wazero/internal/wazeroir" -) - -func TestCompiler_compileHostFunction(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, nil) - - err := compiler.compileGoDefinedHostFunction() - require.NoError(t, err) - - // Get the location of caller function's location stored in the stack, which depends on the type. - // In this test, the host function has empty sig. - _, _, callerFuncLoc := compiler.runtimeValueLocationStack().getCallFrameLocations(&wasm.FunctionType{}) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate the machine code for the test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - - // Set the caller's function which always exists in the real usecase. - f := &function{moduleInstance: &wasm.ModuleInstance{}} - env.stack()[callerFuncLoc.stackPointer] = uint64(uintptr(unsafe.Pointer(f))) - env.exec(code.Bytes()) - - // On the return, the code must exit with the host call status. - require.Equal(t, nativeCallStatusCodeCallGoHostFunction, env.compilerStatus()) - // Plus, the exitContext holds the caller's wasm.FunctionInstance. - require.Equal(t, f.moduleInstance, env.ce.exitContext.callerModuleInstance) - - // Re-enter the return address. - require.NotEqual(t, uintptr(0), uintptr(env.ce.returnAddress)) - nativecall(env.ce.returnAddress, env.callEngine(), env.module()) - - // After that, the code must exit with returned status. - require.Equal(t, nativeCallStatusCodeReturned, env.compilerStatus()) -} - -func TestCompiler_compileLabel(t *testing.T) { - label := wazeroir.NewLabel(wazeroir.LabelKindContinuation, 100) - for _, expectSkip := range []bool{false, true} { - expectSkip := expectSkip - t.Run(fmt.Sprintf("expect skip=%v", expectSkip), func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, nil) - - if expectSkip { - // If the initial stack is not set, compileLabel must return skip=true. - actual := compiler.compileLabel(operationPtr(wazeroir.NewOperationLabel(label))) - require.True(t, actual) - } else { - err := compiler.compileBr(operationPtr(wazeroir.NewOperationBr(label))) - require.NoError(t, err) - actual := compiler.compileLabel(operationPtr(wazeroir.NewOperationLabel(label))) - require.False(t, actual) - } - }) - } -} - -func TestCompiler_compileBrIf(t *testing.T) { - unreachableStatus, thenLabelExitStatus, elseLabelExitStatus := nativeCallStatusCodeUnreachable, nativeCallStatusCodeUnreachable+1, nativeCallStatusCodeUnreachable+2 - thenBranchTarget := wazeroir.NewLabel(wazeroir.LabelKindHeader, 1) - elseBranchTarget := wazeroir.NewLabel(wazeroir.LabelKindHeader, 2) - - tests := []struct { - name string - setupFunc func(t *testing.T, compiler compilerImpl, shouldGoElse bool) - }{ - { - name: "cond on register", - setupFunc: func(t *testing.T, compiler compilerImpl, shouldGoElse bool) { - val := uint32(1) - if shouldGoElse { - val = 0 - } - err := compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(val))) - require.NoError(t, err) - }, - }, - { - name: "LS", - setupFunc: func(t *testing.T, compiler compilerImpl, shouldGoElse bool) { - x1, x2 := uint32(1), uint32(2) - if shouldGoElse { - x2, x1 = x1, x2 - } - requirePushTwoInt32Consts(t, x1, x2, compiler) - // Le on unsigned integer produces the value on COND_LS register. - err := compiler.compileLe(operationPtr(wazeroir.NewOperationLe(wazeroir.SignedTypeUint32))) - require.NoError(t, err) - }, - }, - { - name: "LE", - setupFunc: func(t *testing.T, compiler compilerImpl, shouldGoElse bool) { - x1, x2 := uint32(1), uint32(2) - if shouldGoElse { - x2, x1 = x1, x2 - } - requirePushTwoInt32Consts(t, x1, x2, compiler) - // Le on signed integer produces the value on COND_LE register. - err := compiler.compileLe(operationPtr(wazeroir.NewOperationLe(wazeroir.SignedTypeInt32))) - require.NoError(t, err) - }, - }, - { - name: "HS", - setupFunc: func(t *testing.T, compiler compilerImpl, shouldGoElse bool) { - x1, x2 := uint32(2), uint32(1) - if shouldGoElse { - x2, x1 = x1, x2 - } - requirePushTwoInt32Consts(t, x1, x2, compiler) - // Ge on unsigned integer produces the value on COND_HS register. - err := compiler.compileGe(operationPtr(wazeroir.NewOperationGe(wazeroir.SignedTypeUint32))) - require.NoError(t, err) - }, - }, - { - name: "GE", - setupFunc: func(t *testing.T, compiler compilerImpl, shouldGoElse bool) { - x1, x2 := uint32(2), uint32(1) - if shouldGoElse { - x2, x1 = x1, x2 - } - requirePushTwoInt32Consts(t, x1, x2, compiler) - // Ge on signed integer produces the value on COND_GE register. - err := compiler.compileGe(operationPtr(wazeroir.NewOperationGe(wazeroir.SignedTypeInt32))) - require.NoError(t, err) - }, - }, - { - name: "HI", - setupFunc: func(t *testing.T, compiler compilerImpl, shouldGoElse bool) { - x1, x2 := uint32(2), uint32(1) - if shouldGoElse { - x2, x1 = x1, x2 - } - requirePushTwoInt32Consts(t, x1, x2, compiler) - // Gt on unsigned integer produces the value on COND_HI register. - err := compiler.compileGt(operationPtr(wazeroir.NewOperationGt(wazeroir.SignedTypeUint32))) - require.NoError(t, err) - }, - }, - { - name: "GT", - setupFunc: func(t *testing.T, compiler compilerImpl, shouldGoElse bool) { - x1, x2 := uint32(2), uint32(1) - if shouldGoElse { - x2, x1 = x1, x2 - } - requirePushTwoInt32Consts(t, x1, x2, compiler) - // Gt on signed integer produces the value on COND_GT register. - err := compiler.compileGt(operationPtr(wazeroir.NewOperationGt(wazeroir.SignedTypeInt32))) - require.NoError(t, err) - }, - }, - { - name: "LO", - setupFunc: func(t *testing.T, compiler compilerImpl, shouldGoElse bool) { - x1, x2 := uint32(1), uint32(2) - if shouldGoElse { - x2, x1 = x1, x2 - } - requirePushTwoInt32Consts(t, x1, x2, compiler) - // Lt on unsigned integer produces the value on COND_LO register. - err := compiler.compileLt(operationPtr(wazeroir.NewOperationLt(wazeroir.SignedTypeUint32))) - require.NoError(t, err) - }, - }, - { - name: "LT", - setupFunc: func(t *testing.T, compiler compilerImpl, shouldGoElse bool) { - x1, x2 := uint32(1), uint32(2) - if shouldGoElse { - x2, x1 = x1, x2 - } - requirePushTwoInt32Consts(t, x1, x2, compiler) - // Lt on signed integer produces the value on COND_LT register. - err := compiler.compileLt(operationPtr(wazeroir.NewOperationLt(wazeroir.SignedTypeInt32))) - require.NoError(t, err) - }, - }, - { - name: "MI", - setupFunc: func(t *testing.T, compiler compilerImpl, shouldGoElse bool) { - x1, x2 := float32(1), float32(2) - if shouldGoElse { - x2, x1 = x1, x2 - } - requirePushTwoFloat32Consts(t, x1, x2, compiler) - // Lt on floats produces the value on COND_MI register. - err := compiler.compileLt(operationPtr(wazeroir.NewOperationLt(wazeroir.SignedTypeFloat32))) - require.NoError(t, err) - }, - }, - { - name: "EQ", - setupFunc: func(t *testing.T, compiler compilerImpl, shouldGoElse bool) { - x1, x2 := uint32(1), uint32(1) - if shouldGoElse { - x2++ - } - requirePushTwoInt32Consts(t, x1, x2, compiler) - err := compiler.compileEq(operationPtr(wazeroir.NewOperationEq(wazeroir.UnsignedTypeI32))) - require.NoError(t, err) - }, - }, - { - name: "NE", - setupFunc: func(t *testing.T, compiler compilerImpl, shouldGoElse bool) { - x1, x2 := uint32(1), uint32(2) - if shouldGoElse { - x2 = x1 - } - requirePushTwoInt32Consts(t, x1, x2, compiler) - err := compiler.compileNe(operationPtr(wazeroir.NewOperationNe(wazeroir.UnsignedTypeI32))) - require.NoError(t, err) - }, - }, - } - - for _, tt := range tests { - tc := tt - t.Run(tc.name, func(t *testing.T) { - for _, shouldGoToElse := range []bool{false, true} { - shouldGoToElse := shouldGoToElse - t.Run(fmt.Sprintf("should_goto_else=%v", shouldGoToElse), func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, nil) - err := compiler.compilePreamble() - require.NoError(t, err) - - tc.setupFunc(t, compiler, shouldGoToElse) - requireRuntimeLocationStackPointerEqual(t, uint64(1), compiler) - - err = compiler.compileBrIf(operationPtr(wazeroir.NewOperationBrIf(thenBranchTarget, elseBranchTarget, wazeroir.NopInclusiveRange))) - require.NoError(t, err) - compiler.compileExitFromNativeCode(unreachableStatus) - - // Emit code for .then label. - skip := compiler.compileLabel(operationPtr(wazeroir.NewOperationLabel(thenBranchTarget))) - require.False(t, skip) - compiler.compileExitFromNativeCode(thenLabelExitStatus) - - // Emit code for .else label. - skip = compiler.compileLabel(operationPtr(wazeroir.NewOperationLabel(elseBranchTarget))) - require.False(t, skip) - compiler.compileExitFromNativeCode(elseLabelExitStatus) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - - // The generated code looks like this: - // - // ... code from compilePreamble() - // ... code from tc.setupFunc() - // br_if .then, .else - // exit $unreachableStatus - // .then: - // exit $thenLabelExitStatus - // .else: - // exit $elseLabelExitStatus - // - // Therefore, if we start executing from the top, we must end up exiting with an appropriate status. - env.exec(code.Bytes()) - require.NotEqual(t, unreachableStatus, env.compilerStatus()) - if shouldGoToElse { - require.Equal(t, elseLabelExitStatus, env.compilerStatus()) - } else { - require.Equal(t, thenLabelExitStatus, env.compilerStatus()) - } - }) - } - }) - } -} - -func TestCompiler_compileBrTable(t *testing.T) { - requireRunAndExpectedValueReturned := func(t *testing.T, env *compilerEnv, c compilerImpl, expValue uint32) { - // Emit code for each label which returns the frame ID. - for returnValue := uint32(0); returnValue < 7; returnValue++ { - label := wazeroir.NewLabel(wazeroir.LabelKindHeader, returnValue) - err := c.compileBr(operationPtr(wazeroir.NewOperationBr(label))) - require.NoError(t, err) - _ = c.compileLabel(operationPtr(wazeroir.NewOperationLabel(label))) - _ = c.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(uint32(label.FrameID())))) - err = c.compileReturnFunction() - require.NoError(t, err) - } - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate the code under test and run. - _, err := c.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - // Check the returned value. - require.Equal(t, uint64(1), env.stackPointer()) - require.Equal(t, expValue, env.stackTopAsUint32()) - } - - getBranchLabelFromFrameID := func(frameid uint32) uint64 { - return uint64(wazeroir.NewLabel(wazeroir.LabelKindHeader, frameid)) - } - - tests := []struct { - name string - index int64 - o *wazeroir.UnionOperation - expectedValue uint32 - }{ - { - name: "only default with index 0", - o: operationPtr(wazeroir.NewOperationBrTable([]uint64{ - getBranchLabelFromFrameID(6), - wazeroir.NopInclusiveRange.AsU64(), - })), - index: 0, - expectedValue: 6, - }, - { - name: "only default with index 100", - o: operationPtr(wazeroir.NewOperationBrTable([]uint64{ - getBranchLabelFromFrameID(6), - wazeroir.NopInclusiveRange.AsU64(), - })), - index: 100, - expectedValue: 6, - }, - { - name: "select default with targets and good index", - o: operationPtr(wazeroir.NewOperationBrTable([]uint64{ - getBranchLabelFromFrameID(1), - wazeroir.NopInclusiveRange.AsU64(), - getBranchLabelFromFrameID(2), - wazeroir.NopInclusiveRange.AsU64(), - getBranchLabelFromFrameID(6), // default - wazeroir.NopInclusiveRange.AsU64(), - })), - index: 3, - expectedValue: 6, - }, - { - name: "select default with targets and huge index", - o: operationPtr(wazeroir.NewOperationBrTable([]uint64{ - getBranchLabelFromFrameID(1), - wazeroir.NopInclusiveRange.AsU64(), - getBranchLabelFromFrameID(2), - wazeroir.NopInclusiveRange.AsU64(), - getBranchLabelFromFrameID(6), // default - wazeroir.NopInclusiveRange.AsU64(), - }, - )), - index: 100000, - expectedValue: 6, - }, - { - name: "select first with two targets", - o: operationPtr(wazeroir.NewOperationBrTable([]uint64{ - getBranchLabelFromFrameID(1), - wazeroir.NopInclusiveRange.AsU64(), - getBranchLabelFromFrameID(2), - wazeroir.NopInclusiveRange.AsU64(), - getBranchLabelFromFrameID(5), // default - wazeroir.NopInclusiveRange.AsU64(), - })), - index: 0, - expectedValue: 1, - }, - { - name: "select last with two targets", - o: operationPtr(wazeroir.NewOperationBrTable([]uint64{ - getBranchLabelFromFrameID(1), - wazeroir.NopInclusiveRange.AsU64(), - getBranchLabelFromFrameID(2), - wazeroir.NopInclusiveRange.AsU64(), - getBranchLabelFromFrameID(6), // default - wazeroir.NopInclusiveRange.AsU64(), - })), - index: 1, - expectedValue: 2, - }, - { - name: "select first with five targets", - o: operationPtr(wazeroir.NewOperationBrTable([]uint64{ - getBranchLabelFromFrameID(1), - wazeroir.NopInclusiveRange.AsU64(), - getBranchLabelFromFrameID(2), - wazeroir.NopInclusiveRange.AsU64(), - getBranchLabelFromFrameID(3), - wazeroir.NopInclusiveRange.AsU64(), - getBranchLabelFromFrameID(4), - wazeroir.NopInclusiveRange.AsU64(), - getBranchLabelFromFrameID(5), - wazeroir.NopInclusiveRange.AsU64(), - getBranchLabelFromFrameID(5), // default - wazeroir.NopInclusiveRange.AsU64(), - })), - index: 0, - expectedValue: 1, - }, - { - name: "select middle with five targets", - o: operationPtr(wazeroir.NewOperationBrTable([]uint64{ - getBranchLabelFromFrameID(1), - wazeroir.NopInclusiveRange.AsU64(), - getBranchLabelFromFrameID(2), - wazeroir.NopInclusiveRange.AsU64(), - getBranchLabelFromFrameID(3), - wazeroir.NopInclusiveRange.AsU64(), - getBranchLabelFromFrameID(4), - wazeroir.NopInclusiveRange.AsU64(), - getBranchLabelFromFrameID(5), - wazeroir.NopInclusiveRange.AsU64(), - getBranchLabelFromFrameID(5), // default - wazeroir.NopInclusiveRange.AsU64(), - })), - index: 2, - expectedValue: 3, - }, - { - name: "select last with five targets", - o: operationPtr(wazeroir.NewOperationBrTable([]uint64{ - getBranchLabelFromFrameID(1), - wazeroir.NopInclusiveRange.AsU64(), - getBranchLabelFromFrameID(2), - wazeroir.NopInclusiveRange.AsU64(), - getBranchLabelFromFrameID(3), - wazeroir.NopInclusiveRange.AsU64(), - getBranchLabelFromFrameID(4), - wazeroir.NopInclusiveRange.AsU64(), - getBranchLabelFromFrameID(5), - wazeroir.NopInclusiveRange.AsU64(), - getBranchLabelFromFrameID(5), // default - wazeroir.NopInclusiveRange.AsU64(), - })), - index: 4, - expectedValue: 5, - }, - } - - for _, tt := range tests { - tc := tt - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, nil) - - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(uint32(tc.index)))) - require.NoError(t, err) - - err = compiler.compileBrTable(tc.o) - require.NoError(t, err) - - require.Zero(t, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - - requireRunAndExpectedValueReturned(t, env, compiler, tc.expectedValue) - }) - } -} - -func requirePushTwoInt32Consts(t *testing.T, x1, x2 uint32, compiler compilerImpl) { - err := compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(x1))) - require.NoError(t, err) - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(x2))) - require.NoError(t, err) -} - -func requirePushTwoFloat32Consts(t *testing.T, x1, x2 float32, compiler compilerImpl) { - err := compiler.compileConstF32(operationPtr(wazeroir.NewOperationConstF32(x1))) - require.NoError(t, err) - err = compiler.compileConstF32(operationPtr(wazeroir.NewOperationConstF32(x2))) - require.NoError(t, err) -} - -func TestCompiler_compileBr(t *testing.T) { - t.Run("return", func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, nil) - err := compiler.compilePreamble() - require.NoError(t, err) - - // Branch into nil label is interpreted as return. See BranchTarget.IsReturnTarget - err = compiler.compileBr(operationPtr(wazeroir.NewOperationBr(wazeroir.NewLabel(wazeroir.LabelKindReturn, 0)))) - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Compile and execute the code under test. - // Note: we don't invoke "compiler.return()" as the code emitted by compilerBr is enough to exit. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - require.Equal(t, nativeCallStatusCodeReturned, env.compilerStatus()) - }) - t.Run("back-and-forth br", func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, nil) - err := compiler.compilePreamble() - require.NoError(t, err) - - // Emit the forward br, meaning that handle Br instruction where the target label hasn't been compiled yet. - forwardLabel := wazeroir.NewLabel(wazeroir.LabelKindHeader, 0) - err = compiler.compileBr(operationPtr(wazeroir.NewOperationBr(forwardLabel))) - require.NoError(t, err) - - // We must not reach the code after Br, so emit the code exiting with Unreachable status. - compiler.compileExitFromNativeCode(nativeCallStatusCodeUnreachable) - require.NoError(t, err) - - exitLabel := wazeroir.NewLabel(wazeroir.LabelKindHeader, 1) - err = compiler.compileBr(operationPtr(wazeroir.NewOperationBr(exitLabel))) - require.NoError(t, err) - - // Emit code for the exitLabel. - skip := compiler.compileLabel(operationPtr(wazeroir.NewOperationLabel(exitLabel))) - require.False(t, skip) - compiler.compileExitFromNativeCode(nativeCallStatusCodeReturned) - require.NoError(t, err) - - // Emit code for the forwardLabel. - skip = compiler.compileLabel(operationPtr(wazeroir.NewOperationLabel(forwardLabel))) - require.False(t, skip) - err = compiler.compileBr(operationPtr(wazeroir.NewOperationBr(exitLabel))) - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - - // The generated code looks like this:) - // - // ... code from compilePreamble() - // br .forwardLabel - // exit nativeCallStatusCodeUnreachable // must not be reached - // br .exitLabel // must not be reached - // .exitLabel: - // exit nativeCallStatusCodeReturned - // .forwardLabel: - // br .exitLabel - // - // Therefore, if we start executing from the top, we must end up exiting nativeCallStatusCodeReturned. - env.exec(code.Bytes()) - require.Equal(t, nativeCallStatusCodeReturned, env.compilerStatus()) - }) -} - -func TestCompiler_compileCallIndirect(t *testing.T) { - t.Run("out of bounds", func(t *testing.T) { - env := newCompilerEnvironment() - env.addTable(&wasm.TableInstance{References: make([]wasm.Reference, 10)}) - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, &wazeroir.CompilationResult{ - Types: []wasm.FunctionType{{}}, - HasTable: true, - }) - err := compiler.compilePreamble() - require.NoError(t, err) - - targetOperation := operationPtr(wazeroir.NewOperationCallIndirect(0, 0)) - - // Place the offset value. - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(10))) - require.NoError(t, err) - - err = compiler.compileCallIndirect(targetOperation) - require.NoError(t, err) - - // We expect to exit from the code in callIndirect so the subsequent code must be unreachable. - compiler.compileExitFromNativeCode(nativeCallStatusCodeUnreachable) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate the code under test and run. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - require.Equal(t, nativeCallStatusCodeInvalidTableAccess, env.compilerStatus()) - }) - - t.Run("uninitialized", func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, &wazeroir.CompilationResult{ - Types: []wasm.FunctionType{{}}, - HasTable: true, - }) - err := compiler.compilePreamble() - require.NoError(t, err) - - targetOperation := operationPtr(wazeroir.NewOperationCallIndirect(0, 0)) - targetOffset := operationPtr(wazeroir.NewOperationConstI32(uint32(0))) - - // and the typeID doesn't match the table[targetOffset]'s type ID. - table := make([]wasm.Reference, 10) - env.addTable(&wasm.TableInstance{References: table}) - env.module().TypeIDs = make([]wasm.FunctionTypeID, 10) - - // Place the offset value. - err = compiler.compileConstI32(targetOffset) - require.NoError(t, err) - err = compiler.compileCallIndirect(targetOperation) - require.NoError(t, err) - - // We expect to exit from the code in callIndirect so the subsequent code must be unreachable. - compiler.compileExitFromNativeCode(nativeCallStatusCodeUnreachable) - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate the code under test and run. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - require.Equal(t, nativeCallStatusCodeInvalidTableAccess, env.compilerStatus()) - }) - - t.Run("type not match", func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, &wazeroir.CompilationResult{ - Types: []wasm.FunctionType{{}}, - HasTable: true, - }) - err := compiler.compilePreamble() - require.NoError(t, err) - - targetOperation := operationPtr(wazeroir.NewOperationCallIndirect(0, 0)) - targetOffset := operationPtr(wazeroir.NewOperationConstI32(uint32(0))) - env.module().TypeIDs = []wasm.FunctionTypeID{1000} - // Ensure that the module instance has the type information for targetOperation.TypeIndex, - // and the typeID doesn't match the table[targetOffset]'s type ID. - table := make([]wasm.Reference, 10) - env.addTable(&wasm.TableInstance{References: table}) - - cf := &function{typeID: 50} - table[0] = uintptr(unsafe.Pointer(cf)) - - // Place the offset value. - err = compiler.compileConstI32(targetOffset) - require.NoError(t, err) - - // Now emit the code. - require.NoError(t, compiler.compileCallIndirect(targetOperation)) - - // We expect to exit from the code in callIndirect so the subsequent code must be unreachable. - compiler.compileExitFromNativeCode(nativeCallStatusCodeUnreachable) - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate the code under test and run. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - require.Equal(t, nativeCallStatusCodeTypeMismatchOnIndirectCall.String(), env.compilerStatus().String()) - }) - - t.Run("ok", func(t *testing.T) { - targetType := wasm.FunctionType{ - Results: []wasm.ValueType{wasm.ValueTypeI32}, - ResultNumInUint64: 1, - } - const typeIndex = 0 - targetTypeID := wasm.FunctionTypeID(10) - operation := operationPtr(wazeroir.NewOperationCallIndirect(typeIndex, 0)) - - table := make([]wasm.Reference, 10) - env := newCompilerEnvironment() - env.addTable(&wasm.TableInstance{References: table}) - - // Ensure that the module instance has the type information for targetOperation.TypeIndex, - // and the typeID matches the table[targetOffset]'s type ID. - env.module().TypeIDs = make([]wasm.FunctionTypeID, 100) - env.module().TypeIDs[typeIndex] = targetTypeID - env.module().Engine = &moduleEngine{functions: []function{}} - - me := env.moduleEngine() - me.functions = make([]function, len(table)) - for i := 0; i < len(table); i++ { - // First, we create the call target function for the table element i. - // To match its function type, it must return one value. - expectedReturnValue := uint32(i * 1000) - - compiler := env.requireNewCompiler(t, &targetType, newCompiler, &wazeroir.CompilationResult{}) - err := compiler.compilePreamble() - require.NoError(t, err) - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(expectedReturnValue))) - require.NoError(t, err) - - requireRuntimeLocationStackPointerEqual(t, uint64(2), compiler) - // The function result value must be set at the bottom of the stack. - err = compiler.compileSet(operationPtr(wazeroir.NewOperationSet(int(compiler.runtimeValueLocationStack().sp-1), false))) - require.NoError(t, err) - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - - makeExecutable(code.Bytes()) - - // Now that we've generated the code for this function, - // add it to the module engine and assign its pointer to the table index. - me.functions[i] = function{ - codeInitialAddress: uintptr(unsafe.Pointer(&code.Bytes()[0])), - moduleInstance: env.moduleInstance, - typeID: targetTypeID, - } - table[i] = uintptr(unsafe.Pointer(&me.functions[i])) - } - - // Test to ensure that we can call all the functions stored in the table. - for i := 1; i < len(table); i++ { - expectedReturnValue := uint32(i * 1000) - t.Run(fmt.Sprintf("%d", i), func(t *testing.T) { - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, - &wazeroir.CompilationResult{ - Types: []wasm.FunctionType{targetType}, - HasTable: true, - }, - ) - err := compiler.compilePreamble() - require.NoError(t, err) - - // Place the offset value. Here we try calling a function of functionaddr == table[i].FunctionIndex. - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(uint32(i)))) - require.NoError(t, err) - - // At this point, we should have one item (offset value) on the stack. - requireRuntimeLocationStackPointerEqual(t, 1, compiler) - - require.NoError(t, compiler.compileCallIndirect(operation)) - - // At this point, we consumed the offset value, but the function returns one value, - // so the stack pointer results in the same. - requireRuntimeLocationStackPointerEqual(t, 1, compiler) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate the code under test and run. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - require.Equal(t, nativeCallStatusCodeReturned.String(), env.compilerStatus().String()) - require.Equal(t, uint64(1), env.stackPointer()) - require.Equal(t, expectedReturnValue, uint32(env.ce.popValue())) - }) - } - }) -} - -// TestCompiler_callIndirect_largeTypeIndex ensures that non-trivial large type index works well during call_indirect. -// Note: any index larger than 8-bit range is considered as large for arm64 compiler. -func TestCompiler_callIndirect_largeTypeIndex(t *testing.T) { - env := newCompilerEnvironment() - table := make([]wasm.Reference, 1) - env.addTable(&wasm.TableInstance{References: table}) - // Ensure that the module instance has the type information for targetOperation.TypeIndex, - // and the typeID matches the table[targetOffset]'s type ID. - const typeIndex, typeID = 12345, 0 - operation := operationPtr(wazeroir.NewOperationCallIndirect(typeIndex, 0)) - env.module().TypeIDs = make([]wasm.FunctionTypeID, typeIndex+1) - env.module().TypeIDs[typeIndex] = typeID - env.module().Engine = &moduleEngine{functions: []function{}} - - types := make([]wasm.FunctionType, typeIndex+1) - types[typeIndex] = wasm.FunctionType{} - - code1 := asm.CodeSegment{} - code2 := asm.CodeSegment{} - defer func() { - require.NoError(t, code1.Unmap()) - require.NoError(t, code2.Unmap()) - }() - - me := env.moduleEngine() - { // Compiling call target. - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, nil) - err := compiler.compilePreamble() - require.NoError(t, err) - err = compiler.compileReturnFunction() - require.NoError(t, err) - - _, err = compiler.compile(code1.NextCodeSection()) - require.NoError(t, err) - - makeExecutable(code1.Bytes()) - f := function{ - parent: &compiledFunction{parent: &compiledCode{executable: code1}}, - codeInitialAddress: uintptr(unsafe.Pointer(&code1.Bytes()[0])), - moduleInstance: env.moduleInstance, - } - me.functions = append(me.functions, f) - table[0] = uintptr(unsafe.Pointer(&f)) - } - - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, &wazeroir.CompilationResult{ - Types: types, - HasTable: true, - }) - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(0))) - require.NoError(t, err) - - require.NoError(t, compiler.compileCallIndirect(operation)) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - // Generate the code under test and run. - _, err = compiler.compile(code2.NextCodeSection()) - require.NoError(t, err) - env.exec(code2.Bytes()) -} - -func TestCompiler_compileCall(t *testing.T) { - env := newCompilerEnvironment() - me := env.moduleEngine() - expectedValue := uint32(0) - - // Emit the call target function. - const numCalls = 3 - targetFunctionType := wasm.FunctionType{ - Params: []wasm.ValueType{wasm.ValueTypeI32}, - Results: []wasm.ValueType{wasm.ValueTypeI32}, - ParamNumInUint64: 1, ResultNumInUint64: 1, - } - - for i := 0; i < numCalls; i++ { - // Each function takes one argument, adds the value with 100 + i and returns the result. - addTargetValue := uint32(100 + i) - expectedValue += addTargetValue - compiler := env.requireNewCompiler(t, &targetFunctionType, newCompiler, &wazeroir.CompilationResult{}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(addTargetValue))) - require.NoError(t, err) - // Picks the function argument placed at the bottom of the stack. - err = compiler.compilePick(operationPtr(wazeroir.NewOperationPick(int(compiler.runtimeValueLocationStack().sp-1), false))) - require.NoError(t, err) - // Adds the const to the picked value. - err = compiler.compileAdd(operationPtr(wazeroir.NewOperationAdd(wazeroir.UnsignedTypeI32))) - require.NoError(t, err) - // Then store the added result into the bottom of the stack (which is treated as the result of the function). - err = compiler.compileSet(operationPtr(wazeroir.NewOperationSet(int(compiler.runtimeValueLocationStack().sp-1), false))) - require.NoError(t, err) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - - makeExecutable(code.Bytes()) - me.functions = append(me.functions, function{ - parent: &compiledFunction{parent: &compiledCode{executable: code}}, - codeInitialAddress: uintptr(unsafe.Pointer(&code.Bytes()[0])), - moduleInstance: env.moduleInstance, - }) - } - - // Now we start building the caller's code. - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, &wazeroir.CompilationResult{ - Functions: make([]uint32, numCalls), - Types: []wasm.FunctionType{targetFunctionType}, - }) - - err := compiler.compilePreamble() - require.NoError(t, err) - - const initialValue = 100 - expectedValue += initialValue - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(1234))) // Dummy value so the base pointer would be non-trivial for callees. - require.NoError(t, err) - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(initialValue))) - require.NoError(t, err) - - // Call all the built functions. - for i := 0; i < numCalls; i++ { - err = compiler.compileCall(operationPtr(wazeroir.NewOperationCall(1))) - require.NoError(t, err) - } - - // Set the result slot - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - // Check status and returned values. - require.Equal(t, nativeCallStatusCodeReturned, env.compilerStatus()) - require.Equal(t, uint64(0), env.stackBasePointer()) - require.Equal(t, uint64(2), env.stackPointer()) // Must be 2 (dummy value + the calculation results) - require.Equal(t, expectedValue, env.stackTopAsUint32()) -} diff --git a/internal/engine/compiler/compiler_conversion_test.go b/internal/engine/compiler/compiler_conversion_test.go deleted file mode 100644 index 265f3f32c8..0000000000 --- a/internal/engine/compiler/compiler_conversion_test.go +++ /dev/null @@ -1,563 +0,0 @@ -package compiler - -import ( - "fmt" - "math" - "testing" - - "github.com/tetratelabs/wazero/internal/asm" - "github.com/tetratelabs/wazero/internal/testing/require" - "github.com/tetratelabs/wazero/internal/wasm" - "github.com/tetratelabs/wazero/internal/wazeroir" -) - -func TestCompiler_compileReinterpret(t *testing.T) { - for _, kind := range []wazeroir.OperationKind{ - wazeroir.OperationKindF32ReinterpretFromI32, - wazeroir.OperationKindF64ReinterpretFromI64, - wazeroir.OperationKindI32ReinterpretFromF32, - wazeroir.OperationKindI64ReinterpretFromF64, - } { - kind := kind - t.Run(kind.String(), func(t *testing.T) { - for _, originOnStack := range []bool{false, true} { - originOnStack := originOnStack - t.Run(fmt.Sprintf("%v", originOnStack), func(t *testing.T) { - for _, v := range []uint64{ - 0, 1, 1 << 16, 1 << 31, 1 << 32, 1 << 63, - math.MaxInt32, math.MaxUint32, math.MaxUint64, - } { - v := v - t.Run(fmt.Sprintf("%d", v), func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, nil) - err := compiler.compilePreamble() - require.NoError(t, err) - - if originOnStack { - loc := compiler.runtimeValueLocationStack().pushRuntimeValueLocationOnStack() - env.stack()[loc.stackPointer] = v - env.setStackPointer(1) - } - - var is32Bit bool - switch kind { - case wazeroir.OperationKindF32ReinterpretFromI32: - is32Bit = true - if !originOnStack { - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(uint32(v)))) - require.NoError(t, err) - } - err = compiler.compileF32ReinterpretFromI32() - require.NoError(t, err) - case wazeroir.OperationKindF64ReinterpretFromI64: - if !originOnStack { - err = compiler.compileConstI64(operationPtr(wazeroir.NewOperationConstI64(v))) - require.NoError(t, err) - } - err = compiler.compileF64ReinterpretFromI64() - require.NoError(t, err) - case wazeroir.OperationKindI32ReinterpretFromF32: - is32Bit = true - if !originOnStack { - err = compiler.compileConstF32(operationPtr(wazeroir.NewOperationConstF32(math.Float32frombits(uint32(v))))) - require.NoError(t, err) - } - err = compiler.compileI32ReinterpretFromF32() - require.NoError(t, err) - case wazeroir.OperationKindI64ReinterpretFromF64: - if !originOnStack { - err = compiler.compileConstF64(operationPtr(wazeroir.NewOperationConstF64(math.Float64frombits(v)))) - require.NoError(t, err) - } - err = compiler.compileI64ReinterpretFromF64() - require.NoError(t, err) - default: - t.Fail() - } - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - // Reinterpret must preserve the bit-pattern. - if is32Bit { - require.Equal(t, uint32(v), env.stackTopAsUint32()) - } else { - require.Equal(t, v, env.stackTopAsUint64()) - } - }) - } - }) - } - }) - } -} - -func TestCompiler_compileExtend(t *testing.T) { - for _, signed := range []bool{false, true} { - signed := signed - t.Run(fmt.Sprintf("signed=%v", signed), func(t *testing.T) { - for _, v := range []uint32{ - 0, 1, 1 << 14, 1 << 31, math.MaxUint32, 0xFFFFFFFF, math.MaxInt32, - } { - v := v - t.Run(fmt.Sprintf("%v", v), func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, nil) - err := compiler.compilePreamble() - require.NoError(t, err) - - // Setup the promote target. - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(v))) - require.NoError(t, err) - - err = compiler.compileExtend(operationPtr(wazeroir.NewOperationExtend(signed))) - require.NoError(t, err) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - require.Equal(t, uint64(1), env.stackPointer()) - if signed { - expected := int64(int32(v)) - require.Equal(t, expected, env.stackTopAsInt64()) - } else { - expected := uint64(uint32(v)) - require.Equal(t, expected, env.stackTopAsUint64()) - } - }) - } - }) - } -} - -func TestCompiler_compileITruncFromF(t *testing.T) { - tests := []struct { - outputType wazeroir.SignedInt - inputType wazeroir.Float - nonTrapping bool - }{ - {outputType: wazeroir.SignedInt32, inputType: wazeroir.Float32}, - {outputType: wazeroir.SignedInt32, inputType: wazeroir.Float64}, - {outputType: wazeroir.SignedInt64, inputType: wazeroir.Float32}, - {outputType: wazeroir.SignedInt64, inputType: wazeroir.Float64}, - {outputType: wazeroir.SignedUint32, inputType: wazeroir.Float32}, - {outputType: wazeroir.SignedUint32, inputType: wazeroir.Float64}, - {outputType: wazeroir.SignedUint64, inputType: wazeroir.Float32}, - {outputType: wazeroir.SignedUint64, inputType: wazeroir.Float64}, - {outputType: wazeroir.SignedInt32, inputType: wazeroir.Float32, nonTrapping: true}, - {outputType: wazeroir.SignedInt32, inputType: wazeroir.Float64, nonTrapping: true}, - {outputType: wazeroir.SignedInt64, inputType: wazeroir.Float32, nonTrapping: true}, - {outputType: wazeroir.SignedInt64, inputType: wazeroir.Float64, nonTrapping: true}, - {outputType: wazeroir.SignedUint32, inputType: wazeroir.Float32, nonTrapping: true}, - {outputType: wazeroir.SignedUint32, inputType: wazeroir.Float64, nonTrapping: true}, - {outputType: wazeroir.SignedUint64, inputType: wazeroir.Float32, nonTrapping: true}, - {outputType: wazeroir.SignedUint64, inputType: wazeroir.Float64, nonTrapping: true}, - } - - for _, tt := range tests { - tc := tt - t.Run(fmt.Sprintf("%s from %s (non-trapping=%v)", tc.outputType, tc.inputType, tc.nonTrapping), func(t *testing.T) { - for _, v := range []float64{ - 1.0, - } { - v := v - if v == math.MaxInt32 { - // Note that math.MaxInt32 is rounded up to math.MaxInt32+1 in 32-bit float representation. - require.Equal(t, float32(2147483648.0) /* = math.MaxInt32+1 */, float32(v)) - } else if v == math.MaxUint32 { - // Note that math.MaxUint32 is rounded up to math.MaxUint32+1 in 32-bit float representation. - require.Equal(t, float32(4294967296 /* = math.MaxUint32+1 */), float32(v)) - } else if v == math.MaxInt64 { - // Note that math.MaxInt64 is rounded up to math.MaxInt64+1 in 32/64-bit float representation. - require.Equal(t, float32(9223372036854775808.0) /* = math.MaxInt64+1 */, float32(v)) - require.Equal(t, float64(9223372036854775808.0) /* = math.MaxInt64+1 */, float64(v)) - } else if v == math.MaxUint64 { - // Note that math.MaxUint64 is rounded up to math.MaxUint64+1 in 32/64-bit float representation. - require.Equal(t, float32(18446744073709551616.0) /* = math.MaxInt64+1 */, float32(v)) - require.Equal(t, float64(18446744073709551616.0) /* = math.MaxInt64+1 */, float64(v)) - } - - t.Run(fmt.Sprintf("%v", v), func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, nil) - err := compiler.compilePreamble() - require.NoError(t, err) - - // Setup the conversion target. - if tc.inputType == wazeroir.Float32 { - err = compiler.compileConstF32(operationPtr(wazeroir.NewOperationConstF32(float32(v)))) - } else { - err = compiler.compileConstF64(operationPtr(wazeroir.NewOperationConstF64(v))) - } - require.NoError(t, err) - - err = compiler.compileITruncFromF(operationPtr(wazeroir.NewOperationITruncFromF( - tc.inputType, tc.outputType, tc.nonTrapping, - ))) - require.NoError(t, err) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - // Check the result. - expStatus := nativeCallStatusCodeReturned - if math.IsNaN(v) { - if tc.nonTrapping { - v = 0 - } else { - expStatus = nativeCallStatusCodeInvalidFloatToIntConversion - } - } - if tc.inputType == wazeroir.Float32 && tc.outputType == wazeroir.SignedInt32 { - f32 := float32(v) - exp := int32(math.Trunc(float64(f32))) - if f32 < math.MinInt32 || f32 >= math.MaxInt32 { - if tc.nonTrapping { - if f32 < 0 { - exp = math.MinInt32 - } else { - exp = math.MaxInt32 - } - } else { - expStatus = nativeCallStatusIntegerOverflow - } - } - if expStatus == nativeCallStatusCodeReturned { - require.Equal(t, exp, env.stackTopAsInt32()) - } - } else if tc.inputType == wazeroir.Float32 && tc.outputType == wazeroir.SignedInt64 { - f32 := float32(v) - exp := int64(math.Trunc(float64(f32))) - if f32 < math.MinInt64 || f32 >= math.MaxInt64 { - if tc.nonTrapping { - if f32 < 0 { - exp = math.MinInt64 - } else { - exp = math.MaxInt64 - } - } else { - expStatus = nativeCallStatusIntegerOverflow - } - } - if expStatus == nativeCallStatusCodeReturned { - require.Equal(t, exp, env.stackTopAsInt64()) - } - } else if tc.inputType == wazeroir.Float64 && tc.outputType == wazeroir.SignedInt32 { - if v < math.MinInt32 || v > math.MaxInt32 { - if tc.nonTrapping { - if v < 0 { - v = math.MinInt32 - } else { - v = math.MaxInt32 - } - } else { - expStatus = nativeCallStatusIntegerOverflow - } - } - if expStatus == nativeCallStatusCodeReturned { - require.Equal(t, int32(math.Trunc(v)), env.stackTopAsInt32()) - } - } else if tc.inputType == wazeroir.Float64 && tc.outputType == wazeroir.SignedInt64 { - exp := int64(math.Trunc(v)) - if v < math.MinInt64 || v >= math.MaxInt64 { - if tc.nonTrapping { - if v < 0 { - exp = math.MinInt64 - } else { - exp = math.MaxInt64 - } - } else { - expStatus = nativeCallStatusIntegerOverflow - } - } - if expStatus == nativeCallStatusCodeReturned { - require.Equal(t, exp, env.stackTopAsInt64()) - } - } else if tc.inputType == wazeroir.Float32 && tc.outputType == wazeroir.SignedUint32 { - f32 := float32(v) - exp := uint32(math.Trunc(float64(f32))) - if f32 < 0 || f32 >= math.MaxUint32 { - if tc.nonTrapping { - if v < 0 { - exp = 0 - } else { - exp = math.MaxUint32 - } - } else { - expStatus = nativeCallStatusIntegerOverflow - } - } - if expStatus == nativeCallStatusCodeReturned { - require.Equal(t, exp, env.stackTopAsUint32()) - } - } else if tc.inputType == wazeroir.Float64 && tc.outputType == wazeroir.SignedUint32 { - exp := uint32(math.Trunc(v)) - if v < 0 || v > math.MaxUint32 { - if tc.nonTrapping { - if v < 0 { - exp = 0 - } else { - exp = math.MaxUint32 - } - } else { - expStatus = nativeCallStatusIntegerOverflow - } - } - if expStatus == nativeCallStatusCodeReturned { - require.Equal(t, exp, env.stackTopAsUint32()) - } - } else if tc.inputType == wazeroir.Float32 && tc.outputType == wazeroir.SignedUint64 { - f32 := float32(v) - exp := uint64(math.Trunc(float64(f32))) - if f32 < 0 || f32 >= math.MaxUint64 { - if tc.nonTrapping { - if v < 0 { - exp = 0 - } else { - exp = math.MaxUint64 - } - } else { - expStatus = nativeCallStatusIntegerOverflow - } - } - if expStatus == nativeCallStatusCodeReturned { - require.Equal(t, exp, env.stackTopAsUint64()) - } - } else if tc.inputType == wazeroir.Float64 && tc.outputType == wazeroir.SignedUint64 { - exp := uint64(math.Trunc(v)) - if v < 0 || v >= math.MaxUint64 { - if tc.nonTrapping { - if v < 0 { - exp = 0 - } else { - exp = math.MaxUint64 - } - } else { - expStatus = nativeCallStatusIntegerOverflow - } - } - if expStatus == nativeCallStatusCodeReturned { - require.Equal(t, exp, env.stackTopAsUint64()) - } - } - require.Equal(t, expStatus, env.compilerStatus()) - }) - } - }) - } -} - -func TestCompiler_compileFConvertFromI(t *testing.T) { - tests := []struct { - inputType wazeroir.SignedInt - outputType wazeroir.Float - }{ - {inputType: wazeroir.SignedInt32, outputType: wazeroir.Float32}, - {inputType: wazeroir.SignedInt32, outputType: wazeroir.Float64}, - {inputType: wazeroir.SignedInt64, outputType: wazeroir.Float32}, - {inputType: wazeroir.SignedInt64, outputType: wazeroir.Float64}, - {inputType: wazeroir.SignedUint32, outputType: wazeroir.Float32}, - {inputType: wazeroir.SignedUint32, outputType: wazeroir.Float64}, - {inputType: wazeroir.SignedUint64, outputType: wazeroir.Float32}, - {inputType: wazeroir.SignedUint64, outputType: wazeroir.Float64}, - } - - for _, tt := range tests { - tc := tt - t.Run(fmt.Sprintf("%s from %s", tc.outputType, tc.inputType), func(t *testing.T) { - for _, v := range []uint64{ - 0, 1, 12345, 1 << 31, 1 << 32, 1 << 54, 1 << 63, - 0xffff_ffff_ffff_ffff, 0xffff_ffff, - 0xffff_ffff_ffff_fffe, 0xffff_fffe, - math.MaxUint32, math.MaxUint64, math.MaxInt32, math.MaxInt64, - } { - t.Run(fmt.Sprintf("%d", v), func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, nil) - err := compiler.compilePreamble() - require.NoError(t, err) - - // Setup the conversion target. - if tc.inputType == wazeroir.SignedInt32 || tc.inputType == wazeroir.SignedUint32 { - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(uint32(v)))) - } else { - err = compiler.compileConstI64(operationPtr(wazeroir.NewOperationConstI64(uint64(v)))) - } - require.NoError(t, err) - - err = compiler.compileFConvertFromI(operationPtr(wazeroir.NewOperationFConvertFromI( - tc.inputType, tc.outputType, - ))) - require.NoError(t, err) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - // Check the result. - require.Equal(t, uint64(1), env.stackPointer()) - actualBits := env.stackTopAsUint64() - if tc.outputType == wazeroir.Float32 && tc.inputType == wazeroir.SignedInt32 { - exp := float32(int32(v)) - actual := math.Float32frombits(uint32(actualBits)) - require.Equal(t, exp, actual) - } else if tc.outputType == wazeroir.Float32 && tc.inputType == wazeroir.SignedInt64 { - exp := float32(int64(v)) - actual := math.Float32frombits(uint32(actualBits)) - require.Equal(t, exp, actual) - } else if tc.outputType == wazeroir.Float64 && tc.inputType == wazeroir.SignedInt32 { - exp := float64(int32(v)) - actual := math.Float64frombits(actualBits) - require.Equal(t, exp, actual) - } else if tc.outputType == wazeroir.Float64 && tc.inputType == wazeroir.SignedInt64 { - exp := float64(int64(v)) - actual := math.Float64frombits(actualBits) - require.Equal(t, exp, actual) - } else if tc.outputType == wazeroir.Float32 && tc.inputType == wazeroir.SignedUint32 { - exp := float32(uint32(v)) - actual := math.Float32frombits(uint32(actualBits)) - require.Equal(t, exp, actual) - } else if tc.outputType == wazeroir.Float64 && tc.inputType == wazeroir.SignedUint32 { - exp := float64(uint32(v)) - actual := math.Float64frombits(actualBits) - require.Equal(t, exp, actual) - } else if tc.outputType == wazeroir.Float32 && tc.inputType == wazeroir.SignedUint64 { - exp := float32(v) - actual := math.Float32frombits(uint32(actualBits)) - require.Equal(t, exp, actual) - } else if tc.outputType == wazeroir.Float64 && tc.inputType == wazeroir.SignedUint64 { - exp := float64(v) - actual := math.Float64frombits(actualBits) - require.Equal(t, exp, actual) - } - }) - } - }) - } -} - -func TestCompiler_compileF64PromoteFromF32(t *testing.T) { - for _, v := range []float32{ - 0, 100, -100, 1, -1, - 100.01234124, -100.01234124, 200.12315, - math.MaxFloat32, - math.SmallestNonzeroFloat32, - float32(math.Inf(1)), float32(math.Inf(-1)), float32(math.NaN()), - } { - t.Run(fmt.Sprintf("%f", v), func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, nil) - err := compiler.compilePreamble() - require.NoError(t, err) - - // Setup the promote target. - err = compiler.compileConstF32(operationPtr(wazeroir.NewOperationConstF32(v))) - require.NoError(t, err) - - err = compiler.compileF64PromoteFromF32() - require.NoError(t, err) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - // Check the result. - require.Equal(t, uint64(1), env.stackPointer()) - if math.IsNaN(float64(v)) { - require.True(t, math.IsNaN(env.stackTopAsFloat64())) - } else { - exp := float64(v) - actual := env.stackTopAsFloat64() - require.Equal(t, exp, actual) - } - }) - } -} - -func TestCompiler_compileF32DemoteFromF64(t *testing.T) { - for _, v := range []float64{ - 0, 100, -100, 1, -1, - 100.01234124, -100.01234124, 200.12315, - math.MaxFloat32, - math.SmallestNonzeroFloat32, - math.MaxFloat64, - math.SmallestNonzeroFloat64, - 6.8719476736e+10, /* = 1 << 36 */ - 1.37438953472e+11, /* = 1 << 37 */ - math.Inf(1), math.Inf(-1), math.NaN(), - } { - t.Run(fmt.Sprintf("%f", v), func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, nil) - err := compiler.compilePreamble() - require.NoError(t, err) - - // Setup the demote target. - err = compiler.compileConstF64(operationPtr(wazeroir.NewOperationConstF64(v))) - require.NoError(t, err) - - err = compiler.compileF32DemoteFromF64() - require.NoError(t, err) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - // Check the result. - require.Equal(t, uint64(1), env.stackPointer()) - if math.IsNaN(v) { - require.True(t, math.IsNaN(float64(env.stackTopAsFloat32()))) - } else { - exp := float32(v) - actual := env.stackTopAsFloat32() - require.Equal(t, exp, actual) - } - }) - } -} diff --git a/internal/engine/compiler/compiler_drop.go b/internal/engine/compiler/compiler_drop.go deleted file mode 100644 index 342cee0e1d..0000000000 --- a/internal/engine/compiler/compiler_drop.go +++ /dev/null @@ -1,126 +0,0 @@ -package compiler - -import ( - "github.com/tetratelabs/wazero/internal/asm" - "github.com/tetratelabs/wazero/internal/wazeroir" -) - -// compileDropRange adds instruction to drop the values on the target range -// in an architecture independent way. -func compileDropRange(c compiler, raw uint64) (err error) { - r := wazeroir.InclusiveRangeFromU64(raw) - locationStack := c.runtimeValueLocationStack() - if r.Start < 0 { - return - } else if r.Start == 0 { - for i := 0; i <= int(r.End); i++ { - if loc := locationStack.pop(); loc.onRegister() { - locationStack.releaseRegister(loc) - } - } - return - } - - // If the top value is alive, we must ensure that it is not located as a conditional. - // Otherwise, the conditional flag might end up modified by the following operation. - if err = c.maybeCompileMoveTopConditionalToGeneralPurposeRegister(); err != nil { - return - } - - dropValues, liveValues := locationStack.dropsLivesForInclusiveRange(r) - - // Frees all the registers used by drop target values. - for i := range dropValues { - dv := &dropValues[i] - if dv.onRegister() { - locationStack.releaseRegister(dv) - } - } - - // These registers are not nil if a live value of that type is currently located on the memory stack. - // In order to migrate these values, we can use them below. - gpTmp, vecTmp, err := getTemporariesForStackedLiveValues(c, liveValues) - if err != nil { - return err - } - - // Reset the stack pointer below the end. - locationStack.sp -= uint64(len(liveValues) + len(dropValues)) - - // Push back the live values again. - for i := range liveValues { - live := &liveValues[i] - migrateLiveValue(c, live, gpTmp, vecTmp) - } - return -} - -// migrateLiveValue migrates the live value `live` into the top of the stack. It might be located on the stack -// and in that case, we have to load it into either `generalPurposeTmpReg` or `vectorTmpReg` temporarily, and -// write it back into the *new* stack location. -func migrateLiveValue(c compiler, live *runtimeValueLocation, generalPurposeTmpReg, vectorTmpReg asm.Register) { - if live.valueType == runtimeValueTypeV128Hi { - // Higher bits of vector was already handled together with the lower bits. - return - } - - previouslyOnStack := live.onStack() - if previouslyOnStack { - // If the value is on the stack, load the value on the old location into the temporary value, - // and then write it back to the new memory location below. - switch live.getRegisterType() { - case registerTypeGeneralPurpose: - live.setRegister(generalPurposeTmpReg) - case registerTypeVector: - live.setRegister(vectorTmpReg) - } - // Load the value into tmp. - c.compileLoadValueOnStackToRegister(live) - } - - var newLocation *runtimeValueLocation - if live.valueType == runtimeValueTypeV128Lo { - newLocation = c.pushVectorRuntimeValueLocationOnRegister(live.register) - } else { - newLocation = c.pushRuntimeValueLocationOnRegister(live.register, live.valueType) - } - - if previouslyOnStack { - // This case, the location is on the temporary register. Therefore, - // we have to release the value there into the *new* memory location - // so that the tmp can be used for subsequent live value migrations. - c.compileReleaseRegisterToStack(newLocation) - } -} - -func getTemporariesForStackedLiveValues(c compiler, liveValues []runtimeValueLocation) (gpTmp, vecTmp asm.Register, err error) { - gpTmp, vecTmp = asm.NilRegister, asm.NilRegister - for i := range liveValues { - l := &liveValues[i] - if l.onStack() { - if rt := l.getRegisterType(); rt == registerTypeGeneralPurpose && gpTmp == asm.NilRegister { - gpTmp, err = c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return - } - } else if rt == registerTypeVector && vecTmp == asm.NilRegister { - vecTmp, err = c.allocateRegister(registerTypeVector) - if err != nil { - return - } - } - } - } - return -} - -// dropsLivesForInclusiveRange returns the live and drop target values for the given wazeroir.InclusiveRange. -func (v *runtimeValueLocationStack) dropsLivesForInclusiveRange( - r wazeroir.InclusiveRange, -) (dropValues, liveValues []runtimeValueLocation) { - // liveValues are must be pushed backed after dropping the target range. - liveValues = v.stack[v.sp-uint64(r.Start) : v.sp] - // dropValues are the values on the drop target range. - dropValues = v.stack[v.sp-uint64(r.End)-1 : v.sp-uint64(r.Start)] - return -} diff --git a/internal/engine/compiler/compiler_drop_test.go b/internal/engine/compiler/compiler_drop_test.go deleted file mode 100644 index 8ebbc5e9cb..0000000000 --- a/internal/engine/compiler/compiler_drop_test.go +++ /dev/null @@ -1,223 +0,0 @@ -package compiler - -import ( - "fmt" - "testing" - - "github.com/tetratelabs/wazero/internal/asm" - "github.com/tetratelabs/wazero/internal/testing/require" - "github.com/tetratelabs/wazero/internal/wasm" - "github.com/tetratelabs/wazero/internal/wazeroir" -) - -func Test_compileDropRange(t *testing.T) { - t.Run("nop range", func(t *testing.T) { - c := newCompiler() - - err := compileDropRange(c, wazeroir.NopInclusiveRange.AsU64()) - require.NoError(t, err) - }) - - t.Run("start at the top", func(t *testing.T) { - c := newCompiler() - c.Init(&wasm.FunctionType{}, nil, false) - - // Use up all unreserved registers. - for _, reg := range unreservedGeneralPurposeRegisters { - c.pushRuntimeValueLocationOnRegister(reg, runtimeValueTypeI32) - } - for i, vreg := range unreservedVectorRegisters { - // Mix and match scalar float and vector values. - if i%2 == 0 { - c.pushVectorRuntimeValueLocationOnRegister(vreg) - } else { - c.pushRuntimeValueLocationOnRegister(vreg, runtimeValueTypeF32) - } - } - - unreservedRegisterTotal := len(unreservedGeneralPurposeRegisters) + len(unreservedVectorRegisters) - ls := c.runtimeValueLocationStack() - require.Equal(t, unreservedRegisterTotal, len(ls.usedRegisters.list())) - - // Drop all the values. - err := compileDropRange(c, wazeroir.InclusiveRange{Start: 0, End: int32(ls.sp - 1)}.AsU64()) - require.NoError(t, err) - - // All the registers must be marked unused. - require.Equal(t, 0, len(ls.usedRegisters.list())) - // Also, stack pointer must be zero. - require.Equal(t, 0, int(ls.sp)) - }) -} - -func TestRuntimeValueLocationStack_dropsLivesForInclusiveRange(t *testing.T) { - tests := []struct { - v *runtimeValueLocationStack - ir wazeroir.InclusiveRange - lives, drops []runtimeValueLocation - }{ - { - v: &runtimeValueLocationStack{ - stack: []runtimeValueLocation{{register: 0}, {register: 1} /* drop target */, {register: 2}}, - sp: 3, - }, - ir: wazeroir.InclusiveRange{Start: 1, End: 1}, - drops: []runtimeValueLocation{{register: 1}}, - lives: []runtimeValueLocation{{register: 2}}, - }, - { - v: &runtimeValueLocationStack{ - stack: []runtimeValueLocation{ - {register: 0}, - {register: 1}, - {register: 2}, // drop target - {register: 3}, // drop target - {register: 4}, // drop target - {register: 5}, - {register: 6}, - }, - sp: 7, - }, - ir: wazeroir.InclusiveRange{Start: 2, End: 4}, - drops: []runtimeValueLocation{{register: 2}, {register: 3}, {register: 4}}, - lives: []runtimeValueLocation{{register: 5}, {register: 6}}, - }, - } - - for _, tc := range tests { - actualDrops, actualLives := tc.v.dropsLivesForInclusiveRange(tc.ir) - require.Equal(t, tc.drops, actualDrops) - require.Equal(t, tc.lives, actualLives) - } -} - -func Test_getTemporariesForStackedLiveValues(t *testing.T) { - t.Run("no stacked values", func(t *testing.T) { - liveValues := []runtimeValueLocation{{register: 1}, {register: 2}} - c := newCompiler() - c.Init(&wasm.FunctionType{}, nil, false) - - gpTmp, vecTmp, err := getTemporariesForStackedLiveValues(c, liveValues) - require.NoError(t, err) - - require.Equal(t, asm.NilRegister, gpTmp) - require.Equal(t, asm.NilRegister, vecTmp) - }) - t.Run("general purpose needed", func(t *testing.T) { - for _, freeRegisterExists := range []bool{false, true} { - freeRegisterExists := freeRegisterExists - t.Run(fmt.Sprintf("free register exists=%v", freeRegisterExists), func(t *testing.T) { - liveValues := []runtimeValueLocation{ - // Even multiple integer values are alive and on stack, - // only one general purpose register should be chosen. - {valueType: runtimeValueTypeI32}, - {valueType: runtimeValueTypeI64}, - } - c := newCompiler() - c.Init(&wasm.FunctionType{}, nil, false) - - if !freeRegisterExists { - // Use up all the unreserved gp registers. - for _, reg := range unreservedGeneralPurposeRegisters { - c.pushRuntimeValueLocationOnRegister(reg, runtimeValueTypeI32) - } - // Ensures actually we used them up all. - require.Equal(t, len(c.runtimeValueLocationStack().usedRegisters.list()), - len(unreservedGeneralPurposeRegisters)) - } - - gpTmp, vecTmp, err := getTemporariesForStackedLiveValues(c, liveValues) - require.NoError(t, err) - - if !freeRegisterExists { - // At this point, one register should be marked as unused. - require.Equal(t, len(c.runtimeValueLocationStack().usedRegisters.list()), - len(unreservedGeneralPurposeRegisters)-1) - } - - require.NotEqual(t, asm.NilRegister, gpTmp) - require.Equal(t, asm.NilRegister, vecTmp) - }) - } - }) - - t.Run("vector needed", func(t *testing.T) { - for _, freeRegisterExists := range []bool{false, true} { - freeRegisterExists := freeRegisterExists - t.Run(fmt.Sprintf("free register exists=%v", freeRegisterExists), func(t *testing.T) { - liveValues := []runtimeValueLocation{ - // Even multiple vectors are alive and on stack, - // only one vector register should be chosen. - {valueType: runtimeValueTypeF32}, - {valueType: runtimeValueTypeV128Lo}, - {valueType: runtimeValueTypeV128Hi}, - {valueType: runtimeValueTypeV128Lo}, - {valueType: runtimeValueTypeV128Hi}, - } - c := newCompiler() - c.Init(&wasm.FunctionType{}, nil, false) - - if !freeRegisterExists { - // Use up all the unreserved gp registers. - for _, reg := range unreservedVectorRegisters { - c.pushVectorRuntimeValueLocationOnRegister(reg) - } - // Ensures actually we used them up all. - require.Equal(t, len(c.runtimeValueLocationStack().usedRegisters.list()), - len(unreservedVectorRegisters)) - } - - gpTmp, vecTmp, err := getTemporariesForStackedLiveValues(c, liveValues) - require.NoError(t, err) - - if !freeRegisterExists { - // At this point, one register should be marked as unused. - require.Equal(t, len(c.runtimeValueLocationStack().usedRegisters.list()), - len(unreservedVectorRegisters)-1) - } - - require.Equal(t, asm.NilRegister, gpTmp) - require.NotEqual(t, asm.NilRegister, vecTmp) - }) - } - }) -} - -func Test_migrateLiveValue(t *testing.T) { - t.Run("v128.hi", func(t *testing.T) { - migrateLiveValue(nil, &runtimeValueLocation{valueType: runtimeValueTypeV128Hi}, asm.NilRegister, asm.NilRegister) - }) - t.Run("already on register", func(t *testing.T) { - // This case, we don't use tmp registers. - c := newCompiler() - c.Init(&wasm.FunctionType{}, nil, false) - - // Push the dummy values. - for i := 0; i < 10; i++ { - _ = c.runtimeValueLocationStack().pushRuntimeValueLocationOnStack() - } - - gpReg := unreservedGeneralPurposeRegisters[0] - vReg := unreservedVectorRegisters[0] - c.pushRuntimeValueLocationOnRegister(gpReg, runtimeValueTypeI64) - c.pushVectorRuntimeValueLocationOnRegister(vReg) - - // Emulate the compileDrop - ls := c.runtimeValueLocationStack() - vLive, gpLive := ls.popV128(), ls.pop() - const dropNum = 5 - ls.sp -= dropNum - - // Migrate these two values. - migrateLiveValue(c, gpLive, asm.NilRegister, asm.NilRegister) - migrateLiveValue(c, vLive, asm.NilRegister, asm.NilRegister) - - // Check the new stack location. - vectorMigrated, gpMigrated := ls.popV128(), ls.pop() - require.Equal(t, uint64(5), gpMigrated.stackPointer) - require.Equal(t, uint64(6), vectorMigrated.stackPointer) - - require.Equal(t, gpLive.register, gpMigrated.register) - require.Equal(t, vLive.register, vectorMigrated.register) - }) -} diff --git a/internal/engine/compiler/compiler_global_test.go b/internal/engine/compiler/compiler_global_test.go deleted file mode 100644 index 2729c5e679..0000000000 --- a/internal/engine/compiler/compiler_global_test.go +++ /dev/null @@ -1,221 +0,0 @@ -package compiler - -import ( - "testing" - - "github.com/tetratelabs/wazero/internal/asm" - "github.com/tetratelabs/wazero/internal/testing/require" - "github.com/tetratelabs/wazero/internal/wasm" - "github.com/tetratelabs/wazero/internal/wazeroir" -) - -func TestCompiler_compileGlobalGet(t *testing.T) { - const globalValue uint64 = 12345 - for _, tp := range []wasm.ValueType{ - wasm.ValueTypeF32, wasm.ValueTypeF64, wasm.ValueTypeI32, wasm.ValueTypeI64, wasm.ValueTypeExternref, wasm.ValueTypeFuncref, - } { - tp := tp - t.Run(wasm.ValueTypeName(tp), func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, &wazeroir.CompilationResult{ - Globals: []wasm.GlobalType{{}, {ValType: tp}}, - }) - - // Setup the global. (start with nil as a dummy so that global index can be non-trivial.) - globals := []*wasm.GlobalInstance{nil, {Val: globalValue, Type: wasm.GlobalType{ValType: tp}}} - env.addGlobals(globals...) - - // Emit the code. - err := compiler.compilePreamble() - require.NoError(t, err) - op := operationPtr(wazeroir.NewOperationGlobalGet(1)) - err = compiler.compileGlobalGet(op) - require.NoError(t, err) - - // At this point, the top of stack must be the retrieved global on a register. - global := compiler.runtimeValueLocationStack().peek() - require.True(t, global.onRegister()) - require.Equal(t, 1, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - switch tp { - case wasm.ValueTypeF32, wasm.ValueTypeF64: - require.True(t, isVectorRegister(global.register)) - case wasm.ValueTypeI32, wasm.ValueTypeI64: - require.True(t, isGeneralPurposeRegister(global.register)) - } - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - - // Run the code assembled above. - env.exec(code.Bytes()) - - // Since we call global.get, the top of the stack must be the global value. - require.Equal(t, globalValue, env.stackTopAsUint64()) - // Plus as we push the value, the stack pointer must be incremented. - require.Equal(t, uint64(1), env.stackPointer()) - }) - } -} - -func TestCompiler_compileGlobalGet_v128(t *testing.T) { - const v128Type = wasm.ValueTypeV128 - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, &wazeroir.CompilationResult{ - Globals: []wasm.GlobalType{{}, {ValType: v128Type}}, - }) - - // Setup the global. (start with nil as a dummy so that global index can be non-trivial.) - globals := []*wasm.GlobalInstance{nil, {Val: 12345, ValHi: 6789, Type: wasm.GlobalType{ValType: v128Type}}} - env.addGlobals(globals...) - - // Emit the code. - err := compiler.compilePreamble() - require.NoError(t, err) - op := operationPtr(wazeroir.NewOperationGlobalGet(1)) - err = compiler.compileGlobalGet(op) - require.NoError(t, err) - - // At this point, the top of stack must be the retrieved global on a register. - global := compiler.runtimeValueLocationStack().peek() - require.True(t, global.onRegister()) - require.Equal(t, 1, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - require.True(t, isVectorRegister(global.register)) - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - - // Run the code assembled above. - env.exec(code.Bytes()) - - require.Equal(t, uint64(2), env.stackPointer()) - require.Equal(t, nativeCallStatusCodeReturned, env.callEngine().statusCode) - - // Since we call global.get, the top of the stack must be the global value. - actual := globals[1] - sp := env.ce.stackContext.stackPointer - stack := env.stack() - require.Equal(t, actual.Val, stack[sp-2]) - require.Equal(t, actual.ValHi, stack[sp-1]) -} - -func TestCompiler_compileGlobalSet(t *testing.T) { - const valueToSet uint64 = 12345 - for _, tp := range []wasm.ValueType{ - wasm.ValueTypeF32, wasm.ValueTypeF64, - wasm.ValueTypeI32, wasm.ValueTypeI64, - wasm.ValueTypeExternref, wasm.ValueTypeFuncref, - } { - tp := tp - t.Run(wasm.ValueTypeName(tp), func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, &wazeroir.CompilationResult{ - Globals: []wasm.GlobalType{{}, {ValType: tp}}, - }) - - // Setup the global. (start with nil as a dummy so that global index can be non-trivial.) - env.addGlobals(nil, &wasm.GlobalInstance{Val: 40, Type: wasm.GlobalType{ValType: tp}}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - // Place the set target value. - loc := compiler.runtimeValueLocationStack().pushRuntimeValueLocationOnStack() - switch tp { - case wasm.ValueTypeI32: - loc.valueType = runtimeValueTypeI32 - case wasm.ValueTypeI64, wasm.ValueTypeExternref, wasm.ValueTypeFuncref: - loc.valueType = runtimeValueTypeI64 - case wasm.ValueTypeF32: - loc.valueType = runtimeValueTypeF32 - case wasm.ValueTypeF64: - loc.valueType = runtimeValueTypeF64 - } - env.stack()[loc.stackPointer] = valueToSet - - const index = 1 - op := operationPtr(wazeroir.NewOperationGlobalSet(index)) - err = compiler.compileGlobalSet(op) - requireRuntimeLocationStackPointerEqual(t, 0, compiler) - - require.NoError(t, err) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - // The global value should be set to valueToSet. - actual := env.globals()[index] - require.Equal(t, valueToSet, actual.Val) - // Plus we consumed the top of the stack, the stack pointer must be decremented. - require.Equal(t, uint64(0), env.stackPointer()) - }) - } -} - -func TestCompiler_compileGlobalSet_v128(t *testing.T) { - const v128Type = wasm.ValueTypeV128 - const valueToSetLo, valueToSetHi uint64 = 0xffffff, 1 - - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, &wazeroir.CompilationResult{ - Globals: []wasm.GlobalType{{}, {ValType: v128Type}}, - }) - - // Setup the global. (start with nil as a dummy so that global index can be non-trivial.) - env.addGlobals(nil, &wasm.GlobalInstance{Val: 0, ValHi: 0, Type: wasm.GlobalType{ValType: v128Type}}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - // Place the set target value. - lo := compiler.runtimeValueLocationStack().pushRuntimeValueLocationOnStack() - lo.valueType = runtimeValueTypeV128Lo - env.stack()[lo.stackPointer] = valueToSetLo - hi := compiler.runtimeValueLocationStack().pushRuntimeValueLocationOnStack() - hi.valueType = runtimeValueTypeV128Hi - env.stack()[hi.stackPointer] = valueToSetHi - - const index = 1 - op := operationPtr(wazeroir.NewOperationGlobalSet(index)) - err = compiler.compileGlobalSet(op) - requireRuntimeLocationStackPointerEqual(t, 0, compiler) - require.NoError(t, err) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - require.Equal(t, uint64(0), env.stackPointer()) - require.Equal(t, nativeCallStatusCodeReturned, env.callEngine().statusCode) - - // The global value should be set to valueToSet. - actual := env.globals()[index] - require.Equal(t, valueToSetLo, actual.Val) - require.Equal(t, valueToSetHi, actual.ValHi) -} diff --git a/internal/engine/compiler/compiler_initialization_test.go b/internal/engine/compiler/compiler_initialization_test.go deleted file mode 100644 index 843e5d8ba4..0000000000 --- a/internal/engine/compiler/compiler_initialization_test.go +++ /dev/null @@ -1,283 +0,0 @@ -package compiler - -import ( - "fmt" - "reflect" - "testing" - "unsafe" - - "github.com/tetratelabs/wazero/internal/asm" - "github.com/tetratelabs/wazero/internal/testing/require" - "github.com/tetratelabs/wazero/internal/wasm" - "github.com/tetratelabs/wazero/internal/wazeroir" -) - -func TestCompiler_compileModuleContextInitialization(t *testing.T) { - tests := []struct { - name string - moduleInstance *wasm.ModuleInstance - memoryType wazeroir.MemoryType - }{ - { - name: "no nil", - moduleInstance: &wasm.ModuleInstance{ - Globals: []*wasm.GlobalInstance{{Val: 100}}, - MemoryInstance: &wasm.MemoryInstance{Buffer: make([]byte, 10)}, - Tables: []*wasm.TableInstance{ - {References: make([]wasm.Reference, 20)}, - {References: make([]wasm.Reference, 10)}, - }, - TypeIDs: make([]wasm.FunctionTypeID, 10), - DataInstances: make([][]byte, 10), - ElementInstances: make([]wasm.ElementInstance, 10), - }, - memoryType: wazeroir.MemoryTypeStandard, - }, - { - name: "element instances nil", - moduleInstance: &wasm.ModuleInstance{ - Globals: []*wasm.GlobalInstance{{Val: 100}}, - MemoryInstance: &wasm.MemoryInstance{Buffer: make([]byte, 10)}, - Tables: []*wasm.TableInstance{{References: make([]wasm.Reference, 20)}}, - TypeIDs: make([]wasm.FunctionTypeID, 10), - DataInstances: make([][]byte, 10), - ElementInstances: nil, - }, - memoryType: wazeroir.MemoryTypeStandard, - }, - { - name: "data instances nil", - moduleInstance: &wasm.ModuleInstance{ - Globals: []*wasm.GlobalInstance{{Val: 100}}, - MemoryInstance: &wasm.MemoryInstance{Buffer: make([]byte, 10)}, - Tables: []*wasm.TableInstance{{References: make([]wasm.Reference, 20)}}, - TypeIDs: make([]wasm.FunctionTypeID, 10), - DataInstances: nil, - ElementInstances: make([]wasm.ElementInstance, 10), - }, - memoryType: wazeroir.MemoryTypeStandard, - }, - { - name: "globals nil", - moduleInstance: &wasm.ModuleInstance{ - MemoryInstance: &wasm.MemoryInstance{Buffer: make([]byte, 10)}, - Tables: []*wasm.TableInstance{{References: make([]wasm.Reference, 20)}}, - TypeIDs: make([]wasm.FunctionTypeID, 10), - DataInstances: make([][]byte, 10), - ElementInstances: make([]wasm.ElementInstance, 10), - }, - memoryType: wazeroir.MemoryTypeStandard, - }, - { - name: "memory nil", - moduleInstance: &wasm.ModuleInstance{ - Globals: []*wasm.GlobalInstance{{Val: 100}}, - Tables: []*wasm.TableInstance{{References: make([]wasm.Reference, 20)}}, - TypeIDs: make([]wasm.FunctionTypeID, 10), - DataInstances: make([][]byte, 10), - ElementInstances: make([]wasm.ElementInstance, 10), - }, - }, - { - name: "table nil", - moduleInstance: &wasm.ModuleInstance{ - MemoryInstance: &wasm.MemoryInstance{Buffer: make([]byte, 10)}, - Tables: []*wasm.TableInstance{{References: nil}}, - TypeIDs: make([]wasm.FunctionTypeID, 10), - DataInstances: make([][]byte, 10), - ElementInstances: make([]wasm.ElementInstance, 10), - }, - memoryType: wazeroir.MemoryTypeStandard, - }, - { - name: "table empty", - moduleInstance: &wasm.ModuleInstance{ - Tables: []*wasm.TableInstance{{References: make([]wasm.Reference, 20)}}, - TypeIDs: make([]wasm.FunctionTypeID, 10), - DataInstances: make([][]byte, 10), - ElementInstances: make([]wasm.ElementInstance, 10), - }, - }, - { - name: "memory zero length", - moduleInstance: &wasm.ModuleInstance{ - MemoryInstance: &wasm.MemoryInstance{Buffer: make([]byte, 0)}, - }, - memoryType: wazeroir.MemoryTypeStandard, - }, - { - name: "memory shared", - moduleInstance: &wasm.ModuleInstance{ - MemoryInstance: &wasm.MemoryInstance{Buffer: make([]byte, 10), Shared: true}, - }, - memoryType: wazeroir.MemoryTypeShared, - }, - { - name: "all nil except mod engine", - moduleInstance: &wasm.ModuleInstance{}, - }, - } - - for _, tt := range tests { - tc := tt - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - env.moduleInstance = tc.moduleInstance - ce := env.callEngine() - - ir := &wazeroir.CompilationResult{ - Memory: tc.memoryType, - HasTable: len(tc.moduleInstance.Tables) > 0, - HasDataInstances: len(tc.moduleInstance.DataInstances) > 0, - HasElementInstances: len(tc.moduleInstance.ElementInstances) > 0, - } - for _, g := range tc.moduleInstance.Globals { - ir.Globals = append(ir.Globals, g.Type) - } - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, ir) - me := &moduleEngine{functions: make([]function, 10)} - tc.moduleInstance.Engine = me - - err := compiler.compileModuleContextInitialization() - require.NoError(t, err) - require.Zero(t, len(compiler.runtimeValueLocationStack().usedRegisters.list()), "expected no usedRegisters") - - compiler.compileExitFromNativeCode(nativeCallStatusCodeReturned) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - - env.exec(code.Bytes()) - - // Check the exit status. - require.Equal(t, nativeCallStatusCodeReturned, env.compilerStatus()) - - // Check if the fields of callEngine.moduleContext are updated. - bufSliceHeader := (*reflect.SliceHeader)(unsafe.Pointer(&tc.moduleInstance.Globals)) - require.Equal(t, bufSliceHeader.Data, ce.moduleContext.globalElement0Address) - - if tc.moduleInstance.MemoryInstance != nil { - bufSliceHeader := (*reflect.SliceHeader)(unsafe.Pointer(&tc.moduleInstance.MemoryInstance.Buffer)) - require.Equal(t, uint64(bufSliceHeader.Len), ce.moduleContext.memorySliceLen) - require.Equal(t, bufSliceHeader.Data, ce.moduleContext.memoryElement0Address) - require.Equal(t, tc.moduleInstance.MemoryInstance, ce.moduleContext.memoryInstance) - } - - if len(tc.moduleInstance.Tables) > 0 { - tableHeader := (*reflect.SliceHeader)(unsafe.Pointer(&tc.moduleInstance.Tables)) - require.Equal(t, tableHeader.Data, ce.moduleContext.tablesElement0Address) - require.Equal(t, uintptr(unsafe.Pointer(&tc.moduleInstance.TypeIDs[0])), ce.moduleContext.typeIDsElement0Address) - require.Equal(t, uintptr(unsafe.Pointer(&tc.moduleInstance.Tables[0])), ce.moduleContext.tablesElement0Address) - } - - if len(tc.moduleInstance.DataInstances) > 0 { - dataInstancesHeader := (*reflect.SliceHeader)(unsafe.Pointer(&tc.moduleInstance.DataInstances)) - require.Equal(t, dataInstancesHeader.Data, ce.moduleContext.dataInstancesElement0Address) - require.Equal(t, uintptr(unsafe.Pointer(&tc.moduleInstance.DataInstances[0])), ce.moduleContext.dataInstancesElement0Address) - } - - if len(tc.moduleInstance.ElementInstances) > 0 { - elementInstancesHeader := (*reflect.SliceHeader)(unsafe.Pointer(&tc.moduleInstance.ElementInstances)) - require.Equal(t, elementInstancesHeader.Data, ce.moduleContext.elementInstancesElement0Address) - require.Equal(t, uintptr(unsafe.Pointer(&tc.moduleInstance.ElementInstances[0])), ce.moduleContext.elementInstancesElement0Address) - } - - require.Equal(t, uintptr(unsafe.Pointer(&me.functions[0])), ce.moduleContext.functionsElement0Address) - }) - } -} - -func TestCompiler_compileMaybeGrowStack(t *testing.T) { - t.Run("not grow", func(t *testing.T) { - const stackPointerCeil = 5 - for _, baseOffset := range []uint64{5, 10, 20} { - t.Run(fmt.Sprintf("%d", baseOffset), func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, nil) - - err := compiler.compilePreamble() - require.NoError(t, err) - - stackLen := uint64(len(env.stack())) - stackBasePointer := stackLen - baseOffset // Ceil <= stackLen - stackBasePointer = no need to grow! - compiler.assignStackPointerCeil(stackPointerCeil) - env.setStackBasePointer(stackBasePointer) - - compiler.compileExitFromNativeCode(nativeCallStatusCodeReturned) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - // The status code must be "Returned", not "BuiltinFunctionCall". - require.Equal(t, nativeCallStatusCodeReturned, env.compilerStatus()) - }) - } - }) - - defaultStackLen := uint64(initialStackSize) - t.Run("grow", func(t *testing.T) { - tests := []struct { - name string - stackPointerCeil uint64 - stackBasePointer uint64 - }{ - { - name: "ceil=6/sbp=len-5", - stackPointerCeil: 6, - stackBasePointer: defaultStackLen - 5, - }, - { - name: "ceil=10000/sbp=0", - stackPointerCeil: 10000, - stackBasePointer: 0, - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, nil) - - err := compiler.compilePreamble() - require.NoError(t, err) - - // On the return from grow value stack, we simply return. - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate code under test with the given stackPointerCeil. - compiler.setStackPointerCeil(tc.stackPointerCeil) - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - - // And run the code with the specified stackBasePointer. - env.setStackBasePointer(tc.stackBasePointer) - env.exec(code.Bytes()) - - // Check if the call exits with builtin function call status. - require.Equal(t, nativeCallStatusCodeCallBuiltInFunction, env.compilerStatus()) - - // Reenter from the return address. - returnAddress := env.ce.returnAddress - require.True(t, returnAddress != 0, "returnAddress was zero %d", returnAddress) - nativecall(returnAddress, env.callEngine(), env.module()) - - // Check the result. This should be "Returned". - require.Equal(t, nativeCallStatusCodeReturned, env.compilerStatus()) - }) - } - }) -} diff --git a/internal/engine/compiler/compiler_memory_test.go b/internal/engine/compiler/compiler_memory_test.go deleted file mode 100644 index c66aafc54a..0000000000 --- a/internal/engine/compiler/compiler_memory_test.go +++ /dev/null @@ -1,497 +0,0 @@ -package compiler - -import ( - "encoding/binary" - "fmt" - "math" - "testing" - - "github.com/tetratelabs/wazero/internal/asm" - "github.com/tetratelabs/wazero/internal/testing/require" - "github.com/tetratelabs/wazero/internal/wasm" - "github.com/tetratelabs/wazero/internal/wazeroir" -) - -func TestCompiler_compileMemoryGrow(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, nil) - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileMemoryGrow() - require.NoError(t, err) - - // Emit arbitrary code after MemoryGrow returned so that we can verify - // that the code can set the return address properly. - const expValue uint32 = 100 - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(expValue))) - require.NoError(t, err) - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - // After the initial exec, the code must exit with builtin function call status and funcaddress for memory grow. - require.Equal(t, nativeCallStatusCodeCallBuiltInFunction, env.compilerStatus()) - require.Equal(t, builtinFunctionIndexMemoryGrow, env.builtinFunctionCallAddress()) - - // Reenter from the return address. - nativecall( - env.ce.returnAddress, - env.callEngine(), - env.module(), - ) - - // Check if the code successfully executed the code after builtin function call. - require.Equal(t, expValue, env.stackTopAsUint32()) - require.Equal(t, nativeCallStatusCodeReturned, env.compilerStatus()) -} - -func TestCompiler_compileMemorySize(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - // Emit memory.size instructions. - err = compiler.compileMemorySize() - require.NoError(t, err) - // At this point, the size of memory should be pushed onto the stack. - requireRuntimeLocationStackPointerEqual(t, uint64(1), compiler) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - require.Equal(t, nativeCallStatusCodeReturned, env.compilerStatus()) - require.Equal(t, uint32(defaultMemoryPageNumInTest), env.stackTopAsUint32()) -} - -func TestCompiler_compileLoad(t *testing.T) { - // For testing. Arbitrary number is fine. - loadTargetValue := uint64(0x12_34_56_78_9a_bc_ef_fe) - baseOffset := uint32(100) - arg := wazeroir.MemoryArg{Offset: 361} - offset := baseOffset + arg.Offset - - tests := []struct { - name string - isFloatTarget bool - operationSetupFn func(t *testing.T, compiler compilerImpl) - loadedValueVerifyFn func(t *testing.T, loadedValueAsUint64 uint64) - }{ - { - name: "i32.load", - operationSetupFn: func(t *testing.T, compiler compilerImpl) { - err := compiler.compileLoad(operationPtr(wazeroir.NewOperationLoad(wazeroir.UnsignedTypeI32, arg))) - require.NoError(t, err) - }, - loadedValueVerifyFn: func(t *testing.T, loadedValueAsUint64 uint64) { - require.Equal(t, uint32(loadTargetValue), uint32(loadedValueAsUint64)) - }, - }, - { - name: "i64.load", - operationSetupFn: func(t *testing.T, compiler compilerImpl) { - err := compiler.compileLoad(operationPtr(wazeroir.NewOperationLoad(wazeroir.UnsignedTypeI64, arg))) - require.NoError(t, err) - }, - loadedValueVerifyFn: func(t *testing.T, loadedValueAsUint64 uint64) { - require.Equal(t, loadTargetValue, loadedValueAsUint64) - }, - }, - { - name: "f32.load", - operationSetupFn: func(t *testing.T, compiler compilerImpl) { - err := compiler.compileLoad(operationPtr(wazeroir.NewOperationLoad(wazeroir.UnsignedTypeF32, arg))) - require.NoError(t, err) - }, - loadedValueVerifyFn: func(t *testing.T, loadedValueAsUint64 uint64) { - require.Equal(t, uint32(loadTargetValue), uint32(loadedValueAsUint64)) - }, - isFloatTarget: true, - }, - { - name: "f64.load", - operationSetupFn: func(t *testing.T, compiler compilerImpl) { - err := compiler.compileLoad(operationPtr(wazeroir.NewOperationLoad(wazeroir.UnsignedTypeF64, arg))) - require.NoError(t, err) - }, - loadedValueVerifyFn: func(t *testing.T, loadedValueAsUint64 uint64) { - require.Equal(t, loadTargetValue, loadedValueAsUint64) - }, - isFloatTarget: true, - }, - { - name: "i32.load8s", - operationSetupFn: func(t *testing.T, compiler compilerImpl) { - err := compiler.compileLoad8(operationPtr(wazeroir.NewOperationLoad8(wazeroir.SignedInt32, arg))) - require.NoError(t, err) - }, - loadedValueVerifyFn: func(t *testing.T, loadedValueAsUint64 uint64) { - require.Equal(t, int32(int8(loadedValueAsUint64)), int32(uint32(loadedValueAsUint64))) - }, - }, - { - name: "i32.load8u", - operationSetupFn: func(t *testing.T, compiler compilerImpl) { - err := compiler.compileLoad8(operationPtr(wazeroir.NewOperationLoad8(wazeroir.SignedUint32, arg))) - require.NoError(t, err) - }, - loadedValueVerifyFn: func(t *testing.T, loadedValueAsUint64 uint64) { - require.Equal(t, uint32(byte(loadedValueAsUint64)), uint32(loadedValueAsUint64)) - }, - }, - { - name: "i64.load8s", - operationSetupFn: func(t *testing.T, compiler compilerImpl) { - err := compiler.compileLoad8(operationPtr(wazeroir.NewOperationLoad8(wazeroir.SignedInt64, arg))) - require.NoError(t, err) - }, - loadedValueVerifyFn: func(t *testing.T, loadedValueAsUint64 uint64) { - require.Equal(t, int64(int8(loadedValueAsUint64)), int64(loadedValueAsUint64)) - }, - }, - { - name: "i64.load8u", - operationSetupFn: func(t *testing.T, compiler compilerImpl) { - err := compiler.compileLoad8(operationPtr(wazeroir.NewOperationLoad8(wazeroir.SignedUint64, arg))) - require.NoError(t, err) - }, - loadedValueVerifyFn: func(t *testing.T, loadedValueAsUint64 uint64) { - require.Equal(t, uint64(byte(loadedValueAsUint64)), loadedValueAsUint64) - }, - }, - { - name: "i32.load16s", - operationSetupFn: func(t *testing.T, compiler compilerImpl) { - err := compiler.compileLoad16(operationPtr(wazeroir.NewOperationLoad16(wazeroir.SignedInt32, arg))) - require.NoError(t, err) - }, - loadedValueVerifyFn: func(t *testing.T, loadedValueAsUint64 uint64) { - require.Equal(t, int32(int16(loadedValueAsUint64)), int32(uint32(loadedValueAsUint64))) - }, - }, - { - name: "i32.load16u", - operationSetupFn: func(t *testing.T, compiler compilerImpl) { - err := compiler.compileLoad16(operationPtr(wazeroir.NewOperationLoad16(wazeroir.SignedUint32, arg))) - require.NoError(t, err) - }, - loadedValueVerifyFn: func(t *testing.T, loadedValueAsUint64 uint64) { - require.Equal(t, uint32(loadedValueAsUint64), uint32(loadedValueAsUint64)) - }, - }, - { - name: "i64.load16s", - operationSetupFn: func(t *testing.T, compiler compilerImpl) { - err := compiler.compileLoad16(operationPtr(wazeroir.NewOperationLoad16(wazeroir.SignedInt64, arg))) - require.NoError(t, err) - }, - loadedValueVerifyFn: func(t *testing.T, loadedValueAsUint64 uint64) { - require.Equal(t, int64(int16(loadedValueAsUint64)), int64(loadedValueAsUint64)) - }, - }, - { - name: "i64.load16u", - operationSetupFn: func(t *testing.T, compiler compilerImpl) { - err := compiler.compileLoad16(operationPtr(wazeroir.NewOperationLoad16(wazeroir.SignedUint64, arg))) - require.NoError(t, err) - }, - loadedValueVerifyFn: func(t *testing.T, loadedValueAsUint64 uint64) { - require.Equal(t, uint64(uint16(loadedValueAsUint64)), loadedValueAsUint64) - }, - }, - { - name: "i64.load32s", - operationSetupFn: func(t *testing.T, compiler compilerImpl) { - err := compiler.compileLoad32(operationPtr(wazeroir.NewOperationLoad32(true, arg))) - require.NoError(t, err) - }, - loadedValueVerifyFn: func(t *testing.T, loadedValueAsUint64 uint64) { - require.Equal(t, int64(int32(loadedValueAsUint64)), int64(loadedValueAsUint64)) - }, - }, - { - name: "i64.load32u", - operationSetupFn: func(t *testing.T, compiler compilerImpl) { - err := compiler.compileLoad32(operationPtr(wazeroir.NewOperationLoad32(false, arg))) - require.NoError(t, err) - }, - loadedValueVerifyFn: func(t *testing.T, loadedValueAsUint64 uint64) { - require.Equal(t, uint64(uint32(loadedValueAsUint64)), loadedValueAsUint64) - }, - }, - } - - for _, tt := range tests { - tc := tt - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - binary.LittleEndian.PutUint64(env.memory()[offset:], loadTargetValue) - - // Before load operation, we must push the base offset value. - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(baseOffset))) - require.NoError(t, err) - - tc.operationSetupFn(t, compiler) - - // At this point, the loaded value must be on top of the stack, and placed on a register. - requireRuntimeLocationStackPointerEqual(t, uint64(1), compiler) - require.Equal(t, 1, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - loadedLocation := compiler.runtimeValueLocationStack().peek() - require.True(t, loadedLocation.onRegister()) - if tc.isFloatTarget { - require.Equal(t, registerTypeVector, loadedLocation.getRegisterType()) - } else { - require.Equal(t, registerTypeGeneralPurpose, loadedLocation.getRegisterType()) - } - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - // Verify the loaded value. - require.Equal(t, uint64(1), env.stackPointer()) - tc.loadedValueVerifyFn(t, env.stackTopAsUint64()) - }) - } -} - -func TestCompiler_compileStore(t *testing.T) { - // For testing. Arbitrary number is fine. - storeTargetValue := uint64(math.MaxUint64) - baseOffset := uint32(100) - arg := wazeroir.MemoryArg{Offset: 361} - offset := arg.Offset + baseOffset - - tests := []struct { - name string - isFloatTarget bool - targetSizeInBytes uint32 - operationSetupFn func(t *testing.T, compiler compilerImpl) - storedValueVerifyFn func(t *testing.T, mem []byte) - }{ - { - name: "i32.store", - targetSizeInBytes: 32 / 8, - operationSetupFn: func(t *testing.T, compiler compilerImpl) { - err := compiler.compileStore(operationPtr(wazeroir.NewOperationStore(wazeroir.UnsignedTypeI32, arg))) - require.NoError(t, err) - }, - storedValueVerifyFn: func(t *testing.T, mem []byte) { - require.Equal(t, uint32(storeTargetValue), binary.LittleEndian.Uint32(mem[offset:])) - }, - }, - { - name: "f32.store", - isFloatTarget: true, - targetSizeInBytes: 32 / 8, - operationSetupFn: func(t *testing.T, compiler compilerImpl) { - err := compiler.compileStore(operationPtr(wazeroir.NewOperationStore(wazeroir.UnsignedTypeF32, arg))) - require.NoError(t, err) - }, - storedValueVerifyFn: func(t *testing.T, mem []byte) { - require.Equal(t, uint32(storeTargetValue), binary.LittleEndian.Uint32(mem[offset:])) - }, - }, - { - name: "i64.store", - targetSizeInBytes: 64 / 8, - operationSetupFn: func(t *testing.T, compiler compilerImpl) { - err := compiler.compileStore(operationPtr(wazeroir.NewOperationStore(wazeroir.UnsignedTypeI64, arg))) - require.NoError(t, err) - }, - storedValueVerifyFn: func(t *testing.T, mem []byte) { - require.Equal(t, storeTargetValue, binary.LittleEndian.Uint64(mem[offset:])) - }, - }, - { - name: "f64.store", - isFloatTarget: true, - targetSizeInBytes: 64 / 8, - operationSetupFn: func(t *testing.T, compiler compilerImpl) { - err := compiler.compileStore(operationPtr(wazeroir.NewOperationStore(wazeroir.UnsignedTypeF64, arg))) - require.NoError(t, err) - }, - storedValueVerifyFn: func(t *testing.T, mem []byte) { - require.Equal(t, storeTargetValue, binary.LittleEndian.Uint64(mem[offset:])) - }, - }, - { - name: "store8", - targetSizeInBytes: 1, - operationSetupFn: func(t *testing.T, compiler compilerImpl) { - err := compiler.compileStore8(operationPtr(wazeroir.NewOperationStore8(arg))) - require.NoError(t, err) - }, - storedValueVerifyFn: func(t *testing.T, mem []byte) { - require.Equal(t, byte(storeTargetValue), mem[offset]) - }, - }, - { - name: "store16", - targetSizeInBytes: 16 / 8, - operationSetupFn: func(t *testing.T, compiler compilerImpl) { - err := compiler.compileStore16(operationPtr(wazeroir.NewOperationStore16(arg))) - require.NoError(t, err) - }, - storedValueVerifyFn: func(t *testing.T, mem []byte) { - require.Equal(t, uint16(storeTargetValue), binary.LittleEndian.Uint16(mem[offset:])) - }, - }, - { - name: "store32", - targetSizeInBytes: 32 / 8, - operationSetupFn: func(t *testing.T, compiler compilerImpl) { - err := compiler.compileStore32(operationPtr(wazeroir.NewOperationStore32(arg))) - require.NoError(t, err) - }, - storedValueVerifyFn: func(t *testing.T, mem []byte) { - require.Equal(t, uint32(storeTargetValue), binary.LittleEndian.Uint32(mem[offset:])) - }, - }, - } - - for _, tt := range tests { - tc := tt - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - // Before store operations, we must push the base offset, and the store target values. - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(baseOffset))) - require.NoError(t, err) - if tc.isFloatTarget { - err = compiler.compileConstF64(operationPtr(wazeroir.NewOperationConstF64(math.Float64frombits(storeTargetValue)))) - } else { - err = compiler.compileConstI64(operationPtr(wazeroir.NewOperationConstI64(storeTargetValue))) - } - require.NoError(t, err) - - tc.operationSetupFn(t, compiler) - - // At this point, no registers must be in use, and no values on the stack since we consumed two values. - require.Zero(t, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - requireRuntimeLocationStackPointerEqual(t, uint64(0), compiler) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate the code under test. - err = compiler.compileReturnFunction() - require.NoError(t, err) - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - - // Set the value on the left and right neighboring memoryregion, - // so that we can verify the operation doesn't affect there. - ceil := offset + tc.targetSizeInBytes - mem := env.memory() - expectedNeighbor8Bytes := uint64(0x12_34_56_78_9a_bc_ef_fe) - binary.LittleEndian.PutUint64(mem[offset-8:offset], expectedNeighbor8Bytes) - binary.LittleEndian.PutUint64(mem[ceil:ceil+8], expectedNeighbor8Bytes) - - // Run code. - env.exec(code.Bytes()) - - tc.storedValueVerifyFn(t, mem) - - // The neighboring bytes must be intact. - require.Equal(t, expectedNeighbor8Bytes, binary.LittleEndian.Uint64(mem[offset-8:offset])) - require.Equal(t, expectedNeighbor8Bytes, binary.LittleEndian.Uint64(mem[ceil:ceil+8])) - }) - } -} - -func TestCompiler_MemoryOutOfBounds(t *testing.T) { - bases := []uint32{0, 1 << 5, 1 << 9, 1 << 10, 1 << 15, math.MaxUint32 - 1, math.MaxUint32} - offsets := []uint32{ - 0, - 1 << 10, 1 << 31, - defaultMemoryPageNumInTest*wasm.MemoryPageSize - 1, defaultMemoryPageNumInTest * wasm.MemoryPageSize, - math.MaxInt32 - 1, math.MaxInt32 - 2, math.MaxInt32 - 3, math.MaxInt32 - 4, - math.MaxInt32 - 5, math.MaxInt32 - 8, math.MaxInt32 - 9, math.MaxInt32, math.MaxUint32, - } - targetSizeInBytes := []int64{1, 2, 4, 8} - for _, base := range bases { - base := base - for _, offset := range offsets { - offset := offset - for _, targetSizeInByte := range targetSizeInBytes { - targetSizeInByte := targetSizeInByte - t.Run(fmt.Sprintf("base=%d,offset=%d,targetSizeInBytes=%d", base, offset, targetSizeInByte), func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, nil) - - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(base))) - require.NoError(t, err) - - arg := wazeroir.MemoryArg{Offset: offset} - - switch targetSizeInByte { - case 1: - err = compiler.compileLoad8(operationPtr(wazeroir.NewOperationLoad8(wazeroir.SignedInt32, arg))) - case 2: - err = compiler.compileLoad16(operationPtr(wazeroir.NewOperationLoad16(wazeroir.SignedInt32, arg))) - case 4: - err = compiler.compileLoad32(operationPtr(wazeroir.NewOperationLoad32(false, arg))) - case 8: - err = compiler.compileLoad(operationPtr(wazeroir.NewOperationLoad(wazeroir.UnsignedTypeF64, arg))) - default: - t.Fail() - } - - require.NoError(t, err) - require.NoError(t, compiler.compileReturnFunction()) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate the code under test and run. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - mem := env.memory() - if ceil := int64(base) + int64(offset) + int64(targetSizeInByte); int64(len(mem)) < ceil { - // If the targe memory region's ceil exceeds the length of memory, we must exit the function - // with nativeCallStatusCodeMemoryOutOfBounds status code. - require.Equal(t, nativeCallStatusCodeMemoryOutOfBounds, env.compilerStatus()) - } - }) - } - } - } -} diff --git a/internal/engine/compiler/compiler_numeric_test.go b/internal/engine/compiler/compiler_numeric_test.go deleted file mode 100644 index 34688b45ad..0000000000 --- a/internal/engine/compiler/compiler_numeric_test.go +++ /dev/null @@ -1,1611 +0,0 @@ -package compiler - -import ( - "fmt" - "math" - "math/bits" - "testing" - - "github.com/tetratelabs/wazero/internal/asm" - "github.com/tetratelabs/wazero/internal/moremath" - "github.com/tetratelabs/wazero/internal/testing/require" - "github.com/tetratelabs/wazero/internal/wasm" - "github.com/tetratelabs/wazero/internal/wazeroir" -) - -func TestCompiler_compileConsts(t *testing.T) { - for _, op := range []wazeroir.OperationKind{ - wazeroir.OperationKindConstI32, - wazeroir.OperationKindConstI64, - wazeroir.OperationKindConstF32, - wazeroir.OperationKindConstF64, - wazeroir.OperationKindV128Const, - } { - op := op - t.Run(op.String(), func(t *testing.T) { - for _, val := range []uint64{ - 0x0, 0x1, 0x1111000, 1 << 16, 1 << 21, 1 << 27, 1 << 32, 1<<32 + 1, 1 << 53, - math.Float64bits(math.Inf(1)), - math.Float64bits(math.Inf(-1)), - math.Float64bits(math.NaN()), - math.MaxUint32, - math.MaxInt32, - math.MaxUint64, - math.MaxInt64, - uint64(math.Float32bits(float32(math.Inf(1)))), - uint64(math.Float32bits(float32(math.Inf(-1)))), - uint64(math.Float32bits(float32(math.NaN()))), - } { - t.Run(fmt.Sprintf("0x%x", val), func(t *testing.T) { - env := newCompilerEnvironment() - - // Compile code. - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, nil) - err := compiler.compilePreamble() - require.NoError(t, err) - - switch op { - case wazeroir.OperationKindConstI32: - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(uint32(val)))) - case wazeroir.OperationKindConstI64: - err = compiler.compileConstI64(operationPtr(wazeroir.NewOperationConstI64(val))) - case wazeroir.OperationKindConstF32: - err = compiler.compileConstF32(operationPtr(wazeroir.NewOperationConstF32(math.Float32frombits(uint32(val))))) - case wazeroir.OperationKindConstF64: - err = compiler.compileConstF64(operationPtr(wazeroir.NewOperationConstF64(math.Float64frombits(val)))) - case wazeroir.OperationKindV128Const: - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(val, ^val))) - } - require.NoError(t, err) - - // After compiling const operations, we must see the register allocated value on the top of value. - loc := compiler.runtimeValueLocationStack().peek() - require.True(t, loc.onRegister()) - - if op == wazeroir.OperationKindV128Const { - require.Equal(t, runtimeValueTypeV128Hi, loc.valueType) - } - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - - // Run native code. - env.exec(code.Bytes()) - - // Compiler status must be returned. - require.Equal(t, nativeCallStatusCodeReturned, env.compilerStatus()) - if op == wazeroir.OperationKindV128Const { - require.Equal(t, uint64(2), env.stackPointer()) // a vector value consists of two uint64. - } else { - require.Equal(t, uint64(1), env.stackPointer()) - } - - switch op { - case wazeroir.OperationKindConstI32, wazeroir.OperationKindConstF32: - require.Equal(t, uint32(val), env.stackTopAsUint32()) - case wazeroir.OperationKindConstI64, wazeroir.OperationKindConstF64: - require.Equal(t, val, env.stackTopAsUint64()) - case wazeroir.OperationKindV128Const: - lo, hi := env.stackTopAsV128() - require.Equal(t, val, lo) - require.Equal(t, ^val, hi) - } - }) - } - }) - } -} - -func TestCompiler_compile_Add_Sub_Mul(t *testing.T) { - for _, kind := range []wazeroir.OperationKind{ - wazeroir.OperationKindAdd, - wazeroir.OperationKindSub, - wazeroir.OperationKindMul, - } { - kind := kind - t.Run(kind.String(), func(t *testing.T) { - for _, unsignedType := range []wazeroir.UnsignedType{ - wazeroir.UnsignedTypeI32, - wazeroir.UnsignedTypeI64, - wazeroir.UnsignedTypeF32, - wazeroir.UnsignedTypeF64, - } { - unsignedType := unsignedType - t.Run(unsignedType.String(), func(t *testing.T) { - for _, values := range [][2]uint64{ - {0, 0}, - {1, 1}, - {2, 1}, - {100, 1}, - {1, 0}, - {0, 1}, - {math.MaxInt16, math.MaxInt32}, - {1 << 14, 1 << 21}, - {1 << 14, 1 << 21}, - {0xffff_ffff_ffff_ffff, 0}, - {0xffff_ffff_ffff_ffff, 1}, - {0, 0xffff_ffff_ffff_ffff}, - {1, 0xffff_ffff_ffff_ffff}, - {0, math.Float64bits(math.Inf(1))}, - {0, math.Float64bits(math.Inf(-1))}, - {math.Float64bits(math.Inf(1)), 1}, - {math.Float64bits(math.Inf(-1)), 1}, - {math.Float64bits(1.11231), math.Float64bits(math.Inf(1))}, - {math.Float64bits(1.11231), math.Float64bits(math.Inf(-1))}, - {math.Float64bits(math.Inf(1)), math.Float64bits(1.11231)}, - {math.Float64bits(math.Inf(-1)), math.Float64bits(1.11231)}, - {math.Float64bits(math.Inf(1)), math.Float64bits(math.NaN())}, - {math.Float64bits(math.Inf(-1)), math.Float64bits(math.NaN())}, - {math.Float64bits(math.NaN()), math.Float64bits(math.Inf(1))}, - {math.Float64bits(math.NaN()), math.Float64bits(math.Inf(-1))}, - } { - x1, x2 := values[0], values[1] - t.Run(fmt.Sprintf("x1=0x%x,x2=0x%x", x1, x2), func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, nil) - err := compiler.compilePreamble() - require.NoError(t, err) - - // Emit consts operands. - for _, v := range []uint64{x1, x2} { - switch unsignedType { - case wazeroir.UnsignedTypeI32: - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(uint32(v)))) - case wazeroir.UnsignedTypeI64: - err = compiler.compileConstI64(operationPtr(wazeroir.NewOperationConstI64(v))) - case wazeroir.UnsignedTypeF32: - err = compiler.compileConstF32(operationPtr(wazeroir.NewOperationConstF32(math.Float32frombits(uint32(v))))) - case wazeroir.UnsignedTypeF64: - err = compiler.compileConstF64(operationPtr(wazeroir.NewOperationConstF64(math.Float64frombits(v)))) - } - require.NoError(t, err) - } - - // At this point, two values exist. - requireRuntimeLocationStackPointerEqual(t, uint64(2), compiler) - - // Emit the operation. - switch kind { - case wazeroir.OperationKindAdd: - err = compiler.compileAdd(operationPtr(wazeroir.NewOperationAdd(unsignedType))) - case wazeroir.OperationKindSub: - err = compiler.compileSub(operationPtr(wazeroir.NewOperationSub(unsignedType))) - case wazeroir.OperationKindMul: - err = compiler.compileMul(operationPtr(wazeroir.NewOperationMul(unsignedType))) - } - require.NoError(t, err) - - // We consumed two values, but push the result back. - requireRuntimeLocationStackPointerEqual(t, uint64(1), compiler) - resultLocation := compiler.runtimeValueLocationStack().peek() - // Plus the result must be located on a register. - require.True(t, resultLocation.onRegister()) - // Also, the result must have an appropriate register type. - if unsignedType == wazeroir.UnsignedTypeF32 || unsignedType == wazeroir.UnsignedTypeF64 { - require.Equal(t, registerTypeVector, resultLocation.getRegisterType()) - } else { - require.Equal(t, registerTypeGeneralPurpose, resultLocation.getRegisterType()) - } - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Compile and execute the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - // Check the stack. - require.Equal(t, uint64(1), env.stackPointer()) - - switch kind { - case wazeroir.OperationKindAdd: - switch unsignedType { - case wazeroir.UnsignedTypeI32: - require.Equal(t, uint32(x1)+uint32(x2), env.stackTopAsUint32()) - case wazeroir.UnsignedTypeI64: - require.Equal(t, x1+x2, env.stackTopAsUint64()) - case wazeroir.UnsignedTypeF32: - exp := math.Float32frombits(uint32(x1)) + math.Float32frombits(uint32(x2)) - // NaN cannot be compared with themselves, so we have to use IsNaN - if math.IsNaN(float64(exp)) { - require.True(t, math.IsNaN(float64(env.stackTopAsFloat32()))) - } else { - require.Equal(t, exp, env.stackTopAsFloat32()) - } - case wazeroir.UnsignedTypeF64: - exp := math.Float64frombits(x1) + math.Float64frombits(x2) - // NaN cannot be compared with themselves, so we have to use IsNaN - if math.IsNaN(exp) { - require.True(t, math.IsNaN(env.stackTopAsFloat64())) - } else { - require.Equal(t, exp, env.stackTopAsFloat64()) - } - } - case wazeroir.OperationKindSub: - switch unsignedType { - case wazeroir.UnsignedTypeI32: - require.Equal(t, uint32(x1)-uint32(x2), env.stackTopAsUint32()) - case wazeroir.UnsignedTypeI64: - require.Equal(t, x1-x2, env.stackTopAsUint64()) - case wazeroir.UnsignedTypeF32: - exp := math.Float32frombits(uint32(x1)) - math.Float32frombits(uint32(x2)) - // NaN cannot be compared with themselves, so we have to use IsNaN - if math.IsNaN(float64(exp)) { - require.True(t, math.IsNaN(float64(env.stackTopAsFloat32()))) - } else { - require.Equal(t, exp, env.stackTopAsFloat32()) - } - case wazeroir.UnsignedTypeF64: - exp := math.Float64frombits(x1) - math.Float64frombits(x2) - // NaN cannot be compared with themselves, so we have to use IsNaN - if math.IsNaN(exp) { - require.True(t, math.IsNaN(env.stackTopAsFloat64())) - } else { - require.Equal(t, exp, env.stackTopAsFloat64()) - } - } - case wazeroir.OperationKindMul: - switch unsignedType { - case wazeroir.UnsignedTypeI32: - require.Equal(t, uint32(x1)*uint32(x2), env.stackTopAsUint32()) - case wazeroir.UnsignedTypeI64: - require.Equal(t, x1*x2, env.stackTopAsUint64()) - case wazeroir.UnsignedTypeF32: - exp := math.Float32frombits(uint32(x1)) * math.Float32frombits(uint32(x2)) - // NaN cannot be compared with themselves, so we have to use IsNaN - if math.IsNaN(float64(exp)) { - require.True(t, math.IsNaN(float64(env.stackTopAsFloat32()))) - } else { - require.Equal(t, exp, env.stackTopAsFloat32()) - } - case wazeroir.UnsignedTypeF64: - exp := math.Float64frombits(x1) * math.Float64frombits(x2) - // NaN cannot be compared with themselves, so we have to use IsNaN - if math.IsNaN(exp) { - require.True(t, math.IsNaN(env.stackTopAsFloat64())) - } else { - require.Equal(t, exp, env.stackTopAsFloat64()) - } - } - } - }) - } - }) - } - }) - } -} - -func TestCompiler_compile_And_Or_Xor_Shl_Rotl_Rotr(t *testing.T) { - for _, kind := range []wazeroir.OperationKind{ - wazeroir.OperationKindAnd, - wazeroir.OperationKindOr, - wazeroir.OperationKindXor, - wazeroir.OperationKindShl, - wazeroir.OperationKindRotl, - wazeroir.OperationKindRotr, - } { - kind := kind - t.Run(kind.String(), func(t *testing.T) { - for _, unsignedInt := range []wazeroir.UnsignedInt{ - wazeroir.UnsignedInt32, - wazeroir.UnsignedInt64, - } { - unsignedInt := unsignedInt - t.Run(unsignedInt.String(), func(t *testing.T) { - for _, values := range [][2]uint64{ - {0, 0}, - {0, 1}, - {1, 0}, - {1, 1}, - {1 << 31, 1}, - {1, 1 << 31}, - {1 << 31, 1 << 31}, - {1 << 63, 1}, - {1, 1 << 63}, - {1 << 63, 1 << 63}, - } { - x1, x2 := values[0], values[1] - for _, x1OnRegister := range []bool{ - true, false, - } { - x1OnRegister := x1OnRegister - t.Run(fmt.Sprintf("x1=0x%x(on_register=%v),x2=0x%x", x1, x1OnRegister, x2), func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, nil) - err := compiler.compilePreamble() - require.NoError(t, err) - - // Emit consts operands. - var x1Location *runtimeValueLocation - switch unsignedInt { - case wazeroir.UnsignedInt32: - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(uint32(x1)))) - require.NoError(t, err) - x1Location = compiler.runtimeValueLocationStack().peek() - err = compiler.compileConstI64(operationPtr(wazeroir.NewOperationConstI64(x2))) - require.NoError(t, err) - case wazeroir.UnsignedInt64: - err = compiler.compileConstI64(operationPtr(wazeroir.NewOperationConstI64(x1))) - require.NoError(t, err) - x1Location = compiler.runtimeValueLocationStack().peek() - err = compiler.compileConstI64(operationPtr(wazeroir.NewOperationConstI64(x2))) - require.NoError(t, err) - } - - if !x1OnRegister { - compiler.compileReleaseRegisterToStack(x1Location) - } - - // At this point, two values exist. - requireRuntimeLocationStackPointerEqual(t, uint64(2), compiler) - - // Emit the operation. - switch kind { - case wazeroir.OperationKindAnd: - err = compiler.compileAnd(operationPtr(wazeroir.NewOperationAnd(unsignedInt))) - case wazeroir.OperationKindOr: - err = compiler.compileOr(operationPtr(wazeroir.NewOperationOr(unsignedInt))) - case wazeroir.OperationKindXor: - err = compiler.compileXor(operationPtr(wazeroir.NewOperationXor(unsignedInt))) - case wazeroir.OperationKindShl: - err = compiler.compileShl(operationPtr(wazeroir.NewOperationShl(unsignedInt))) - case wazeroir.OperationKindRotl: - err = compiler.compileRotl(operationPtr(wazeroir.NewOperationRotl(unsignedInt))) - case wazeroir.OperationKindRotr: - err = compiler.compileRotr(operationPtr(wazeroir.NewOperationRotr(unsignedInt))) - } - require.NoError(t, err) - - // We consumed two values, but push the result back. - requireRuntimeLocationStackPointerEqual(t, uint64(1), compiler) - resultLocation := compiler.runtimeValueLocationStack().peek() - // Also, the result must have an appropriate register type. - require.Equal(t, registerTypeGeneralPurpose, resultLocation.getRegisterType()) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Compile and execute the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - // Check the stack. - require.Equal(t, uint64(1), env.stackPointer()) - - switch kind { - case wazeroir.OperationKindAnd: - switch unsignedInt { - case wazeroir.UnsignedInt32: - require.Equal(t, uint32(x1)&uint32(x2), env.stackTopAsUint32()) - case wazeroir.UnsignedInt64: - require.Equal(t, x1&x2, env.stackTopAsUint64()) - } - case wazeroir.OperationKindOr: - switch unsignedInt { - case wazeroir.UnsignedInt32: - require.Equal(t, uint32(x1)|uint32(x2), env.stackTopAsUint32()) - case wazeroir.UnsignedInt64: - require.Equal(t, x1|x2, env.stackTopAsUint64()) - } - case wazeroir.OperationKindXor: - switch unsignedInt { - case wazeroir.UnsignedInt32: - require.Equal(t, uint32(x1)^uint32(x2), env.stackTopAsUint32()) - case wazeroir.UnsignedInt64: - require.Equal(t, x1^x2, env.stackTopAsUint64()) - } - case wazeroir.OperationKindShl: - switch unsignedInt { - case wazeroir.UnsignedInt32: - require.Equal(t, uint32(x1)<>(uint32(x2)%32), env.stackTopAsInt32()) - case wazeroir.SignedInt64: - require.Equal(t, int64(x1)>>(x2%64), env.stackTopAsInt64()) - case wazeroir.SignedUint32: - require.Equal(t, uint32(x1)>>(uint32(x2)%32), env.stackTopAsUint32()) - case wazeroir.SignedUint64: - require.Equal(t, x1>>(x2%64), env.stackTopAsUint64()) - } - }) - } - }) - } - }) -} - -func TestCompiler_compile_Le_Lt_Gt_Ge_Eq_Eqz_Ne(t *testing.T) { - for _, kind := range []wazeroir.OperationKind{ - wazeroir.OperationKindEq, - wazeroir.OperationKindEqz, - wazeroir.OperationKindNe, - wazeroir.OperationKindLe, - wazeroir.OperationKindLt, - wazeroir.OperationKindGe, - wazeroir.OperationKindGt, - } { - kind := kind - t.Run(kind.String(), func(t *testing.T) { - for _, signedType := range []wazeroir.SignedType{ - wazeroir.SignedTypeUint32, - wazeroir.SignedTypeUint64, - wazeroir.SignedTypeInt32, - wazeroir.SignedTypeInt64, - wazeroir.SignedTypeFloat32, - wazeroir.SignedTypeFloat64, - } { - signedType := signedType - t.Run(signedType.String(), func(t *testing.T) { - for _, values := range [][2]uint64{ - {0, 0}, - {1, 1}, - {2, 1}, - {100, 1}, - {1, 0}, - {0, 1}, - {math.MaxInt16, math.MaxInt32}, - {1 << 14, 1 << 21}, - {1 << 14, 1 << 21}, - {0xffff_ffff_ffff_ffff, 0}, - {0xffff_ffff_ffff_ffff, 1}, - {0, 0xffff_ffff_ffff_ffff}, - {1, 0xffff_ffff_ffff_ffff}, - {1, math.Float64bits(math.NaN())}, - {math.Float64bits(math.NaN()), 1}, - {0xffff_ffff_ffff_ffff, math.Float64bits(math.NaN())}, - {math.Float64bits(math.NaN()), 0xffff_ffff_ffff_ffff}, - {math.Float64bits(math.MaxFloat32), 1}, - {math.Float64bits(math.SmallestNonzeroFloat32), 1}, - {math.Float64bits(math.MaxFloat64), 1}, - {math.Float64bits(math.SmallestNonzeroFloat64), 1}, - {0, math.Float64bits(math.Inf(1))}, - {0, math.Float64bits(math.Inf(-1))}, - {math.Float64bits(math.Inf(1)), 0}, - {math.Float64bits(math.Inf(-1)), 0}, - {math.Float64bits(math.Inf(1)), 1}, - {math.Float64bits(math.Inf(-1)), 1}, - {math.Float64bits(1.11231), math.Float64bits(math.Inf(1))}, - {math.Float64bits(1.11231), math.Float64bits(math.Inf(-1))}, - {math.Float64bits(math.Inf(1)), math.Float64bits(1.11231)}, - {math.Float64bits(math.Inf(-1)), math.Float64bits(1.11231)}, - {math.Float64bits(math.Inf(1)), math.Float64bits(math.NaN())}, - {math.Float64bits(math.Inf(-1)), math.Float64bits(math.NaN())}, - {math.Float64bits(math.NaN()), math.Float64bits(math.Inf(1))}, - {math.Float64bits(math.NaN()), math.Float64bits(math.Inf(-1))}, - } { - x1, x2 := values[0], values[1] - isEqz := kind == wazeroir.OperationKindEqz - if isEqz && (signedType == wazeroir.SignedTypeFloat32 || signedType == wazeroir.SignedTypeFloat64) { - // Eqz isn't defined for float. - return - } - t.Run(fmt.Sprintf("x1=0x%x,x2=0x%x", x1, x2), func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, nil) - err := compiler.compilePreamble() - require.NoError(t, err) - - // Emit consts operands. - for _, v := range []uint64{x1, x2} { - switch signedType { - case wazeroir.SignedTypeUint32: - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(uint32(v)))) - case wazeroir.SignedTypeInt32: - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(uint32(int32(v))))) - case wazeroir.SignedTypeInt64, wazeroir.SignedTypeUint64: - err = compiler.compileConstI64(operationPtr(wazeroir.NewOperationConstI64(v))) - case wazeroir.SignedTypeFloat32: - err = compiler.compileConstF32(operationPtr(wazeroir.NewOperationConstF32(math.Float32frombits(uint32(v))))) - case wazeroir.SignedTypeFloat64: - err = compiler.compileConstF64(operationPtr(wazeroir.NewOperationConstF64(math.Float64frombits(v)))) - } - require.NoError(t, err) - } - - if isEqz { - // Eqz only needs one value, so pop the top one (x2). - compiler.runtimeValueLocationStack().pop() - requireRuntimeLocationStackPointerEqual(t, uint64(1), compiler) - } else { - // At this point, two values exist for comparison. - requireRuntimeLocationStackPointerEqual(t, uint64(2), compiler) - } - - // Emit the operation. - switch kind { - case wazeroir.OperationKindLe: - err = compiler.compileLe(operationPtr(wazeroir.NewOperationLe(signedType))) - case wazeroir.OperationKindLt: - err = compiler.compileLt(operationPtr(wazeroir.NewOperationLt(signedType))) - case wazeroir.OperationKindGe: - err = compiler.compileGe(operationPtr(wazeroir.NewOperationGe(signedType))) - case wazeroir.OperationKindGt: - err = compiler.compileGt(operationPtr(wazeroir.NewOperationGt(signedType))) - case wazeroir.OperationKindEq: - // Eq uses UnsignedType instead, so we translate the signed one. - switch signedType { - case wazeroir.SignedTypeUint32, wazeroir.SignedTypeInt32: - err = compiler.compileEq(operationPtr(wazeroir.NewOperationEq(wazeroir.UnsignedTypeI32))) - case wazeroir.SignedTypeUint64, wazeroir.SignedTypeInt64: - err = compiler.compileEq(operationPtr(wazeroir.NewOperationEq(wazeroir.UnsignedTypeI64))) - case wazeroir.SignedTypeFloat32: - err = compiler.compileEq(operationPtr(wazeroir.NewOperationEq(wazeroir.UnsignedTypeF32))) - case wazeroir.SignedTypeFloat64: - err = compiler.compileEq(operationPtr(wazeroir.NewOperationEq(wazeroir.UnsignedTypeF64))) - } - case wazeroir.OperationKindNe: - // Ne uses UnsignedType, so we translate the signed one. - switch signedType { - case wazeroir.SignedTypeUint32, wazeroir.SignedTypeInt32: - err = compiler.compileNe(operationPtr(wazeroir.NewOperationNe(wazeroir.UnsignedTypeI32))) - case wazeroir.SignedTypeUint64, wazeroir.SignedTypeInt64: - err = compiler.compileNe(operationPtr(wazeroir.NewOperationNe(wazeroir.UnsignedTypeI64))) - case wazeroir.SignedTypeFloat32: - err = compiler.compileNe(operationPtr(wazeroir.NewOperationNe(wazeroir.UnsignedTypeF32))) - case wazeroir.SignedTypeFloat64: - err = compiler.compileNe(operationPtr(wazeroir.NewOperationNe(wazeroir.UnsignedTypeF64))) - } - case wazeroir.OperationKindEqz: - // Eqz uses UnsignedInt, so we translate the signed one. - switch signedType { - case wazeroir.SignedTypeUint32, wazeroir.SignedTypeInt32: - err = compiler.compileEqz(operationPtr(wazeroir.NewOperationEqz(wazeroir.UnsignedInt32))) - case wazeroir.SignedTypeUint64, wazeroir.SignedTypeInt64: - err = compiler.compileEqz(operationPtr(wazeroir.NewOperationEqz(wazeroir.UnsignedInt64))) - } - } - require.NoError(t, err) - - // We consumed two values, but push the result back. - requireRuntimeLocationStackPointerEqual(t, uint64(1), compiler) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Compile and execute the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - // There should only be one value on the stack - require.Equal(t, uint64(1), env.stackPointer()) - - actual := env.stackTopAsUint32() == 1 - - switch kind { - case wazeroir.OperationKindLe: - switch signedType { - case wazeroir.SignedTypeInt32: - require.Equal(t, int32(x1) <= int32(x2), actual) - case wazeroir.SignedTypeUint32: - require.Equal(t, uint32(x1) <= uint32(x2), actual) - case wazeroir.SignedTypeInt64: - require.Equal(t, int64(x1) <= int64(x2), actual) - case wazeroir.SignedTypeUint64: - require.Equal(t, x1 <= x2, actual) - case wazeroir.SignedTypeFloat32: - require.Equal(t, math.Float32frombits(uint32(x1)) <= math.Float32frombits(uint32(x2)), actual) - case wazeroir.SignedTypeFloat64: - require.Equal(t, math.Float64frombits(x1) <= math.Float64frombits(x2), actual) - } - case wazeroir.OperationKindLt: - switch signedType { - case wazeroir.SignedTypeInt32: - require.Equal(t, int32(x1) < int32(x2), actual) - case wazeroir.SignedTypeUint32: - require.Equal(t, uint32(x1) < uint32(x2), actual) - case wazeroir.SignedTypeInt64: - require.Equal(t, int64(x1) < int64(x2), actual) - case wazeroir.SignedTypeUint64: - require.Equal(t, x1 < x2, actual) - case wazeroir.SignedTypeFloat32: - require.Equal(t, math.Float32frombits(uint32(x1)) < math.Float32frombits(uint32(x2)), actual) - case wazeroir.SignedTypeFloat64: - require.Equal(t, math.Float64frombits(x1) < math.Float64frombits(x2), actual) - } - case wazeroir.OperationKindGe: - switch signedType { - case wazeroir.SignedTypeInt32: - require.Equal(t, int32(x1) >= int32(x2), actual) - case wazeroir.SignedTypeUint32: - require.Equal(t, uint32(x1) >= uint32(x2), actual) - case wazeroir.SignedTypeInt64: - require.Equal(t, int64(x1) >= int64(x2), actual) - case wazeroir.SignedTypeUint64: - require.Equal(t, x1 >= x2, actual) - case wazeroir.SignedTypeFloat32: - require.Equal(t, math.Float32frombits(uint32(x1)) >= math.Float32frombits(uint32(x2)), actual) - case wazeroir.SignedTypeFloat64: - require.Equal(t, math.Float64frombits(x1) >= math.Float64frombits(x2), actual) - } - case wazeroir.OperationKindGt: - switch signedType { - case wazeroir.SignedTypeInt32: - require.Equal(t, int32(x1) > int32(x2), actual) - case wazeroir.SignedTypeUint32: - require.Equal(t, uint32(x1) > uint32(x2), actual) - case wazeroir.SignedTypeInt64: - require.Equal(t, int64(x1) > int64(x2), actual) - case wazeroir.SignedTypeUint64: - require.Equal(t, x1 > x2, actual) - case wazeroir.SignedTypeFloat32: - require.Equal(t, math.Float32frombits(uint32(x1)) > math.Float32frombits(uint32(x2)), actual) - case wazeroir.SignedTypeFloat64: - require.Equal(t, math.Float64frombits(x1) > math.Float64frombits(x2), actual) - } - case wazeroir.OperationKindEq: - switch signedType { - case wazeroir.SignedTypeInt32, wazeroir.SignedTypeUint32: - require.Equal(t, uint32(x1) == uint32(x2), actual) - case wazeroir.SignedTypeInt64, wazeroir.SignedTypeUint64: - require.Equal(t, x1 == x2, actual) - case wazeroir.SignedTypeFloat32: - require.Equal(t, math.Float32frombits(uint32(x1)) == math.Float32frombits(uint32(x2)), actual) - case wazeroir.SignedTypeFloat64: - require.Equal(t, math.Float64frombits(x1) == math.Float64frombits(x2), actual) - } - case wazeroir.OperationKindNe: - switch signedType { - case wazeroir.SignedTypeInt32, wazeroir.SignedTypeUint32: - require.Equal(t, uint32(x1) != uint32(x2), actual) - case wazeroir.SignedTypeInt64, wazeroir.SignedTypeUint64: - require.Equal(t, x1 != x2, actual) - case wazeroir.SignedTypeFloat32: - require.Equal(t, math.Float32frombits(uint32(x1)) != math.Float32frombits(uint32(x2)), actual) - case wazeroir.SignedTypeFloat64: - require.Equal(t, math.Float64frombits(x1) != math.Float64frombits(x2), actual) - } - case wazeroir.OperationKindEqz: - switch signedType { - case wazeroir.SignedTypeInt32, wazeroir.SignedTypeUint32: - require.Equal(t, uint32(x1) == 0, actual) - case wazeroir.SignedTypeInt64, wazeroir.SignedTypeUint64: - require.Equal(t, x1 == 0, actual) - } - } - }) - } - }) - } - }) - } -} - -func TestCompiler_compile_Clz_Ctz_Popcnt(t *testing.T) { - for _, kind := range []wazeroir.OperationKind{ - wazeroir.OperationKindClz, - wazeroir.OperationKindCtz, - wazeroir.OperationKindPopcnt, - } { - kind := kind - t.Run(kind.String(), func(t *testing.T) { - for _, tp := range []wazeroir.UnsignedInt{wazeroir.UnsignedInt32, wazeroir.UnsignedInt64} { - tp := tp - is32bit := tp == wazeroir.UnsignedInt32 - t.Run(tp.String(), func(t *testing.T) { - for _, v := range []uint64{ - 0, 1, 1 << 4, 1 << 6, 1 << 31, - 0b11111111110000, 0b010101010, 0b1111111111111, math.MaxUint64, - } { - name := fmt.Sprintf("%064b", v) - if is32bit { - name = fmt.Sprintf("%032b", v) - } - t.Run(name, func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, nil) - err := compiler.compilePreamble() - require.NoError(t, err) - - if is32bit { - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(uint32(v)))) - } else { - err = compiler.compileConstI64(operationPtr(wazeroir.NewOperationConstI64(v))) - } - require.NoError(t, err) - - switch kind { - case wazeroir.OperationKindClz: - err = compiler.compileClz(operationPtr(wazeroir.NewOperationClz(tp))) - case wazeroir.OperationKindCtz: - err = compiler.compileCtz(operationPtr(wazeroir.NewOperationCtz(tp))) - case wazeroir.OperationKindPopcnt: - err = compiler.compilePopcnt(operationPtr(wazeroir.NewOperationPopcnt(tp))) - } - require.NoError(t, err) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - // One value must be pushed as a result. - require.Equal(t, uint64(1), env.stackPointer()) - - switch kind { - case wazeroir.OperationKindClz: - if is32bit { - require.Equal(t, bits.LeadingZeros32(uint32(v)), int(env.stackTopAsUint32())) - } else { - require.Equal(t, bits.LeadingZeros64(v), int(env.stackTopAsUint32())) - } - case wazeroir.OperationKindCtz: - if is32bit { - require.Equal(t, bits.TrailingZeros32(uint32(v)), int(env.stackTopAsUint32())) - } else { - require.Equal(t, bits.TrailingZeros64(v), int(env.stackTopAsUint32())) - } - case wazeroir.OperationKindPopcnt: - if is32bit { - require.Equal(t, bits.OnesCount32(uint32(v)), int(env.stackTopAsUint32())) - } else { - require.Equal(t, bits.OnesCount64(v), int(env.stackTopAsUint32())) - } - } - }) - } - }) - } - }) - } -} - -func TestCompiler_compile_Min_Max_Copysign(t *testing.T) { - tests := []struct { - name string - is32bit bool - setupFunc func(t *testing.T, compiler compilerImpl) - verifyFunc func(t *testing.T, x1, x2 float64, raw uint64) - }{ - { - name: "min-32-bit", - is32bit: true, - setupFunc: func(t *testing.T, compiler compilerImpl) { - err := compiler.compileMin(operationPtr(wazeroir.NewOperationMin(wazeroir.Float32))) - require.NoError(t, err) - }, - verifyFunc: func(t *testing.T, x1, x2 float64, raw uint64) { - exp := moremath.WasmCompatMin32(float32(x1), float32(x2)) - actual := math.Float32frombits(uint32(raw)) - if math.IsNaN(float64(exp)) { // NaN cannot be compared with themselves, so we have to use IsNaN - require.True(t, math.IsNaN(float64(actual))) - } else { - require.Equal(t, math.Float32bits(exp), math.Float32bits(actual)) - } - }, - }, - { - name: "min-64-bit", - is32bit: false, - setupFunc: func(t *testing.T, compiler compilerImpl) { - err := compiler.compileMin(operationPtr(wazeroir.NewOperationMin(wazeroir.Float64))) - require.NoError(t, err) - }, - verifyFunc: func(t *testing.T, x1, x2 float64, raw uint64) { - exp := moremath.WasmCompatMin64(x1, x2) - actual := math.Float64frombits(raw) - if math.IsNaN(exp) { // NaN cannot be compared with themselves, so we have to use IsNaN - require.True(t, math.IsNaN(actual)) - } else { - require.Equal(t, math.Float64bits(exp), math.Float64bits(actual)) - } - }, - }, - { - name: "max-32-bit", - is32bit: true, - setupFunc: func(t *testing.T, compiler compilerImpl) { - err := compiler.compileMax(operationPtr(wazeroir.NewOperationMax(wazeroir.Float32))) - require.NoError(t, err) - }, - verifyFunc: func(t *testing.T, x1, x2 float64, raw uint64) { - exp := moremath.WasmCompatMax32(float32(x1), float32(x2)) - actual := math.Float32frombits(uint32(raw)) - if math.IsNaN(float64(exp)) { // NaN cannot be compared with themselves, so we have to use IsNaN - require.True(t, math.IsNaN(float64(actual))) - } else { - require.Equal(t, math.Float32bits(exp), math.Float32bits(actual)) - } - }, - }, - { - name: "max-64-bit", - is32bit: false, - setupFunc: func(t *testing.T, compiler compilerImpl) { - err := compiler.compileMax(operationPtr(wazeroir.NewOperationMax(wazeroir.Float64))) - require.NoError(t, err) - }, - verifyFunc: func(t *testing.T, x1, x2 float64, raw uint64) { - exp := moremath.WasmCompatMax64(x1, x2) - actual := math.Float64frombits(raw) - if math.IsNaN(exp) { // NaN cannot be compared with themselves, so we have to use IsNaN - require.True(t, math.IsNaN(actual)) - } else { - require.Equal(t, math.Float64bits(exp), math.Float64bits(actual)) - } - }, - }, - { - name: "copysign-32-bit", - is32bit: true, - setupFunc: func(t *testing.T, compiler compilerImpl) { - err := compiler.compileCopysign(operationPtr(wazeroir.NewOperationCopysign(wazeroir.Float32))) - require.NoError(t, err) - }, - verifyFunc: func(t *testing.T, x1, x2 float64, raw uint64) { - exp := float32(math.Copysign(float64(float32(x1)), float64(float32(x2)))) - actual := math.Float32frombits(uint32(raw)) - if math.IsNaN(float64(exp)) { // NaN cannot be compared with themselves, so we have to use IsNaN - require.True(t, math.IsNaN(float64(actual))) - } else { - require.Equal(t, exp, actual) - } - }, - }, - { - name: "copysign-64-bit", - is32bit: false, - setupFunc: func(t *testing.T, compiler compilerImpl) { - err := compiler.compileCopysign(operationPtr(wazeroir.NewOperationCopysign(wazeroir.Float64))) - require.NoError(t, err) - }, - verifyFunc: func(t *testing.T, x1, x2 float64, raw uint64) { - exp := math.Copysign(x1, x2) - actual := math.Float64frombits(raw) - if math.IsNaN(exp) { // NaN cannot be compared with themselves, so we have to use IsNaN - require.True(t, math.IsNaN(actual)) - } else { - require.Equal(t, exp, actual) - } - }, - }, - } - - for _, tt := range tests { - tc := tt - t.Run(tc.name, func(t *testing.T) { - for _, vs := range [][2]float64{ - {math.Copysign(0, 1), math.Copysign(0, 1)}, - {math.Copysign(0, -1), math.Copysign(0, 1)}, - {math.Copysign(0, 1), math.Copysign(0, -1)}, - {math.Copysign(0, -1), math.Copysign(0, -1)}, - {100, -1.1}, - {100, 0}, - {0, 0}, - {1, 1}, - {-1, 100}, - {100, 200}, - {100.01234124, 100.01234124}, - {100.01234124, -100.01234124}, - {200.12315, 100}, - {6.8719476736e+10 /* = 1 << 36 */, 100}, - {6.8719476736e+10 /* = 1 << 36 */, 1.37438953472e+11 /* = 1 << 37*/}, - {math.Inf(1), 100}, - {math.Inf(1), -100}, - {100, math.Inf(1)}, - {-100, math.Inf(1)}, - {math.Inf(-1), 100}, - {math.Inf(-1), -100}, - {100, math.Inf(-1)}, - {-100, math.Inf(-1)}, - {math.Inf(1), 0}, - {math.Inf(-1), 0}, - {0, math.Inf(1)}, - {0, math.Inf(-1)}, - {math.NaN(), 0}, - {0, math.NaN()}, - {math.NaN(), 12321}, - {12313, math.NaN()}, - {math.NaN(), math.NaN()}, - } { - x1, x2 := vs[0], vs[1] - t.Run(fmt.Sprintf("x1=%f_x2=%f", x1, x2), func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, nil) - err := compiler.compilePreamble() - require.NoError(t, err) - - // Setup the target values. - if tc.is32bit { - err := compiler.compileConstF32(operationPtr(wazeroir.NewOperationConstF32(float32(x1)))) - require.NoError(t, err) - err = compiler.compileConstF32(operationPtr(wazeroir.NewOperationConstF32(float32(x2)))) - require.NoError(t, err) - } else { - err := compiler.compileConstF64(operationPtr(wazeroir.NewOperationConstF64(x1))) - require.NoError(t, err) - err = compiler.compileConstF64(operationPtr(wazeroir.NewOperationConstF64(x2))) - require.NoError(t, err) - } - - // At this point two values are pushed. - requireRuntimeLocationStackPointerEqual(t, uint64(2), compiler) - require.Equal(t, 2, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - - tc.setupFunc(t, compiler) - - // We consumed two values, but push one value after operation. - requireRuntimeLocationStackPointerEqual(t, uint64(1), compiler) - require.Equal(t, 1, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - require.Equal(t, nativeCallStatusCodeReturned, env.compilerStatus()) - require.Equal(t, uint64(1), env.stackPointer()) // Result must be pushed! - - tc.verifyFunc(t, x1, x2, env.stackTopAsUint64()) - }) - } - }) - } -} - -func TestCompiler_compile_Abs_Neg_Ceil_Floor_Trunc_Nearest_Sqrt(t *testing.T) { - tests := []struct { - name string - is32bit bool - setupFunc func(t *testing.T, compiler compilerImpl) - verifyFunc func(t *testing.T, v float64, raw uint64) - }{ - { - name: "abs-32-bit", - is32bit: true, - setupFunc: func(t *testing.T, compiler compilerImpl) { - err := compiler.compileAbs(operationPtr(wazeroir.NewOperationAbs(wazeroir.Float32))) - require.NoError(t, err) - }, - verifyFunc: func(t *testing.T, v float64, raw uint64) { - exp := float32(math.Abs(float64(v))) - actual := math.Float32frombits(uint32(raw)) - if math.IsNaN(float64(exp)) { // NaN cannot be compared with themselves, so we have to use IsNaN - require.True(t, math.IsNaN(float64(actual))) - } else { - require.Equal(t, exp, actual) - } - }, - }, - { - name: "abs-64-bit", - is32bit: false, - setupFunc: func(t *testing.T, compiler compilerImpl) { - err := compiler.compileAbs(operationPtr(wazeroir.NewOperationAbs(wazeroir.Float64))) - require.NoError(t, err) - }, - verifyFunc: func(t *testing.T, v float64, raw uint64) { - exp := math.Abs(v) - actual := math.Float64frombits(raw) - if math.IsNaN(exp) { // NaN cannot be compared with themselves, so we have to use IsNaN - require.True(t, math.IsNaN(actual)) - } else { - require.Equal(t, exp, actual) - } - }, - }, - { - name: "neg-32-bit", - is32bit: true, - setupFunc: func(t *testing.T, compiler compilerImpl) { - err := compiler.compileNeg(operationPtr(wazeroir.NewOperationNeg(wazeroir.Float32))) - require.NoError(t, err) - }, - verifyFunc: func(t *testing.T, v float64, raw uint64) { - exp := -float32(v) - actual := math.Float32frombits(uint32(raw)) - if math.IsNaN(float64(exp)) { // NaN cannot be compared with themselves, so we have to use IsNaN - require.True(t, math.IsNaN(float64(actual))) - } else { - require.Equal(t, exp, actual) - } - }, - }, - { - name: "neg-64-bit", - is32bit: false, - setupFunc: func(t *testing.T, compiler compilerImpl) { - err := compiler.compileNeg(operationPtr(wazeroir.NewOperationNeg(wazeroir.Float64))) - require.NoError(t, err) - }, - verifyFunc: func(t *testing.T, v float64, raw uint64) { - exp := -v - actual := math.Float64frombits(raw) - if math.IsNaN(exp) { // NaN cannot be compared with themselves, so we have to use IsNaN - require.True(t, math.IsNaN(actual)) - } else { - require.Equal(t, exp, actual) - } - }, - }, - { - name: "ceil-32-bit", - is32bit: true, - setupFunc: func(t *testing.T, compiler compilerImpl) { - err := compiler.compileCeil(operationPtr(wazeroir.NewOperationCeil(wazeroir.Float32))) - require.NoError(t, err) - }, - verifyFunc: func(t *testing.T, v float64, raw uint64) { - exp := float32(math.Ceil(float64(v))) - actual := math.Float32frombits(uint32(raw)) - if math.IsNaN(float64(exp)) { // NaN cannot be compared with themselves, so we have to use IsNaN - require.True(t, math.IsNaN(float64(actual))) - } else { - require.Equal(t, exp, actual) - } - }, - }, - { - name: "ceil-64-bit", - is32bit: false, - setupFunc: func(t *testing.T, compiler compilerImpl) { - err := compiler.compileCeil(operationPtr(wazeroir.NewOperationCeil(wazeroir.Float64))) - require.NoError(t, err) - }, - verifyFunc: func(t *testing.T, v float64, raw uint64) { - exp := math.Ceil(v) - actual := math.Float64frombits(raw) - if math.IsNaN(exp) { // NaN cannot be compared with themselves, so we have to use IsNaN - require.True(t, math.IsNaN(actual)) - } else { - require.Equal(t, exp, actual) - } - }, - }, - { - name: "floor-32-bit", - is32bit: true, - setupFunc: func(t *testing.T, compiler compilerImpl) { - err := compiler.compileFloor(operationPtr(wazeroir.NewOperationFloor(wazeroir.Float32))) - require.NoError(t, err) - }, - verifyFunc: func(t *testing.T, v float64, raw uint64) { - exp := float32(math.Floor(float64(v))) - actual := math.Float32frombits(uint32(raw)) - if math.IsNaN(float64(exp)) { // NaN cannot be compared with themselves, so we have to use IsNaN - require.True(t, math.IsNaN(float64(actual))) - } else { - require.Equal(t, exp, actual) - } - }, - }, - { - name: "floor-64-bit", - is32bit: false, - setupFunc: func(t *testing.T, compiler compilerImpl) { - err := compiler.compileFloor(operationPtr(wazeroir.NewOperationFloor(wazeroir.Float64))) - require.NoError(t, err) - }, - verifyFunc: func(t *testing.T, v float64, raw uint64) { - exp := math.Floor(v) - actual := math.Float64frombits(raw) - if math.IsNaN(exp) { // NaN cannot be compared with themselves, so we have to use IsNaN - require.True(t, math.IsNaN(actual)) - } else { - require.Equal(t, exp, actual) - } - }, - }, - { - name: "trunc-32-bit", - is32bit: true, - setupFunc: func(t *testing.T, compiler compilerImpl) { - err := compiler.compileTrunc(operationPtr(wazeroir.NewOperationTrunc(wazeroir.Float32))) - require.NoError(t, err) - }, - verifyFunc: func(t *testing.T, v float64, raw uint64) { - exp := float32(math.Trunc(float64(v))) - actual := math.Float32frombits(uint32(raw)) - if math.IsNaN(float64(exp)) { // NaN cannot be compared with themselves, so we have to use IsNaN - require.True(t, math.IsNaN(float64(actual))) - } else { - require.Equal(t, exp, actual) - } - }, - }, - { - name: "trunc-64-bit", - is32bit: false, - setupFunc: func(t *testing.T, compiler compilerImpl) { - err := compiler.compileTrunc(operationPtr(wazeroir.NewOperationTrunc(wazeroir.Float64))) - require.NoError(t, err) - }, - verifyFunc: func(t *testing.T, v float64, raw uint64) { - exp := math.Trunc(v) - actual := math.Float64frombits(raw) - if math.IsNaN(exp) { // NaN cannot be compared with themselves, so we have to use IsNaN - require.True(t, math.IsNaN(actual)) - } else { - require.Equal(t, exp, actual) - } - }, - }, - { - name: "nearest-32-bit", - is32bit: true, - setupFunc: func(t *testing.T, compiler compilerImpl) { - err := compiler.compileNearest(operationPtr(wazeroir.NewOperationNearest(wazeroir.Float32))) - require.NoError(t, err) - }, - verifyFunc: func(t *testing.T, v float64, raw uint64) { - exp := moremath.WasmCompatNearestF32(float32(v)) - actual := math.Float32frombits(uint32(raw)) - if math.IsNaN(float64(exp)) { // NaN cannot be compared with themselves, so we have to use IsNaN - require.True(t, math.IsNaN(float64(actual))) - } else { - require.Equal(t, exp, actual) - } - }, - }, - { - name: "nearest-64-bit", - is32bit: false, - setupFunc: func(t *testing.T, compiler compilerImpl) { - err := compiler.compileNearest(operationPtr(wazeroir.NewOperationNearest(wazeroir.Float64))) - require.NoError(t, err) - }, - verifyFunc: func(t *testing.T, v float64, raw uint64) { - exp := moremath.WasmCompatNearestF64(v) - actual := math.Float64frombits(raw) - if math.IsNaN(exp) { // NaN cannot be compared with themselves, so we have to use IsNaN - require.True(t, math.IsNaN(actual)) - } else { - require.Equal(t, exp, actual) - } - }, - }, - { - name: "sqrt-32-bit", - is32bit: true, - setupFunc: func(t *testing.T, compiler compilerImpl) { - err := compiler.compileSqrt(operationPtr(wazeroir.NewOperationSqrt(wazeroir.Float32))) - require.NoError(t, err) - }, - verifyFunc: func(t *testing.T, v float64, raw uint64) { - exp := float32(math.Sqrt(float64(v))) - actual := math.Float32frombits(uint32(raw)) - if math.IsNaN(float64(exp)) { // NaN cannot be compared with themselves, so we have to use IsNaN - require.True(t, math.IsNaN(float64(actual))) - } else { - require.Equal(t, exp, actual) - } - }, - }, - { - name: "sqrt-64-bit", - is32bit: false, - setupFunc: func(t *testing.T, compiler compilerImpl) { - err := compiler.compileSqrt(operationPtr(wazeroir.NewOperationSqrt(wazeroir.Float64))) - require.NoError(t, err) - }, - verifyFunc: func(t *testing.T, v float64, raw uint64) { - exp := math.Sqrt(v) - actual := math.Float64frombits(raw) - if math.IsNaN(exp) { // NaN cannot be compared with themselves, so we have to use IsNaN - require.True(t, math.IsNaN(actual)) - } else { - require.Equal(t, exp, actual) - } - }, - }, - } - - for _, tt := range tests { - tc := tt - t.Run(tc.name, func(t *testing.T) { - for _, v := range []float64{ - 0, 1 << 63, 1<<63 | 12345, 1 << 31, - 1<<31 | 123455, 6.8719476736e+10, - // This verifies that the impl is Wasm compatible in nearest, rather than being equivalent of math.Round. - // See moremath.WasmCompatNearestF32 and moremath.WasmCompatNearestF64 - -4.5, - 1.37438953472e+11, -1.3, - -1231.123, 1.3, 100.3, -100.3, 1231.123, - math.Inf(1), math.Inf(-1), math.NaN(), - } { - v := v - t.Run(fmt.Sprintf("%f", v), func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, nil) - err := compiler.compilePreamble() - require.NoError(t, err) - - if tc.is32bit { - err := compiler.compileConstF32(operationPtr(wazeroir.NewOperationConstF32(float32(v)))) - require.NoError(t, err) - } else { - err := compiler.compileConstF64(operationPtr(wazeroir.NewOperationConstF64(v))) - require.NoError(t, err) - } - - // At this point two values are pushed. - requireRuntimeLocationStackPointerEqual(t, uint64(1), compiler) - require.Equal(t, 1, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - - tc.setupFunc(t, compiler) - - // We consumed one value, but push the result after operation. - requireRuntimeLocationStackPointerEqual(t, uint64(1), compiler) - require.Equal(t, 1, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - require.Equal(t, nativeCallStatusCodeReturned, env.compilerStatus()) - require.Equal(t, uint64(1), env.stackPointer()) // Result must be pushed! - - tc.verifyFunc(t, v, env.stackTopAsUint64()) - }) - } - }) - } -} - -func TestCompiler_compile_Div_Rem(t *testing.T) { - for _, kind := range []wazeroir.OperationKind{ - wazeroir.OperationKindDiv, - wazeroir.OperationKindRem, - } { - kind := kind - t.Run(kind.String(), func(t *testing.T) { - for _, signedType := range []wazeroir.SignedType{ - wazeroir.SignedTypeUint32, - wazeroir.SignedTypeUint64, - wazeroir.SignedTypeInt32, - wazeroir.SignedTypeInt64, - wazeroir.SignedTypeFloat32, - wazeroir.SignedTypeFloat64, - } { - signedType := signedType - t.Run(signedType.String(), func(t *testing.T) { - for _, values := range [][2]uint64{ - {0, 0}, - {1, 1}, - {2, 1}, - {100, 1}, - {1, 0}, - {0, 1}, - {math.MaxInt16, math.MaxInt32}, - {1234, 5}, - {5, 1234}, - {4, 2}, - {40, 4}, - {123456, 4}, - {1 << 14, 1 << 21}, - {1 << 14, 1 << 21}, - {0xffff_ffff_ffff_ffff, 0}, - {0xffff_ffff_ffff_ffff, 1}, - {0, 0xffff_ffff_ffff_ffff}, - {1, 0xffff_ffff_ffff_ffff}, - {0x80000000, 0xffffffff}, // This is equivalent to (-2^31 / -1) and results in overflow for 32-bit signed div. - {0x8000000000000000, 0xffffffffffffffff}, // This is equivalent to (-2^63 / -1) and results in overflow for 64-bit signed div. - {0xffffffff /* -1 in signed 32bit */, 0xfffffffe /* -2 in signed 32bit */}, - {0xffffffffffffffff /* -1 in signed 64bit */, 0xfffffffffffffffe /* -2 in signed 64bit */}, - {1, 0xffff_ffff_ffff_ffff}, - {math.Float64bits(1.11231), math.Float64bits(12312312.12312)}, - {math.Float64bits(1.11231), math.Float64bits(-12312312.12312)}, - {math.Float64bits(-1.11231), math.Float64bits(12312312.12312)}, - {math.Float64bits(-1.11231), math.Float64bits(-12312312.12312)}, - {math.Float64bits(1.11231), math.Float64bits(12312312.12312)}, - {math.Float64bits(-12312312.12312), math.Float64bits(1.11231)}, - {math.Float64bits(12312312.12312), math.Float64bits(-1.11231)}, - {math.Float64bits(-12312312.12312), math.Float64bits(-1.11231)}, - {1, math.Float64bits(math.NaN())}, - {math.Float64bits(math.NaN()), 1}, - {0xffff_ffff_ffff_ffff, math.Float64bits(math.NaN())}, - {math.Float64bits(math.NaN()), 0xffff_ffff_ffff_ffff}, - {math.Float64bits(math.MaxFloat32), 1}, - {math.Float64bits(math.SmallestNonzeroFloat32), 1}, - {math.Float64bits(math.MaxFloat64), 1}, - {math.Float64bits(math.SmallestNonzeroFloat64), 1}, - {0, math.Float64bits(math.Inf(1))}, - {0, math.Float64bits(math.Inf(-1))}, - {math.Float64bits(math.Inf(1)), 0}, - {math.Float64bits(math.Inf(-1)), 0}, - {math.Float64bits(math.Inf(1)), 1}, - {math.Float64bits(math.Inf(-1)), 1}, - {math.Float64bits(1.11231), math.Float64bits(math.Inf(1))}, - {math.Float64bits(1.11231), math.Float64bits(math.Inf(-1))}, - {math.Float64bits(math.Inf(1)), math.Float64bits(1.11231)}, - {math.Float64bits(math.Inf(-1)), math.Float64bits(1.11231)}, - {math.Float64bits(math.Inf(1)), math.Float64bits(math.NaN())}, - {math.Float64bits(math.Inf(-1)), math.Float64bits(math.NaN())}, - {math.Float64bits(math.NaN()), math.Float64bits(math.Inf(1))}, - {math.Float64bits(math.NaN()), math.Float64bits(math.Inf(-1))}, - } { - x1, x2 := values[0], values[1] - t.Run(fmt.Sprintf("x1=0x%x,x2=0x%x", x1, x2), func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, nil) - err := compiler.compilePreamble() - require.NoError(t, err) - - // Emit consts operands. - for _, v := range []uint64{x1, x2} { - switch signedType { - case wazeroir.SignedTypeUint32: - // In order to test zero value on non-zero register, we directly assign an register. - loc := compiler.runtimeValueLocationStack().pushRuntimeValueLocationOnStack() - loc.valueType = runtimeValueTypeI32 - err = compiler.compileEnsureOnRegister(loc) - require.NoError(t, err) - env.stack()[loc.stackPointer] = uint64(v) - case wazeroir.SignedTypeInt32: - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(uint32(int32(v))))) - case wazeroir.SignedTypeInt64, wazeroir.SignedTypeUint64: - err = compiler.compileConstI64(operationPtr(wazeroir.NewOperationConstI64(v))) - case wazeroir.SignedTypeFloat32: - err = compiler.compileConstF32(operationPtr(wazeroir.NewOperationConstF32(math.Float32frombits(uint32(v))))) - case wazeroir.SignedTypeFloat64: - err = compiler.compileConstF64(operationPtr(wazeroir.NewOperationConstF64(math.Float64frombits(v)))) - } - require.NoError(t, err) - } - - // At this point, two values exist for comparison. - requireRuntimeLocationStackPointerEqual(t, uint64(2), compiler) - - switch kind { - case wazeroir.OperationKindDiv: - err = compiler.compileDiv(operationPtr(wazeroir.NewOperationDiv(signedType))) - case wazeroir.OperationKindRem: - switch signedType { - case wazeroir.SignedTypeInt32: - err = compiler.compileRem(operationPtr(wazeroir.NewOperationRem(wazeroir.SignedInt32))) - case wazeroir.SignedTypeInt64: - err = compiler.compileRem(operationPtr(wazeroir.NewOperationRem(wazeroir.SignedInt64))) - case wazeroir.SignedTypeUint32: - err = compiler.compileRem(operationPtr(wazeroir.NewOperationRem(wazeroir.SignedUint32))) - case wazeroir.SignedTypeUint64: - err = compiler.compileRem(operationPtr(wazeroir.NewOperationRem(wazeroir.SignedUint64))) - case wazeroir.SignedTypeFloat32: - // Rem undefined for float32. - return - case wazeroir.SignedTypeFloat64: - // Rem undefined for float64. - return - } - } - require.NoError(t, err) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Compile and execute the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - switch kind { - case wazeroir.OperationKindDiv: - switch signedType { - case wazeroir.SignedTypeUint32: - if uint32(x2) == 0 { - require.Equal(t, nativeCallStatusIntegerDivisionByZero, env.compilerStatus()) - } else { - require.Equal(t, uint32(x1)/uint32(x2), env.stackTopAsUint32()) - } - case wazeroir.SignedTypeInt32: - v1, v2 := int32(x1), int32(x2) - if v2 == 0 { - require.Equal(t, nativeCallStatusIntegerDivisionByZero, env.compilerStatus()) - } else if v1 == math.MinInt32 && v2 == -1 { - require.Equal(t, nativeCallStatusIntegerOverflow, env.compilerStatus()) - } else { - require.Equal(t, v1/v2, env.stackTopAsInt32()) - } - case wazeroir.SignedTypeUint64: - if x2 == 0 { - require.Equal(t, nativeCallStatusIntegerDivisionByZero, env.compilerStatus()) - } else { - require.Equal(t, x1/x2, env.stackTopAsUint64()) - } - case wazeroir.SignedTypeInt64: - v1, v2 := int64(x1), int64(x2) - if v2 == 0 { - require.Equal(t, nativeCallStatusIntegerDivisionByZero, env.compilerStatus()) - } else if v1 == math.MinInt64 && v2 == -1 { - require.Equal(t, nativeCallStatusIntegerOverflow, env.compilerStatus()) - } else { - require.Equal(t, v1/v2, env.stackTopAsInt64()) - } - case wazeroir.SignedTypeFloat32: - exp := math.Float32frombits(uint32(x1)) / math.Float32frombits(uint32(x2)) - // NaN cannot be compared with themselves, so we have to use IsNaN - if math.IsNaN(float64(exp)) { - require.True(t, math.IsNaN(float64(env.stackTopAsFloat32()))) - } else { - require.Equal(t, exp, env.stackTopAsFloat32()) - } - case wazeroir.SignedTypeFloat64: - exp := math.Float64frombits(x1) / math.Float64frombits(x2) - // NaN cannot be compared with themselves, so we have to use IsNaN - if math.IsNaN(exp) { - require.True(t, math.IsNaN(env.stackTopAsFloat64())) - } else { - require.Equal(t, exp, env.stackTopAsFloat64()) - } - } - case wazeroir.OperationKindRem: - switch signedType { - case wazeroir.SignedTypeInt32: - v1, v2 := int32(x1), int32(x2) - if v2 == 0 { - require.Equal(t, nativeCallStatusIntegerDivisionByZero, env.compilerStatus()) - } else { - require.Equal(t, v1%v2, env.stackTopAsInt32()) - } - case wazeroir.SignedTypeInt64: - v1, v2 := int64(x1), int64(x2) - if v2 == 0 { - require.Equal(t, nativeCallStatusIntegerDivisionByZero, env.compilerStatus()) - } else { - require.Equal(t, v1%v2, env.stackTopAsInt64()) - } - case wazeroir.SignedTypeUint32: - v1, v2 := uint32(x1), uint32(x2) - if v2 == 0 { - require.Equal(t, nativeCallStatusIntegerDivisionByZero, env.compilerStatus()) - } else { - require.Equal(t, v1%v2, env.stackTopAsUint32()) - } - case wazeroir.SignedTypeUint64: - if x2 == 0 { - require.Equal(t, nativeCallStatusIntegerDivisionByZero, env.compilerStatus()) - } else { - require.Equal(t, x1%x2, env.stackTopAsUint64()) - } - - } - } - }) - } - }) - } - }) - } -} diff --git a/internal/engine/compiler/compiler_post1_0_test.go b/internal/engine/compiler/compiler_post1_0_test.go deleted file mode 100644 index b76be97513..0000000000 --- a/internal/engine/compiler/compiler_post1_0_test.go +++ /dev/null @@ -1,999 +0,0 @@ -package compiler - -import ( - "fmt" - "strconv" - "testing" - "unsafe" - - "github.com/tetratelabs/wazero/internal/asm" - "github.com/tetratelabs/wazero/internal/testing/require" - "github.com/tetratelabs/wazero/internal/wasm" - "github.com/tetratelabs/wazero/internal/wazeroir" -) - -func TestCompiler_compileSignExtend(t *testing.T) { - type fromKind byte - from8, from16, from32 := fromKind(0), fromKind(1), fromKind(2) - - t.Run("32bit", func(t *testing.T) { - tests := []struct { - in int32 - expected int32 - fromKind fromKind - }{ - // https://github.com/WebAssembly/spec/blob/ee4a6c40afa22e3e4c58610ce75186aafc22344e/test/core/i32.wast#L270-L276 - {in: 0, expected: 0, fromKind: from8}, - {in: 0x7f, expected: 127, fromKind: from8}, - {in: 0x80, expected: -128, fromKind: from8}, - {in: 0xff, expected: -1, fromKind: from8}, - {in: 0x012345_00, expected: 0, fromKind: from8}, - {in: -19088768 /* = 0xfedcba_80 bit pattern */, expected: -0x80, fromKind: from8}, - {in: -1, expected: -1, fromKind: from8}, - - // https://github.com/WebAssembly/spec/blob/ee4a6c40afa22e3e4c58610ce75186aafc22344e/test/core/i32.wast#L278-L284 - {in: 0, expected: 0, fromKind: from16}, - {in: 0x7fff, expected: 32767, fromKind: from16}, - {in: 0x8000, expected: -32768, fromKind: from16}, - {in: 0xffff, expected: -1, fromKind: from16}, - {in: 0x0123_0000, expected: 0, fromKind: from16}, - {in: -19103744 /* = 0xfedc_8000 bit pattern */, expected: -0x8000, fromKind: from16}, - {in: -1, expected: -1, fromKind: from16}, - } - - for _, tt := range tests { - tc := tt - t.Run(fmt.Sprintf("0x%x", tc.in), func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, nil) - err := compiler.compilePreamble() - require.NoError(t, err) - - // Setup the promote target. - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(uint32(tc.in)))) - require.NoError(t, err) - - if tc.fromKind == from8 { - err = compiler.compileSignExtend32From8() - } else { - err = compiler.compileSignExtend32From16() - } - require.NoError(t, err) - - // To verify the behavior, we release the value - // to the stack. - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - require.Equal(t, uint64(1), env.stackPointer()) - require.Equal(t, tc.expected, env.stackTopAsInt32()) - }) - } - }) - t.Run("64bit", func(t *testing.T) { - tests := []struct { - in int64 - expected int64 - fromKind fromKind - }{ - // https://github.com/WebAssembly/spec/blob/ee4a6c40afa22e3e4c58610ce75186aafc22344e/test/core/i64.wast#L271-L277 - {in: 0, expected: 0, fromKind: from8}, - {in: 0x7f, expected: 127, fromKind: from8}, - {in: 0x80, expected: -128, fromKind: from8}, - {in: 0xff, expected: -1, fromKind: from8}, - {in: 0x01234567_89abcd_00, expected: 0, fromKind: from8}, - {in: 81985529216486784 /* = 0xfedcba98_765432_80 bit pattern */, expected: -0x80, fromKind: from8}, - {in: -1, expected: -1, fromKind: from8}, - - // https://github.com/WebAssembly/spec/blob/ee4a6c40afa22e3e4c58610ce75186aafc22344e/test/core/i64.wast#L279-L285 - {in: 0, expected: 0, fromKind: from16}, - {in: 0x7fff, expected: 32767, fromKind: from16}, - {in: 0x8000, expected: -32768, fromKind: from16}, - {in: 0xffff, expected: -1, fromKind: from16}, - {in: 0x12345678_9abc_0000, expected: 0, fromKind: from16}, - {in: 81985529216466944 /* = 0xfedcba98_7654_8000 bit pattern */, expected: -0x8000, fromKind: from16}, - {in: -1, expected: -1, fromKind: from16}, - - // https://github.com/WebAssembly/spec/blob/ee4a6c40afa22e3e4c58610ce75186aafc22344e/test/core/i64.wast#L287-L296 - {in: 0, expected: 0, fromKind: from32}, - {in: 0x7fff, expected: 32767, fromKind: from32}, - {in: 0x8000, expected: 32768, fromKind: from32}, - {in: 0xffff, expected: 65535, fromKind: from32}, - {in: 0x7fffffff, expected: 0x7fffffff, fromKind: from32}, - {in: 0x80000000, expected: -0x80000000, fromKind: from32}, - {in: 0xffffffff, expected: -1, fromKind: from32}, - {in: 0x01234567_00000000, expected: 0, fromKind: from32}, - {in: -81985529054232576 /* = 0xfedcba98_80000000 bit pattern */, expected: -0x80000000, fromKind: from32}, - {in: -1, expected: -1, fromKind: from32}, - } - - for _, tt := range tests { - tc := tt - t.Run(fmt.Sprintf("0x%x", tc.in), func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, nil) - err := compiler.compilePreamble() - require.NoError(t, err) - - // Setup the promote target. - err = compiler.compileConstI64(operationPtr(wazeroir.NewOperationConstI64(uint64(tc.in)))) - require.NoError(t, err) - - if tc.fromKind == from8 { - err = compiler.compileSignExtend64From8() - } else if tc.fromKind == from16 { - err = compiler.compileSignExtend64From16() - } else { - err = compiler.compileSignExtend64From32() - } - require.NoError(t, err) - - // To verify the behavior, we release the value - // to the stack. - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - require.Equal(t, uint64(1), env.stackPointer()) - require.Equal(t, tc.expected, env.stackTopAsInt64()) - }) - } - }) -} - -func TestCompiler_compileMemoryCopy(t *testing.T) { - const checkCeil = 100 - tests := []struct { - sourceOffset, destOffset, size uint32 - requireOutOfBoundsError bool - }{ - {sourceOffset: 0, destOffset: 0, size: 0}, - {sourceOffset: 10, destOffset: 5, size: 10}, - {sourceOffset: 10, destOffset: 9, size: 1}, - {sourceOffset: 10, destOffset: 9, size: 2}, - {sourceOffset: 0, destOffset: 10, size: 10}, - {sourceOffset: 0, destOffset: 5, size: 10}, - {sourceOffset: 9, destOffset: 10, size: 10}, - {sourceOffset: 11, destOffset: 13, size: 4}, - {sourceOffset: 0, destOffset: 10, size: 5}, - {sourceOffset: 1, destOffset: 10, size: 5}, - {sourceOffset: 0, destOffset: 10, size: 1}, - {sourceOffset: 0, destOffset: 10, size: 0}, - {sourceOffset: 5, destOffset: 10, size: 10}, - {sourceOffset: 5, destOffset: 10, size: 5}, - {sourceOffset: 5, destOffset: 10, size: 1}, - {sourceOffset: 5, destOffset: 10, size: 0}, - {sourceOffset: 10, destOffset: 0, size: 10}, - {sourceOffset: 1, destOffset: 0, size: 2}, - {sourceOffset: 1, destOffset: 0, size: 20}, - {sourceOffset: 10, destOffset: 0, size: 5}, - {sourceOffset: 10, destOffset: 0, size: 1}, - {sourceOffset: 10, destOffset: 0, size: 0}, - {sourceOffset: 0, destOffset: 50, size: 48}, - {sourceOffset: 0, destOffset: 50, size: 49}, - {sourceOffset: 10, destOffset: 20, size: 72}, - {sourceOffset: 20, destOffset: 10, size: 72}, - {sourceOffset: 19, destOffset: 18, size: 79}, - {sourceOffset: 20, destOffset: 19, size: 79}, - {sourceOffset: defaultMemoryPageNumInTest * wasm.MemoryPageSize, destOffset: 0, size: 1, requireOutOfBoundsError: true}, - {sourceOffset: defaultMemoryPageNumInTest*wasm.MemoryPageSize + 1, destOffset: 0, size: 0, requireOutOfBoundsError: true}, - {sourceOffset: 0, destOffset: defaultMemoryPageNumInTest * wasm.MemoryPageSize, size: 1, requireOutOfBoundsError: true}, - {sourceOffset: 0, destOffset: defaultMemoryPageNumInTest*wasm.MemoryPageSize + 1, size: 0, requireOutOfBoundsError: true}, - {sourceOffset: defaultMemoryPageNumInTest*wasm.MemoryPageSize - 99, destOffset: 0, size: 100, requireOutOfBoundsError: true}, - {sourceOffset: 0, destOffset: defaultMemoryPageNumInTest*wasm.MemoryPageSize - 99, size: 100, requireOutOfBoundsError: true}, - } - - for i, tt := range tests { - tc := tt - t.Run(strconv.Itoa(i), func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - // Compile operands. - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(tc.destOffset))) - require.NoError(t, err) - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(tc.sourceOffset))) - require.NoError(t, err) - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(tc.size))) - require.NoError(t, err) - - err = compiler.compileMemoryCopy() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate the code under test. - err = compiler.compileReturnFunction() - require.NoError(t, err) - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - - // Setup the source memory region. - mem := env.memory() - for i := 0; i < checkCeil; i++ { - mem[i] = byte(i) - } - - // Run code. - env.exec(code.Bytes()) - - if !tc.requireOutOfBoundsError { - exp := make([]byte, checkCeil) - for i := 0; i < checkCeil; i++ { - exp[i] = byte(i) - } - copy(exp[tc.destOffset:], - exp[tc.sourceOffset:tc.sourceOffset+tc.size]) - - // Check the status code and the destination memory region. - require.Equal(t, nativeCallStatusCodeReturned, env.compilerStatus()) - require.Equal(t, exp, mem[:checkCeil]) - } else { - require.Equal(t, nativeCallStatusCodeMemoryOutOfBounds, env.compilerStatus()) - } - }) - } -} - -func TestCompiler_compileMemoryFill(t *testing.T) { - const checkCeil = 50 - - tests := []struct { - v, destOffset uint32 - size uint32 - requireOutOfBoundsError bool - }{ - {v: 0, destOffset: 0, size: 25}, - {v: 0, destOffset: 10, size: 17}, - {v: 0, destOffset: 10, size: 15}, - {v: 0, destOffset: 10, size: 5}, - {v: 0, destOffset: 10, size: 1}, - {v: 0, destOffset: 10, size: 0}, - {v: 5, destOffset: 10, size: 27}, - {v: 5, destOffset: 10, size: 25}, - {v: 5, destOffset: 10, size: 21}, - {v: 5, destOffset: 10, size: 10}, - {v: 5, destOffset: 10, size: 5}, - {v: 5, destOffset: 10, size: 1}, - {v: 5, destOffset: 10, size: 0}, - {v: 10, destOffset: 0, size: 10}, - {v: 10, destOffset: 0, size: 5}, - {v: 10, destOffset: 0, size: 1}, - {v: 10, destOffset: 0, size: 0}, - {v: 10, destOffset: defaultMemoryPageNumInTest*wasm.MemoryPageSize - 99, size: 100, requireOutOfBoundsError: true}, - {v: 10, destOffset: defaultMemoryPageNumInTest * wasm.MemoryPageSize, size: 5, requireOutOfBoundsError: true}, - {v: 10, destOffset: defaultMemoryPageNumInTest * wasm.MemoryPageSize, size: 1, requireOutOfBoundsError: true}, - {v: 10, destOffset: defaultMemoryPageNumInTest*wasm.MemoryPageSize + 1, size: 0, requireOutOfBoundsError: true}, - } - - for i, tt := range tests { - tc := tt - t.Run(strconv.Itoa(i), func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - // Compile operands. - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(tc.destOffset))) - require.NoError(t, err) - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(tc.v))) - require.NoError(t, err) - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(tc.size))) - require.NoError(t, err) - - err = compiler.compileMemoryFill() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate the code under test. - err = compiler.compileReturnFunction() - require.NoError(t, err) - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - - // Setup the memory region. - mem := env.memory() - for i := 0; i < checkCeil; i++ { - mem[i] = byte(i) - } - - // Run code. - env.exec(code.Bytes()) - - if !tc.requireOutOfBoundsError { - exp := make([]byte, checkCeil) - for i := 0; i < checkCeil; i++ { - if i >= int(tc.destOffset) && i < int(tc.destOffset+tc.size) { - exp[i] = byte(tc.v) - } else { - exp[i] = byte(i) - } - } - - // Check the status code and the destination memory region. - require.Equal(t, nativeCallStatusCodeReturned, env.compilerStatus()) - require.Equal(t, exp, mem[:checkCeil]) - } else { - require.Equal(t, nativeCallStatusCodeMemoryOutOfBounds, env.compilerStatus()) - } - }) - } -} - -func TestCompiler_compileDataDrop(t *testing.T) { - origins := [][]byte{ - {1}, {2}, {3}, {4}, {5}, {6}, {7}, {8}, {9}, {10}, - } - - for i := 0; i < len(origins); i++ { - t.Run(strconv.Itoa(i), func(t *testing.T) { - env := newCompilerEnvironment() - - env.module().DataInstances = make([][]byte, len(origins)) - copy(env.module().DataInstances, origins) - - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, &wazeroir.CompilationResult{ - HasDataInstances: true, - }) - - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileDataDrop(operationPtr(wazeroir.NewOperationDataDrop(uint32(i)))) - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate the code under test. - err = compiler.compileReturnFunction() - require.NoError(t, err) - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - - // Run code. - env.exec(code.Bytes()) - - require.Equal(t, nativeCallStatusCodeReturned, env.compilerStatus()) - - // Check if the target data instance is dropped from the dataInstances slice. - for j := 0; j < len(origins); j++ { - if i == j { - require.Nil(t, env.module().DataInstances[j]) - } else { - require.NotNil(t, env.module().DataInstances[j]) - } - } - }) - } -} - -func TestCompiler_compileMemoryInit(t *testing.T) { - dataInstances := []wasm.DataInstance{ - nil, {1, 2, 3, 4, 5}, - } - - tests := []struct { - sourceOffset, destOffset uint32 - dataIndex uint32 - copySize uint32 - expOutOfBounds bool - }{ - {sourceOffset: 0, destOffset: 0, copySize: 0, dataIndex: 0}, - {sourceOffset: 0, destOffset: 0, copySize: 1, dataIndex: 0, expOutOfBounds: true}, - {sourceOffset: 1, destOffset: 0, copySize: 0, dataIndex: 0, expOutOfBounds: true}, - {sourceOffset: 0, destOffset: 0, copySize: 0, dataIndex: 1}, - {sourceOffset: 0, destOffset: 0, copySize: 5, dataIndex: 1}, - {sourceOffset: 0, destOffset: 0, copySize: 1, dataIndex: 1}, - {sourceOffset: 0, destOffset: 0, copySize: 3, dataIndex: 1}, - {sourceOffset: 0, destOffset: 1, copySize: 3, dataIndex: 1}, - {sourceOffset: 0, destOffset: 7, copySize: 4, dataIndex: 1}, - {sourceOffset: 1, destOffset: 7, copySize: 4, dataIndex: 1}, - {sourceOffset: 4, destOffset: 7, copySize: 1, dataIndex: 1}, - {sourceOffset: 5, destOffset: 7, copySize: 0, dataIndex: 1}, - {sourceOffset: 0, destOffset: 7, copySize: 5, dataIndex: 1}, - {sourceOffset: 1, destOffset: 0, copySize: 3, dataIndex: 1}, - {sourceOffset: 0, destOffset: 1, copySize: 4, dataIndex: 1}, - {sourceOffset: 1, destOffset: 1, copySize: 3, dataIndex: 1}, - {sourceOffset: 0, destOffset: 10, copySize: 5, dataIndex: 1}, - {sourceOffset: 0, destOffset: 0, copySize: 6, dataIndex: 1, expOutOfBounds: true}, - {sourceOffset: 0, destOffset: defaultMemoryPageNumInTest * wasm.MemoryPageSize, copySize: 5, dataIndex: 1, expOutOfBounds: true}, - {sourceOffset: 0, destOffset: defaultMemoryPageNumInTest*wasm.MemoryPageSize - 3, copySize: 5, dataIndex: 1, expOutOfBounds: true}, - {sourceOffset: 6, destOffset: 0, copySize: 0, dataIndex: 1, expOutOfBounds: true}, - } - - for i, tt := range tests { - tc := tt - t.Run(strconv.Itoa(i), func(t *testing.T) { - env := newCompilerEnvironment() - env.module().DataInstances = dataInstances - - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, &wazeroir.CompilationResult{ - HasDataInstances: true, Memory: wazeroir.MemoryTypeStandard, - }) - - err := compiler.compilePreamble() - require.NoError(t, err) - - // Compile operands. - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(tc.destOffset))) - require.NoError(t, err) - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(tc.sourceOffset))) - require.NoError(t, err) - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(tc.copySize))) - require.NoError(t, err) - - err = compiler.compileMemoryInit(operationPtr(wazeroir.NewOperationMemoryInit(tc.dataIndex))) - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate the code under test. - err = compiler.compileReturnFunction() - require.NoError(t, err) - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - - // Run code. - env.exec(code.Bytes()) - - if !tc.expOutOfBounds { - mem := env.memory() - exp := make([]byte, defaultMemoryPageNumInTest*wasm.MemoryPageSize) - if dataInst := dataInstances[tc.dataIndex]; dataInst != nil { - copy(exp[tc.destOffset:], dataInst[tc.sourceOffset:tc.sourceOffset+tc.copySize]) - } - require.Equal(t, exp[:20], mem[:20]) - } else { - require.Equal(t, nativeCallStatusCodeMemoryOutOfBounds, env.compilerStatus()) - } - }) - } -} - -func TestCompiler_compileElemDrop(t *testing.T) { - origins := []wasm.ElementInstance{{1}, {2}, {3}, {4}, {5}} - - for i := 0; i < len(origins); i++ { - t.Run(strconv.Itoa(i), func(t *testing.T) { - env := newCompilerEnvironment() - - insts := make([]wasm.ElementInstance, len(origins)) - copy(insts, origins) - env.module().ElementInstances = insts - - // Verify assumption that before Drop instruction, all the element instances are not empty. - for _, inst := range insts { - require.NotEqual(t, 0, len(inst)) - } - - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, &wazeroir.CompilationResult{ - HasElementInstances: true, - }) - - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileElemDrop(operationPtr(wazeroir.NewOperationElemDrop(uint32(i)))) - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate the code under test. - err = compiler.compileReturnFunction() - require.NoError(t, err) - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - - // Run code. - env.exec(code.Bytes()) - - require.Equal(t, nativeCallStatusCodeReturned, env.compilerStatus()) - - for j := 0; j < len(insts); j++ { - if i == j { - require.Zero(t, len(env.module().ElementInstances[j])) - } else { - require.NotEqual(t, 0, len(env.module().ElementInstances[j])) - } - } - }) - } -} - -func TestCompiler_compileTableCopy(t *testing.T) { - const tableSize = 100 - tests := []struct { - sourceOffset, destOffset, size uint32 - requireOutOfBoundsError bool - }{ - {sourceOffset: 0, destOffset: 0, size: 0}, - {sourceOffset: 10, destOffset: 5, size: 10}, - {sourceOffset: 10, destOffset: 9, size: 1}, - {sourceOffset: 10, destOffset: 9, size: 2}, - {sourceOffset: 0, destOffset: 10, size: 10}, - {sourceOffset: 0, destOffset: 5, size: 10}, - {sourceOffset: 9, destOffset: 10, size: 10}, - {sourceOffset: 11, destOffset: 13, size: 4}, - {sourceOffset: 0, destOffset: 10, size: 5}, - {sourceOffset: 1, destOffset: 10, size: 5}, - {sourceOffset: 0, destOffset: 10, size: 1}, - {sourceOffset: 0, destOffset: 10, size: 0}, - {sourceOffset: 5, destOffset: 10, size: 10}, - {sourceOffset: 5, destOffset: 10, size: 5}, - {sourceOffset: 5, destOffset: 10, size: 1}, - {sourceOffset: 5, destOffset: 10, size: 0}, - {sourceOffset: 10, destOffset: 0, size: 10}, - {sourceOffset: 1, destOffset: 0, size: 2}, - {sourceOffset: 1, destOffset: 0, size: 20}, - {sourceOffset: 10, destOffset: 0, size: 5}, - {sourceOffset: 10, destOffset: 0, size: 1}, - {sourceOffset: 10, destOffset: 0, size: 0}, - {sourceOffset: tableSize, destOffset: 0, size: 1, requireOutOfBoundsError: true}, - {sourceOffset: tableSize + 1, destOffset: 0, size: 0, requireOutOfBoundsError: true}, - {sourceOffset: 0, destOffset: tableSize, size: 1, requireOutOfBoundsError: true}, - {sourceOffset: 0, destOffset: tableSize + 1, size: 0, requireOutOfBoundsError: true}, - {sourceOffset: tableSize - 99, destOffset: 0, size: 100, requireOutOfBoundsError: true}, - {sourceOffset: 0, destOffset: tableSize - 99, size: 100, requireOutOfBoundsError: true}, - } - - for i, tt := range tests { - tc := tt - t.Run(strconv.Itoa(i), func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, &wazeroir.CompilationResult{HasTable: true}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - // Compile operands. - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(tc.destOffset))) - require.NoError(t, err) - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(tc.sourceOffset))) - require.NoError(t, err) - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(tc.size))) - require.NoError(t, err) - - err = compiler.compileTableCopy(operationPtr(wazeroir.NewOperationTableCopy(0, 0))) - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate the code under test. - err = compiler.compileReturnFunction() - require.NoError(t, err) - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - - // Setup the table. - table := make([]wasm.Reference, tableSize) - env.addTable(&wasm.TableInstance{References: table}) - for i := 0; i < tableSize; i++ { - table[i] = uintptr(i) - } - - // Run code. - env.exec(code.Bytes()) - - if !tc.requireOutOfBoundsError { - exp := make([]wasm.Reference, tableSize) - for i := 0; i < tableSize; i++ { - exp[i] = uintptr(i) - } - copy(exp[tc.destOffset:], - exp[tc.sourceOffset:tc.sourceOffset+tc.size]) - - // Check the status code and the destination memory region. - require.Equal(t, nativeCallStatusCodeReturned, env.compilerStatus()) - require.Equal(t, exp, table) - } else { - require.Equal(t, nativeCallStatusCodeInvalidTableAccess, env.compilerStatus()) - } - }) - } -} - -func TestCompiler_compileTableInit(t *testing.T) { - elementInstances := []wasm.ElementInstance{ - {}, {1, 2, 3, 4, 5}, - } - - const tableSize = 100 - tests := []struct { - sourceOffset, destOffset uint32 - elemIndex uint32 - copySize uint32 - expOutOfBounds bool - }{ - {sourceOffset: 0, destOffset: 0, copySize: 0, elemIndex: 0}, - {sourceOffset: 0, destOffset: 0, copySize: 1, elemIndex: 0, expOutOfBounds: true}, - {sourceOffset: 1, destOffset: 0, copySize: 0, elemIndex: 0, expOutOfBounds: true}, - {sourceOffset: 0, destOffset: 0, copySize: 0, elemIndex: 1}, - {sourceOffset: 0, destOffset: 0, copySize: 5, elemIndex: 1}, - {sourceOffset: 0, destOffset: 0, copySize: 1, elemIndex: 1}, - {sourceOffset: 0, destOffset: 0, copySize: 3, elemIndex: 1}, - {sourceOffset: 0, destOffset: 1, copySize: 3, elemIndex: 1}, - {sourceOffset: 0, destOffset: 7, copySize: 4, elemIndex: 1}, - {sourceOffset: 1, destOffset: 7, copySize: 4, elemIndex: 1}, - {sourceOffset: 4, destOffset: 7, copySize: 1, elemIndex: 1}, - {sourceOffset: 5, destOffset: 7, copySize: 0, elemIndex: 1}, - {sourceOffset: 0, destOffset: 7, copySize: 5, elemIndex: 1}, - {sourceOffset: 1, destOffset: 0, copySize: 3, elemIndex: 1}, - {sourceOffset: 0, destOffset: 1, copySize: 4, elemIndex: 1}, - {sourceOffset: 1, destOffset: 1, copySize: 3, elemIndex: 1}, - {sourceOffset: 0, destOffset: 10, copySize: 5, elemIndex: 1}, - {sourceOffset: 0, destOffset: 0, copySize: 6, elemIndex: 1, expOutOfBounds: true}, - {sourceOffset: 6, destOffset: 0, copySize: 0, elemIndex: 1, expOutOfBounds: true}, - } - - for i, tt := range tests { - tc := tt - t.Run(strconv.Itoa(i), func(t *testing.T) { - env := newCompilerEnvironment() - env.module().ElementInstances = elementInstances - - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, &wazeroir.CompilationResult{ - HasElementInstances: true, HasTable: true, - }) - - err := compiler.compilePreamble() - require.NoError(t, err) - - // Compile operands. - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(tc.destOffset))) - require.NoError(t, err) - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(tc.sourceOffset))) - require.NoError(t, err) - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(tc.copySize))) - require.NoError(t, err) - - err = compiler.compileTableInit(operationPtr(wazeroir.NewOperationTableInit(tc.elemIndex, 0))) - require.NoError(t, err) - - // Setup the table. - table := make([]wasm.Reference, tableSize) - env.addTable(&wasm.TableInstance{References: table}) - for i := 0; i < tableSize; i++ { - table[i] = uintptr(i) - } - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate the code under test. - err = compiler.compileReturnFunction() - require.NoError(t, err) - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - - // Run code. - env.exec(code.Bytes()) - - if !tc.expOutOfBounds { - require.Equal(t, nativeCallStatusCodeReturned, env.compilerStatus()) - exp := make([]wasm.Reference, tableSize) - for i := 0; i < tableSize; i++ { - exp[i] = uintptr(i) - } - if inst := elementInstances[tc.elemIndex]; inst != nil { - copy(exp[tc.destOffset:], inst[tc.sourceOffset:tc.sourceOffset+tc.copySize]) - } - require.Equal(t, exp, table) - } else { - require.Equal(t, nativeCallStatusCodeInvalidTableAccess, env.compilerStatus()) - } - }) - } -} - -type dog struct{ name string } - -func TestCompiler_compileTableSet(t *testing.T) { - externDog := &dog{name: "sushi"} - externrefOpaque := uintptr(unsafe.Pointer(externDog)) - funcref := &function{moduleInstance: &wasm.ModuleInstance{}} - funcrefOpaque := uintptr(unsafe.Pointer(funcref)) - - externTable := &wasm.TableInstance{Type: wasm.RefTypeExternref, References: []wasm.Reference{0, 0, externrefOpaque, 0, 0}} - funcrefTable := &wasm.TableInstance{Type: wasm.RefTypeFuncref, References: []wasm.Reference{0, 0, 0, 0, funcrefOpaque}} - tables := []*wasm.TableInstance{externTable, funcrefTable} - - tests := []struct { - name string - tableIndex uint32 - offset uint32 - in uintptr - expExtern bool - expError bool - }{ - { - name: "externref - non nil", - tableIndex: 0, - offset: 2, - in: externrefOpaque, - expExtern: true, - }, - { - name: "externref - nil", - tableIndex: 0, - offset: 1, - in: 0, - expExtern: true, - }, - { - name: "externref - out of bounds", - tableIndex: 0, - offset: 10, - in: 0, - expError: true, - }, - { - name: "funcref - non nil", - tableIndex: 1, - offset: 4, - in: funcrefOpaque, - expExtern: false, - }, - { - name: "funcref - nil", - tableIndex: 1, - offset: 3, - in: 0, - expExtern: false, - }, - { - name: "funcref - out of bounds", - tableIndex: 1, - offset: 100000, - in: 0, - expError: true, - }, - } - - for _, tt := range tests { - tc := tt - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - - for _, table := range tables { - env.addTable(table) - } - - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, &wazeroir.CompilationResult{ - HasTable: true, - }) - - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(tc.offset))) - require.NoError(t, err) - - err = compiler.compileConstI64(operationPtr(wazeroir.NewOperationConstI64(uint64(tc.in)))) - require.NoError(t, err) - - err = compiler.compileTableSet(operationPtr(wazeroir.NewOperationTableSet(tc.tableIndex))) - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate the code under test. - err = compiler.compileReturnFunction() - require.NoError(t, err) - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - - // Run code. - env.exec(code.Bytes()) - - if tc.expError { - require.Equal(t, nativeCallStatusCodeInvalidTableAccess, env.compilerStatus()) - } else { - require.Equal(t, nativeCallStatusCodeReturned, env.compilerStatus()) - require.Equal(t, uint64(0), env.stackPointer()) - - if tc.expExtern { - actual := dogFromPtr(externTable.References[tc.offset]) - exp := externDog - if tc.in == 0 { - exp = nil - } - require.Equal(t, exp, actual) - } else { - actual := functionFromPtr(funcrefTable.References[tc.offset]) - exp := funcref - if tc.in == 0 { - exp = nil - } - require.Equal(t, exp, actual) - } - } - }) - } -} - -//go:nocheckptr ignore "pointer arithmetic result points to invalid allocation" -func dogFromPtr(ptr uintptr) *dog { - if ptr == 0 { - return nil - } - return (*dog)(unsafe.Pointer(ptr)) -} - -//go:nocheckptr ignore "pointer arithmetic result points to invalid allocation" -func functionFromPtr(ptr uintptr) *function { - if ptr == 0 { - return nil - } - return (*function)(unsafe.Pointer(ptr)) -} - -func TestCompiler_compileTableGet(t *testing.T) { - externDog := &dog{name: "sushi"} - externrefOpaque := uintptr(unsafe.Pointer(externDog)) - funcref := &function{moduleInstance: &wasm.ModuleInstance{}} - funcrefOpaque := uintptr(unsafe.Pointer(funcref)) - tables := []*wasm.TableInstance{ - {Type: wasm.RefTypeExternref, References: []wasm.Reference{0, 0, externrefOpaque, 0, 0}}, - {Type: wasm.RefTypeFuncref, References: []wasm.Reference{0, 0, 0, 0, funcrefOpaque}}, - } - - tests := []struct { - name string - tableIndex uint32 - offset uint32 - exp uintptr - expError bool - }{ - { - name: "externref - non nil", - tableIndex: 0, - offset: 2, - exp: externrefOpaque, - }, - { - name: "externref - nil", - tableIndex: 0, - offset: 4, - exp: 0, - }, - { - name: "externref - out of bounds", - tableIndex: 0, - offset: 5, - expError: true, - }, - { - name: "funcref - non nil", - tableIndex: 1, - offset: 4, - exp: funcrefOpaque, - }, - { - name: "funcref - nil", - tableIndex: 1, - offset: 1, - exp: 0, - }, - { - name: "funcref - out of bounds", - tableIndex: 1, - offset: 1000, - expError: true, - }, - } - - for _, tt := range tests { - tc := tt - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - - for _, table := range tables { - env.addTable(table) - } - - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, &wazeroir.CompilationResult{ - HasTable: true, - }) - - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(tc.offset))) - require.NoError(t, err) - - err = compiler.compileTableGet(operationPtr(wazeroir.NewOperationTableGet(tc.tableIndex))) - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate the code under test. - err = compiler.compileReturnFunction() - require.NoError(t, err) - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - - // Run code. - env.exec(code.Bytes()) - - if tc.expError { - require.Equal(t, nativeCallStatusCodeInvalidTableAccess, env.compilerStatus()) - } else { - require.Equal(t, nativeCallStatusCodeReturned, env.compilerStatus()) - require.Equal(t, uint64(1), env.stackPointer()) - require.Equal(t, uint64(tc.exp), env.stackTopAsUint64()) - } - }) - } -} - -func TestCompiler_compileRefFunc(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, &wazeroir.CompilationResult{}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - me := env.moduleEngine() - const numFuncs = 20 - for i := 0; i < numFuncs; i++ { - me.functions = append(me.functions, function{moduleInstance: &wasm.ModuleInstance{}}) - } - - for i := 0; i < numFuncs; i++ { - i := i - t.Run(strconv.Itoa(i), func(t *testing.T) { - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, &wazeroir.CompilationResult{}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileRefFunc(operationPtr(wazeroir.NewOperationRefFunc(uint32(i)))) - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate the code under test. - err = compiler.compileReturnFunction() - require.NoError(t, err) - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - - // Run code. - env.exec(code.Bytes()) - - require.Equal(t, nativeCallStatusCodeReturned, env.compilerStatus()) - require.Equal(t, uint64(1), env.stackPointer()) - require.Equal(t, uintptr(unsafe.Pointer(&me.functions[i])), uintptr(env.stackTopAsUint64())) - }) - } -} diff --git a/internal/engine/compiler/compiler_stack_test.go b/internal/engine/compiler/compiler_stack_test.go deleted file mode 100644 index 8c8a439493..0000000000 --- a/internal/engine/compiler/compiler_stack_test.go +++ /dev/null @@ -1,785 +0,0 @@ -package compiler - -import ( - "fmt" - "math" - "testing" - - "github.com/tetratelabs/wazero/internal/asm" - "github.com/tetratelabs/wazero/internal/testing/require" - "github.com/tetratelabs/wazero/internal/wasm" - "github.com/tetratelabs/wazero/internal/wazeroir" -) - -func TestCompiler_releaseRegisterToStack(t *testing.T) { - const val = 10000 - tests := []struct { - name string - stackPointer uint64 - isFloat bool - }{ - {name: "int", stackPointer: 10, isFloat: false}, - {name: "float", stackPointer: 10, isFloat: true}, - {name: "int-huge-height", stackPointer: math.MaxInt16 + 1, isFloat: false}, - {name: "float-huge-height", stackPointer: math.MaxInt16 + 1, isFloat: true}, - } - - for _, tt := range tests { - tc := tt - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - - // Compile code. - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, nil) - err := compiler.compilePreamble() - require.NoError(t, err) - - // Set up the location stack so that we push the const on the specified height. - s := &runtimeValueLocationStack{ - sp: tc.stackPointer, - stack: make([]runtimeValueLocation, tc.stackPointer), - unreservedVectorRegisters: unreservedVectorRegisters, - unreservedGeneralPurposeRegisters: unreservedGeneralPurposeRegisters, - } - // Peek must be non-nil. Otherwise, compileConst* would fail. - compiler.setRuntimeValueLocationStack(s) - - if tc.isFloat { - err = compiler.compileConstF64(operationPtr(wazeroir.NewOperationConstF64(math.Float64frombits(val)))) - } else { - err = compiler.compileConstI64(operationPtr(wazeroir.NewOperationConstI64(val))) - } - require.NoError(t, err) - // Release the register allocated value to the memory stack so that we can see the value after exiting. - compiler.compileReleaseRegisterToStack(compiler.runtimeValueLocationStack().peek()) - compiler.compileExitFromNativeCode(nativeCallStatusCodeReturned) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - - // Run native code after growing the value stack. - env.callEngine().builtinFunctionGrowStack(tc.stackPointer) - env.exec(code.Bytes()) - - // Compiler status must be returned and stack pointer must end up the specified one. - require.Equal(t, nativeCallStatusCodeReturned, env.compilerStatus()) - require.Equal(t, tc.stackPointer+1, env.ce.stackPointer) - - if tc.isFloat { - require.Equal(t, math.Float64frombits(val), env.stackTopAsFloat64()) - } else { - require.Equal(t, uint64(val), env.stackTopAsUint64()) - } - }) - } -} - -func TestCompiler_compileLoadValueOnStackToRegister(t *testing.T) { - const val = 123 - tests := []struct { - name string - stackPointer uint64 - isFloat bool - }{ - {name: "int", stackPointer: 10, isFloat: false}, - {name: "float", stackPointer: 10, isFloat: true}, - {name: "int-huge-height", stackPointer: math.MaxInt16 + 1, isFloat: false}, - {name: "float-huge-height", stackPointer: math.MaxInt16 + 1, isFloat: true}, - } - - for _, tt := range tests { - tc := tt - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - - // Compile code. - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, nil) - err := compiler.compilePreamble() - require.NoError(t, err) - - // Setup the location stack so that we push the const on the specified height. - compiler.runtimeValueLocationStack().sp = tc.stackPointer - compiler.runtimeValueLocationStack().stack = make([]runtimeValueLocation, tc.stackPointer) - - require.Zero(t, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - loc := compiler.runtimeValueLocationStack().pushRuntimeValueLocationOnStack() - if tc.isFloat { - loc.valueType = runtimeValueTypeF64 - } else { - loc.valueType = runtimeValueTypeI64 - } - // At this point the value must be recorded as being on stack. - require.True(t, loc.onStack()) - - // Release the stack-allocated value to register. - err = compiler.compileEnsureOnRegister(loc) - require.NoError(t, err) - require.Equal(t, 1, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - require.True(t, loc.onRegister()) - - // To verify the behavior, increment the value on the register. - if tc.isFloat { - err = compiler.compileConstF64(operationPtr(wazeroir.NewOperationConstF64(1))) - require.NoError(t, err) - err = compiler.compileAdd(operationPtr(wazeroir.NewOperationAdd(wazeroir.UnsignedTypeF64))) - require.NoError(t, err) - } else { - err = compiler.compileConstI64(operationPtr(wazeroir.NewOperationConstI64(1))) - require.NoError(t, err) - err = compiler.compileAdd(operationPtr(wazeroir.NewOperationAdd(wazeroir.UnsignedTypeI64))) - require.NoError(t, err) - } - - // Release the value to the memory stack so that we can see the value after exiting. - compiler.compileReleaseRegisterToStack(loc) - require.NoError(t, err) - compiler.compileExitFromNativeCode(nativeCallStatusCodeReturned) - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - - // Run native code after growing the value stack, and place the original value. - env.callEngine().builtinFunctionGrowStack(tc.stackPointer) - env.stack()[tc.stackPointer] = val - env.exec(code.Bytes()) - - // Compiler status must be returned and stack pointer must end up the specified one. - require.Equal(t, nativeCallStatusCodeReturned, env.compilerStatus()) - require.Equal(t, tc.stackPointer+1, env.ce.stackPointer) - - if tc.isFloat { - require.Equal(t, math.Float64frombits(val)+1, env.stackTopAsFloat64()) - } else { - require.Equal(t, uint64(val)+1, env.stackTopAsUint64()) - } - }) - } -} - -func TestCompiler_compilePick_v128(t *testing.T) { - const pickTargetLo, pickTargetHi uint64 = 12345, 6789 - - op := operationPtr(wazeroir.NewOperationPick(2, true)) - tests := []struct { - name string - isPickTargetOnRegister bool - }{ - {name: "target on register", isPickTargetOnRegister: false}, - {name: "target on stack", isPickTargetOnRegister: true}, - } - - for _, tt := range tests { - tc := tt - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, nil) - err := compiler.compilePreamble() - require.NoError(t, err) - - // Set up the stack before picking. - if tc.isPickTargetOnRegister { - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(pickTargetLo, pickTargetHi))) - require.NoError(t, err) - } else { - lo := compiler.runtimeValueLocationStack().pushRuntimeValueLocationOnStack() // lo - lo.valueType = runtimeValueTypeV128Lo - env.stack()[lo.stackPointer] = pickTargetLo - hi := compiler.runtimeValueLocationStack().pushRuntimeValueLocationOnStack() // hi - hi.valueType = runtimeValueTypeV128Hi - env.stack()[hi.stackPointer] = pickTargetHi - } - - // Push the unused median value. - _ = compiler.runtimeValueLocationStack().pushRuntimeValueLocationOnStack() - requireRuntimeLocationStackPointerEqual(t, uint64(3), compiler) - - // Now ready to compile Pick operation. - err = compiler.compilePick(op) - require.NoError(t, err) - requireRuntimeLocationStackPointerEqual(t, uint64(5), compiler) - - hiLoc := compiler.runtimeValueLocationStack().peek() - loLoc := compiler.runtimeValueLocationStack().stack[hiLoc.stackPointer-1] - require.True(t, hiLoc.onRegister()) - require.Equal(t, runtimeValueTypeV128Hi, hiLoc.valueType) - require.Equal(t, runtimeValueTypeV128Lo, loLoc.valueType) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Compile and execute the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - // Check the returned status and stack pointer. - require.Equal(t, nativeCallStatusCodeReturned, env.compilerStatus()) - require.Equal(t, uint64(5), env.stackPointer()) - - // Verify the top value is the picked one and the pick target's value stays the same. - lo, hi := env.stackTopAsV128() - require.Equal(t, pickTargetLo, lo) - require.Equal(t, pickTargetHi, hi) - require.Equal(t, pickTargetLo, env.stack()[loLoc.stackPointer]) - require.Equal(t, pickTargetHi, env.stack()[hiLoc.stackPointer]) - }) - } -} - -func TestCompiler_compilePick(t *testing.T) { - const pickTargetValue uint64 = 12345 - op := operationPtr(wazeroir.NewOperationPick(1, false)) - tests := []struct { - name string - pickTargetSetupFunc func(compiler compilerImpl, ce *callEngine) error - isPickTargetFloat, isPickTargetOnRegister bool - }{ - { - name: "float on register", - pickTargetSetupFunc: func(compiler compilerImpl, _ *callEngine) error { - return compiler.compileConstF64(operationPtr(wazeroir.NewOperationConstF64(math.Float64frombits(pickTargetValue)))) - }, - isPickTargetFloat: true, - isPickTargetOnRegister: true, - }, - { - name: "int on register", - pickTargetSetupFunc: func(compiler compilerImpl, _ *callEngine) error { - return compiler.compileConstI64(operationPtr(wazeroir.NewOperationConstI64(pickTargetValue))) - }, - isPickTargetFloat: false, - isPickTargetOnRegister: true, - }, - { - name: "float on stack", - pickTargetSetupFunc: func(compiler compilerImpl, ce *callEngine) error { - pickTargetLocation := compiler.runtimeValueLocationStack().pushRuntimeValueLocationOnStack() - pickTargetLocation.valueType = runtimeValueTypeF64 - ce.stack[pickTargetLocation.stackPointer] = pickTargetValue - return nil - }, - isPickTargetFloat: true, - isPickTargetOnRegister: false, - }, - { - name: "int on stack", - pickTargetSetupFunc: func(compiler compilerImpl, ce *callEngine) error { - pickTargetLocation := compiler.runtimeValueLocationStack().pushRuntimeValueLocationOnStack() - pickTargetLocation.valueType = runtimeValueTypeI64 - ce.stack[pickTargetLocation.stackPointer] = pickTargetValue - return nil - }, - isPickTargetFloat: false, - isPickTargetOnRegister: false, - }, - } - - for _, tt := range tests { - tc := tt - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, nil) - err := compiler.compilePreamble() - require.NoError(t, err) - - // Set up the stack before picking. - err = tc.pickTargetSetupFunc(compiler, env.callEngine()) - require.NoError(t, err) - pickTargetLocation := compiler.runtimeValueLocationStack().peek() - - // Push the unused median value. - _ = compiler.runtimeValueLocationStack().pushRuntimeValueLocationOnStack() - requireRuntimeLocationStackPointerEqual(t, uint64(2), compiler) - - // Now ready to compile Pick operation. - err = compiler.compilePick(op) - require.NoError(t, err) - requireRuntimeLocationStackPointerEqual(t, uint64(3), compiler) - - pickedLocation := compiler.runtimeValueLocationStack().peek() - require.True(t, pickedLocation.onRegister()) - require.Equal(t, pickTargetLocation.getRegisterType(), pickedLocation.getRegisterType()) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Compile and execute the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - // Check the returned status and stack pointer. - require.Equal(t, nativeCallStatusCodeReturned, env.compilerStatus()) - require.Equal(t, uint64(3), env.stackPointer()) - - // Verify the top value is the picked one and the pick target's value stays the same. - if tc.isPickTargetFloat { - require.Equal(t, math.Float64frombits(pickTargetValue), env.stackTopAsFloat64()) - require.Equal(t, math.Float64frombits(pickTargetValue), math.Float64frombits(env.stack()[pickTargetLocation.stackPointer])) - } else { - require.Equal(t, pickTargetValue, env.stackTopAsUint64()) - require.Equal(t, pickTargetValue, env.stack()[pickTargetLocation.stackPointer]) - } - }) - } -} - -func TestCompiler_compileDrop(t *testing.T) { - t.Run("range nop", func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, nil) - - err := compiler.compilePreamble() - require.NoError(t, err) - - // Put existing contents on stack. - liveNum := 10 - for i := 0; i < liveNum; i++ { - compiler.runtimeValueLocationStack().pushRuntimeValueLocationOnStack() - } - requireRuntimeLocationStackPointerEqual(t, uint64(liveNum), compiler) - - err = compiler.compileDrop(operationPtr(wazeroir.NewOperationDrop(wazeroir.NopInclusiveRange))) - require.NoError(t, err) - - // After the nil range drop, the stack must remain the same. - requireRuntimeLocationStackPointerEqual(t, uint64(liveNum), compiler) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - - env.exec(code.Bytes()) - require.Equal(t, nativeCallStatusCodeReturned, env.compilerStatus()) - }) - t.Run("start top", func(t *testing.T) { - r := wazeroir.InclusiveRange{Start: 0, End: 2} - dropTargetNum := int(r.End - r.Start + 1) // +1 as the range is inclusive! - liveNum := 5 - - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, nil) - - err := compiler.compilePreamble() - require.NoError(t, err) - - // Put existing contents on stack. - const expectedTopLiveValue = 100 - for i := 0; i < liveNum+dropTargetNum; i++ { - if i == liveNum-1 { - err := compiler.compileConstI64(operationPtr(wazeroir.NewOperationConstI64(expectedTopLiveValue))) - require.NoError(t, err) - } else { - compiler.runtimeValueLocationStack().pushRuntimeValueLocationOnStack() - } - } - requireRuntimeLocationStackPointerEqual(t, uint64(liveNum+dropTargetNum), compiler) - - err = compiler.compileDrop(operationPtr(wazeroir.NewOperationDrop(r))) - require.NoError(t, err) - - // After the drop operation, the stack contains only live contents. - requireRuntimeLocationStackPointerEqual(t, uint64(liveNum), compiler) - // Plus, the top value must stay on a register. - top := compiler.runtimeValueLocationStack().peek() - require.True(t, top.onRegister()) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - - env.exec(code.Bytes()) - require.Equal(t, nativeCallStatusCodeReturned, env.compilerStatus()) - require.Equal(t, uint64(5), env.stackPointer()) - require.Equal(t, uint64(expectedTopLiveValue), env.stackTopAsUint64()) - }) - - t.Run("start from middle", func(t *testing.T) { - r := wazeroir.InclusiveRange{Start: 2, End: 3} - liveAboveDropStartNum := 3 - dropTargetNum := int(r.End - r.Start + 1) // +1 as the range is inclusive! - liveBelowDropEndNum := 5 - total := liveAboveDropStartNum + dropTargetNum + liveBelowDropEndNum - liveTotal := liveAboveDropStartNum + liveBelowDropEndNum - - env := newCompilerEnvironment() - ce := env.callEngine() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, nil) - - err := compiler.compilePreamble() - require.NoError(t, err) - - // We don't need call frame in this test case, so simply pop them out! - for i := 0; i < callFrameDataSizeInUint64; i++ { - compiler.runtimeValueLocationStack().pop() - } - - // Put existing contents except the top on stack - for i := 0; i < total-1; i++ { - loc := compiler.runtimeValueLocationStack().pushRuntimeValueLocationOnStack() - loc.valueType = runtimeValueTypeI32 - ce.stack[loc.stackPointer] = uint64(i) // Put the initial value. - } - - // Place the top value. - const expectedTopLiveValue = 100 - err = compiler.compileConstI64(operationPtr(wazeroir.NewOperationConstI64(expectedTopLiveValue))) - require.NoError(t, err) - - require.Equal(t, uint64(total), compiler.runtimeValueLocationStack().sp) - - err = compiler.compileDrop(operationPtr(wazeroir.NewOperationDrop(r))) - require.NoError(t, err) - - // After the drop operation, the stack contains only live contents. - require.Equal(t, uint64(liveTotal), compiler.runtimeValueLocationStack().sp) - // Plus, the top value must stay on a register. - require.True(t, compiler.runtimeValueLocationStack().peek().onRegister()) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - - env.exec(code.Bytes()) - require.Equal(t, nativeCallStatusCodeReturned, env.compilerStatus()) - require.Equal(t, uint64(liveTotal), env.ce.stackPointer) - - stack := env.stack()[:env.stackPointer()] - for i, val := range stack { - if i <= liveBelowDropEndNum { - require.Equal(t, uint64(i), val) - } else if i == liveTotal-1 { - require.Equal(t, uint64(expectedTopLiveValue), val) - } else { - require.Equal(t, uint64(i+dropTargetNum), val) - } - } - }) -} - -func TestCompiler_compileSelect(t *testing.T) { - // There are mainly 8 cases we have to test: - // - [x1 = reg, x2 = reg] select x1 - // - [x1 = reg, x2 = reg] select x2 - // - [x1 = reg, x2 = stack] select x1 - // - [x1 = reg, x2 = stack] select x2 - // - [x1 = stack, x2 = reg] select x1 - // - [x1 = stack, x2 = reg] select x2 - // - [x1 = stack, x2 = stack] select x1 - // - [x1 = stack, x2 = stack] select x2 - // And for each case, we have to test with - // three conditional value location: stack, gp register, conditional register. - // So in total we have 24 cases. - tests := []struct { - x1OnRegister, x2OnRegister bool - selectX1 bool - condlValueOnStack, condValueOnGPRegister, condValueOnCondRegister bool - }{ - // Conditional value on stack. - {x1OnRegister: true, x2OnRegister: true, selectX1: true, condlValueOnStack: true}, - {x1OnRegister: true, x2OnRegister: true, selectX1: false, condlValueOnStack: true}, - {x1OnRegister: true, x2OnRegister: false, selectX1: true, condlValueOnStack: true}, - {x1OnRegister: true, x2OnRegister: false, selectX1: false, condlValueOnStack: true}, - {x1OnRegister: false, x2OnRegister: true, selectX1: true, condlValueOnStack: true}, - {x1OnRegister: false, x2OnRegister: true, selectX1: false, condlValueOnStack: true}, - {x1OnRegister: false, x2OnRegister: false, selectX1: true, condlValueOnStack: true}, - {x1OnRegister: false, x2OnRegister: false, selectX1: false, condlValueOnStack: true}, - // Conditional value on register. - {x1OnRegister: true, x2OnRegister: true, selectX1: true, condValueOnGPRegister: true}, - {x1OnRegister: true, x2OnRegister: true, selectX1: false, condValueOnGPRegister: true}, - {x1OnRegister: true, x2OnRegister: false, selectX1: true, condValueOnGPRegister: true}, - {x1OnRegister: true, x2OnRegister: false, selectX1: false, condValueOnGPRegister: true}, - {x1OnRegister: false, x2OnRegister: true, selectX1: true, condValueOnGPRegister: true}, - {x1OnRegister: false, x2OnRegister: true, selectX1: false, condValueOnGPRegister: true}, - {x1OnRegister: false, x2OnRegister: false, selectX1: true, condValueOnGPRegister: true}, - {x1OnRegister: false, x2OnRegister: false, selectX1: false, condValueOnGPRegister: true}, - // Conditional value on conditional register. - {x1OnRegister: true, x2OnRegister: true, selectX1: true, condValueOnCondRegister: true}, - {x1OnRegister: true, x2OnRegister: true, selectX1: false, condValueOnCondRegister: true}, - {x1OnRegister: true, x2OnRegister: false, selectX1: true, condValueOnCondRegister: true}, - {x1OnRegister: true, x2OnRegister: false, selectX1: false, condValueOnCondRegister: true}, - {x1OnRegister: false, x2OnRegister: true, selectX1: true, condValueOnCondRegister: true}, - {x1OnRegister: false, x2OnRegister: true, selectX1: false, condValueOnCondRegister: true}, - {x1OnRegister: false, x2OnRegister: false, selectX1: true, condValueOnCondRegister: true}, - {x1OnRegister: false, x2OnRegister: false, selectX1: false, condValueOnCondRegister: true}, - } - - for i, tt := range tests { - tc := tt - t.Run(fmt.Sprintf("%d", i), func(t *testing.T) { - for _, vals := range [][2]uint64{ - {1, 2}, - {0, 1}, - {1, 0}, - {math.Float64bits(-1), math.Float64bits(-1)}, - {math.Float64bits(-1), math.Float64bits(1)}, - {math.Float64bits(1), math.Float64bits(-1)}, - } { - x1Value, x2Value := vals[0], vals[1] - t.Run(fmt.Sprintf("x1=0x%x,x2=0x%x", vals[0], vals[1]), func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, nil) - - // To make the assertion below stable, we preallocate the underlying stack, - // so that the pointer to the entry will be stale. - compiler.runtimeValueLocationStack().stack = make([]runtimeValueLocation, 100) - - err := compiler.compilePreamble() - require.NoError(t, err) - - x1 := compiler.runtimeValueLocationStack().pushRuntimeValueLocationOnStack() - x1.valueType = runtimeValueTypeI64 - env.stack()[x1.stackPointer] = x1Value - if tc.x1OnRegister { - err = compiler.compileEnsureOnRegister(x1) - require.NoError(t, err) - } - - x2 := compiler.runtimeValueLocationStack().pushRuntimeValueLocationOnStack() - x2.valueType = runtimeValueTypeI64 - env.stack()[x2.stackPointer] = x2Value - if tc.x2OnRegister { - err = compiler.compileEnsureOnRegister(x2) - require.NoError(t, err) - } - - var c *runtimeValueLocation - if tc.condlValueOnStack { - c = compiler.runtimeValueLocationStack().pushRuntimeValueLocationOnStack() - c.valueType = runtimeValueTypeI32 - if tc.selectX1 { - env.stack()[c.stackPointer] = 1 - } else { - env.stack()[c.stackPointer] = 0 - } - } else if tc.condValueOnGPRegister { - c = compiler.runtimeValueLocationStack().pushRuntimeValueLocationOnStack() - c.valueType = runtimeValueTypeI32 - if tc.selectX1 { - env.stack()[c.stackPointer] = 1 - } else { - env.stack()[c.stackPointer] = 0 - } - err = compiler.compileEnsureOnRegister(c) - require.NoError(t, err) - } else if tc.condValueOnCondRegister { - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(0))) - require.NoError(t, err) - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(0))) - require.NoError(t, err) - if tc.selectX1 { - err = compiler.compileEq(operationPtr(wazeroir.NewOperationEq(wazeroir.UnsignedTypeI32))) - } else { - err = compiler.compileNe(operationPtr(wazeroir.NewOperationNe(wazeroir.UnsignedTypeI32))) - } - require.NoError(t, err) - } - - // Now emit code for select. - err = compiler.compileSelect(operationPtr(wazeroir.NewOperationSelect(false))) - require.NoError(t, err) - - // x1 should be top of the stack. - require.Equal(t, x1, compiler.runtimeValueLocationStack().peek()) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Run code. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - // Check the selected value. - require.Equal(t, uint64(1), env.stackPointer()) - if tc.selectX1 { - require.Equal(t, env.stack()[x1.stackPointer], x1Value) - } else { - require.Equal(t, env.stack()[x1.stackPointer], x2Value) - } - }) - } - }) - } -} - -func TestCompiler_compileSwap_v128(t *testing.T) { - const x1Lo, x1Hi uint64 = 100000, 200000 - const x2Lo, x2Hi uint64 = 1, 2 - - tests := []struct { - x1OnRegister, x2OnRegister bool - }{ - {x1OnRegister: true, x2OnRegister: true}, - {x1OnRegister: true, x2OnRegister: false}, - {x1OnRegister: false, x2OnRegister: true}, - {x1OnRegister: false, x2OnRegister: false}, - } - - for _, tt := range tests { - tc := tt - t.Run(fmt.Sprintf("x1_register=%v, x2_register=%v", tc.x1OnRegister, tc.x2OnRegister), func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, nil) - err := compiler.compilePreamble() - require.NoError(t, err) - - if tc.x1OnRegister { - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(x1Lo, x1Hi))) - require.NoError(t, err) - } else { - lo := compiler.runtimeValueLocationStack().pushRuntimeValueLocationOnStack() // lo - lo.valueType = runtimeValueTypeV128Lo - env.stack()[lo.stackPointer] = x1Lo - hi := compiler.runtimeValueLocationStack().pushRuntimeValueLocationOnStack() // hi - hi.valueType = runtimeValueTypeV128Hi - env.stack()[hi.stackPointer] = x1Hi - } - - _ = compiler.runtimeValueLocationStack().pushRuntimeValueLocationOnStack() // Dummy value! - - if tc.x2OnRegister { - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(x2Lo, x2Hi))) - require.NoError(t, err) - } else { - lo := compiler.runtimeValueLocationStack().pushRuntimeValueLocationOnStack() // lo - lo.valueType = runtimeValueTypeV128Lo - env.stack()[lo.stackPointer] = x2Lo - hi := compiler.runtimeValueLocationStack().pushRuntimeValueLocationOnStack() // hi - hi.valueType = runtimeValueTypeV128Hi - env.stack()[hi.stackPointer] = x2Hi - } - - // Swap x1 and x2. - err = compiler.compileSet(operationPtr(wazeroir.NewOperationSet(4, true))) - require.NoError(t, err) - - require.NoError(t, compiler.compileReturnFunction()) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - - // Run code. - env.exec(code.Bytes()) - - require.Equal(t, nativeCallStatusCodeReturned, env.compilerStatus()) - require.Equal(t, uint64(3), env.stackPointer()) - - // The first variable is above the call frame. - st := env.stack() - require.Equal(t, x2Lo, st[callFrameDataSizeInUint64]) - require.Equal(t, x2Hi, st[callFrameDataSizeInUint64+1]) - }) - } -} - -func TestCompiler_compileSet(t *testing.T) { - var x1Value, x2Value int64 = 100, 200 - tests := []struct { - x1OnConditionalRegister, x1OnRegister, x2OnRegister bool - }{ - {x1OnRegister: true, x2OnRegister: true}, - {x1OnRegister: true, x2OnRegister: false}, - {x1OnRegister: false, x2OnRegister: true}, - {x1OnRegister: false, x2OnRegister: false}, - // x1 on conditional register - {x1OnConditionalRegister: true, x2OnRegister: false}, - {x1OnConditionalRegister: true, x2OnRegister: true}, - } - - for i, tt := range tests { - tc := tt - t.Run(fmt.Sprintf("%d", i), func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, nil) - err := compiler.compilePreamble() - require.NoError(t, err) - - x2 := compiler.runtimeValueLocationStack().pushRuntimeValueLocationOnStack() - x2.valueType = runtimeValueTypeI32 - env.stack()[x2.stackPointer] = uint64(x2Value) - if tc.x2OnRegister { - err = compiler.compileEnsureOnRegister(x2) - require.NoError(t, err) - } - - _ = compiler.runtimeValueLocationStack().pushRuntimeValueLocationOnStack() // Dummy value! - if tc.x1OnRegister && !tc.x1OnConditionalRegister { - x1 := compiler.runtimeValueLocationStack().pushRuntimeValueLocationOnStack() - x1.valueType = runtimeValueTypeI32 - env.stack()[x1.stackPointer] = uint64(x1Value) - err = compiler.compileEnsureOnRegister(x1) - require.NoError(t, err) - } else if !tc.x1OnConditionalRegister { - x1 := compiler.runtimeValueLocationStack().pushRuntimeValueLocationOnStack() - x1.valueType = runtimeValueTypeI32 - env.stack()[x1.stackPointer] = uint64(x1Value) - } else { - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(0))) - require.NoError(t, err) - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(0))) - require.NoError(t, err) - err = compiler.compileEq(operationPtr(wazeroir.NewOperationEq(wazeroir.UnsignedTypeI32))) - require.NoError(t, err) - x1Value = 1 - } - - // Set x2 into the x1. - err = compiler.compileSet(operationPtr(wazeroir.NewOperationSet(2, false))) - require.NoError(t, err) - - require.NoError(t, compiler.compileReturnFunction()) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - - // Run code. - env.exec(code.Bytes()) - - require.Equal(t, uint64(2), env.stackPointer()) - // Check the value was set. Note that it is placed above the call frame. - require.Equal(t, uint64(x1Value), env.stack()[callFrameDataSizeInUint64]) - }) - } -} diff --git a/internal/engine/compiler/compiler_test.go b/internal/engine/compiler/compiler_test.go deleted file mode 100644 index 285300d7ec..0000000000 --- a/internal/engine/compiler/compiler_test.go +++ /dev/null @@ -1,315 +0,0 @@ -package compiler - -import ( - "fmt" - "math" - "os" - "runtime" - "testing" - "unsafe" - - "github.com/tetratelabs/wazero/internal/platform" - "github.com/tetratelabs/wazero/internal/testing/require" - "github.com/tetratelabs/wazero/internal/wasm" - "github.com/tetratelabs/wazero/internal/wazeroir" -) - -func TestMain(m *testing.M) { - if !platform.CompilerSupported() { - os.Exit(0) - } - os.Exit(m.Run()) -} - -// Ensures that the offset consts do not drift when we manipulate the target -// structs. -// -// Note: This is a package initializer as many tests could fail if these -// constants are misaligned, hiding the root cause. -func init() { - var me moduleEngine - requireEqual := func(expected, actual int, name string) { - if expected != actual { - panic(fmt.Sprintf("%s: expected %d, but was %d", name, expected, actual)) - } - } - requireEqual(int(unsafe.Offsetof(me.functions)), moduleEngineFunctionsOffset, "moduleEngineFunctionsOffset") - - var ce callEngine - // Offsets for callEngine.moduleContext. - requireEqual(int(unsafe.Offsetof(ce.fn)), callEngineModuleContextFnOffset, "callEngineModuleContextFnOffset") - requireEqual(int(unsafe.Offsetof(ce.moduleInstance)), callEngineModuleContextModuleInstanceOffset, "callEngineModuleContextModuleInstanceOffset") - requireEqual(int(unsafe.Offsetof(ce.globalElement0Address)), callEngineModuleContextGlobalElement0AddressOffset, "callEngineModuleContextGlobalElement0AddressOffset") - requireEqual(int(unsafe.Offsetof(ce.memoryElement0Address)), callEngineModuleContextMemoryElement0AddressOffset, "callEngineModuleContextMemoryElement0AddressOffset") - requireEqual(int(unsafe.Offsetof(ce.memorySliceLen)), callEngineModuleContextMemorySliceLenOffset, "callEngineModuleContextMemorySliceLenOffset") - requireEqual(int(unsafe.Offsetof(ce.memoryInstance)), callEngineModuleContextMemoryInstanceOffset, "callEngineModuleContextMemoryInstanceOffset") - requireEqual(int(unsafe.Offsetof(ce.tablesElement0Address)), callEngineModuleContextTablesElement0AddressOffset, "callEngineModuleContextTablesElement0AddressOffset") - requireEqual(int(unsafe.Offsetof(ce.functionsElement0Address)), callEngineModuleContextFunctionsElement0AddressOffset, "callEngineModuleContextFunctionsElement0AddressOffset") - requireEqual(int(unsafe.Offsetof(ce.typeIDsElement0Address)), callEngineModuleContextTypeIDsElement0AddressOffset, "callEngineModuleContextTypeIDsElement0AddressOffset") - requireEqual(int(unsafe.Offsetof(ce.dataInstancesElement0Address)), callEngineModuleContextDataInstancesElement0AddressOffset, "callEngineModuleContextDataInstancesElement0AddressOffset") - requireEqual(int(unsafe.Offsetof(ce.elementInstancesElement0Address)), callEngineModuleContextElementInstancesElement0AddressOffset, "callEngineModuleContextElementInstancesElement0AddressOffset") - - // Offsets for callEngine.stackContext - requireEqual(int(unsafe.Offsetof(ce.stackPointer)), callEngineStackContextStackPointerOffset, "callEngineStackContextStackPointerOffset") - requireEqual(int(unsafe.Offsetof(ce.stackBasePointerInBytes)), callEngineStackContextStackBasePointerInBytesOffset, "callEngineStackContextStackBasePointerInBytesOffset") - requireEqual(int(unsafe.Offsetof(ce.stackElement0Address)), callEngineStackContextStackElement0AddressOffset, "callEngineStackContextStackElement0AddressOffset") - requireEqual(int(unsafe.Offsetof(ce.stackLenInBytes)), callEngineStackContextStackLenInBytesOffset, "callEngineStackContextStackLenInBytesOffset") - - // Offsets for callEngine.exitContext. - requireEqual(int(unsafe.Offsetof(ce.statusCode)), callEngineExitContextNativeCallStatusCodeOffset, "callEngineExitContextNativeCallStatusCodeOffset") - requireEqual(int(unsafe.Offsetof(ce.builtinFunctionCallIndex)), callEngineExitContextBuiltinFunctionCallIndexOffset, "callEngineExitContextBuiltinFunctionCallIndexOffset") - requireEqual(int(unsafe.Offsetof(ce.returnAddress)), callEngineExitContextReturnAddressOffset, "callEngineExitContextReturnAddressOffset") - requireEqual(int(unsafe.Offsetof(ce.callerModuleInstance)), callEngineExitContextCallerModuleInstanceOffset, "callEngineExitContextCallerModuleInstanceOffset") - - // Size and offsets for callFrame. - var frame callFrame - requireEqual(int(unsafe.Sizeof(frame))/8, callFrameDataSizeInUint64, "callFrameDataSize") - - // Offsets for code. - var f function - requireEqual(int(unsafe.Offsetof(f.codeInitialAddress)), functionCodeInitialAddressOffset, "functionCodeInitialAddressOffset") - requireEqual(int(unsafe.Offsetof(f.moduleInstance)), functionModuleInstanceOffset, "functionModuleInstanceOffset") - requireEqual(int(unsafe.Offsetof(f.typeID)), functionTypeIDOffset, "functionTypeIDOffset") - requireEqual(int(unsafe.Sizeof(f)), functionSize, "functionModuleInstanceOffset") - - // Offsets for wasm.ModuleInstance. - var moduleInstance wasm.ModuleInstance - requireEqual(int(unsafe.Offsetof(moduleInstance.Globals)), moduleInstanceGlobalsOffset, "moduleInstanceGlobalsOffset") - requireEqual(int(unsafe.Offsetof(moduleInstance.MemoryInstance)), moduleInstanceMemoryOffset, "moduleInstanceMemoryOffset") - requireEqual(int(unsafe.Offsetof(moduleInstance.Tables)), moduleInstanceTablesOffset, "moduleInstanceTablesOffset") - requireEqual(int(unsafe.Offsetof(moduleInstance.Engine)), moduleInstanceEngineOffset, "moduleInstanceEngineOffset") - requireEqual(int(unsafe.Offsetof(moduleInstance.TypeIDs)), moduleInstanceTypeIDsOffset, "moduleInstanceTypeIDsOffset") - requireEqual(int(unsafe.Offsetof(moduleInstance.DataInstances)), moduleInstanceDataInstancesOffset, "moduleInstanceDataInstancesOffset") - requireEqual(int(unsafe.Offsetof(moduleInstance.ElementInstances)), moduleInstanceElementInstancesOffset, "moduleInstanceElementInstancesOffset") - - // Offsets for wasm.Table. - var tableInstance wasm.TableInstance - requireEqual(int(unsafe.Offsetof(tableInstance.References)), tableInstanceTableOffset, "tableInstanceTableOffset") - // We add "+8" to get the length of Tables[0].Table - // since the slice header is laid out as {Data uintptr, Len int64, Cap int64} on memory. - requireEqual(int(unsafe.Offsetof(tableInstance.References)+8), tableInstanceTableLenOffset, "tableInstanceTableLenOffset") - - // Offsets for wasm.Memory - var memoryInstance wasm.MemoryInstance - requireEqual(int(unsafe.Offsetof(memoryInstance.Buffer)), memoryInstanceBufferOffset, "memoryInstanceBufferOffset") - // "+8" because the slice header is laid out as {Data uintptr, Len int64, Cap int64} on memory. - requireEqual(int(unsafe.Offsetof(memoryInstance.Buffer)+8), memoryInstanceBufferLenOffset, "memoryInstanceBufferLenOffset") - - // Offsets for wasm.GlobalInstance - var globalInstance wasm.GlobalInstance - requireEqual(int(unsafe.Offsetof(globalInstance.Val)), globalInstanceValueOffset, "globalInstanceValueOffset") - - var dataInstance wasm.DataInstance - requireEqual(int(unsafe.Sizeof(dataInstance)), dataInstanceStructSize, "dataInstanceStructSize") - - var elementInstance wasm.ElementInstance - requireEqual(int(unsafe.Sizeof(elementInstance)), elementInstanceStructSize, "elementInstanceStructSize") - - var pointer uintptr - requireEqual(int(unsafe.Sizeof(pointer)), 1<> 3 -} - -func (j *compilerEnv) setStackPointer(sp uint64) { - j.ce.stackContext.stackPointer = sp -} - -func (j *compilerEnv) addGlobals(g ...*wasm.GlobalInstance) { - j.moduleInstance.Globals = append(j.moduleInstance.Globals, g...) -} - -func (j *compilerEnv) globals() []*wasm.GlobalInstance { - return j.moduleInstance.Globals -} - -func (j *compilerEnv) addTable(table *wasm.TableInstance) { - j.moduleInstance.Tables = append(j.moduleInstance.Tables, table) -} - -func (j *compilerEnv) setStackBasePointer(sp uint64) { - j.ce.stackContext.stackBasePointerInBytes = sp << 3 -} - -func (j *compilerEnv) module() *wasm.ModuleInstance { - return j.moduleInstance -} - -func (j *compilerEnv) moduleEngine() *moduleEngine { - return j.me -} - -func (j *compilerEnv) callEngine() *callEngine { - return j.ce -} - -func (j *compilerEnv) exec(machineCode []byte) { - cm := &compiledModule{compiledCode: &compiledCode{}} - if err := cm.executable.Map(len(machineCode)); err != nil { - panic(err) - } - executable := cm.executable.Bytes() - copy(executable, machineCode) - makeExecutable(executable) - - f := &function{ - parent: &compiledFunction{parent: cm.compiledCode}, - codeInitialAddress: uintptr(unsafe.Pointer(&executable[0])), - moduleInstance: j.moduleInstance, - } - j.ce.initialFn = f - j.ce.fn = f - - nativecall( - uintptr(unsafe.Pointer(&executable[0])), - j.ce, j.moduleInstance, - ) -} - -func (j *compilerEnv) requireNewCompiler(t *testing.T, functionType *wasm.FunctionType, fn func() compiler, ir *wazeroir.CompilationResult) compilerImpl { - requireSupportedOSArch(t) - - if ir == nil { - ir = &wazeroir.CompilationResult{ - LabelCallers: map[wazeroir.Label]uint32{}, - } - } - - c := fn() - c.Init(functionType, ir, false) - - ret, ok := c.(compilerImpl) - require.True(t, ok) - return ret -} - -// compilerImpl is the interface used for architecture-independent unit tests in this pkg. -// This is currently implemented by amd64 and arm64. -type compilerImpl interface { - compiler - compileExitFromNativeCode(nativeCallStatusCode) - compileMaybeGrowStack() error - compileReturnFunction() error - assignStackPointerCeil(uint64) - setStackPointerCeil(uint64) - compileReleaseRegisterToStack(loc *runtimeValueLocation) - setRuntimeValueLocationStack(*runtimeValueLocationStack) - compileEnsureOnRegister(loc *runtimeValueLocation) error - compileModuleContextInitialization() error -} - -const defaultMemoryPageNumInTest = 1 - -func newCompilerEnvironment() *compilerEnv { - me := &moduleEngine{} - return &compilerEnv{ - me: me, - moduleInstance: &wasm.ModuleInstance{ - MemoryInstance: &wasm.MemoryInstance{Buffer: make([]byte, wasm.MemoryPageSize*defaultMemoryPageNumInTest)}, - Tables: []*wasm.TableInstance{}, - Globals: []*wasm.GlobalInstance{}, - Engine: me, - }, - ce: me.newCallEngine(initialStackSize, &function{parent: &compiledFunction{parent: &compiledCode{}}}), - } -} - -// requireRuntimeLocationStackPointerEqual ensures that the compiler's runtimeValueLocationStack has -// the expected stack pointer value relative to the call frame. -func requireRuntimeLocationStackPointerEqual(t *testing.T, expSP uint64, c compiler) { - require.Equal(t, expSP, c.runtimeValueLocationStack().sp-callFrameDataSizeInUint64) -} - -// TestCompileI32WrapFromI64 is the regression test for https://github.com/tetratelabs/wazero/issues/1008 -func TestCompileI32WrapFromI64(t *testing.T) { - c := newCompiler() - c.Init(&wasm.FunctionType{}, nil, false) - - // Push the original i64 value. - loc := c.runtimeValueLocationStack().pushRuntimeValueLocationOnStack() - loc.valueType = runtimeValueTypeI64 - // Wrap it as the i32, and this should result in having runtimeValueTypeI32 on top of the stack. - err := c.compileI32WrapFromI64() - require.NoError(t, err) - require.Equal(t, runtimeValueTypeI32, loc.valueType) -} - -func operationPtr(operation wazeroir.UnionOperation) *wazeroir.UnionOperation { - return &operation -} - -func requireExecutable(original []byte) (executable []byte) { - executable, err := platform.MmapCodeSegment(len(original)) - if err != nil { - panic(err) - } - copy(executable, original) - makeExecutable(executable) - return executable -} - -func makeExecutable(executable []byte) { - if runtime.GOARCH == "arm64" { - if err := platform.MprotectRX(executable); err != nil { - panic(err) - } - } -} diff --git a/internal/engine/compiler/compiler_value_location.go b/internal/engine/compiler/compiler_value_location.go deleted file mode 100644 index 30036fed1b..0000000000 --- a/internal/engine/compiler/compiler_value_location.go +++ /dev/null @@ -1,425 +0,0 @@ -package compiler - -import ( - "fmt" - "strings" - - "github.com/tetratelabs/wazero/internal/asm" - "github.com/tetratelabs/wazero/internal/wasm" -) - -var ( - // unreservedGeneralPurposeRegisters contains unreserved general purpose registers of integer type. - unreservedGeneralPurposeRegisters []asm.Register - - // unreservedVectorRegisters contains unreserved vector registers. - unreservedVectorRegisters []asm.Register -) - -func isGeneralPurposeRegister(r asm.Register) bool { - return unreservedGeneralPurposeRegisters[0] <= r && r <= unreservedGeneralPurposeRegisters[len(unreservedGeneralPurposeRegisters)-1] -} - -func isVectorRegister(r asm.Register) bool { - return unreservedVectorRegisters[0] <= r && r <= unreservedVectorRegisters[len(unreservedVectorRegisters)-1] -} - -// runtimeValueLocation corresponds to each variable pushed onto the wazeroir (virtual) stack, -// and it has the information about where it exists in the physical machine. -// It might exist in registers, or maybe on in the non-virtual physical stack allocated in memory. -type runtimeValueLocation struct { - valueType runtimeValueType - // register is set to asm.NilRegister if the value is stored in the memory stack. - register asm.Register - // conditionalRegister is set to conditionalRegisterStateUnset if the value is not on the conditional register. - conditionalRegister asm.ConditionalRegisterState - // stackPointer is the location of this value in the memory stack at runtime, - stackPointer uint64 -} - -func (v *runtimeValueLocation) getRegisterType() (ret registerType) { - switch v.valueType { - case runtimeValueTypeI32, runtimeValueTypeI64: - ret = registerTypeGeneralPurpose - case runtimeValueTypeF32, runtimeValueTypeF64, - runtimeValueTypeV128Lo, runtimeValueTypeV128Hi: - ret = registerTypeVector - default: - panic("BUG") - } - return -} - -type runtimeValueType byte - -const ( - runtimeValueTypeNone runtimeValueType = iota - runtimeValueTypeI32 - runtimeValueTypeI64 - runtimeValueTypeF32 - runtimeValueTypeF64 - runtimeValueTypeV128Lo - runtimeValueTypeV128Hi -) - -func (r runtimeValueType) String() (ret string) { - switch r { - case runtimeValueTypeI32: - ret = "i32" - case runtimeValueTypeI64: - ret = "i64" - case runtimeValueTypeF32: - ret = "f32" - case runtimeValueTypeF64: - ret = "f64" - case runtimeValueTypeV128Lo: - ret = "v128.lo" - case runtimeValueTypeV128Hi: - ret = "v128.hi" - } - return -} - -func (v *runtimeValueLocation) setRegister(reg asm.Register) { - v.register = reg - v.conditionalRegister = asm.ConditionalRegisterStateUnset -} - -func (v *runtimeValueLocation) onRegister() bool { - return v.register != asm.NilRegister && v.conditionalRegister == asm.ConditionalRegisterStateUnset -} - -func (v *runtimeValueLocation) onStack() bool { - return v.register == asm.NilRegister && v.conditionalRegister == asm.ConditionalRegisterStateUnset -} - -func (v *runtimeValueLocation) onConditionalRegister() bool { - return v.conditionalRegister != asm.ConditionalRegisterStateUnset -} - -func (v *runtimeValueLocation) String() string { - var location string - if v.onStack() { - location = fmt.Sprintf("stack(%d)", v.stackPointer) - } else if v.onConditionalRegister() { - location = fmt.Sprintf("conditional(%d)", v.conditionalRegister) - } else if v.onRegister() { - location = fmt.Sprintf("register(%s)", registerNameFn(v.register)) - } - return fmt.Sprintf("{type=%s,location=%s}", v.valueType, location) -} - -func newRuntimeValueLocationStack() runtimeValueLocationStack { - return runtimeValueLocationStack{ - unreservedVectorRegisters: unreservedVectorRegisters, - unreservedGeneralPurposeRegisters: unreservedGeneralPurposeRegisters, - } -} - -// runtimeValueLocationStack represents the wazeroir virtual stack -// where each item holds the location information about where it exists -// on the physical machine at runtime. -// -// Notably this is only used in the compilation phase, not runtime, -// and we change the state of this struct at every wazeroir operation we compile. -// In this way, we can see where the operands of an operation (for example, -// two variables for wazeroir add operation.) exist and check the necessity for -// moving the variable to registers to perform actual CPU instruction -// to achieve wazeroir's add operation. -type runtimeValueLocationStack struct { - // stack holds all the variables. - stack []runtimeValueLocation - // sp is the current stack pointer. - sp uint64 - // usedRegisters is the bit map to track the used registers. - usedRegisters usedRegistersMask - // stackPointerCeil tracks max(.sp) across the lifespan of this struct. - stackPointerCeil uint64 - // unreservedGeneralPurposeRegisters and unreservedVectorRegisters hold - // architecture dependent unreserved register list. - unreservedGeneralPurposeRegisters, unreservedVectorRegisters []asm.Register -} - -func (v *runtimeValueLocationStack) reset() { - stack := v.stack[:0] - *v = runtimeValueLocationStack{ - unreservedVectorRegisters: unreservedVectorRegisters, - unreservedGeneralPurposeRegisters: unreservedGeneralPurposeRegisters, - stack: stack, - } -} - -func (v *runtimeValueLocationStack) String() string { - var stackStr []string - for i := uint64(0); i < v.sp; i++ { - stackStr = append(stackStr, v.stack[i].String()) - } - usedRegisters := v.usedRegisters.list() - return fmt.Sprintf("sp=%d, stack=[%s], used_registers=[%s]", v.sp, strings.Join(stackStr, ","), strings.Join(usedRegisters, ",")) -} - -// cloneFrom clones the values on `from` into self except for the slice of .stack field. -// The content on .stack will be copied from the origin to self, and grow the underlying slice -// if necessary. -func (v *runtimeValueLocationStack) cloneFrom(from runtimeValueLocationStack) { - // Assigns the same values for fields except for the stack which we want to reuse. - prev := v.stack - *v = from - v.stack = prev[:cap(prev)] // Expand the length to the capacity so that we can minimize "diff" below. - // Copy the content in the stack. - if diff := int(from.sp) - len(v.stack); diff > 0 { - v.stack = append(v.stack, make([]runtimeValueLocation, diff)...) - } - copy(v.stack, from.stack[:from.sp]) -} - -// pushRuntimeValueLocationOnRegister creates a new runtimeValueLocation with a given register and pushes onto -// the location stack. -func (v *runtimeValueLocationStack) pushRuntimeValueLocationOnRegister(reg asm.Register, vt runtimeValueType) (loc *runtimeValueLocation) { - loc = v.push(reg, asm.ConditionalRegisterStateUnset) - loc.valueType = vt - return -} - -// pushRuntimeValueLocationOnRegister creates a new runtimeValueLocation and pushes onto the location stack. -func (v *runtimeValueLocationStack) pushRuntimeValueLocationOnStack() (loc *runtimeValueLocation) { - loc = v.push(asm.NilRegister, asm.ConditionalRegisterStateUnset) - loc.valueType = runtimeValueTypeNone - return -} - -// pushRuntimeValueLocationOnRegister creates a new runtimeValueLocation with a given conditional register state -// and pushes onto the location stack. -func (v *runtimeValueLocationStack) pushRuntimeValueLocationOnConditionalRegister(state asm.ConditionalRegisterState) (loc *runtimeValueLocation) { - loc = v.push(asm.NilRegister, state) - loc.valueType = runtimeValueTypeI32 - return -} - -// push a runtimeValueLocation onto the stack. -func (v *runtimeValueLocationStack) push(reg asm.Register, conditionalRegister asm.ConditionalRegisterState) (ret *runtimeValueLocation) { - if v.sp >= uint64(len(v.stack)) { - // This case we need to grow the stack capacity by appending the item, - // rather than indexing. - v.stack = append(v.stack, runtimeValueLocation{}) - } - ret = &v.stack[v.sp] - ret.register, ret.conditionalRegister, ret.stackPointer = reg, conditionalRegister, v.sp - v.sp++ - // stackPointerCeil must be set after sp is incremented since - // we skip the stack grow if len(stack) >= basePointer+stackPointerCeil. - if v.sp > v.stackPointerCeil { - v.stackPointerCeil = v.sp - } - return -} - -func (v *runtimeValueLocationStack) pop() (loc *runtimeValueLocation) { - v.sp-- - loc = &v.stack[v.sp] - return -} - -func (v *runtimeValueLocationStack) popV128() (loc *runtimeValueLocation) { - v.sp -= 2 - loc = &v.stack[v.sp] - return -} - -func (v *runtimeValueLocationStack) peek() (loc *runtimeValueLocation) { - loc = &v.stack[v.sp-1] - return -} - -func (v *runtimeValueLocationStack) releaseRegister(loc *runtimeValueLocation) { - v.markRegisterUnused(loc.register) - loc.register = asm.NilRegister - loc.conditionalRegister = asm.ConditionalRegisterStateUnset -} - -func (v *runtimeValueLocationStack) markRegisterUnused(regs ...asm.Register) { - for _, reg := range regs { - v.usedRegisters.remove(reg) - } -} - -func (v *runtimeValueLocationStack) markRegisterUsed(regs ...asm.Register) { - for _, reg := range regs { - v.usedRegisters.add(reg) - } -} - -type registerType byte - -const ( - registerTypeGeneralPurpose registerType = iota - // registerTypeVector represents a vector register which can be used for either scalar float - // operation or SIMD vector operation depending on the instruction by which the register is used. - // - // Note: In normal assembly language, scalar float and vector register have different notations as - // Vn is for vectors and Qn is for scalar floats on arm64 for example. But on physical hardware, - // they are placed on the same locations. (Qn means the lower 64-bit of Vn vector register on arm64). - // - // In wazero, for the sake of simplicity in the register allocation, we intentionally conflate these two types - // and delegate the decision to the assembler which is aware of the instruction types for which these registers are used. - registerTypeVector -) - -func (tp registerType) String() (ret string) { - switch tp { - case registerTypeGeneralPurpose: - ret = "int" - case registerTypeVector: - ret = "vector" - } - return -} - -// takeFreeRegister searches for unused registers. Any found are marked used and returned. -func (v *runtimeValueLocationStack) takeFreeRegister(tp registerType) (reg asm.Register, found bool) { - var targetRegs []asm.Register - switch tp { - case registerTypeVector: - targetRegs = v.unreservedVectorRegisters - case registerTypeGeneralPurpose: - targetRegs = v.unreservedGeneralPurposeRegisters - } - for _, candidate := range targetRegs { - if v.usedRegisters.exist(candidate) { - continue - } - return candidate, true - } - return 0, false -} - -// Search through the stack, and steal the register from the last used -// variable on the stack. -func (v *runtimeValueLocationStack) takeStealTargetFromUsedRegister(tp registerType) (*runtimeValueLocation, bool) { - for i := uint64(0); i < v.sp; i++ { - loc := &v.stack[i] - if loc.onRegister() { - switch tp { - case registerTypeVector: - if loc.valueType == runtimeValueTypeV128Hi { - panic("BUG: V128Hi must be above the corresponding V128Lo") - } - if isVectorRegister(loc.register) { - return loc, true - } - case registerTypeGeneralPurpose: - if isGeneralPurposeRegister(loc.register) { - return loc, true - } - } - } - } - return nil, false -} - -// init sets up the runtimeValueLocationStack which reflects the state of -// the stack at the beginning of the function. -// -// See the diagram in callEngine.stack. -func (v *runtimeValueLocationStack) init(sig *wasm.FunctionType) { - for _, t := range sig.Params { - loc := v.pushRuntimeValueLocationOnStack() - switch t { - case wasm.ValueTypeI32: - loc.valueType = runtimeValueTypeI32 - case wasm.ValueTypeI64, wasm.ValueTypeFuncref, wasm.ValueTypeExternref: - loc.valueType = runtimeValueTypeI64 - case wasm.ValueTypeF32: - loc.valueType = runtimeValueTypeF32 - case wasm.ValueTypeF64: - loc.valueType = runtimeValueTypeF64 - case wasm.ValueTypeV128: - loc.valueType = runtimeValueTypeV128Lo - hi := v.pushRuntimeValueLocationOnStack() - hi.valueType = runtimeValueTypeV128Hi - default: - panic("BUG") - } - } - - // If the len(results) > len(args), the slots for all results are reserved after - // arguments, so we reflect that into the location stack. - for i := 0; i < sig.ResultNumInUint64-sig.ParamNumInUint64; i++ { - _ = v.pushRuntimeValueLocationOnStack() - } - - // Then push the control frame fields. - for i := 0; i < callFrameDataSizeInUint64; i++ { - loc := v.pushRuntimeValueLocationOnStack() - loc.valueType = runtimeValueTypeI64 - } -} - -// getCallFrameLocations returns each field of callFrame's runtime location. -// -// See the diagram in callEngine.stack. -func (v *runtimeValueLocationStack) getCallFrameLocations(sig *wasm.FunctionType) ( - returnAddress, callerStackBasePointerInBytes, callerFunction *runtimeValueLocation, -) { - offset := callFrameOffset(sig) - return &v.stack[offset], &v.stack[offset+1], &v.stack[offset+2] -} - -// pushCallFrame pushes a call frame's runtime locations onto the stack assuming that -// the function call parameters are already pushed there. -// -// See the diagram in callEngine.stack. -func (v *runtimeValueLocationStack) pushCallFrame(callTargetFunctionType *wasm.FunctionType) ( - returnAddress, callerStackBasePointerInBytes, callerFunction *runtimeValueLocation, -) { - // If len(results) > len(args), we reserve the slots for the results below the call frame. - reservedSlotsBeforeCallFrame := callTargetFunctionType.ResultNumInUint64 - callTargetFunctionType.ParamNumInUint64 - for i := 0; i < reservedSlotsBeforeCallFrame; i++ { - v.pushRuntimeValueLocationOnStack() - } - - // Push the runtime location for each field of callFrame struct. Note that each of them has - // uint64 type, and therefore must be treated as runtimeValueTypeI64. - - // callFrame.returnAddress - returnAddress = v.pushRuntimeValueLocationOnStack() - returnAddress.valueType = runtimeValueTypeI64 - // callFrame.returnStackBasePointerInBytes - callerStackBasePointerInBytes = v.pushRuntimeValueLocationOnStack() - callerStackBasePointerInBytes.valueType = runtimeValueTypeI64 - // callFrame.function - callerFunction = v.pushRuntimeValueLocationOnStack() - callerFunction.valueType = runtimeValueTypeI64 - return -} - -// usedRegistersMask tracks the used registers in its bits. -type usedRegistersMask uint64 - -// add adds the given `r` to the mask. -func (u *usedRegistersMask) add(r asm.Register) { - *u = *u | (1 << registerMaskShift(r)) -} - -// remove drops the given `r` from the mask. -func (u *usedRegistersMask) remove(r asm.Register) { - *u = *u & ^(1 << registerMaskShift(r)) -} - -// exist returns true if the given `r` is used. -func (u *usedRegistersMask) exist(r asm.Register) bool { - shift := registerMaskShift(r) - return (*u & (1 << shift)) > 0 -} - -// list returns the list of debug string of used registers. -// Only used for debugging and testing. -func (u *usedRegistersMask) list() (ret []string) { - mask := *u - for i := 0; i < 64; i++ { - if mask&(1< 0 { - ret = append(ret, registerNameFn(registerFromMaskShift(i))) - } - } - return -} diff --git a/internal/engine/compiler/compiler_value_location_test.go b/internal/engine/compiler/compiler_value_location_test.go deleted file mode 100644 index 647104670e..0000000000 --- a/internal/engine/compiler/compiler_value_location_test.go +++ /dev/null @@ -1,269 +0,0 @@ -package compiler - -import ( - "testing" - - "github.com/tetratelabs/wazero/internal/asm" - "github.com/tetratelabs/wazero/internal/testing/require" - "github.com/tetratelabs/wazero/internal/wasm" -) - -func Test_isIntRegister(t *testing.T) { - for _, r := range unreservedGeneralPurposeRegisters { - require.True(t, isGeneralPurposeRegister(r)) - } -} - -func Test_isVectorRegister(t *testing.T) { - for _, r := range unreservedVectorRegisters { - require.True(t, isVectorRegister(r)) - } -} - -func TestRuntimeValueLocationStack_basic(t *testing.T) { - s := newRuntimeValueLocationStack() - // Push stack value. - loc := s.pushRuntimeValueLocationOnStack() - require.Equal(t, uint64(1), s.sp) - require.Equal(t, uint64(0), loc.stackPointer) - // Push the register value. - tmpReg := unreservedGeneralPurposeRegisters[0] - loc = s.pushRuntimeValueLocationOnRegister(tmpReg, runtimeValueTypeI64) - require.Equal(t, uint64(2), s.sp) - require.Equal(t, uint64(1), loc.stackPointer) - require.Equal(t, tmpReg, loc.register) - require.Equal(t, loc.valueType, runtimeValueTypeI64) - // markRegisterUsed. - tmpReg2 := unreservedGeneralPurposeRegisters[1] - s.markRegisterUsed(tmpReg2) - require.True(t, s.usedRegisters.exist(tmpReg2)) - // releaseRegister. - s.releaseRegister(loc) - require.False(t, s.usedRegisters.exist(loc.register)) - require.Equal(t, asm.NilRegister, loc.register) - // Check the max stack pointer. - for i := 0; i < 1000; i++ { - s.pushRuntimeValueLocationOnStack() - } - for i := 0; i < 1000; i++ { - s.pop() - } - require.Equal(t, uint64(1002), s.stackPointerCeil) -} - -func TestRuntimeValueLocationStack_takeFreeRegister(t *testing.T) { - s := newRuntimeValueLocationStack() - // For int registers. - r, ok := s.takeFreeRegister(registerTypeGeneralPurpose) - require.True(t, ok) - require.True(t, isGeneralPurposeRegister(r)) - // Mark all the int registers used. - for _, r := range unreservedGeneralPurposeRegisters { - s.markRegisterUsed(r) - } - // Now we cannot take free ones for int. - _, ok = s.takeFreeRegister(registerTypeGeneralPurpose) - require.False(t, ok) - // But we still should be able to take float regs. - r, ok = s.takeFreeRegister(registerTypeVector) - require.True(t, ok) - require.True(t, isVectorRegister(r)) - // Mark all the float registers used. - for _, r := range unreservedVectorRegisters { - s.markRegisterUsed(r) - } - // Now we cannot take free ones for floats. - _, ok = s.takeFreeRegister(registerTypeVector) - require.False(t, ok) -} - -func TestRuntimeValueLocationStack_takeStealTargetFromUsedRegister(t *testing.T) { - s := newRuntimeValueLocationStack() - intReg := unreservedGeneralPurposeRegisters[0] - floatReg := unreservedVectorRegisters[0] - intLocation := s.push(intReg, asm.ConditionalRegisterStateUnset) - floatLocation := s.push(floatReg, asm.ConditionalRegisterStateUnset) - // Take for float. - target, ok := s.takeStealTargetFromUsedRegister(registerTypeVector) - require.True(t, ok) - require.Equal(t, floatLocation, target) - // Take for ints. - target, ok = s.takeStealTargetFromUsedRegister(registerTypeGeneralPurpose) - require.True(t, ok) - require.Equal(t, intLocation, target) - // Pop float value. - popped := s.pop() - require.Equal(t, floatLocation, popped) - // Now we cannot find the steal target. - target, ok = s.takeStealTargetFromUsedRegister(registerTypeVector) - require.False(t, ok) - require.Nil(t, target) - // Pop int value. - popped = s.pop() - require.Equal(t, intLocation, popped) - // Now we cannot find the steal target. - target, ok = s.takeStealTargetFromUsedRegister(registerTypeGeneralPurpose) - require.False(t, ok) - require.Nil(t, target) -} - -func TestRuntimeValueLocationStack_setupInitialStack(t *testing.T) { - const f32 = wasm.ValueTypeF32 - tests := []struct { - name string - sig *wasm.FunctionType - expectedSP uint64 - }{ - { - name: "no params / no results", - sig: &wasm.FunctionType{}, - expectedSP: callFrameDataSizeInUint64, - }, - { - name: "no results", - sig: &wasm.FunctionType{ - Params: []wasm.ValueType{f32, f32}, - ParamNumInUint64: 2, - }, - expectedSP: callFrameDataSizeInUint64 + 2, - }, - { - name: "no params", - sig: &wasm.FunctionType{ - Results: []wasm.ValueType{f32, f32}, - ResultNumInUint64: 2, - }, - expectedSP: callFrameDataSizeInUint64 + 2, - }, - { - name: "params == results", - sig: &wasm.FunctionType{ - Params: []wasm.ValueType{f32, f32}, - ParamNumInUint64: 2, - Results: []wasm.ValueType{f32, f32}, - ResultNumInUint64: 2, - }, - expectedSP: callFrameDataSizeInUint64 + 2, - }, - { - name: "params > results", - sig: &wasm.FunctionType{ - Params: []wasm.ValueType{f32, f32, f32}, - ParamNumInUint64: 3, - Results: []wasm.ValueType{f32, f32}, - ResultNumInUint64: 2, - }, - expectedSP: callFrameDataSizeInUint64 + 3, - }, - { - name: "params < results", - sig: &wasm.FunctionType{ - Params: []wasm.ValueType{f32}, - ParamNumInUint64: 1, - Results: []wasm.ValueType{f32, f32, f32}, - ResultNumInUint64: 3, - }, - expectedSP: callFrameDataSizeInUint64 + 3, - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - s := newRuntimeValueLocationStack() - s.init(tc.sig) - require.Equal(t, tc.expectedSP, s.sp) - - callFrameLocations := s.stack[s.sp-callFrameDataSizeInUint64 : s.sp] - for _, loc := range callFrameLocations { - require.Equal(t, runtimeValueTypeI64, loc.valueType) - } - }) - } -} - -func TestRuntimeValueLocation_pushCallFrame(t *testing.T) { - for _, sig := range []*wasm.FunctionType{ - {ParamNumInUint64: 0, ResultNumInUint64: 1}, - {ParamNumInUint64: 1, ResultNumInUint64: 0}, - {ParamNumInUint64: 1, ResultNumInUint64: 1}, - {ParamNumInUint64: 0, ResultNumInUint64: 2}, - {ParamNumInUint64: 2, ResultNumInUint64: 0}, - {ParamNumInUint64: 2, ResultNumInUint64: 3}, - } { - sig := sig - t.Run(sig.String(), func(t *testing.T) { - s := newRuntimeValueLocationStack() - // pushCallFrame assumes that the parameters are already pushed. - for i := 0; i < sig.ParamNumInUint64; i++ { - _ = s.pushRuntimeValueLocationOnStack() - } - - retAddr, stackBasePointer, fn := s.pushCallFrame(sig) - - expOffset := uint64(callFrameOffset(sig)) - require.Equal(t, expOffset, retAddr.stackPointer) - require.Equal(t, expOffset+1, stackBasePointer.stackPointer) - require.Equal(t, expOffset+2, fn.stackPointer) - }) - } -} - -func Test_usedRegistersMask(t *testing.T) { - for _, r := range append(unreservedVectorRegisters, unreservedGeneralPurposeRegisters...) { - mask := usedRegistersMask(0) - mask.add(r) - require.False(t, mask == 0) - require.True(t, mask.exist(r)) - mask.remove(r) - require.True(t, mask == 0) - require.False(t, mask.exist(r)) - } -} - -func TestRuntimeValueLocation_cloneFrom(t *testing.T) { - t.Run("spcap", func(t *testing.T) { - v := runtimeValueLocationStack{stack: make([]runtimeValueLocation, 0, 3)} - orig := v.stack[:cap(v.stack)] - v.cloneFrom(runtimeValueLocationStack{sp: 5, usedRegisters: 0xffff, stack: []runtimeValueLocation{ - {register: 5}, {register: 4}, {register: 3}, {register: 2}, {register: 1}, - }}) - require.Equal(t, uint64(5), v.sp) - require.Equal(t, usedRegistersMask(0xffff), v.usedRegisters) - // Underlying stack should have changed since sp=5>cap(v.stack). - require.NotEqual(t, &orig[0], &v.stack[0]) - require.Equal(t, v.stack[0].register, asm.Register(5)) - require.Equal(t, v.stack[1].register, asm.Register(4)) - require.Equal(t, v.stack[2].register, asm.Register(3)) - require.Equal(t, v.stack[3].register, asm.Register(2)) - require.Equal(t, v.stack[4].register, asm.Register(1)) - }) -} diff --git a/internal/engine/compiler/compiler_vec_test.go b/internal/engine/compiler/compiler_vec_test.go deleted file mode 100644 index 23385c31ab..0000000000 --- a/internal/engine/compiler/compiler_vec_test.go +++ /dev/null @@ -1,7336 +0,0 @@ -package compiler - -import ( - "encoding/binary" - "math" - "testing" - - "github.com/tetratelabs/wazero/internal/asm" - "github.com/tetratelabs/wazero/internal/moremath" - "github.com/tetratelabs/wazero/internal/testing/require" - "github.com/tetratelabs/wazero/internal/wasm" - "github.com/tetratelabs/wazero/internal/wazeroir" -) - -func TestCompiler_compileV128Add(t *testing.T) { - tests := []struct { - name string - shape wazeroir.Shape - x1, x2, exp [16]byte - }{ - { - name: "i8x16", - shape: wazeroir.ShapeI8x16, - x1: [16]byte{0: 1, 2: 10, 10: 10}, - x2: [16]byte{0: 10, 4: 5, 10: 5}, - exp: [16]byte{0: 11, 2: 10, 4: 5, 10: 15}, - }, - { - name: "i16x8", - shape: wazeroir.ShapeI16x8, - x1: i16x8(1123, 0, 123, 1, 1, 5, 8, 1), - x2: i16x8(0, 123, 123, 0, 1, 5, 9, 1), - exp: i16x8(1123, 123, 246, 1, 2, 10, 17, 2), - }, - { - name: "i32x4", - shape: wazeroir.ShapeI32x4, - x1: i32x4(i32ToU32(-123), 5, 4, math.MaxUint32), - x2: i32x4(i32ToU32(-10), 1, i32ToU32(-104), math.MaxUint32), - exp: i32x4(i32ToU32(-133), 6, i32ToU32(-100), math.MaxUint32-1), - }, - { - name: "i64x2", - shape: wazeroir.ShapeI64x2, - x1: i64x2(i64ToU64(math.MinInt64), 12345), - x2: i64x2(i64ToU64(-1), i64ToU64(-12345)), - exp: i64x2(i64ToU64(math.MinInt64)+i64ToU64(-1), 0), - }, - { - name: "f32x4", - shape: wazeroir.ShapeF32x4, - x1: f32x4(1.0, 123, float32(math.Inf(1)), float32(math.Inf(-1))), - x2: f32x4(51234.12341, 123, math.MaxFloat32, -123), - exp: f32x4(51235.12341, 246, float32(math.Inf(1)), float32(math.Inf(-1))), - }, - { - name: "f64x2", - shape: wazeroir.ShapeF64x2, - x1: f64x2(1.123, math.Inf(1)), - x2: f64x2(1.123, math.MinInt64), - exp: f64x2(2.246, math.Inf(1)), - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, - &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.x1[:8]), binary.LittleEndian.Uint64(tc.x1[8:])))) - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.x2[:8]), binary.LittleEndian.Uint64(tc.x2[8:])))) - require.NoError(t, err) - - err = compiler.compileV128Add(operationPtr(wazeroir.NewOperationV128Add(tc.shape))) - require.NoError(t, err) - - requireRuntimeLocationStackPointerEqual(t, uint64(2), compiler) - require.Equal(t, 1, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - require.Equal(t, nativeCallStatusCodeReturned, env.callEngine().statusCode) - - lo, hi := env.stackTopAsV128() - var actual [16]byte - binary.LittleEndian.PutUint64(actual[:8], lo) - binary.LittleEndian.PutUint64(actual[8:], hi) - require.Equal(t, tc.exp, actual) - }) - } -} - -func TestCompiler_compileV128Sub(t *testing.T) { - tests := []struct { - name string - shape wazeroir.Shape - x1, x2, exp [16]byte - }{ - { - name: "i8x16", - shape: wazeroir.ShapeI8x16, - x1: [16]byte{0: 1, 2: 10, 10: 10}, - x2: [16]byte{0: 10, 4: 5, 10: 5}, - exp: [16]byte{0: i8ToU8(-9), 2: 10, 4: i8ToU8(-5), 10: 5}, - }, - { - name: "i16x8", - shape: wazeroir.ShapeI16x8, - x1: i16x8(1123, 0, 123, 1, 1, 5, 8, 1), - x2: i16x8(0, 123, 123, 0, 1, 5, 9, 1), - exp: i16x8(1123, i16ToU16(-123), 0, 1, 0, 0, i16ToU16(-1), 0), - }, - { - name: "i32x4", - shape: wazeroir.ShapeI32x4, - x1: i32x4(i32ToU32(-123), 5, 4, math.MaxUint32), - x2: i32x4(i32ToU32(-10), 1, i32ToU32(-104), math.MaxUint32), - exp: i32x4(i32ToU32(-113), 4, 108, 0), - }, - { - name: "i64x2", - shape: wazeroir.ShapeI64x2, - x1: i64x2(i64ToU64(math.MinInt64), 12345), - x2: i64x2(i64ToU64(-1), i64ToU64(-12345)), - exp: i64x2(i64ToU64(math.MinInt64+1), 12345*2), - }, - { - name: "f32x4", - shape: wazeroir.ShapeF32x4, - x1: f32x4(1.0, 123, float32(math.Inf(1)), float32(math.Inf(-1))), - x2: f32x4(51234.12341, 123, math.MaxFloat32, -123), - exp: f32x4(-51233.12341, 0, float32(math.Inf(1)), float32(math.Inf(-1))), - }, - { - name: "f64x2", - shape: wazeroir.ShapeF64x2, - x1: f64x2(1.123, math.Inf(1)), - x2: f64x2(1.123, math.MinInt64), - exp: f64x2(0, math.Inf(1)), - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, - &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.x1[:8]), binary.LittleEndian.Uint64(tc.x1[8:])))) - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.x2[:8]), binary.LittleEndian.Uint64(tc.x2[8:])))) - require.NoError(t, err) - - err = compiler.compileV128Sub(operationPtr(wazeroir.NewOperationV128Sub(tc.shape))) - require.NoError(t, err) - - requireRuntimeLocationStackPointerEqual(t, uint64(2), compiler) - require.Equal(t, 1, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - require.Equal(t, nativeCallStatusCodeReturned, env.callEngine().statusCode) - - lo, hi := env.stackTopAsV128() - var actual [16]byte - binary.LittleEndian.PutUint64(actual[:8], lo) - binary.LittleEndian.PutUint64(actual[8:], hi) - require.Equal(t, tc.exp, actual) - }) - } -} - -func TestCompiler_compileV128Load(t *testing.T) { - tests := []struct { - name string - memSetupFn func(buf []byte) - loadType wazeroir.V128LoadType - offset uint32 - exp [16]byte - }{ - { - name: "v128 offset=0", loadType: wazeroir.V128LoadType128, offset: 0, - memSetupFn: func(buf []byte) { - copy(buf, []byte{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20}) - }, - exp: [16]byte{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, - }, - { - name: "v128 offset=2", loadType: wazeroir.V128LoadType128, offset: 2, - memSetupFn: func(buf []byte) { - copy(buf, []byte{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20}) - }, - exp: [16]byte{3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18}, - }, - { - name: "8x8s offset=0", loadType: wazeroir.V128LoadType8x8s, offset: 0, - memSetupFn: func(buf []byte) { - copy(buf, []byte{ - 1, 0xff, 3, 0xff, 5, 0xff, 7, 0xff, 9, 10, - 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, - }) - }, - exp: [16]byte{ - 1, 0, 0xff, 0xff, 3, 0, 0xff, 0xff, 5, 0, 0xff, 0xff, 7, 0, 0xff, 0xff, - }, - }, - { - name: "8x8s offset=3", loadType: wazeroir.V128LoadType8x8s, offset: 3, - memSetupFn: func(buf []byte) { - copy(buf, []byte{ - 1, 0xff, 3, 0xff, 5, 0xff, 7, 0xff, 9, 10, - 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, - }) - }, - exp: [16]byte{ - 0xff, 0xff, 5, 0, 0xff, 0xff, 7, 0, 0xff, 0xff, 9, 0, 10, 0, 11, 0, - }, - }, - { - name: "8x8u offset=0", loadType: wazeroir.V128LoadType8x8u, offset: 0, - memSetupFn: func(buf []byte) { - copy(buf, []byte{ - 1, 0xff, 3, 0xff, 5, 0xff, 7, 0xff, 9, 10, - 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, - }) - }, - exp: [16]byte{ - 1, 0, 0xff, 0, 3, 0, 0xff, 0, 5, 0, 0xff, 0, 7, 0, 0xff, 0, - }, - }, - { - name: "8x8i offset=3", loadType: wazeroir.V128LoadType8x8u, offset: 3, - memSetupFn: func(buf []byte) { - copy(buf, []byte{ - 1, 0xff, 3, 0xff, 5, 0xff, 7, 0xff, 9, 10, - 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, - }) - }, - exp: [16]byte{ - 0xff, 0, 5, 0, 0xff, 0, 7, 0, 0xff, 0, 9, 0, 10, 0, 11, 0, - }, - }, - { - name: "16x4s offset=0", loadType: wazeroir.V128LoadType16x4s, offset: 0, - memSetupFn: func(buf []byte) { - copy(buf, []byte{ - 1, 0xff, 3, 0xff, 5, 0xff, 7, 0xff, 9, 10, - 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, - }) - }, - exp: [16]byte{ - 1, 0xff, 0xff, 0xff, - 3, 0xff, 0xff, 0xff, - 5, 0xff, 0xff, 0xff, - 7, 0xff, 0xff, 0xff, - }, - }, - { - name: "16x4s offset=3", loadType: wazeroir.V128LoadType16x4s, offset: 3, - memSetupFn: func(buf []byte) { - copy(buf, []byte{ - 1, 0xff, 3, 0xff, 5, 6, 0xff, 0xff, 9, 10, - 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, - }) - }, - exp: [16]byte{ - 0xff, 5, 0, 0, - 6, 0xff, 0xff, 0xff, - 0xff, 9, 0, 0, - 10, 11, 0, 0, - }, - }, - { - name: "16x4u offset=0", loadType: wazeroir.V128LoadType16x4u, offset: 0, - memSetupFn: func(buf []byte) { - copy(buf, []byte{ - 1, 0xff, 3, 0xff, 5, 0xff, 7, 0xff, 9, 10, - 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, - }) - }, - exp: [16]byte{ - 1, 0xff, 0, 0, - 3, 0xff, 0, 0, - 5, 0xff, 0, 0, - 7, 0xff, 0, 0, - }, - }, - { - name: "16x4u offset=3", loadType: wazeroir.V128LoadType16x4u, offset: 3, - memSetupFn: func(buf []byte) { - copy(buf, []byte{ - 1, 0xff, 3, 0xff, 5, 6, 0xff, 0xff, 9, 10, - 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, - }) - }, - exp: [16]byte{ - 0xff, 5, 0, 0, - 6, 0xff, 0, 0, - 0xff, 9, 0, 0, - 10, 11, 0, 0, - }, - }, - { - name: "32x2s offset=0", loadType: wazeroir.V128LoadType32x2s, offset: 0, - memSetupFn: func(buf []byte) { - copy(buf, []byte{ - 1, 0xff, 3, 0xff, 5, 6, 7, 0xff, 9, 10, - 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, - }) - }, - exp: [16]byte{ - 1, 0xff, 3, 0xff, 0xff, 0xff, 0xff, 0xff, - 5, 6, 7, 0xff, 0xff, 0xff, 0xff, 0xff, - }, - }, - { - name: "32x2s offset=2", loadType: wazeroir.V128LoadType32x2s, offset: 2, - memSetupFn: func(buf []byte) { - copy(buf, []byte{ - 1, 0xff, 3, 0xff, 5, 6, 7, 0xff, 9, 0xff, - 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, - }) - }, - exp: [16]byte{ - 3, 0xff, 5, 6, 0, 0, 0, 0, - 7, 0xff, 9, 0xff, 0xff, 0xff, 0xff, 0xff, - }, - }, - { - name: "32x2u offset=0", loadType: wazeroir.V128LoadType32x2u, offset: 0, - memSetupFn: func(buf []byte) { - copy(buf, []byte{ - 1, 0xff, 3, 0xff, 5, 6, 7, 0xff, 9, 10, - 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, - }) - }, - exp: [16]byte{ - 1, 0xff, 3, 0xff, 0, 0, 0, 0, - 5, 6, 7, 0xff, 0, 0, 0, 0, - }, - }, - { - name: "32x2u offset=2", loadType: wazeroir.V128LoadType32x2u, offset: 2, - memSetupFn: func(buf []byte) { - copy(buf, []byte{ - 1, 0xff, 3, 0xff, 5, 6, 7, 0xff, 9, 0xff, - 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, - }) - }, - exp: [16]byte{ - 3, 0xff, 5, 6, 0, 0, 0, 0, - 7, 0xff, 9, 0xff, 0, 0, 0, 0, - }, - }, - { - name: "32zero offset=0", loadType: wazeroir.V128LoadType32zero, offset: 0, - memSetupFn: func(buf []byte) { - copy(buf, []byte{ - 1, 0xff, 3, 0xff, 5, 6, 7, 0xff, 9, 0xff, - 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, - }) - }, - exp: [16]byte{ - 1, 0xff, 3, 0xff, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - }, - }, - { - name: "32zero offset=3", loadType: wazeroir.V128LoadType32zero, offset: 3, - memSetupFn: func(buf []byte) { - copy(buf, []byte{ - 1, 0xff, 3, 0xff, 5, 6, 0xff, 8, 9, 0xff, - 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, - }) - }, - exp: [16]byte{ - 0xff, 5, 6, 0xff, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - }, - }, - { - name: "32zero on ceil", loadType: wazeroir.V128LoadType32zero, - offset: wasm.MemoryPageSize - 4, - memSetupFn: func(buf []byte) { - copy(buf[wasm.MemoryPageSize-8:], []byte{ - 1, 0xff, 3, 0xff, - 5, 6, 0xff, 8, - }) - }, - exp: [16]byte{5, 6, 0xff, 8}, - }, - { - name: "64zero offset=0", loadType: wazeroir.V128LoadType64zero, offset: 0, - memSetupFn: func(buf []byte) { - copy(buf, []byte{ - 1, 0xff, 3, 0xff, 5, 6, 7, 0xff, 9, 0xff, - 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, - }) - }, - exp: [16]byte{ - 1, 0xff, 3, 0xff, 5, 6, 7, 0xff, - 0, 0, 0, 0, 0, 0, 0, 0, - }, - }, - { - name: "64zero offset=2", loadType: wazeroir.V128LoadType64zero, offset: 2, - memSetupFn: func(buf []byte) { - copy(buf, []byte{ - 1, 0xff, 3, 0xff, 5, 6, 7, 0xff, 9, 0xff, - 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, - }) - }, - exp: [16]byte{ - 3, 0xff, 5, 6, 7, 0xff, 9, 0xff, - 0, 0, 0, 0, 0, 0, 0, 0, - }, - }, - { - name: "64zero on ceil", loadType: wazeroir.V128LoadType64zero, - offset: wasm.MemoryPageSize - 8, - memSetupFn: func(buf []byte) { - copy(buf[wasm.MemoryPageSize-16:], []byte{ - 1, 0xff, 3, 0xff, 5, 6, 7, 0xff, - 9, 0xff, 11, 12, 13, 14, 15, - }) - }, - exp: [16]byte{9, 0xff, 11, 12, 13, 14, 15, 0, 0, 0, 0, 0, 0}, - }, - { - name: "8splat offset=0", loadType: wazeroir.V128LoadType8Splat, offset: 0, - memSetupFn: func(buf []byte) { - copy(buf, []byte{ - 1, 0xff, 3, 0xff, 5, 6, 7, 0xff, 9, 0xff, - }) - }, - exp: [16]byte{1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}, - }, - { - name: "8splat offset=1", loadType: wazeroir.V128LoadType8Splat, offset: 1, - memSetupFn: func(buf []byte) { - copy(buf, []byte{ - 1, 0xff, 3, 0xff, 5, 6, 7, 0xff, 9, 0xff, - }) - }, - exp: [16]byte{ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - }, - }, - { - name: "16splat offset=0", loadType: wazeroir.V128LoadType16Splat, offset: 0, - memSetupFn: func(buf []byte) { - copy(buf, []byte{ - 1, 0xff, 3, 0xff, 5, 6, 7, 0xff, 9, 0xff, - }) - }, - exp: [16]byte{1, 0xff, 1, 0xff, 1, 0xff, 1, 0xff, 1, 0xff, 1, 0xff, 1, 0xff, 1, 0xff}, - }, - { - name: "16splat offset=5", loadType: wazeroir.V128LoadType16Splat, offset: 5, - memSetupFn: func(buf []byte) { - copy(buf, []byte{ - 1, 0xff, 3, 0xff, 5, 6, 7, 0xff, 9, 0xff, - }) - }, - exp: [16]byte{6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7, 6, 7}, - }, - { - name: "32splat offset=0", loadType: wazeroir.V128LoadType32Splat, offset: 0, - memSetupFn: func(buf []byte) { - copy(buf, []byte{ - 1, 0xff, 3, 0xff, 5, 6, 7, 0xff, 9, 0xff, - }) - }, - exp: [16]byte{1, 0xff, 3, 0xff, 1, 0xff, 3, 0xff, 1, 0xff, 3, 0xff, 1, 0xff, 3, 0xff}, - }, - { - name: "32splat offset=1", loadType: wazeroir.V128LoadType32Splat, offset: 1, - memSetupFn: func(buf []byte) { - copy(buf, []byte{ - 1, 0xff, 3, 0xff, 5, 6, 7, 0xff, 9, 0xff, - }) - }, - exp: [16]byte{0xff, 3, 0xff, 5, 0xff, 3, 0xff, 5, 0xff, 3, 0xff, 5, 0xff, 3, 0xff, 5}, - }, - { - name: "64splat offset=0", loadType: wazeroir.V128LoadType64Splat, offset: 0, - memSetupFn: func(buf []byte) { - copy(buf, []byte{ - 1, 0xff, 3, 0xff, 5, 6, 7, 0xff, 9, 0xff, - }) - }, - exp: [16]byte{1, 0xff, 3, 0xff, 5, 6, 7, 0xff, 1, 0xff, 3, 0xff, 5, 6, 7, 0xff}, - }, - { - name: "64splat offset=1", loadType: wazeroir.V128LoadType64Splat, offset: 1, - memSetupFn: func(buf []byte) { - copy(buf, []byte{ - 1, 0xff, 3, 0xff, 5, 6, 7, 0xff, 9, 0xff, - }) - }, - exp: [16]byte{0xff, 3, 0xff, 5, 6, 7, 0xff, 9, 0xff, 3, 0xff, 5, 6, 7, 0xff, 9}, - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - tc.memSetupFn(env.memory()) - - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, - &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(tc.offset))) - require.NoError(t, err) - - err = compiler.compileV128Load(operationPtr(wazeroir.NewOperationV128Load(tc.loadType, wazeroir.MemoryArg{}))) - require.NoError(t, err) - - requireRuntimeLocationStackPointerEqual(t, uint64(2), compiler) - require.Equal(t, 1, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - loadedLocation := compiler.runtimeValueLocationStack().peek() - require.True(t, loadedLocation.onRegister()) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - require.Equal(t, nativeCallStatusCodeReturned, env.callEngine().statusCode) - - require.Equal(t, uint64(2), env.stackPointer()) - lo, hi := env.stackTopAsV128() - - var actual [16]byte - binary.LittleEndian.PutUint64(actual[:8], lo) - binary.LittleEndian.PutUint64(actual[8:], hi) - require.Equal(t, tc.exp, actual) - }) - } -} - -func TestCompiler_compileV128LoadLane(t *testing.T) { - originalVecLo, originalVecHi := uint64(0), uint64(0) - tests := []struct { - name string - memSetupFn func(buf []byte) - laneIndex, laneSize byte - offset uint32 - exp [16]byte - }{ - { - name: "8_lane offset=0 laneIndex=0", - memSetupFn: func(buf []byte) { - copy(buf, []byte{ - 1, 0xff, - }) - }, - laneSize: 8, - laneIndex: 0, - offset: 0, - exp: [16]byte{1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, - }, - { - name: "8_lane offset=1 laneIndex=0", - memSetupFn: func(buf []byte) { - copy(buf, []byte{ - 1, 0xff, - }) - }, - laneSize: 8, - laneIndex: 0, - offset: 1, - exp: [16]byte{0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, - }, - { - name: "8_lane offset=1 laneIndex=5", - memSetupFn: func(buf []byte) { - copy(buf, []byte{ - 1, 0xff, - }) - }, - laneSize: 8, - laneIndex: 5, - offset: 1, - exp: [16]byte{0, 0, 0, 0, 0, 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, - }, - { - name: "16_lane offset=0 laneIndex=0", - memSetupFn: func(buf []byte) { - copy(buf, []byte{ - 1, 0xff, 1, 0xa, - }) - }, - laneSize: 16, - laneIndex: 0, - offset: 0, - exp: [16]byte{1, 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, - }, - { - name: "16_lane offset=1 laneIndex=0", - memSetupFn: func(buf []byte) { - copy(buf, []byte{ - 1, 0xff, 1, 0xa, - }) - }, - laneSize: 16, - laneIndex: 0, - offset: 1, - exp: [16]byte{0xff, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, - }, - { - name: "16_lane offset=1 laneIndex=5", - memSetupFn: func(buf []byte) { - copy(buf, []byte{ - 1, 0xff, 1, 0xa, - }) - }, - laneSize: 16, - laneIndex: 5, - offset: 1, - exp: [16]byte{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0xff, 1, 0, 0, 0, 0}, - }, - { - name: "32_lane offset=0 laneIndex=0", - memSetupFn: func(buf []byte) { - copy(buf, []byte{ - 1, 0xff, 1, 0xa, 0x9, 0x8, - }) - }, - laneSize: 32, - laneIndex: 0, - offset: 0, - exp: [16]byte{1, 0xff, 1, 0xa, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, - }, - { - name: "32_lane offset=1 laneIndex=0", - memSetupFn: func(buf []byte) { - copy(buf, []byte{ - 1, 0xff, 1, 0xa, 0x9, 0x8, - }) - }, - laneSize: 32, - laneIndex: 0, - offset: 1, - exp: [16]byte{0xff, 1, 0xa, 0x9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, - }, - { - name: "32_lane offset=1 laneIndex=3", - memSetupFn: func(buf []byte) { - copy(buf, []byte{ - 1, 0xff, 1, 0xa, 0x9, 0x8, - }) - }, - laneSize: 32, - laneIndex: 3, - offset: 1, - exp: [16]byte{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0xff, 1, 0xa, 0x9}, - }, - - { - name: "64_lane offset=0 laneIndex=0", - memSetupFn: func(buf []byte) { - copy(buf, []byte{ - 1, 0xff, 1, 0xa, 0x9, 0x8, 0x1, 0x2, 0x3, 0x4, - }) - }, - laneSize: 64, - laneIndex: 0, - offset: 0, - exp: [16]byte{1, 0xff, 1, 0xa, 0x9, 0x8, 0x1, 0x2, 0, 0, 0, 0, 0, 0, 0, 0}, - }, - { - name: "64_lane offset=1 laneIndex=0", - memSetupFn: func(buf []byte) { - copy(buf, []byte{ - 1, 0xff, 1, 0xa, 0x9, 0x8, 0x1, 0x2, 0x3, 0x4, - }) - }, - laneSize: 64, - laneIndex: 0, - offset: 1, - exp: [16]byte{0xff, 1, 0xa, 0x9, 0x8, 0x1, 0x2, 0x3, 0, 0, 0, 0, 0, 0, 0, 0}, - }, - { - name: "64_lane offset=3 laneIndex=1", - memSetupFn: func(buf []byte) { - copy(buf, []byte{ - 1, 0xff, 1, 0xa, 0x9, 0x8, 0x1, 0x2, 0x3, 0x4, 0xa, - }) - }, - laneSize: 64, - laneIndex: 1, - offset: 3, - exp: [16]byte{0, 0, 0, 0, 0, 0, 0, 0, 0xa, 0x9, 0x8, 0x1, 0x2, 0x3, 0x4, 0xa}, - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - tc.memSetupFn(env.memory()) - - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, - &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(tc.offset))) - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(originalVecLo, originalVecHi))) - require.NoError(t, err) - - err = compiler.compileV128LoadLane( - operationPtr(wazeroir.NewOperationV128LoadLane(tc.laneIndex, tc.laneSize, wazeroir.MemoryArg{}))) - require.NoError(t, err) - - requireRuntimeLocationStackPointerEqual(t, uint64(2), compiler) - require.Equal(t, 1, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - loadedLocation := compiler.runtimeValueLocationStack().peek() - require.True(t, loadedLocation.onRegister()) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - require.Equal(t, uint64(2), env.stackPointer()) - lo, hi := env.stackTopAsV128() - - var actual [16]byte - binary.LittleEndian.PutUint64(actual[:8], lo) - binary.LittleEndian.PutUint64(actual[8:], hi) - require.Equal(t, tc.exp, actual) - }) - } -} - -func TestCompiler_compileV128Store(t *testing.T) { - tests := []struct { - name string - offset uint32 - }{ - {name: "offset=1", offset: 1}, - {name: "offset=5", offset: 5}, - {name: "offset=10", offset: 10}, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, - &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(tc.offset))) - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(^uint64(0), ^uint64(0)))) - require.NoError(t, err) - - err = compiler.compileV128Store(operationPtr(wazeroir.NewOperationV128Store(wazeroir.MemoryArg{}))) - require.NoError(t, err) - - requireRuntimeLocationStackPointerEqual(t, uint64(0), compiler) - require.Equal(t, 0, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - require.Equal(t, uint64(0), env.stackPointer()) - - mem := env.memory() - require.Equal(t, []byte{ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - }, - mem[tc.offset:tc.offset+16]) - }) - } -} - -func TestCompiler_compileV128StoreLane(t *testing.T) { - vecBytes := [16]byte{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16} - tests := []struct { - name string - laneIndex, laneSize byte - offset uint32 - exp [16]byte - }{ - { - name: "8_lane offset=0 laneIndex=0", - laneSize: 8, - laneIndex: 0, - offset: 0, - exp: [16]byte{1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, - }, - { - name: "8_lane offset=1 laneIndex=0", - laneSize: 8, - laneIndex: 0, - offset: 1, - exp: [16]byte{0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, - }, - { - name: "8_lane offset=3 laneIndex=5", - laneSize: 8, - laneIndex: 5, - offset: 3, - exp: [16]byte{0, 0, 0, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, - }, - { - name: "16_lane offset=0 laneIndex=0", - laneSize: 16, - laneIndex: 0, - offset: 0, - exp: [16]byte{1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, - }, - { - name: "16_lane offset=1 laneIndex=0", - laneSize: 16, - laneIndex: 0, - offset: 1, - exp: [16]byte{0, 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, - }, - { - name: "16_lane offset=5 laneIndex=7", - laneSize: 16, - laneIndex: 7, - offset: 5, - exp: [16]byte{0, 0, 0, 0, 0, 15, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0}, - }, - - { - name: "32_lane offset=0 laneIndex=0", - laneSize: 32, - laneIndex: 0, - offset: 0, - exp: [16]byte{1, 2, 3, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, - }, - { - name: "32_lane offset=1 laneIndex=0", - laneSize: 32, - laneIndex: 0, - offset: 1, - exp: [16]byte{0, 1, 2, 3, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, - }, - { - name: "32_lane offset=5 laneIndex=3", - laneSize: 32, - laneIndex: 3, - offset: 5, - exp: [16]byte{0, 0, 0, 0, 0, 13, 14, 15, 16, 0, 0, 0, 0, 0, 0, 0}, - }, - - { - name: "64_lane offset=0 laneIndex=0", - laneSize: 64, - laneIndex: 0, - offset: 0, - exp: [16]byte{1, 2, 3, 4, 5, 6, 7, 8, 0, 0, 0, 0, 0, 0, 0, 0}, - }, - { - name: "64_lane offset=1 laneIndex=0", - laneSize: 64, - laneIndex: 0, - offset: 1, - exp: [16]byte{0, 1, 2, 3, 4, 5, 6, 7, 8, 0, 0, 0, 0, 0, 0, 0}, - }, - { - name: "64_lane offset=5 laneIndex=3", - laneSize: 64, - laneIndex: 1, - offset: 6, - exp: [16]byte{0, 0, 0, 0, 0, 0, 9, 10, 11, 12, 13, 14, 15, 16, 0, 0}, - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, - &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(tc.offset))) - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(vecBytes[:8]), binary.LittleEndian.Uint64(vecBytes[8:])))) - require.NoError(t, err) - - err = compiler.compileV128StoreLane(operationPtr(wazeroir.NewOperationV128StoreLane(tc.laneIndex, tc.laneSize, wazeroir.MemoryArg{}))) - require.NoError(t, err) - - requireRuntimeLocationStackPointerEqual(t, uint64(0), compiler) - require.Equal(t, 0, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - require.Equal(t, tc.exp[:], env.memory()[:16]) - }) - } -} - -func TestCompiler_compileV128ExtractLane(t *testing.T) { - tests := []struct { - name string - vecBytes [16]byte - shape wazeroir.Shape - signed bool - laneIndex byte - exp uint64 - }{ - { - name: "i8x16 unsigned index=0", - vecBytes: [16]byte{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, - shape: wazeroir.ShapeI8x16, - signed: false, - laneIndex: 0, - exp: uint64(byte(1)), - }, - { - name: "i8x16 unsigned index=15", - vecBytes: [16]byte{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0xff}, - shape: wazeroir.ShapeI8x16, - signed: false, - laneIndex: 15, - exp: uint64(byte(0xff)), - }, - { - name: "i8x16 signed index=0", - vecBytes: [16]byte{0xf1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, - shape: wazeroir.ShapeI8x16, - signed: true, - laneIndex: 0, - exp: uint64(0xff_ff_ff_f1), - }, - { - name: "i8x16 signed index=1", - vecBytes: [16]byte{0xf0, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, - shape: wazeroir.ShapeI8x16, - signed: true, - laneIndex: 1, - exp: uint64(2), - }, - { - name: "i16x8 unsigned index=0", - vecBytes: [16]byte{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, - shape: wazeroir.ShapeI16x8, - signed: false, - laneIndex: 0, - exp: uint64(uint16(0x2<<8 | 0x1)), - }, - { - name: "i16x8 unsigned index=7", - vecBytes: [16]byte{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0xff}, - shape: wazeroir.ShapeI16x8, - signed: false, - laneIndex: 7, - exp: uint64(uint16(0xff<<8 | 15)), - }, - { - name: "i16x8 signed index=0", - vecBytes: [16]byte{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, - shape: wazeroir.ShapeI16x8, - signed: true, - laneIndex: 0, - exp: uint64(uint16(0x2<<8 | 0x1)), - }, - { - name: "i16x8 signed index=7", - vecBytes: [16]byte{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0xf1}, - shape: wazeroir.ShapeI16x8, - signed: true, - laneIndex: 7, - exp: uint64(uint32(0xffff<<16) | uint32(uint16(0xf1<<8|15))), - }, - { - name: "i32x4 index=0", - vecBytes: [16]byte{0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16}, - shape: wazeroir.ShapeI32x4, - laneIndex: 0, - exp: uint64(uint32(0x04_03_02_01)), - }, - { - name: "i32x4 index=3", - vecBytes: [16]byte{0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16}, - shape: wazeroir.ShapeI32x4, - laneIndex: 3, - exp: uint64(uint32(0x16_15_14_13)), - }, - { - name: "i64x4 index=0", - vecBytes: [16]byte{0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16}, - shape: wazeroir.ShapeI64x2, - laneIndex: 0, - exp: uint64(0x08_07_06_05_04_03_02_01), - }, - { - name: "i64x4 index=1", - vecBytes: [16]byte{0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16}, - shape: wazeroir.ShapeI64x2, - laneIndex: 1, - exp: uint64(0x16_15_14_13_12_11_10_09), - }, - { - name: "f32x4 index=0", - vecBytes: [16]byte{0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16}, - shape: wazeroir.ShapeF32x4, - laneIndex: 0, - exp: uint64(uint32(0x04_03_02_01)), - }, - { - name: "f32x4 index=3", - vecBytes: [16]byte{0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16}, - shape: wazeroir.ShapeF32x4, - laneIndex: 3, - exp: uint64(uint32(0x16_15_14_13)), - }, - { - name: "f64x4 index=0", - vecBytes: [16]byte{0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16}, - shape: wazeroir.ShapeF64x2, - laneIndex: 0, - exp: uint64(0x08_07_06_05_04_03_02_01), - }, - { - name: "f64x4 index=1", - vecBytes: [16]byte{0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16}, - shape: wazeroir.ShapeF64x2, - laneIndex: 1, - exp: uint64(0x16_15_14_13_12_11_10_09), - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, - &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.vecBytes[:8]), binary.LittleEndian.Uint64(tc.vecBytes[8:])))) - require.NoError(t, err) - - err = compiler.compileV128ExtractLane(operationPtr(wazeroir.NewOperationV128ExtractLane(tc.laneIndex, tc.signed, tc.shape))) - require.NoError(t, err) - - requireRuntimeLocationStackPointerEqual(t, uint64(1), compiler) - require.Equal(t, 1, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - - vt := compiler.runtimeValueLocationStack().peek().valueType - switch tc.shape { - case wazeroir.ShapeI8x16, wazeroir.ShapeI16x8, wazeroir.ShapeI32x4: - require.Equal(t, runtimeValueTypeI32, vt) - case wazeroir.ShapeI64x2: - require.Equal(t, runtimeValueTypeI64, vt) - case wazeroir.ShapeF32x4: - require.Equal(t, runtimeValueTypeF32, vt) - case wazeroir.ShapeF64x2: - require.Equal(t, runtimeValueTypeF64, vt) - } - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - switch tc.shape { - case wazeroir.ShapeI8x16, wazeroir.ShapeI16x8, wazeroir.ShapeI32x4, wazeroir.ShapeF32x4: - require.Equal(t, uint32(tc.exp), env.stackTopAsUint32()) - case wazeroir.ShapeI64x2, wazeroir.ShapeF64x2: - require.Equal(t, tc.exp, env.stackTopAsUint64()) - } - }) - } -} - -func TestCompiler_compileV128ReplaceLane(t *testing.T) { - tests := []struct { - name string - originValueSetupFn func(*testing.T, compilerImpl) - shape wazeroir.Shape - laneIndex byte - exp [16]byte - lo, hi uint64 - }{ - { - name: "i8x16 index=0", - shape: wazeroir.ShapeI8x16, - laneIndex: 5, - originValueSetupFn: func(t *testing.T, c compilerImpl) { - err := c.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(0xff))) - require.NoError(t, err) - }, - exp: [16]byte{5: 0xff}, - }, - { - name: "i8x16 index=3", - shape: wazeroir.ShapeI8x16, - laneIndex: 5, - originValueSetupFn: func(t *testing.T, c compilerImpl) { - err := c.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(0xff << 8))) - require.NoError(t, err) - }, - exp: [16]byte{}, - }, - { - name: "i8x16 index=5", - shape: wazeroir.ShapeI8x16, - laneIndex: 5, - originValueSetupFn: func(t *testing.T, c compilerImpl) { - err := c.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(0xff))) - require.NoError(t, err) - }, - exp: [16]byte{5: 0xff}, - }, - { - name: "i16x8 index=0", - shape: wazeroir.ShapeI16x8, - laneIndex: 0, - originValueSetupFn: func(t *testing.T, c compilerImpl) { - err := c.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(0xee_ff))) - require.NoError(t, err) - }, - exp: [16]byte{0: 0xff, 1: 0xee}, - }, - { - name: "i16x8 index=3", - shape: wazeroir.ShapeI16x8, - laneIndex: 3, - originValueSetupFn: func(t *testing.T, c compilerImpl) { - err := c.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(0xaa_00))) - require.NoError(t, err) - }, - exp: [16]byte{7: 0xaa}, - }, - { - name: "i16x8 index=7", - shape: wazeroir.ShapeI16x8, - laneIndex: 3, - originValueSetupFn: func(t *testing.T, c compilerImpl) { - err := c.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(0xaa_bb << 16))) - require.NoError(t, err) - }, - exp: [16]byte{}, - }, - { - name: "i32x4 index=0", - shape: wazeroir.ShapeI32x4, - laneIndex: 0, - originValueSetupFn: func(t *testing.T, c compilerImpl) { - err := c.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(0xaa_bb_cc_dd))) - require.NoError(t, err) - }, - exp: [16]byte{0: 0xdd, 1: 0xcc, 2: 0xbb, 3: 0xaa}, - }, - { - name: "i32x4 index=3", - shape: wazeroir.ShapeI32x4, - laneIndex: 3, - originValueSetupFn: func(t *testing.T, c compilerImpl) { - err := c.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(0xaa_bb_cc_dd))) - require.NoError(t, err) - }, - exp: [16]byte{12: 0xdd, 13: 0xcc, 14: 0xbb, 15: 0xaa}, - }, - { - name: "i64x2 index=0", - shape: wazeroir.ShapeI64x2, - laneIndex: 0, - originValueSetupFn: func(t *testing.T, c compilerImpl) { - err := c.compileConstI64(operationPtr(wazeroir.NewOperationConstI64(0xaa_bb_cc_dd_01_02_03_04))) - require.NoError(t, err) - }, - exp: [16]byte{0: 0x04, 1: 0x03, 2: 0x02, 3: 0x01, 4: 0xdd, 5: 0xcc, 6: 0xbb, 7: 0xaa}, - }, - { - name: "i64x2 index=1", - shape: wazeroir.ShapeI64x2, - laneIndex: 1, - originValueSetupFn: func(t *testing.T, c compilerImpl) { - err := c.compileConstI64(operationPtr(wazeroir.NewOperationConstI64(0xaa_bb_cc_dd_01_02_03_04))) - require.NoError(t, err) - }, - exp: [16]byte{8: 0x04, 9: 0x03, 10: 0x02, 11: 0x01, 12: 0xdd, 13: 0xcc, 14: 0xbb, 15: 0xaa}, - }, - { - name: "f32x4 index=0", - shape: wazeroir.ShapeF32x4, - laneIndex: 0, - originValueSetupFn: func(t *testing.T, c compilerImpl) { - err := c.compileConstF32(operationPtr(wazeroir.NewOperationConstF32(math.Float32frombits(0xaa_bb_cc_dd)))) - require.NoError(t, err) - }, - exp: [16]byte{0: 0xdd, 1: 0xcc, 2: 0xbb, 3: 0xaa}, - }, - { - name: "f32x4 index=1", - shape: wazeroir.ShapeF32x4, - laneIndex: 1, - originValueSetupFn: func(t *testing.T, c compilerImpl) { - err := c.compileConstF32(operationPtr(wazeroir.NewOperationConstF32(math.Float32frombits(0xaa_bb_cc_dd)))) - require.NoError(t, err) - }, - exp: [16]byte{4: 0xdd, 5: 0xcc, 6: 0xbb, 7: 0xaa}, - }, - { - name: "f32x4 index=2", - shape: wazeroir.ShapeF32x4, - laneIndex: 2, - originValueSetupFn: func(t *testing.T, c compilerImpl) { - err := c.compileConstF32(operationPtr(wazeroir.NewOperationConstF32(math.Float32frombits(0xaa_bb_cc_dd)))) - require.NoError(t, err) - }, - exp: [16]byte{8: 0xdd, 9: 0xcc, 10: 0xbb, 11: 0xaa}, - }, - { - name: "f32x4 index=3", - shape: wazeroir.ShapeF32x4, - laneIndex: 3, - originValueSetupFn: func(t *testing.T, c compilerImpl) { - err := c.compileConstF32(operationPtr(wazeroir.NewOperationConstF32(math.Float32frombits(0xaa_bb_cc_dd)))) - require.NoError(t, err) - }, - exp: [16]byte{12: 0xdd, 13: 0xcc, 14: 0xbb, 15: 0xaa}, - }, - { - name: "f64x2 index=0", - shape: wazeroir.ShapeF64x2, - laneIndex: 0, - originValueSetupFn: func(t *testing.T, c compilerImpl) { - err := c.compileConstF64(operationPtr(wazeroir.NewOperationConstF64(math.Float64frombits(0xaa_bb_cc_dd_01_02_03_04)))) - require.NoError(t, err) - }, - exp: [16]byte{0: 0x04, 1: 0x03, 2: 0x02, 3: 0x01, 4: 0xdd, 5: 0xcc, 6: 0xbb, 7: 0xaa}, - }, - { - name: "f64x2 index=1", - shape: wazeroir.ShapeF64x2, - laneIndex: 1, - originValueSetupFn: func(t *testing.T, c compilerImpl) { - err := c.compileConstF64(operationPtr(wazeroir.NewOperationConstF64(math.Float64frombits(0xaa_bb_cc_dd_01_02_03_04)))) - require.NoError(t, err) - }, - exp: [16]byte{8: 0x04, 9: 0x03, 10: 0x02, 11: 0x01, 12: 0xdd, 13: 0xcc, 14: 0xbb, 15: 0xaa}, - }, - { - name: "f64x2 index=0 / lo,hi = 1.0", - shape: wazeroir.ShapeF64x2, - laneIndex: 0, - originValueSetupFn: func(t *testing.T, c compilerImpl) { - err := c.compileConstF64(operationPtr(wazeroir.NewOperationConstF64(math.Float64frombits(0.0)))) - require.NoError(t, err) - }, - lo: math.Float64bits(1.0), - hi: math.Float64bits(1.0), - exp: [16]byte{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf0, 0x3f}, - }, - { - name: "f64x2 index=1 / lo,hi = 1.0", - shape: wazeroir.ShapeF64x2, - laneIndex: 1, - originValueSetupFn: func(t *testing.T, c compilerImpl) { - err := c.compileConstF64(operationPtr(wazeroir.NewOperationConstF64(math.Float64frombits(0.0)))) - require.NoError(t, err) - }, - lo: math.Float64bits(1.0), - hi: math.Float64bits(1.0), - exp: [16]byte{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf0, 0x3f, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, - &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(tc.lo, tc.hi))) - require.NoError(t, err) - - tc.originValueSetupFn(t, compiler) - - err = compiler.compileV128ReplaceLane(operationPtr(wazeroir.NewOperationV128ReplaceLane(tc.laneIndex, tc.shape))) - require.NoError(t, err) - - requireRuntimeLocationStackPointerEqual(t, uint64(2), compiler) - require.Equal(t, 1, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - lo, hi := env.stackTopAsV128() - var actual [16]byte - binary.LittleEndian.PutUint64(actual[:8], lo) - binary.LittleEndian.PutUint64(actual[8:], hi) - require.Equal(t, tc.exp, actual) - }) - } -} - -func TestCompiler_compileV128Splat(t *testing.T) { - tests := []struct { - name string - originValueSetupFn func(*testing.T, compilerImpl) - shape wazeroir.Shape - exp [16]byte - }{ - { - name: "i8x16", - originValueSetupFn: func(t *testing.T, c compilerImpl) { - err := c.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(0x1))) - require.NoError(t, err) - }, - shape: wazeroir.ShapeI8x16, - exp: [16]byte{0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1}, - }, - { - name: "i16x8", - originValueSetupFn: func(t *testing.T, c compilerImpl) { - err := c.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(0xff_11))) - require.NoError(t, err) - }, - shape: wazeroir.ShapeI16x8, - exp: [16]byte{0x11, 0xff, 0x11, 0xff, 0x11, 0xff, 0x11, 0xff, 0x11, 0xff, 0x11, 0xff, 0x11, 0xff, 0x11, 0xff}, - }, - { - name: "i32x4", - originValueSetupFn: func(t *testing.T, c compilerImpl) { - err := c.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(0xff_11_ee_22))) - require.NoError(t, err) - }, - shape: wazeroir.ShapeI32x4, - exp: [16]byte{0x22, 0xee, 0x11, 0xff, 0x22, 0xee, 0x11, 0xff, 0x22, 0xee, 0x11, 0xff, 0x22, 0xee, 0x11, 0xff}, - }, - { - name: "i64x2", - originValueSetupFn: func(t *testing.T, c compilerImpl) { - err := c.compileConstI64(operationPtr(wazeroir.NewOperationConstI64(0xff_00_ee_00_11_00_22_00))) - require.NoError(t, err) - }, - shape: wazeroir.ShapeI64x2, - exp: [16]byte{0x00, 0x22, 0x00, 0x11, 0x00, 0xee, 0x00, 0xff, 0x00, 0x22, 0x00, 0x11, 0x00, 0xee, 0x00, 0xff}, - }, - { - name: "f32x4", - originValueSetupFn: func(t *testing.T, c compilerImpl) { - err := c.compileConstF32(operationPtr(wazeroir.NewOperationConstF32(math.Float32frombits(0xff_11_ee_22)))) - require.NoError(t, err) - }, - shape: wazeroir.ShapeF32x4, - exp: [16]byte{0x22, 0xee, 0x11, 0xff, 0x22, 0xee, 0x11, 0xff, 0x22, 0xee, 0x11, 0xff, 0x22, 0xee, 0x11, 0xff}, - }, - { - name: "f64x2", - originValueSetupFn: func(t *testing.T, c compilerImpl) { - err := c.compileConstF64(operationPtr(wazeroir.NewOperationConstF64(math.Float64frombits(0xff_00_ee_00_11_00_22_00)))) - require.NoError(t, err) - }, - shape: wazeroir.ShapeF64x2, - exp: [16]byte{0x00, 0x22, 0x00, 0x11, 0x00, 0xee, 0x00, 0xff, 0x00, 0x22, 0x00, 0x11, 0x00, 0xee, 0x00, 0xff}, - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, - &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - tc.originValueSetupFn(t, compiler) - - err = compiler.compileV128Splat(operationPtr(wazeroir.NewOperationV128Splat(tc.shape))) - require.NoError(t, err) - - requireRuntimeLocationStackPointerEqual(t, uint64(2), compiler) - require.Equal(t, 1, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - lo, hi := env.stackTopAsV128() - var actual [16]byte - binary.LittleEndian.PutUint64(actual[:8], lo) - binary.LittleEndian.PutUint64(actual[8:], hi) - require.Equal(t, tc.exp, actual) - }) - } -} - -func TestCompiler_compileV128AnyTrue(t *testing.T) { - tests := []struct { - name string - lo, hi uint64 - exp uint32 - }{ - {name: "lo == 0 && hi == 0", lo: 0, hi: 0, exp: 0}, - {name: "lo != 0", lo: 1, exp: 1}, - {name: "hi != 0", hi: 1, exp: 1}, - {name: "lo != 0 && hi != 0", lo: 1, hi: 1, exp: 1}, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, - &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(tc.lo, tc.hi))) - require.NoError(t, err) - - err = compiler.compileV128AnyTrue(operationPtr(wazeroir.NewOperationV128AnyTrue())) - require.NoError(t, err) - - requireRuntimeLocationStackPointerEqual(t, uint64(1), compiler) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - require.Equal(t, nativeCallStatusCodeReturned, env.callEngine().statusCode) - require.Equal(t, uint64(1), env.stackPointer()) - require.Equal(t, tc.exp, env.stackTopAsUint32()) - }) - } -} - -func TestCompiler_compileV128AllTrue(t *testing.T) { - tests := []struct { - name string - shape wazeroir.Shape - lo, hi uint64 - exp uint32 - }{ - { - name: "i8x16 - true", - shape: wazeroir.ShapeI8x16, - lo: 0xffff_ffff_ffff_ffff, - hi: 0x0101_0101_0101_0101, - exp: 1, - }, - { - name: "i8x16 - false on lo", - shape: wazeroir.ShapeI8x16, - lo: 0xffff_ffff_ffff_ffff, - hi: 0x1111_1111_0011_1111, - exp: 0, - }, - { - name: "i8x16 - false on hi", - shape: wazeroir.ShapeI8x16, - lo: 0xffff_00ff_ffff_ffff, - hi: 0x1111_1111_1111_1111, - exp: 0, - }, - { - name: "i16x8 - true", - shape: wazeroir.ShapeI16x8, - lo: 0x1000_0100_0010_0001, - hi: 0x0101_0101_0101_0101, - exp: 1, - }, - { - name: "i16x8 - false on hi", - shape: wazeroir.ShapeI16x8, - lo: 0x1000_0100_0010_0001, - hi: 0x1111_1111_0000_1111, - exp: 0, - }, - { - name: "i16x8 - false on lo", - shape: wazeroir.ShapeI16x8, - lo: 0xffff_0000_ffff_ffff, - hi: 0x1111_1111_1111_1111, - exp: 0, - }, - { - name: "i32x4 - true", - shape: wazeroir.ShapeI32x4, - lo: 0x1000_0000_0010_0000, - hi: 0x0000_0001_0000_1000, - exp: 1, - }, - { - name: "i32x4 - true", - shape: wazeroir.ShapeI32x4, - lo: 0x0000_1111_1111_0000, - hi: 0x0000_0001_1000_0000, - exp: 1, - }, - { - name: "i32x4 - false on lo", - shape: wazeroir.ShapeI32x4, - lo: 0x1111_1111_0000_0000, - hi: 0x1111_1111_1111_1111, - exp: 0, - }, - { - name: "i32x4 - false on lo", - shape: wazeroir.ShapeI32x4, - lo: 0x0000_0000_1111_1111, - hi: 0x1111_1111_1111_1111, - exp: 0, - }, - { - name: "i32x4 - false on hi", - shape: wazeroir.ShapeI32x4, - lo: 0x1111_1111_1111_1111, - hi: 0x1111_1111_0000_0000, - exp: 0, - }, - { - name: "i32x4 - false on hi", - shape: wazeroir.ShapeI32x4, - lo: 0x1111_1111_1111_1111, - hi: 0x0000_0000_1111_1111, - exp: 0, - }, - - { - name: "i64x2 - true", - shape: wazeroir.ShapeI64x2, - lo: 0x1000_0000_0000_0000, - hi: 0x0000_0001_0000_0000, - exp: 1, - }, - { - name: "i64x2 - true", - shape: wazeroir.ShapeI64x2, - lo: 0x0000_0000_0010_0000, - hi: 0x0000_0000_0000_0100, - exp: 1, - }, - { - name: "i64x2 - true", - shape: wazeroir.ShapeI64x2, - lo: 0x0000_0000_0000_1000, - hi: 0x1000_0000_0000_0000, - exp: 1, - }, - { - name: "i64x2 - false on lo", - shape: wazeroir.ShapeI64x2, - lo: 0, - hi: 0x1111_1111_1111_1111, - exp: 0, - }, - { - name: "i64x2 - false on hi", - shape: wazeroir.ShapeI64x2, - lo: 0x1111_1111_1111_1111, - hi: 0, - exp: 0, - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, - &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(tc.lo, tc.hi))) - require.NoError(t, err) - - err = compiler.compileV128AllTrue(operationPtr(wazeroir.NewOperationV128AllTrue(tc.shape))) - require.NoError(t, err) - - require.Equal(t, 0, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - require.Equal(t, nativeCallStatusCodeReturned, env.callEngine().statusCode) - require.Equal(t, uint64(1), env.stackPointer()) - require.Equal(t, tc.exp, env.stackTopAsUint32()) - }) - } -} - -func i8ToU8(v int8) byte { - return byte(v) -} - -func i16ToU16(v int16) uint16 { - return uint16(v) -} - -func i32ToU32(v int32) uint32 { - return uint32(v) -} - -func i64ToU64(v int64) uint64 { - return uint64(v) -} - -func TestCompiler_compileV128Swizzle(t *testing.T) { - tests := []struct { - name string - indexVec, baseVec [16]byte - expVec [16]byte - }{ - { - name: "1", - baseVec: [16]byte{16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31}, - indexVec: [16]byte{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}, - expVec: [16]byte{16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31}, - }, - { - name: "2", - baseVec: [16]byte{ - i8ToU8(-16), i8ToU8(-15), i8ToU8(-14), i8ToU8(-13), i8ToU8(-12), - i8ToU8(-11), i8ToU8(-10), i8ToU8(-9), i8ToU8(-8), i8ToU8(-7), i8ToU8(-6), i8ToU8(-5), - i8ToU8(-4), i8ToU8(-3), i8ToU8(-2), i8ToU8(-1), - }, - indexVec: [16]byte{ - i8ToU8(-8), i8ToU8(-7), i8ToU8(-6), i8ToU8(-5), i8ToU8(-4), - i8ToU8(-3), i8ToU8(-2), i8ToU8(-1), 16, 17, 18, 19, 20, 21, 22, 23, - }, - expVec: [16]byte{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, - }, - { - name: "3", - baseVec: [16]byte{100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115}, - indexVec: [16]byte{15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0}, - expVec: [16]byte{115, 114, 113, 112, 111, 110, 109, 108, 107, 106, 105, 104, 103, 102, 101, 100}, - }, - { - name: "4", - baseVec: [16]byte{100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115}, - indexVec: [16]byte{ - 9, 16, 10, 17, 11, 18, 12, 19, 13, 20, 14, 21, 15, 22, 16, 23, - }, - expVec: [16]byte{109, 0, 110, 0, 111, 0, 112, 0, 113, 0, 114, 0, 115, 0, 0, 0}, - }, - { - name: "5", - baseVec: [16]byte{0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70, 0x71, 0x72, 0x73}, - indexVec: [16]byte{9, 16, 10, 17, 11, 18, 12, 19, 13, 20, 14, 21, 15, 22, 16, 23}, - expVec: [16]byte{0x6d, 0, 0x6e, 0, 0x6f, 0, 0x70, 0, 0x71, 0, 0x72, 0, 0x73, 0, 0, 0}, - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, - &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.baseVec[:8]), binary.LittleEndian.Uint64(tc.baseVec[8:])))) - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.indexVec[:8]), binary.LittleEndian.Uint64(tc.indexVec[8:])))) - require.NoError(t, err) - - err = compiler.compileV128Swizzle(operationPtr(wazeroir.NewOperationV128Swizzle())) - require.NoError(t, err) - - requireRuntimeLocationStackPointerEqual(t, uint64(2), compiler) - require.Equal(t, 1, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - require.Equal(t, nativeCallStatusCodeReturned, env.callEngine().statusCode) - - lo, hi := env.stackTopAsV128() - var actual [16]byte - binary.LittleEndian.PutUint64(actual[:8], lo) - binary.LittleEndian.PutUint64(actual[8:], hi) - require.Equal(t, tc.expVec, actual) - }) - } -} - -func TestCompiler_compileV128Shuffle(t *testing.T) { - tests := []struct { - name string - lanes []uint64 - w, v, exp [16]byte - }{ - { - name: "v only", - lanes: []uint64{1, 1, 1, 1, 0, 0, 0, 0, 10, 10, 10, 10, 0, 0, 0, 0}, - v: [16]byte{0: 0xa, 1: 0xb, 10: 0xc}, - w: [16]byte{0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - exp: [16]byte{ - 0xb, 0xb, 0xb, 0xb, - 0xa, 0xa, 0xa, 0xa, - 0xc, 0xc, 0xc, 0xc, - 0xa, 0xa, 0xa, 0xa, - }, - }, - { - name: "w only", - lanes: []uint64{17, 17, 17, 17, 16, 16, 16, 16, 26, 26, 26, 26, 16, 16, 16, 16}, - v: [16]byte{0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - w: [16]byte{0: 0xa, 1: 0xb, 10: 0xc}, - exp: [16]byte{ - 0xb, 0xb, 0xb, 0xb, - 0xa, 0xa, 0xa, 0xa, - 0xc, 0xc, 0xc, 0xc, - 0xa, 0xa, 0xa, 0xa, - }, - }, - { - name: "mix", - lanes: []uint64{0, 17, 2, 19, 4, 21, 6, 23, 8, 25, 10, 27, 12, 29, 14, 31}, - v: [16]byte{ - 0x1, 0xff, 0x2, 0xff, 0x3, 0xff, 0x4, 0xff, - 0x5, 0xff, 0x6, 0xff, 0x7, 0xff, 0x8, 0xff, - }, - w: [16]byte{ - 0xff, 0x11, 0xff, 0x12, 0xff, 0x13, 0xff, 0x14, - 0xff, 0x15, 0xff, 0x16, 0xff, 0x17, 0xff, 0x18, - }, - exp: [16]byte{ - 0x1, 0x11, 0x2, 0x12, 0x3, 0x13, 0x4, 0x14, - 0x5, 0x15, 0x6, 0x16, 0x7, 0x17, 0x8, 0x18, - }, - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, - &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.v[:8]), binary.LittleEndian.Uint64(tc.v[8:])))) - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.w[:8]), binary.LittleEndian.Uint64(tc.w[8:])))) - require.NoError(t, err) - - err = compiler.compileV128Shuffle(operationPtr(wazeroir.NewOperationV128Shuffle(tc.lanes))) - require.NoError(t, err) - - requireRuntimeLocationStackPointerEqual(t, uint64(2), compiler) - require.Equal(t, 1, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - lo, hi := env.stackTopAsV128() - var actual [16]byte - binary.LittleEndian.PutUint64(actual[:8], lo) - binary.LittleEndian.PutUint64(actual[8:], hi) - require.Equal(t, tc.exp, actual) - }) - } -} - -func TestCompiler_compileV128Bitmask(t *testing.T) { - u16x8 := func(u1, u2, u3, u4, u5, u6, u7, u8 uint16) (ret [16]byte) { - binary.LittleEndian.PutUint16(ret[0:], u1) - binary.LittleEndian.PutUint16(ret[2:], u2) - binary.LittleEndian.PutUint16(ret[4:], u3) - binary.LittleEndian.PutUint16(ret[6:], u4) - binary.LittleEndian.PutUint16(ret[8:], u5) - binary.LittleEndian.PutUint16(ret[10:], u6) - binary.LittleEndian.PutUint16(ret[12:], u7) - binary.LittleEndian.PutUint16(ret[14:], u8) - return - } - u32x4 := func(u1, u2, u3, u4 uint32) (ret [16]byte) { - binary.LittleEndian.PutUint32(ret[0:], u1) - binary.LittleEndian.PutUint32(ret[4:], u2) - binary.LittleEndian.PutUint32(ret[8:], u3) - binary.LittleEndian.PutUint32(ret[12:], u4) - return - } - u64x2 := func(u1, u2 uint64) (ret [16]byte) { - binary.LittleEndian.PutUint64(ret[0:], u1) - binary.LittleEndian.PutUint64(ret[8:], u2) - return - } - - tests := []struct { - name string - shape wazeroir.Shape - v [16]byte - exp uint32 - }{ - { - name: wasm.OpcodeVecI8x16BitMaskName, - v: [16]byte{ - i8ToU8(-1), 1, i8ToU8(-1), 1, i8ToU8(-1), 1, i8ToU8(-1), 1, - i8ToU8(-1), 1, i8ToU8(-1), 1, i8ToU8(-1), 1, i8ToU8(-1), 1, - }, - shape: wazeroir.ShapeI8x16, - exp: 0b0101_0101_0101_0101, - }, - { - name: wasm.OpcodeVecI8x16BitMaskName, - v: [16]byte{ - i8ToU8(-1), 1, i8ToU8(-1), 1, i8ToU8(-1), 1, i8ToU8(-1), 1, - 0, 0, 0, 0, 0, 0, 0, 0, - }, - shape: wazeroir.ShapeI8x16, - exp: 0b0000_0000_0101_0101, - }, - { - name: wasm.OpcodeVecI8x16BitMaskName, - v: [16]byte{ - 0, 0, 0, 0, 0, 0, 0, 0, - i8ToU8(-1), 1, i8ToU8(-1), 1, i8ToU8(-1), 1, i8ToU8(-1), 1, - }, - shape: wazeroir.ShapeI8x16, - exp: 0b0101_0101_0000_0000, - }, - { - name: wasm.OpcodeVecI16x8BitMaskName, - v: u16x8(0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff), - shape: wazeroir.ShapeI16x8, - exp: 0b1111_1111, - }, - { - name: wasm.OpcodeVecI16x8BitMaskName, - v: u16x8(0, 0xffff, 0, 0xffff, 0, 0xffff, 0, 0xffff), - shape: wazeroir.ShapeI16x8, - exp: 0b1010_1010, - }, - { - name: wasm.OpcodeVecI32x4BitMaskName, - v: u32x4(0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff), - shape: wazeroir.ShapeI32x4, - exp: 0b1111, - }, - { - name: wasm.OpcodeVecI32x4BitMaskName, - v: u32x4(0, 0xffffffff, 0xffffffff, 0), - shape: wazeroir.ShapeI32x4, - exp: 0b0110, - }, - { - name: wasm.OpcodeVecI64x2BitMaskName, - v: u64x2(0, 0xffffffffffffffff), - shape: wazeroir.ShapeI64x2, - exp: 0b10, - }, - { - name: wasm.OpcodeVecI64x2BitMaskName, - v: u64x2(0xffffffffffffffff, 0xffffffffffffffff), - shape: wazeroir.ShapeI64x2, - exp: 0b11, - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, - &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.v[:8]), binary.LittleEndian.Uint64(tc.v[8:])))) - require.NoError(t, err) - - err = compiler.compileV128BitMask(operationPtr(wazeroir.NewOperationV128BitMask(tc.shape))) - require.NoError(t, err) - - requireRuntimeLocationStackPointerEqual(t, uint64(1), compiler) - require.Equal(t, 1, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - actual := env.stackTopAsUint32() - require.Equal(t, tc.exp, actual) - }) - } -} - -func TestCompiler_compileV128_Not(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, - &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - var originalLo, originalHi uint64 = 0xffff_0000_ffff_0000, 0x0000_ffff_0000_ffff - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(originalLo, originalHi))) - require.NoError(t, err) - - err = compiler.compileV128Not(operationPtr(wazeroir.NewOperationV128Not())) - require.NoError(t, err) - - requireRuntimeLocationStackPointerEqual(t, uint64(2), compiler) - require.Equal(t, 1, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - lo, hi := env.stackTopAsV128() - require.Equal(t, ^originalLo, lo) - require.Equal(t, ^originalHi, hi) -} - -func TestCompiler_compileV128_And_Or_Xor_AndNot(t *testing.T) { - tests := []struct { - name string - op wazeroir.OperationKind - x1, x2, exp [16]byte - }{ - { - name: "AND", - op: wazeroir.OperationKindV128And, - x1: [16]byte{ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - }, - x2: [16]byte{}, - exp: [16]byte{}, - }, - { - name: "AND", - op: wazeroir.OperationKindV128And, - x2: [16]byte{ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - }, - x1: [16]byte{}, - exp: [16]byte{}, - }, - { - name: "AND", - op: wazeroir.OperationKindV128And, - x2: [16]byte{ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - }, - x1: [16]byte{0: 0x1, 5: 0x1, 15: 0x1}, - exp: [16]byte{0: 0x1, 5: 0x1, 15: 0x1}, - }, - { - name: "OR", - op: wazeroir.OperationKindV128Or, - x1: [16]byte{ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - }, - x2: [16]byte{}, - exp: [16]byte{ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - }, - }, - { - name: "OR", - op: wazeroir.OperationKindV128Or, - x2: [16]byte{ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - }, - x1: [16]byte{}, - exp: [16]byte{ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - }, - }, - { - name: "OR", - op: wazeroir.OperationKindV128Or, - x2: [16]byte{}, - x1: [16]byte{0: 0x1, 5: 0x1, 15: 0x1}, - exp: [16]byte{0: 0x1, 5: 0x1, 15: 0x1}, - }, - { - name: "OR", - op: wazeroir.OperationKindV128Or, - x2: [16]byte{8: 0x1, 10: 0x1}, - x1: [16]byte{0: 0x1}, - exp: [16]byte{0: 0x1, 8: 0x1, 10: 0x1}, - }, - { - name: "XOR", - op: wazeroir.OperationKindV128Xor, - x1: [16]byte{ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - }, - x2: [16]byte{}, - exp: [16]byte{ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - }, - }, - { - name: "XOR", - op: wazeroir.OperationKindV128Xor, - x2: [16]byte{ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - }, - x1: [16]byte{}, - exp: [16]byte{ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - }, - }, - { - name: "XOR", - op: wazeroir.OperationKindV128Xor, - x2: [16]byte{ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - }, - x1: [16]byte{ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - }, - exp: [16]byte{}, - }, - { - name: "XOR", - op: wazeroir.OperationKindV128Xor, - x2: [16]byte{ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - }, - x1: [16]byte{0: 0x1, 15: 0x2}, - exp: [16]byte{ - 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, - }, - }, - - { - name: "AndNot", - op: wazeroir.OperationKindV128AndNot, - x2: [16]byte{}, - x1: [16]byte{ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - }, - exp: [16]byte{ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - }, - }, - { - name: "AndNot", - op: wazeroir.OperationKindV128AndNot, - x2: [16]byte{ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - }, - x1: [16]byte{}, - exp: [16]byte{}, - }, - { - name: "AndNot", - op: wazeroir.OperationKindV128AndNot, - x2: [16]byte{ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - }, - x1: [16]byte{ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - }, - exp: [16]byte{}, - }, - { - name: "AndNot", - op: wazeroir.OperationKindV128AndNot, - x2: [16]byte{ - 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, - }, - x1: [16]byte{0: 0x1, 15: 0x2}, - exp: [16]byte{0: 0x1, 15: 0x2}, - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, - &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.x1[:8]), binary.LittleEndian.Uint64(tc.x1[8:])))) - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.x2[:8]), binary.LittleEndian.Uint64(tc.x2[8:])))) - require.NoError(t, err) - - switch tc.op { - case wazeroir.OperationKindV128And: - err = compiler.compileV128And(operationPtr(wazeroir.NewOperationV128And())) - case wazeroir.OperationKindV128Or: - err = compiler.compileV128Or(operationPtr(wazeroir.NewOperationV128Or())) - case wazeroir.OperationKindV128Xor: - err = compiler.compileV128Xor(operationPtr(wazeroir.NewOperationV128Xor())) - case wazeroir.OperationKindV128AndNot: - err = compiler.compileV128AndNot(operationPtr(wazeroir.NewOperationV128AndNot())) - } - require.NoError(t, err) - - requireRuntimeLocationStackPointerEqual(t, uint64(2), compiler) - require.Equal(t, 1, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - lo, hi := env.stackTopAsV128() - var actual [16]byte - binary.LittleEndian.PutUint64(actual[:8], lo) - binary.LittleEndian.PutUint64(actual[8:], hi) - require.Equal(t, tc.exp, actual) - }) - } -} - -func TestCompiler_compileV128Bitselect(t *testing.T) { - tests := []struct { - name string - selector, x1, x2, exp [16]byte - }{ - { - name: "all x1", - selector: [16]byte{ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - }, - x1: [16]byte{1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}, - x2: [16]byte{2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2}, - exp: [16]byte{1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}, - }, - { - name: "all x2", - selector: [16]byte{}, - x1: [16]byte{1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}, - x2: [16]byte{2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2}, - exp: [16]byte{2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2}, - }, - { - name: "mix", - selector: [16]byte{ - 0b1111_0000, 0b1111_0000, 0b1111_0000, 0b1111_0000, 0b1111_0000, 0b1111_0000, 0b1111_0000, 0b1111_0000, - 0b0000_0000, 0b0000_0000, 0b0000_0000, 0b0000_0000, 0b1111_1111, 0b1111_1111, 0b1111_1111, 0b1111_1111, - }, - x1: [16]byte{ - 0b1010_1010, 0b1010_1010, 0b1010_1010, 0b1010_1010, 0b1010_1010, 0b1010_1010, 0b1010_1010, 0b1010_1010, - 0b1010_1010, 0b1010_1010, 0b1010_1010, 0b1010_1010, 0b1010_1010, 0b1010_1010, 0b1010_1010, 0b1010_1010, - }, - x2: [16]byte{ - 0b0101_0101, 0b0101_0101, 0b0101_0101, 0b0101_0101, 0b0101_0101, 0b0101_0101, 0b0101_0101, 0b0101_0101, - 0b0101_0101, 0b0101_0101, 0b0101_0101, 0b0101_0101, 0b0101_0101, 0b0101_0101, 0b0101_0101, 0b0101_0101, - }, - exp: [16]byte{ - 0b1010_0101, 0b1010_0101, 0b1010_0101, 0b1010_0101, 0b1010_0101, 0b1010_0101, 0b1010_0101, 0b1010_0101, - 0b0101_0101, 0b0101_0101, 0b0101_0101, 0b0101_0101, 0b1010_1010, 0b1010_1010, 0b1010_1010, 0b1010_1010, - }, - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, - &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.x1[:8]), binary.LittleEndian.Uint64(tc.x1[8:])))) - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.x2[:8]), binary.LittleEndian.Uint64(tc.x2[8:])))) - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.selector[:8]), binary.LittleEndian.Uint64(tc.selector[8:])))) - require.NoError(t, err) - - err = compiler.compileV128Bitselect(operationPtr(wazeroir.NewOperationV128Bitselect())) - require.NoError(t, err) - - requireRuntimeLocationStackPointerEqual(t, uint64(2), compiler) - require.Equal(t, 1, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - lo, hi := env.stackTopAsV128() - var actual [16]byte - binary.LittleEndian.PutUint64(actual[:8], lo) - binary.LittleEndian.PutUint64(actual[8:], hi) - require.Equal(t, tc.exp, actual) - }) - } -} - -func TestCompiler_compileV128Shl(t *testing.T) { - tests := []struct { - name string - shape wazeroir.Shape - s uint32 - x, exp [16]byte - }{ - { - name: "i8x16/shift=0", - shape: wazeroir.ShapeI8x16, - x: [16]byte{ - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - }, - exp: [16]byte{ - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - }, - s: 0, - }, - { - name: "i8x16/shift=1", - shape: wazeroir.ShapeI8x16, - x: [16]byte{ - 1, 0xff, 1, 0xff, 1, 0xff, 1, 0xff, - 1, 0xff, 1, 0xff, 1, 0xff, 1, 0xff, - }, - exp: [16]byte{ - 2, 0xfe, 2, 0xfe, 2, 0xfe, 2, 0xfe, - 2, 0xfe, 2, 0xfe, 2, 0xfe, 2, 0xfe, - }, - s: 1, - }, - { - name: "i8x16/shift=2", - shape: wazeroir.ShapeI8x16, - x: [16]byte{ - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - }, - exp: [16]byte{ - 4, 0, 4, 0, 4, 0, 4, 0, - 4, 0, 4, 0, 4, 0, 4, 0, - }, - s: 2, - }, - { - name: "i8x16/shift=3", - shape: wazeroir.ShapeI8x16, - x: [16]byte{ - 1, 0xff, 1, 0xff, 1, 0xff, 1, 0xff, - 1, 0xff, 1, 0xff, 1, 0xff, 1, 0xff, - }, - exp: [16]byte{ - 8, 0xff & ^0b111, 8, 0xff & ^0b111, 8, 0xff & ^0b111, 8, 0xff & ^0b111, - 8, 0xff & ^0b111, 8, 0xff & ^0b111, 8, 0xff & ^0b111, 8, 0xff & ^0b111, - }, - s: 3, - }, - { - name: "i8x16/shift=4", - shape: wazeroir.ShapeI8x16, - x: [16]byte{ - 0xff, 1, 0xff, 1, 0xff, 1, 0xff, 1, - 0xff, 1, 0xff, 1, 0xff, 1, 0xff, 1, - }, - exp: [16]byte{ - 0xff & ^0b1111, 16, 0xff & ^0b1111, 16, 0xff & ^0b1111, 16, 0xff & ^0b1111, 16, - 0xff & ^0b1111, 16, 0xff & ^0b1111, 16, 0xff & ^0b1111, 16, 0xff & ^0b1111, 16, - }, - s: 4, - }, - { - name: "i8x16/shift=5", - shape: wazeroir.ShapeI8x16, - x: [16]byte{ - 0xff, 0xff, 0xff, 0xff, 1, 1, 1, 1, - 0xff, 0xff, 0xff, 0xff, 1, 1, 1, 1, - }, - exp: [16]byte{ - 0xff & ^0b11111, 0xff & ^0b11111, 0xff & ^0b11111, 0xff & ^0b11111, 32, 32, 32, 32, - 0xff & ^0b11111, 0xff & ^0b11111, 0xff & ^0b11111, 0xff & ^0b11111, 32, 32, 32, 32, - }, - s: 5, - }, - { - name: "i8x16/shift=6", - shape: wazeroir.ShapeI8x16, - x: [16]byte{ - 0xff, 0x81, 0xff, 0x81, 0xff, 0x81, 0xff, 0x81, - 0xff, 0x81, 0xff, 0x81, 0xff, 0x81, 0xff, 0x81, - }, - exp: [16]byte{ - 0xc0, 1 << 6, 0xc0, 1 << 6, 0xc0, 1 << 6, 0xc0, 1 << 6, - 0xc0, 1 << 6, 0xc0, 1 << 6, 0xc0, 1 << 6, 0xc0, 1 << 6, - }, - s: 6, - }, - { - name: "i8x16/shift=7", - shape: wazeroir.ShapeI8x16, - x: [16]byte{ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - }, - exp: [16]byte{ - 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, - 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, - }, - s: 7, - }, - { - name: "i16x8/shift=0", - shape: wazeroir.ShapeI16x8, - x: [16]byte{ - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - }, - exp: [16]byte{ - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - }, - s: 0, - }, - { - name: "i16x8/shift=1", - shape: wazeroir.ShapeI16x8, - x: [16]byte{ - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - }, - exp: [16]byte{ - 2, 0, 2, 0, 2, 0, 2, 0, - 2, 0, 2, 0, 2, 0, 2, 0, - }, - s: 1, - }, - { - name: "i16x8/shift=7", - shape: wazeroir.ShapeI16x8, - x: [16]byte{ - 1, 1, 1, 1, 0x80, 0x80, 0x80, 0x80, - 0, 0x80, 0, 0x80, 0b11, 0b11, 0b11, 0b11, - }, - exp: [16]byte{ - 0, 1, 0, 1, 0, 0x80, 0, 0x80, - 0, 0, 0, 0, 0, 0b11, 0, 0b11, - }, - s: 8, - }, - { - name: "i16x8/shift=15", - shape: wazeroir.ShapeI16x8, - x: [16]byte{ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - }, - exp: [16]byte{ - 0, 0x80, 0, 0x80, 0, 0x80, 0, 0x80, - 0, 0x80, 0, 0x80, 0, 0x80, 0, 0x80, - }, - s: 15, - }, - { - name: "i32x4/shift=0", - shape: wazeroir.ShapeI32x4, - x: [16]byte{ - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - }, - exp: [16]byte{ - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - }, - s: 0, - }, - { - name: "i32x4/shift=1", - shape: wazeroir.ShapeI32x4, - x: [16]byte{ - 1, 0x80, 0, 0x80, 1, 0x80, 0, 0x80, - 1, 0x80, 0, 0x80, 1, 0x80, 0, 0x80, - }, - exp: [16]byte{ - 2, 0, 1, 0, 2, 0, 1, 0, - 2, 0, 1, 0, 2, 0, 1, 0, - }, - s: 1, - }, - { - name: "i32x4/shift=31", - shape: wazeroir.ShapeI32x4, - x: [16]byte{ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - }, - exp: [16]byte{ - 0, 0, 0, 0x80, 0, 0, 0, 0x80, - 0, 0, 0, 0x80, 0, 0, 0, 0x80, - }, - s: 31, - }, - { - name: "i64x2/shift=0", - shape: wazeroir.ShapeI64x2, - x: [16]byte{ - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - }, - exp: [16]byte{ - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - }, - s: 0, - }, - { - name: "i64x2/shift=5", - shape: wazeroir.ShapeI64x2, - x: [16]byte{ - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - }, - exp: [16]byte{ - 1 << 5, 0, 1<<4 | 1<<5, 0, 1<<4 | 1<<5, 0, 1<<4 | 1<<5, 0, - 1 << 5, 0, 1<<4 | 1<<5, 0, 1<<4 | 1<<5, 0, 1<<4 | 1<<5, 0, - }, - s: 5, - }, - { - name: "i64x2/shift=63", - shape: wazeroir.ShapeI64x2, - x: [16]byte{ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - }, - exp: [16]byte{ - 0, 0, 0, 0, 0, 0, 0, 0x80, - 0, 0, 0, 0, 0, 0, 0, 0x80, - }, - s: 63, - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, - &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.x[:8]), binary.LittleEndian.Uint64(tc.x[8:])))) - require.NoError(t, err) - - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(tc.s))) - require.NoError(t, err) - - err = compiler.compileV128Shl(operationPtr(wazeroir.NewOperationV128Shl(tc.shape))) - require.NoError(t, err) - - requireRuntimeLocationStackPointerEqual(t, uint64(2), compiler) - require.Equal(t, 1, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - lo, hi := env.stackTopAsV128() - var actual [16]byte - binary.LittleEndian.PutUint64(actual[:8], lo) - binary.LittleEndian.PutUint64(actual[8:], hi) - require.Equal(t, tc.exp, actual) - }) - } -} - -func TestCompiler_compileV128Shr(t *testing.T) { - tests := []struct { - name string - signed bool - shape wazeroir.Shape - s uint32 - x, exp [16]byte - }{ - { - name: "i8x16/shift=0/signed=false", - shape: wazeroir.ShapeI8x16, - x: [16]byte{ - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - }, - exp: [16]byte{ - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - }, - s: 0, - signed: false, - }, - { - name: "i8x16/shift=7/signed=false", - shape: wazeroir.ShapeI8x16, - x: [16]byte{ - 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, - 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, - }, - exp: [16]byte{ - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - }, - s: 7, - signed: false, - }, - { - name: "i8x16/shift=0/signed=false", - shape: wazeroir.ShapeI8x16, - x: [16]byte{ - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - }, - exp: [16]byte{ - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - }, - s: 0, - signed: true, - }, - { - name: "i8x16/shift=7/signed=false", - shape: wazeroir.ShapeI8x16, - x: [16]byte{ - 1, 0x80, 0x7e, 0x80, 1, 0x80, 0x7e, 0x80, - 1, 0x80, 0x7e, 0x80, 1, 0x80, 0x7e, 0x80, - }, - exp: [16]byte{ - 0, 0xff, 0, 0xff, 0, 0xff, 0, 0xff, - 0, 0xff, 0, 0xff, 0, 0xff, 0, 0xff, - }, - s: 7, - signed: true, - }, - { - name: "i16x8/shift=0/signed=false", - shape: wazeroir.ShapeI16x8, - x: [16]byte{ - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - }, - exp: [16]byte{ - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - }, - s: 0, - signed: false, - }, - { - name: "i16x8/shift=8/signed=false", - shape: wazeroir.ShapeI16x8, - x: [16]byte{ - 0xff, 0x80, 0xff, 0x80, 0xff, 0x80, 0xff, 0x80, - 0xff, 0x80, 0xff, 0x80, 0xff, 0x80, 0xff, 0x80, - }, - exp: [16]byte{ - 0x80, 0, 0x80, 0, 0x80, 0, 0x80, 0, - 0x80, 0, 0x80, 0, 0x80, 0, 0x80, 0, - }, - s: 8, - signed: false, - }, - { - name: "i16x8/shift=0/signed=true", - shape: wazeroir.ShapeI16x8, - x: [16]byte{ - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - }, - exp: [16]byte{ - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - }, - s: 0, - signed: true, - }, - { - name: "i16x8/shift=8/signed=true", - shape: wazeroir.ShapeI16x8, - x: [16]byte{ - 0xff, 0x80, 0xff, 0x80, 0xff, 0x80, 0xff, 0x80, - 0xff, 0x80, 0xff, 0x80, 0xff, 0x80, 0xff, 0x80, - }, - exp: [16]byte{ - 0x80, 0xff, 0x80, 0xff, 0x80, 0xff, 0x80, 0xff, - 0x80, 0xff, 0x80, 0xff, 0x80, 0xff, 0x80, 0xff, - }, - s: 8, - signed: true, - }, - { - name: "i32x4/shift=0/signed=false", - shape: wazeroir.ShapeI32x4, - x: [16]byte{ - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - }, - exp: [16]byte{ - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - }, - s: 0, - signed: false, - }, - { - name: "i32x4/shift=16/signed=false", - shape: wazeroir.ShapeI32x4, - x: [16]byte{ - 0, 0, 0, 0x80, 0, 0, 0, 0x80, - 0, 0, 0, 0x80, 0, 0, 0, 0x80, - }, - exp: [16]byte{ - 0, 0x80, 0, 0, 0, 0x80, 0, 0, - 0, 0x80, 0, 0, 0, 0x80, 0, 0, - }, - s: 16, - signed: false, - }, - { - name: "i32x4/shift=0/signed=true", - shape: wazeroir.ShapeI32x4, - x: [16]byte{ - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - }, - exp: [16]byte{ - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - }, - s: 0, - signed: true, - }, - { - name: "i32x4/shift=16/signed=true", - shape: wazeroir.ShapeI32x4, - x: [16]byte{ - 0, 0, 0, 0x80, 0, 0, 0, 0x80, - 0, 0, 0, 0x80, 0, 0, 0, 0x80, - }, - exp: [16]byte{ - 0, 0x80, 0xff, 0xff, 0, 0x80, 0xff, 0xff, - 0, 0x80, 0xff, 0xff, 0, 0x80, 0xff, 0xff, - }, - s: 16, - signed: true, - }, - { - name: "i64x2/shift=0/signed=false", - shape: wazeroir.ShapeI32x4, - x: [16]byte{ - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - }, - exp: [16]byte{ - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - }, - s: 0, - signed: false, - }, - { - name: "i64x2/shift=16/signed=false", - shape: wazeroir.ShapeI64x2, - x: [16]byte{ - 0, 0, 0, 0x80, 0, 0, 0, 0x80, - 0, 0, 0, 0x80, 0, 0, 0, 0x80, - }, - exp: [16]byte{ - 0, 0x80, 0, 0, 0, 0x80, 0, 0, - 0, 0x80, 0, 0, 0, 0x80, 0, 0, - }, - s: 16, - signed: false, - }, - { - name: "i64x2/shift=0/signed=true", - shape: wazeroir.ShapeI64x2, - x: [16]byte{ - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - }, - exp: [16]byte{ - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - 1, 0x80, 1, 0x80, 1, 0x80, 1, 0x80, - }, - s: 0, - signed: true, - }, - { - name: "i64x2/shift=16/signed=true", - shape: wazeroir.ShapeI64x2, - x: [16]byte{ - 0, 0, 0, 0x80, 0, 0, 0, 0x80, - 0, 0, 0, 0x80, 0, 0, 0, 0x80, - }, - exp: [16]byte{ - 0, 0x80, 0, 0, 0, 0x80, 0xff, 0xff, - 0, 0x80, 0, 0, 0, 0x80, 0xff, 0xff, - }, - s: 16, - signed: true, - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, - &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.x[:8]), binary.LittleEndian.Uint64(tc.x[8:])))) - require.NoError(t, err) - - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(tc.s))) - require.NoError(t, err) - - err = compiler.compileV128Shr(operationPtr(wazeroir.NewOperationV128Shr(tc.shape, tc.signed))) - require.NoError(t, err) - - requireRuntimeLocationStackPointerEqual(t, uint64(2), compiler) - require.Equal(t, 1, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - lo, hi := env.stackTopAsV128() - var actual [16]byte - binary.LittleEndian.PutUint64(actual[:8], lo) - binary.LittleEndian.PutUint64(actual[8:], hi) - require.Equal(t, tc.exp, actual) - }) - } -} - -func i16x8(i1, i2, i3, i4, i5, i6, i7, i8 uint16) (ret [16]byte) { - binary.LittleEndian.PutUint16(ret[0:], i1) - binary.LittleEndian.PutUint16(ret[2:], i2) - binary.LittleEndian.PutUint16(ret[4:], i3) - binary.LittleEndian.PutUint16(ret[6:], i4) - binary.LittleEndian.PutUint16(ret[8:], i5) - binary.LittleEndian.PutUint16(ret[10:], i6) - binary.LittleEndian.PutUint16(ret[12:], i7) - binary.LittleEndian.PutUint16(ret[14:], i8) - return -} - -func i32x4(i1, i2, i3, i4 uint32) (ret [16]byte) { - binary.LittleEndian.PutUint32(ret[0:], i1) - binary.LittleEndian.PutUint32(ret[4:], i2) - binary.LittleEndian.PutUint32(ret[8:], i3) - binary.LittleEndian.PutUint32(ret[12:], i4) - return -} - -func f32x4(f1, f2, f3, f4 float32) (ret [16]byte) { - binary.LittleEndian.PutUint32(ret[0:], math.Float32bits(f1)) - binary.LittleEndian.PutUint32(ret[4:], math.Float32bits(f2)) - binary.LittleEndian.PutUint32(ret[8:], math.Float32bits(f3)) - binary.LittleEndian.PutUint32(ret[12:], math.Float32bits(f4)) - return -} - -func i64x2(i1, i2 uint64) (ret [16]byte) { - binary.LittleEndian.PutUint64(ret[0:], i1) - binary.LittleEndian.PutUint64(ret[8:], i2) - return -} - -func f64x2(f1, f2 float64) (ret [16]byte) { - binary.LittleEndian.PutUint64(ret[0:], math.Float64bits(f1)) - binary.LittleEndian.PutUint64(ret[8:], math.Float64bits(f2)) - return -} - -func TestCompiler_compileV128Cmp(t *testing.T) { - tests := []struct { - name string - cmpType wazeroir.V128CmpType - x1, x2, exp [16]byte - }{ - { - name: "f32x4 eq", - cmpType: wazeroir.V128CmpTypeF32x4Eq, - x1: f32x4(1.0, -123.123, 0, 3214231), - x2: f32x4(0, 0, 0, 0), - exp: [16]byte{0, 0, 0, 0, 0, 0, 0, 0, 0xff, 0xff, 0xff, 0xff, 0, 0, 0, 0}, - }, - { - name: "f32x4 ne", - cmpType: wazeroir.V128CmpTypeF32x4Ne, - x1: f32x4(1.0, -123.123, 123, 3214231), - x2: f32x4(2.0, 213123123.1231, 123, 0), - exp: [16]byte{0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0, 0, 0, 0, 0xff, 0xff, 0xff, 0xff}, - }, - { - name: "f32x4 lt", - cmpType: wazeroir.V128CmpTypeF32x4Lt, - x1: f32x4(2.0, -123.123, 1234, 3214231), - x2: f32x4(2.0, 213123123.1231, 123, 0), - exp: [16]byte{0, 0, 0, 0, 0xff, 0xff, 0xff, 0xff, 0, 0, 0, 0, 0, 0, 0, 0}, - }, - { - name: "f32x4 le", - cmpType: wazeroir.V128CmpTypeF32x4Le, - x1: f32x4(2.0, -123.123, 1234, 3214231), - x2: f32x4(2.0, 213123123.1231, 123, 0), - exp: [16]byte{0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0, 0, 0, 0, 0, 0, 0, 0}, - }, - { - name: "f32x4 gt", - cmpType: wazeroir.V128CmpTypeF32x4Gt, - x1: f32x4(2.0, -123.123, 1234, 3214231), - x2: f32x4(2.0, 213123123.1231, 123, 0), - exp: [16]byte{0, 0, 0, 0, 0, 0, 0, 0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - }, - { - name: "f32x4 ge", - cmpType: wazeroir.V128CmpTypeF32x4Ge, - x1: f32x4(2.0, -123.123, 1234, 3214231), - x2: f32x4(2.0, 213123123.1231, 123, 0), - exp: [16]byte{0xff, 0xff, 0xff, 0xff, 0, 0, 0, 0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - }, - { - name: "f64x2 eq", - cmpType: wazeroir.V128CmpTypeF64x2Eq, - x1: f64x2(1.0, -123.12412), - x2: f64x2(1.0, 123.123124), - exp: [16]byte{0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0, 0, 0, 0, 0, 0, 0, 0}, - }, - { - name: "f64x2 ne", - cmpType: wazeroir.V128CmpTypeF64x2Ne, - x1: f64x2(1.0, -123.12412), - x2: f64x2(1.0, 123.123124), - exp: [16]byte{0, 0, 0, 0, 0, 0, 0, 0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - }, - { - name: "f64x2 lt", - cmpType: wazeroir.V128CmpTypeF64x2Lt, - x1: f64x2(-123, math.Inf(-1)), - x2: f64x2(-123, -1234515), - exp: [16]byte{0, 0, 0, 0, 0, 0, 0, 0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - }, - { - name: "f64x2 le", - cmpType: wazeroir.V128CmpTypeF64x2Le, - x1: f64x2(-123, 123), - x2: f64x2(-123, math.MaxFloat64), - exp: [16]byte{0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - }, - { - name: "f64x2 gt", - cmpType: wazeroir.V128CmpTypeF64x2Gt, - x1: f64x2(math.MaxFloat64, -123.0), - x2: f64x2(123, -123.0), - exp: [16]byte{ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0, 0, 0, 0, 0, 0, 0, 0, - }, - }, - { - name: "f64x2 ge", - cmpType: wazeroir.V128CmpTypeF64x2Ge, - x1: f64x2(math.MaxFloat64, -123.0), - x2: f64x2(123, -123.0), - exp: [16]byte{ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - }, - }, - { - name: "i8x16 eq", - cmpType: wazeroir.V128CmpTypeI8x16Eq, - x1: [16]byte{0, 1, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1}, - x2: [16]byte{1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 0}, - exp: [16]byte{0, 0xff, 0, 0xff, 0xff, 0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0, 0xff, 0xff, 0}, - }, - { - name: "i8x16 ne", - cmpType: wazeroir.V128CmpTypeI8x16Ne, - x1: [16]byte{0, 1, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1}, - x2: [16]byte{1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 0}, - exp: [16]byte{0xff, 0, 0xff, 0, 0, 0xff, 0, 0, 0, 0, 0, 0, 0xff, 0, 0, 0xff}, - }, - { - name: "i8x16 lt_s", - cmpType: wazeroir.V128CmpTypeI8x16LtS, - x1: [16]byte{0: i8ToU8(-1), 15: 0}, - x2: [16]byte{0: 0x7f, 15: i8ToU8(-1)}, - exp: [16]byte{0: 0xff}, - }, - { - name: "i8x16 lt_u", - cmpType: wazeroir.V128CmpTypeI8x16LtU, - x1: [16]byte{0: 0xff, 15: 0}, - x2: [16]byte{0: 0x7f, 15: 0xff}, - exp: [16]byte{15: 0xff}, - }, - { - name: "i8x16 gt_s", - cmpType: wazeroir.V128CmpTypeI8x16GtS, - x1: [16]byte{0: i8ToU8(-1), 15: 0}, - x2: [16]byte{0: 0x7f, 15: i8ToU8(-1)}, - exp: [16]byte{15: 0xff}, - }, - { - name: "i8x16 gt_u", - cmpType: wazeroir.V128CmpTypeI8x16GtU, - x1: [16]byte{0: 0xff, 15: 0}, - x2: [16]byte{0: 0x7f, 15: 0xff}, - exp: [16]byte{0: 0xff}, - }, - { - name: "i8x16 le_s", - cmpType: wazeroir.V128CmpTypeI8x16LeS, - x1: [16]byte{i8ToU8(-1), 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, i8ToU8(-1)}, - x2: [16]byte{0: 0x7f, 15: i8ToU8(-1)}, - exp: [16]byte{0: 0xff, 15: 0xff}, - }, - { - name: "i8x16 le_u", - cmpType: wazeroir.V128CmpTypeI8x16LeU, - x1: [16]byte{0x80, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0xff}, - x2: [16]byte{0: 0x7f, 5: 0x1, 15: 0xff}, - exp: [16]byte{5: 0xff, 15: 0xff}, - }, - { - name: "i8x16 ge_s", - cmpType: wazeroir.V128CmpTypeI8x16GeS, - x1: [16]byte{0: 0x7f, 15: i8ToU8(-1)}, - x2: [16]byte{i8ToU8(-1), 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, i8ToU8(-1)}, - exp: [16]byte{0: 0xff, 15: 0xff}, - }, - { - name: "i8x16 ge_u", - cmpType: wazeroir.V128CmpTypeI8x16GeU, - x1: [16]byte{0: 0x7f, 3: 0xe, 15: 0xff}, - x2: [16]byte{0xff, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0xff}, - exp: [16]byte{3: 0xff, 15: 0xff}, - }, - { - name: "i16x8 eq", - cmpType: wazeroir.V128CmpTypeI16x8Eq, - x1: i16x8(0, 1, 0, 1, 0, 1, 0, 1), - x2: i16x8(0, 0, 0, 1, 1, 1, 0, 0), - exp: i16x8(0xffff, 0, 0xffff, 0xffff, 0, 0xffff, 0xffff, 0), - }, - { - name: "i8x16 ne", - cmpType: wazeroir.V128CmpTypeI16x8Ne, - x1: i16x8(0, 1, 0, 1, 0, 1, 0, 1), - x2: i16x8(0, 0, 0, 1, 1, 1, 0, 0), - exp: i16x8(0, 0xffff, 0, 0, 0xffff, 0, 0, 0xffff), - }, - { - name: "i8x16 lt_s", - cmpType: wazeroir.V128CmpTypeI16x8LtS, - x1: i16x8(0xffff, 1, 0, 1, 0, 1, 0, 1), - x2: i16x8(0, 0, 0, 1, 1, 1, 0, 0), - exp: i16x8(0xffff, 0, 0, 0, 0xffff, 0, 0, 0), - }, - { - name: "i8x16 lt_u", - cmpType: wazeroir.V128CmpTypeI16x8LtU, - x1: i16x8(0xffff, 1, 0, 1, 0, 1, 0, 1), - x2: i16x8(0, 0, 0, 1, 1, 1, 0, 0), - exp: i16x8(0, 0, 0, 0, 0xffff, 0, 0, 0), - }, - { - name: "i8x16 gt_s", - cmpType: wazeroir.V128CmpTypeI16x8GtS, - x1: i16x8(0, 1, 0, 1, 0, 1, 0, 1), - x2: i16x8(0xffff, 0, 0, 1, 1, 1, 0, 0), - exp: i16x8(0xffff, 0xffff, 0, 0, 0, 0, 0, 0xffff), - }, - { - name: "i8x16 gt_u", - cmpType: wazeroir.V128CmpTypeI16x8GtU, - x1: i16x8(0, 1, 0, 1, 0, 1, 0, 1), - x2: i16x8(0xffff, 0, 0, 1, 1, 1, 0, 0), - exp: i16x8(0, 0xffff, 0, 0, 0, 0, 0, 0xffff), - }, - { - name: "i8x16 le_s", - cmpType: wazeroir.V128CmpTypeI16x8LeS, - x1: i16x8(0xffff, 1, 0, 1, 0, 1, 0, 1), - x2: i16x8(0, 0, 0, 1, 1, 1, 0, 0), - exp: i16x8(0xffff, 0, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0), - }, - { - name: "i8x16 le_u", - cmpType: wazeroir.V128CmpTypeI16x8LeU, - x1: i16x8(0xffff, 1, 0, 1, 0, 1, 0, 1), - x2: i16x8(0, 0, 0, 1, 1, 1, 0, 0), - exp: i16x8(0, 0, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0), - }, - { - name: "i8x16 ge_s", - cmpType: wazeroir.V128CmpTypeI16x8GeS, - x1: i16x8(0, 1, 0, 1, 0, 1, 0, 1), - x2: i16x8(0xffff, 0, 0, 1, 1, 1, 0, 0), - exp: i16x8(0xffff, 0xffff, 0xffff, 0xffff, 0, 0xffff, 0xffff, 0xffff), - }, - { - name: "i8x16 ge_u", - cmpType: wazeroir.V128CmpTypeI16x8GeU, - x1: i16x8(0, 1, 0, 1, 0, 1, 0, 1), - x2: i16x8(0xffff, 0, 0, 1, 1, 1, 0, 0), - exp: i16x8(0, 0xffff, 0xffff, 0xffff, 0, 0xffff, 0xffff, 0xffff), - }, - { - name: "i32x4 eq", - cmpType: wazeroir.V128CmpTypeI32x4Eq, - x1: i32x4(0, 1, 1, 0), - x2: i32x4(0, 1, 0, 1), - exp: i32x4(0xffffffff, 0xffffffff, 0, 0), - }, - { - name: "i32x4 ne", - cmpType: wazeroir.V128CmpTypeI32x4Ne, - x1: i32x4(0, 1, 1, 0), - x2: i32x4(0, 1, 0, 1), - exp: i32x4(0, 0, 0xffffffff, 0xffffffff), - }, - { - name: "i32x4 lt_s", - cmpType: wazeroir.V128CmpTypeI32x4LtS, - x1: i32x4(0xffffffff, 1, 1, 0), - x2: i32x4(0, 1, 0, 1), - exp: i32x4(0xffffffff, 0, 0, 0xffffffff), - }, - { - name: "i32x4 lt_u", - cmpType: wazeroir.V128CmpTypeI32x4LtU, - x1: i32x4(0xffffffff, 1, 1, 0), - x2: i32x4(0, 1, 0, 1), - exp: i32x4(0, 0, 0, 0xffffffff), - }, - { - name: "i32x4 gt_s", - cmpType: wazeroir.V128CmpTypeI32x4GtS, - x1: i32x4(0, 1, 1, 1), - x2: i32x4(0xffffffff, 1, 0, 0), - exp: i32x4(0xffffffff, 0, 0xffffffff, 0xffffffff), - }, - { - name: "i32x4 gt_u", - cmpType: wazeroir.V128CmpTypeI32x4GtU, - x1: i32x4(0, 1, 1, 1), - x2: i32x4(0xffffffff, 1, 0, 0), - exp: i32x4(0, 0, 0xffffffff, 0xffffffff), - }, - { - name: "i32x4 le_s", - cmpType: wazeroir.V128CmpTypeI32x4LeS, - x1: i32x4(0xffffffff, 1, 1, 0), - x2: i32x4(0, 1, 0, 1), - exp: i32x4(0xffffffff, 0xffffffff, 0, 0xffffffff), - }, - { - name: "i32x4 le_u", - cmpType: wazeroir.V128CmpTypeI32x4LeU, - x1: i32x4(0xffffffff, 1, 1, 0), - x2: i32x4(0, 1, 0, 1), - exp: i32x4(0, 0xffffffff, 0, 0xffffffff), - }, - { - name: "i32x4 ge_s", - cmpType: wazeroir.V128CmpTypeI32x4GeS, - x1: i32x4(0, 1, 1, 0), - x2: i32x4(0xffffffff, 1, 0, 1), - exp: i32x4(0xffffffff, 0xffffffff, 0xffffffff, 0), - }, - { - name: "i32x4 ge_u", - cmpType: wazeroir.V128CmpTypeI32x4GeU, - x1: i32x4(0, 1, 1, 0), - x2: i32x4(0xffffffff, 1, 0, 1), - exp: i32x4(0, 0xffffffff, 0xffffffff, 0), - }, - { - name: "i64x2 eq", - cmpType: wazeroir.V128CmpTypeI64x2Eq, - x1: i64x2(1, 0), - x2: i64x2(0, 0), - exp: i64x2(0, 0xffffffffffffffff), - }, - { - name: "i64x2 ne", - cmpType: wazeroir.V128CmpTypeI64x2Ne, - x1: i64x2(1, 0), - x2: i64x2(0, 0), - exp: i64x2(0xffffffffffffffff, 0), - }, - { - name: "i64x2 lt_s", - cmpType: wazeroir.V128CmpTypeI64x2LtS, - x1: i64x2(0xffffffffffffffff, 0), - x2: i64x2(0, 0), - exp: i64x2(0xffffffffffffffff, 0), - }, - { - name: "i64x2 gt_s", - cmpType: wazeroir.V128CmpTypeI64x2GtS, - x1: i64x2(123, 0), - x2: i64x2(123, 0xffffffffffffffff), - exp: i64x2(0, 0xffffffffffffffff), - }, - { - name: "i64x2 le_s", - cmpType: wazeroir.V128CmpTypeI64x2LeS, - x1: i64x2(123, 0xffffffffffffffff), - x2: i64x2(123, 0), - exp: i64x2(0xffffffffffffffff, 0xffffffffffffffff), - }, - { - name: "i64x2 ge_s", - cmpType: wazeroir.V128CmpTypeI64x2GeS, - x1: i64x2(123, 0), - x2: i64x2(123, 0xffffffffffffffff), - exp: i64x2(0xffffffffffffffff, 0xffffffffffffffff), - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, - &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.x1[:8]), binary.LittleEndian.Uint64(tc.x1[8:])))) - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.x2[:8]), binary.LittleEndian.Uint64(tc.x2[8:])))) - require.NoError(t, err) - - err = compiler.compileV128Cmp(operationPtr(wazeroir.NewOperationV128Cmp(tc.cmpType))) - require.NoError(t, err) - - requireRuntimeLocationStackPointerEqual(t, uint64(2), compiler) - require.Equal(t, 1, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - lo, hi := env.stackTopAsV128() - var actual [16]byte - binary.LittleEndian.PutUint64(actual[:8], lo) - binary.LittleEndian.PutUint64(actual[8:], hi) - require.Equal(t, tc.exp, actual) - }) - } -} - -func TestCompiler_compileV128AvgrU(t *testing.T) { - tests := []struct { - name string - shape wazeroir.Shape - x1, x2, exp [16]byte - }{ - { - name: "i8x16", - shape: wazeroir.ShapeI8x16, - x1: [16]byte{0: 1, 2: 10, 10: 10, 15: math.MaxUint8}, - x2: [16]byte{0: 10, 4: 5, 10: 5, 15: 10}, - exp: [16]byte{ - 0: byte((uint16(1) + uint16(10) + 1) / 2), - 2: byte((uint16(10) + 1) / 2), - 4: byte((uint16(5) + 1) / 2), - 10: byte((uint16(10) + uint16(5) + 1) / 2), - 15: byte((uint16(math.MaxUint8) + uint16(10) + 1) / 2), - }, - }, - { - name: "i16x8", - shape: wazeroir.ShapeI16x8, - x1: i16x8(1, 0, 100, 0, 0, math.MaxUint16, 0, 0), - x2: i16x8(10, 0, math.MaxUint16, 0, 0, 1, 0, 0), - exp: i16x8( - uint16((uint32(1)+uint32(10)+1)/2), - 0, - uint16((uint32(100)+uint32(math.MaxUint16)+1)/2), - 0, - 0, - uint16((uint32(1)+uint32(math.MaxUint16)+1)/2), - 0, 0, - ), - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, - &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.x1[:8]), binary.LittleEndian.Uint64(tc.x1[8:])))) - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.x2[:8]), binary.LittleEndian.Uint64(tc.x2[8:])))) - require.NoError(t, err) - - err = compiler.compileV128AvgrU(operationPtr(wazeroir.NewOperationV128AvgrU(tc.shape))) - require.NoError(t, err) - - requireRuntimeLocationStackPointerEqual(t, uint64(2), compiler) - require.Equal(t, 1, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - require.Equal(t, nativeCallStatusCodeReturned, env.callEngine().statusCode) - - lo, hi := env.stackTopAsV128() - var actual [16]byte - binary.LittleEndian.PutUint64(actual[:8], lo) - binary.LittleEndian.PutUint64(actual[8:], hi) - require.Equal(t, tc.exp, actual) - }) - } -} - -func TestCompiler_compileV128Sqrt(t *testing.T) { - tests := []struct { - name string - shape wazeroir.Shape - v, exp [16]byte - }{ - { - name: "f32x4", - shape: wazeroir.ShapeF32x4, - v: f32x4(1.23, -123.1231, math.MaxFloat32, float32(math.Inf(1))), - exp: f32x4( - float32(math.Sqrt(float64(float32(1.23)))), - float32(math.Sqrt(float64(float32(-123.1231)))), - float32(math.Sqrt(float64(float32(math.MaxFloat32)))), - float32(math.Sqrt(float64(float32(math.Inf(1))))), - ), - }, - { - name: "f64x2", - shape: wazeroir.ShapeF64x2, - v: f64x2(1.2314, math.MaxFloat64), - exp: f64x2(math.Sqrt(1.2314), math.Sqrt(math.MaxFloat64)), - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, - &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.v[:8]), binary.LittleEndian.Uint64(tc.v[8:])))) - require.NoError(t, err) - - err = compiler.compileV128Sqrt(operationPtr(wazeroir.NewOperationV128Sqrt(tc.shape))) - require.NoError(t, err) - - requireRuntimeLocationStackPointerEqual(t, uint64(2), compiler) - require.Equal(t, 1, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - require.Equal(t, nativeCallStatusCodeReturned, env.callEngine().statusCode) - - lo, hi := env.stackTopAsV128() - var actual [16]byte - binary.LittleEndian.PutUint64(actual[:8], lo) - binary.LittleEndian.PutUint64(actual[8:], hi) - require.Equal(t, tc.exp, actual) - }) - } -} - -func TestCompiler_compileV128Mul(t *testing.T) { - tests := []struct { - name string - shape wazeroir.Shape - x1, x2, exp [16]byte - }{ - { - name: "i16x8", - shape: wazeroir.ShapeI16x8, - x1: i16x8(1123, 0, 123, 1, 1, 5, 8, 1), - x2: i16x8(0, 123, 123, 0, 1, 5, 9, 1), - exp: i16x8(0, 0, 123*123, 0, 1, 25, 8*9, 1), - }, - { - name: "i32x4", - shape: wazeroir.ShapeI32x4, - x1: i32x4(i32ToU32(-123), 5, 4, math.MaxUint32), - x2: i32x4(i32ToU32(-10), 1, i32ToU32(-104), 0), - exp: i32x4(1230, 5, i32ToU32(-416), 0), - }, - { - name: "i64x2", - shape: wazeroir.ShapeI64x2, - x1: i64x2(1, 12345), - x2: i64x2(100, i64ToU64(-10)), - exp: i64x2(100, i64ToU64(-123450)), - }, - { - name: "f32x4", - shape: wazeroir.ShapeF32x4, - x1: f32x4(1.0, 123, float32(math.Inf(1)), float32(math.Inf(-1))), - x2: f32x4(51234.12341, 123, math.MaxFloat32, -123), - exp: f32x4(51234.12341, 123*123, float32(math.Inf(1)), float32(math.Inf(1))), - }, - { - name: "f64x2", - shape: wazeroir.ShapeF64x2, - x1: f64x2(1.123, math.Inf(1)), - x2: f64x2(1.123, math.MinInt64), - exp: f64x2(1.123*1.123, math.Inf(-1)), - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, - &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.x1[:8]), binary.LittleEndian.Uint64(tc.x1[8:])))) - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.x2[:8]), binary.LittleEndian.Uint64(tc.x2[8:])))) - require.NoError(t, err) - - err = compiler.compileV128Mul(operationPtr(wazeroir.NewOperationV128Mul(tc.shape))) - require.NoError(t, err) - - requireRuntimeLocationStackPointerEqual(t, uint64(2), compiler) - require.Equal(t, 1, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - require.Equal(t, nativeCallStatusCodeReturned, env.callEngine().statusCode) - - lo, hi := env.stackTopAsV128() - var actual [16]byte - binary.LittleEndian.PutUint64(actual[:8], lo) - binary.LittleEndian.PutUint64(actual[8:], hi) - require.Equal(t, tc.exp, actual) - }) - } -} - -func TestCompiler_compileV128Neg(t *testing.T) { - tests := []struct { - name string - shape wazeroir.Shape - v, exp [16]byte - }{ - { - name: "i8x16", - shape: wazeroir.ShapeI8x16, - v: [16]byte{1: 123, 5: i8ToU8(-1), 15: i8ToU8(-125)}, - exp: [16]byte{1: i8ToU8(-123), 5: 1, 15: 125}, - }, - { - name: "i16x8", - shape: wazeroir.ShapeI16x8, - v: i16x8(0, 0, i16ToU16(-123), 0, 1, 25, 8, i16ToU16(-1)), - exp: i16x8(0, 0, 123, 0, i16ToU16(-1), i16ToU16(-25), i16ToU16(-8), 1), - }, - { - name: "i32x4", - shape: wazeroir.ShapeI32x4, - v: i32x4(1230, 5, i32ToU32(-416), 0), - exp: i32x4(i32ToU32(-1230), i32ToU32(-5), 416, 0), - }, - { - name: "i64x2", - shape: wazeroir.ShapeI64x2, - v: i64x2(100, i64ToU64(-123450)), - exp: i64x2(i64ToU64(-100), 123450), - }, - { - name: "f32x4", - shape: wazeroir.ShapeF32x4, - v: f32x4(51234.12341, -123, float32(math.Inf(1)), 0.1), - exp: f32x4(-51234.12341, 123, float32(math.Inf(-1)), -0.1), - }, - { - name: "f32x4", - shape: wazeroir.ShapeF32x4, - v: f32x4(51234.12341, 0, float32(math.Inf(1)), 0.1), - exp: f32x4(-51234.12341, float32(math.Copysign(0, -1)), float32(math.Inf(-1)), -0.1), - }, - { - name: "f64x2", - shape: wazeroir.ShapeF64x2, - v: f64x2(1.123, math.Inf(-1)), - exp: f64x2(-1.123, math.Inf(1)), - }, - { - name: "f64x2", - shape: wazeroir.ShapeF64x2, - v: f64x2(0, math.Inf(-1)), - exp: f64x2(math.Copysign(0, -1), math.Inf(1)), - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, - &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.v[:8]), binary.LittleEndian.Uint64(tc.v[8:])))) - require.NoError(t, err) - - err = compiler.compileV128Neg(operationPtr(wazeroir.NewOperationV128Neg(tc.shape))) - require.NoError(t, err) - - requireRuntimeLocationStackPointerEqual(t, uint64(2), compiler) - require.Equal(t, 1, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - require.Equal(t, nativeCallStatusCodeReturned, env.callEngine().statusCode) - - lo, hi := env.stackTopAsV128() - var actual [16]byte - binary.LittleEndian.PutUint64(actual[:8], lo) - binary.LittleEndian.PutUint64(actual[8:], hi) - require.Equal(t, tc.exp, actual) - }) - } -} - -func TestCompiler_compileV128Abs(t *testing.T) { - tests := []struct { - name string - shape wazeroir.Shape - v, exp [16]byte - }{ - { - name: "i8x16", - shape: wazeroir.ShapeI8x16, - v: [16]byte{1: 123, 5: i8ToU8(-1), 15: i8ToU8(-125)}, - exp: [16]byte{1: 123, 5: 1, 15: 125}, - }, - { - name: "i16x8", - shape: wazeroir.ShapeI16x8, - v: i16x8(0, 0, i16ToU16(-123), 0, 1, 25, 8, i16ToU16(-1)), - exp: i16x8(0, 0, 123, 0, 1, 25, 8, 1), - }, - { - name: "i32x4", - shape: wazeroir.ShapeI32x4, - v: i32x4(i32ToU32(-1230), 5, i32ToU32(-416), 0), - exp: i32x4(1230, 5, 416, 0), - }, - { - name: "i64x2", - shape: wazeroir.ShapeI64x2, - v: i64x2(i64ToU64(-100), i64ToU64(-123450)), - exp: i64x2(100, 123450), - }, - { - name: "f32x4", - shape: wazeroir.ShapeF32x4, - v: f32x4(51234.12341, -123, float32(math.Inf(1)), 0.1), - exp: f32x4(51234.12341, 123, float32(math.Inf(1)), 0.1), - }, - { - name: "f32x4", - shape: wazeroir.ShapeF32x4, - v: f32x4(51234.12341, 0, float32(math.Inf(1)), -0.1), - exp: f32x4(51234.12341, 0, float32(math.Inf(1)), 0.1), - }, - { - name: "f64x2", - shape: wazeroir.ShapeF64x2, - v: f64x2(-1.123, math.Inf(-1)), - exp: f64x2(1.123, math.Inf(1)), - }, - { - name: "f64x2", - shape: wazeroir.ShapeF64x2, - v: f64x2(0, math.Inf(-1)), - exp: f64x2(0, math.Inf(1)), - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, - &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.v[:8]), binary.LittleEndian.Uint64(tc.v[8:])))) - require.NoError(t, err) - - err = compiler.compileV128Abs(operationPtr(wazeroir.NewOperationV128Abs(tc.shape))) - require.NoError(t, err) - - requireRuntimeLocationStackPointerEqual(t, uint64(2), compiler) - require.Equal(t, 1, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - require.Equal(t, nativeCallStatusCodeReturned, env.callEngine().statusCode) - - lo, hi := env.stackTopAsV128() - var actual [16]byte - binary.LittleEndian.PutUint64(actual[:8], lo) - binary.LittleEndian.PutUint64(actual[8:], hi) - require.Equal(t, tc.exp, actual) - }) - } -} - -func TestCompiler_compileV128Div(t *testing.T) { - tests := []struct { - name string - shape wazeroir.Shape - x1, x2, exp [16]byte - }{ - { - name: "f32x4", - shape: wazeroir.ShapeF32x4, - x1: f32x4(1.0, 123, float32(math.Inf(1)), float32(math.Inf(-1))), - x2: f32x4(123.12, 123, math.MaxFloat32, -123), - exp: f32x4(float32(1.0)/float32(123.12), 1, float32(math.Inf(1)), float32(math.Inf(1))), - }, - { - name: "f64x2", - shape: wazeroir.ShapeF64x2, - x1: f64x2(1.123, math.Inf(1)), - x2: f64x2(1.123, math.MinInt64), - exp: f64x2(1.0, math.Inf(-1)), - }, - { - name: "f64x2", - shape: wazeroir.ShapeF64x2, - x1: f64x2(0, math.Inf(1)), - x2: f64x2(1.123, math.MaxInt64), - exp: f64x2(0, math.Inf(1)), - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, - &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.x1[:8]), binary.LittleEndian.Uint64(tc.x1[8:])))) - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.x2[:8]), binary.LittleEndian.Uint64(tc.x2[8:])))) - require.NoError(t, err) - - err = compiler.compileV128Div(operationPtr(wazeroir.NewOperationV128Div(tc.shape))) - require.NoError(t, err) - - requireRuntimeLocationStackPointerEqual(t, uint64(2), compiler) - require.Equal(t, 1, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - require.Equal(t, nativeCallStatusCodeReturned, env.callEngine().statusCode) - - lo, hi := env.stackTopAsV128() - var actual [16]byte - binary.LittleEndian.PutUint64(actual[:8], lo) - binary.LittleEndian.PutUint64(actual[8:], hi) - require.Equal(t, tc.exp, actual) - }) - } -} - -func TestCompiler_compileV128Min(t *testing.T) { - tests := []struct { - name string - shape wazeroir.Shape - signed bool - x1, x2, exp [16]byte - }{ - { - name: "i8x16s", - shape: wazeroir.ShapeI8x16, - signed: true, - x1: [16]byte{0: 123, 5: i8ToU8(-1), 15: 2}, - x2: [16]byte{0: 1, 5: 0, 15: i8ToU8(-1)}, - exp: [16]byte{0: 1, 5: i8ToU8(-1), 15: i8ToU8(-1)}, - }, - { - name: "i8x16u", - shape: wazeroir.ShapeI8x16, - signed: false, - x1: [16]byte{0: 123, 5: i8ToU8(-1), 15: 2}, - x2: [16]byte{0: 1, 5: 0, 15: i8ToU8(-1)}, - exp: [16]byte{0: 1, 5: 0, 15: 2}, - }, - { - name: "i16x8s", - shape: wazeroir.ShapeI16x8, - signed: true, - x1: i16x8(1123, 0, 123, 1, 1, 6, i16ToU16(-123), 1), - x2: i16x8(0, 123, i16ToU16(-123), 3, 1, 4, 5, 1), - exp: i16x8(0, 0, i16ToU16(-123), 1, 1, 4, i16ToU16(-123), 1), - }, - { - name: "i16x8u", - shape: wazeroir.ShapeI16x8, - signed: false, - x1: i16x8(1123, 0, 123, 1, 1, 6, i16ToU16(-123), 1), - x2: i16x8(0, 123, i16ToU16(-123), 3, 1, 4, 5, 1), - exp: i16x8(0, 0, 123, 1, 1, 4, 5, 1), - }, - { - name: "i32x4s", - shape: wazeroir.ShapeI32x4, - signed: true, - x1: i32x4(i32ToU32(-123), 0, 1, i32ToU32(math.MinInt32)), - x2: i32x4(123, 5, 1, 0), - exp: i32x4(i32ToU32(-123), 0, 1, i32ToU32(math.MinInt32)), - }, - { - name: "i32x4u", - shape: wazeroir.ShapeI32x4, - signed: false, - x1: i32x4(i32ToU32(-123), 0, 1, i32ToU32(math.MinInt32)), - x2: i32x4(123, 5, 1, 0), - exp: i32x4(123, 0, 1, 0), - }, - { - name: "f32x4", - shape: wazeroir.ShapeF32x4, - // If the sign of zeros are different, negative zeros must be returned according to the spec. - x1: f32x4(0, math.Float32frombits(0b1<<31), 0, 0), - x2: f32x4(math.Float32frombits(0b1<<31), math.Float32frombits(0b1<<31), math.Float32frombits(0b1<<31), 0), - exp: f32x4(math.Float32frombits(0b1<<31), math.Float32frombits(0b1<<31), math.Float32frombits(0b1<<31), 0), - }, - { - name: "f32x4", - shape: wazeroir.ShapeF32x4, - // If the sign of zeros are different, negative zeros must be returned according to the spec. - x1: f32x4(math.Float32frombits(0b1<<31), math.Float32frombits(0b1<<31), math.Float32frombits(0b1<<31), 0), - x2: f32x4(0, math.Float32frombits(0b1<<31), 0, 0), - exp: f32x4(math.Float32frombits(0b1<<31), math.Float32frombits(0b1<<31), math.Float32frombits(0b1<<31), 0), - }, - { - name: "f32x4", - shape: wazeroir.ShapeF32x4, - x1: f32x4(float32(math.NaN()), -123.12, 2.3, float32(math.Inf(1))), - x2: f32x4(5.5, 123.12, 5.0, float32(math.Inf(-1))), - exp: f32x4(float32(math.NaN()), -123.12, 2.3, float32(math.Inf(-1))), - }, - { - name: "f32x4", - shape: wazeroir.ShapeF32x4, - x1: f32x4(5.5, 123.12, -5.0, float32(math.Inf(-1))), - x2: f32x4(-123.12, float32(math.NaN()), 2.3, float32(math.Inf(-1))), - exp: f32x4(-123.12, float32(math.NaN()), -5.0, float32(math.Inf(-1))), - }, - { - name: "f32x4", - shape: wazeroir.ShapeF32x4, - x1: f32x4(float32(math.Inf(1)), float32(math.Inf(-1)), float32(math.Inf(-1)), float32(math.Inf(1))), - x2: f32x4(float32(math.NaN()), float32(math.NaN()), float32(math.NaN()), float32(math.NaN())), - exp: f32x4(float32(math.NaN()), float32(math.NaN()), float32(math.NaN()), float32(math.NaN())), - }, - { - name: "f32x4", - shape: wazeroir.ShapeF32x4, - x1: f32x4(float32(math.NaN()), float32(math.NaN()), float32(math.NaN()), float32(math.NaN())), - x2: f32x4(float32(math.Inf(1)), float32(math.Inf(-1)), float32(math.Inf(-1)), float32(math.Inf(1))), - exp: f32x4(float32(math.NaN()), float32(math.NaN()), float32(math.NaN()), float32(math.NaN())), - }, - { - name: "f64x2", - shape: wazeroir.ShapeF64x2, - // If the sign of zeros are different, negative zeros must be returned according to the spec. - x1: f64x2(math.Copysign(0, -1), math.Copysign(0, 1)), - x2: f64x2(math.Copysign(0, -1), math.Copysign(0, -1)), - exp: f64x2(math.Copysign(0, -1), math.Copysign(0, -1)), - }, - { - name: "f64x2", - shape: wazeroir.ShapeF64x2, - // If the sign of zeros are different, negative zeros must be returned according to the spec. - x1: f64x2(math.Copysign(0, -1), 0), - x2: f64x2(0, math.Copysign(0, -1)), - exp: f64x2(math.Copysign(0, -1), math.Copysign(0, -1)), - }, - { - name: "f64x2", - shape: wazeroir.ShapeF64x2, - x1: f64x2(math.MinInt64, 0), - x2: f64x2(math.MaxInt64, -12.3), - exp: f64x2(math.MinInt64, -12.3), - }, - { - name: "f64x2", - shape: wazeroir.ShapeF64x2, - x1: f64x2(math.MaxInt64, -12.3), - x2: f64x2(math.MinInt64, 0), - exp: f64x2(math.MinInt64, -12.3), - }, - { - name: "f64x2", - shape: wazeroir.ShapeF64x2, - x1: f64x2(math.NaN(), math.NaN()), - x2: f64x2(math.Inf(1), math.Inf(-1)), - exp: f64x2(math.NaN(), math.NaN()), - }, - { - name: "f64x2", - shape: wazeroir.ShapeF64x2, - x1: f64x2(math.Inf(1), math.Inf(-1)), - x2: f64x2(math.NaN(), math.NaN()), - exp: f64x2(math.NaN(), math.NaN()), - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, - &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.x1[:8]), binary.LittleEndian.Uint64(tc.x1[8:])))) - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.x2[:8]), binary.LittleEndian.Uint64(tc.x2[8:])))) - require.NoError(t, err) - - err = compiler.compileV128Min(operationPtr(wazeroir.NewOperationV128Min(tc.shape, tc.signed))) - require.NoError(t, err) - - requireRuntimeLocationStackPointerEqual(t, uint64(2), compiler) - require.Equal(t, 1, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - require.Equal(t, nativeCallStatusCodeReturned, env.callEngine().statusCode) - - lo, hi := env.stackTopAsV128() - switch tc.shape { - case wazeroir.ShapeF64x2: - for _, vs := range [][2]float64{ - {math.Float64frombits(lo), math.Float64frombits(binary.LittleEndian.Uint64(tc.exp[:8]))}, - {math.Float64frombits(hi), math.Float64frombits(binary.LittleEndian.Uint64(tc.exp[8:]))}, - } { - actual, exp := vs[0], vs[1] - if math.IsNaN(exp) { - require.True(t, math.IsNaN(actual)) - } else { - require.Equal(t, math.Float64bits(exp), math.Float64bits(actual)) - } - } - case wazeroir.ShapeF32x4: - for _, vs := range [][2]float32{ - {math.Float32frombits(uint32(lo)), math.Float32frombits(binary.LittleEndian.Uint32(tc.exp[:4]))}, - {math.Float32frombits(uint32(lo >> 32)), math.Float32frombits(binary.LittleEndian.Uint32(tc.exp[4:8]))}, - {math.Float32frombits(uint32(hi)), math.Float32frombits(binary.LittleEndian.Uint32(tc.exp[8:12]))}, - {math.Float32frombits(uint32(hi >> 32)), math.Float32frombits(binary.LittleEndian.Uint32(tc.exp[12:]))}, - } { - actual, exp := vs[0], vs[1] - if math.IsNaN(float64(exp)) { - require.True(t, math.IsNaN(float64(actual))) - } else { - require.Equal(t, math.Float32bits(exp), math.Float32bits(actual)) - } - } - default: - var actual [16]byte - binary.LittleEndian.PutUint64(actual[:8], lo) - binary.LittleEndian.PutUint64(actual[8:], hi) - require.Equal(t, tc.exp, actual) - } - }) - } -} - -func TestCompiler_compileV128Max(t *testing.T) { - tests := []struct { - name string - shape wazeroir.Shape - signed bool - x1, x2, exp [16]byte - }{ - { - name: "i8x16s", - shape: wazeroir.ShapeI8x16, - signed: true, - x1: [16]byte{0: 123, 5: i8ToU8(-1), 15: 2}, - x2: [16]byte{0: 1, 5: 0, 15: i8ToU8(-1)}, - exp: [16]byte{0: 123, 5: 0, 15: 2}, - }, - { - name: "i8x16u", - shape: wazeroir.ShapeI8x16, - signed: false, - x1: [16]byte{0: 123, 5: i8ToU8(-1), 15: 2}, - x2: [16]byte{0: 1, 5: 0, 15: i8ToU8(-1)}, - exp: [16]byte{0: 123, 5: i8ToU8(-1), 15: i8ToU8(-1)}, - }, - { - name: "i16x8s", - shape: wazeroir.ShapeI16x8, - signed: true, - x1: i16x8(1123, 0, 123, 1, 1, 6, i16ToU16(-123), 1), - x2: i16x8(0, 123, i16ToU16(-123), 3, 1, 4, 5, 1), - exp: i16x8(1123, 123, 123, 3, 1, 6, 5, 1), - }, - { - name: "i16x8u", - shape: wazeroir.ShapeI16x8, - signed: false, - x1: i16x8(1123, 0, 123, 1, 1, 6, i16ToU16(-123), 1), - x2: i16x8(0, 123, i16ToU16(-123), 3, 1, 4, 5, 1), - exp: i16x8(1123, 123, i16ToU16(-123), 3, 1, 6, i16ToU16(-123), 1), - }, - { - name: "i32x4s", - shape: wazeroir.ShapeI32x4, - signed: true, - x1: i32x4(i32ToU32(-123), 0, 1, i32ToU32(math.MinInt32)), - x2: i32x4(123, 5, 1, 0), - exp: i32x4(123, 5, 1, 0), - }, - { - name: "i32x4u", - shape: wazeroir.ShapeI32x4, - signed: false, - x1: i32x4(i32ToU32(-123), 0, 1, i32ToU32(math.MinInt32)), - x2: i32x4(123, 5, 1, 0), - exp: i32x4(i32ToU32(-123), 5, 1, i32ToU32(math.MinInt32)), - }, - { - name: "f32x4", - shape: wazeroir.ShapeF32x4, - x1: f32x4(float32(math.NaN()), -123.12, 2.3, float32(math.Inf(1))), - x2: f32x4(5.5, 123.12, 5.0, float32(math.Inf(-1))), - exp: f32x4(float32(math.NaN()), 123.12, 5.0, float32(math.Inf(1))), - }, - { - name: "f32x4", - shape: wazeroir.ShapeF32x4, - x1: f32x4(5.5, 123.12, -5.0, float32(math.Inf(-1))), - x2: f32x4(-123.12, float32(math.NaN()), 2.3, float32(math.Inf(-1))), - exp: f32x4(5.5, float32(math.NaN()), 2.3, float32(math.Inf(-1))), - }, - { - name: "f32x4", - shape: wazeroir.ShapeF32x4, - x1: f32x4(float32(math.Inf(1)), float32(math.Inf(-1)), float32(math.Inf(-1)), float32(math.Inf(1))), - x2: f32x4(float32(math.NaN()), float32(math.NaN()), float32(math.NaN()), float32(math.NaN())), - exp: f32x4(float32(math.NaN()), float32(math.NaN()), float32(math.NaN()), float32(math.NaN())), - }, - { - name: "f32x4", - shape: wazeroir.ShapeF32x4, - x1: f32x4(float32(math.NaN()), float32(math.NaN()), float32(math.NaN()), float32(math.NaN())), - x2: f32x4(float32(math.Inf(1)), float32(math.Inf(-1)), float32(math.Inf(-1)), float32(math.Inf(1))), - exp: f32x4(float32(math.NaN()), float32(math.NaN()), float32(math.NaN()), float32(math.NaN())), - }, - { - name: "f32x4", - shape: wazeroir.ShapeF32x4, - // If the sign of zeros are different, positive zeros must be returned according to the spec. - x1: f32x4(0, 0, math.Float32frombits(1<<31), 0), - x2: f32x4(math.Float32frombits(1<<31), math.Float32frombits(1<<31), math.Float32frombits(1<<31), math.Float32frombits(1<<31)), - exp: f32x4(0, 0, math.Float32frombits(1<<31), 0), - }, - { - name: "f64x2", - shape: wazeroir.ShapeF64x2, - x1: f64x2(math.MinInt64, 0), - x2: f64x2(math.MaxInt64, -12.3), - exp: f64x2(math.MaxInt64, 0), - }, - { - name: "f64x2", - shape: wazeroir.ShapeF64x2, - x1: f64x2(math.MaxInt64, -12.3), - x2: f64x2(math.MinInt64, 0), - exp: f64x2(math.MaxInt64, 0), - }, - { - name: "f64x2", - shape: wazeroir.ShapeF64x2, - x1: f64x2(math.NaN(), -12.3), - x2: f64x2(math.MinInt64, math.NaN()), - exp: f64x2(math.NaN(), math.NaN()), - }, - { - name: "f64x2", - shape: wazeroir.ShapeF64x2, - x1: f64x2(math.MinInt64, math.NaN()), - x2: f64x2(math.NaN(), -12.3), - exp: f64x2(math.NaN(), math.NaN()), - }, - { - name: "f64x2", - shape: wazeroir.ShapeF64x2, - x1: f64x2(math.NaN(), math.NaN()), - x2: f64x2(math.Inf(1), math.Inf(-1)), - exp: f64x2(math.NaN(), math.NaN()), - }, - { - name: "f64x2", - shape: wazeroir.ShapeF64x2, - x1: f64x2(math.Inf(1), math.Inf(-1)), - x2: f64x2(math.NaN(), math.NaN()), - exp: f64x2(math.NaN(), math.NaN()), - }, - { - name: "f64x2", - shape: wazeroir.ShapeF64x2, - // If the sign of zeros are different, positive zeros must be returned according to the spec. - x1: f64x2(0, 0), - x2: f64x2(math.Copysign(0, -1), math.Copysign(0, -1)), - exp: f64x2(0, 0), - }, - { - name: "f64x2", - shape: wazeroir.ShapeF64x2, - // If the sign of zeros are different, positive zeros must be returned according to the spec. - x1: f64x2(math.Copysign(0, -1), math.Copysign(0, 1)), - x2: f64x2(math.Copysign(0, -1), math.Copysign(0, -1)), - exp: f64x2(math.Copysign(0, -1), 0), - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, - &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.x1[:8]), binary.LittleEndian.Uint64(tc.x1[8:])))) - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.x2[:8]), binary.LittleEndian.Uint64(tc.x2[8:])))) - require.NoError(t, err) - - err = compiler.compileV128Max(operationPtr(wazeroir.NewOperationV128Max(tc.shape, tc.signed))) - require.NoError(t, err) - - requireRuntimeLocationStackPointerEqual(t, uint64(2), compiler) - require.Equal(t, 1, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - require.Equal(t, nativeCallStatusCodeReturned, env.callEngine().statusCode) - - lo, hi := env.stackTopAsV128() - switch tc.shape { - case wazeroir.ShapeF64x2: - for _, vs := range [][2]float64{ - {math.Float64frombits(lo), math.Float64frombits(binary.LittleEndian.Uint64(tc.exp[:8]))}, - {math.Float64frombits(hi), math.Float64frombits(binary.LittleEndian.Uint64(tc.exp[8:]))}, - } { - actual, exp := vs[0], vs[1] - if math.IsNaN(exp) { - require.True(t, math.IsNaN(actual)) - } else { - require.Equal(t, math.Float64bits(exp), math.Float64bits(actual)) - } - } - case wazeroir.ShapeF32x4: - for _, vs := range [][2]float32{ - {math.Float32frombits(uint32(lo)), math.Float32frombits(binary.LittleEndian.Uint32(tc.exp[:4]))}, - {math.Float32frombits(uint32(lo >> 32)), math.Float32frombits(binary.LittleEndian.Uint32(tc.exp[4:8]))}, - {math.Float32frombits(uint32(hi)), math.Float32frombits(binary.LittleEndian.Uint32(tc.exp[8:12]))}, - {math.Float32frombits(uint32(hi >> 32)), math.Float32frombits(binary.LittleEndian.Uint32(tc.exp[12:]))}, - } { - actual, exp := vs[0], vs[1] - if math.IsNaN(float64(exp)) { - require.True(t, math.IsNaN(float64(actual))) - } else { - require.Equal(t, math.Float32bits(exp), math.Float32bits(actual)) - } - } - default: - var actual [16]byte - binary.LittleEndian.PutUint64(actual[:8], lo) - binary.LittleEndian.PutUint64(actual[8:], hi) - require.Equal(t, tc.exp, actual) - } - }) - } -} - -func TestCompiler_compileV128AddSat(t *testing.T) { - tests := []struct { - name string - shape wazeroir.Shape - signed bool - x1, x2, exp [16]byte - }{ - { - name: "i8x16s", - shape: wazeroir.ShapeI8x16, - signed: true, - x1: [16]byte{ - 0: i8ToU8(math.MaxInt8), - 5: i8ToU8(-1), - 15: i8ToU8(math.MinInt8), - }, - x2: [16]byte{ - 0: 1, - 5: 0, - 15: i8ToU8(-1), - }, - exp: [16]byte{ - 0: i8ToU8(math.MaxInt8), - 5: i8ToU8(-1), - 15: i8ToU8(math.MinInt8), - }, - }, - { - name: "i8x16u", - shape: wazeroir.ShapeI8x16, - signed: false, - x1: [16]byte{ - 0: i8ToU8(math.MaxInt8), - 5: 0, - 15: math.MaxUint8, - }, - x2: [16]byte{ - 0: 1, - 5: i8ToU8(-1), - 15: 1, - }, - exp: [16]byte{ - 0: i8ToU8(math.MaxInt8) + 1, - 5: i8ToU8(-1), - 15: math.MaxUint8, - }, - }, - { - name: "i16x8s", - shape: wazeroir.ShapeI16x8, - signed: true, - x1: i16x8(i16ToU16(math.MinInt16), 0, 123, 1, 1, 6, i16ToU16(-123), i16ToU16(math.MaxInt16)), - x2: i16x8(i16ToU16(-1), 123, i16ToU16(-123), 3, 1, 4, 5, 1), - exp: i16x8(i16ToU16(math.MinInt16), 123, 0, 4, 2, 10, i16ToU16(-118), i16ToU16(math.MaxInt16)), - }, - { - name: "i16x8u", - shape: wazeroir.ShapeI16x8, - signed: false, - x1: i16x8(1123, 0, 123, 1, 1, 6, i16ToU16(-123), math.MaxUint16), - x2: i16x8(0, 123, math.MaxUint16, 3, 1, 4, 0, 1), - exp: i16x8(1123, 123, math.MaxUint16, 4, 2, 10, i16ToU16(-123), math.MaxUint16), - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, - &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.x1[:8]), binary.LittleEndian.Uint64(tc.x1[8:])))) - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.x2[:8]), binary.LittleEndian.Uint64(tc.x2[8:])))) - require.NoError(t, err) - - err = compiler.compileV128AddSat(operationPtr(wazeroir.NewOperationV128AddSat(tc.shape, tc.signed))) - require.NoError(t, err) - - requireRuntimeLocationStackPointerEqual(t, uint64(2), compiler) - require.Equal(t, 1, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - require.Equal(t, nativeCallStatusCodeReturned, env.callEngine().statusCode) - - lo, hi := env.stackTopAsV128() - var actual [16]byte - binary.LittleEndian.PutUint64(actual[:8], lo) - binary.LittleEndian.PutUint64(actual[8:], hi) - require.Equal(t, tc.exp, actual) - }) - } -} - -func TestCompiler_compileV128SubSat(t *testing.T) { - tests := []struct { - name string - shape wazeroir.Shape - signed bool - x1, x2, exp [16]byte - }{ - { - name: "i8x16s", - shape: wazeroir.ShapeI8x16, - signed: true, - x1: [16]byte{ - 0: i8ToU8(math.MinInt8), - 5: i8ToU8(-1), - 15: i8ToU8(math.MaxInt8), - }, - x2: [16]byte{ - 0: 1, - 5: 0, - 15: i8ToU8(-1), - }, - exp: [16]byte{ - 0: i8ToU8(math.MinInt8), - 5: i8ToU8(-1), - 15: i8ToU8(math.MaxInt8), - }, - }, - { - name: "i8x16u", - shape: wazeroir.ShapeI8x16, - signed: false, - x1: [16]byte{ - 0: i8ToU8(math.MinInt8), - 5: i8ToU8(-1), - 15: 0, - }, - x2: [16]byte{ - 0: 1, - 5: 0, - 15: 1, - }, - exp: [16]byte{ - 0: i8ToU8(math.MinInt8) - 1, - 5: i8ToU8(-1), - 15: 0, - }, - }, - { - name: "i16x8s", - shape: wazeroir.ShapeI16x8, - signed: true, - x1: i16x8(i16ToU16(math.MinInt16), 0, 123, 1, 1, 6, i16ToU16(-123), i16ToU16(math.MaxInt16)), - x2: i16x8(1, 123, i16ToU16(-123), 3, 1, 4, 5, i16ToU16(-123)), - exp: i16x8(i16ToU16(math.MinInt16), i16ToU16(-123), 246, i16ToU16(-2), 0, 2, i16ToU16(-128), i16ToU16(math.MaxInt16)), - }, - { - name: "i16x8u", - shape: wazeroir.ShapeI16x8, - signed: false, - x1: i16x8(1123, 0, 123, 1, 1, 6, 200, math.MaxUint16), - x2: i16x8(0, 123, math.MaxUint16, 3, 1, 4, i16ToU16(-1), 12), - exp: i16x8(1123, 0, 0, 0, 0, 2, 0, math.MaxUint16-12), - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, - &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.x1[:8]), binary.LittleEndian.Uint64(tc.x1[8:])))) - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.x2[:8]), binary.LittleEndian.Uint64(tc.x2[8:])))) - require.NoError(t, err) - - err = compiler.compileV128SubSat(operationPtr(wazeroir.NewOperationV128SubSat(tc.shape, tc.signed))) - require.NoError(t, err) - - requireRuntimeLocationStackPointerEqual(t, uint64(2), compiler) - require.Equal(t, 1, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - require.Equal(t, nativeCallStatusCodeReturned, env.callEngine().statusCode) - - lo, hi := env.stackTopAsV128() - var actual [16]byte - binary.LittleEndian.PutUint64(actual[:8], lo) - binary.LittleEndian.PutUint64(actual[8:], hi) - require.Equal(t, tc.exp, actual) - }) - } -} - -func TestCompiler_compileV128Popcnt(t *testing.T) { - tests := []struct { - name string - v, exp [16]byte - }{ - { - name: "ones", - v: [16]byte{ - 1, 1 << 1, 1 << 2, 1 << 3, 1 << 4, 1 << 5, 1 << 6, 1 << 7, - 0, 1 << 2, 0, 1 << 4, 0, 1 << 6, 0, 0, - }, - exp: [16]byte{ - 1, 1, 1, 1, 1, 1, 1, 1, - 0, 1, 0, 1, 0, 1, 0, 0, - }, - }, - { - name: "mix", - v: [16]byte{ - 0b1, 0b11, 0b111, 0b1111, 0b11111, 0b111111, 0b1111111, 0b11111111, - 0b10000001, 0b10000010, 0b10000100, 0b10001000, 0b10010000, 0b10100000, 0b11000000, 0, - }, - exp: [16]byte{ - 1, 2, 3, 4, 5, 6, 7, 8, - 2, 2, 2, 2, 2, 2, 2, 0, - }, - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, - &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.v[:8]), binary.LittleEndian.Uint64(tc.v[8:])))) - require.NoError(t, err) - - err = compiler.compileV128Popcnt(operationPtr(wazeroir.NewOperationV128Popcnt(0))) - require.NoError(t, err) - - requireRuntimeLocationStackPointerEqual(t, uint64(2), compiler) - require.Equal(t, 1, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - require.Equal(t, nativeCallStatusCodeReturned, env.callEngine().statusCode) - - lo, hi := env.stackTopAsV128() - var actual [16]byte - binary.LittleEndian.PutUint64(actual[:8], lo) - binary.LittleEndian.PutUint64(actual[8:], hi) - require.Equal(t, tc.exp, actual) - }) - } -} - -func TestCompiler_compileV128Round(t *testing.T) { - tests := []struct { - name string - shape wazeroir.Shape - kind wazeroir.OperationKind - v [16]byte - }{ - { - name: "f32 ceil", - shape: wazeroir.ShapeF32x4, - kind: wazeroir.OperationKindV128Ceil, - v: f32x4(1.4, -1.5, 1.5, float32(math.Inf(1))), - }, - { - name: "f32 ceil", - shape: wazeroir.ShapeF32x4, - kind: wazeroir.OperationKindV128Ceil, - v: f32x4(math.Pi, -1231231.123, float32(math.NaN()), float32(math.Inf(-1))), - }, - { - name: "f64 ceil", - shape: wazeroir.ShapeF64x2, - kind: wazeroir.OperationKindV128Ceil, - v: f64x2(1.231, -123.12313), - }, - { - name: "f64 ceil", - shape: wazeroir.ShapeF64x2, - kind: wazeroir.OperationKindV128Ceil, - v: f64x2(math.Inf(1), math.NaN()), - }, - { - name: "f64 ceil", - shape: wazeroir.ShapeF64x2, - kind: wazeroir.OperationKindV128Ceil, - v: f64x2(math.Inf(-1), math.Pi), - }, - { - name: "f32 floor", - shape: wazeroir.ShapeF32x4, - kind: wazeroir.OperationKindV128Floor, - v: f32x4(1.4, -1.5, 1.5, float32(math.Inf(1))), - }, - { - name: "f32 floor", - shape: wazeroir.ShapeF32x4, - kind: wazeroir.OperationKindV128Floor, - v: f32x4(math.Pi, -1231231.123, float32(math.NaN()), float32(math.Inf(-1))), - }, - { - name: "f64 floor", - shape: wazeroir.ShapeF64x2, - kind: wazeroir.OperationKindV128Floor, - v: f64x2(1.231, -123.12313), - }, - { - name: "f64 floor", - shape: wazeroir.ShapeF64x2, - kind: wazeroir.OperationKindV128Floor, - v: f64x2(math.Inf(1), math.NaN()), - }, - { - name: "f64 floor", - shape: wazeroir.ShapeF64x2, - kind: wazeroir.OperationKindV128Floor, - v: f64x2(math.Inf(-1), math.Pi), - }, - { - name: "f32 trunc", - shape: wazeroir.ShapeF32x4, - kind: wazeroir.OperationKindV128Trunc, - v: f32x4(1.4, -1.5, 1.5, float32(math.Inf(1))), - }, - { - name: "f32 trunc", - shape: wazeroir.ShapeF32x4, - kind: wazeroir.OperationKindV128Trunc, - v: f32x4(math.Pi, -1231231.123, float32(math.NaN()), float32(math.Inf(-1))), - }, - { - name: "f64 trunc", - shape: wazeroir.ShapeF64x2, - kind: wazeroir.OperationKindV128Trunc, - v: f64x2(1.231, -123.12313), - }, - { - name: "f64 trunc", - shape: wazeroir.ShapeF64x2, - kind: wazeroir.OperationKindV128Trunc, - v: f64x2(math.Inf(1), math.NaN()), - }, - { - name: "f64 trunc", - shape: wazeroir.ShapeF64x2, - kind: wazeroir.OperationKindV128Trunc, - v: f64x2(math.Inf(-1), math.Pi), - }, - { - name: "f32 nearest", - shape: wazeroir.ShapeF32x4, - kind: wazeroir.OperationKindV128Nearest, - v: f32x4(1.4, -1.5, 1.5, float32(math.Inf(1))), - }, - { - name: "f32 nearest", - shape: wazeroir.ShapeF32x4, - kind: wazeroir.OperationKindV128Nearest, - v: f32x4(math.Pi, -1231231.123, float32(math.NaN()), float32(math.Inf(-1))), - }, - { - name: "f64 nearest", - shape: wazeroir.ShapeF64x2, - kind: wazeroir.OperationKindV128Nearest, - v: f64x2(1.231, -123.12313), - }, - { - name: "f64 nearest", - shape: wazeroir.ShapeF64x2, - kind: wazeroir.OperationKindV128Nearest, - v: f64x2(math.Inf(1), math.NaN()), - }, - { - name: "f64 nearest", - shape: wazeroir.ShapeF64x2, - kind: wazeroir.OperationKindV128Nearest, - v: f64x2(math.Inf(-1), math.Pi), - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, - &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.v[:8]), binary.LittleEndian.Uint64(tc.v[8:])))) - require.NoError(t, err) - - is32bit := tc.shape == wazeroir.ShapeF32x4 - switch tc.kind { - case wazeroir.OperationKindV128Ceil: - err = compiler.compileV128Ceil(operationPtr(wazeroir.NewOperationV128Ceil(tc.shape))) - case wazeroir.OperationKindV128Floor: - err = compiler.compileV128Floor(operationPtr(wazeroir.NewOperationV128Floor(tc.shape))) - case wazeroir.OperationKindV128Trunc: - err = compiler.compileV128Trunc(operationPtr(wazeroir.NewOperationV128Trunc(tc.shape))) - case wazeroir.OperationKindV128Nearest: - err = compiler.compileV128Nearest(operationPtr(wazeroir.NewOperationV128Nearest(tc.shape))) - } - require.NoError(t, err) - - requireRuntimeLocationStackPointerEqual(t, uint64(2), compiler) - require.Equal(t, 1, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - require.Equal(t, nativeCallStatusCodeReturned, env.callEngine().statusCode) - - lo, hi := env.stackTopAsV128() - - if is32bit { - actualFs := [4]float32{ - math.Float32frombits(uint32(lo)), - math.Float32frombits(uint32(lo >> 32)), - math.Float32frombits(uint32(hi)), - math.Float32frombits(uint32(hi >> 32)), - } - f1Original, f2Original, f3Original, f4Original := math.Float32frombits(binary.LittleEndian.Uint32(tc.v[:4])), - math.Float32frombits(binary.LittleEndian.Uint32(tc.v[4:8])), - math.Float32frombits(binary.LittleEndian.Uint32(tc.v[8:12])), - math.Float32frombits(binary.LittleEndian.Uint32(tc.v[12:])) - - var expFs [4]float32 - switch tc.kind { - case wazeroir.OperationKindV128Ceil: - expFs[0] = float32(math.Ceil(float64(f1Original))) - expFs[1] = float32(math.Ceil(float64(f2Original))) - expFs[2] = float32(math.Ceil(float64(f3Original))) - expFs[3] = float32(math.Ceil(float64(f4Original))) - case wazeroir.OperationKindV128Floor: - expFs[0] = float32(math.Floor(float64(f1Original))) - expFs[1] = float32(math.Floor(float64(f2Original))) - expFs[2] = float32(math.Floor(float64(f3Original))) - expFs[3] = float32(math.Floor(float64(f4Original))) - case wazeroir.OperationKindV128Trunc: - expFs[0] = float32(math.Trunc(float64(f1Original))) - expFs[1] = float32(math.Trunc(float64(f2Original))) - expFs[2] = float32(math.Trunc(float64(f3Original))) - expFs[3] = float32(math.Trunc(float64(f4Original))) - case wazeroir.OperationKindV128Nearest: - expFs[0] = moremath.WasmCompatNearestF32(f1Original) - expFs[1] = moremath.WasmCompatNearestF32(f2Original) - expFs[2] = moremath.WasmCompatNearestF32(f3Original) - expFs[3] = moremath.WasmCompatNearestF32(f4Original) - } - - for i := range expFs { - exp, actual := expFs[i], actualFs[i] - if math.IsNaN(float64(exp)) { - require.True(t, math.IsNaN(float64(actual))) - } else { - require.Equal(t, exp, actual) - } - } - } else { - actualFs := [2]float64{math.Float64frombits(lo), math.Float64frombits(hi)} - f1Original, f2Original := math.Float64frombits(binary.LittleEndian.Uint64(tc.v[:8])), math.Float64frombits(binary.LittleEndian.Uint64(tc.v[8:])) - - var expFs [2]float64 - switch tc.kind { - case wazeroir.OperationKindV128Ceil: - expFs[0] = math.Ceil(f1Original) - expFs[1] = math.Ceil(f2Original) - case wazeroir.OperationKindV128Floor: - expFs[0] = math.Floor(f1Original) - expFs[1] = math.Floor(f2Original) - case wazeroir.OperationKindV128Trunc: - expFs[0] = math.Trunc(f1Original) - expFs[1] = math.Trunc(f2Original) - case wazeroir.OperationKindV128Nearest: - expFs[0] = moremath.WasmCompatNearestF64(f1Original) - expFs[1] = moremath.WasmCompatNearestF64(f2Original) - } - - for i := range expFs { - exp, actual := expFs[i], actualFs[i] - if math.IsNaN(exp) { - require.True(t, math.IsNaN(actual)) - } else { - require.Equal(t, exp, actual) - } - } - } - }) - } -} - -func TestCompiler_compileV128_Pmax_Pmin(t *testing.T) { - tests := []struct { - name string - shape wazeroir.Shape - kind wazeroir.OperationKind - x1, x2, exp [16]byte - }{ - { - name: "f32 pmin", - shape: wazeroir.ShapeF32x4, - kind: wazeroir.OperationKindV128Pmin, - x1: f32x4(float32(math.Inf(1)), -1.5, 1123.5, float32(math.Inf(1))), - x2: f32x4(1.4, float32(math.Inf(-1)), -1231.5, float32(math.Inf(1))), - exp: f32x4(1.4, float32(math.Inf(-1)), -1231.5, float32(math.Inf(1))), - }, - { - name: "f32 pmin", - shape: wazeroir.ShapeF32x4, - kind: wazeroir.OperationKindV128Pmin, - x1: f32x4(float32(math.NaN()), float32(math.NaN()), float32(math.NaN()), float32(math.NaN())), - x2: f32x4(1.4, -1.5, 1.5, float32(math.Inf(1))), - exp: f32x4(float32(math.NaN()), float32(math.NaN()), float32(math.NaN()), float32(math.NaN())), - }, - { - name: "f32 pmin", - shape: wazeroir.ShapeF32x4, - kind: wazeroir.OperationKindV128Pmin, - x1: f32x4(1.4, -1.5, 1.5, float32(math.Inf(1))), - x2: f32x4(float32(math.NaN()), float32(math.NaN()), float32(math.NaN()), float32(math.NaN())), - exp: f32x4(1.4, -1.5, 1.5, float32(math.Inf(1))), - }, - { - name: "f32 pmin", - shape: wazeroir.ShapeF32x4, - kind: wazeroir.OperationKindV128Pmin, - x1: f32x4(float32(math.Inf(1)), float32(math.Inf(-1)), float32(math.Inf(-1)), float32(math.Inf(1))), - x2: f32x4(float32(math.NaN()), float32(math.NaN()), float32(math.NaN()), float32(math.NaN())), - exp: f32x4(float32(math.Inf(1)), float32(math.Inf(-1)), float32(math.Inf(-1)), float32(math.Inf(1))), - }, - { - name: "f32 pmin", - shape: wazeroir.ShapeF32x4, - kind: wazeroir.OperationKindV128Pmin, - x1: f32x4(float32(math.NaN()), float32(math.NaN()), float32(math.NaN()), float32(math.NaN())), - x2: f32x4(float32(math.Inf(1)), float32(math.Inf(-1)), float32(math.Inf(-1)), float32(math.Inf(1))), - exp: f32x4(float32(math.NaN()), float32(math.NaN()), float32(math.NaN()), float32(math.NaN())), - }, - { - name: "f64 pmin", - shape: wazeroir.ShapeF64x2, - kind: wazeroir.OperationKindV128Pmin, - x1: f64x2(math.Inf(1), -123123.1231), - x2: f64x2(-123123.1, math.Inf(-1)), - exp: f64x2(-123123.1, math.Inf(-1)), - }, - { - name: "f64 pmin", - shape: wazeroir.ShapeF64x2, - kind: wazeroir.OperationKindV128Pmin, - x1: f64x2(math.NaN(), math.NaN()), - x2: f64x2(-123123.1, 1.0), - exp: f64x2(math.NaN(), math.NaN()), - }, - { - name: "f64 pmin", - shape: wazeroir.ShapeF64x2, - kind: wazeroir.OperationKindV128Pmin, - x1: f64x2(-123123.1, 1.0), - x2: f64x2(math.NaN(), math.NaN()), - exp: f64x2(-123123.1, 1.0), - }, - { - name: "f64 pmin", - shape: wazeroir.ShapeF64x2, - kind: wazeroir.OperationKindV128Pmin, - x1: f64x2(math.NaN(), math.NaN()), - x2: f64x2(math.Inf(1), math.Inf(-1)), - exp: f64x2(math.NaN(), math.NaN()), - }, - { - name: "f64 pmin", - shape: wazeroir.ShapeF64x2, - kind: wazeroir.OperationKindV128Pmin, - x1: f64x2(math.Inf(1), math.Inf(-1)), - x2: f64x2(math.NaN(), math.NaN()), - exp: f64x2(math.Inf(1), math.Inf(-1)), - }, - { - name: "f32 pmax", - shape: wazeroir.ShapeF32x4, - kind: wazeroir.OperationKindV128Pmax, - x1: f32x4(float32(math.Inf(1)), -1.5, 1123.5, float32(math.Inf(1))), - x2: f32x4(1.4, float32(math.Inf(-1)), -1231.5, float32(math.Inf(1))), - exp: f32x4(float32(math.Inf(1)), -1.5, 1123.5, float32(math.Inf(1))), - }, - { - name: "f32 pmax", - shape: wazeroir.ShapeF32x4, - kind: wazeroir.OperationKindV128Pmax, - x1: f32x4(float32(math.NaN()), float32(math.NaN()), float32(math.NaN()), float32(math.NaN())), - x2: f32x4(1.4, -1.5, 1.5, float32(math.Inf(1))), - exp: f32x4(float32(math.NaN()), float32(math.NaN()), float32(math.NaN()), float32(math.NaN())), - }, - { - name: "f32 pmax", - shape: wazeroir.ShapeF32x4, - kind: wazeroir.OperationKindV128Pmax, - x1: f32x4(1.4, -1.5, 1.5, float32(math.Inf(1))), - x2: f32x4(float32(math.NaN()), float32(math.NaN()), float32(math.NaN()), float32(math.NaN())), - exp: f32x4(1.4, -1.5, 1.5, float32(math.Inf(1))), - }, - { - name: "f32 pmax", - shape: wazeroir.ShapeF32x4, - kind: wazeroir.OperationKindV128Pmax, - x1: f32x4(float32(math.Inf(1)), float32(math.Inf(-1)), float32(math.Inf(-1)), float32(math.Inf(1))), - x2: f32x4(float32(math.NaN()), float32(math.NaN()), float32(math.NaN()), float32(math.NaN())), - exp: f32x4(float32(math.Inf(1)), float32(math.Inf(-1)), float32(math.Inf(-1)), float32(math.Inf(1))), - }, - { - name: "f32 pmax", - shape: wazeroir.ShapeF32x4, - kind: wazeroir.OperationKindV128Pmax, - x1: f32x4(float32(math.NaN()), float32(math.NaN()), float32(math.NaN()), float32(math.NaN())), - x2: f32x4(float32(math.Inf(1)), float32(math.Inf(-1)), float32(math.Inf(-1)), float32(math.Inf(1))), - exp: f32x4(float32(math.NaN()), float32(math.NaN()), float32(math.NaN()), float32(math.NaN())), - }, - { - name: "f64 pmax", - shape: wazeroir.ShapeF64x2, - kind: wazeroir.OperationKindV128Pmax, - x1: f64x2(math.Inf(1), -123123.1231), - x2: f64x2(-123123.1, math.Inf(-1)), - exp: f64x2(math.Inf(1), -123123.1231), - }, - { - name: "f64 pmax", - shape: wazeroir.ShapeF64x2, - kind: wazeroir.OperationKindV128Pmax, - x1: f64x2(math.NaN(), math.NaN()), - x2: f64x2(-123123.1, 1.0), - exp: f64x2(math.NaN(), math.NaN()), - }, - { - name: "f64 pmax", - shape: wazeroir.ShapeF64x2, - kind: wazeroir.OperationKindV128Pmax, - x1: f64x2(-123123.1, 1.0), - x2: f64x2(math.NaN(), math.NaN()), - exp: f64x2(-123123.1, 1.0), - }, - { - name: "f64 pmax", - shape: wazeroir.ShapeF64x2, - kind: wazeroir.OperationKindV128Pmax, - x1: f64x2(math.NaN(), math.NaN()), - x2: f64x2(math.Inf(1), math.Inf(-1)), - exp: f64x2(math.NaN(), math.NaN()), - }, - { - name: "f64 pmax", - shape: wazeroir.ShapeF64x2, - kind: wazeroir.OperationKindV128Pmax, - x1: f64x2(math.Inf(1), math.Inf(-1)), - x2: f64x2(math.NaN(), math.NaN()), - exp: f64x2(math.Inf(1), math.Inf(-1)), - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, - &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.x1[:8]), binary.LittleEndian.Uint64(tc.x1[8:])))) - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.x2[:8]), binary.LittleEndian.Uint64(tc.x2[8:])))) - require.NoError(t, err) - - is32bit := tc.shape == wazeroir.ShapeF32x4 - switch tc.kind { - case wazeroir.OperationKindV128Pmin: - err = compiler.compileV128Pmin(operationPtr(wazeroir.NewOperationV128Pmin(tc.shape))) - case wazeroir.OperationKindV128Pmax: - err = compiler.compileV128Pmax(operationPtr(wazeroir.NewOperationV128Pmax(tc.shape))) - } - require.NoError(t, err) - - requireRuntimeLocationStackPointerEqual(t, uint64(2), compiler) - require.Equal(t, 1, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - require.Equal(t, nativeCallStatusCodeReturned, env.callEngine().statusCode) - - lo, hi := env.stackTopAsV128() - - if is32bit { - actualFs := [4]float32{ - math.Float32frombits(uint32(lo)), - math.Float32frombits(uint32(lo >> 32)), - math.Float32frombits(uint32(hi)), - math.Float32frombits(uint32(hi >> 32)), - } - expFs := [4]float32{ - math.Float32frombits(binary.LittleEndian.Uint32(tc.exp[:4])), - math.Float32frombits(binary.LittleEndian.Uint32(tc.exp[4:8])), - math.Float32frombits(binary.LittleEndian.Uint32(tc.exp[8:12])), - math.Float32frombits(binary.LittleEndian.Uint32(tc.exp[12:])), - } - for i := range expFs { - exp, actual := expFs[i], actualFs[i] - if math.IsNaN(float64(exp)) { - require.True(t, math.IsNaN(float64(actual))) - } else { - require.Equal(t, exp, actual) - } - } - } else { - actualFs := [2]float64{ - math.Float64frombits(lo), math.Float64frombits(hi), - } - expFs := [2]float64{ - math.Float64frombits(binary.LittleEndian.Uint64(tc.exp[:8])), - math.Float64frombits(binary.LittleEndian.Uint64(tc.exp[8:])), - } - for i := range expFs { - exp, actual := expFs[i], actualFs[i] - if math.IsNaN(exp) { - require.True(t, math.IsNaN(actual)) - } else { - require.Equal(t, exp, actual) - } - } - } - }) - } -} - -func TestCompiler_compileV128ExtMul(t *testing.T) { - tests := []struct { - name string - shape wazeroir.Shape - signed, useLow bool - x1, x2, exp [16]byte - }{ - { - name: "i8x16s low", - shape: wazeroir.ShapeI8x16, - signed: true, - useLow: true, - x1: [16]byte{}, x2: [16]byte{}, - exp: i16x8(0, 0, 0, 0, 0, 0, 0, 0), - }, - { - name: "i8x16s low", - shape: wazeroir.ShapeI8x16, - signed: true, - useLow: true, - x1: [16]byte{ - 255, 255, 255, 255, 255, 255, 255, 255, - 0, 0, 0, 0, 0, 0, 0, 0, - }, - x2: [16]byte{ - i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), - i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), - i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), - i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), - }, - exp: i16x8(128, 128, 128, 128, 128, 128, 128, 128), - }, - { - name: "i8x16s low", - shape: wazeroir.ShapeI8x16, - signed: true, - useLow: true, - x1: [16]byte{ - 255, 255, 255, 255, 255, 255, 255, 255, - 0, 0, 0, 0, 0, 0, 0, 0, - }, - x2: [16]byte{ - 255, 255, 255, 255, 255, 255, 255, 255, - 0, 0, 0, 0, 0, 0, 0, 0, - }, - exp: i16x8(1, 1, 1, 1, 1, 1, 1, 1), - }, - { - name: "i8x16s low", - shape: wazeroir.ShapeI8x16, - signed: true, - useLow: true, - x1: [16]byte{ - i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), - i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), - 0, 0, 0, 0, 0, 0, 0, 0, - }, - x2: [16]byte{ - i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), - i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), - 0, 0, 0, 0, 0, 0, 0, 0, - }, - exp: i16x8(16384, 16384, 16384, 16384, 16384, 16384, 16384, 16384), - }, - { - name: "i8x16s hi", - shape: wazeroir.ShapeI8x16, - signed: true, - useLow: false, - x1: [16]byte{}, x2: [16]byte{}, - exp: i16x8(0, 0, 0, 0, 0, 0, 0, 0), - }, - { - name: "i8x16s hi", - shape: wazeroir.ShapeI8x16, - signed: true, - useLow: false, - x1: [16]byte{ - 0, 0, 0, 0, 0, 0, 0, 0, - 255, 255, 255, 255, 255, 255, 255, 255, - }, - x2: [16]byte{ - 0, 0, 0, 0, 0, 0, 0, 0, - i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), - i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), - }, - exp: i16x8(128, 128, 128, 128, 128, 128, 128, 128), - }, - { - name: "i8x16s hi", - shape: wazeroir.ShapeI8x16, - signed: true, - useLow: false, - x1: [16]byte{ - 0, 0, 0, 0, 0, 0, 0, 0, - 255, 255, 255, 255, 255, 255, 255, 255, - }, - x2: [16]byte{ - 0, 0, 0, 0, 0, 0, 0, 0, - 255, 255, 255, 255, 255, 255, 255, 255, - }, - exp: i16x8(1, 1, 1, 1, 1, 1, 1, 1), - }, - { - name: "i8x16s hi", - shape: wazeroir.ShapeI8x16, - signed: true, - useLow: false, - x1: [16]byte{ - 0, 0, 0, 0, 0, 0, 0, 0, - i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), - i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), - }, - x2: [16]byte{ - 0, 0, 0, 0, 0, 0, 0, 0, - i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), - i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), - }, - exp: i16x8(16384, 16384, 16384, 16384, 16384, 16384, 16384, 16384), - }, - { - name: "i8x16u low", - shape: wazeroir.ShapeI8x16, - signed: false, - useLow: true, - x1: [16]byte{}, x2: [16]byte{}, - exp: i16x8(0, 0, 0, 0, 0, 0, 0, 0), - }, - { - name: "i8x16u low", - shape: wazeroir.ShapeI8x16, - signed: false, - useLow: true, - x1: [16]byte{ - 255, 255, 255, 255, 255, 255, 255, 255, - 0, 0, 0, 0, 0, 0, 0, 0, - }, - x2: [16]byte{ - i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), - i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), - i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), - 0, 0, 0, 0, - }, - exp: i16x8(32640, 32640, 32640, 32640, 32640, 32640, 32640, 32640), - }, - { - name: "i8x16u low", - shape: wazeroir.ShapeI8x16, - signed: false, - useLow: true, - x1: [16]byte{ - 255, 255, 255, 255, 255, 255, 255, 255, - 0, 0, 0, 0, 0, 0, 0, 0, - }, - x2: [16]byte{ - 255, 255, 255, 255, 255, 255, 255, 255, - 0, 0, 0, 0, 0, 0, 0, 0, - }, - exp: i16x8(i16ToU16(-511), i16ToU16(-511), i16ToU16(-511), i16ToU16(-511), - i16ToU16(-511), i16ToU16(-511), i16ToU16(-511), i16ToU16(-511)), - }, - { - name: "i8x16u low", - shape: wazeroir.ShapeI8x16, - signed: false, - useLow: true, - x1: [16]byte{ - i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), - i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), - 0, 0, 0, 0, 0, 0, 0, 0, - }, - x2: [16]byte{ - i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), - i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), - 0, 0, 0, 0, 0, 0, 0, 0, - }, - exp: i16x8(16384, 16384, 16384, 16384, 16384, 16384, 16384, 16384), - }, - { - name: "i8x16u hi", - shape: wazeroir.ShapeI8x16, - signed: false, - useLow: false, - x1: [16]byte{}, x2: [16]byte{}, - exp: i16x8(0, 0, 0, 0, 0, 0, 0, 0), - }, - { - name: "i8x16u hi", - shape: wazeroir.ShapeI8x16, - signed: false, - useLow: false, - x1: [16]byte{ - 0, 0, 0, 0, 0, 0, 0, 0, - 255, 255, 255, 255, 255, 255, 255, 255, - }, - x2: [16]byte{ - i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), - 0, 0, 0, 0, - i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), - i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), - }, - exp: i16x8(32640, 32640, 32640, 32640, 32640, 32640, 32640, 32640), - }, - { - name: "i8x16u hi", - shape: wazeroir.ShapeI8x16, - signed: false, - useLow: false, - x1: [16]byte{ - 0, 0, 0, 0, 0, 0, 0, 0, - 255, 255, 255, 255, 255, 255, 255, 255, - }, - x2: [16]byte{ - 0, 0, 0, 0, 0, 0, 0, 0, - 255, 255, 255, 255, 255, 255, 255, 255, - }, - exp: i16x8(i16ToU16(-511), i16ToU16(-511), i16ToU16(-511), i16ToU16(-511), - i16ToU16(-511), i16ToU16(-511), i16ToU16(-511), i16ToU16(-511)), - }, - { - name: "i8x16u hi", - shape: wazeroir.ShapeI8x16, - signed: false, - useLow: false, - x1: [16]byte{ - 0, 0, 0, 0, 0, 0, 0, 0, - i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), - i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), - }, - x2: [16]byte{ - 0, 0, 0, 0, 0, 0, 0, 0, - i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), - i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), - }, - exp: i16x8(16384, 16384, 16384, 16384, 16384, 16384, 16384, 16384), - }, - { - name: "i16x8s lo", - shape: wazeroir.ShapeI16x8, - signed: true, - useLow: true, - x1: [16]byte{}, - x2: [16]byte{}, - exp: [16]byte{}, - }, - { - name: "i16x8s lo", - shape: wazeroir.ShapeI16x8, - signed: true, - useLow: true, - x1: i16x8( - 16383, 16383, 16383, 16383, - 0, 0, 1, 0, - ), - x2: i16x8( - 16384, 16384, 16384, 16384, - 0, 0, 1, 0, - ), - exp: i32x4(268419072, 268419072, 268419072, 268419072), - }, - { - name: "i16x8s lo", - shape: wazeroir.ShapeI16x8, - signed: true, - useLow: true, - x1: i16x8( - i16ToU16(-32768), i16ToU16(-32768), i16ToU16(-32768), i16ToU16(-32768), - 0, 0, 1, 0, - ), - x2: i16x8( - i16ToU16(-32767), 0, i16ToU16(-32767), 0, - 0, 0, 1, 0, - ), - exp: i32x4(1073709056, 0, 1073709056, 0), - }, - { - name: "i16x8s lo", - shape: wazeroir.ShapeI16x8, - signed: true, - useLow: true, - x1: i16x8( - 65535, 65535, 65535, 65535, - 0, 0, 1, 0, - ), - x2: i16x8( - 65535, 0, 65535, 0, - 0, 0, 1, 0, - ), - exp: i32x4(1, 0, 1, 0), - }, - { - name: "i16x8s hi", - shape: wazeroir.ShapeI16x8, - signed: true, - useLow: false, - x1: [16]byte{}, - x2: [16]byte{}, - exp: [16]byte{}, - }, - { - name: "i16x8s hi", - shape: wazeroir.ShapeI16x8, - signed: true, - useLow: false, - x1: i16x8( - 0, 0, 1, 0, - 16383, 16383, 16383, 16383, - ), - x2: i16x8( - 0, 0, 1, 0, - 16384, 16384, 16384, 16384, - ), - exp: i32x4(268419072, 268419072, 268419072, 268419072), - }, - { - name: "i16x8s hi", - shape: wazeroir.ShapeI16x8, - signed: true, - useLow: false, - x1: i16x8( - 0, 0, 1, 0, - i16ToU16(-32768), i16ToU16(-32768), i16ToU16(-32768), i16ToU16(-32768), - ), - x2: i16x8( - 0, 0, 1, 0, - i16ToU16(-32767), 0, i16ToU16(-32767), 0, - ), - exp: i32x4(1073709056, 0, 1073709056, 0), - }, - { - name: "i16x8s hi", - shape: wazeroir.ShapeI16x8, - signed: true, - useLow: false, - x1: i16x8( - 0, 0, 1, 0, - 65535, 65535, 65535, 65535, - ), - x2: i16x8( - 0, 0, 1, 0, - - 65535, 0, 65535, 0, - ), - exp: i32x4(1, 0, 1, 0), - }, - { - name: "i16x8u lo", - shape: wazeroir.ShapeI16x8, - signed: false, - useLow: true, - x1: [16]byte{}, - x2: [16]byte{}, - exp: [16]byte{}, - }, - { - name: "i16x8u lo", - shape: wazeroir.ShapeI16x8, - signed: false, - useLow: true, - x1: i16x8( - 16383, 16383, 16383, 16383, - 0, 0, 1, 0, - ), - x2: i16x8( - 16384, 16384, 16384, 16384, - 0, 0, 1, 0, - ), - exp: i32x4(268419072, 268419072, 268419072, 268419072), - }, - { - name: "i16x8u lo", - shape: wazeroir.ShapeI16x8, - signed: false, - useLow: true, - x1: i16x8( - i16ToU16(-32768), i16ToU16(-32768), i16ToU16(-32768), i16ToU16(-32768), - 0, 0, 1, 0, - ), - x2: i16x8( - i16ToU16(-32767), 0, i16ToU16(-32767), 0, - 0, 0, 1, 0, - ), - exp: i32x4(1073774592, 0, 1073774592, 0), - }, - { - name: "i16x8u lo", - shape: wazeroir.ShapeI16x8, - signed: false, - useLow: true, - x1: i16x8( - 65535, 65535, 65535, 65535, - 0, 0, 1, 0, - ), - x2: i16x8( - 65535, 0, 65535, 0, - 0, 0, 1, 0, - ), - exp: i32x4(i32ToU32(-131071), 0, i32ToU32(-131071), 0), - }, - { - name: "i16x8u hi", - shape: wazeroir.ShapeI16x8, - signed: false, - useLow: false, - x1: [16]byte{}, - x2: [16]byte{}, - exp: [16]byte{}, - }, - { - name: "i16x8u hi", - shape: wazeroir.ShapeI16x8, - signed: false, - useLow: false, - x1: i16x8( - 0, 0, 1, 0, - 16383, 16383, 16383, 16383, - ), - x2: i16x8( - 0, 0, 1, 0, - 16384, 16384, 16384, 16384, - ), - exp: i32x4(268419072, 268419072, 268419072, 268419072), - }, - { - name: "i16x8u hi", - shape: wazeroir.ShapeI16x8, - signed: false, - useLow: false, - x1: i16x8( - 0, 0, 1, 0, - i16ToU16(-32768), i16ToU16(-32768), i16ToU16(-32768), i16ToU16(-32768), - ), - x2: i16x8( - 0, 0, 1, 0, - i16ToU16(-32767), 0, i16ToU16(-32767), 0, - ), - exp: i32x4(1073774592, 0, 1073774592, 0), - }, - { - name: "i16x8u hi", - shape: wazeroir.ShapeI16x8, - signed: false, - useLow: false, - x1: i16x8( - 0, 0, 1, 0, - 65535, 65535, 65535, 65535, - ), - x2: i16x8( - 0, 0, 1, 0, - 65535, 0, 65535, 0, - ), - exp: i32x4(i32ToU32(-131071), 0, i32ToU32(-131071), 0), - }, - { - name: "i32x4s lo", - shape: wazeroir.ShapeI32x4, - signed: true, - useLow: true, - x1: [16]byte{}, - x2: [16]byte{}, - exp: [16]byte{}, - }, - { - name: "i32x4s lo", - shape: wazeroir.ShapeI32x4, - signed: true, - useLow: true, - x1: i32x4( - 1, i32ToU32(-1), - 0, 0, - ), - x2: i32x4( - i32ToU32(-1), 1, - 0, 0, - ), - exp: i64x2(i64ToU64(-1), i64ToU64(-1)), - }, - { - name: "i32x4s lo", - shape: wazeroir.ShapeI32x4, - signed: true, - useLow: true, - x1: i32x4( - 1073741824, 4294967295, - 0, 0, - ), - x2: i32x4( - 1073741824, 4294967295, - 0, 0, - ), - exp: i64x2(1152921504606846976, 1), - }, - { - name: "i32x4s hi", - shape: wazeroir.ShapeI32x4, - signed: true, - useLow: false, - x1: [16]byte{}, - x2: [16]byte{}, - exp: [16]byte{}, - }, - { - name: "i32x4s hi", - shape: wazeroir.ShapeI32x4, - signed: true, - useLow: false, - x1: i32x4( - 0, 0, - 1, i32ToU32(-1), - ), - x2: i32x4( - 0, 0, - i32ToU32(-1), 1, - ), - exp: i64x2(i64ToU64(-1), i64ToU64(-1)), - }, - { - name: "i32x4s hi", - shape: wazeroir.ShapeI32x4, - signed: true, - useLow: false, - x1: i32x4( - 0, 0, - 1073741824, 4294967295, - ), - x2: i32x4( - 0, 0, - 1073741824, 4294967295, - ), - exp: i64x2(1152921504606846976, 1), - }, - { - name: "i32x4u lo", - shape: wazeroir.ShapeI32x4, - signed: false, - useLow: true, - x1: [16]byte{}, - x2: [16]byte{}, - exp: [16]byte{}, - }, - { - name: "i32x4u lo", - shape: wazeroir.ShapeI32x4, - signed: false, - useLow: true, - x1: i32x4( - 1, i32ToU32(-1), - 0, 0, - ), - x2: i32x4( - i32ToU32(-1), 1, - 0, 0, - ), - exp: i64x2(4294967295, 4294967295), - }, - { - name: "i32x4u lo", - shape: wazeroir.ShapeI32x4, - signed: false, - useLow: true, - x1: i32x4( - 1073741824, 4294967295, - 0, 0, - ), - x2: i32x4( - 1073741824, 4294967295, - 0, 0, - ), - exp: i64x2(1152921504606846976, i64ToU64(-8589934591)), - }, - { - name: "i32x4u hi", - shape: wazeroir.ShapeI32x4, - signed: false, - useLow: false, - x1: [16]byte{}, - x2: [16]byte{}, - exp: [16]byte{}, - }, - { - name: "i32x4u hi", - shape: wazeroir.ShapeI32x4, - signed: false, - useLow: false, - x1: i32x4( - 0, 0, - 1, i32ToU32(-1), - ), - x2: i32x4( - 0, 0, - i32ToU32(-1), 1, - ), - exp: i64x2(4294967295, 4294967295), - }, - { - name: "i32x4u hi", - shape: wazeroir.ShapeI32x4, - signed: false, - useLow: false, - x1: i32x4( - 0, 0, - 1073741824, 4294967295, - ), - x2: i32x4( - 0, 0, - 1073741824, 4294967295, - ), - exp: i64x2(1152921504606846976, i64ToU64(-8589934591)), - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, - &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.x1[:8]), binary.LittleEndian.Uint64(tc.x1[8:])))) - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.x2[:8]), binary.LittleEndian.Uint64(tc.x2[8:])))) - require.NoError(t, err) - - err = compiler.compileV128ExtMul(operationPtr(wazeroir.NewOperationV128ExtMul(tc.shape, tc.signed, tc.useLow))) - require.NoError(t, err) - - requireRuntimeLocationStackPointerEqual(t, uint64(2), compiler) - require.Equal(t, 1, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - require.Equal(t, nativeCallStatusCodeReturned, env.callEngine().statusCode) - - lo, hi := env.stackTopAsV128() - var actual [16]byte - binary.LittleEndian.PutUint64(actual[:8], lo) - binary.LittleEndian.PutUint64(actual[8:], hi) - require.Equal(t, tc.exp, actual) - }) - } -} - -func TestCompiler_compileV128Extend(t *testing.T) { - tests := []struct { - name string - shape wazeroir.Shape - signed, useLow bool - v, exp [16]byte - }{ - { - name: "i8x16s hi", - shape: wazeroir.ShapeI8x16, - signed: true, - useLow: false, - v: [16]byte{}, - exp: [16]byte{}, - }, - { - name: "i8x16s hi", - shape: wazeroir.ShapeI8x16, - signed: true, - useLow: false, - v: [16]byte{ - 0, 0, 0, 0, 0, 0, 0, 0, - i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), - }, - exp: i16x8(i16ToU16(-1), i16ToU16(-1), i16ToU16(-1), i16ToU16(-1), i16ToU16(-1), i16ToU16(-1), i16ToU16(-1), i16ToU16(-1)), - }, - { - name: "i8x16s hi", - shape: wazeroir.ShapeI8x16, - signed: true, - useLow: false, - v: [16]byte{ - 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 1, 1, 1, 1, 1, - }, - exp: i16x8(1, 1, 1, 1, 1, 1, 1, 1), - }, - { - name: "i8x16s hi", - shape: wazeroir.ShapeI8x16, - signed: true, - useLow: false, - v: [16]byte{ - i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), - 0, 0, 0, 0, 0, 0, 0, 0, - }, - exp: i16x8(0, 0, 0, 0, 0, 0, 0, 0), - }, - { - name: "i8x16s lo", - shape: wazeroir.ShapeI8x16, - signed: true, - useLow: true, - v: [16]byte{}, - exp: [16]byte{}, - }, - { - name: "i8x16s lo", - shape: wazeroir.ShapeI8x16, - signed: true, - useLow: true, - v: [16]byte{ - i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), - 0, 0, 0, 0, 0, 0, 0, 0, - }, - exp: i16x8(i16ToU16(-1), i16ToU16(-1), i16ToU16(-1), i16ToU16(-1), i16ToU16(-1), i16ToU16(-1), i16ToU16(-1), i16ToU16(-1)), - }, - { - name: "i8x16s lo", - shape: wazeroir.ShapeI8x16, - signed: true, - useLow: true, - v: [16]byte{ - 1, 1, 1, 1, 1, 1, 1, 1, - 0, 0, 0, 0, 0, 0, 0, 0, - }, - exp: i16x8(1, 1, 1, 1, 1, 1, 1, 1), - }, - { - name: "i8x16s lo", - shape: wazeroir.ShapeI8x16, - signed: true, - useLow: true, - v: [16]byte{ - 0, 0, 0, 0, 0, 0, 0, 0, - i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), - }, - exp: i16x8(0, 0, 0, 0, 0, 0, 0, 0), - }, - // unsigned - { - name: "i8x16u hi", - shape: wazeroir.ShapeI8x16, - signed: false, - useLow: false, - v: [16]byte{}, - exp: [16]byte{}, - }, - { - name: "i8x16u hi", - shape: wazeroir.ShapeI8x16, - signed: false, - useLow: false, - v: [16]byte{ - 0, 0, 0, 0, 0, 0, 0, 0, - i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), - }, - exp: i16x8(255, 255, 255, 255, 255, 255, 255, 255), - }, - { - name: "i8x16u hi", - shape: wazeroir.ShapeI8x16, - signed: false, - useLow: false, - v: [16]byte{ - 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 1, 1, 1, 1, 1, - }, - exp: i16x8(1, 1, 1, 1, 1, 1, 1, 1), - }, - { - name: "i8x16u hi", - shape: wazeroir.ShapeI8x16, - signed: false, - useLow: false, - v: [16]byte{ - i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), - 0, 0, 0, 0, 0, 0, 0, 0, - }, - exp: i16x8(0, 0, 0, 0, 0, 0, 0, 0), - }, - { - name: "i8x16u lo", - shape: wazeroir.ShapeI8x16, - signed: false, - useLow: true, - v: [16]byte{}, - exp: [16]byte{}, - }, - { - name: "i8x16u lo", - shape: wazeroir.ShapeI8x16, - signed: false, - useLow: true, - v: [16]byte{ - i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), - 0, 0, 0, 0, 0, 0, 0, 0, - }, - exp: i16x8(255, 255, 255, 255, 255, 255, 255, 255), - }, - { - name: "i8x16u lo", - shape: wazeroir.ShapeI8x16, - signed: false, - useLow: true, - v: [16]byte{ - 1, 1, 1, 1, 1, 1, 1, 1, - 0, 0, 0, 0, 0, 0, 0, 0, - }, - exp: i16x8(1, 1, 1, 1, 1, 1, 1, 1), - }, - { - name: "i8x16u lo", - shape: wazeroir.ShapeI8x16, - signed: false, - useLow: true, - v: [16]byte{ - 0, 0, 0, 0, 0, 0, 0, 0, - i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), - }, - exp: i16x8(0, 0, 0, 0, 0, 0, 0, 0), - }, - { - name: "i16x8s hi", - shape: wazeroir.ShapeI16x8, - signed: true, - useLow: false, - v: [16]byte{}, - exp: [16]byte{}, - }, - { - name: "i16x8s hi", - shape: wazeroir.ShapeI16x8, - signed: true, - useLow: false, - v: i16x8(1, 1, 1, 1, 0, 0, 0, 0), - exp: i32x4(0, 0, 0, 0), - }, - { - name: "i16x8s hi", - shape: wazeroir.ShapeI16x8, - signed: true, - useLow: false, - v: i16x8(0, 0, 0, 0, i16ToU16(-1), i16ToU16(-1), i16ToU16(-1), i16ToU16(-1)), - exp: i32x4(i32ToU32(-1), i32ToU32(-1), i32ToU32(-1), i32ToU32(-1)), - }, - { - name: "i16x8s hi", - shape: wazeroir.ShapeI16x8, - signed: true, - useLow: false, - v: i16x8(0, 0, 0, 0, 123, 0, 123, 0), - exp: i32x4(123, 0, 123, 0), - }, - { - name: "i16x8s lo", - shape: wazeroir.ShapeI16x8, - signed: true, - useLow: true, - v: [16]byte{}, - exp: [16]byte{}, - }, - { - name: "i16x8s lo", - shape: wazeroir.ShapeI16x8, - signed: true, - useLow: true, - v: i16x8(0, 0, 0, 0, 1, 1, 1, 1), - exp: i32x4(0, 0, 0, 0), - }, - { - name: "i16x8s lo", - shape: wazeroir.ShapeI16x8, - signed: true, - useLow: true, - v: i16x8(i16ToU16(-1), i16ToU16(-1), i16ToU16(-1), i16ToU16(-1), 0, 0, 0, 0), - exp: i32x4(i32ToU32(-1), i32ToU32(-1), i32ToU32(-1), i32ToU32(-1)), - }, - { - name: "i16x8s lo", - shape: wazeroir.ShapeI16x8, - signed: true, - useLow: true, - v: i16x8(123, 0, 123, 0, 0, 0, 0, 0), - exp: i32x4(123, 0, 123, 0), - }, - { - name: "i16x8u hi", - shape: wazeroir.ShapeI16x8, - signed: false, - useLow: false, - v: [16]byte{}, - exp: [16]byte{}, - }, - { - name: "i16x8u hi", - shape: wazeroir.ShapeI16x8, - signed: false, - useLow: false, - v: i16x8(1, 1, 1, 1, 0, 0, 0, 0), - exp: i32x4(0, 0, 0, 0), - }, - { - name: "i16x8u hi", - shape: wazeroir.ShapeI16x8, - signed: false, - useLow: false, - v: i16x8(0, 0, 0, 0, i16ToU16(-1), i16ToU16(-1), i16ToU16(-1), i16ToU16(-1)), - exp: i32x4(65535, 65535, 65535, 65535), - }, - { - name: "i16x8u hi", - shape: wazeroir.ShapeI16x8, - signed: false, - useLow: false, - v: i16x8(0, 0, 0, 0, 123, 0, 123, 0), - exp: i32x4(123, 0, 123, 0), - }, - { - name: "i16x8u lo", - shape: wazeroir.ShapeI16x8, - signed: false, - useLow: true, - v: [16]byte{}, - exp: [16]byte{}, - }, - { - name: "i16x8u lo", - shape: wazeroir.ShapeI16x8, - signed: false, - useLow: true, - v: i16x8(0, 0, 0, 0, 1, 1, 1, 1), - exp: i32x4(0, 0, 0, 0), - }, - { - name: "i16x8u lo", - shape: wazeroir.ShapeI16x8, - signed: false, - useLow: true, - v: i16x8(i16ToU16(-1), i16ToU16(-1), i16ToU16(-1), i16ToU16(-1), 0, 0, 0, 0), - exp: i32x4(65535, 65535, 65535, 65535), - }, - { - name: "i16x8u lo", - shape: wazeroir.ShapeI16x8, - signed: false, - useLow: true, - v: i16x8(123, 0, 123, 0, 0, 0, 0, 0), - exp: i32x4(123, 0, 123, 0), - }, - { - name: "i32x4s hi", - shape: wazeroir.ShapeI32x4, - signed: true, - useLow: false, - v: [16]byte{}, - exp: [16]byte{}, - }, - { - name: "i32x4s hi", - shape: wazeroir.ShapeI32x4, - signed: true, - useLow: false, - v: i32x4(0, 0, 1, i32ToU32(-1)), - exp: i64x2(1, i64ToU64(-1)), - }, - { - name: "i32x4s hi", - shape: wazeroir.ShapeI32x4, - signed: true, - useLow: false, - v: i32x4(1, i32ToU32(-1), 0, 0), - exp: i64x2(0, 0), - }, - { - name: "i32x4s hi", - shape: wazeroir.ShapeI32x4, - signed: true, - useLow: false, - v: i32x4(1, i32ToU32(-1), 123, 123), - exp: i64x2(123, 123), - }, - { - name: "i32x4s lo", - shape: wazeroir.ShapeI32x4, - signed: true, - useLow: true, - v: [16]byte{}, - exp: [16]byte{}, - }, - { - name: "i32x4s lo", - shape: wazeroir.ShapeI32x4, - signed: true, - useLow: true, - v: i32x4(1, i32ToU32(-1), 0, 0), - exp: i64x2(1, i64ToU64(-1)), - }, - { - name: "i32x4s lo", - shape: wazeroir.ShapeI32x4, - signed: true, - useLow: true, - v: i32x4(0, 0, 1, i32ToU32(-1)), - exp: i64x2(0, 0), - }, - { - name: "i32x4s lo", - shape: wazeroir.ShapeI32x4, - signed: true, - useLow: true, - v: i32x4(123, 123, 1, i32ToU32(-1)), - exp: i64x2(123, 123), - }, - { - name: "i32x4u hi", - shape: wazeroir.ShapeI32x4, - signed: false, - useLow: false, - v: [16]byte{}, - exp: [16]byte{}, - }, - { - name: "i32x4u hi", - shape: wazeroir.ShapeI32x4, - signed: false, - useLow: false, - v: i32x4(0, 0, 1, i32ToU32(-1)), - exp: i64x2(1, 4294967295), - }, - { - name: "i32x4u hi", - shape: wazeroir.ShapeI32x4, - signed: false, - useLow: false, - v: i32x4(1, i32ToU32(-1), 0, 0), - exp: i64x2(0, 0), - }, - { - name: "i32x4u hi", - shape: wazeroir.ShapeI32x4, - signed: false, - useLow: false, - v: i32x4(1, i32ToU32(-1), 123, 123), - exp: i64x2(123, 123), - }, - { - name: "i32x4u lo", - shape: wazeroir.ShapeI32x4, - signed: false, - useLow: true, - v: [16]byte{}, - exp: [16]byte{}, - }, - { - name: "i32x4u lo", - shape: wazeroir.ShapeI32x4, - signed: false, - useLow: true, - v: i32x4(1, i32ToU32(-1), 0, 0), - exp: i64x2(1, 4294967295), - }, - { - name: "i32x4u lo", - shape: wazeroir.ShapeI32x4, - signed: false, - useLow: true, - v: i32x4(0, 0, 1, i32ToU32(-1)), - exp: i64x2(0, 0), - }, - { - name: "i32x4u lo", - shape: wazeroir.ShapeI32x4, - signed: false, - useLow: true, - v: i32x4(123, 123, 1, i32ToU32(-1)), - exp: i64x2(123, 123), - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, - &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.v[:8]), binary.LittleEndian.Uint64(tc.v[8:])))) - require.NoError(t, err) - - err = compiler.compileV128Extend(operationPtr(wazeroir.NewOperationV128Extend(tc.shape, tc.signed, tc.useLow))) - require.NoError(t, err) - - requireRuntimeLocationStackPointerEqual(t, uint64(2), compiler) - require.Equal(t, 1, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - require.Equal(t, nativeCallStatusCodeReturned, env.callEngine().statusCode) - - lo, hi := env.stackTopAsV128() - var actual [16]byte - binary.LittleEndian.PutUint64(actual[:8], lo) - binary.LittleEndian.PutUint64(actual[8:], hi) - require.Equal(t, tc.exp, actual) - }) - } -} - -func TestCompiler_compileV128Q15mulrSatS(t *testing.T) { - tests := []struct { - name string - x1, x2, exp [16]byte - }{ - { - name: "1", - x1: i16x8(0, 0, 0, 0, 0, 0, 0, 0), - x2: i16x8(0, 0, 0, 0, 0, 0, 0, 0), - exp: i16x8(0, 0, 0, 0, 0, 0, 0, 0), - }, - { - name: "2", - x1: i16x8(0, 0, 0, 0, 0, 0, 0, 0), - x2: i16x8(1, 1, 1, 1, 1, 1, 1, 1), - exp: i16x8(0, 0, 0, 0, 0, 0, 0, 0), - }, - { - name: "3", - x1: i16x8(1, 1, 1, 1, 1, 1, 1, 1), - x2: i16x8(1, 1, 1, 1, 1, 1, 1, 1), - exp: i16x8(0, 0, 0, 0, 0, 0, 0, 0), - }, - { - name: "4", - x1: i16x8(65535, 65535, 65535, 65535, 65535, 65535, 65535, 65535), - x2: i16x8(1, 1, 1, 1, 1, 1, 1, 1), - exp: i16x8(0, 0, 0, 0, 0, 0, 0, 0), - }, - { - name: "5", - x1: i16x8(32767, 32767, 32767, 32767, 32767, 32767, 32767, 32767), - x2: i16x8(32767, 32767, 32767, 32767, 32767, 32767, 32767, 32767), - exp: i16x8(32766, 32766, 32766, 32766, 32766, 32766, 32766, 32766), - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, - &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.x1[:8]), binary.LittleEndian.Uint64(tc.x1[8:])))) - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.x2[:8]), binary.LittleEndian.Uint64(tc.x2[8:])))) - require.NoError(t, err) - - err = compiler.compileV128Q15mulrSatS(operationPtr(wazeroir.NewOperationV128Q15mulrSatS())) - require.NoError(t, err) - - requireRuntimeLocationStackPointerEqual(t, uint64(2), compiler) - require.Equal(t, 1, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - require.Equal(t, nativeCallStatusCodeReturned, env.callEngine().statusCode) - - lo, hi := env.stackTopAsV128() - var actual [16]byte - binary.LittleEndian.PutUint64(actual[:8], lo) - binary.LittleEndian.PutUint64(actual[8:], hi) - require.Equal(t, tc.exp, actual) - }) - } -} - -func TestCompiler_compileFloatPromote(t *testing.T) { - tests := []struct { - name string - v, exp [16]byte - }{ - { - name: "1", - v: f32x4(float32(0x1.8f867ep+125), float32(0x1.8f867ep+125), float32(0x1.8f867ep+125), float32(0x1.8f867ep+125)), - exp: f64x2(6.6382536710104395e+37, 6.6382536710104395e+37), - }, - { - name: "2", - v: f32x4(float32(0x1.8f867ep+125), float32(0x1.8f867ep+125), 0, 0), - exp: f64x2(6.6382536710104395e+37, 6.6382536710104395e+37), - }, - { - name: "3", - v: f32x4(0, 0, float32(0x1.8f867ep+125), float32(0x1.8f867ep+125)), - exp: f64x2(0, 0), - }, - { - name: "4", - v: f32x4(float32(math.NaN()), float32(math.NaN()), float32(0x1.8f867ep+125), float32(0x1.8f867ep+125)), - exp: f64x2(math.NaN(), math.NaN()), - }, - { - name: "5", - v: f32x4(float32(math.Inf(1)), float32(math.Inf(-1)), float32(0x1.8f867ep+125), float32(0x1.8f867ep+125)), - exp: f64x2(math.Inf(1), math.Inf(-1)), - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, - &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.v[:8]), binary.LittleEndian.Uint64(tc.v[8:])))) - require.NoError(t, err) - - err = compiler.compileV128FloatPromote(operationPtr(wazeroir.NewOperationV128FloatPromote())) - require.NoError(t, err) - - requireRuntimeLocationStackPointerEqual(t, uint64(2), compiler) - require.Equal(t, 1, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - require.Equal(t, nativeCallStatusCodeReturned, env.callEngine().statusCode) - - lo, hi := env.stackTopAsV128() - actualFs := [2]float64{ - math.Float64frombits(lo), math.Float64frombits(hi), - } - expFs := [2]float64{ - math.Float64frombits(binary.LittleEndian.Uint64(tc.exp[:8])), - math.Float64frombits(binary.LittleEndian.Uint64(tc.exp[8:])), - } - for i := range expFs { - exp, actual := expFs[i], actualFs[i] - if math.IsNaN(exp) { - require.True(t, math.IsNaN(actual)) - } else { - require.Equal(t, exp, actual) - } - } - }) - } -} - -func TestCompiler_compileV128FloatDemote(t *testing.T) { - tests := []struct { - name string - v, exp [16]byte - }{ - { - name: "1", - v: f64x2(0, 0), - exp: f32x4(0, 0, 0, 0), - }, - { - name: "2", - v: f64x2(0x1.fffffe0000000p-127, 0x1.fffffe0000000p-127), - exp: f32x4(0x1p-126, 0x1p-126, 0, 0), - }, - { - name: "3", - v: f64x2(0x1.fffffep+127, 0x1.fffffep+127), - exp: f32x4(0x1.fffffep+127, 0x1.fffffep+127, 0, 0), - }, - { - name: "4", - v: f64x2(math.NaN(), math.NaN()), - exp: f32x4(float32(math.NaN()), float32(math.NaN()), 0, 0), - }, - { - name: "5", - v: f64x2(math.Inf(1), math.Inf(-1)), - exp: f32x4(float32(math.Inf(1)), float32(math.Inf(-1)), 0, 0), - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, - &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.v[:8]), binary.LittleEndian.Uint64(tc.v[8:])))) - require.NoError(t, err) - - err = compiler.compileV128FloatDemote(operationPtr(wazeroir.NewOperationV128FloatDemote())) - require.NoError(t, err) - - requireRuntimeLocationStackPointerEqual(t, uint64(2), compiler) - require.Equal(t, 1, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - require.Equal(t, nativeCallStatusCodeReturned, env.callEngine().statusCode) - - lo, hi := env.stackTopAsV128() - actualFs := [4]float32{ - math.Float32frombits(uint32(lo)), - math.Float32frombits(uint32(lo >> 32)), - math.Float32frombits(uint32(hi)), - math.Float32frombits(uint32(hi >> 32)), - } - expFs := [4]float32{ - math.Float32frombits(binary.LittleEndian.Uint32(tc.exp[:4])), - math.Float32frombits(binary.LittleEndian.Uint32(tc.exp[4:8])), - math.Float32frombits(binary.LittleEndian.Uint32(tc.exp[8:12])), - math.Float32frombits(binary.LittleEndian.Uint32(tc.exp[12:])), - } - for i := range expFs { - exp, actual := expFs[i], actualFs[i] - if math.IsNaN(float64(exp)) { - require.True(t, math.IsNaN(float64(actual))) - } else { - require.Equal(t, exp, actual) - } - } - }) - } -} - -func TestCompiler_compileV128ExtAddPairwise(t *testing.T) { - tests := []struct { - name string - shape wazeroir.Shape - signed bool - v, exp [16]byte - }{ - { - name: "i8x16 s", - shape: wazeroir.ShapeI8x16, - signed: true, - v: [16]byte{}, - exp: [16]byte{}, - }, - { - name: "i8x16 s", - shape: wazeroir.ShapeI8x16, - signed: true, - v: [16]byte{1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}, - exp: i16x8(2, 2, 2, 2, 2, 2, 2, 2), - }, - { - name: "i8x16 s", - shape: wazeroir.ShapeI8x16, - signed: true, - v: [16]byte{ - i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), - i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), - }, - exp: i16x8( - i16ToU16(-2), i16ToU16(-2), i16ToU16(-2), i16ToU16(-2), - i16ToU16(-2), i16ToU16(-2), i16ToU16(-2), i16ToU16(-2), - ), - }, - { - name: "i8x16 s", - shape: wazeroir.ShapeI8x16, - signed: true, - v: [16]byte{ - i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), - i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), - }, - exp: i16x8( - i16ToU16(-256), i16ToU16(-256), i16ToU16(-256), i16ToU16(-256), - i16ToU16(-256), i16ToU16(-256), i16ToU16(-256), i16ToU16(-256), - ), - }, - { - name: "i8x16 u", - shape: wazeroir.ShapeI8x16, - signed: false, - v: [16]byte{}, - exp: [16]byte{}, - }, - { - name: "i8x16 u", - shape: wazeroir.ShapeI8x16, - signed: false, - v: [16]byte{1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}, - exp: i16x8(2, 2, 2, 2, 2, 2, 2, 2), - }, - { - name: "i8x16 u", - shape: wazeroir.ShapeI8x16, - signed: false, - v: [16]byte{ - i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), - i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), i8ToU8(-1), - }, - exp: i16x8(510, 510, 510, 510, 510, 510, 510, 510), - }, - { - name: "i8x16 u", - shape: wazeroir.ShapeI8x16, - signed: false, - v: [16]byte{ - i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), - i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), i8ToU8(-128), - }, - exp: i16x8(256, 256, 256, 256, 256, 256, 256, 256), - }, - { - name: "i16x8 s", - shape: wazeroir.ShapeI16x8, - signed: true, - v: [16]byte{}, - exp: [16]byte{}, - }, - { - name: "i16x8 s", - shape: wazeroir.ShapeI16x8, - signed: true, - v: i16x8(1, 1, 1, 1, 1, 1, 1, 1), - exp: i32x4(2, 2, 2, 2), - }, - { - name: "i16x8 s", - shape: wazeroir.ShapeI16x8, - signed: true, - v: i16x8( - i16ToU16(-1), i16ToU16(-1), i16ToU16(-1), i16ToU16(-1), - i16ToU16(-1), i16ToU16(-1), i16ToU16(-1), i16ToU16(-1), - ), - exp: i32x4(i32ToU32(-2), i32ToU32(-2), i32ToU32(-2), i32ToU32(-2)), - }, - { - name: "i16x8 s", - shape: wazeroir.ShapeI16x8, - signed: true, - v: i16x8( - i16ToU16(-32768), i16ToU16(-32768), i16ToU16(-32768), i16ToU16(-32768), - i16ToU16(-32768), i16ToU16(-32768), i16ToU16(-32768), i16ToU16(-32768), - ), - exp: i32x4(i32ToU32(-65536), i32ToU32(-65536), i32ToU32(-65536), i32ToU32(-65536)), - }, - { - name: "i16x8 u", - shape: wazeroir.ShapeI16x8, - signed: false, - v: [16]byte{}, - exp: [16]byte{}, - }, - { - name: "i16x8 u", - shape: wazeroir.ShapeI16x8, - signed: false, - v: i16x8(1, 1, 1, 1, 1, 1, 1, 1), - exp: i32x4(2, 2, 2, 2), - }, - { - name: "i16x8 u", - shape: wazeroir.ShapeI16x8, - signed: false, - v: i16x8( - i16ToU16(-1), i16ToU16(-1), i16ToU16(-1), i16ToU16(-1), - i16ToU16(-1), i16ToU16(-1), i16ToU16(-1), i16ToU16(-1), - ), - exp: i32x4(131070, 131070, 131070, 131070), - }, - { - name: "i16x8 u", - shape: wazeroir.ShapeI16x8, - signed: false, - v: i16x8( - i16ToU16(-32768), i16ToU16(-32768), i16ToU16(-32768), i16ToU16(-32768), - i16ToU16(-32768), i16ToU16(-32768), i16ToU16(-32768), i16ToU16(-32768), - ), - exp: i32x4(65536, 65536, 65536, 65536), - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, - &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.v[:8]), binary.LittleEndian.Uint64(tc.v[8:])))) - require.NoError(t, err) - - err = compiler.compileV128ExtAddPairwise(operationPtr(wazeroir.NewOperationV128ExtAddPairwise(tc.shape, tc.signed))) - require.NoError(t, err) - - requireRuntimeLocationStackPointerEqual(t, uint64(2), compiler) - require.Equal(t, 1, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - require.Equal(t, nativeCallStatusCodeReturned, env.callEngine().statusCode) - - lo, hi := env.stackTopAsV128() - var actual [16]byte - binary.LittleEndian.PutUint64(actual[:8], lo) - binary.LittleEndian.PutUint64(actual[8:], hi) - require.Equal(t, tc.exp, actual) - }) - } -} - -func TestCompiler_compileV128Narrow(t *testing.T) { - tests := []struct { - name string - shape wazeroir.Shape - signed bool - x1, x2, exp [16]byte - }{ - { - name: "i16x8 s", - shape: wazeroir.ShapeI16x8, - signed: true, - x1: i16x8(0, 0, 0, 0, 0, 0, 0, 0), - x2: i16x8(0, 0, 0, 0, 0, 0, 0, 0), - exp: [16]byte{}, - }, - { - name: "i16x8 s", - shape: wazeroir.ShapeI16x8, - signed: true, - x1: i16x8(0, 0, 0, 0, 0, 0, 0, 0), - x2: i16x8(1, 1, 1, 1, 1, 1, 1, 1), - exp: [16]byte{ - 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 1, 1, 1, 1, 1, - }, - }, - { - name: "i16x8 s", - shape: wazeroir.ShapeI16x8, - signed: true, - x1: i16x8(1, 1, 1, 1, 1, 1, 1, 1), - x2: i16x8(0, 0, 0, 0, 0, 0, 0, 0), - exp: [16]byte{ - 1, 1, 1, 1, 1, 1, 1, 1, - 0, 0, 0, 0, 0, 0, 0, 0, - }, - }, - { - name: "i16x8 s", - shape: wazeroir.ShapeI16x8, - signed: true, - x1: i16x8(i16ToU16(-0x8000), 0, i16ToU16(-0x8000), 0, i16ToU16(-0x8000), 0, i16ToU16(-0x8000), 0), - x2: i16x8(0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff), - exp: [16]byte{ - 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - }, - }, - { - name: "i16x8 s", - shape: wazeroir.ShapeI16x8, - signed: true, - x1: i16x8(0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff), - x2: i16x8(i16ToU16(-0x8000), 0, i16ToU16(-0x8000), 0, i16ToU16(-0x8000), 0, i16ToU16(-0x8000), 0), - exp: [16]byte{ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, - }, - }, - { - name: "i16x8 u", - shape: wazeroir.ShapeI16x8, - signed: false, - x1: i16x8(0, 0, 0, 0, 0, 0, 0, 0), - x2: i16x8(0, 0, 0, 0, 0, 0, 0, 0), - exp: [16]byte{}, - }, - { - name: "i16x8 u", - shape: wazeroir.ShapeI16x8, - signed: false, - x1: i16x8(0, 0, 0, 0, 0, 0, 0, 0), - x2: i16x8(1, 1, 1, 1, 1, 1, 1, 1), - exp: [16]byte{ - 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 1, 1, 1, 1, 1, - }, - }, - { - name: "i16x8 u", - shape: wazeroir.ShapeI16x8, - signed: false, - x1: i16x8(1, 1, 1, 1, 1, 1, 1, 1), - x2: i16x8(0, 0, 0, 0, 0, 0, 0, 0), - exp: [16]byte{ - 1, 1, 1, 1, 1, 1, 1, 1, - 0, 0, 0, 0, 0, 0, 0, 0, - }, - }, - { - name: "i16x8 u", - shape: wazeroir.ShapeI16x8, - signed: false, - x1: i16x8(i16ToU16(-0x8000), 0, i16ToU16(-0x8000), 0, i16ToU16(-0x8000), 0, i16ToU16(-0x8000), 0), - x2: i16x8(0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff), - exp: [16]byte{ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - }, - }, - { - name: "i16x8 u", - shape: wazeroir.ShapeI16x8, - signed: false, - x1: i16x8(0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff), - x2: i16x8(i16ToU16(-0x8000), 0, i16ToU16(-0x8000), 0, i16ToU16(-0x8000), 0, i16ToU16(-0x8000), 0), - exp: [16]byte{ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - }, - }, - { - name: "i16x8 u", - shape: wazeroir.ShapeI16x8, - signed: false, - x1: i16x8(i16ToU16(-1), 0, i16ToU16(-1), 0, i16ToU16(-1), 0, i16ToU16(-1), 0), - x2: i16x8(0, 0x100, 0, 0x100, 0, 0x100, 0, 0x100), - exp: [16]byte{ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0xff, 0x00, 0xff, 0x00, 0xff, 0x00, 0xff, - }, - }, - { - name: "i16x8 u", - shape: wazeroir.ShapeI16x8, - signed: false, - x1: i16x8(0, 0x100, 0, 0x100, 0, 0x100, 0, 0x100), - x2: i16x8(i16ToU16(-1), 0, i16ToU16(-1), 0, i16ToU16(-1), 0, i16ToU16(-1), 0), - exp: [16]byte{ - 0x00, 0xff, 0x00, 0xff, 0x00, 0xff, 0x00, 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - }, - }, - { - name: "i32x4 s", - shape: wazeroir.ShapeI32x4, - signed: true, - x1: i32x4(0, 0, 0, 0), - x2: i32x4(0, 0, 0, 0), - exp: i16x8(0, 0, 0, 0, 0, 0, 0, 0), - }, - { - name: "i32x4 s", - shape: wazeroir.ShapeI32x4, - signed: true, - x1: i32x4(0, 0, 0, 0), - x2: i32x4(1, 1, 1, 1), - exp: i16x8(0, 0, 0, 0, 1, 1, 1, 1), - }, - { - name: "i32x4 s", - shape: wazeroir.ShapeI32x4, - signed: true, - x1: i32x4(1, 1, 1, 1), - x2: i32x4(0, 0, 0, 0), - exp: i16x8(1, 1, 1, 1, 0, 0, 0, 0), - }, - { - name: "i32x4 s", - shape: wazeroir.ShapeI32x4, - signed: true, - x1: i32x4(0x8000, 0x8000, 0x7fff, 0x7fff), - x2: i32x4(0x7fff, 0x7fff, 0x8000, 0x8000), - exp: i16x8(0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff), - }, - { - name: "i32x4 u", - shape: wazeroir.ShapeI32x4, - signed: false, - x1: i32x4(0, 0, 0, 0), - x2: i32x4(0, 0, 0, 0), - exp: i16x8(0, 0, 0, 0, 0, 0, 0, 0), - }, - { - name: "i32x4 u", - shape: wazeroir.ShapeI32x4, - signed: false, - x1: i32x4(0, 0, 0, 0), - x2: i32x4(1, 1, 1, 1), - exp: i16x8(0, 0, 0, 0, 1, 1, 1, 1), - }, - { - name: "i32x4 u", - shape: wazeroir.ShapeI32x4, - signed: false, - x1: i32x4(1, 1, 1, 1), - x2: i32x4(0, 0, 0, 0), - exp: i16x8(1, 1, 1, 1, 0, 0, 0, 0), - }, - { - name: "i32x4 u", - shape: wazeroir.ShapeI32x4, - signed: false, - x1: i32x4(0x8000, 0x8000, 0x7fff, 0x7fff), - x2: i32x4(0x7fff, 0x7fff, 0x8000, 0x8000), - exp: i16x8(0x8000, 0x8000, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x8000, 0x8000), - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, - &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.x1[:8]), binary.LittleEndian.Uint64(tc.x1[8:])))) - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.x2[:8]), binary.LittleEndian.Uint64(tc.x2[8:])))) - require.NoError(t, err) - - err = compiler.compileV128Narrow(operationPtr(wazeroir.NewOperationV128Narrow(tc.shape, tc.signed))) - require.NoError(t, err) - - requireRuntimeLocationStackPointerEqual(t, uint64(2), compiler) - require.Equal(t, 1, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - require.Equal(t, nativeCallStatusCodeReturned, env.callEngine().statusCode) - - lo, hi := env.stackTopAsV128() - var actual [16]byte - binary.LittleEndian.PutUint64(actual[:8], lo) - binary.LittleEndian.PutUint64(actual[8:], hi) - require.Equal(t, tc.exp, actual) - }) - } -} - -func TestCompiler_compileV128FConvertFromI(t *testing.T) { - tests := []struct { - name string - destShape wazeroir.Shape - signed bool - v, exp [16]byte - }{ - { - name: "f32x4 s", - destShape: wazeroir.ShapeF32x4, - signed: true, - v: i32x4(0, 0, 0, 0), - exp: f32x4(0, 0, 0, 0), - }, - { - name: "f32x4 s", - destShape: wazeroir.ShapeF32x4, - signed: true, - v: i32x4(1, 0, 2, 3), - exp: f32x4(1, 0, 2.0, 3), - }, - { - name: "f32x4 s", - destShape: wazeroir.ShapeF32x4, - signed: true, - v: i32x4(1234567890, i32ToU32(-2147483648.0), 2147483647, 1234567890), - exp: f32x4(0x1.26580cp+30, -2147483648.0, 2147483647, 0x1.26580cp+30), - }, - { - name: "f32x4 s", - destShape: wazeroir.ShapeF32x4, - signed: false, - v: i32x4(0, 0, 0, 0), - exp: f32x4(0, 0, 0, 0), - }, - { - name: "f32x4 s", - destShape: wazeroir.ShapeF32x4, - signed: false, - v: i32x4(1, 0, 2, 3), - exp: f32x4(1, 0, 2.0, 3), - }, - { - name: "f32x4 s", - destShape: wazeroir.ShapeF32x4, - signed: false, - v: i32x4(2147483647, i32ToU32(-2147483648.0), 2147483647, i32ToU32(-1)), - exp: f32x4(2147483648.0, 2147483648.0, 2147483648.0, 4294967295.0), - }, - { - name: "f64x2 s", - destShape: wazeroir.ShapeF64x2, - signed: true, - v: i32x4(0, 0, 0, 0), - exp: f64x2(0, 0), - }, - { - name: "f64x2 s", - destShape: wazeroir.ShapeF64x2, - signed: true, - v: i32x4(0, 0, i32ToU32(-1), i32ToU32(-32)), - exp: f64x2(0, 0), - }, - { - name: "f64x2 s", - destShape: wazeroir.ShapeF64x2, - signed: true, - v: i32x4(2147483647, i32ToU32(-2147483648), 0, 0), - exp: f64x2(2147483647, -2147483648), - }, - { - name: "f64x2 s", - destShape: wazeroir.ShapeF64x2, - signed: false, - v: i32x4(0, 0, 0, 0), - exp: f64x2(0, 0), - }, - { - name: "f64x2 s", - destShape: wazeroir.ShapeF64x2, - signed: false, - v: i32x4(0, 0, i32ToU32(-1), i32ToU32(-32)), - exp: f64x2(0, 0), - }, - { - name: "f64x2 s", - destShape: wazeroir.ShapeF64x2, - signed: false, - v: i32x4(2147483647, i32ToU32(-2147483648), 0, 0), - exp: f64x2(2147483647, 2147483648), - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, - &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.v[:8]), binary.LittleEndian.Uint64(tc.v[8:])))) - require.NoError(t, err) - - err = compiler.compileV128FConvertFromI(operationPtr(wazeroir.NewOperationV128FConvertFromI(tc.destShape, tc.signed))) - require.NoError(t, err) - - requireRuntimeLocationStackPointerEqual(t, uint64(2), compiler) - require.Equal(t, 1, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - require.Equal(t, nativeCallStatusCodeReturned, env.callEngine().statusCode) - - lo, hi := env.stackTopAsV128() - var actual [16]byte - binary.LittleEndian.PutUint64(actual[:8], lo) - binary.LittleEndian.PutUint64(actual[8:], hi) - require.Equal(t, tc.exp, actual) - }) - } -} - -func TestCompiler_compileV128Dot(t *testing.T) { - tests := []struct { - name string - x1, x2, exp [16]byte - }{ - { - name: "1", - x1: i16x8(0, 0, 0, 0, 0, 0, 0, 0), - x2: i16x8(0, 0, 0, 0, 0, 0, 0, 0), - exp: i32x4(0, 0, 0, 0), - }, - { - name: "2", - x1: i16x8(1, 1, 1, 1, i16ToU16(-1), i16ToU16(-1), i16ToU16(-1), i16ToU16(-1)), - x2: i16x8(i16ToU16(-1), i16ToU16(-1), i16ToU16(-1), i16ToU16(-1), 2, 2, 2, 2), - exp: i32x4(i32ToU32(-2), i32ToU32(-2), i32ToU32(-4), i32ToU32(-4)), - }, - { - name: "3", - x1: i16x8(65535, 65535, 65535, 65535, 65535, 65535, 65535, 65535), - x2: i16x8(65535, 65535, 65535, 65535, 65535, 65535, 65535, 65535), - exp: i32x4(2, 2, 2, 2), - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, - &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.x2[:8]), binary.LittleEndian.Uint64(tc.x2[8:])))) - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.x1[:8]), binary.LittleEndian.Uint64(tc.x1[8:])))) - require.NoError(t, err) - - err = compiler.compileV128Dot(operationPtr(wazeroir.NewOperationV128Dot())) - require.NoError(t, err) - - requireRuntimeLocationStackPointerEqual(t, uint64(2), compiler) - require.Equal(t, 1, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - require.Equal(t, nativeCallStatusCodeReturned, env.callEngine().statusCode) - - lo, hi := env.stackTopAsV128() - var actual [16]byte - binary.LittleEndian.PutUint64(actual[:8], lo) - binary.LittleEndian.PutUint64(actual[8:], hi) - require.Equal(t, tc.exp, actual) - }) - } -} - -func TestCompiler_compileV128ITruncSatFromF(t *testing.T) { - tests := []struct { - name string - originShape wazeroir.Shape - signed bool - v, exp [16]byte - }{ - { - name: "f32x4 s", - originShape: wazeroir.ShapeF32x4, - signed: true, - v: i32x4(0, 0, 0, 0), - exp: f32x4(0, 0, 0, 0), - }, - { - name: "f32x4 s", - originShape: wazeroir.ShapeF32x4, - signed: true, - v: f32x4(1.5, -1.9, -1.9, 1.5), - exp: i32x4(1, i32ToU32(-1), i32ToU32(-1), 1), - }, - { - name: "f32x4 s", - originShape: wazeroir.ShapeF32x4, - signed: true, - v: f32x4(float32(math.NaN()), -4294967294.0, float32(math.Inf(-1)), float32(math.Inf(1))), - exp: i32x4(0, i32ToU32(-2147483648), i32ToU32(-2147483648), 2147483647), - }, - { - name: "f32x4 u", - originShape: wazeroir.ShapeF32x4, - signed: false, - v: i32x4(0, 0, 0, 0), - exp: f32x4(0, 0, 0, 0), - }, - { - name: "f32x4 u", - originShape: wazeroir.ShapeF32x4, - signed: false, - v: f32x4(1.5, -1.9, -1.9, 1.5), - exp: i32x4(1, 0, 0, 1), - }, - { - name: "f32x4 u", - originShape: wazeroir.ShapeF32x4, - signed: false, - v: f32x4(float32(math.NaN()), -4294967294.0, 4294967294.0, float32(math.Inf(1))), - exp: i32x4(0, 0, 4294967295, 4294967295), - }, - { - name: "f64x2 s", - originShape: wazeroir.ShapeF64x2, - signed: true, - v: f64x2(0, 0), - exp: i32x4(0, 0, 0, 0), - }, - { - name: "f64x2 s", - originShape: wazeroir.ShapeF64x2, - signed: true, - v: f64x2(5.123, -2.0), - exp: i32x4(5, i32ToU32(-2), 0, 0), - }, - { - name: "f64x2 s", - originShape: wazeroir.ShapeF64x2, - signed: true, - v: f64x2(math.NaN(), math.Inf(1)), - exp: i32x4(0, 2147483647, 0, 0), - }, - { - name: "f64x2 s", - originShape: wazeroir.ShapeF64x2, - signed: true, - v: f64x2(math.Inf(-1), 4294967294.0), - exp: i32x4(i32ToU32(-2147483648), 2147483647, 0, 0), - }, - { - name: "f64x2 u", - originShape: wazeroir.ShapeF64x2, - signed: false, - v: f64x2(0, 0), - exp: i32x4(0, 0, 0, 0), - }, - { - name: "f64x2 u", - originShape: wazeroir.ShapeF64x2, - signed: false, - v: f64x2(5.123, -2.0), - exp: i32x4(5, 0, 0, 0), - }, - { - name: "f64x2 u", - originShape: wazeroir.ShapeF64x2, - signed: false, - v: f64x2(math.NaN(), math.Inf(1)), - exp: i32x4(0, 4294967295, 0, 0), - }, - { - name: "f64x2 u", - originShape: wazeroir.ShapeF64x2, - signed: false, - v: f64x2(math.Inf(-1), 4294967296.0), - exp: i32x4(0, 4294967295, 0, 0), - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, - &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.v[:8]), binary.LittleEndian.Uint64(tc.v[8:])))) - require.NoError(t, err) - - err = compiler.compileV128ITruncSatFromF(operationPtr(wazeroir.NewOperationV128ITruncSatFromF(tc.originShape, tc.signed))) - require.NoError(t, err) - - requireRuntimeLocationStackPointerEqual(t, uint64(2), compiler) - require.Equal(t, 1, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - require.Equal(t, nativeCallStatusCodeReturned, env.callEngine().statusCode) - - lo, hi := env.stackTopAsV128() - var actual [16]byte - binary.LittleEndian.PutUint64(actual[:8], lo) - binary.LittleEndian.PutUint64(actual[8:], hi) - require.Equal(t, tc.exp, actual) - }) - } -} - -// TestCompiler_compileSelect_v128 is for select instructions on vector values. -func TestCompiler_compileSelect_v128(t *testing.T) { - const x1Lo, x1Hi = uint64(0x1), uint64(0x2) - const x2Lo, x2Hi = uint64(0x3), uint64(0x4) - - for _, selector := range []uint32{0, 1} { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, - &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(x1Lo, x1Hi))) - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(x2Lo, x2Hi))) - require.NoError(t, err) - - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(selector))) - require.NoError(t, err) - - err = compiler.compileSelect(operationPtr(wazeroir.NewOperationSelect(true))) - require.NoError(t, err) - - requireRuntimeLocationStackPointerEqual(t, uint64(2), compiler) - require.Equal(t, 1, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - require.Equal(t, nativeCallStatusCodeReturned, env.callEngine().statusCode) - - lo, hi := env.stackTopAsV128() - if selector == 0 { - require.Equal(t, x2Lo, lo) - require.Equal(t, x2Hi, hi) - } else { - require.Equal(t, x1Lo, lo) - require.Equal(t, x1Hi, hi) - } - } -} diff --git a/internal/engine/compiler/engine.go b/internal/engine/compiler/engine.go deleted file mode 100644 index 6f46cb4f79..0000000000 --- a/internal/engine/compiler/engine.go +++ /dev/null @@ -1,1770 +0,0 @@ -package compiler - -import ( - "context" - "errors" - "fmt" - "reflect" - "runtime" - "sort" - "sync" - "sync/atomic" - "unsafe" - - "github.com/tetratelabs/wazero/api" - "github.com/tetratelabs/wazero/experimental" - "github.com/tetratelabs/wazero/internal/asm" - "github.com/tetratelabs/wazero/internal/bitpack" - "github.com/tetratelabs/wazero/internal/filecache" - "github.com/tetratelabs/wazero/internal/internalapi" - "github.com/tetratelabs/wazero/internal/platform" - "github.com/tetratelabs/wazero/internal/version" - "github.com/tetratelabs/wazero/internal/wasm" - "github.com/tetratelabs/wazero/internal/wasmdebug" - "github.com/tetratelabs/wazero/internal/wasmruntime" - "github.com/tetratelabs/wazero/internal/wazeroir" -) - -// NOTE: The offset of many of the struct fields defined here are referenced from -// assembly using the constants below such as moduleEngineFunctionsOffset. -// If changing a struct, update the constant and associated tests as needed. -type ( - // engine is a Compiler implementation of wasm.Engine - engine struct { - enabledFeatures api.CoreFeatures - codes map[wasm.ModuleID]*compiledModule // guarded by mutex. - fileCache filecache.Cache - mux sync.RWMutex - // setFinalizer defaults to runtime.SetFinalizer, but overridable for tests. - setFinalizer func(obj interface{}, finalizer interface{}) - wazeroVersion string - } - - // moduleEngine implements wasm.ModuleEngine - moduleEngine struct { - // See note at top of file before modifying this struct. - - // functions are the functions in a module instances. - // The index is module instance-scoped. We intentionally avoid using map - // as the underlying memory region is accessed by assembly directly by using - // codesElement0Address. - functions []function - - // Keep a reference to the compiled module to prevent the GC from reclaiming - // it while the code may still be needed. - module *compiledModule - } - - // callEngine holds context per moduleEngine.Call, and shared across all the - // function calls originating from the same moduleEngine.Call execution. - // - // This implements api.Function. - callEngine struct { - internalapi.WazeroOnlyType - - // See note at top of file before modifying this struct. - - // These contexts are read and written by compiled code. - // Note: structs are embedded to reduce the costs to access fields inside them. Also, this eases field offset - // calculation. - moduleContext - stackContext - exitContext - archContext - - // The following fields are not accessed by compiled code directly. - - // stack is the go-allocated stack for holding values and call frames. - // Note: We never edit len or cap in compiled code, so we won't get screwed when GC comes in. - // - // At any point of execution, say currently executing function F2 which was called by F1, then - // the stack should look like like: - // - // [..., arg0, arg1, ..., argN, _, _, _, v1, v2, v3, .... - // ^ { } - // | F1's callFrame - // | - // stackBasePointer - // - // where - // - callFrame is the F1's callFrame which called F2. It contains F1's return address, F1's base pointer, and F1's *function. - // - stackBasePointer is the stack base pointer stored at (callEngine stackContext.stackBasePointerInBytes) - // - arg0, ..., argN are the function parameters, and v1, v2, v3,... are the local variables - // including the non-function param locals as well as the temporary variable produced by instructions (e.g i32.const). - // - // If the F2 makes a function call to F3 which takes two arguments, then the stack will become: - // - // [..., arg0, arg1, ..., argN, _, _, _, v1, v2, v3, _, _, _ - // { } ^ { } - // F1's callFrame | F2's callFrame - // | - // stackBasePointer - // where - // - F2's callFrame is pushed above the v2 and v3 (arguments for F3). - // - The previous stackBasePointer (pointed at arg0) was saved inside the F2's callFrame. - // - // Then, if F3 returns one result, say w1, then the result will look like: - // - // [..., arg0, arg1, ..., argN, _, _, _, v1, w1, ... - // ^ { } - // | F1's callFrame - // | - // stackBasePointer - // - // where - // - stackBasePointer was reverted to the position at arg0 - // - The result from F3 was pushed above v1 - // - // If the number of parameters is smaller than that of return values, then the empty slots are reserved - // below the callFrame to store the results on teh return. - // For example, if F3 takes no parameter but returns N(>0) results, then the stack - // after making a call against F3 will look like: - // - // [..., arg0, arg1, ..., argN, _, _, _, v1, v2, v3, res_1, _, res_N, _, _, _ - // { } ^ { } - // F1's callFrame | F2's callFrame - // | - // stackBasePointer - // where res_1, ..., res_N are the reserved slots below the call frame. In general, - // the number of reserved slots equals max(0, len(results)-len(params). - // - // This reserved slots are necessary to save the result values onto the stack while not destroying - // the callFrame value on function returns. - stack []uint64 - - // initialFn is the initial function for this call engine. - initialFn *function - - // Keep a reference to the compiled module to prevent the GC from reclaiming - // it while the code may still be needed. - module *compiledModule - - // stackIterator provides a way to iterate over the stack for Listeners. - // It is setup and valid only during a call to a Listener hook. - stackIterator stackIterator - } - - // moduleContext holds the per-function call specific module information. - // This is subject to be manipulated from compiled native code whenever we make function calls. - moduleContext struct { - // See note at top of file before modifying this struct. - - // fn holds the currently executed *function. - fn *function - - // moduleInstance is the address of module instance from which we initialize - // the following fields. This is set whenever we enter a function or return from function calls. - // - // On the entry to the native code, this must be initialized to zero to let native code preamble know - // that this is the initial function call (which leads to moduleContext initialization pass). - moduleInstance *wasm.ModuleInstance //lint:ignore U1000 This is only used by Compiler code. - - // globalElement0Address is the address of the first element in the global slice, - // i.e. &ModuleInstance.Globals[0] as uintptr. - globalElement0Address uintptr - // memoryElement0Address is the address of the first element in the global slice, - // i.e. &ModuleInstance.Memory.Buffer[0] as uintptr. - memoryElement0Address uintptr - // memorySliceLen is the length of the memory buffer, i.e. len(ModuleInstance.Memory.Buffer). - memorySliceLen uint64 - // memoryInstance holds the memory instance for this module instance. - memoryInstance *wasm.MemoryInstance - // tableElement0Address is the address of the first item in the tables slice, - // i.e. &ModuleInstance.Tables[0] as uintptr. - tablesElement0Address uintptr - - // functionsElement0Address is &moduleContext.functions[0] as uintptr. - functionsElement0Address uintptr - - // typeIDsElement0Address holds the &ModuleInstance.TypeIDs[0] as uintptr. - typeIDsElement0Address uintptr - - // dataInstancesElement0Address holds the &ModuleInstance.DataInstances[0] as uintptr. - dataInstancesElement0Address uintptr - - // elementInstancesElement0Address holds the &ModuleInstance.ElementInstances[0] as uintptr. - elementInstancesElement0Address uintptr - } - - // stackContext stores the data to access engine.stack. - stackContext struct { - // See note at top of file before modifying this struct. - - // stackPointer on .stack field which is accessed by stack[stackBasePointer+stackBasePointerInBytes*8]. - // - // Note: stackPointer is not used in assembly since the native code knows exact position of - // each variable in the value stack from the info from compilation. - // Therefore, only updated when native code exit from the Compiler world and go back to the Go function. - stackPointer uint64 - - // stackBasePointerInBytes is updated whenever we make function calls. - // Background: Functions might be compiled as if they use the stack from the bottom. - // However, in reality, they have to use it from the middle of the stack depending on - // when these function calls are made. So instead of accessing stack via stackPointer alone, - // functions are compiled, so they access the stack via [stackBasePointer](fixed for entire function) + [stackPointer]. - // More precisely, stackBasePointer is set to [callee's stack pointer] + [callee's stack base pointer] - [caller's params]. - // This way, compiled functions can be independent of the timing of functions calls made against them. - stackBasePointerInBytes uint64 - - // stackElement0Address is &engine.stack[0] as uintptr. - // Note: this is updated when growing the stack in builtinFunctionGrowStack. - stackElement0Address uintptr - - // stackLenInBytes is len(engine.stack[0]) * 8 (bytes). - // Note: this is updated when growing the stack in builtinFunctionGrowStack. - stackLenInBytes uint64 - } - - // exitContext will be manipulated whenever compiled native code returns into the Go function. - exitContext struct { - // See note at top of file before modifying this struct. - - // Where we store the status code of Compiler execution. - statusCode nativeCallStatusCode - - // Set when statusCode == compilerStatusCallBuiltInFunction - // Indicating the function call index. - builtinFunctionCallIndex wasm.Index - - // returnAddress is the return address which the engine jumps into - // after executing a builtin function or host function. - returnAddress uintptr - - // callerModuleInstance holds the caller's wasm.ModuleInstance, and is only valid if currently executing a host function. - callerModuleInstance *wasm.ModuleInstance - } - - // callFrame holds the information to which the caller function can return. - // This is mixed in callEngine.stack with other Wasm values just like any other - // native program (where the stack is the system stack though), and we retrieve the struct - // with unsafe pointer casts. - callFrame struct { - // See note at top of file before modifying this struct. - - // returnAddress is the return address to which the engine jumps when the callee function returns. - returnAddress uintptr - // returnStackBasePointerInBytes is the stack base pointer to set on stackContext.stackBasePointerInBytes - // when the callee function returns. - returnStackBasePointerInBytes uint64 - // function is the caller *function, and is used to retrieve the stack trace. - // Note: should be possible to revive *function from returnAddress, but might be costly. - function *function - } - - // Function corresponds to function instance in Wasm, and is created from `code`. - function struct { - // See note at top of file before modifying this struct. - - // codeInitialAddress is the pre-calculated pointer pointing to the initial byte of .codeSegment slice. - // That mean codeInitialAddress always equals uintptr(unsafe.Pointer(&.codeSegment[0])) - // and we cache the value (uintptr(unsafe.Pointer(&.codeSegment[0]))) to this field, - // so we don't need to repeat the calculation on each function call. - codeInitialAddress uintptr - // moduleInstance holds the address of source.ModuleInstance. - moduleInstance *wasm.ModuleInstance - // typeID is the corresponding wasm.FunctionTypeID for funcType. - typeID wasm.FunctionTypeID - // funcType is the function type for this function. Created during compilation. - funcType *wasm.FunctionType - // parent holds code from which this is created. - parent *compiledFunction - } - - compiledModule struct { - // The data that need to be accessed by compiledFunction.parent are - // separated in an embedded field because we use finalizers to manage - // the lifecycle of compiledModule instances and having cyclic pointers - // prevents the Go runtime from calling them, which results in memory - // leaks since the memory mapped code segments cannot be released. - // - // The indirection guarantees that the finalizer set on compiledModule - // instances can run when all references are gone, and the Go GC can - // manage to reclaim the compiledCode when all compiledFunction objects - // referencing it have been freed. - *compiledCode - functions []compiledFunction - - ensureTermination bool - } - - compiledCode struct { - source *wasm.Module - executable asm.CodeSegment - } - - // compiledFunction corresponds to a function in a module (not instantiated one). This holds the machine code - // compiled by wazero compiler. - compiledFunction struct { - // codeSegment is holding the compiled native code as a byte slice. - executableOffset uintptr - // See the doc for codeStaticData type. - // stackPointerCeil is the max of the stack pointer this function can reach. Lazily applied via maybeGrowStack. - stackPointerCeil uint64 - - index wasm.Index - goFunc interface{} - listener experimental.FunctionListener - parent *compiledCode - sourceOffsetMap sourceOffsetMap - } - - // sourceOffsetMap holds the information to retrieve the original offset in - // the Wasm binary from the offset in the native binary. - // - // The fields are implemented as bit-packed arrays of 64 bits integers to - // reduce the memory footprint. Indexing into such arrays is not as fast as - // indexing into a simple slice, but the source offset map is intended to be - // used for debugging, lookups into the arrays should not appear on code - // paths that are critical to the application performance. - // - // The bitpack.OffsetArray fields may be nil, use bitpack.OffsetArrayLen to - // determine whether they are empty prior to indexing into the arrays to - // avoid panics caused by accessing nil pointers. - sourceOffsetMap struct { - // See note at top of file before modifying this struct. - - // irOperationOffsetsInNativeBinary is index-correlated with irOperationSourceOffsetsInWasmBinary, - // and maps each index (corresponding to each IR Operation) to the offset in the compiled native code. - irOperationOffsetsInNativeBinary bitpack.OffsetArray - // irOperationSourceOffsetsInWasmBinary is index-correlated with irOperationOffsetsInNativeBinary. - // See wazeroir.CompilationResult irOperationOffsetsInNativeBinary. - irOperationSourceOffsetsInWasmBinary bitpack.OffsetArray - } - - // functionListenerInvocation captures arguments needed to perform function - // listener invocations when unwinding the call stack. - functionListenerInvocation struct { - experimental.FunctionListener - def api.FunctionDefinition - } -) - -// Native code reads/writes Go's structs with the following constants. -// See TestVerifyOffsetValue for how to derive these values. -const ( - // Offsets for moduleEngine.functions - moduleEngineFunctionsOffset = 0 - - // Offsets for callEngine moduleContext. - callEngineModuleContextFnOffset = 0 - callEngineModuleContextModuleInstanceOffset = 8 - callEngineModuleContextGlobalElement0AddressOffset = 16 - callEngineModuleContextMemoryElement0AddressOffset = 24 - callEngineModuleContextMemorySliceLenOffset = 32 - callEngineModuleContextMemoryInstanceOffset = 40 - callEngineModuleContextTablesElement0AddressOffset = 48 - callEngineModuleContextFunctionsElement0AddressOffset = 56 - callEngineModuleContextTypeIDsElement0AddressOffset = 64 - callEngineModuleContextDataInstancesElement0AddressOffset = 72 - callEngineModuleContextElementInstancesElement0AddressOffset = 80 - - // Offsets for callEngine stackContext. - callEngineStackContextStackPointerOffset = 88 - callEngineStackContextStackBasePointerInBytesOffset = 96 - callEngineStackContextStackElement0AddressOffset = 104 - callEngineStackContextStackLenInBytesOffset = 112 - - // Offsets for callEngine exitContext. - callEngineExitContextNativeCallStatusCodeOffset = 120 - callEngineExitContextBuiltinFunctionCallIndexOffset = 124 - callEngineExitContextReturnAddressOffset = 128 - callEngineExitContextCallerModuleInstanceOffset = 136 - - // Offsets for function. - functionCodeInitialAddressOffset = 0 - functionModuleInstanceOffset = 8 - functionTypeIDOffset = 16 - functionSize = 40 - - // Offsets for wasm.ModuleInstance. - moduleInstanceGlobalsOffset = 24 - moduleInstanceMemoryOffset = 48 - moduleInstanceTablesOffset = 56 - moduleInstanceEngineOffset = 80 - moduleInstanceTypeIDsOffset = 96 - moduleInstanceDataInstancesOffset = 120 - moduleInstanceElementInstancesOffset = 144 - - // Offsets for wasm.TableInstance. - tableInstanceTableOffset = 0 - tableInstanceTableLenOffset = 8 - - // Offsets for wasm.MemoryInstance. - memoryInstanceBufferOffset = 0 - memoryInstanceBufferLenOffset = 8 - - // Offsets for wasm.GlobalInstance. - globalInstanceValueOffset = 8 - - // Offsets for Go's interface. - // https://research.swtch.com/interfaces - // https://github.com/golang/go/blob/release-branch.go1.20/src/runtime/runtime2.go#L207-L210 - interfaceDataOffset = 8 - - // Consts for wasm.DataInstance. - dataInstanceStructSize = 24 - - // Consts for wasm.ElementInstance. - elementInstanceStructSize = 24 - - // pointerSizeLog2 satisfies: 1 << pointerSizeLog2 = sizeOf(uintptr) - pointerSizeLog2 = 3 - - // callFrameDataSizeInUint64 is the size of callFrame struct per 8 bytes (= size of uint64). - callFrameDataSizeInUint64 = 24 / 8 -) - -// nativeCallStatusCode represents the result of `nativecall`. -// This is set by the native code. -type nativeCallStatusCode uint32 - -const ( - // nativeCallStatusCodeReturned means the nativecall reaches the end of function, and returns successfully. - nativeCallStatusCodeReturned nativeCallStatusCode = iota - // nativeCallStatusCodeCallGoHostFunction means the nativecall returns to make a host function call. - nativeCallStatusCodeCallGoHostFunction - // nativeCallStatusCodeCallBuiltInFunction means the nativecall returns to make a builtin function call. - nativeCallStatusCodeCallBuiltInFunction - // nativeCallStatusCodeUnreachable means the function invocation reaches "unreachable" instruction. - nativeCallStatusCodeUnreachable - // nativeCallStatusCodeInvalidFloatToIntConversion means an invalid conversion of integer to floats happened. - nativeCallStatusCodeInvalidFloatToIntConversion - // nativeCallStatusCodeMemoryOutOfBounds means an out-of-bounds memory access happened. - nativeCallStatusCodeMemoryOutOfBounds - // nativeCallStatusCodeInvalidTableAccess means either offset to the table was out of bounds of table, or - // the target element in the table was uninitialized during call_indirect instruction. - nativeCallStatusCodeInvalidTableAccess - // nativeCallStatusCodeTypeMismatchOnIndirectCall means the type check failed during call_indirect. - nativeCallStatusCodeTypeMismatchOnIndirectCall - nativeCallStatusIntegerOverflow - nativeCallStatusIntegerDivisionByZero - nativeCallStatusUnalignedAtomic - nativeCallStatusModuleClosed -) - -// causePanic causes a panic with the corresponding error to the nativeCallStatusCode. -func (s nativeCallStatusCode) causePanic() { - var err error - switch s { - case nativeCallStatusIntegerOverflow: - err = wasmruntime.ErrRuntimeIntegerOverflow - case nativeCallStatusIntegerDivisionByZero: - err = wasmruntime.ErrRuntimeIntegerDivideByZero - case nativeCallStatusCodeInvalidFloatToIntConversion: - err = wasmruntime.ErrRuntimeInvalidConversionToInteger - case nativeCallStatusCodeUnreachable: - err = wasmruntime.ErrRuntimeUnreachable - case nativeCallStatusCodeMemoryOutOfBounds: - err = wasmruntime.ErrRuntimeOutOfBoundsMemoryAccess - case nativeCallStatusCodeInvalidTableAccess: - err = wasmruntime.ErrRuntimeInvalidTableAccess - case nativeCallStatusCodeTypeMismatchOnIndirectCall: - err = wasmruntime.ErrRuntimeIndirectCallTypeMismatch - case nativeCallStatusUnalignedAtomic: - err = wasmruntime.ErrRuntimeUnalignedAtomic - } - panic(err) -} - -func (s nativeCallStatusCode) String() (ret string) { - switch s { - case nativeCallStatusCodeReturned: - ret = "returned" - case nativeCallStatusCodeCallGoHostFunction: - ret = "call_host_function" - case nativeCallStatusCodeCallBuiltInFunction: - ret = "call_builtin_function" - case nativeCallStatusCodeUnreachable: - ret = "unreachable" - case nativeCallStatusCodeInvalidFloatToIntConversion: - ret = "invalid float to int conversion" - case nativeCallStatusCodeMemoryOutOfBounds: - ret = "memory out of bounds" - case nativeCallStatusCodeInvalidTableAccess: - ret = "invalid table access" - case nativeCallStatusCodeTypeMismatchOnIndirectCall: - ret = "type mismatch on indirect call" - case nativeCallStatusIntegerOverflow: - ret = "integer overflow" - case nativeCallStatusIntegerDivisionByZero: - ret = "integer division by zero" - case nativeCallStatusModuleClosed: - ret = "module closed" - case nativeCallStatusUnalignedAtomic: - ret = "unaligned atomic" - default: - panic("BUG") - } - return -} - -// releaseCompiledModule is a runtime.SetFinalizer function that munmaps the compiledModule.executable. -func releaseCompiledModule(cm *compiledModule) { - if err := cm.executable.Unmap(); err != nil { - // munmap failure cannot recover, and happen asynchronously on the - // finalizer thread. While finalizer functions can return errors, - // they are ignored. - panic(fmt.Errorf("compiler: failed to munmap code segment: %w", err)) - } -} - -// CompiledModuleCount implements the same method as documented on wasm.Engine. -func (e *engine) CompiledModuleCount() uint32 { - return uint32(len(e.codes)) -} - -// DeleteCompiledModule implements the same method as documented on wasm.Engine. -func (e *engine) DeleteCompiledModule(module *wasm.Module) { - e.deleteCompiledModule(module) -} - -// Close implements the same method as documented on wasm.Engine. -func (e *engine) Close() (err error) { - e.mux.Lock() - defer e.mux.Unlock() - // Releasing the references to compiled codes including the memory-mapped machine codes. - e.codes = nil - return -} - -// CompileModule implements the same method as documented on wasm.Engine. -func (e *engine) CompileModule(_ context.Context, module *wasm.Module, listeners []experimental.FunctionListener, ensureTermination bool) error { - if _, ok, err := e.getCompiledModule(module, listeners); ok { // cache hit! - return nil - } else if err != nil { - return err - } - - irCompiler, err := wazeroir.NewCompiler(e.enabledFeatures, callFrameDataSizeInUint64, module, ensureTermination) - if err != nil { - return err - } - - var withGoFunc bool - localFuncs, importedFuncs := len(module.FunctionSection), module.ImportFunctionCount - cm := &compiledModule{ - compiledCode: &compiledCode{ - source: module, - }, - functions: make([]compiledFunction, localFuncs), - ensureTermination: ensureTermination, - } - - if localFuncs == 0 { - return e.addCompiledModule(module, cm, withGoFunc) - } - - // As this uses mmap, we need to munmap on the compiled machine code when it's GCed. - e.setFinalizer(cm, releaseCompiledModule) - ln := len(listeners) - cmp := newCompiler() - asmNodes := new(asmNodes) - offsets := new(offsets) - - // The executable code is allocated in memory mappings held by the - // CodeSegment, which gros on demand when it exhausts its capacity. - var executable asm.CodeSegment - defer func() { - // At the end of the function, the executable is set on the compiled - // module and the local variable cleared; until then, the function owns - // the memory mapping and is reponsible for clearing it if it returns - // due to an error. Note that an error at this stage is not recoverable - // so we panic if we fail to unmap the memory segment. - if err := executable.Unmap(); err != nil { - panic(fmt.Errorf("compiler: failed to munmap code segment: %w", err)) - } - }() - - for i := range module.CodeSection { - typ := &module.TypeSection[module.FunctionSection[i]] - buf := executable.NextCodeSection() - funcIndex := wasm.Index(i) - compiledFn := &cm.functions[i] - compiledFn.executableOffset = executable.Size() - compiledFn.parent = cm.compiledCode - compiledFn.index = importedFuncs + funcIndex - if i < ln { - compiledFn.listener = listeners[i] - } - - if codeSeg := &module.CodeSection[i]; codeSeg.GoFunc != nil { - cmp.Init(typ, nil, compiledFn.listener != nil) - withGoFunc = true - if err = compileGoDefinedHostFunction(buf, cmp); err != nil { - def := module.FunctionDefinition(compiledFn.index) - return fmt.Errorf("error compiling host go func[%s]: %w", def.DebugName(), err) - } - compiledFn.goFunc = codeSeg.GoFunc - } else { - ir, err := irCompiler.Next() - if err != nil { - return fmt.Errorf("failed to lower func[%d]: %v", i, err) - } - cmp.Init(typ, ir, compiledFn.listener != nil) - - compiledFn.stackPointerCeil, compiledFn.sourceOffsetMap, err = compileWasmFunction(buf, cmp, ir, asmNodes, offsets) - if err != nil { - def := module.FunctionDefinition(compiledFn.index) - return fmt.Errorf("error compiling wasm func[%s]: %w", def.DebugName(), err) - } - } - } - - if runtime.GOARCH == "arm64" { - // On arm64, we cannot give all of rwx at the same time, so we change it to exec. - if err := platform.MprotectRX(executable.Bytes()); err != nil { - return err - } - } - cm.executable, executable = executable, asm.CodeSegment{} - return e.addCompiledModule(module, cm, withGoFunc) -} - -// NewModuleEngine implements the same method as documented on wasm.Engine. -func (e *engine) NewModuleEngine(module *wasm.Module, instance *wasm.ModuleInstance) (wasm.ModuleEngine, error) { - me := &moduleEngine{ - functions: make([]function, len(module.FunctionSection)+int(module.ImportFunctionCount)), - } - - // Note: imported functions are resolved in moduleEngine.ResolveImportedFunction. - - cm, ok, err := e.getCompiledModule(module, - // listeners arg is not needed here since NewModuleEngine is called after CompileModule which - // ensures the association of listener with *code. - nil) - if !ok { - return nil, errors.New("source module must be compiled before instantiation") - } else if err != nil { - return nil, err - } - - for i := range cm.functions { - c := &cm.functions[i] - offset := int(module.ImportFunctionCount) + i - typeIndex := module.FunctionSection[i] - me.functions[offset] = function{ - codeInitialAddress: cm.executable.Addr() + c.executableOffset, - moduleInstance: instance, - typeID: instance.TypeIDs[typeIndex], - funcType: &module.TypeSection[typeIndex], - parent: c, - } - } - - me.module = cm - return me, nil -} - -// ResolveImportedFunction implements wasm.ModuleEngine. -func (e *moduleEngine) ResolveImportedFunction(index, indexInImportedModule wasm.Index, importedModuleEngine wasm.ModuleEngine) { - imported := importedModuleEngine.(*moduleEngine) - // Copies the content from the import target moduleEngine. - e.functions[index] = imported.functions[indexInImportedModule] -} - -// GetGlobalValue implements the same method as documented on wasm.ModuleEngine. -func (e *moduleEngine) GetGlobalValue(wasm.Index) (lo, hi uint64) { - panic("BUG: GetGlobalValue should never be called on compiler mode") -} - -// OwnsGlobals implements the same method as documented on wasm.ModuleEngine. -func (e *moduleEngine) OwnsGlobals() bool { return false } - -// ResolveImportedMemory implements wasm.ModuleEngine. -func (e *moduleEngine) ResolveImportedMemory(wasm.ModuleEngine) {} - -// FunctionInstanceReference implements the same method as documented on wasm.ModuleEngine. -func (e *moduleEngine) FunctionInstanceReference(funcIndex wasm.Index) wasm.Reference { - return uintptr(unsafe.Pointer(&e.functions[funcIndex])) -} - -// DoneInstantiation implements wasm.ModuleEngine. -func (e *moduleEngine) DoneInstantiation() {} - -// NewFunction implements wasm.ModuleEngine. -func (e *moduleEngine) NewFunction(index wasm.Index) api.Function { - return e.newFunction(&e.functions[index]) -} - -func (e *moduleEngine) newFunction(f *function) api.Function { - initStackSize := initialStackSize - if initialStackSize < f.parent.stackPointerCeil { - initStackSize = f.parent.stackPointerCeil * 2 - } - return e.newCallEngine(initStackSize, f) -} - -// LookupFunction implements the same method as documented on wasm.ModuleEngine. -func (e *moduleEngine) LookupFunction(t *wasm.TableInstance, typeId wasm.FunctionTypeID, tableOffset wasm.Index) (*wasm.ModuleInstance, wasm.Index) { - if tableOffset >= uint32(len(t.References)) || t.Type != wasm.RefTypeFuncref { - panic(wasmruntime.ErrRuntimeInvalidTableAccess) - } - rawPtr := t.References[tableOffset] - if rawPtr == 0 { - panic(wasmruntime.ErrRuntimeInvalidTableAccess) - } - - tf := functionFromUintptr(rawPtr) - if tf.typeID != typeId { - panic(wasmruntime.ErrRuntimeIndirectCallTypeMismatch) - } - return tf.moduleInstance, tf.parent.index -} - -// functionFromUintptr resurrects the original *function from the given uintptr -// which comes from either funcref table or OpcodeRefFunc instruction. -func functionFromUintptr(ptr uintptr) *function { - // Wraps ptrs as the double pointer in order to avoid the unsafe access as detected by race detector. - // - // For example, if we have (*function)(unsafe.Pointer(ptr)) instead, then the race detector's "checkptr" - // subroutine wanrs as "checkptr: pointer arithmetic result points to invalid allocation" - // https://github.com/golang/go/blob/1ce7fcf139417d618c2730010ede2afb41664211/src/runtime/checkptr.go#L69 - var wrapped *uintptr = &ptr - return *(**function)(unsafe.Pointer(wrapped)) -} - -// Definition implements the same method as documented on wasm.ModuleEngine. -func (ce *callEngine) Definition() api.FunctionDefinition { - return ce.initialFn.definition() -} - -func (f *function) definition() api.FunctionDefinition { - compiled := f.parent - return compiled.parent.source.FunctionDefinition(compiled.index) -} - -// Call implements the same method as documented on wasm.ModuleEngine. -func (ce *callEngine) Call(ctx context.Context, params ...uint64) (results []uint64, err error) { - ft := ce.initialFn.funcType - if n := ft.ParamNumInUint64; n != len(params) { - return nil, fmt.Errorf("expected %d params, but passed %d", n, len(params)) - } - return ce.call(ctx, params, nil) -} - -// CallWithStack implements the same method as documented on wasm.ModuleEngine. -func (ce *callEngine) CallWithStack(ctx context.Context, stack []uint64) error { - params, results, err := wasm.SplitCallStack(ce.initialFn.funcType, stack) - if err != nil { - return err - } - _, err = ce.call(ctx, params, results) - return err -} - -func (ce *callEngine) call(ctx context.Context, params, results []uint64) (_ []uint64, err error) { - m := ce.initialFn.moduleInstance - if ce.module.ensureTermination { - select { - case <-ctx.Done(): - // If the provided context is already done, close the call context - // and return the error. - m.CloseWithCtxErr(ctx) - return nil, m.FailIfClosed() - default: - } - } - - // We ensure that this Call method never panics as - // this Call method is indirectly invoked by embedders via store.CallFunction, - // and we have to make sure that all the runtime errors, including the one happening inside - // host functions, will be captured as errors, not panics. - defer func() { - err = ce.deferredOnCall(ctx, m, recover()) - if err == nil { - // If the module closed during the call, and the call didn't err for another reason, set an ExitError. - err = m.FailIfClosed() - } - // Ensure that the compiled module will never be GC'd before this method returns. - runtime.KeepAlive(ce.module) - }() - - ft := ce.initialFn.funcType - ce.initializeStack(ft, params) - - if ce.module.ensureTermination { - done := m.CloseModuleOnCanceledOrTimeout(ctx) - defer done() - } - - snapshotEnabled := ctx.Value(experimental.EnableSnapshotterKey{}) != nil - if snapshotEnabled { - ctx = context.WithValue(ctx, experimental.SnapshotterKey{}, ce) - } - - ce.execWasmFunction(ctx, m, snapshotEnabled) - - // This returns a safe copy of the results, instead of a slice view. If we - // returned a re-slice, the caller could accidentally or purposefully - // corrupt the stack of subsequent calls. - if results == nil && ft.ResultNumInUint64 > 0 { - results = make([]uint64, ft.ResultNumInUint64) - } - copy(results, ce.stack) - return results, nil -} - -// initializeStack initializes callEngine.stack before entering native code. -// -// The stack must look like, if len(params) < len(results): -// -// [arg0, arg1, ..., argN, 0, 0, 0, ... -// { } ^ -// callFrame | -// | -// stackPointer -// -// else: -// -// [arg0, arg1, ..., argN, _, _, _, 0, 0, 0, ... -// | | { } ^ -// |reserved| callFrame | -// | | | -// |--------> stackPointer -// len(results)-len(params) -// -// where we reserve the slots below the callframe with the length len(results)-len(params). -// -// Note: callFrame { } is zeroed to indicate that the initial "caller" is this callEngine, not the Wasm function. -// -// See callEngine.stack as well. -func (ce *callEngine) initializeStack(tp *wasm.FunctionType, args []uint64) { - for _, v := range args { - ce.pushValue(v) - } - - ce.stackPointer = uint64(callFrameOffset(tp)) - - for i := 0; i < callFrameDataSizeInUint64; i++ { - ce.stack[ce.stackPointer] = 0 - ce.stackPointer++ - } -} - -// callFrameOffset returns the offset of the call frame from the stack base pointer. -// -// See the diagram in callEngine.stack. -func callFrameOffset(funcType *wasm.FunctionType) (ret int) { - ret = funcType.ResultNumInUint64 - if ret < funcType.ParamNumInUint64 { - ret = funcType.ParamNumInUint64 - } - return -} - -// deferredOnCall takes the recovered value `recovered`, and wraps it -// with the call frame stack traces when not nil. This also resets -// the state of callEngine so that it can be used for the subsequent calls. -// -// This is defined for testability. -func (ce *callEngine) deferredOnCall(ctx context.Context, m *wasm.ModuleInstance, recovered interface{}) (err error) { - if s, ok := recovered.(*snapshot); ok { - // A snapshot that wasn't handled was created by a different call engine possibly from a nested wasm invocation, - // let it propagate up to be handled by the caller. - panic(s) - } - if recovered != nil { - builder := wasmdebug.NewErrorBuilder() - - // Unwinds call frames from the values stack, starting from the - // current function `ce.fn`, and the current stack base pointer `ce.stackBasePointerInBytes`. - fn := ce.fn - pc := uint64(ce.returnAddress) - stackBasePointer := int(ce.stackBasePointerInBytes >> 3) - functionListeners := make([]functionListenerInvocation, 0, 16) - - left := wasmdebug.MaxFrames - for { - def := fn.definition() - - // sourceInfo holds the source code information corresponding to the frame. - // It is not empty only when the DWARF is enabled. - var sources []string - if p := fn.parent; p.parent.executable.Bytes() != nil { - if fn.parent.sourceOffsetMap.irOperationSourceOffsetsInWasmBinary != nil { - offset := fn.getSourceOffsetInWasmBinary(pc) - sources = p.parent.source.DWARFLines.Line(offset) - } - } - builder.AddFrame(def.DebugName(), def.ParamTypes(), def.ResultTypes(), sources) - left-- - - if fn.parent.listener != nil { - functionListeners = append(functionListeners, functionListenerInvocation{ - FunctionListener: fn.parent.listener, - def: fn.definition(), - }) - } - - callFrameOffset := callFrameOffset(fn.funcType) - if left > 0 && stackBasePointer != 0 { - frame := *(*callFrame)(unsafe.Pointer(&ce.stack[stackBasePointer+callFrameOffset])) - fn = frame.function - pc = uint64(frame.returnAddress) - stackBasePointer = int(frame.returnStackBasePointerInBytes >> 3) - } else { // base == 0 means that this was the last call frame stacked. - break - } - } - - err = builder.FromRecovered(recovered) - for i := range functionListeners { - functionListeners[i].Abort(ctx, m, functionListeners[i].def, err) - } - } - - // Allows the reuse of CallEngine. - ce.stackBasePointerInBytes, ce.stackPointer, ce.moduleInstance = 0, 0, nil - ce.moduleContext.fn = ce.initialFn - return -} - -// getSourceOffsetInWasmBinary returns the corresponding offset in the original Wasm binary's code section -// for the given pc (which is an absolute address in the memory). -// If needPreviousInstr equals true, this returns the previous instruction's offset for the given pc. -func (f *function) getSourceOffsetInWasmBinary(pc uint64) uint64 { - srcMap := &f.parent.sourceOffsetMap - n := bitpack.OffsetArrayLen(srcMap.irOperationOffsetsInNativeBinary) + 1 - - // Calculate the offset in the compiled native binary. - pcOffsetInNativeBinary := pc - uint64(f.codeInitialAddress) - - // Then, do the binary search on the list of offsets in the native binary - // for all the IR operations. This returns the index of the *next* IR - // operation of the one corresponding to the origin of this pc. - // See sort.Search. - // - // TODO: the underlying implementation of irOperationOffsetsInNativeBinary - // uses uses delta encoding an calls to the Index method might require a - // O(N) scan of the underlying array, turning binary search into a - // O(N*log(N)) operation. If this code path ends up being a bottleneck, - // we could add a Search method on the bitpack.OffsetArray types to delegate - // the lookup to the underlying data structure, allowing for the selection - // of a more optimized version of the algorithm. If you do so, please add a - // benchmark to verify the impact on compute time. - index := sort.Search(n, func(i int) bool { - if i == n-1 { - return true - } - return srcMap.irOperationOffsetsInNativeBinary.Index(i) >= pcOffsetInNativeBinary - }) - if index == 0 && bitpack.OffsetArrayLen(srcMap.irOperationSourceOffsetsInWasmBinary) > 0 { - // When pc is the beginning of the function, the next IR - // operation (returned by sort.Search) is the first of the - // offset map. - return srcMap.irOperationSourceOffsetsInWasmBinary.Index(0) - } - - if index == n || index == 0 { // This case, somehow pc is not found in the source offset map. - return 0 - } else { - return srcMap.irOperationSourceOffsetsInWasmBinary.Index(index - 1) - } -} - -func NewEngine(_ context.Context, enabledFeatures api.CoreFeatures, fileCache filecache.Cache) wasm.Engine { - return newEngine(enabledFeatures, fileCache) -} - -func newEngine(enabledFeatures api.CoreFeatures, fileCache filecache.Cache) *engine { - return &engine{ - enabledFeatures: enabledFeatures, - codes: map[wasm.ModuleID]*compiledModule{}, - setFinalizer: runtime.SetFinalizer, - fileCache: fileCache, - wazeroVersion: version.GetWazeroVersion(), - } -} - -// Do not make this variable as constant, otherwise there would be -// dangerous memory access from native code. -// -// Background: Go has a mechanism called "goroutine stack-shrink" where Go -// runtime shrinks Goroutine's stack when it is GCing. Shrinking means that -// all the contents on the goroutine stack will be relocated by runtime, -// Therefore, the memory address of these contents change undeterministically. -// Not only shrinks, but also Go runtime grows the goroutine stack at any point -// of function call entries, which also might end up relocating contents. -// -// On the other hand, we hold pointers to the data region of value stack and -// call-frame stack slices and use these raw pointers from native code. -// Therefore, it is dangerous if these two stacks are allocated on stack -// as these stack's address might be changed by Goroutine which we cannot -// detect. -// -// By declaring these values as `var`, slices created via `make([]..., var)` -// will never be allocated on stack [1]. This means accessing these slices via -// raw pointers is safe: As of version 1.21, Go's garbage collector never relocates -// heap-allocated objects (aka no compaction of memory [2]). -// -// On Go upgrades, re-validate heap-allocation via `go build -gcflags='-m' ./internal/engine/compiler/...`. -// -// [1] https://github.com/golang/go/blob/c19c4c566c63818dfd059b352e52c4710eecf14d/src/cmd/compile/internal/escape/utils.go#L213-L215 -// [2] https://github.com/golang/go/blob/c19c4c566c63818dfd059b352e52c4710eecf14d/src/runtime/mgc.go#L9 -// [3] https://mayurwadekar2.medium.com/escape-analysis-in-golang-ee40a1c064c1 -// [4] https://medium.com/@yulang.chu/go-stack-or-heap-2-slices-which-keep-in-stack-have-limitation-of-size-b3f3adfd6190 -var initialStackSize uint64 = 512 - -func (e *moduleEngine) newCallEngine(stackSize uint64, fn *function) *callEngine { - ce := &callEngine{ - stack: make([]uint64, stackSize), - archContext: newArchContext(), - initialFn: fn, - moduleContext: moduleContext{fn: fn}, - module: e.module, - } - - stackHeader := (*reflect.SliceHeader)(unsafe.Pointer(&ce.stack)) - ce.stackContext = stackContext{ - stackElement0Address: stackHeader.Data, - stackLenInBytes: uint64(stackHeader.Len) << 3, - } - return ce -} - -func (ce *callEngine) popValue() (ret uint64) { - ce.stackContext.stackPointer-- - ret = ce.stack[ce.stackTopIndex()] - return -} - -func (ce *callEngine) pushValue(v uint64) { - ce.stack[ce.stackTopIndex()] = v - ce.stackContext.stackPointer++ -} - -func (ce *callEngine) stackTopIndex() uint64 { - return ce.stackContext.stackPointer + (ce.stackContext.stackBasePointerInBytes >> 3) -} - -const ( - builtinFunctionIndexMemoryGrow wasm.Index = iota - builtinFunctionIndexGrowStack - builtinFunctionIndexTableGrow - builtinFunctionIndexFunctionListenerBefore - builtinFunctionIndexFunctionListenerAfter - builtinFunctionIndexCheckExitCode - // builtinFunctionIndexBreakPoint is internal (only for wazero developers). Disabled by default. - builtinFunctionIndexBreakPoint - builtinFunctionMemoryWait32 - builtinFunctionMemoryWait64 - builtinFunctionMemoryNotify -) - -func (ce *callEngine) execWasmFunction(ctx context.Context, m *wasm.ModuleInstance, snapshotEnabled bool) { - codeAddr := ce.initialFn.codeInitialAddress - modAddr := ce.initialFn.moduleInstance - -entry: - { - // Call into the native code. - nativecall(codeAddr, ce, modAddr) - - // Check the status code from Compiler code. - switch status := ce.exitContext.statusCode; status { - case nativeCallStatusCodeReturned: - case nativeCallStatusCodeCallGoHostFunction: - calleeHostFunction := ce.moduleContext.fn - base := int(ce.stackBasePointerInBytes >> 3) - - // In the compiler engine, ce.stack has enough capacity for the - // max of param or result length, so we don't need to grow when - // there are more results than parameters. - stackLen := calleeHostFunction.funcType.ParamNumInUint64 - if resultLen := calleeHostFunction.funcType.ResultNumInUint64; resultLen > stackLen { - stackLen = resultLen - } - stack := ce.stack[base : base+stackLen] - - fn := calleeHostFunction.parent.goFunc - func() { - if snapshotEnabled { - defer func() { - if r := recover(); r != nil { - if s, ok := r.(*snapshot); ok && s.ce == ce { - s.doRestore() - } else { - panic(r) - } - } - }() - } - switch fn := fn.(type) { - case api.GoModuleFunction: - fn.Call(ctx, ce.callerModuleInstance, stack) - case api.GoFunction: - fn.Call(ctx, stack) - } - }() - - codeAddr, modAddr = ce.returnAddress, ce.moduleInstance - goto entry - case nativeCallStatusCodeCallBuiltInFunction: - caller := ce.moduleContext.fn - switch ce.exitContext.builtinFunctionCallIndex { - case builtinFunctionIndexMemoryGrow: - ce.builtinFunctionMemoryGrow(caller.moduleInstance.MemoryInstance) - case builtinFunctionIndexGrowStack: - ce.builtinFunctionGrowStack(caller.parent.stackPointerCeil) - case builtinFunctionIndexTableGrow: - ce.builtinFunctionTableGrow(caller.moduleInstance.Tables) - case builtinFunctionMemoryWait32: - ce.builtinFunctionMemoryWait32(caller.moduleInstance.MemoryInstance) - case builtinFunctionMemoryWait64: - ce.builtinFunctionMemoryWait64(caller.moduleInstance.MemoryInstance) - case builtinFunctionMemoryNotify: - ce.builtinFunctionMemoryNotify(caller.moduleInstance.MemoryInstance) - case builtinFunctionIndexFunctionListenerBefore: - ce.builtinFunctionFunctionListenerBefore(ctx, m, caller) - case builtinFunctionIndexFunctionListenerAfter: - ce.builtinFunctionFunctionListenerAfter(ctx, m, caller) - case builtinFunctionIndexCheckExitCode: - // Note: this operation must be done in Go, not native code. The reason is that - // native code cannot be preempted and that means it can block forever if there are not - // enough OS threads (which we don't have control over). - if err := m.FailIfClosed(); err != nil { - panic(err) - } - } - if false { - if ce.exitContext.builtinFunctionCallIndex == builtinFunctionIndexBreakPoint { - runtime.Breakpoint() - } - } - - codeAddr, modAddr = ce.returnAddress, ce.moduleInstance - goto entry - default: - status.causePanic() - } - } -} - -// callStackCeiling is the maximum WebAssembly call frame stack height. This allows wazero to raise -// wasm.ErrCallStackOverflow instead of overflowing the Go runtime. -// -// The default value should suffice for most use cases. Those wishing to change this can via `go build -ldflags`. -// -// TODO: allows to configure this via context? -var callStackCeiling = uint64(5000000) // in uint64 (8 bytes) == 40000000 bytes in total == 40mb. - -func (ce *callEngine) builtinFunctionGrowStack(stackPointerCeil uint64) { - oldLen := uint64(len(ce.stack)) - if callStackCeiling < oldLen { - panic(wasmruntime.ErrRuntimeStackOverflow) - } - - // Extends the stack's length to oldLen*2+stackPointerCeil. - newLen := oldLen<<1 + (stackPointerCeil) - newStack := make([]uint64, newLen) - top := ce.stackTopIndex() - copy(newStack[:top], ce.stack[:top]) - ce.stack = newStack - stackHeader := (*reflect.SliceHeader)(unsafe.Pointer(&ce.stack)) - ce.stackContext.stackElement0Address = stackHeader.Data - ce.stackContext.stackLenInBytes = newLen << 3 -} - -func (ce *callEngine) builtinFunctionMemoryGrow(mem *wasm.MemoryInstance) { - newPages := ce.popValue() - - if res, ok := mem.Grow(uint32(newPages)); !ok { - ce.pushValue(uint64(0xffffffff)) // = -1 in signed 32-bit integer. - } else { - ce.pushValue(uint64(res)) - } - - // Update the moduleContext fields as they become stale after the update ^^. - bufSliceHeader := (*reflect.SliceHeader)(unsafe.Pointer(&mem.Buffer)) - if mem.Shared { - // Use atomic to ensure visibility for good measure. Though in practice, we know - // the data address should never change for shared memory, and the length field - // in the context is ignored. - atomic.StoreUint64(&ce.moduleContext.memorySliceLen, uint64(bufSliceHeader.Len)) - atomic.StoreUintptr(&ce.moduleContext.memoryElement0Address, bufSliceHeader.Data) - } else { - ce.moduleContext.memorySliceLen = uint64(bufSliceHeader.Len) - ce.moduleContext.memoryElement0Address = bufSliceHeader.Data - } -} - -func (ce *callEngine) builtinFunctionTableGrow(tables []*wasm.TableInstance) { - tableIndex := uint32(ce.popValue()) - table := tables[tableIndex] // verified not to be out of range by the func validation at compilation phase. - num := ce.popValue() - ref := ce.popValue() - res := table.Grow(uint32(num), uintptr(ref)) - ce.pushValue(uint64(res)) -} - -func (ce *callEngine) builtinFunctionMemoryWait32(mem *wasm.MemoryInstance) { - if !mem.Shared { - panic(wasmruntime.ErrRuntimeExpectedSharedMemory) - } - - timeout := int64(ce.popValue()) - exp := uint32(ce.popValue()) - addr := uintptr(ce.popValue()) - base := uintptr(unsafe.Pointer(&mem.Buffer[0])) - - offset := uint32(addr - base) - - ce.pushValue(mem.Wait32(offset, exp, timeout, func(mem *wasm.MemoryInstance, offset uint32) uint32 { - addr := unsafe.Add(unsafe.Pointer(&mem.Buffer[0]), offset) - return atomic.LoadUint32((*uint32)(addr)) - })) -} - -func (ce *callEngine) builtinFunctionMemoryWait64(mem *wasm.MemoryInstance) { - if !mem.Shared { - panic(wasmruntime.ErrRuntimeExpectedSharedMemory) - } - - timeout := int64(ce.popValue()) - exp := ce.popValue() - addr := uintptr(ce.popValue()) - base := uintptr(unsafe.Pointer(&mem.Buffer[0])) - - offset := uint32(addr - base) - - ce.pushValue(mem.Wait64(offset, exp, timeout, func(mem *wasm.MemoryInstance, offset uint32) uint64 { - addr := unsafe.Add(unsafe.Pointer(&mem.Buffer[0]), offset) - return atomic.LoadUint64((*uint64)(addr)) - })) -} - -func (ce *callEngine) builtinFunctionMemoryNotify(mem *wasm.MemoryInstance) { - count := ce.popValue() - addr := ce.popValue() - - offset := uint32(uintptr(addr) - uintptr(unsafe.Pointer(&mem.Buffer[0]))) - - ce.pushValue(uint64(mem.Notify(offset, uint32(count)))) -} - -// snapshot implements experimental.Snapshot -type snapshot struct { - stackPointer uint64 - stackBasePointerInBytes uint64 - returnAddress uint64 - hostBase int - stack []uint64 - - ret []uint64 - - ce *callEngine -} - -// Snapshot implements the same method as documented on experimental.Snapshotter. -func (ce *callEngine) Snapshot() experimental.Snapshot { - hostBase := int(ce.stackBasePointerInBytes >> 3) - - stackTop := int(ce.stackTopIndex()) - stack := make([]uint64, stackTop) - copy(stack, ce.stack[:stackTop]) - - return &snapshot{ - stackPointer: ce.stackContext.stackPointer, - stackBasePointerInBytes: ce.stackBasePointerInBytes, - returnAddress: uint64(ce.returnAddress), - hostBase: hostBase, - stack: stack, - ce: ce, - } -} - -// Restore implements the same method as documented on experimental.Snapshot. -func (s *snapshot) Restore(ret []uint64) { - s.ret = ret - panic(s) -} - -func (s *snapshot) doRestore() { - ce := s.ce - ce.stackContext.stackPointer = s.stackPointer - ce.stackContext.stackBasePointerInBytes = s.stackBasePointerInBytes - copy(ce.stack, s.stack) - ce.returnAddress = uintptr(s.returnAddress) - copy(ce.stack[s.hostBase:], s.ret) -} - -// Error implements the same method on error. -func (s *snapshot) Error() string { - return "unhandled snapshot restore, this generally indicates restore was called from a different " + - "exported function invocation than snapshot" -} - -// stackIterator implements experimental.StackIterator. -type stackIterator struct { - stack []uint64 - fn *function - base int - pc uint64 - started bool -} - -func (si *stackIterator) reset(stack []uint64, fn *function, base int, pc uint64) { - si.stack = stack - si.fn = fn - si.base = base - si.pc = pc - si.started = false -} - -func (si *stackIterator) clear() { - si.stack = nil - si.fn = nil - si.base = 0 - si.started = false -} - -// Next implements the same method as documented on experimental.StackIterator. -func (si *stackIterator) Next() bool { - if !si.started { - si.started = true - return true - } - - if si.fn == nil || si.base == 0 { - return false - } - - frame := si.base + callFrameOffset(si.fn.funcType) - si.pc = si.stack[frame+0] - si.base = int(si.stack[frame+1] >> 3) - // *function lives in the third field of callFrame struct. This must be - // aligned with the definition of callFrame struct. - si.fn = *(**function)(unsafe.Pointer(&si.stack[frame+2])) - return si.fn != nil -} - -// ProgramCounter implements the same method as documented on experimental.StackIterator. -func (si *stackIterator) ProgramCounter() experimental.ProgramCounter { - return experimental.ProgramCounter(si.pc) -} - -// Function implements the same method as documented on experimental.StackIterator. -func (si *stackIterator) Function() experimental.InternalFunction { - return internalFunction{si.fn} -} - -// internalFunction implements experimental.InternalFunction. -type internalFunction struct{ *function } - -// Definition implements the same method as documented on experimental.InternalFunction. -func (f internalFunction) Definition() api.FunctionDefinition { - return f.definition() -} - -// SourceOffsetForPC implements the same method as documented on experimental.InternalFunction. -func (f internalFunction) SourceOffsetForPC(pc experimental.ProgramCounter) uint64 { - p := f.parent - if bitpack.OffsetArrayLen(p.sourceOffsetMap.irOperationSourceOffsetsInWasmBinary) == 0 { - return 0 // source not available - } - return f.getSourceOffsetInWasmBinary(uint64(pc)) -} - -func (ce *callEngine) builtinFunctionFunctionListenerBefore(ctx context.Context, mod api.Module, fn *function) { - base := int(ce.stackBasePointerInBytes >> 3) - pc := uint64(ce.returnAddress) - ce.stackIterator.reset(ce.stack, fn, base, pc) - - params := ce.stack[base : base+fn.funcType.ParamNumInUint64] - fn.parent.listener.Before(ctx, mod, fn.definition(), params, &ce.stackIterator) - - ce.stackIterator.clear() -} - -func (ce *callEngine) builtinFunctionFunctionListenerAfter(ctx context.Context, mod api.Module, fn *function) { - base := int(ce.stackBasePointerInBytes >> 3) - fn.parent.listener.After(ctx, mod, fn.definition(), ce.stack[base:base+fn.funcType.ResultNumInUint64]) -} - -func compileGoDefinedHostFunction(buf asm.Buffer, cmp compiler) error { - if err := cmp.compileGoDefinedHostFunction(); err != nil { - return err - } - _, err := cmp.compile(buf) - return err -} - -type asmNodes struct { - nodes []asm.Node -} - -type offsets struct { - values []uint64 -} - -func compileWasmFunction(buf asm.Buffer, cmp compiler, ir *wazeroir.CompilationResult, asmNodes *asmNodes, offsets *offsets) (spCeil uint64, sm sourceOffsetMap, err error) { - if err = cmp.compilePreamble(); err != nil { - err = fmt.Errorf("failed to emit preamble: %w", err) - return - } - - needSourceOffsets := len(ir.IROperationSourceOffsetsInWasmBinary) > 0 - var irOpBegins []asm.Node - if needSourceOffsets { - irOpBegins = append(asmNodes.nodes[:0], make([]asm.Node, len(ir.Operations))...) - defer func() { asmNodes.nodes = irOpBegins }() - } - - var skip bool - for i := range ir.Operations { - op := &ir.Operations[i] - if needSourceOffsets { - // If this compilation requires source offsets for DWARF based back trace, - // we emit a NOP node at the beginning of each IR operation to get the - // binary offset of the beginning of the corresponding compiled native code. - irOpBegins[i] = cmp.compileNOP() - } - - // Compiler determines whether skip the entire label. - // For example, if the label doesn't have any caller, - // we don't need to generate native code at all as we never reach the region. - if op.Kind == wazeroir.OperationKindLabel { - skip = cmp.compileLabel(op) - } - if skip { - continue - } - - if false { - fmt.Printf("compiling op=%s: %s\n", op.Kind, cmp) - } - switch op.Kind { - case wazeroir.OperationKindUnreachable: - err = cmp.compileUnreachable() - case wazeroir.OperationKindLabel: - // label op is already handled ^^. - case wazeroir.OperationKindBr: - err = cmp.compileBr(op) - case wazeroir.OperationKindBrIf: - err = cmp.compileBrIf(op) - case wazeroir.OperationKindBrTable: - err = cmp.compileBrTable(op) - case wazeroir.OperationKindCall: - err = cmp.compileCall(op) - case wazeroir.OperationKindCallIndirect: - err = cmp.compileCallIndirect(op) - case wazeroir.OperationKindDrop: - err = cmp.compileDrop(op) - case wazeroir.OperationKindSelect: - err = cmp.compileSelect(op) - case wazeroir.OperationKindPick: - err = cmp.compilePick(op) - case wazeroir.OperationKindSet: - err = cmp.compileSet(op) - case wazeroir.OperationKindGlobalGet: - err = cmp.compileGlobalGet(op) - case wazeroir.OperationKindGlobalSet: - err = cmp.compileGlobalSet(op) - case wazeroir.OperationKindLoad: - err = cmp.compileLoad(op) - case wazeroir.OperationKindLoad8: - err = cmp.compileLoad8(op) - case wazeroir.OperationKindLoad16: - err = cmp.compileLoad16(op) - case wazeroir.OperationKindLoad32: - err = cmp.compileLoad32(op) - case wazeroir.OperationKindStore: - err = cmp.compileStore(op) - case wazeroir.OperationKindStore8: - err = cmp.compileStore8(op) - case wazeroir.OperationKindStore16: - err = cmp.compileStore16(op) - case wazeroir.OperationKindStore32: - err = cmp.compileStore32(op) - case wazeroir.OperationKindMemorySize: - err = cmp.compileMemorySize() - case wazeroir.OperationKindMemoryGrow: - err = cmp.compileMemoryGrow() - case wazeroir.OperationKindConstI32: - err = cmp.compileConstI32(op) - case wazeroir.OperationKindConstI64: - err = cmp.compileConstI64(op) - case wazeroir.OperationKindConstF32: - err = cmp.compileConstF32(op) - case wazeroir.OperationKindConstF64: - err = cmp.compileConstF64(op) - case wazeroir.OperationKindEq: - err = cmp.compileEq(op) - case wazeroir.OperationKindNe: - err = cmp.compileNe(op) - case wazeroir.OperationKindEqz: - err = cmp.compileEqz(op) - case wazeroir.OperationKindLt: - err = cmp.compileLt(op) - case wazeroir.OperationKindGt: - err = cmp.compileGt(op) - case wazeroir.OperationKindLe: - err = cmp.compileLe(op) - case wazeroir.OperationKindGe: - err = cmp.compileGe(op) - case wazeroir.OperationKindAdd: - err = cmp.compileAdd(op) - case wazeroir.OperationKindSub: - err = cmp.compileSub(op) - case wazeroir.OperationKindMul: - err = cmp.compileMul(op) - case wazeroir.OperationKindClz: - err = cmp.compileClz(op) - case wazeroir.OperationKindCtz: - err = cmp.compileCtz(op) - case wazeroir.OperationKindPopcnt: - err = cmp.compilePopcnt(op) - case wazeroir.OperationKindDiv: - err = cmp.compileDiv(op) - case wazeroir.OperationKindRem: - err = cmp.compileRem(op) - case wazeroir.OperationKindAnd: - err = cmp.compileAnd(op) - case wazeroir.OperationKindOr: - err = cmp.compileOr(op) - case wazeroir.OperationKindXor: - err = cmp.compileXor(op) - case wazeroir.OperationKindShl: - err = cmp.compileShl(op) - case wazeroir.OperationKindShr: - err = cmp.compileShr(op) - case wazeroir.OperationKindRotl: - err = cmp.compileRotl(op) - case wazeroir.OperationKindRotr: - err = cmp.compileRotr(op) - case wazeroir.OperationKindAbs: - err = cmp.compileAbs(op) - case wazeroir.OperationKindNeg: - err = cmp.compileNeg(op) - case wazeroir.OperationKindCeil: - err = cmp.compileCeil(op) - case wazeroir.OperationKindFloor: - err = cmp.compileFloor(op) - case wazeroir.OperationKindTrunc: - err = cmp.compileTrunc(op) - case wazeroir.OperationKindNearest: - err = cmp.compileNearest(op) - case wazeroir.OperationKindSqrt: - err = cmp.compileSqrt(op) - case wazeroir.OperationKindMin: - err = cmp.compileMin(op) - case wazeroir.OperationKindMax: - err = cmp.compileMax(op) - case wazeroir.OperationKindCopysign: - err = cmp.compileCopysign(op) - case wazeroir.OperationKindI32WrapFromI64: - err = cmp.compileI32WrapFromI64() - case wazeroir.OperationKindITruncFromF: - err = cmp.compileITruncFromF(op) - case wazeroir.OperationKindFConvertFromI: - err = cmp.compileFConvertFromI(op) - case wazeroir.OperationKindF32DemoteFromF64: - err = cmp.compileF32DemoteFromF64() - case wazeroir.OperationKindF64PromoteFromF32: - err = cmp.compileF64PromoteFromF32() - case wazeroir.OperationKindI32ReinterpretFromF32: - err = cmp.compileI32ReinterpretFromF32() - case wazeroir.OperationKindI64ReinterpretFromF64: - err = cmp.compileI64ReinterpretFromF64() - case wazeroir.OperationKindF32ReinterpretFromI32: - err = cmp.compileF32ReinterpretFromI32() - case wazeroir.OperationKindF64ReinterpretFromI64: - err = cmp.compileF64ReinterpretFromI64() - case wazeroir.OperationKindExtend: - err = cmp.compileExtend(op) - case wazeroir.OperationKindSignExtend32From8: - err = cmp.compileSignExtend32From8() - case wazeroir.OperationKindSignExtend32From16: - err = cmp.compileSignExtend32From16() - case wazeroir.OperationKindSignExtend64From8: - err = cmp.compileSignExtend64From8() - case wazeroir.OperationKindSignExtend64From16: - err = cmp.compileSignExtend64From16() - case wazeroir.OperationKindSignExtend64From32: - err = cmp.compileSignExtend64From32() - case wazeroir.OperationKindMemoryInit: - err = cmp.compileMemoryInit(op) - case wazeroir.OperationKindDataDrop: - err = cmp.compileDataDrop(op) - case wazeroir.OperationKindMemoryCopy: - err = cmp.compileMemoryCopy() - case wazeroir.OperationKindMemoryFill: - err = cmp.compileMemoryFill() - case wazeroir.OperationKindTableInit: - err = cmp.compileTableInit(op) - case wazeroir.OperationKindElemDrop: - err = cmp.compileElemDrop(op) - case wazeroir.OperationKindTableCopy: - err = cmp.compileTableCopy(op) - case wazeroir.OperationKindRefFunc: - err = cmp.compileRefFunc(op) - case wazeroir.OperationKindTableGet: - err = cmp.compileTableGet(op) - case wazeroir.OperationKindTableSet: - err = cmp.compileTableSet(op) - case wazeroir.OperationKindTableGrow: - err = cmp.compileTableGrow(op) - case wazeroir.OperationKindTableSize: - err = cmp.compileTableSize(op) - case wazeroir.OperationKindTableFill: - err = cmp.compileTableFill(op) - case wazeroir.OperationKindV128Const: - err = cmp.compileV128Const(op) - case wazeroir.OperationKindV128Add: - err = cmp.compileV128Add(op) - case wazeroir.OperationKindV128Sub: - err = cmp.compileV128Sub(op) - case wazeroir.OperationKindV128Load: - err = cmp.compileV128Load(op) - case wazeroir.OperationKindV128LoadLane: - err = cmp.compileV128LoadLane(op) - case wazeroir.OperationKindV128Store: - err = cmp.compileV128Store(op) - case wazeroir.OperationKindV128StoreLane: - err = cmp.compileV128StoreLane(op) - case wazeroir.OperationKindV128ExtractLane: - err = cmp.compileV128ExtractLane(op) - case wazeroir.OperationKindV128ReplaceLane: - err = cmp.compileV128ReplaceLane(op) - case wazeroir.OperationKindV128Splat: - err = cmp.compileV128Splat(op) - case wazeroir.OperationKindV128Shuffle: - err = cmp.compileV128Shuffle(op) - case wazeroir.OperationKindV128Swizzle: - err = cmp.compileV128Swizzle(op) - case wazeroir.OperationKindV128AnyTrue: - err = cmp.compileV128AnyTrue(op) - case wazeroir.OperationKindV128AllTrue: - err = cmp.compileV128AllTrue(op) - case wazeroir.OperationKindV128BitMask: - err = cmp.compileV128BitMask(op) - case wazeroir.OperationKindV128And: - err = cmp.compileV128And(op) - case wazeroir.OperationKindV128Not: - err = cmp.compileV128Not(op) - case wazeroir.OperationKindV128Or: - err = cmp.compileV128Or(op) - case wazeroir.OperationKindV128Xor: - err = cmp.compileV128Xor(op) - case wazeroir.OperationKindV128Bitselect: - err = cmp.compileV128Bitselect(op) - case wazeroir.OperationKindV128AndNot: - err = cmp.compileV128AndNot(op) - case wazeroir.OperationKindV128Shl: - err = cmp.compileV128Shl(op) - case wazeroir.OperationKindV128Shr: - err = cmp.compileV128Shr(op) - case wazeroir.OperationKindV128Cmp: - err = cmp.compileV128Cmp(op) - case wazeroir.OperationKindV128AddSat: - err = cmp.compileV128AddSat(op) - case wazeroir.OperationKindV128SubSat: - err = cmp.compileV128SubSat(op) - case wazeroir.OperationKindV128Mul: - err = cmp.compileV128Mul(op) - case wazeroir.OperationKindV128Div: - err = cmp.compileV128Div(op) - case wazeroir.OperationKindV128Neg: - err = cmp.compileV128Neg(op) - case wazeroir.OperationKindV128Sqrt: - err = cmp.compileV128Sqrt(op) - case wazeroir.OperationKindV128Abs: - err = cmp.compileV128Abs(op) - case wazeroir.OperationKindV128Popcnt: - err = cmp.compileV128Popcnt(op) - case wazeroir.OperationKindV128Min: - err = cmp.compileV128Min(op) - case wazeroir.OperationKindV128Max: - err = cmp.compileV128Max(op) - case wazeroir.OperationKindV128AvgrU: - err = cmp.compileV128AvgrU(op) - case wazeroir.OperationKindV128Pmin: - err = cmp.compileV128Pmin(op) - case wazeroir.OperationKindV128Pmax: - err = cmp.compileV128Pmax(op) - case wazeroir.OperationKindV128Ceil: - err = cmp.compileV128Ceil(op) - case wazeroir.OperationKindV128Floor: - err = cmp.compileV128Floor(op) - case wazeroir.OperationKindV128Trunc: - err = cmp.compileV128Trunc(op) - case wazeroir.OperationKindV128Nearest: - err = cmp.compileV128Nearest(op) - case wazeroir.OperationKindV128Extend: - err = cmp.compileV128Extend(op) - case wazeroir.OperationKindV128ExtMul: - err = cmp.compileV128ExtMul(op) - case wazeroir.OperationKindV128Q15mulrSatS: - err = cmp.compileV128Q15mulrSatS(op) - case wazeroir.OperationKindV128ExtAddPairwise: - err = cmp.compileV128ExtAddPairwise(op) - case wazeroir.OperationKindV128FloatPromote: - err = cmp.compileV128FloatPromote(op) - case wazeroir.OperationKindV128FloatDemote: - err = cmp.compileV128FloatDemote(op) - case wazeroir.OperationKindV128FConvertFromI: - err = cmp.compileV128FConvertFromI(op) - case wazeroir.OperationKindV128Dot: - err = cmp.compileV128Dot(op) - case wazeroir.OperationKindV128Narrow: - err = cmp.compileV128Narrow(op) - case wazeroir.OperationKindV128ITruncSatFromF: - err = cmp.compileV128ITruncSatFromF(op) - case wazeroir.OperationKindAtomicLoad: - err = cmp.compileAtomicLoad(op) - case wazeroir.OperationKindAtomicLoad8: - err = cmp.compileAtomicLoad8(op) - case wazeroir.OperationKindAtomicLoad16: - err = cmp.compileAtomicLoad16(op) - case wazeroir.OperationKindAtomicStore: - err = cmp.compileAtomicStore(op) - case wazeroir.OperationKindAtomicStore8: - err = cmp.compileAtomicStore8(op) - case wazeroir.OperationKindAtomicStore16: - err = cmp.compileAtomicStore16(op) - case wazeroir.OperationKindAtomicRMW: - err = cmp.compileAtomicRMW(op) - case wazeroir.OperationKindAtomicRMW8: - err = cmp.compileAtomicRMW8(op) - case wazeroir.OperationKindAtomicRMW16: - err = cmp.compileAtomicRMW16(op) - case wazeroir.OperationKindAtomicRMWCmpxchg: - err = cmp.compileAtomicRMWCmpxchg(op) - case wazeroir.OperationKindAtomicRMW8Cmpxchg: - err = cmp.compileAtomicRMW8Cmpxchg(op) - case wazeroir.OperationKindAtomicRMW16Cmpxchg: - err = cmp.compileAtomicRMW16Cmpxchg(op) - case wazeroir.OperationKindAtomicMemoryWait: - err = cmp.compileAtomicMemoryWait(op) - case wazeroir.OperationKindAtomicMemoryNotify: - err = cmp.compileAtomicMemoryNotify(op) - case wazeroir.OperationKindAtomicFence: - err = cmp.compileAtomicFence(op) - case wazeroir.OperationKindBuiltinFunctionCheckExitCode: - err = cmp.compileBuiltinFunctionCheckExitCode() - default: - err = errors.New("unsupported") - } - if err != nil { - err = fmt.Errorf("operation %s: %w", op.Kind.String(), err) - return - } - } - - spCeil, err = cmp.compile(buf) - if err != nil { - err = fmt.Errorf("failed to compile: %w", err) - return - } - - if needSourceOffsets { - offsetInNativeBin := append(offsets.values[:0], make([]uint64, len(irOpBegins))...) - offsets.values = offsetInNativeBin - for i, nop := range irOpBegins { - offsetInNativeBin[i] = nop.OffsetInBinary() - } - sm.irOperationOffsetsInNativeBinary = bitpack.NewOffsetArray(offsetInNativeBin) - sm.irOperationSourceOffsetsInWasmBinary = bitpack.NewOffsetArray(ir.IROperationSourceOffsetsInWasmBinary) - } - return -} diff --git a/internal/engine/compiler/engine_bench_test.go b/internal/engine/compiler/engine_bench_test.go deleted file mode 100644 index 39bac99e69..0000000000 --- a/internal/engine/compiler/engine_bench_test.go +++ /dev/null @@ -1,45 +0,0 @@ -package compiler - -import ( - "context" - "testing" - - "github.com/tetratelabs/wazero/api" - "github.com/tetratelabs/wazero/experimental" - "github.com/tetratelabs/wazero/internal/wasm" -) - -func BenchmarkCallEngine_builtinFunctionFunctionListener(b *testing.B) { - f := &function{ - funcType: &wasm.FunctionType{ParamNumInUint64: 3}, - parent: &compiledFunction{ - listener: mockListener{ - before: func(context.Context, api.Module, api.FunctionDefinition, []uint64, experimental.StackIterator) { - }, - after: func(context.Context, api.Module, api.FunctionDefinition, []uint64) { - }, - }, - index: 0, - parent: &compiledCode{ - source: &wasm.Module{ - TypeSection: []wasm.FunctionType{{}}, - FunctionSection: []wasm.Index{0}, - CodeSection: []wasm.Code{{Body: []byte{wasm.OpcodeEnd}}}, - }, - }, - }, - } - - ce := &callEngine{ - stack: []uint64{0, 1, 2, 3, 4, 0, 0, 0}, - stackContext: stackContext{stackBasePointerInBytes: 16}, - } - - mod := new(wasm.ModuleInstance) - ctx := context.Background() - - for i := 0; i < b.N; i++ { - ce.builtinFunctionFunctionListenerBefore(ctx, mod, f) - ce.builtinFunctionFunctionListenerAfter(ctx, mod, f) - } -} diff --git a/internal/engine/compiler/engine_cache.go b/internal/engine/compiler/engine_cache.go deleted file mode 100644 index de6a7e3dd0..0000000000 --- a/internal/engine/compiler/engine_cache.go +++ /dev/null @@ -1,254 +0,0 @@ -package compiler - -import ( - "bytes" - "encoding/binary" - "fmt" - "hash/crc32" - "io" - "runtime" - - "github.com/tetratelabs/wazero/experimental" - "github.com/tetratelabs/wazero/internal/platform" - "github.com/tetratelabs/wazero/internal/u32" - "github.com/tetratelabs/wazero/internal/u64" - "github.com/tetratelabs/wazero/internal/wasm" -) - -var crc = crc32.MakeTable(crc32.Castagnoli) - -func (e *engine) deleteCompiledModule(module *wasm.Module) { - e.mux.Lock() - defer e.mux.Unlock() - - delete(e.codes, module.ID) - - // Note: we do not call e.Cache.Delete, as the lifetime of - // the content is up to the implementation of extencache.Cache interface. -} - -func (e *engine) addCompiledModule(module *wasm.Module, cm *compiledModule, withGoFunc bool) (err error) { - e.addCompiledModuleToMemory(module, cm) - if !withGoFunc { - err = e.addCompiledModuleToCache(module, cm) - } - return -} - -func (e *engine) getCompiledModule(module *wasm.Module, listeners []experimental.FunctionListener) (cm *compiledModule, ok bool, err error) { - cm, ok = e.getCompiledModuleFromMemory(module) - if ok { - return - } - cm, ok, err = e.getCompiledModuleFromCache(module) - if ok { - e.addCompiledModuleToMemory(module, cm) - if len(listeners) > 0 { - // Files do not contain the actual listener instances (it's impossible to cache them as files!), so assign each here. - for i := range cm.functions { - cm.functions[i].listener = listeners[i] - } - } - - // As this uses mmap, we need to munmap on the compiled machine code when it's GCed. - e.setFinalizer(cm, releaseCompiledModule) - } - return -} - -func (e *engine) addCompiledModuleToMemory(module *wasm.Module, cm *compiledModule) { - e.mux.Lock() - defer e.mux.Unlock() - e.codes[module.ID] = cm -} - -func (e *engine) getCompiledModuleFromMemory(module *wasm.Module) (cm *compiledModule, ok bool) { - e.mux.RLock() - defer e.mux.RUnlock() - cm, ok = e.codes[module.ID] - return -} - -func (e *engine) addCompiledModuleToCache(module *wasm.Module, cm *compiledModule) (err error) { - if e.fileCache == nil || module.IsHostModule { - return - } - err = e.fileCache.Add(module.ID, serializeCompiledModule(e.wazeroVersion, cm)) - return -} - -func (e *engine) getCompiledModuleFromCache(module *wasm.Module) (cm *compiledModule, hit bool, err error) { - if e.fileCache == nil || module.IsHostModule { - return - } - - // Check if the entries exist in the external cache. - var cached io.ReadCloser - cached, hit, err = e.fileCache.Get(module.ID) - if !hit || err != nil { - return - } - - // Otherwise, we hit the cache on external cache. - // We retrieve *code structures from `cached`. - var staleCache bool - // Note: cached.Close is ensured to be called in deserializeCodes. - cm, staleCache, err = deserializeCompiledModule(e.wazeroVersion, cached, module) - if err != nil { - hit = false - return - } else if staleCache { - return nil, false, e.fileCache.Delete(module.ID) - } - - cm.source = module - return -} - -var wazeroMagic = "WAZERO" // version must be synced with the tag of the wazero library. - -func serializeCompiledModule(wazeroVersion string, cm *compiledModule) io.Reader { - buf := bytes.NewBuffer(nil) - // First 6 byte: WAZERO header. - buf.WriteString(wazeroMagic) - // Next 1 byte: length of version: - buf.WriteByte(byte(len(wazeroVersion))) - // Version of wazero. - buf.WriteString(wazeroVersion) - if cm.ensureTermination { - buf.WriteByte(1) - } else { - buf.WriteByte(0) - } - // Number of *code (== locally defined functions in the module): 4 bytes. - buf.Write(u32.LeBytes(uint32(len(cm.functions)))) - for i := 0; i < len(cm.functions); i++ { - f := &cm.functions[i] - // The stack pointer ceil (8 bytes). - buf.Write(u64.LeBytes(f.stackPointerCeil)) - // The offset of this function in the executable (8 bytes). - buf.Write(u64.LeBytes(uint64(f.executableOffset))) - } - // The length of code segment (8 bytes). - buf.Write(u64.LeBytes(uint64(cm.executable.Len()))) - // Append the native code. - buf.Write(cm.executable.Bytes()) - // Append checksum. - checksum := crc32.Checksum(cm.executable.Bytes(), crc) - buf.Write(u32.LeBytes(checksum)) - return bytes.NewReader(buf.Bytes()) -} - -func deserializeCompiledModule(wazeroVersion string, reader io.ReadCloser, module *wasm.Module) (cm *compiledModule, staleCache bool, err error) { - defer reader.Close() - cacheHeaderSize := len(wazeroMagic) + 1 /* version size */ + len(wazeroVersion) + 1 /* ensure termination */ + 4 /* number of functions */ - - // Read the header before the native code. - header := make([]byte, cacheHeaderSize) - n, err := reader.Read(header) - if err != nil { - return nil, false, fmt.Errorf("compilationcache: error reading header: %v", err) - } - - if n != cacheHeaderSize { - return nil, false, fmt.Errorf("compilationcache: invalid header length: %d", n) - } - - // Check the version compatibility. - versionSize := int(header[len(wazeroMagic)]) - - cachedVersionBegin, cachedVersionEnd := len(wazeroMagic)+1, len(wazeroMagic)+1+versionSize - if cachedVersionEnd >= len(header) { - staleCache = true - return - } else if cachedVersion := string(header[cachedVersionBegin:cachedVersionEnd]); cachedVersion != wazeroVersion { - staleCache = true - return - } - - ensureTermination := header[cachedVersionEnd] != 0 - functionsNum := binary.LittleEndian.Uint32(header[len(header)-4:]) - cm = &compiledModule{ - compiledCode: new(compiledCode), - functions: make([]compiledFunction, functionsNum), - ensureTermination: ensureTermination, - } - - imported := module.ImportFunctionCount - - var eightBytes [8]byte - for i := uint32(0); i < functionsNum; i++ { - f := &cm.functions[i] - f.parent = cm.compiledCode - - // Read the stack pointer ceil. - if f.stackPointerCeil, err = readUint64(reader, &eightBytes); err != nil { - err = fmt.Errorf("compilationcache: error reading func[%d] stack pointer ceil: %v", i, err) - return - } - - // Read the offset of each function in the executable. - var offset uint64 - if offset, err = readUint64(reader, &eightBytes); err != nil { - err = fmt.Errorf("compilationcache: error reading func[%d] executable offset: %v", i, err) - return - } - f.executableOffset = uintptr(offset) - f.index = imported + i - } - - executableLen, err := readUint64(reader, &eightBytes) - if err != nil { - err = fmt.Errorf("compilationcache: error reading executable size: %v", err) - return - } - - if executableLen > 0 { - if err = cm.executable.Map(int(executableLen)); err != nil { - err = fmt.Errorf("compilationcache: error mmapping executable (len=%d): %v", executableLen, err) - return - } - - _, err = io.ReadFull(reader, cm.executable.Bytes()) - if err != nil { - err = fmt.Errorf("compilationcache: error reading executable (len=%d): %v", executableLen, err) - return - } - - expected := crc32.Checksum(cm.executable.Bytes(), crc) - if _, err = io.ReadFull(reader, eightBytes[:4]); err != nil { - return nil, false, fmt.Errorf("compilationcache: could not read checksum: %v", err) - } else if checksum := binary.LittleEndian.Uint32(eightBytes[:4]); expected != checksum { - return nil, false, fmt.Errorf("compilationcache: checksum mismatch (expected %d, got %d)", expected, checksum) - } - - if runtime.GOARCH == "arm64" { - // On arm64, we cannot give all of rwx at the same time, so we change it to exec. - if err = platform.MprotectRX(cm.executable.Bytes()); err != nil { - return - } - } - } - return -} - -// readUint64 strictly reads an uint64 in little-endian byte order, using the -// given array as a buffer. This returns io.EOF if less than 8 bytes were read. -func readUint64(reader io.Reader, b *[8]byte) (uint64, error) { - s := b[0:8] - n, err := reader.Read(s) - if err != nil { - return 0, err - } else if n < 8 { // more strict than reader.Read - return 0, io.EOF - } - - // Read the u64 from the underlying buffer. - ret := binary.LittleEndian.Uint64(s) - - // Clear the underlying array. - for i := 0; i < 8; i++ { - b[i] = 0 - } - return ret, nil -} diff --git a/internal/engine/compiler/engine_cache_test.go b/internal/engine/compiler/engine_cache_test.go deleted file mode 100644 index 612da0ca61..0000000000 --- a/internal/engine/compiler/engine_cache_test.go +++ /dev/null @@ -1,602 +0,0 @@ -package compiler - -import ( - "bytes" - "crypto/sha256" - "encoding/binary" - "errors" - "hash/crc32" - "io" - "math" - "testing" - "testing/iotest" - - "github.com/tetratelabs/wazero/internal/asm" - "github.com/tetratelabs/wazero/internal/filecache" - "github.com/tetratelabs/wazero/internal/testing/require" - "github.com/tetratelabs/wazero/internal/u32" - "github.com/tetratelabs/wazero/internal/u64" - "github.com/tetratelabs/wazero/internal/wasm" -) - -var testVersion = "" - -func crcf(b []byte) []byte { - c := crc32.Checksum(b, crc) - return u32.LeBytes(c) -} - -func concat(ins ...[]byte) (ret []byte) { - for _, in := range ins { - ret = append(ret, in...) - } - return -} - -func makeCodeSegment(bytes ...byte) asm.CodeSegment { - return *asm.NewCodeSegment(bytes) -} - -func TestSerializeCompiledModule(t *testing.T) { - tests := []struct { - in *compiledModule - exp []byte - }{ - { - in: &compiledModule{ - compiledCode: &compiledCode{ - executable: makeCodeSegment(1, 2, 3, 4, 5), - }, - functions: []compiledFunction{ - {executableOffset: 0, stackPointerCeil: 12345}, - }, - }, - exp: concat( - []byte(wazeroMagic), - []byte{byte(len(testVersion))}, - []byte(testVersion), - []byte{0}, // ensure termination. - u32.LeBytes(1), // number of functions. - u64.LeBytes(12345), // stack pointer ceil. - u64.LeBytes(0), // offset. - u64.LeBytes(5), // length of code. - []byte{1, 2, 3, 4, 5}, // code. - crcf([]byte{1, 2, 3, 4, 5}), // crc of code. - ), - }, - { - in: &compiledModule{ - compiledCode: &compiledCode{ - executable: makeCodeSegment(1, 2, 3, 4, 5), - }, - functions: []compiledFunction{ - {executableOffset: 0, stackPointerCeil: 12345}, - }, - ensureTermination: true, - }, - exp: concat( - []byte(wazeroMagic), - []byte{byte(len(testVersion))}, - []byte(testVersion), - []byte{1}, // ensure termination. - u32.LeBytes(1), // number of functions. - u64.LeBytes(12345), // stack pointer ceil. - u64.LeBytes(0), // offset. - u64.LeBytes(5), // length of code. - []byte{1, 2, 3, 4, 5}, // code. - crcf([]byte{1, 2, 3, 4, 5}), // crc of code. - ), - }, - { - in: &compiledModule{ - compiledCode: &compiledCode{ - executable: makeCodeSegment(1, 2, 3, 4, 5, 1, 2, 3), - }, - functions: []compiledFunction{ - {executableOffset: 0, stackPointerCeil: 12345}, - {executableOffset: 5, stackPointerCeil: 0xffffffff}, - }, - ensureTermination: true, - }, - exp: concat( - []byte(wazeroMagic), - []byte{byte(len(testVersion))}, - []byte(testVersion), - []byte{1}, // ensure termination. - u32.LeBytes(2), // number of functions. - // Function index = 0. - u64.LeBytes(12345), // stack pointer ceil. - u64.LeBytes(0), // offset. - // Function index = 1. - u64.LeBytes(0xffffffff), // stack pointer ceil. - u64.LeBytes(5), // offset. - // Executable. - u64.LeBytes(8), // length of code. - []byte{1, 2, 3, 4, 5, 1, 2, 3}, // code. - crcf([]byte{1, 2, 3, 4, 5, 1, 2, 3}), // crc of code. - ), - }, - } - - for i, tc := range tests { - actual, err := io.ReadAll(serializeCompiledModule(testVersion, tc.in)) - require.NoError(t, err, i) - require.Equal(t, tc.exp, actual, i) - } -} - -func TestDeserializeCompiledModule(t *testing.T) { - tests := []struct { - name string - in []byte - importedFunctionCount uint32 - expCompiledModule *compiledModule - expStaleCache bool - expErr string - }{ - { - name: "invalid header", - in: []byte{1}, - expErr: "compilationcache: invalid header length: 1", - }, - { - name: "version mismatch", - in: concat( - []byte(wazeroMagic), - []byte{byte(len("1233123.1.1"))}, - []byte("1233123.1.1"), - u32.LeBytes(1), // number of functions. - ), - expStaleCache: true, - }, - { - name: "version mismatch", - in: concat( - []byte(wazeroMagic), - []byte{byte(len("1"))}, - []byte("1"), - u32.LeBytes(1), // number of functions. - ), - expStaleCache: true, - }, - { - name: "invalid crc", - in: concat( - []byte(wazeroMagic), - []byte{byte(len(testVersion))}, - []byte(testVersion), - []byte{0}, // ensure termination. - u32.LeBytes(1), // number of functions. - u64.LeBytes(12345), // stack pointer ceil. - u64.LeBytes(0), // offset. - // Executable. - u64.LeBytes(5), // size. - []byte{1, 2, 3, 4, 5}, // machine code. - crcf([]byte{1, 2, 3, 4}), // crc of code. - ), - expStaleCache: false, - expErr: "compilationcache: checksum mismatch (expected 1397854123, got 691047668)", - }, - { - name: "missing crc", - in: concat( - []byte(wazeroMagic), - []byte{byte(len(testVersion))}, - []byte(testVersion), - []byte{0}, // ensure termination. - u32.LeBytes(1), // number of functions. - u64.LeBytes(12345), // stack pointer ceil. - u64.LeBytes(0), // offset. - // Executable. - u64.LeBytes(5), // size. - []byte{1, 2, 3, 4, 5}, // machine code. - ), - expStaleCache: false, - expErr: "compilationcache: could not read checksum: EOF", - }, - { - name: "one function", - in: concat( - []byte(wazeroMagic), - []byte{byte(len(testVersion))}, - []byte(testVersion), - []byte{0}, // ensure termination. - u32.LeBytes(1), // number of functions. - u64.LeBytes(12345), // stack pointer ceil. - u64.LeBytes(0), // offset. - // Executable. - u64.LeBytes(5), // size. - []byte{1, 2, 3, 4, 5}, // machine code. - crcf([]byte{1, 2, 3, 4, 5}), // crc of code. - ), - expCompiledModule: &compiledModule{ - compiledCode: &compiledCode{ - executable: makeCodeSegment(1, 2, 3, 4, 5), - }, - functions: []compiledFunction{ - {executableOffset: 0, stackPointerCeil: 12345, index: 0}, - }, - }, - expStaleCache: false, - expErr: "", - }, - { - name: "one function with ensure termination", - in: concat( - []byte(wazeroMagic), - []byte{byte(len(testVersion))}, - []byte(testVersion), - []byte{1}, // ensure termination. - u32.LeBytes(1), // number of functions. - u64.LeBytes(12345), // stack pointer ceil. - u64.LeBytes(0), // offset. - u64.LeBytes(5), // length of code. - []byte{1, 2, 3, 4, 5}, // code. - crcf([]byte{1, 2, 3, 4, 5}), // crc of code. - ), - expCompiledModule: &compiledModule{ - compiledCode: &compiledCode{ - executable: makeCodeSegment(1, 2, 3, 4, 5), - }, - functions: []compiledFunction{{executableOffset: 0, stackPointerCeil: 12345, index: 0}}, - ensureTermination: true, - }, - expStaleCache: false, - expErr: "", - }, - { - name: "two functions", - in: concat( - []byte(wazeroMagic), - []byte{byte(len(testVersion))}, - []byte(testVersion), - []byte{0}, // ensure termination. - u32.LeBytes(2), // number of functions. - // Function index = 0. - u64.LeBytes(12345), // stack pointer ceil. - u64.LeBytes(0), // offset. - // Function index = 1. - u64.LeBytes(0xffffffff), // stack pointer ceil. - u64.LeBytes(7), // offset. - // Executable. - u64.LeBytes(10), // size. - []byte{1, 2, 3, 4, 5, 6, 7, 8, 9, 10}, // machine code. - crcf([]byte{1, 2, 3, 4, 5, 6, 7, 8, 9, 10}), // crc of code. - ), - importedFunctionCount: 1, - expCompiledModule: &compiledModule{ - compiledCode: &compiledCode{ - executable: makeCodeSegment(1, 2, 3, 4, 5, 6, 7, 8, 9, 10), - }, - functions: []compiledFunction{ - {executableOffset: 0, stackPointerCeil: 12345, index: 1}, - {executableOffset: 7, stackPointerCeil: 0xffffffff, index: 2}, - }, - }, - expStaleCache: false, - expErr: "", - }, - { - name: "reading stack pointer", - in: concat( - []byte(wazeroMagic), - []byte{byte(len(testVersion))}, - []byte(testVersion), - []byte{0}, // ensure termination. - u32.LeBytes(2), // number of functions. - // Function index = 0. - u64.LeBytes(12345), // stack pointer ceil. - u64.LeBytes(5), // offset. - // Function index = 1. - ), - expErr: "compilationcache: error reading func[1] stack pointer ceil: EOF", - }, - { - name: "reading executable offset", - in: concat( - []byte(wazeroMagic), - []byte{byte(len(testVersion))}, - []byte(testVersion), - []byte{0}, // ensure termination. - u32.LeBytes(2), // number of functions. - // Function index = 0. - u64.LeBytes(12345), // stack pointer ceil. - u64.LeBytes(5), // offset. - // Function index = 1. - u64.LeBytes(12345), // stack pointer ceil. - ), - expErr: "compilationcache: error reading func[1] executable offset: EOF", - }, - { - name: "mmapping", - in: concat( - []byte(wazeroMagic), - []byte{byte(len(testVersion))}, - []byte(testVersion), - []byte{0}, // ensure termination. - u32.LeBytes(2), // number of functions. - // Function index = 0. - u64.LeBytes(12345), // stack pointer ceil. - u64.LeBytes(0), // offset. - // Function index = 1. - u64.LeBytes(12345), // stack pointer ceil. - u64.LeBytes(5), // offset. - // Executable. - u64.LeBytes(5), // size of the executable. - // Lack of machine code here. - ), - expErr: "compilationcache: error reading executable (len=5): EOF", - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - cm, staleCache, err := deserializeCompiledModule(testVersion, io.NopCloser(bytes.NewReader(tc.in)), - &wasm.Module{ImportFunctionCount: tc.importedFunctionCount}) - - if tc.expCompiledModule != nil { - require.Equal(t, len(tc.expCompiledModule.functions), len(cm.functions)) - for i := 0; i < len(cm.functions); i++ { - require.Equal(t, cm.compiledCode, cm.functions[i].parent) - tc.expCompiledModule.functions[i].parent = cm.compiledCode - } - } - - if tc.expErr != "" { - require.EqualError(t, err, tc.expErr) - } else { - require.NoError(t, err) - require.Equal(t, tc.expCompiledModule, cm) - } - - require.Equal(t, tc.expStaleCache, staleCache) - }) - } -} - -func TestEngine_getCompiledModuleFromCache(t *testing.T) { - valid := concat( - []byte(wazeroMagic), - []byte{byte(len(testVersion))}, - []byte(testVersion), - []byte{0}, // ensure termination. - u32.LeBytes(2), // number of functions. - // Function index = 0. - u64.LeBytes(12345), // stack pointer ceil. - u64.LeBytes(0), // offset. - // Function index = 1. - u64.LeBytes(0xffffffff), // stack pointer ceil. - u64.LeBytes(5), // offset. - // executables. - u64.LeBytes(10), // length of code. - []byte{1, 2, 3, 4, 5, 6, 7, 8, 9, 10}, // code. - crcf([]byte{1, 2, 3, 4, 5, 6, 7, 8, 9, 10}), // code. - ) - - tests := []struct { - name string - ext map[wasm.ModuleID][]byte - key wasm.ModuleID - isHostMod bool - expCompiledModule *compiledModule - expHit bool - expErr string - expDeleted bool - }{ - {name: "extern cache not given"}, - { - name: "not hit", - ext: map[wasm.ModuleID][]byte{}, - }, - { - name: "host module", - ext: map[wasm.ModuleID][]byte{{}: valid}, - isHostMod: true, - }, - { - name: "error in Cache.Get", - ext: map[wasm.ModuleID][]byte{{}: {}}, - expErr: "compilationcache: error reading header: EOF", - }, - { - name: "error in deserialization", - ext: map[wasm.ModuleID][]byte{{}: {1, 2, 3}}, - expErr: "compilationcache: invalid header length: 3", - }, - { - name: "stale cache", - ext: map[wasm.ModuleID][]byte{{}: concat( - []byte(wazeroMagic), - []byte{byte(len("1233123.1.1"))}, - []byte("1233123.1.1"), - u32.LeBytes(1), // number of functions. - )}, - expDeleted: true, - }, - { - name: "hit", - ext: map[wasm.ModuleID][]byte{ - {}: valid, - }, - expHit: true, - expCompiledModule: &compiledModule{ - compiledCode: &compiledCode{ - executable: makeCodeSegment(1, 2, 3, 4, 5, 6, 7, 8, 9, 10), - }, - functions: []compiledFunction{ - {stackPointerCeil: 12345, executableOffset: 0, index: 0}, - {stackPointerCeil: 0xffffffff, executableOffset: 5, index: 1}, - }, - }, - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - m := &wasm.Module{ID: tc.key, IsHostModule: tc.isHostMod} - if exp := tc.expCompiledModule; exp != nil { - exp.source = m - for i := range tc.expCompiledModule.functions { - tc.expCompiledModule.functions[i].parent = exp.compiledCode - } - } - - e := engine{} - if tc.ext != nil { - tmp := t.TempDir() - e.fileCache = filecache.New(tmp) - for key, value := range tc.ext { - err := e.fileCache.Add(key, bytes.NewReader(value)) - require.NoError(t, err) - } - } - - codes, hit, err := e.getCompiledModuleFromCache(m) - if tc.expErr != "" { - require.EqualError(t, err, tc.expErr) - } else { - require.NoError(t, err) - } - - require.Equal(t, tc.expHit, hit) - require.Equal(t, tc.expCompiledModule, codes) - - if tc.ext != nil && tc.expDeleted { - _, hit, err := e.fileCache.Get(tc.key) - require.NoError(t, err) - require.False(t, hit) - } - }) - } -} - -func TestEngine_addCompiledModuleToCache(t *testing.T) { - t.Run("not defined", func(t *testing.T) { - e := engine{} - err := e.addCompiledModuleToCache(nil, nil) - require.NoError(t, err) - }) - t.Run("host module", func(t *testing.T) { - tc := filecache.New(t.TempDir()) - e := engine{fileCache: tc} - cm := &compiledModule{ - compiledCode: &compiledCode{ - executable: makeCodeSegment(1, 2, 3), - }, - functions: []compiledFunction{{stackPointerCeil: 123}}, - } - m := &wasm.Module{ID: sha256.Sum256(nil), IsHostModule: true} // Host module! - err := e.addCompiledModuleToCache(m, cm) - require.NoError(t, err) - // Check the host module not cached. - _, hit, err := tc.Get(m.ID) - require.NoError(t, err) - require.False(t, hit) - }) - t.Run("add", func(t *testing.T) { - tc := filecache.New(t.TempDir()) - e := engine{fileCache: tc} - m := &wasm.Module{} - cm := &compiledModule{ - compiledCode: &compiledCode{ - executable: makeCodeSegment(1, 2, 3), - }, - functions: []compiledFunction{{stackPointerCeil: 123}}, - } - err := e.addCompiledModuleToCache(m, cm) - require.NoError(t, err) - - content, ok, err := tc.Get(m.ID) - require.NoError(t, err) - require.True(t, ok) - actual, err := io.ReadAll(content) - require.NoError(t, err) - require.Equal(t, concat( - []byte(wazeroMagic), - []byte{byte(len(testVersion))}, - []byte(testVersion), - []byte{0}, - u32.LeBytes(1), // number of functions. - u64.LeBytes(123), // stack pointer ceil. - u64.LeBytes(0), // offset. - u64.LeBytes(3), // size of executable. - []byte{1, 2, 3}, - crcf([]byte{1, 2, 3}), // code. - ), actual) - require.NoError(t, content.Close()) - }) -} - -func Test_readUint64(t *testing.T) { - tests := []struct { - name string - input uint64 - }{ - { - name: "zero", - input: 0, - }, - { - name: "half", - input: math.MaxUint32, - }, - { - name: "max", - input: math.MaxUint64, - }, - } - - for _, tt := range tests { - tc := tt - - t.Run(tc.name, func(t *testing.T) { - input := make([]byte, 8) - binary.LittleEndian.PutUint64(input, tc.input) - - var b [8]byte - n, err := readUint64(bytes.NewReader(input), &b) - require.NoError(t, err) - require.Equal(t, tc.input, n) - - // ensure the buffer was cleared - var expectedB [8]byte - require.Equal(t, expectedB, b) - }) - } -} - -func Test_readUint64_errors(t *testing.T) { - tests := []struct { - name string - input io.Reader - expectedErr string - }{ - { - name: "zero", - input: bytes.NewReader([]byte{}), - expectedErr: "EOF", - }, - { - name: "not enough", - input: bytes.NewReader([]byte{1, 2}), - expectedErr: "EOF", - }, - { - name: "error reading", - input: iotest.ErrReader(errors.New("ice cream")), - expectedErr: "ice cream", - }, - } - - for _, tt := range tests { - tc := tt - - t.Run(tc.name, func(t *testing.T) { - var b [8]byte - _, err := readUint64(tc.input, &b) - require.EqualError(t, err, tc.expectedErr) - }) - } -} diff --git a/internal/engine/compiler/engine_test.go b/internal/engine/compiler/engine_test.go deleted file mode 100644 index c68a05865f..0000000000 --- a/internal/engine/compiler/engine_test.go +++ /dev/null @@ -1,593 +0,0 @@ -package compiler - -import ( - "context" - "errors" - "fmt" - "runtime" - "testing" - "unsafe" - - "github.com/tetratelabs/wazero/api" - "github.com/tetratelabs/wazero/experimental" - "github.com/tetratelabs/wazero/internal/bitpack" - "github.com/tetratelabs/wazero/internal/platform" - "github.com/tetratelabs/wazero/internal/testing/require" - "github.com/tetratelabs/wazero/internal/wasm" -) - -// testCtx is an arbitrary, non-default context. Non-nil also prevents linter errors. -var testCtx = context.WithValue(context.Background(), struct{}{}, "arbitrary") - -// requireSupportedOSArch is duplicated also in the platform package to ensure no cyclic dependency. -func requireSupportedOSArch(t *testing.T) { - if !platform.CompilerSupported() { - t.Skip() - } -} - -type fakeFinalizer map[*compiledModule]func(module *compiledModule) - -func (f fakeFinalizer) setFinalizer(obj interface{}, finalizer interface{}) { - cf := obj.(*compiledModule) - if _, ok := f[cf]; ok { // easier than adding a field for testing.T - panic(fmt.Sprintf("BUG: %v already had its finalizer set", cf)) - } - f[cf] = finalizer.(func(*compiledModule)) -} - -func TestCompiler_CompileModule(t *testing.T) { - t.Run("ok", func(t *testing.T) { - e := NewEngine(testCtx, api.CoreFeaturesV1, nil).(*engine) - ff := fakeFinalizer{} - e.setFinalizer = ff.setFinalizer - - okModule := &wasm.Module{ - TypeSection: []wasm.FunctionType{{}}, - FunctionSection: []wasm.Index{0, 0, 0, 0}, - CodeSection: []wasm.Code{ - {Body: []byte{wasm.OpcodeEnd}}, - {Body: []byte{wasm.OpcodeEnd}}, - {Body: []byte{wasm.OpcodeEnd}}, - {Body: []byte{wasm.OpcodeEnd}}, - }, - ID: wasm.ModuleID{}, - } - - err := e.CompileModule(testCtx, okModule, nil, false) - require.NoError(t, err) - - // Compiling same module shouldn't be compiled again, but instead should be cached. - err = e.CompileModule(testCtx, okModule, nil, false) - require.NoError(t, err) - - compiled, ok := e.codes[okModule.ID] - require.True(t, ok) - require.Equal(t, len(okModule.FunctionSection), len(compiled.functions)) - - // Pretend the finalizer executed, by invoking them one-by-one. - for k, v := range ff { - v(k) - } - }) - - t.Run("fail", func(t *testing.T) { - errModule := &wasm.Module{ - TypeSection: []wasm.FunctionType{{}}, - FunctionSection: []wasm.Index{0, 0, 0}, - CodeSection: []wasm.Code{ - {Body: []byte{wasm.OpcodeEnd}}, - {Body: []byte{wasm.OpcodeEnd}}, - {Body: []byte{wasm.OpcodeCall}}, // Call instruction without immediate for call target index is invalid and should fail to compile. - }, - ID: wasm.ModuleID{}, - } - - e := NewEngine(testCtx, api.CoreFeaturesV1, nil).(*engine) - err := e.CompileModule(testCtx, errModule, nil, false) - require.EqualError(t, err, "failed to lower func[2]: handling instruction: apply stack failed for call: reading immediates: EOF") - - // On the compilation failure, the compiled functions must not be cached. - _, ok := e.codes[errModule.ID] - require.False(t, ok) - }) -} - -func TestCompiler_Releasecode_Panic(t *testing.T) { - captured := require.CapturePanic(func() { - releaseCompiledModule(&compiledModule{ - compiledCode: &compiledCode{ - executable: makeCodeSegment(1, 2), - }, - }) - }) - require.Contains(t, captured.Error(), "compiler: failed to munmap code segment") -} - -// Ensures that value stack and call-frame stack are allocated on heap which -// allows us to safely access to their data region from native code. -// See comments on initialStackSize and initialCallFrameStackSize. -func TestCompiler_SliceAllocatedOnHeap(t *testing.T) { - enabledFeatures := api.CoreFeaturesV1 - e := newEngine(enabledFeatures, nil) - s := wasm.NewStore(enabledFeatures, e) - - const hostModuleName = "env" - const hostFnName = "grow_and_shrink_goroutine_stack" - hostFn := func() { - // This function aggressively grow the goroutine stack by recursively - // calling the function many times. - callNum := 1000 - var growGoroutineStack func() - growGoroutineStack = func() { - if callNum != 0 { - callNum-- - growGoroutineStack() - } - } - growGoroutineStack() - - // Trigger relocation of goroutine stack because at this point we have the majority of - // goroutine stack unused after recursive call. - runtime.GC() - } - hm, err := wasm.NewHostModule( - hostModuleName, - []string{hostFnName}, - map[string]*wasm.HostFunc{hostFnName: {ExportName: hostFnName, Code: wasm.Code{GoFunc: hostFn}}}, - enabledFeatures, - ) - require.NoError(t, err) - - err = s.Engine.CompileModule(testCtx, hm, nil, false) - require.NoError(t, err) - - typeIDs, err := s.GetFunctionTypeIDs(hm.TypeSection) - require.NoError(t, err) - - _, err = s.Instantiate(testCtx, hm, hostModuleName, nil, typeIDs) - require.NoError(t, err) - - const stackCorruption = "value_stack_corruption" - const callStackCorruption = "call_stack_corruption" - const expectedReturnValue = 0x1 - m := &wasm.Module{ - ImportFunctionCount: 1, - TypeSection: []wasm.FunctionType{ - {Params: []wasm.ValueType{}, Results: []wasm.ValueType{wasm.ValueTypeI32}, ResultNumInUint64: 1}, - {Params: []wasm.ValueType{}, Results: []wasm.ValueType{}}, - }, - FunctionSection: []wasm.Index{ - wasm.Index(0), - wasm.Index(0), - wasm.Index(0), - }, - CodeSection: []wasm.Code{ - { - // value_stack_corruption - Body: []byte{ - wasm.OpcodeCall, 0, // Call host function to shrink Goroutine stack - // We expect this value is returned, but if the stack is allocated on - // goroutine stack, we write this expected value into the old-location of - // stack. - wasm.OpcodeI32Const, expectedReturnValue, - wasm.OpcodeEnd, - }, - }, - { - // call_stack_corruption - Body: []byte{ - wasm.OpcodeCall, 3, // Call the wasm function below. - // At this point, call stack's memory looks like [call_stack_corruption, index3] - // With this function call it should end up [call_stack_corruption, host func] - // but if the call-frame stack is allocated on goroutine stack, we exit the native code - // with [call_stack_corruption, index3] (old call frame stack) with HostCall status code, - // and end up trying to call index3 as a host function which results in nil pointer exception. - wasm.OpcodeCall, 0, - wasm.OpcodeI32Const, expectedReturnValue, - wasm.OpcodeEnd, - }, - }, - {Body: []byte{wasm.OpcodeCall, 0, wasm.OpcodeEnd}}, - }, - ImportSection: []wasm.Import{{Module: hostModuleName, Name: hostFnName, DescFunc: 1}}, - ImportPerModule: map[string][]*wasm.Import{ - hostModuleName: {{Module: hostModuleName, Name: hostFnName, DescFunc: 1}}, - }, - ExportSection: []wasm.Export{ - {Type: wasm.ExternTypeFunc, Index: 1, Name: stackCorruption}, - {Type: wasm.ExternTypeFunc, Index: 2, Name: callStackCorruption}, - }, - Exports: map[string]*wasm.Export{ - stackCorruption: {Type: wasm.ExternTypeFunc, Index: 1, Name: stackCorruption}, - callStackCorruption: {Type: wasm.ExternTypeFunc, Index: 2, Name: callStackCorruption}, - }, - ID: wasm.ModuleID{1}, - } - - err = s.Engine.CompileModule(testCtx, m, nil, false) - require.NoError(t, err) - - typeIDs, err = s.GetFunctionTypeIDs(m.TypeSection) - require.NoError(t, err) - - mi, err := s.Instantiate(testCtx, m, t.Name(), nil, typeIDs) - require.NoError(t, err) - - for _, fnName := range []string{stackCorruption, callStackCorruption} { - fnName := fnName - t.Run(fnName, func(t *testing.T) { - ret, err := mi.ExportedFunction(fnName).Call(testCtx) - require.NoError(t, err) - - require.Equal(t, uint32(expectedReturnValue), uint32(ret[0])) - }) - } -} - -func TestCallEngine_builtinFunctionTableGrow(t *testing.T) { - ce := &callEngine{ - stack: []uint64{ - 0xff, // pseudo-ref - 1, // num - // Table Index = 0 (lower 32-bits), but the higher bits (32-63) are all sets, - // which happens if the previous value on that stack location was 64-bit wide. - 0xffffffff << 32, - }, - stackContext: stackContext{stackPointer: 3}, - } - - table := &wasm.TableInstance{References: []wasm.Reference{}, Min: 10} - ce.builtinFunctionTableGrow([]*wasm.TableInstance{table}) - - require.Equal(t, 1, len(table.References)) - require.Equal(t, uintptr(0xff), table.References[0]) -} - -func ptrAsUint64(f *function) uint64 { - return uint64(uintptr(unsafe.Pointer(f))) -} - -func TestCallEngine_deferredOnCall(t *testing.T) { - s := &wasm.Module{ - FunctionSection: []wasm.Index{0, 1, 2}, - CodeSection: []wasm.Code{{}, {}, {}}, - TypeSection: []wasm.FunctionType{{}, {}, {}}, - } - f1 := &function{ - funcType: &wasm.FunctionType{ParamNumInUint64: 2}, - parent: &compiledFunction{parent: &compiledCode{source: s}, index: 0}, - } - f2 := &function{ - funcType: &wasm.FunctionType{ParamNumInUint64: 2, ResultNumInUint64: 3}, - parent: &compiledFunction{parent: &compiledCode{source: s}, index: 1}, - } - f3 := &function{ - funcType: &wasm.FunctionType{ResultNumInUint64: 1}, - parent: &compiledFunction{parent: &compiledCode{source: s}, index: 2}, - } - - ce := &callEngine{ - stack: []uint64{ - 0xff, 0xff, // dummy argument for f1 - 0, 0, 0, 0, - 0xcc, 0xcc, // local variable for f1. - // <----- stack base point of f2 (top) == index 8. - 0xaa, 0xaa, 0xdeadbeaf, // dummy argument for f2 (0xaa, 0xaa) and the reserved slot for result 0xdeadbeaf) - 0, 0, ptrAsUint64(f1), 0, // callFrame - 0xcc, 0xcc, 0xcc, // local variable for f2. - // <----- stack base point of f3 (top) == index 18 - 0xdeadbeaf, // the reserved slot for result 0xdeadbeaf) from f3. - 0, 8 << 3, ptrAsUint64(f2), 0, // callFrame - }, - stackContext: stackContext{ - stackBasePointerInBytes: 18 << 3, // currently executed function (f3)'s base pointer. - stackPointer: 0xff, // dummy supposed to be reset to zero. - }, - moduleContext: moduleContext{ - fn: f3, // currently executed function (f3)! - moduleInstance: nil, - }, - } - - beforeRecoverStack := ce.stack - - err := ce.deferredOnCall(context.Background(), &wasm.ModuleInstance{}, errors.New("some error")) - require.EqualError(t, err, `some error (recovered by wazero) -wasm stack trace: - .$2() - .$1() - .$0()`) - - // After recover, the state of callEngine must be reset except that the underlying slices must be intact - // for the subsequent calls to avoid additional allocations on each call. - require.Equal(t, uint64(0), ce.stackBasePointerInBytes) - require.Equal(t, uint64(0), ce.stackPointer) - require.Equal(t, nil, ce.moduleInstance) - require.Equal(t, beforeRecoverStack, ce.stack) - - // Keep f1, f2, and f3 alive until we reach here, as we access these functions from the uint64 raw pointers in the stack. - // In practice, they are guaranteed to be alive as they are held by moduleContext. - runtime.KeepAlive(f1) - runtime.KeepAlive(f2) - runtime.KeepAlive(f3) -} - -func TestCallEngine_initializeStack(t *testing.T) { - const i32 = wasm.ValueTypeI32 - const stackSize = 10 - const initialVal = ^uint64(0) - tests := []struct { - name string - funcType *wasm.FunctionType - args []uint64 - expStackPointer uint64 - expStack [stackSize]uint64 - }{ - { - name: "no param/result", - funcType: &wasm.FunctionType{}, - expStackPointer: callFrameDataSizeInUint64, - expStack: [stackSize]uint64{ - 0, 0, 0, // zeroed call frame - initialVal, initialVal, initialVal, initialVal, initialVal, initialVal, initialVal, - }, - }, - { - name: "no result", - funcType: &wasm.FunctionType{ - Params: []wasm.ValueType{i32, i32}, - ParamNumInUint64: 2, - }, - args: []uint64{0xdeadbeaf, 0xdeadbeaf}, - expStackPointer: callFrameDataSizeInUint64 + 2, - expStack: [stackSize]uint64{ - 0xdeadbeaf, 0xdeadbeaf, // arguments - 0, 0, 0, // zeroed call frame - initialVal, initialVal, initialVal, initialVal, initialVal, - }, - }, - { - name: "no param", - funcType: &wasm.FunctionType{ - Results: []wasm.ValueType{i32, i32, i32}, - ResultNumInUint64: 3, - }, - expStackPointer: callFrameDataSizeInUint64 + 3, - expStack: [stackSize]uint64{ - initialVal, initialVal, initialVal, // reserved slots for results - 0, 0, 0, // zeroed call frame - initialVal, initialVal, initialVal, initialVal, - }, - }, - { - name: "params > results", - funcType: &wasm.FunctionType{ - Params: []wasm.ValueType{i32, i32, i32, i32, i32}, - ParamNumInUint64: 5, - Results: []wasm.ValueType{i32, i32, i32}, - ResultNumInUint64: 3, - }, - args: []uint64{0xdeafbeaf, 0xdeafbeaf, 0xdeafbeaf, 0xdeafbeaf, 0xdeafbeaf}, - expStackPointer: callFrameDataSizeInUint64 + 5, - expStack: [stackSize]uint64{ - 0xdeafbeaf, 0xdeafbeaf, 0xdeafbeaf, 0xdeafbeaf, 0xdeafbeaf, - 0, 0, 0, // zeroed call frame - initialVal, initialVal, - }, - }, - { - name: "params == results", - funcType: &wasm.FunctionType{ - Params: []wasm.ValueType{i32, i32, i32, i32, i32}, - ParamNumInUint64: 5, - Results: []wasm.ValueType{i32, i32, i32, i32, i32}, - ResultNumInUint64: 5, - }, - args: []uint64{0xdeafbeaf, 0xdeafbeaf, 0xdeafbeaf, 0xdeafbeaf, 0xdeafbeaf}, - expStackPointer: callFrameDataSizeInUint64 + 5, - expStack: [stackSize]uint64{ - 0xdeafbeaf, 0xdeafbeaf, 0xdeafbeaf, 0xdeafbeaf, 0xdeafbeaf, - 0, 0, 0, // zeroed call frame - initialVal, initialVal, - }, - }, - { - name: "params < results", - funcType: &wasm.FunctionType{ - Params: []wasm.ValueType{i32, i32, i32}, - ParamNumInUint64: 3, - Results: []wasm.ValueType{i32, i32, i32, i32, i32}, - ResultNumInUint64: 5, - }, - args: []uint64{0xdeafbeaf, 0xdeafbeaf, 0xdeafbeaf}, - expStackPointer: callFrameDataSizeInUint64 + 5, - expStack: [stackSize]uint64{ - 0xdeafbeaf, 0xdeafbeaf, 0xdeafbeaf, - initialVal, initialVal, // reserved for results - 0, 0, 0, // zeroed call frame - initialVal, initialVal, - }, - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - initialStack := make([]uint64, stackSize) - for i := range initialStack { - initialStack[i] = initialVal - } - ce := &callEngine{stack: initialStack} - ce.initializeStack(tc.funcType, tc.args) - require.Equal(t, tc.expStackPointer, ce.stackPointer) - require.Equal(t, tc.expStack[:], ce.stack) - }) - } -} - -func Test_callFrameOffset(t *testing.T) { - require.Equal(t, 1, callFrameOffset(&wasm.FunctionType{ParamNumInUint64: 0, ResultNumInUint64: 1})) - require.Equal(t, 10, callFrameOffset(&wasm.FunctionType{ParamNumInUint64: 5, ResultNumInUint64: 10})) - require.Equal(t, 100, callFrameOffset(&wasm.FunctionType{ParamNumInUint64: 50, ResultNumInUint64: 100})) - require.Equal(t, 1, callFrameOffset(&wasm.FunctionType{ParamNumInUint64: 1, ResultNumInUint64: 0})) - require.Equal(t, 10, callFrameOffset(&wasm.FunctionType{ParamNumInUint64: 10, ResultNumInUint64: 5})) - require.Equal(t, 100, callFrameOffset(&wasm.FunctionType{ParamNumInUint64: 100, ResultNumInUint64: 50})) -} - -type stackEntry struct { - def api.FunctionDefinition -} - -func assertStackIterator(t *testing.T, it experimental.StackIterator, expected []stackEntry) { - var actual []stackEntry - for it.Next() { - actual = append(actual, stackEntry{def: it.Function().Definition()}) - } - require.Equal(t, expected, actual) -} - -func TestCallEngine_builtinFunctionFunctionListenerBefore(t *testing.T) { - currentContext := context.Background() - - f := &function{ - funcType: &wasm.FunctionType{ParamNumInUint64: 3}, - parent: &compiledFunction{ - listener: mockListener{ - before: func(ctx context.Context, _ api.Module, def api.FunctionDefinition, params []uint64, stackIterator experimental.StackIterator) { - require.Equal(t, currentContext, ctx) - require.Equal(t, []uint64{2, 3, 4}, params) - assertStackIterator(t, stackIterator, []stackEntry{{def: def}}) - }, - }, - index: 0, - parent: &compiledCode{source: &wasm.Module{ - FunctionSection: []wasm.Index{0}, - CodeSection: []wasm.Code{{}}, - TypeSection: []wasm.FunctionType{{}}, - }}, - }, - } - ce := &callEngine{ - stack: []uint64{0, 1, 2, 3, 4, 0, 0, 0}, - stackContext: stackContext{stackBasePointerInBytes: 16}, - } - ce.builtinFunctionFunctionListenerBefore(currentContext, &wasm.ModuleInstance{}, f) -} - -func TestCallEngine_builtinFunctionFunctionListenerAfter(t *testing.T) { - currentContext := context.Background() - f := &function{ - funcType: &wasm.FunctionType{ResultNumInUint64: 1}, - parent: &compiledFunction{ - listener: mockListener{ - after: func(ctx context.Context, mod api.Module, def api.FunctionDefinition, results []uint64) { - require.Equal(t, currentContext, ctx) - require.Equal(t, []uint64{5}, results) - }, - }, - index: 0, - parent: &compiledCode{source: &wasm.Module{ - FunctionSection: []wasm.Index{0}, - CodeSection: []wasm.Code{{}}, - TypeSection: []wasm.FunctionType{{}}, - }}, - }, - } - - ce := &callEngine{ - stack: []uint64{0, 1, 2, 3, 4, 5}, - stackContext: stackContext{stackBasePointerInBytes: 40}, - } - ce.builtinFunctionFunctionListenerAfter(currentContext, &wasm.ModuleInstance{}, f) -} - -type mockListener struct { - before func(context.Context, api.Module, api.FunctionDefinition, []uint64, experimental.StackIterator) - after func(context.Context, api.Module, api.FunctionDefinition, []uint64) - abort func(context.Context, api.Module, api.FunctionDefinition, error) -} - -func (m mockListener) Before(ctx context.Context, mod api.Module, def api.FunctionDefinition, params []uint64, stackIterator experimental.StackIterator) { - if m.before != nil { - m.before(ctx, mod, def, params, stackIterator) - } -} - -func (m mockListener) After(ctx context.Context, mod api.Module, def api.FunctionDefinition, results []uint64) { - if m.after != nil { - m.after(ctx, mod, def, results) - } -} - -func (m mockListener) Abort(ctx context.Context, mod api.Module, def api.FunctionDefinition, err error) { - if m.abort != nil { - m.abort(ctx, mod, def, err) - } -} - -func TestFunction_getSourceOffsetInWasmBinary(t *testing.T) { - tests := []struct { - name string - pc, exp uint64 - codeInitialAddress uintptr - srcMap sourceOffsetMap - }{ - {name: "not found", srcMap: sourceOffsetMap{}}, - { - name: "first IR", - pc: 4000, - codeInitialAddress: 3999, - srcMap: sourceOffsetMap{ - irOperationOffsetsInNativeBinary: bitpack.NewOffsetArray([]uint64{ - 0 /*4000-3999=1 exists here*/, 5, 8, 15, - }), - irOperationSourceOffsetsInWasmBinary: bitpack.NewOffsetArray([]uint64{ - 10, 100, 800, 12344, - }), - }, - exp: 10, - }, - { - name: "middle", - pc: 100, - codeInitialAddress: 90, - srcMap: sourceOffsetMap{ - irOperationOffsetsInNativeBinary: bitpack.NewOffsetArray([]uint64{ - 0, 5, 8 /*100-90=10 exists here*/, 15, - }), - irOperationSourceOffsetsInWasmBinary: bitpack.NewOffsetArray([]uint64{ - 10, 100, 800, 12344, - }), - }, - exp: 800, - }, - { - name: "last", - pc: 9999, - codeInitialAddress: 8999, - srcMap: sourceOffsetMap{ - irOperationOffsetsInNativeBinary: bitpack.NewOffsetArray([]uint64{ - 0, 5, 8, 15, /*9999-8999=1000 exists here*/ - }), - irOperationSourceOffsetsInWasmBinary: bitpack.NewOffsetArray([]uint64{ - 10, 100, 800, 12344, - }), - }, - exp: 12344, - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - f := function{ - parent: &compiledFunction{sourceOffsetMap: tc.srcMap}, - codeInitialAddress: tc.codeInitialAddress, - } - - actual := f.getSourceOffsetInWasmBinary(tc.pc) - require.Equal(t, tc.exp, actual) - }) - } -} diff --git a/internal/engine/compiler/impl_amd64.go b/internal/engine/compiler/impl_amd64.go deleted file mode 100644 index 1e91b99573..0000000000 --- a/internal/engine/compiler/impl_amd64.go +++ /dev/null @@ -1,5243 +0,0 @@ -package compiler - -// This file implements the compiler for amd64/x86_64 target. -// Please refer to https://www.felixcloutier.com/x86/index.html -// if unfamiliar with amd64 instructions used here. - -import ( - "fmt" - "math" - - "github.com/tetratelabs/wazero/internal/asm" - "github.com/tetratelabs/wazero/internal/asm/amd64" - "github.com/tetratelabs/wazero/internal/platform" - "github.com/tetratelabs/wazero/internal/u32" - "github.com/tetratelabs/wazero/internal/u64" - "github.com/tetratelabs/wazero/internal/wasm" - "github.com/tetratelabs/wazero/internal/wazeroir" -) - -var ( - _minimum32BitSignedInt int32 = math.MinInt32 - _maximum32BitSignedInt int32 = math.MaxInt32 - _maximum32BitUnsignedInt uint32 = math.MaxUint32 - _minimum64BitSignedInt int64 = math.MinInt64 - _maximum64BitSignedInt int64 = math.MaxInt64 - _maximum64BitUnsignedInt uint64 = math.MaxUint64 - _float32SignBitMask uint32 = 1 << 31 - _float32RestBitMask = ^_float32SignBitMask - _float64SignBitMask uint64 = 1 << 63 - _float64RestBitMask = ^_float64SignBitMask - _float32ForMinimumSigned32bitInteger = uint32(0xCF00_0000) - _float64ForMinimumSigned32bitInteger = uint64(0xC1E0_0000_0020_0000) - _float32ForMinimumSigned64bitInteger = uint32(0xDF00_0000) - _float64ForMinimumSigned64bitInteger = uint64(0xC3E0_0000_0000_0000) - _float32ForMaximumSigned32bitIntPlusOne = uint32(0x4F00_0000) - _float64ForMaximumSigned32bitIntPlusOne = uint64(0x41E0_0000_0000_0000) - _float32ForMaximumSigned64bitIntPlusOne = uint32(0x5F00_0000) - _float64ForMaximumSigned64bitIntPlusOne = uint64(0x43E0_0000_0000_0000) -) - -var ( - // amd64ReservedRegisterForCallEngine: pointer to callEngine (i.e. *callEngine as uintptr) - amd64ReservedRegisterForCallEngine = amd64.RegR13 - // amd64ReservedRegisterForStackBasePointerAddress: stack base pointer's address (callEngine.stackBasePointer) in the current function call. - amd64ReservedRegisterForStackBasePointerAddress = amd64.RegR14 - // amd64ReservedRegisterForMemory: pointer to the memory slice's data (i.e. &memory.Buffer[0] as uintptr). - amd64ReservedRegisterForMemory = amd64.RegR15 -) - -var ( - amd64UnreservedVectorRegisters = []asm.Register{ //nolint - amd64.RegX0, amd64.RegX1, amd64.RegX2, amd64.RegX3, - amd64.RegX4, amd64.RegX5, amd64.RegX6, amd64.RegX7, - amd64.RegX8, amd64.RegX9, amd64.RegX10, amd64.RegX11, - amd64.RegX12, amd64.RegX13, amd64.RegX14, amd64.RegX15, - } - // Note that we never invoke "call" instruction, - // so we don't need to care about the calling convention. - // TODO: Maybe it is safe just save rbp, rsp somewhere - // in Go-allocated variables, and reuse these registers - // in compiled functions and write them back before returns. - amd64UnreservedGeneralPurposeRegisters = []asm.Register{ //nolint - amd64.RegAX, amd64.RegCX, amd64.RegDX, amd64.RegBX, - amd64.RegSI, amd64.RegDI, amd64.RegR8, amd64.RegR9, - amd64.RegR10, amd64.RegR11, amd64.RegR12, - } -) - -// amd64CallingConventionDestinationFunctionModuleInstanceAddressRegister holds *wasm.ModuleInstance of the -// next executing function instance. The value is set and used when making function calls -// or function returns in the ModuleContextInitialization. See compileModuleContextInitialization. -var amd64CallingConventionDestinationFunctionModuleInstanceAddressRegister = amd64.RegR12 - -func (c *amd64Compiler) String() string { - return c.locationStack.String() -} - -// compileNOP implements compiler.compileNOP for the amd64 architecture. -func (c *amd64Compiler) compileNOP() asm.Node { - return c.assembler.CompileStandAlone(amd64.NOP) -} - -type amd64Compiler struct { - assembler amd64.Assembler - ir *wazeroir.CompilationResult - cpuFeatures platform.CpuFeatureFlags - // locationStack holds the state of wazeroir virtual stack. - // and each item is either placed in register or the actual memory stack. - locationStack *runtimeValueLocationStack - // labels hold per wazeroir label specific information in this function. - labels [wazeroir.LabelKindNum][]amd64LabelInfo - // stackPointerCeil is the greatest stack pointer value (from runtimeValueLocationStack) seen during compilation. - stackPointerCeil uint64 - // assignStackPointerCeilNeeded holds an asm.Node whose AssignDestinationConstant must be called with the determined stack pointer ceiling. - assignStackPointerCeilNeeded asm.Node - compiledTrapTargets [nativeCallStatusModuleClosed]asm.Node - withListener bool - typ *wasm.FunctionType - // locationStackForEntrypoint is the initial location stack for all functions. To reuse the allocated stack, - // we cache it here, and reset and set to .locationStack in the Init method. - locationStackForEntrypoint runtimeValueLocationStack - // frameIDMax tracks the maximum value of frame id per function. - frameIDMax int - brTableTmp []runtimeValueLocation - - fourZeros, - eightZeros, - minimum32BitSignedInt, - maximum32BitSignedInt, - maximum32BitUnsignedInt, - minimum64BitSignedInt, - maximum64BitSignedInt, - maximum64BitUnsignedInt, - float32SignBitMask, - float32RestBitMask, - float64SignBitMask, - float64RestBitMask, - float32ForMinimumSigned32bitInteger, - float64ForMinimumSigned32bitInteger, - float32ForMinimumSigned64bitInteger, - float64ForMinimumSigned64bitInteger, - float32ForMaximumSigned32bitIntPlusOne, - float64ForMaximumSigned32bitIntPlusOne, - float32ForMaximumSigned64bitIntPlusOne, - float64ForMaximumSigned64bitIntPlusOne *asm.StaticConst -} - -func newAmd64Compiler() compiler { - c := &amd64Compiler{ - assembler: amd64.NewAssembler(), - locationStackForEntrypoint: newRuntimeValueLocationStack(), - cpuFeatures: platform.CpuFeatures, - } - - c.fourZeros = asm.NewStaticConst([]byte{0, 0, 0, 0}) - c.eightZeros = asm.NewStaticConst([]byte{0, 0, 0, 0, 0, 0, 0, 0}) - c.minimum32BitSignedInt = asm.NewStaticConst(u32.LeBytes(uint32(_minimum32BitSignedInt))) - c.maximum32BitSignedInt = asm.NewStaticConst(u32.LeBytes(uint32(_maximum32BitSignedInt))) - c.maximum32BitUnsignedInt = asm.NewStaticConst(u32.LeBytes(_maximum32BitUnsignedInt)) - c.minimum64BitSignedInt = asm.NewStaticConst(u64.LeBytes(uint64(_minimum64BitSignedInt))) - c.maximum64BitSignedInt = asm.NewStaticConst(u64.LeBytes(uint64(_maximum64BitSignedInt))) - c.maximum64BitUnsignedInt = asm.NewStaticConst(u64.LeBytes(_maximum64BitUnsignedInt)) - c.float32SignBitMask = asm.NewStaticConst(u32.LeBytes(_float32SignBitMask)) - c.float32RestBitMask = asm.NewStaticConst(u32.LeBytes(_float32RestBitMask)) - c.float64SignBitMask = asm.NewStaticConst(u64.LeBytes(_float64SignBitMask)) - c.float64RestBitMask = asm.NewStaticConst(u64.LeBytes(_float64RestBitMask)) - c.float32ForMinimumSigned32bitInteger = asm.NewStaticConst(u32.LeBytes(_float32ForMinimumSigned32bitInteger)) - c.float64ForMinimumSigned32bitInteger = asm.NewStaticConst(u64.LeBytes(_float64ForMinimumSigned32bitInteger)) - c.float32ForMinimumSigned64bitInteger = asm.NewStaticConst(u32.LeBytes(_float32ForMinimumSigned64bitInteger)) - c.float64ForMinimumSigned64bitInteger = asm.NewStaticConst(u64.LeBytes(_float64ForMinimumSigned64bitInteger)) - c.float32ForMaximumSigned32bitIntPlusOne = asm.NewStaticConst(u32.LeBytes(_float32ForMaximumSigned32bitIntPlusOne)) - c.float64ForMaximumSigned32bitIntPlusOne = asm.NewStaticConst(u64.LeBytes(_float64ForMaximumSigned32bitIntPlusOne)) - c.float32ForMaximumSigned64bitIntPlusOne = asm.NewStaticConst(u32.LeBytes(_float32ForMaximumSigned64bitIntPlusOne)) - c.float64ForMaximumSigned64bitIntPlusOne = asm.NewStaticConst(u64.LeBytes(_float64ForMaximumSigned64bitIntPlusOne)) - return c -} - -// Init implements compiler.Init. -func (c *amd64Compiler) Init(typ *wasm.FunctionType, ir *wazeroir.CompilationResult, withListener bool) { - c.assembler.Reset() - c.locationStackForEntrypoint.reset() - c.resetLabels() - *c = amd64Compiler{ - ir: ir, - withListener: withListener, - typ: typ, - assembler: c.assembler, - cpuFeatures: c.cpuFeatures, - labels: c.labels, - locationStackForEntrypoint: c.locationStackForEntrypoint, - brTableTmp: c.brTableTmp, - fourZeros: c.fourZeros, - eightZeros: c.eightZeros, - minimum32BitSignedInt: c.minimum32BitSignedInt, - maximum32BitSignedInt: c.maximum32BitSignedInt, - maximum32BitUnsignedInt: c.maximum32BitUnsignedInt, - minimum64BitSignedInt: c.minimum64BitSignedInt, - maximum64BitSignedInt: c.maximum64BitSignedInt, - maximum64BitUnsignedInt: c.maximum64BitUnsignedInt, - float32SignBitMask: c.float32SignBitMask, - float32RestBitMask: c.float32RestBitMask, - float64SignBitMask: c.float64SignBitMask, - float64RestBitMask: c.float64RestBitMask, - float32ForMinimumSigned32bitInteger: c.float32ForMinimumSigned32bitInteger, - float64ForMinimumSigned32bitInteger: c.float64ForMinimumSigned32bitInteger, - float32ForMinimumSigned64bitInteger: c.float32ForMinimumSigned64bitInteger, - float64ForMinimumSigned64bitInteger: c.float64ForMinimumSigned64bitInteger, - float32ForMaximumSigned32bitIntPlusOne: c.float32ForMaximumSigned32bitIntPlusOne, - float64ForMaximumSigned32bitIntPlusOne: c.float64ForMaximumSigned32bitIntPlusOne, - float32ForMaximumSigned64bitIntPlusOne: c.float32ForMaximumSigned64bitIntPlusOne, - float64ForMaximumSigned64bitIntPlusOne: c.float64ForMaximumSigned64bitIntPlusOne, - } - - // Reuses the initial location stack for the compilation of subsequent functions. - c.locationStack = &c.locationStackForEntrypoint -} - -// resetLabels resets the existing content in arm64Compiler.labels so that -// we could reuse the allocated slices and stacks in the subsequent compilations. -func (c *amd64Compiler) resetLabels() { - for i := range c.labels { - for j := range c.labels[i] { - if j > c.frameIDMax { - // Only need to reset until the maximum frame id. This makes the compilation faster for large binary. - break - } - l := &c.labels[i][j] - l.initialInstruction = nil - l.stackInitialized = false - l.initialStack.reset() - } - } -} - -// runtimeValueLocationStack implements compilerImpl.runtimeValueLocationStack for the amd64 architecture. -func (c *amd64Compiler) runtimeValueLocationStack() *runtimeValueLocationStack { - return c.locationStack -} - -// setLocationStack sets the given runtimeValueLocationStack to .locationStack field, -// while allowing us to track runtimeValueLocationStack.stackPointerCeil across multiple stacks. -// This is called when we branch into different block. -func (c *amd64Compiler) setLocationStack(newStack *runtimeValueLocationStack) { - if c.stackPointerCeil < c.locationStack.stackPointerCeil { - c.stackPointerCeil = c.locationStack.stackPointerCeil - } - c.locationStack = newStack -} - -// pushRuntimeValueLocationOnRegister implements compiler.pushRuntimeValueLocationOnRegister for amd64. -func (c *amd64Compiler) pushRuntimeValueLocationOnRegister(reg asm.Register, vt runtimeValueType) (ret *runtimeValueLocation) { - ret = c.locationStack.pushRuntimeValueLocationOnRegister(reg, vt) - c.locationStack.markRegisterUsed(reg) - return -} - -// pushVectorRuntimeValueLocationOnRegister implements compiler.pushVectorRuntimeValueLocationOnRegister for amd64. -func (c *amd64Compiler) pushVectorRuntimeValueLocationOnRegister(reg asm.Register) (lowerBitsLocation *runtimeValueLocation) { - lowerBitsLocation = c.locationStack.pushRuntimeValueLocationOnRegister(reg, runtimeValueTypeV128Lo) - c.locationStack.pushRuntimeValueLocationOnRegister(reg, runtimeValueTypeV128Hi) - c.locationStack.markRegisterUsed(reg) - return -} - -type amd64LabelInfo struct { - // initialInstruction is the initial instruction for this label so other block can jump into it. - initialInstruction asm.Node - // initialStack is the initial value location stack from which we start compiling this label. - initialStack runtimeValueLocationStack - stackInitialized bool -} - -func (c *amd64Compiler) label(label wazeroir.Label) *amd64LabelInfo { - kind := label.Kind() - frames := c.labels[kind] - frameID := label.FrameID() - if c.frameIDMax < frameID { - c.frameIDMax = frameID - } - // If the frameID is not allocated yet, expand the slice by twice of the diff, - // so that we could reduce the allocation in the subsequent compilation. - if diff := frameID - len(frames) + 1; diff > 0 { - for i := 0; i < diff; i++ { - frames = append(frames, amd64LabelInfo{initialStack: newRuntimeValueLocationStack()}) - } - c.labels[kind] = frames - } - return &frames[frameID] -} - -// compileBuiltinFunctionCheckExitCode implements compiler.compileBuiltinFunctionCheckExitCode for the amd64 architecture. -func (c *amd64Compiler) compileBuiltinFunctionCheckExitCode() error { - if err := c.compileCallBuiltinFunction(builtinFunctionIndexCheckExitCode); err != nil { - return err - } - - // After the function call, we have to initialize the stack base pointer and memory reserved registers. - c.compileReservedStackBasePointerInitialization() - c.compileReservedMemoryPointerInitialization() - return nil -} - -// compileGoDefinedHostFunction constructs the entire code to enter the host function implementation, -// and return to the caller. -func (c *amd64Compiler) compileGoDefinedHostFunction() error { - // First we must update the location stack to reflect the number of host function inputs. - c.locationStack.init(c.typ) - - if c.withListener { - if err := c.compileCallBuiltinFunction(builtinFunctionIndexFunctionListenerBefore); err != nil { - return err - } - } - - // Host function needs access to the caller's Function Instance, and the caller's information is stored in the stack - // (as described in the doc of callEngine.stack). Here, we get the caller's *wasm.FunctionInstance from the stack, - // and save it in callEngine.exitContext.callerFunctionInstance so we can pass it to the host function - // without sacrificing the performance. - c.compileReservedStackBasePointerInitialization() - // Alias for readability. - tmp := amd64.RegAX - // Get the location of the callerFunction (*function) in the stack, which depends on the signature. - _, _, callerFunction := c.locationStack.getCallFrameLocations(c.typ) - // Load the value into the tmp register: tmp = &function{..} - callerFunction.setRegister(tmp) - c.compileLoadValueOnStackToRegister(callerFunction) - // tmp = *(tmp+functionSourceOffset) = &wasm.ModuleInstance{...} - c.assembler.CompileMemoryToRegister(amd64.MOVQ, tmp, functionModuleInstanceOffset, tmp) - // Load it onto callEngine.exitContext.callerFunctionInstance. - c.assembler.CompileRegisterToMemory(amd64.MOVQ, - tmp, - amd64ReservedRegisterForCallEngine, callEngineExitContextCallerModuleInstanceOffset) - // Reset the state of callerFunction value location so that we won't mess up subsequent code generation below. - c.locationStack.releaseRegister(callerFunction) - - if err := c.compileCallGoHostFunction(); err != nil { - return err - } - - // Initializes the reserved stack base pointer which is used to retrieve the call frame stack. - c.compileReservedStackBasePointerInitialization() - - // Go function can change the module state in arbitrary way, so we have to force - // the callEngine.moduleContext initialization on the function return. To do so, - // we zero-out callEngine.moduleInstance. - c.assembler.CompileConstToMemory(amd64.MOVQ, - 0, amd64ReservedRegisterForCallEngine, callEngineModuleContextModuleInstanceOffset) - return c.compileReturnFunction() -} - -// compile implements compiler.compile for the amd64 architecture. -func (c *amd64Compiler) compile(buf asm.Buffer) (stackPointerCeil uint64, err error) { - // c.stackPointerCeil tracks the stack pointer ceiling (max seen) value across all runtimeValueLocationStack(s) - // used for all labels (via setLocationStack), excluding the current one. - // Hence, we check here if the final block's max one exceeds the current c.stackPointerCeil. - stackPointerCeil = c.stackPointerCeil - if stackPointerCeil < c.locationStack.stackPointerCeil { - stackPointerCeil = c.locationStack.stackPointerCeil - } - - // Now that the max stack pointer is determined, we are invoking the callback. - // Note this MUST be called before Assemble() below. - c.assignStackPointerCeil(stackPointerCeil) - - err = c.assembler.Assemble(buf) - return -} - -// compileUnreachable implements compiler.compileUnreachable for the amd64 architecture. -func (c *amd64Compiler) compileUnreachable() error { - c.compileExitFromNativeCode(nativeCallStatusCodeUnreachable) - return nil -} - -// assignStackPointerCeil implements compilerImpl.assignStackPointerCeil for the amd64 architecture. -func (c *amd64Compiler) assignStackPointerCeil(ceil uint64) { - if c.assignStackPointerCeilNeeded != nil { - c.assignStackPointerCeilNeeded.AssignDestinationConstant(int64(ceil) << 3) - } -} - -// compileSet implements compiler.compileSet for the amd64 architecture. -func (c *amd64Compiler) compileSet(o *wazeroir.UnionOperation) error { - depth := int(o.U1) - isTargetVector := o.B3 - - setTargetIndex := int(c.locationStack.sp) - 1 - depth - - if isTargetVector { - _ = c.locationStack.pop() // ignore the higher 64-bits. - } - v := c.locationStack.pop() - if err := c.compileEnsureOnRegister(v); err != nil { - return err - } - - targetLocation := &c.locationStack.stack[setTargetIndex] - if targetLocation.onRegister() { - // We no longer need the register previously used by the target location. - c.locationStack.markRegisterUnused(targetLocation.register) - } - - reg := v.register - targetLocation.setRegister(reg) - targetLocation.valueType = v.valueType - if isTargetVector { - hi := &c.locationStack.stack[setTargetIndex+1] - hi.setRegister(reg) - } - return nil -} - -// compileGlobalGet implements compiler.compileGlobalGet for the amd64 architecture. -func (c *amd64Compiler) compileGlobalGet(o *wazeroir.UnionOperation) error { - if err := c.maybeCompileMoveTopConditionalToGeneralPurposeRegister(); err != nil { - return err - } - - intReg, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - - // First, move the pointer to the global slice into the allocated register. - c.assembler.CompileMemoryToRegister(amd64.MOVQ, amd64ReservedRegisterForCallEngine, callEngineModuleContextGlobalElement0AddressOffset, intReg) - - index := o.U1 - - // Now, move the location of the global instance into the register. - c.assembler.CompileMemoryToRegister(amd64.MOVQ, intReg, 8*int64(index), intReg) - - // When an integer, reuse the pointer register for the value. Otherwise, allocate a float register for it. - valueReg := intReg - var vt runtimeValueType - var inst asm.Instruction - switch c.ir.Globals[index].ValType { - case wasm.ValueTypeI32: - inst = amd64.MOVL - vt = runtimeValueTypeI32 - case wasm.ValueTypeI64, wasm.ValueTypeExternref, wasm.ValueTypeFuncref: - inst = amd64.MOVQ - vt = runtimeValueTypeI64 - case wasm.ValueTypeF32: - inst = amd64.MOVL - vt = runtimeValueTypeF32 - valueReg, err = c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - case wasm.ValueTypeF64: - inst = amd64.MOVQ - vt = runtimeValueTypeF64 - valueReg, err = c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - case wasm.ValueTypeV128: - inst = amd64.MOVDQU - vt = runtimeValueTypeV128Lo - valueReg, err = c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - default: - panic("BUG: unknown runtime value type") - } - - // Using the register holding the pointer to the target instance, move its value into a register. - c.assembler.CompileMemoryToRegister(inst, intReg, globalInstanceValueOffset, valueReg) - - // Record that the retrieved global value on the top of the stack is now in a register. - if vt == runtimeValueTypeV128Lo { - c.pushVectorRuntimeValueLocationOnRegister(valueReg) - } else { - c.pushRuntimeValueLocationOnRegister(valueReg, vt) - } - return nil -} - -// compileGlobalSet implements compiler.compileGlobalSet for the amd64 architecture. -func (c *amd64Compiler) compileGlobalSet(o *wazeroir.UnionOperation) error { - index := o.U1 - - wasmValueType := c.ir.Globals[index].ValType - isV128 := wasmValueType == wasm.ValueTypeV128 - - // First, move the value to set into a temporary register. - val := c.locationStack.pop() - if isV128 { - // The previous val is higher 64-bits, and have to use lower 64-bit's runtimeValueLocation for allocation, etc. - val = c.locationStack.pop() - } - if err := c.compileEnsureOnRegister(val); err != nil { - return err - } - - // Allocate a register to hold the memory location of the target global instance. - intReg, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - - // First, move the pointer to the global slice into the allocated register. - c.assembler.CompileMemoryToRegister(amd64.MOVQ, amd64ReservedRegisterForCallEngine, callEngineModuleContextGlobalElement0AddressOffset, intReg) - - // Now, move the location of the global instance into the register. - c.assembler.CompileMemoryToRegister(amd64.MOVQ, intReg, 8*int64(index), intReg) - - // Now ready to write the value to the global instance location. - var inst asm.Instruction - if isV128 { - inst = amd64.MOVDQU - } else if wasmValueType == wasm.ValueTypeI32 || wasmValueType == wasm.ValueTypeF32 { - inst = amd64.MOVL - } else { - inst = amd64.MOVQ - } - c.assembler.CompileRegisterToMemory(inst, val.register, intReg, globalInstanceValueOffset) - - // Since the value is now written to memory, release the value register. - c.locationStack.releaseRegister(val) - return nil -} - -// compileBr implements compiler.compileBr for the amd64 architecture. -func (c *amd64Compiler) compileBr(o *wazeroir.UnionOperation) error { - if err := c.maybeCompileMoveTopConditionalToGeneralPurposeRegister(); err != nil { - return err - } - return c.branchInto(wazeroir.Label(o.U1)) -} - -// branchInto adds instruction necessary to jump into the given branch target. -func (c *amd64Compiler) branchInto(target wazeroir.Label) error { - if target.IsReturnTarget() { - return c.compileReturnFunction() - } else { - if c.ir.LabelCallers[target] > 1 { - // We can only re-use register state if when there's a single call-site. - // Release existing values on registers to the stack if there's multiple ones to have - // the consistent value location state at the beginning of label. - if err := c.compileReleaseAllRegistersToStack(); err != nil { - return err - } - } - // Set the initial stack of the target label, so we can start compiling the label - // with the appropriate value locations. Note we clone the stack here as we maybe - // manipulate the stack before compiler reaches the label. - targetLabel := c.label(target) - if !targetLabel.stackInitialized { - targetLabel.initialStack.cloneFrom(*c.locationStack) - targetLabel.stackInitialized = true - } - jmp := c.assembler.CompileJump(amd64.JMP) - c.assignJumpTarget(target, jmp) - } - return nil -} - -// compileBrIf implements compiler.compileBrIf for the amd64 architecture. -func (c *amd64Compiler) compileBrIf(o *wazeroir.UnionOperation) error { - cond := c.locationStack.pop() - var jmpWithCond asm.Node - if cond.onConditionalRegister() { - var inst asm.Instruction - switch cond.conditionalRegister { - case amd64.ConditionalRegisterStateE: - inst = amd64.JEQ - case amd64.ConditionalRegisterStateNE: - inst = amd64.JNE - case amd64.ConditionalRegisterStateS: - inst = amd64.JMI - case amd64.ConditionalRegisterStateNS: - inst = amd64.JPL - case amd64.ConditionalRegisterStateG: - inst = amd64.JGT - case amd64.ConditionalRegisterStateGE: - inst = amd64.JGE - case amd64.ConditionalRegisterStateL: - inst = amd64.JLT - case amd64.ConditionalRegisterStateLE: - inst = amd64.JLE - case amd64.ConditionalRegisterStateA: - inst = amd64.JHI - case amd64.ConditionalRegisterStateAE: - inst = amd64.JCC - case amd64.ConditionalRegisterStateB: - inst = amd64.JCS - case amd64.ConditionalRegisterStateBE: - inst = amd64.JLS - } - jmpWithCond = c.assembler.CompileJump(inst) - } else { - // Usually the comparison operand for br_if is on the conditional register, - // but in some cases, they are on the stack or register. - // For example, the following code - // i64.const 1 - // local.get 1 - // i64.add - // br_if .... - // will try to use the result of i64.add, which resides on the (virtual) stack, - // as the operand for br_if instruction. - if err := c.compileEnsureOnRegister(cond); err != nil { - return err - } - // Check if the value not equals zero. - c.assembler.CompileRegisterToRegister(amd64.TESTQ, cond.register, cond.register) - - // Emit jump instruction which jumps when the value does not equals zero. - jmpWithCond = c.assembler.CompileJump(amd64.JNE) - c.locationStack.markRegisterUnused(cond.register) - } - - // Make sure that the next coming label is the else jump target. - thenTarget := wazeroir.Label(o.U1) - elseTarget := wazeroir.Label(o.U2) - thenToDrop := o.U3 - - // Here's the diagram of how we organize the instructions necessarily for brif operation. - // - // jmp_with_cond -> jmp (.Else) -> Then operations... - // |---------(satisfied)------------^^^ - // - // Note that .Else branch doesn't have ToDrop as .Else is in reality - // corresponding to either If's Else block or Br_if's else block in Wasm. - - // Emit the else branch. - if elseTarget.IsReturnTarget() { - if err := c.compileReturnFunction(); err != nil { - return err - } - } else { - labelInfo := c.label(elseTarget) - if !labelInfo.stackInitialized { - labelInfo.initialStack.cloneFrom(*c.locationStack) - labelInfo.stackInitialized = true - } - - elseJmp := c.assembler.CompileJump(amd64.JMP) - c.assignJumpTarget(elseTarget, elseJmp) - } - - // Handle then branch. - c.assembler.SetJumpTargetOnNext(jmpWithCond) - if err := compileDropRange(c, thenToDrop); err != nil { - return err - } - if thenTarget.IsReturnTarget() { - return c.compileReturnFunction() - } else { - thenLabel := thenTarget - if c.ir.LabelCallers[thenLabel] > 1 { - // We can only re-use register state if when there's a single call-site. - // Release existing values on registers to the stack if there's multiple ones to have - // the consistent value location state at the beginning of label. - if err := c.compileReleaseAllRegistersToStack(); err != nil { - return err - } - } - // Set the initial stack of the target label, so we can start compiling the label - // with the appropriate value locations. Note we clone the stack here as we maybe - // manipulate the stack before compiler reaches the label. - labelInfo := c.label(thenLabel) - if !labelInfo.stackInitialized { - labelInfo.initialStack.cloneFrom(*c.locationStack) - labelInfo.stackInitialized = true - } - thenJmp := c.assembler.CompileJump(amd64.JMP) - c.assignJumpTarget(thenLabel, thenJmp) - return nil - } -} - -// compileBrTable implements compiler.compileBrTable for the amd64 architecture. -func (c *amd64Compiler) compileBrTable(o *wazeroir.UnionOperation) error { - index := c.locationStack.pop() - - // If the operation only consists of the default target, we branch into it and return early. - if len(o.Us) == 2 { - c.locationStack.releaseRegister(index) - if err := compileDropRange(c, o.Us[1]); err != nil { - return err - } - return c.branchInto(wazeroir.Label(o.Us[0])) - } - - // Otherwise, we jump into the selected branch. - if err := c.compileEnsureOnRegister(index); err != nil { - return err - } - - tmp, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - - // First, we move the length of target list into the tmp register. - c.assembler.CompileConstToRegister(amd64.MOVQ, int64(len(o.Us)/2-1), tmp) - - // Then, we compare the value with the length of targets. - c.assembler.CompileRegisterToRegister(amd64.CMPL, tmp, index.register) - - // If the value is larger than the length, - // we round the index to the length as the spec states that - // if the index is larger than or equal the length of list, - // branch into the default branch. - c.assembler.CompileRegisterToRegister(amd64.CMOVQCS, tmp, index.register) - - // We prepare the static data which holds the offset of - // each target's first instruction (incl. default) - // relative to the beginning of label tables. - // - // For example, if we have targets=[L0, L1] and default=L_DEFAULT, - // we emit the the code like this at [Emit the code for each targets and default branch] below. - // - // L0: - // 0x123001: XXXX, ... - // ..... - // L1: - // 0x123005: YYY, ... - // ..... - // L_DEFAULT: - // 0x123009: ZZZ, ... - // - // then offsetData becomes like [0x0, 0x5, 0x8]. - // By using this offset list, we could jump into the label for the index by - // "jmp offsetData[index]+0x123001" and "0x123001" can be acquired by "LEA" - // instruction. - // - // Note: We store each offset of 32-bite unsigned integer as 4 consecutive bytes. So more precisely, - // the above example's offsetData would be [0x0, 0x0, 0x0, 0x0, 0x5, 0x0, 0x0, 0x0, 0x8, 0x0, 0x0, 0x0]. - // - // Note: this is similar to how GCC implements Switch statements in C. - offsetData := asm.NewStaticConst(make([]byte, 4*(len(o.Us)/2))) - - // Load the offsetData's address into tmp. - if err = c.assembler.CompileStaticConstToRegister(amd64.LEAQ, offsetData, tmp); err != nil { - return err - } - - // Now we have the address of first byte of offsetData in tmp register. - // So the target offset's first byte is at tmp+index*4 as we store - // the offset as 4 bytes for a 32-byte integer. - // Here, we store the offset into the index.register. - c.assembler.CompileMemoryWithIndexToRegister(amd64.MOVL, tmp, 0, index.register, 4, index.register) - - // Now we read the address of the beginning of the jump table. - // In the above example, this corresponds to reading the address of 0x123001. - c.assembler.CompileReadInstructionAddress(tmp, amd64.JMP) - - // Now we have the address of L0 in tmp register, and the offset to the target label in the index.register. - // So we could achieve the br_table jump by adding them and jump into the resulting address. - c.assembler.CompileRegisterToRegister(amd64.ADDQ, index.register, tmp) - - c.assembler.CompileJumpToRegister(amd64.JMP, tmp) - - // We no longer need the index's register, so mark it unused. - c.locationStack.markRegisterUnused(index.register) - - // [Emit the code for each targets and default branch] - labelInitialInstructions := make([]asm.Node, len(o.Us)/2) - - // Since we might end up having the different stack state in each branch, - // we need to save the initial stack state here, and use the same initial state - // for each iteration. - initialLocationStack := c.getSavedTemporaryLocationStack() - - for i := range labelInitialInstructions { - // Emit the initial instruction of each target. - // We use NOP as we don't yet know the next instruction in each label. - // Assembler would optimize out this NOP during code generation, so this is harmless. - labelInitialInstructions[i] = c.assembler.CompileStandAlone(amd64.NOP) - - targetLabel := wazeroir.Label(o.Us[i*2]) - targetToDrop := o.Us[i*2+1] - if err = compileDropRange(c, targetToDrop); err != nil { - return err - } - if err = c.branchInto(targetLabel); err != nil { - return err - } - // After the iteration, reset the stack's state with initialLocationStack. - c.locationStack.cloneFrom(initialLocationStack) - } - - c.assembler.BuildJumpTable(offsetData, labelInitialInstructions) - return nil -} - -func (c *amd64Compiler) getSavedTemporaryLocationStack() runtimeValueLocationStack { - initialLocationStack := *c.locationStack // Take copy! - // Use c.brTableTmp for the underlying stack so that we could reduce the allocations. - if diff := int(initialLocationStack.sp) - len(c.brTableTmp); diff > 0 { - c.brTableTmp = append(c.brTableTmp, make([]runtimeValueLocation, diff)...) - } - copy(c.brTableTmp, initialLocationStack.stack[:initialLocationStack.sp]) - initialLocationStack.stack = c.brTableTmp - return initialLocationStack -} - -func (c *amd64Compiler) assignJumpTarget(label wazeroir.Label, jmpInstruction asm.Node) { - jmpTargetLabel := c.label(label) - targetInst := jmpTargetLabel.initialInstruction - if targetInst == nil { - // If the label isn't compiled yet, allocate the NOP node, and set as the initial instruction. - targetInst = c.assembler.AllocateNOP() - jmpTargetLabel.initialInstruction = targetInst - } - jmpInstruction.AssignJumpTarget(targetInst) -} - -// compileLabel implements compiler.compileLabel for the amd64 architecture. -func (c *amd64Compiler) compileLabel(o *wazeroir.UnionOperation) (skipLabel bool) { - label := wazeroir.Label(o.U1) - labelInfo := c.label(label) - - // If initialStack is not set, that means this label has never been reached. - if !labelInfo.stackInitialized { - skipLabel = true - return - } - - // We use NOP as a beginning of instructions in a label. - if labelBegin := labelInfo.initialInstruction; labelBegin == nil { - // We use NOP as a beginning of instructions in a label. - // This should be eventually optimized out by assembler. - labelInfo.initialInstruction = c.assembler.CompileStandAlone(amd64.NOP) - } else { - c.assembler.Add(labelBegin) - } - - // Set the initial stack. - c.setLocationStack(&labelInfo.initialStack) - return -} - -// compileCall implements compiler.compileCall for the amd64 architecture. -func (c *amd64Compiler) compileCall(o *wazeroir.UnionOperation) error { - if err := c.maybeCompileMoveTopConditionalToGeneralPurposeRegister(); err != nil { - return err - } - - functionIndex := o.U1 - - target := c.ir.Functions[functionIndex] - targetType := &c.ir.Types[target] - - targetAddressRegister, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - - // First, push the index to the callEngine.functionsElement0Address into the target register. - c.assembler.CompileConstToRegister(amd64.MOVQ, int64(functionIndex)*functionSize, targetAddressRegister) - - // Next, we add the address of the first item of callEngine.functions slice (= &callEngine.functions[0]) - // to the target register. - c.assembler.CompileMemoryToRegister(amd64.ADDQ, amd64ReservedRegisterForCallEngine, - callEngineModuleContextFunctionsElement0AddressOffset, targetAddressRegister) - - if err := c.compileCallFunctionImpl(targetAddressRegister, targetType); err != nil { - return err - } - return nil -} - -// compileCallIndirect implements compiler.compileCallIndirect for the amd64 architecture. -func (c *amd64Compiler) compileCallIndirect(o *wazeroir.UnionOperation) error { - offset := c.locationStack.pop() - if err := c.compileEnsureOnRegister(offset); err != nil { - return nil - } - typeIndex := o.U1 - tableIndex := o.U2 - - tmp, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - c.locationStack.markRegisterUsed(tmp) - - tmp2, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - c.locationStack.markRegisterUsed(tmp2) - - // Load the address of the target table: tmp = &module.Tables[0] - c.assembler.CompileMemoryToRegister(amd64.MOVQ, amd64ReservedRegisterForCallEngine, callEngineModuleContextTablesElement0AddressOffset, tmp) - // tmp = &module.Tables[0] + Index*8 = &module.Tables[0] + sizeOf(*TableInstance)*index = module.Tables[o.TableIndex]. - c.assembler.CompileMemoryToRegister(amd64.MOVQ, tmp, int64(tableIndex*8), tmp) - - // Then, we need to trap if the offset exceeds the length of table. - c.assembler.CompileMemoryToRegister(amd64.CMPQ, tmp, tableInstanceTableLenOffset, offset.register) - c.compileMaybeExitFromNativeCode(amd64.JHI, nativeCallStatusCodeInvalidTableAccess) - - // next we check if the target's type matches the operation's one. - // In order to get the type instance's address, we have to multiply the offset - // by 8 as the offset is the "length" of table in Go's "[]uintptr{}", - // and size of uintptr equals 8 bytes == (2^3). - c.assembler.CompileConstToRegister(amd64.SHLQ, pointerSizeLog2, offset.register) - - // Adds the address of wasm.Table[0] stored as callEngine.tableElement0Address to the offset. - c.assembler.CompileMemoryToRegister(amd64.ADDQ, - tmp, tableInstanceTableOffset, offset.register) - - // "offset = (*offset) (== table[offset] == *code type)" - c.assembler.CompileMemoryToRegister(amd64.MOVQ, offset.register, 0, offset.register) - - // At this point offset.register holds the address of *code (as uintptr) at wasm.Table[offset]. - // - // Check if the value of table[offset] equals zero, meaning that the target is uninitialized. - c.assembler.CompileRegisterToRegister(amd64.TESTQ, offset.register, offset.register) - - // Skipped if the target is initialized. - c.compileMaybeExitFromNativeCode(amd64.JNE, nativeCallStatusCodeInvalidTableAccess) - - // Next, we need to check the type matches, i.e. table[offset].source.TypeID == targetFunctionType's typeID. - // - // "tmp2 = [&moduleInstance.TypeIDs[0] + index * 4] (== moduleInstance.TypeIDs[index])" - c.assembler.CompileMemoryToRegister(amd64.MOVQ, - amd64ReservedRegisterForCallEngine, callEngineModuleContextTypeIDsElement0AddressOffset, - tmp2) - c.assembler.CompileMemoryToRegister(amd64.MOVL, tmp2, int64(typeIndex)*4, tmp2) - - // Skipped if the type matches. - c.assembler.CompileMemoryToRegister(amd64.CMPL, offset.register, functionTypeIDOffset, tmp2) - c.compileMaybeExitFromNativeCode(amd64.JEQ, nativeCallStatusCodeTypeMismatchOnIndirectCall) - targetFunctionType := &c.ir.Types[typeIndex] - if err = c.compileCallFunctionImpl(offset.register, targetFunctionType); err != nil { - return nil - } - - // The offset register should be marked as un-used as we consumed in the function call. - c.locationStack.markRegisterUnused(offset.register, tmp, tmp2) - return nil -} - -// compileDrop implements compiler.compileDrop for the amd64 architecture. -func (c *amd64Compiler) compileDrop(o *wazeroir.UnionOperation) error { - return compileDropRange(c, o.U1) -} - -// compileSelectV128Impl implements compileSelect for vector values. -func (c *amd64Compiler) compileSelectV128Impl(selectorReg asm.Register) error { - x2 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x2); err != nil { - return err - } - - x1 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x1); err != nil { - return err - } - - // Compare the conditional value with zero. - c.assembler.CompileRegisterToRegister(amd64.TESTQ, selectorReg, selectorReg) - - // Set the jump if the top value is not zero. - jmpIfNotZero := c.assembler.CompileJump(amd64.JNE) - - // In this branch, we select the value of x2, so we move the value into x1.register so that - // we can have the result in x1.register regardless of the selection. - c.assembler.CompileRegisterToRegister(amd64.MOVDQU, x2.register, x1.register) - - // Else, we don't need to adjust value, just need to jump to the next instruction. - c.assembler.SetJumpTargetOnNext(jmpIfNotZero) - - // As noted, the result exists in x1.register regardless of the selector. - c.pushVectorRuntimeValueLocationOnRegister(x1.register) - // Plus, x2.register is no longer used. - c.locationStack.markRegisterUnused(x2.register) - c.locationStack.markRegisterUnused(selectorReg) - return nil -} - -// compileSelect implements compiler.compileSelect for the amd64 architecture. -// -// The emitted native code depends on whether the values are on -// the physical registers or memory stack, or maybe conditional register. -func (c *amd64Compiler) compileSelect(o *wazeroir.UnionOperation) error { - cv := c.locationStack.pop() - if err := c.compileEnsureOnRegister(cv); err != nil { - return err - } - - isTargetVector := o.B3 - if isTargetVector { - return c.compileSelectV128Impl(cv.register) - } - - x2 := c.locationStack.pop() - // We do not consume x1 here, but modify the value according to - // the conditional value "c" above. - peekedX1 := c.locationStack.peek() - - // Compare the conditional value with zero. - c.assembler.CompileRegisterToRegister(amd64.TESTQ, cv.register, cv.register) - - // Now we can use c.register as temporary location. - // We alias it here for readability. - tmpRegister := cv.register - - // Set the jump if the top value is not zero. - jmpIfNotZero := c.assembler.CompileJump(amd64.JNE) - - // If the value is zero, we must place the value of x2 onto the stack position of x1. - - // First we copy the value of x2 to the temporary register if x2 is not currently on a register. - if x2.onStack() { - x2.register = tmpRegister - c.compileLoadValueOnStackToRegister(x2) - } - - // - // At this point x2's value is always on a register. - // - - // Then release the value in the x2's register to the x1's stack position. - if peekedX1.onRegister() { - c.assembler.CompileRegisterToRegister(amd64.MOVQ, x2.register, peekedX1.register) - } else { - peekedX1.register = x2.register - c.compileReleaseRegisterToStack(peekedX1) // Note inside we mark the register unused! - } - - // Else, we don't need to adjust value, just need to jump to the next instruction. - c.assembler.SetJumpTargetOnNext(jmpIfNotZero) - - // In any case, we don't need x2 and c anymore! - c.locationStack.releaseRegister(x2) - c.locationStack.releaseRegister(cv) - return nil -} - -// compilePick implements compiler.compilePick for the amd64 architecture. -func (c *amd64Compiler) compilePick(o *wazeroir.UnionOperation) error { - if err := c.maybeCompileMoveTopConditionalToGeneralPurposeRegister(); err != nil { - return err - } - depth := o.U1 - isTargetVector := o.B3 - - // TODO: if we track the type of values on the stack, - // we could optimize the instruction according to the bit size of the value. - // For now, we just move the entire register i.e. as a quad word (8 bytes). - pickTarget := &c.locationStack.stack[c.locationStack.sp-1-uint64(depth)] - reg, err := c.allocateRegister(pickTarget.getRegisterType()) - if err != nil { - return err - } - - if pickTarget.onRegister() { - var inst asm.Instruction - if isTargetVector { - inst = amd64.MOVDQU - } else if pickTarget.valueType == runtimeValueTypeI32 { // amd64 cannot copy single-precisions between registers. - inst = amd64.MOVL - } else { - inst = amd64.MOVQ - } - c.assembler.CompileRegisterToRegister(inst, pickTarget.register, reg) - } else if pickTarget.onStack() { - // Copy the value from the stack. - var inst asm.Instruction - if isTargetVector { - inst = amd64.MOVDQU - } else if pickTarget.valueType == runtimeValueTypeI32 || pickTarget.valueType == runtimeValueTypeF32 { - inst = amd64.MOVL - } else { - inst = amd64.MOVQ - } - // Note: stack pointers are ensured not to exceed 2^27 so this offset never exceeds 32-bit range. - c.assembler.CompileMemoryToRegister(inst, amd64ReservedRegisterForStackBasePointerAddress, - int64(pickTarget.stackPointer)*8, reg) - } - // Now we already placed the picked value on the register, - // so push the location onto the stack. - if isTargetVector { - c.pushVectorRuntimeValueLocationOnRegister(reg) - } else { - c.pushRuntimeValueLocationOnRegister(reg, pickTarget.valueType) - } - return nil -} - -// compileAdd implements compiler.compileAdd for the amd64 architecture. -func (c *amd64Compiler) compileAdd(o *wazeroir.UnionOperation) error { - // TODO: if the previous instruction is const, then - // this can be optimized. Same goes for other arithmetic instructions. - - var instruction asm.Instruction - - unsignedType := wazeroir.UnsignedType(o.B1) - switch unsignedType { - case wazeroir.UnsignedTypeI32: - instruction = amd64.ADDL - case wazeroir.UnsignedTypeI64: - instruction = amd64.ADDQ - case wazeroir.UnsignedTypeF32: - instruction = amd64.ADDSS - case wazeroir.UnsignedTypeF64: - instruction = amd64.ADDSD - } - - x2 := c.locationStack.pop() - if err := c.compileEnsureOnRegister(x2); err != nil { - return err - } - - x1 := c.locationStack.peek() // Note this is peek! - if err := c.compileEnsureOnRegister(x1); err != nil { - return err - } - - // x1 += x2. - c.assembler.CompileRegisterToRegister(instruction, x2.register, x1.register) - - // We no longer need x2 register after ADD operation here, - // so we release it. - c.locationStack.releaseRegister(x2) - return nil -} - -// compileSub implements compiler.compileSub for the amd64 architecture. -func (c *amd64Compiler) compileSub(o *wazeroir.UnionOperation) error { - // TODO: if the previous instruction is const, then - // this can be optimized. Same goes for other arithmetic instructions. - - var instruction asm.Instruction - unsignedType := wazeroir.UnsignedType(o.B1) - switch unsignedType { - case wazeroir.UnsignedTypeI32: - instruction = amd64.SUBL - case wazeroir.UnsignedTypeI64: - instruction = amd64.SUBQ - case wazeroir.UnsignedTypeF32: - instruction = amd64.SUBSS - case wazeroir.UnsignedTypeF64: - instruction = amd64.SUBSD - } - - x2 := c.locationStack.pop() - if err := c.compileEnsureOnRegister(x2); err != nil { - return err - } - - x1 := c.locationStack.peek() // Note this is peek! - if err := c.compileEnsureOnRegister(x1); err != nil { - return err - } - - // x1 -= x2. - c.assembler.CompileRegisterToRegister(instruction, x2.register, x1.register) - - // We no longer need x2 register after ADD operation here, - // so we release it. - c.locationStack.releaseRegister(x2) - return nil -} - -// compileMul implements compiler.compileMul for the amd64 architecture. -func (c *amd64Compiler) compileMul(o *wazeroir.UnionOperation) (err error) { - unsignedType := wazeroir.UnsignedType(o.B1) - switch unsignedType { - case wazeroir.UnsignedTypeI32: - err = c.compileMulForInts(true, amd64.MULL) - case wazeroir.UnsignedTypeI64: - err = c.compileMulForInts(false, amd64.MULQ) - case wazeroir.UnsignedTypeF32: - err = c.compileMulForFloats(amd64.MULSS) - case wazeroir.UnsignedTypeF64: - err = c.compileMulForFloats(amd64.MULSD) - } - return -} - -// compileMulForInts emits instructions to perform integer multiplication for -// top two values on the stack. If unfamiliar with the convention for integer -// multiplication on x86, see https://www.felixcloutier.com/x86/mul. -// -// In summary, one of the values must be on the AX register, -// and the mul instruction stores the overflow info in DX register which we don't use. -// Here, we mean "the overflow info" by 65 bit or higher part of the result for 64 bit case. -// -// So, we have to ensure that -// 1. Previously located value on DX must be saved to memory stack. That is because -// the existing value will be overridden after the mul execution. -// 2. One of the operands (x1 or x2) must be on AX register. -// -// See https://www.felixcloutier.com/x86/mul#description for detail semantics. -func (c *amd64Compiler) compileMulForInts(is32Bit bool, mulInstruction asm.Instruction) error { - const ( - resultRegister = amd64.RegAX - reservedRegister = amd64.RegDX - ) - - x2 := c.locationStack.pop() - x1 := c.locationStack.pop() - - var valueOnAX *runtimeValueLocation - if x1.register == resultRegister { - valueOnAX = x1 - } else if x2.register == resultRegister { - valueOnAX = x2 - } else { - valueOnAX = x2 - // This case we move x2 to AX register. - c.onValueReleaseRegisterToStack(resultRegister) - if x2.onConditionalRegister() { - c.compileMoveConditionalToGeneralPurposeRegister(x2, resultRegister) - } else if x2.onStack() { - x2.setRegister(resultRegister) - c.compileLoadValueOnStackToRegister(x2) - c.locationStack.markRegisterUsed(resultRegister) - } else { - var inst asm.Instruction - if is32Bit { - inst = amd64.MOVL - } else { - inst = amd64.MOVQ - } - c.assembler.CompileRegisterToRegister(inst, x2.register, resultRegister) - - // We no longer uses the prev register of x2. - c.locationStack.releaseRegister(x2) - x2.setRegister(resultRegister) - c.locationStack.markRegisterUsed(resultRegister) - } - } - - // We have to make sure that at this point the operands must be on registers. - if err := c.compileEnsureOnRegister(x2); err != nil { - return err - } - if err := c.compileEnsureOnRegister(x1); err != nil { - return err - } - - // We have to save the existing value on DX. - // If the DX register is used by either x1 or x2, we don't need to - // save the value because it is consumed by mul anyway. - if x1.register != reservedRegister && x2.register != reservedRegister { - c.onValueReleaseRegisterToStack(reservedRegister) - } - - // Now ready to emit the mul instruction. - if x1 == valueOnAX { - c.assembler.CompileRegisterToNone(mulInstruction, x2.register) - } else { - c.assembler.CompileRegisterToNone(mulInstruction, x1.register) - } - - c.locationStack.markRegisterUnused(x2.register) - c.locationStack.markRegisterUnused(x1.register) - - // Now we have the result in the AX register, - // so we record it. - c.pushRuntimeValueLocationOnRegister(resultRegister, x1.valueType) - return nil -} - -func (c *amd64Compiler) compileMulForFloats(instruction asm.Instruction) error { - x2 := c.locationStack.pop() - if err := c.compileEnsureOnRegister(x2); err != nil { - return err - } - - x1 := c.locationStack.peek() // Note this is peek! - if err := c.compileEnsureOnRegister(x1); err != nil { - return err - } - - // x1 *= x2. - c.assembler.CompileRegisterToRegister(instruction, x2.register, x1.register) - - // We no longer need x2 register after MUL operation here, - // so we release it. - c.locationStack.releaseRegister(x2) - return nil -} - -// compileClz implements compiler.compileClz for the amd64 architecture. -func (c *amd64Compiler) compileClz(o *wazeroir.UnionOperation) error { - target := c.locationStack.pop() - if err := c.compileEnsureOnRegister(target); err != nil { - return err - } - - unsignedInt := wazeroir.UnsignedInt(o.B1) - if c.cpuFeatures.HasExtra(platform.CpuExtraFeatureAmd64ABM) { - if unsignedInt == wazeroir.UnsignedInt32 { - c.assembler.CompileRegisterToRegister(amd64.LZCNTL, target.register, target.register) - } else { - c.assembler.CompileRegisterToRegister(amd64.LZCNTQ, target.register, target.register) - } - } else { - // On processors that do not support LZCNT, we combine BSR (calculating - // most significant set bit) with XOR. This logic is described in - // "Replace Raw Assembly Code with Builtin Intrinsics" section in: - // https://developer.apple.com/documentation/apple-silicon/addressing-architectural-differences-in-your-macos-code. - - // First, we have to check if the target is non-zero as BSR is undefined - // on zero. See https://www.felixcloutier.com/x86/bsr. - c.assembler.CompileRegisterToRegister(amd64.TESTQ, target.register, target.register) - jmpIfNonZero := c.assembler.CompileJump(amd64.JNE) - - // If the value is zero, we just push the const value. - if unsignedInt == wazeroir.UnsignedInt32 { - c.assembler.CompileConstToRegister(amd64.MOVL, int64(32), target.register) - } else { - c.assembler.CompileConstToRegister(amd64.MOVL, int64(64), target.register) - } - - // Emit the jmp instruction to jump to the position right after - // the non-zero case. - jmpAtEndOfZero := c.assembler.CompileJump(amd64.JMP) - - // Start emitting non-zero case. - c.assembler.SetJumpTargetOnNext(jmpIfNonZero) - // First, we calculate the most significant set bit. - if unsignedInt == wazeroir.UnsignedInt32 { - c.assembler.CompileRegisterToRegister(amd64.BSRL, target.register, target.register) - } else { - c.assembler.CompileRegisterToRegister(amd64.BSRQ, target.register, target.register) - } - - // Now we XOR the value with the bit length minus one. - if unsignedInt == wazeroir.UnsignedInt32 { - c.assembler.CompileConstToRegister(amd64.XORL, 31, target.register) - } else { - c.assembler.CompileConstToRegister(amd64.XORQ, 63, target.register) - } - - // Finally the end jump instruction of zero case must target towards - // the next instruction. - c.assembler.SetJumpTargetOnNext(jmpAtEndOfZero) - } - - // We reused the same register of target for the result. - c.locationStack.markRegisterUnused(target.register) - c.pushRuntimeValueLocationOnRegister(target.register, target.valueType) - return nil -} - -// compileCtz implements compiler.compileCtz for the amd64 architecture. -func (c *amd64Compiler) compileCtz(o *wazeroir.UnionOperation) error { - target := c.locationStack.pop() - if err := c.compileEnsureOnRegister(target); err != nil { - return err - } - - unsignedInt := wazeroir.UnsignedInt(o.B1) - if c.cpuFeatures.HasExtra(platform.CpuExtraFeatureAmd64ABM) { - if unsignedInt == wazeroir.UnsignedInt32 { - c.assembler.CompileRegisterToRegister(amd64.TZCNTL, target.register, target.register) - } else { - c.assembler.CompileRegisterToRegister(amd64.TZCNTQ, target.register, target.register) - } - } else { - // On processors that do not support TZCNT, the BSF instruction is - // executed instead. The key difference between TZCNT and BSF - // instruction is that if source operand is zero, the content of - // destination operand is undefined. - // https://www.felixcloutier.com/x86/tzcnt.html - - // First we compare the target with zero. - c.assembler.CompileRegisterToRegister(amd64.TESTQ, target.register, target.register) - jmpIfNonZero := c.assembler.CompileJump(amd64.JNE) - - // If the value is zero, we just push the const value. - if unsignedInt == wazeroir.UnsignedInt32 { - c.assembler.CompileConstToRegister(amd64.MOVL, int64(32), target.register) - } else { - c.assembler.CompileConstToRegister(amd64.MOVL, int64(64), target.register) - } - - // Emit the jmp instruction to jump to the position right after - // the non-zero case. - jmpAtEndOfZero := c.assembler.CompileJump(amd64.JMP) - - // Otherwise, emit the TZCNT. - c.assembler.SetJumpTargetOnNext(jmpIfNonZero) - if unsignedInt == wazeroir.UnsignedInt32 { - c.assembler.CompileRegisterToRegister(amd64.TZCNTL, target.register, target.register) - } else { - c.assembler.CompileRegisterToRegister(amd64.TZCNTQ, target.register, target.register) - } - - // Finally the end jump instruction of zero case must target towards - // the next instruction. - c.assembler.SetJumpTargetOnNext(jmpAtEndOfZero) - } - - // We reused the same register of target for the result. - c.locationStack.markRegisterUnused(target.register) - c.pushRuntimeValueLocationOnRegister(target.register, target.valueType) - return nil -} - -// compilePopcnt implements compiler.compilePopcnt for the amd64 architecture. -func (c *amd64Compiler) compilePopcnt(o *wazeroir.UnionOperation) error { - target := c.locationStack.pop() - if err := c.compileEnsureOnRegister(target); err != nil { - return err - } - - unsignedInt := wazeroir.UnsignedInt(o.B1) - if unsignedInt == wazeroir.UnsignedInt32 { - c.assembler.CompileRegisterToRegister(amd64.POPCNTL, target.register, target.register) - } else { - c.assembler.CompileRegisterToRegister(amd64.POPCNTQ, target.register, target.register) - } - - // We reused the same register of target for the result. - c.locationStack.markRegisterUnused(target.register) - c.pushRuntimeValueLocationOnRegister(target.register, target.valueType) - return nil -} - -// compileDiv implements compiler.compileDiv for the amd64 architecture. -func (c *amd64Compiler) compileDiv(o *wazeroir.UnionOperation) (err error) { - signedType := wazeroir.SignedType(o.B1) - switch signedType { - case wazeroir.SignedTypeUint32: - err = c.compileDivForInts(true, false) - case wazeroir.SignedTypeUint64: - err = c.compileDivForInts(false, false) - case wazeroir.SignedTypeInt32: - err = c.compileDivForInts(true, true) - case wazeroir.SignedTypeInt64: - err = c.compileDivForInts(false, true) - case wazeroir.SignedTypeFloat32: - err = c.compileDivForFloats(true) - case wazeroir.SignedTypeFloat64: - err = c.compileDivForFloats(false) - } - return -} - -// compileDivForInts emits the instructions to perform division on the top -// two values of integer type on the stack and puts the quotient of the result -// onto the stack. For example, stack [..., 10, 3] results in [..., 3] where -// the remainder is discarded. -func (c *amd64Compiler) compileDivForInts(is32Bit bool, signed bool) error { - if err := c.performDivisionOnInts(false, is32Bit, signed); err != nil { - return err - } - // Now we have the quotient of the division result in the AX register, - // so we record it. - if is32Bit { - c.pushRuntimeValueLocationOnRegister(amd64.RegAX, runtimeValueTypeI32) - } else { - c.pushRuntimeValueLocationOnRegister(amd64.RegAX, runtimeValueTypeI64) - } - return nil -} - -// compileRem implements compiler.compileRem for the amd64 architecture. -func (c *amd64Compiler) compileRem(o *wazeroir.UnionOperation) (err error) { - var vt runtimeValueType - signedInt := wazeroir.SignedInt(o.B1) - switch signedInt { - case wazeroir.SignedInt32: - err = c.performDivisionOnInts(true, true, true) - vt = runtimeValueTypeI32 - case wazeroir.SignedInt64: - err = c.performDivisionOnInts(true, false, true) - vt = runtimeValueTypeI64 - case wazeroir.SignedUint32: - err = c.performDivisionOnInts(true, true, false) - vt = runtimeValueTypeI32 - case wazeroir.SignedUint64: - err = c.performDivisionOnInts(true, false, false) - vt = runtimeValueTypeI64 - } - if err != nil { - return err - } - - // Now we have the remainder of the division result in the DX register, - // so we record it. - c.pushRuntimeValueLocationOnRegister(amd64.RegDX, vt) - return -} - -// performDivisionOnInts emits the instructions to do divisions on top two integers on the stack -// via DIV (unsigned div) and IDIV (signed div) instructions. -// See the following explanation of these instructions' semantics from https://www.lri.fr/~filliatr/ens/compil/x86-64.pdf -// -// >> Division requires special arrangements: idiv (signed) and div (unsigned) operate on a 2n-byte dividend and -// >> an n-byte divisor to produce an n-byte quotient and n-byte remainder. The dividend always lives in a fixed pair of -// >> registers (%edx and %eax for the 32-bit case; %rdx and %rax for the 64-bit case); the divisor is specified as the -// >> source operand in the instruction. The quotient goes in %eax (resp. %rax); the remainder in %edx (resp. %rdx). For -// >> signed division, the cltd (resp. ctqo) instruction is used to prepare %edx (resp. %rdx) with the sign extension of -// >> %eax (resp. %rax). For example, if a,b, c are memory locations holding quad words, then we could set c = a/b -// >> using the sequence: movq a(%rip), %rax; ctqo; idivq b(%rip); movq %rax, c(%rip). -// -// tl;dr is that the division result is placed in AX and DX registers after instructions emitted by this function -// where AX holds the quotient while DX the remainder of the division result. -func (c *amd64Compiler) performDivisionOnInts(isRem, is32Bit, signed bool) error { - const ( - quotientRegister = amd64.RegAX - remainderRegister = amd64.RegDX - ) - - if err := c.maybeCompileMoveTopConditionalToGeneralPurposeRegister(); err != nil { - return err - } - - // Ensures that previous values on these registers are saved to memory. - c.onValueReleaseRegisterToStack(quotientRegister) - c.onValueReleaseRegisterToStack(remainderRegister) - - // In order to ensure x2 is placed on a temporary register for x2 value other than AX and DX, - // we mark them as used here. - c.locationStack.markRegisterUsed(quotientRegister) - c.locationStack.markRegisterUsed(remainderRegister) - - // Ensure that x2 is placed on a register which is not either AX or DX. - x2 := c.locationStack.pop() - if err := c.compileEnsureOnRegister(x2); err != nil { - return err - } - - // Now we successfully place x2 on a temp register, so we no longer need to - // mark these registers used. - c.locationStack.markRegisterUnused(quotientRegister) - c.locationStack.markRegisterUnused(remainderRegister) - - // Check if the x2 equals zero. - if is32Bit { - c.assembler.CompileRegisterToRegister(amd64.TESTL, x2.register, x2.register) - } else { - c.assembler.CompileRegisterToRegister(amd64.TESTQ, x2.register, x2.register) - } - - // Skipped if the divisor is nonzero. - c.compileMaybeExitFromNativeCode(amd64.JNE, nativeCallStatusIntegerDivisionByZero) - - // next, we ensure that x1 is placed on AX. - x1 := c.locationStack.pop() - if x1.onRegister() && x1.register != quotientRegister { - // Move x1 to quotientRegister. - if is32Bit { - c.assembler.CompileRegisterToRegister(amd64.MOVL, x1.register, quotientRegister) - } else { - c.assembler.CompileRegisterToRegister(amd64.MOVQ, x1.register, quotientRegister) - } - c.locationStack.markRegisterUnused(x1.register) - x1.setRegister(quotientRegister) - } else if x1.onStack() { - x1.setRegister(quotientRegister) - c.compileLoadValueOnStackToRegister(x1) - } - - // Note: at this point, x1 is placed on AX, x2 is on a register which is not AX or DX. - - isSignedRem := isRem && signed - isSignedDiv := !isRem && signed - var signedRemMinusOneDivisorJmp asm.Node - if isSignedRem { - // If this is for getting remainder of signed division, - // we have to treat the special case where the divisor equals -1. - // For example, if this is 32-bit case, the result of (-2^31) / -1 equals (quotient=2^31, remainder=0) - // where quotient doesn't fit in the 32-bit range whose maximum is 2^31-1. - // x86 in this case cause floating point exception, but according to the Wasm spec - // if the divisor equals -1, the result must be zero (not undefined!) as opposed to be "undefined" - // for divisions on (-2^31) / -1 where we do not need to emit the special branches. - // For detail, please refer to https://stackoverflow.com/questions/56303282/why-idiv-with-1-causes-floating-point-exception - - // First we store zero into the remainder result register (DX) and compare the divisor with -1. - if is32Bit { - c.assembler.CompileRegisterToRegister(amd64.XORL, remainderRegister, remainderRegister) - c.assembler.CompileRegisterToConst(amd64.CMPL, x2.register, -1) - } else { - c.assembler.CompileRegisterToRegister(amd64.XORQ, remainderRegister, remainderRegister) - c.assembler.CompileRegisterToConst(amd64.CMPQ, x2.register, -1) - } - - // If it equals minus one, we skip the normal case. - signedRemMinusOneDivisorJmp = c.assembler.CompileJump(amd64.JEQ) - } else if isSignedDiv { - // For signed division, we have to have branches for "math.MinInt{32,64} / -1" - // case which results in the floating point exception via division error as - // the resulting value exceeds the maximum of signed int. - - // First we compare the division with -1. - if is32Bit { - c.assembler.CompileRegisterToConst(amd64.CMPL, x2.register, -1) - } else { - c.assembler.CompileRegisterToConst(amd64.CMPQ, x2.register, -1) - } - - // If it doesn't equal minus one, we jump to the normal case. - nonMinusOneDivisorJmp := c.assembler.CompileJump(amd64.JNE) - - // next we check if the quotient is the most negative value for the signed integer. - // That means whether or not we try to do (math.MinInt32 / -1) or (math.MinInt64 / -1) respectively. - if is32Bit { - if err := c.assembler.CompileRegisterToStaticConst(amd64.CMPL, x1.register, c.minimum32BitSignedInt); err != nil { - return err - } - } else { - if err := c.assembler.CompileRegisterToStaticConst(amd64.CMPQ, x1.register, c.minimum64BitSignedInt); err != nil { - return err - } - } - - // Trap if we are trying to do (math.MinInt32 / -1) or (math.MinInt64 / -1), - // as that is the overflow in division as the result becomes 2^31 which is larger than - // the maximum of signed 32-bit int (2^31-1). - c.compileMaybeExitFromNativeCode(amd64.JNE, nativeCallStatusIntegerOverflow) - // Set the normal case's jump target. - c.assembler.SetJumpTargetOnNext(nonMinusOneDivisorJmp) - } - - // Now ready to emit the div instruction. - // Since the div instructions takes 2n byte dividend placed in DX:AX registers... - // * signed case - we need to sign-extend the dividend into DX register via CDQ (32 bit) or CQO (64 bit). - // * unsigned case - we need to zero DX register via "XOR DX DX" - if is32Bit && signed { - // Emit sign-extension to have 64 bit dividend over DX and AX registers. - c.assembler.CompileStandAlone(amd64.CDQ) - c.assembler.CompileRegisterToNone(amd64.IDIVL, x2.register) - } else if is32Bit && !signed { - // Zeros DX register to have 64 bit dividend over DX and AX registers. - c.assembler.CompileRegisterToRegister(amd64.XORQ, amd64.RegDX, amd64.RegDX) - c.assembler.CompileRegisterToNone(amd64.DIVL, x2.register) - } else if !is32Bit && signed { - // Emits sign-extension to have 128 bit dividend over DX and AX registers. - c.assembler.CompileStandAlone(amd64.CQO) - c.assembler.CompileRegisterToNone(amd64.IDIVQ, x2.register) - } else if !is32Bit && !signed { - // Zeros DX register to have 128 bit dividend over DX and AX registers. - c.assembler.CompileRegisterToRegister(amd64.XORQ, amd64.RegDX, amd64.RegDX) - c.assembler.CompileRegisterToNone(amd64.DIVQ, x2.register) - } - - // If this is signed rem instruction, we must set the jump target of - // the exit jump from division -1 case towards the next instruction. - if signedRemMinusOneDivisorJmp != nil { - c.assembler.SetJumpTargetOnNext(signedRemMinusOneDivisorJmp) - } - - // We mark them as unused so that we can push one of them onto the location stack at call sites. - c.locationStack.markRegisterUnused(remainderRegister) - c.locationStack.markRegisterUnused(quotientRegister) - c.locationStack.markRegisterUnused(x2.register) - return nil -} - -// compileDivForFloats emits the instructions to perform division -// on the top two values of float type on the stack, placing the result back onto the stack. -// For example, stack [..., 1.0, 4.0] results in [..., 0.25]. -func (c *amd64Compiler) compileDivForFloats(is32Bit bool) error { - if is32Bit { - return c.compileSimpleBinaryOp(amd64.DIVSS) - } else { - return c.compileSimpleBinaryOp(amd64.DIVSD) - } -} - -// compileAnd implements compiler.compileAnd for the amd64 architecture. -func (c *amd64Compiler) compileAnd(o *wazeroir.UnionOperation) (err error) { - unsignedInt := wazeroir.UnsignedInt(o.B1) - switch unsignedInt { - case wazeroir.UnsignedInt32: - err = c.compileSimpleBinaryOp(amd64.ANDL) - case wazeroir.UnsignedInt64: - err = c.compileSimpleBinaryOp(amd64.ANDQ) - } - return -} - -// compileOr implements compiler.compileOr for the amd64 architecture. -func (c *amd64Compiler) compileOr(o *wazeroir.UnionOperation) (err error) { - unsignedInt := wazeroir.UnsignedInt(o.B1) - switch unsignedInt { - case wazeroir.UnsignedInt32: - err = c.compileSimpleBinaryOp(amd64.ORL) - case wazeroir.UnsignedInt64: - err = c.compileSimpleBinaryOp(amd64.ORQ) - } - return -} - -// compileXor implements compiler.compileXor for the amd64 architecture. -func (c *amd64Compiler) compileXor(o *wazeroir.UnionOperation) (err error) { - unsignedInt := wazeroir.UnsignedInt(o.B1) - switch unsignedInt { - case wazeroir.UnsignedInt32: - err = c.compileSimpleBinaryOp(amd64.XORL) - case wazeroir.UnsignedInt64: - err = c.compileSimpleBinaryOp(amd64.XORQ) - } - return -} - -// compileSimpleBinaryOp emits instructions to pop two values from the stack -// and perform the given instruction on these two values and push the result -// onto the stack. -func (c *amd64Compiler) compileSimpleBinaryOp(instruction asm.Instruction) error { - x2 := c.locationStack.pop() - if err := c.compileEnsureOnRegister(x2); err != nil { - return err - } - - x1 := c.locationStack.pop() - if err := c.compileEnsureOnRegister(x1); err != nil { - return err - } - - c.assembler.CompileRegisterToRegister(instruction, x2.register, x1.register) - - // We consumed x2 register after the operation here, - // so we release it. - c.locationStack.releaseRegister(x2) - - // We already stored the result in the register used by x1 - // so we record it. - c.locationStack.markRegisterUnused(x1.register) - c.pushRuntimeValueLocationOnRegister(x1.register, x1.valueType) - return nil -} - -// compileShl implements compiler.compileShl for the amd64 architecture. -func (c *amd64Compiler) compileShl(o *wazeroir.UnionOperation) (err error) { - unsignedInt := wazeroir.UnsignedInt(o.B1) - switch unsignedInt { - case wazeroir.UnsignedInt32: - err = c.compileShiftOp(amd64.SHLL, false) - case wazeroir.UnsignedInt64: - err = c.compileShiftOp(amd64.SHLQ, true) - } - return -} - -// compileShr implements compiler.compileShr for the amd64 architecture. -func (c *amd64Compiler) compileShr(o *wazeroir.UnionOperation) (err error) { - signedInt := wazeroir.SignedInt(o.B1) - switch signedInt { - case wazeroir.SignedInt32: - err = c.compileShiftOp(amd64.SARL, true) - case wazeroir.SignedInt64: - err = c.compileShiftOp(amd64.SARQ, false) - case wazeroir.SignedUint32: - err = c.compileShiftOp(amd64.SHRL, true) - case wazeroir.SignedUint64: - err = c.compileShiftOp(amd64.SHRQ, false) - } - return -} - -// compileRotl implements compiler.compileRotl for the amd64 architecture. -func (c *amd64Compiler) compileRotl(o *wazeroir.UnionOperation) (err error) { - unsignedInt := wazeroir.UnsignedInt(o.B1) - switch unsignedInt { - case wazeroir.UnsignedInt32: - err = c.compileShiftOp(amd64.ROLL, true) - case wazeroir.UnsignedInt64: - err = c.compileShiftOp(amd64.ROLQ, false) - } - return -} - -// compileRotr implements compiler.compileRotr for the amd64 architecture. -func (c *amd64Compiler) compileRotr(o *wazeroir.UnionOperation) (err error) { - unsignedInt := wazeroir.UnsignedInt(o.B1) - switch unsignedInt { - case wazeroir.UnsignedInt32: - err = c.compileShiftOp(amd64.RORL, true) - case wazeroir.UnsignedInt64: - err = c.compileShiftOp(amd64.RORQ, false) - } - return -} - -// compileShiftOp adds instructions for shift operations (SHR, SHL, ROTR, ROTL) -// where we have to place the second value (shift counts) on the CX register. -func (c *amd64Compiler) compileShiftOp(instruction asm.Instruction, is32Bit bool) error { - if err := c.maybeCompileMoveTopConditionalToGeneralPurposeRegister(); err != nil { - return err - } - - x2 := c.locationStack.pop() - - // Ensures that x2 (holding shift counts) is placed on the CX register. - const shiftCountRegister = amd64.RegCX - if (x2.onRegister() && x2.register != shiftCountRegister) || x2.onStack() { - // If another value lives on the CX register, we release it to the stack. - c.onValueReleaseRegisterToStack(shiftCountRegister) - - if x2.onRegister() { - x2r := x2.register - // If x2 lives on a register, we move the value to CX. - if is32Bit { - c.assembler.CompileRegisterToRegister(amd64.MOVL, x2r, shiftCountRegister) - } else { - c.assembler.CompileRegisterToRegister(amd64.MOVQ, x2r, shiftCountRegister) - } - // We no longer place any value on the original register, so we record it. - c.locationStack.markRegisterUnused(x2r) - } else { - // If it is on stack, we just move the memory allocated value to the CX register. - x2.setRegister(shiftCountRegister) - c.compileLoadValueOnStackToRegister(x2) - } - c.locationStack.markRegisterUsed(shiftCountRegister) - } - - x1 := c.locationStack.peek() // Note this is peek! - x1r := x1.register - - if x1.onRegister() { - c.assembler.CompileRegisterToRegister(instruction, shiftCountRegister, x1r) - } else { - // Shift target can be placed on a memory location. - // Note: stack pointers are ensured not to exceed 2^27 so this offset never exceeds 32-bit range. - c.assembler.CompileRegisterToMemory(instruction, shiftCountRegister, amd64ReservedRegisterForStackBasePointerAddress, int64(x1.stackPointer)*8) - } - - // We consumed x2 register after the operation here, - // so we release it. - c.locationStack.markRegisterUnused(shiftCountRegister) - return nil -} - -// compileAbs implements compiler.compileAbs for the amd64 architecture. -// -// See the following discussions for how we could take the abs of floats on x86 assembly. -// https://stackoverflow.com/questions/32408665/fastest-way-to-compute-absolute-value-using-sse/32422471#32422471 -// https://stackoverflow.com/questions/44630015/how-would-fabsdouble-be-implemented-on-x86-is-it-an-expensive-operation -func (c *amd64Compiler) compileAbs(o *wazeroir.UnionOperation) (err error) { - target := c.locationStack.peek() // Note this is peek! - if err = c.compileEnsureOnRegister(target); err != nil { - return err - } - - // First shift left by one to clear the sign bit, and then shift right by one. - if wazeroir.Float(o.B1) == wazeroir.Float32 { - c.assembler.CompileConstToRegister(amd64.PSLLD, 1, target.register) - c.assembler.CompileConstToRegister(amd64.PSRLD, 1, target.register) - } else { - c.assembler.CompileConstToRegister(amd64.PSLLQ, 1, target.register) - c.assembler.CompileConstToRegister(amd64.PSRLQ, 1, target.register) - } - return nil -} - -// compileNeg implements compiler.compileNeg for the amd64 architecture. -func (c *amd64Compiler) compileNeg(o *wazeroir.UnionOperation) (err error) { - target := c.locationStack.peek() // Note this is peek! - if err := c.compileEnsureOnRegister(target); err != nil { - return err - } - - tmpReg, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - - // First we move the sign-bit mask (placed in memory) to the tmp register, - // since we cannot take XOR directly with float reg and const. - // And then negate the value by XOR it with the sign-bit mask. - if wazeroir.Float(o.B1) == wazeroir.Float32 { - err = c.assembler.CompileStaticConstToRegister(amd64.MOVL, c.float32SignBitMask, tmpReg) - if err != nil { - return err - } - c.assembler.CompileRegisterToRegister(amd64.XORPS, tmpReg, target.register) - } else { - err = c.assembler.CompileStaticConstToRegister(amd64.MOVQ, c.float64SignBitMask, tmpReg) - if err != nil { - return err - } - c.assembler.CompileRegisterToRegister(amd64.XORPD, tmpReg, target.register) - } - return nil -} - -// compileCeil implements compiler.compileCeil for the amd64 architecture. -func (c *amd64Compiler) compileCeil(o *wazeroir.UnionOperation) (err error) { - // Internally, ceil can be performed via ROUND instruction with 0x02 mode. - // See https://android.googlesource.com/platform/bionic/+/882b8af/libm/x86_64/ceilf.S for example. - return c.compileRoundInstruction(wazeroir.Float(o.B1) == wazeroir.Float32, 0x02) -} - -// compileFloor implements compiler.compileFloor for the amd64 architecture. -func (c *amd64Compiler) compileFloor(o *wazeroir.UnionOperation) (err error) { - // Internally, floor can be performed via ROUND instruction with 0x01 mode. - // See https://android.googlesource.com/platform/bionic/+/882b8af/libm/x86_64/floorf.S for example. - return c.compileRoundInstruction(wazeroir.Float(o.B1) == wazeroir.Float32, 0x01) -} - -// compileTrunc implements compiler.compileTrunc for the amd64 architecture. -func (c *amd64Compiler) compileTrunc(o *wazeroir.UnionOperation) error { - // Internally, trunc can be performed via ROUND instruction with 0x03 mode. - // See https://android.googlesource.com/platform/bionic/+/882b8af/libm/x86_64/truncf.S for example. - return c.compileRoundInstruction(wazeroir.Float(o.B1) == wazeroir.Float32, 0x03) -} - -// compileNearest implements compiler.compileNearest for the amd64 architecture. -func (c *amd64Compiler) compileNearest(o *wazeroir.UnionOperation) error { - // Nearest can be performed via ROUND instruction with 0x00 mode. - return c.compileRoundInstruction(wazeroir.Float(o.B1) == wazeroir.Float32, 0x00) -} - -func (c *amd64Compiler) compileRoundInstruction(is32Bit bool, mode int64) error { - target := c.locationStack.peek() // Note this is peek! - if err := c.compileEnsureOnRegister(target); err != nil { - return err - } - - if is32Bit { - c.assembler.CompileRegisterToRegisterWithArg(amd64.ROUNDSS, target.register, target.register, byte(mode)) - } else { - c.assembler.CompileRegisterToRegisterWithArg(amd64.ROUNDSD, target.register, target.register, byte(mode)) - } - return nil -} - -// compileMin implements compiler.compileMin for the amd64 architecture. -func (c *amd64Compiler) compileMin(o *wazeroir.UnionOperation) error { - is32Bit := wazeroir.Float(o.B1) == wazeroir.Float32 - if is32Bit { - return c.compileMinOrMax(is32Bit, true, amd64.MINSS) - } else { - return c.compileMinOrMax(is32Bit, true, amd64.MINSD) - } -} - -// compileMax implements compiler.compileMax for the amd64 architecture. -func (c *amd64Compiler) compileMax(o *wazeroir.UnionOperation) error { - is32Bit := wazeroir.Float(o.B1) == wazeroir.Float32 - if is32Bit { - return c.compileMinOrMax(is32Bit, false, amd64.MAXSS) - } else { - return c.compileMinOrMax(is32Bit, false, amd64.MAXSD) - } -} - -// emitMinOrMax adds instructions to pop two values from the stack, and push back either minimum or -// minimum of these two values onto the stack according to the minOrMaxInstruction argument. -// minOrMaxInstruction must be one of MAXSS, MAXSD, MINSS or MINSD. -// Note: These native min/max instructions are almost compatible with min/max in the Wasm specification, -// but it is slightly different with respect to the NaN handling. -// Native min/max instructions return non-NaN value if exactly one of target values -// is NaN. For example native_{min,max}(5.0, NaN) returns always 5.0, not NaN. -// However, WebAssembly specifies that min/max must always return NaN if one of values is NaN. -// Therefore, in this function, we have to add conditional jumps to check if one of values is NaN before -// the native min/max, which is why we cannot simply emit a native min/max instruction here. -// -// For the semantics, see wazeroir.Min and wazeroir.Max for detail. -func (c *amd64Compiler) compileMinOrMax(is32Bit, isMin bool, minOrMaxInstruction asm.Instruction) error { - x2 := c.locationStack.pop() - if err := c.compileEnsureOnRegister(x2); err != nil { - return err - } - x1 := c.locationStack.pop() - if err := c.compileEnsureOnRegister(x1); err != nil { - return err - } - - // Check if this is (either x1 or x2 is NaN) or (x1 equals x2) case - if is32Bit { - c.assembler.CompileRegisterToRegister(amd64.UCOMISS, x2.register, x1.register) - } else { - c.assembler.CompileRegisterToRegister(amd64.UCOMISD, x2.register, x1.register) - } - - // At this point, we have the three cases of conditional flags below - // (See https://www.felixcloutier.com/x86/ucomiss#operation for detail.) - // - // 1) Two values are NaN-free and different: All flags are cleared. - // 2) Two values are NaN-free and equal: Only ZF flags is set. - // 3) One of Two values is NaN: ZF, PF and CF flags are set. - - // Jump instruction to handle 1) case by checking the ZF flag - // as ZF is only set for 2) and 3) cases. - nanFreeOrDiffJump := c.assembler.CompileJump(amd64.JNE) - - // Start handling 2) and 3). - - // Jump if one of two values is NaN by checking the parity flag (PF). - includeNaNJmp := c.assembler.CompileJump(amd64.JPS) - - // Start handling 2). - - // Before we exit this case, we have to ensure that positive zero (or negative zero for min instruction) is - // returned if two values are positive and negative zeros. - var inst asm.Instruction - switch { - case is32Bit && isMin: - inst = amd64.ORPS - case !is32Bit && isMin: - inst = amd64.ORPD - case is32Bit && !isMin: - inst = amd64.ANDPS - case !is32Bit && !isMin: - inst = amd64.ANDPD - } - c.assembler.CompileRegisterToRegister(inst, x2.register, x1.register) - - sameExitJmp := c.assembler.CompileJump(amd64.JMP) - - // start handling 3). - c.assembler.SetJumpTargetOnNext(includeNaNJmp) - - // We emit the ADD instruction to produce the NaN in x1. - if is32Bit { - c.assembler.CompileRegisterToRegister(amd64.ADDSS, x2.register, x1.register) - } else { - c.assembler.CompileRegisterToRegister(amd64.ADDSD, x2.register, x1.register) - } - - // Exit from the NaN case branch. - nanExitJmp := c.assembler.CompileJump(amd64.JMP) - - // Start handling 1). - c.assembler.SetJumpTargetOnNext(nanFreeOrDiffJump) - - // Now handle the NaN-free and different values case. - c.assembler.CompileRegisterToRegister(minOrMaxInstruction, x2.register, x1.register) - - // Set the jump target of 1) and 2) cases to the next instruction after 3) case. - c.assembler.SetJumpTargetOnNext(nanExitJmp) - c.assembler.SetJumpTargetOnNext(sameExitJmp) - - // Record that we consumed the x2 and placed the minOrMax result in the x1's register. - c.locationStack.markRegisterUnused(x2.register) - c.locationStack.markRegisterUnused(x1.register) - c.pushRuntimeValueLocationOnRegister(x1.register, x1.valueType) - return nil -} - -// compileCopysign implements compiler.compileCopysign for the amd64 architecture. -func (c *amd64Compiler) compileCopysign(o *wazeroir.UnionOperation) error { - is32Bit := wazeroir.Float(o.B1) == wazeroir.Float32 - - x2 := c.locationStack.pop() - if err := c.compileEnsureOnRegister(x2); err != nil { - return err - } - x1 := c.locationStack.pop() - if err := c.compileEnsureOnRegister(x1); err != nil { - return err - } - tmpReg, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - - // Move the rest bit mask to the temp register. - if is32Bit { - err = c.assembler.CompileStaticConstToRegister(amd64.MOVL, c.float32RestBitMask, tmpReg) - } else { - err = c.assembler.CompileStaticConstToRegister(amd64.MOVQ, c.float64RestBitMask, tmpReg) - } - if err != nil { - return err - } - - // Clear the sign bit of x1 via AND with the mask. - if is32Bit { - c.assembler.CompileRegisterToRegister(amd64.ANDPS, tmpReg, x1.register) - } else { - c.assembler.CompileRegisterToRegister(amd64.ANDPD, tmpReg, x1.register) - } - - // Move the sign bit mask to the temp register. - if is32Bit { - err = c.assembler.CompileStaticConstToRegister(amd64.MOVL, c.float32SignBitMask, tmpReg) - } else { - err = c.assembler.CompileStaticConstToRegister(amd64.MOVQ, c.float64SignBitMask, tmpReg) - } - if err != nil { - return err - } - - // Clear the non-sign bits of x2 via AND with the mask. - if is32Bit { - c.assembler.CompileRegisterToRegister(amd64.ANDPS, tmpReg, x2.register) - } else { - c.assembler.CompileRegisterToRegister(amd64.ANDPD, tmpReg, x2.register) - } - - // Finally, copy the sign bit of x2 to x1. - if is32Bit { - c.assembler.CompileRegisterToRegister(amd64.ORPS, x2.register, x1.register) - } else { - c.assembler.CompileRegisterToRegister(amd64.ORPD, x2.register, x1.register) - } - - // Record that we consumed the x2 and placed the copysign result in the x1's register. - c.locationStack.markRegisterUnused(x2.register) - c.locationStack.markRegisterUnused(x1.register) - c.pushRuntimeValueLocationOnRegister(x1.register, x1.valueType) - return nil -} - -// compileSqrt implements compiler.compileSqrt for the amd64 architecture. -func (c *amd64Compiler) compileSqrt(o *wazeroir.UnionOperation) error { - target := c.locationStack.peek() // Note this is peek! - if err := c.compileEnsureOnRegister(target); err != nil { - return err - } - if wazeroir.Float(o.B1) == wazeroir.Float32 { - c.assembler.CompileRegisterToRegister(amd64.SQRTSS, target.register, target.register) - } else { - c.assembler.CompileRegisterToRegister(amd64.SQRTSD, target.register, target.register) - } - return nil -} - -// compileI32WrapFromI64 implements compiler.compileI32WrapFromI64 for the amd64 architecture. -func (c *amd64Compiler) compileI32WrapFromI64() error { - target := c.locationStack.peek() // Note this is peek! - if err := c.compileEnsureOnRegister(target); err != nil { - return err - } - c.assembler.CompileRegisterToRegister(amd64.MOVL, target.register, target.register) - target.valueType = runtimeValueTypeI32 - return nil -} - -// compileITruncFromF implements compiler.compileITruncFromF for the amd64 architecture. -// -// Note: in the following implementation, we use CVTSS2SI and CVTSD2SI to convert floats to signed integers. -// According to the Intel manual ([1],[2]), if the source float value is either +-Inf or NaN, or it exceeds representative ranges -// of target signed integer, then the instruction returns "masked" response float32SignBitMask (or float64SignBitMask for 64 bit case). -// [1] Chapter 11.5.2, SIMD Floating-Point Exception Conditions in "Vol 1, Intel® 64 and IA-32 Architectures Manual" -// -// https://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-developer-vol-1-manual.html -// -// [2] https://xem.github.io/minix86/manual/intel-x86-and-64-manual-vol1/o_7281d5ea06a5b67a-268.html -func (c *amd64Compiler) compileITruncFromF(o *wazeroir.UnionOperation) (err error) { - inputType := wazeroir.Float(o.B1) - outputType := wazeroir.SignedInt(o.B2) - nonTrapping := o.B3 - if inputType == wazeroir.Float32 && outputType == wazeroir.SignedInt32 { - err = c.emitSignedI32TruncFromFloat(true, nonTrapping) - } else if inputType == wazeroir.Float32 && outputType == wazeroir.SignedInt64 { - err = c.emitSignedI64TruncFromFloat(true, nonTrapping) - } else if inputType == wazeroir.Float64 && outputType == wazeroir.SignedInt32 { - err = c.emitSignedI32TruncFromFloat(false, nonTrapping) - } else if inputType == wazeroir.Float64 && outputType == wazeroir.SignedInt64 { - err = c.emitSignedI64TruncFromFloat(false, nonTrapping) - } else if inputType == wazeroir.Float32 && outputType == wazeroir.SignedUint32 { - err = c.emitUnsignedI32TruncFromFloat(true, nonTrapping) - } else if inputType == wazeroir.Float32 && outputType == wazeroir.SignedUint64 { - err = c.emitUnsignedI64TruncFromFloat(true, nonTrapping) - } else if inputType == wazeroir.Float64 && outputType == wazeroir.SignedUint32 { - err = c.emitUnsignedI32TruncFromFloat(false, nonTrapping) - } else if inputType == wazeroir.Float64 && outputType == wazeroir.SignedUint64 { - err = c.emitUnsignedI64TruncFromFloat(false, nonTrapping) - } - return -} - -// emitUnsignedI32TruncFromFloat implements compileITruncFromF when the destination type is a 32-bit unsigned integer. -func (c *amd64Compiler) emitUnsignedI32TruncFromFloat(isFloat32Bit, nonTrapping bool) error { - source := c.locationStack.pop() - if err := c.compileEnsureOnRegister(source); err != nil { - return err - } - - result, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - - // First, we check the source float value is above or equal math.MaxInt32+1. - if isFloat32Bit { - err = c.assembler.CompileStaticConstToRegister(amd64.UCOMISS, c.float32ForMaximumSigned32bitIntPlusOne, source.register) - } else { - err = c.assembler.CompileStaticConstToRegister(amd64.UCOMISD, c.float64ForMaximumSigned32bitIntPlusOne, source.register) - } - if err != nil { - return err - } - - // Check the parity flag (set when the value is NaN), and if it is set, we should raise an exception. - var nonTrappingNaNJump asm.Node - if nonTrapping { - jmpIfNotNaN := c.assembler.CompileJump(amd64.JPC) // jump if parity is not set. - // In non trapping case, NaN is casted as zero. - // Zero out the result register by XOR itsself. - c.assembler.CompileRegisterToRegister(amd64.XORL, result, result) - nonTrappingNaNJump = c.assembler.CompileJump(amd64.JMP) - c.assembler.SetJumpTargetOnNext(jmpIfNotNaN) - } else { - c.compileMaybeExitFromNativeCode(amd64.JPC, nativeCallStatusCodeInvalidFloatToIntConversion) - } - - // Jump if the source float value is above or equal math.MaxInt32+1. - jmpAboveOrEqualMaxIn32PlusOne := c.assembler.CompileJump(amd64.JCC) - - // next we convert the value as a signed integer. - if isFloat32Bit { - c.assembler.CompileRegisterToRegister(amd64.CVTTSS2SL, source.register, result) - } else { - c.assembler.CompileRegisterToRegister(amd64.CVTTSD2SL, source.register, result) - } - - // Then if the result is minus, it is invalid conversion from minus float (incl. -Inf). - c.assembler.CompileRegisterToRegister(amd64.TESTL, result, result) - - var nonTrappingMinusJump asm.Node - if nonTrapping { - jmpIfNotMinusOrMinusInf := c.assembler.CompileJump(amd64.JPL) - // In non trapping case, the minus value is casted as zero. - // Zero out the result register by XOR itsself. - c.assembler.CompileRegisterToRegister(amd64.XORL, result, result) - nonTrappingMinusJump = c.assembler.CompileJump(amd64.JMP) - c.assembler.SetJumpTargetOnNext(jmpIfNotMinusOrMinusInf) - } else { - c.compileMaybeExitFromNativeCode(amd64.JPL, nativeCallStatusIntegerOverflow) - } - - // Otherwise, the values is valid. - okJmpForLessThanMaxInt32PlusOne := c.assembler.CompileJump(amd64.JMP) - - // Now, start handling the case where the original float value is above or equal math.MaxInt32+1. - // - // First, we subtract the math.MaxInt32+1 from the original value so it can fit in signed 32-bit integer. - c.assembler.SetJumpTargetOnNext(jmpAboveOrEqualMaxIn32PlusOne) - if isFloat32Bit { - err = c.assembler.CompileStaticConstToRegister(amd64.SUBSS, c.float32ForMaximumSigned32bitIntPlusOne, source.register) - } else { - err = c.assembler.CompileStaticConstToRegister(amd64.SUBSD, c.float64ForMaximumSigned32bitIntPlusOne, source.register) - } - if err != nil { - return err - } - - // Then, convert the subtracted value as a signed 32-bit integer. - if isFloat32Bit { - c.assembler.CompileRegisterToRegister(amd64.CVTTSS2SL, source.register, result) - } else { - c.assembler.CompileRegisterToRegister(amd64.CVTTSD2SL, source.register, result) - } - - // next, we have to check if the value is from NaN, +Inf. - // NaN or +Inf cases result in 0x8000_0000 according to the semantics of conversion, - // This means we check if the result int value is minus or not. - c.assembler.CompileRegisterToRegister(amd64.TESTL, result, result) - - // If the result is minus, the conversion is invalid (from NaN or +Inf) - var nonTrappingAboveOrEqualMaxInt32PlusOne asm.Node - if nonTrapping { - jmpIfNotPlusInf := c.assembler.CompileJump(amd64.JPL) - err = c.assembler.CompileStaticConstToRegister(amd64.MOVL, c.maximum32BitUnsignedInt, result) - if err != nil { - return err - } - nonTrappingAboveOrEqualMaxInt32PlusOne = c.assembler.CompileJump(amd64.JMP) - c.assembler.SetJumpTargetOnNext(jmpIfNotPlusInf) - } else { - c.compileMaybeExitFromNativeCode(amd64.JPL, nativeCallStatusIntegerOverflow) - } - - // Otherwise, we successfully converted the source float minus (math.MaxInt32+1) to int. - // So, we retrieve the original source float value by adding the sign mask. - if err = c.assembler.CompileStaticConstToRegister(amd64.ADDL, c.float32SignBitMask, result); err != nil { - return err - } - - // We jump to the next instructions for valid cases. - c.assembler.SetJumpTargetOnNext(okJmpForLessThanMaxInt32PlusOne) - if nonTrapping { - c.assembler.SetJumpTargetOnNext(nonTrappingAboveOrEqualMaxInt32PlusOne) - c.assembler.SetJumpTargetOnNext(nonTrappingMinusJump) - c.assembler.SetJumpTargetOnNext(nonTrappingNaNJump) - } - - // We consumed the source's register and placed the conversion result - // in the result register. - c.locationStack.markRegisterUnused(source.register) - c.pushRuntimeValueLocationOnRegister(result, runtimeValueTypeI32) - return nil -} - -// emitUnsignedI32TruncFromFloat implements compileITruncFromF when the destination type is a 64-bit unsigned integer. -func (c *amd64Compiler) emitUnsignedI64TruncFromFloat(isFloat32Bit, nonTrapping bool) error { - source := c.locationStack.pop() - if err := c.compileEnsureOnRegister(source); err != nil { - return err - } - - result, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - - // First, we check the source float value is above or equal math.MaxInt64+1. - if isFloat32Bit { - err = c.assembler.CompileStaticConstToRegister(amd64.UCOMISS, c.float32ForMaximumSigned64bitIntPlusOne, source.register) - } else { - err = c.assembler.CompileStaticConstToRegister(amd64.UCOMISD, c.float64ForMaximumSigned64bitIntPlusOne, source.register) - } - if err != nil { - return err - } - - // Check the parity flag (set when the value is NaN), and if it is set, we should raise an exception. - var nonTrappingNaNJump asm.Node - if nonTrapping { - jmpIfNotNaN := c.assembler.CompileJump(amd64.JPC) // jump if parity is c.not set. - // In non trapping case, NaN is casted as zero. - // Zero out the result register by XOR itsself. - c.assembler.CompileRegisterToRegister(amd64.XORQ, result, result) - nonTrappingNaNJump = c.assembler.CompileJump(amd64.JMP) - c.assembler.SetJumpTargetOnNext(jmpIfNotNaN) - } else { - c.compileMaybeExitFromNativeCode(amd64.JPC, nativeCallStatusCodeInvalidFloatToIntConversion) - } - - // Jump if the source float values is above or equal math.MaxInt64+1. - jmpAboveOrEqualMaxIn32PlusOne := c.assembler.CompileJump(amd64.JCC) - - // next we convert the value as a signed integer. - if isFloat32Bit { - c.assembler.CompileRegisterToRegister(amd64.CVTTSS2SQ, source.register, result) - } else { - c.assembler.CompileRegisterToRegister(amd64.CVTTSD2SQ, source.register, result) - } - - // Then if the result is minus, it is invalid conversion from minus float (incl. -Inf). - c.assembler.CompileRegisterToRegister(amd64.TESTQ, result, result) - - var nonTrappingMinusJump asm.Node - if nonTrapping { - jmpIfNotMinusOrMinusInf := c.assembler.CompileJump(amd64.JPL) - // In non trapping case, the minus value is casted as zero. - // Zero out the result register by XOR itsself. - c.assembler.CompileRegisterToRegister(amd64.XORQ, result, result) - nonTrappingMinusJump = c.assembler.CompileJump(amd64.JMP) - c.assembler.SetJumpTargetOnNext(jmpIfNotMinusOrMinusInf) - } else { - c.compileMaybeExitFromNativeCode(amd64.JPL, nativeCallStatusIntegerOverflow) - } - - // Otherwise, the values is valid. - okJmpForLessThanMaxInt64PlusOne := c.assembler.CompileJump(amd64.JMP) - - // Now, start handling the case where the original float value is above or equal math.MaxInt64+1. - // - // First, we subtract the math.MaxInt64+1 from the original value so it can fit in signed 64-bit integer. - c.assembler.SetJumpTargetOnNext(jmpAboveOrEqualMaxIn32PlusOne) - if isFloat32Bit { - err = c.assembler.CompileStaticConstToRegister(amd64.SUBSS, c.float32ForMaximumSigned64bitIntPlusOne, source.register) - } else { - err = c.assembler.CompileStaticConstToRegister(amd64.SUBSD, c.float64ForMaximumSigned64bitIntPlusOne, source.register) - } - if err != nil { - return err - } - - // Then, convert the subtracted value as a signed 64-bit integer. - if isFloat32Bit { - c.assembler.CompileRegisterToRegister(amd64.CVTTSS2SQ, source.register, result) - } else { - c.assembler.CompileRegisterToRegister(amd64.CVTTSD2SQ, source.register, result) - } - - // next, we have to check if the value is from NaN, +Inf. - // NaN or +Inf cases result in 0x8000_0000 according to the semantics of conversion, - // This means we check if the result int value is minus or not. - c.assembler.CompileRegisterToRegister(amd64.TESTQ, result, result) - - // If the result is minus, the conversion is invalid (from NaN or +Inf) - var nonTrappingAboveOrEqualMaxInt64PlusOne asm.Node - if nonTrapping { - jmpIfNotPlusInf := c.assembler.CompileJump(amd64.JPL) - err = c.assembler.CompileStaticConstToRegister(amd64.MOVQ, c.maximum64BitUnsignedInt, result) - if err != nil { - return err - } - nonTrappingAboveOrEqualMaxInt64PlusOne = c.assembler.CompileJump(amd64.JMP) - c.assembler.SetJumpTargetOnNext(jmpIfNotPlusInf) - } else { - c.compileMaybeExitFromNativeCode(amd64.JPL, nativeCallStatusIntegerOverflow) - } - - // Otherwise, we successfully converted the the source float minus (math.MaxInt64+1) to int. - // So, we retrieve the original source float value by adding the sign mask. - if err = c.assembler.CompileStaticConstToRegister(amd64.ADDQ, c.float64SignBitMask, result); err != nil { - return err - } - - // We jump to the next instructions for valid cases. - c.assembler.SetJumpTargetOnNext(okJmpForLessThanMaxInt64PlusOne) - if nonTrapping { - c.assembler.SetJumpTargetOnNext(nonTrappingAboveOrEqualMaxInt64PlusOne) - c.assembler.SetJumpTargetOnNext(nonTrappingMinusJump) - c.assembler.SetJumpTargetOnNext(nonTrappingNaNJump) - } - - // We consumed the source's register and placed the conversion result - // in the result register. - c.locationStack.markRegisterUnused(source.register) - c.pushRuntimeValueLocationOnRegister(result, runtimeValueTypeI64) - return nil -} - -// emitSignedI32TruncFromFloat implements compileITruncFromF when the destination type is a 32-bit signed integer. -func (c *amd64Compiler) emitSignedI32TruncFromFloat(isFloat32Bit, nonTrapping bool) error { - source := c.locationStack.pop() - if err := c.compileEnsureOnRegister(source); err != nil { - return err - } - - result, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - - // First we unconditionally convert source to integer via CVTTSS2SI (CVTTSD2SI for 64bit float). - if isFloat32Bit { - c.assembler.CompileRegisterToRegister(amd64.CVTTSS2SL, source.register, result) - } else { - c.assembler.CompileRegisterToRegister(amd64.CVTTSD2SL, source.register, result) - } - - // We compare the conversion result with the sign bit mask to check if it is either - // 1) the source float value is either +-Inf or NaN, or it exceeds representative ranges of 32bit signed integer, or - // 2) the source equals the minimum signed 32-bit (=-2147483648.000000) whose bit pattern is float32ForMinimumSigned32bitIntegerAddress for 32 bit float - // or float64ForMinimumSigned32bitIntegerAddress for 64bit float. - err = c.assembler.CompileStaticConstToRegister(amd64.CMPL, c.float32SignBitMask, result) - if err != nil { - return err - } - - // Otherwise, jump to exit as the result is valid. - okJmp := c.assembler.CompileJump(amd64.JNE) - - // Start handling the case of 1) and 2). - // First, check if the value is NaN. - if isFloat32Bit { - c.assembler.CompileRegisterToRegister(amd64.UCOMISS, source.register, source.register) - } else { - c.assembler.CompileRegisterToRegister(amd64.UCOMISD, source.register, source.register) - } - - // Check the parity flag (set when the value is NaN), and if it is set, we should raise an exception. - var nontrappingNanJump asm.Node - if nonTrapping { - jmpIfNotNaN := c.assembler.CompileJump(amd64.JPC) // jump if parity is not set. - // In non trapping case, NaN is casted as zero. - // Zero out the result register by XOR itsself. - c.assembler.CompileRegisterToRegister(amd64.XORL, result, result) - nontrappingNanJump = c.assembler.CompileJump(amd64.JMP) - c.assembler.SetJumpTargetOnNext(jmpIfNotNaN) - } else { - // If the value is NaN, we return the function with nativeCallStatusCodeInvalidFloatToIntConversion. - c.compileMaybeExitFromNativeCode(amd64.JPC, nativeCallStatusCodeInvalidFloatToIntConversion) - } - - // Check if the value is larger than or equal the minimum 32-bit integer value, - // meaning that the value exceeds the lower bound of 32-bit signed integer range. - if isFloat32Bit { - err = c.assembler.CompileStaticConstToRegister(amd64.UCOMISS, c.float32ForMinimumSigned32bitInteger, source.register) - } else { - err = c.assembler.CompileStaticConstToRegister(amd64.UCOMISD, c.float64ForMinimumSigned32bitInteger, source.register) - } - if err != nil { - return err - } - - if !nonTrapping { - // Trap if the value does not exceed the lower bound. - if isFloat32Bit { - c.compileMaybeExitFromNativeCode(amd64.JCC, nativeCallStatusIntegerOverflow) - } else { - c.compileMaybeExitFromNativeCode(amd64.JHI, nativeCallStatusIntegerOverflow) - } - - // At this point, the value is the minimum signed 32-bit int (=-2147483648.000000) or larger than 32-bit maximum. - // So, check if the value equals the minimum signed 32-bit int. - if isFloat32Bit { - err = c.assembler.CompileStaticConstToRegister(amd64.UCOMISS, c.fourZeros, source.register) - } else { - err = c.assembler.CompileStaticConstToRegister(amd64.UCOMISD, c.eightZeros, source.register) - } - if err != nil { - return err - } - - // Trap if the value is not minus (= the minimum signed 32-bit int). - c.compileMaybeExitFromNativeCode(amd64.JCS, nativeCallStatusIntegerOverflow) - - // We jump to the next instructions for valid cases. - c.assembler.SetJumpTargetOnNext(okJmp) - } else { - // Jump if the value does not exceed the lower bound. - var jmpIfNotExceedsLowerBound asm.Node - if isFloat32Bit { - jmpIfNotExceedsLowerBound = c.assembler.CompileJump(amd64.JCC) - } else { - jmpIfNotExceedsLowerBound = c.assembler.CompileJump(amd64.JHI) - } - - // If the value exceeds the lower bound, we "saturate" it to the minimum. - if err = c.assembler.CompileStaticConstToRegister(amd64.MOVL, c.minimum32BitSignedInt, result); err != nil { - return err - } - nonTrappingSaturatedMinimumJump := c.assembler.CompileJump(amd64.JMP) - - // Otherwise, the value is the minimum signed 32-bit int (=-2147483648.000000) or larger than 32-bit maximum. - c.assembler.SetJumpTargetOnNext(jmpIfNotExceedsLowerBound) - if isFloat32Bit { - err = c.assembler.CompileStaticConstToRegister(amd64.UCOMISS, c.fourZeros, source.register) - } else { - err = c.assembler.CompileStaticConstToRegister(amd64.UCOMISD, c.eightZeros, source.register) - } - if err != nil { - return err - } - jmpIfMinimumSignedInt := c.assembler.CompileJump(amd64.JCS) // jump if the value is minus (= the minimum signed 32-bit int). - - // If the value exceeds signed 32-bit maximum, we saturate it to the maximum. - if err = c.assembler.CompileStaticConstToRegister(amd64.MOVL, c.maximum32BitSignedInt, result); err != nil { - return err - } - - c.assembler.SetJumpTargetOnNext(okJmp) - c.assembler.SetJumpTargetOnNext(nontrappingNanJump) - c.assembler.SetJumpTargetOnNext(nonTrappingSaturatedMinimumJump) - c.assembler.SetJumpTargetOnNext(jmpIfMinimumSignedInt) - } - - // We consumed the source's register and placed the conversion result - // in the result register. - c.locationStack.markRegisterUnused(source.register) - c.pushRuntimeValueLocationOnRegister(result, runtimeValueTypeI32) - return nil -} - -// emitSignedI64TruncFromFloat implements compileITruncFromF when the destination type is a 64-bit signed integer. -func (c *amd64Compiler) emitSignedI64TruncFromFloat(isFloat32Bit, nonTrapping bool) error { - source := c.locationStack.pop() - if err := c.compileEnsureOnRegister(source); err != nil { - return err - } - - result, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - - // First we unconditionally convert source to integer via CVTTSS2SI (CVTTSD2SI for 64bit float). - if isFloat32Bit { - c.assembler.CompileRegisterToRegister(amd64.CVTTSS2SQ, source.register, result) - } else { - c.assembler.CompileRegisterToRegister(amd64.CVTTSD2SQ, source.register, result) - } - - // We compare the conversion result with the sign bit mask to check if it is either - // 1) the source float value is either +-Inf or NaN, or it exceeds representative ranges of 32bit signed integer, or - // 2) the source equals the minimum signed 32-bit (=-9223372036854775808.0) whose bit pattern is float32ForMinimumSigned64bitIntegerAddress for 32 bit float - // or float64ForMinimumSigned64bitIntegerAddress for 64bit float. - err = c.assembler.CompileStaticConstToRegister(amd64.CMPQ, c.float64SignBitMask, result) - if err != nil { - return err - } - - // Otherwise, we simply jump to exit as the result is valid. - okJmp := c.assembler.CompileJump(amd64.JNE) - - // Start handling the case of 1) and 2). - // First, check if the value is NaN. - if isFloat32Bit { - c.assembler.CompileRegisterToRegister(amd64.UCOMISS, source.register, source.register) - } else { - c.assembler.CompileRegisterToRegister(amd64.UCOMISD, source.register, source.register) - } - - // Check the parity flag (set when the value is NaN), and if it is set, we should raise an exception. - var nontrappingNanJump asm.Node - if nonTrapping { - jmpIfNotNaN := c.assembler.CompileJump(amd64.JPC) // jump if parity is not set. - // In non trapping case, NaN is casted as zero. - // Zero out the result register by XOR itsself. - c.assembler.CompileRegisterToRegister(amd64.XORQ, result, result) - nontrappingNanJump = c.assembler.CompileJump(amd64.JMP) - c.assembler.SetJumpTargetOnNext(jmpIfNotNaN) - } else { - c.compileMaybeExitFromNativeCode(amd64.JPC, nativeCallStatusCodeInvalidFloatToIntConversion) - } - - // Check if the value is larger than or equal the minimum 64-bit integer value, - // meaning that the value exceeds the lower bound of 64-bit signed integer range. - if isFloat32Bit { - err = c.assembler.CompileStaticConstToRegister(amd64.UCOMISS, c.float32ForMinimumSigned64bitInteger, source.register) - } else { - err = c.assembler.CompileStaticConstToRegister(amd64.UCOMISD, c.float64ForMinimumSigned64bitInteger, source.register) - } - if err != nil { - return err - } - - if !nonTrapping { - // Jump if the value is -Inf. - c.compileMaybeExitFromNativeCode(amd64.JCC, nativeCallStatusIntegerOverflow) - - // At this point, the value is the minimum signed 64-bit int (=-9223372036854775808.0) or larger than 64-bit maximum. - // So, check if the value equals the minimum signed 64-bit int. - if isFloat32Bit { - err = c.assembler.CompileStaticConstToRegister(amd64.UCOMISS, c.fourZeros, source.register) - } else { - err = c.assembler.CompileStaticConstToRegister(amd64.UCOMISD, c.eightZeros, source.register) - } - if err != nil { - return err - } - - // Trap if the value is not minus (= the minimum signed 64-bit int). - c.compileMaybeExitFromNativeCode(amd64.JCS, nativeCallStatusIntegerOverflow) - - // We jump to the next instructions for valid cases. - c.assembler.SetJumpTargetOnNext(okJmp) - } else { - // Jump if the value is not -Inf. - jmpIfNotExceedsLowerBound := c.assembler.CompileJump(amd64.JCC) - - // If the value exceeds the lower bound, we "saturate" it to the minimum. - err = c.assembler.CompileStaticConstToRegister(amd64.MOVQ, c.minimum64BitSignedInt, result) - if err != nil { - return err - } - - nonTrappingSaturatedMinimumJump := c.assembler.CompileJump(amd64.JMP) - - // Otherwise, the value is the minimum signed 64-bit int (=-9223372036854775808.0) or larger than 64-bit maximum. - // So, check if the value equals the minimum signed 64-bit int. - c.assembler.SetJumpTargetOnNext(jmpIfNotExceedsLowerBound) - if isFloat32Bit { - err = c.assembler.CompileStaticConstToRegister(amd64.UCOMISS, c.fourZeros, source.register) - } else { - err = c.assembler.CompileStaticConstToRegister(amd64.UCOMISD, c.eightZeros, source.register) - } - if err != nil { - return err - } - - jmpIfMinimumSignedInt := c.assembler.CompileJump(amd64.JCS) // jump if the value is minus (= the minimum signed 64-bit int). - - // If the value exceeds signed 64-bit maximum, we saturate it to the maximum. - if err = c.assembler.CompileStaticConstToRegister(amd64.MOVQ, c.maximum64BitSignedInt, result); err != nil { - return err - } - - c.assembler.SetJumpTargetOnNext(okJmp) - c.assembler.SetJumpTargetOnNext(jmpIfMinimumSignedInt) - c.assembler.SetJumpTargetOnNext(nonTrappingSaturatedMinimumJump) - c.assembler.SetJumpTargetOnNext(nontrappingNanJump) - } - - // We consumed the source's register and placed the conversion result - // in the result register. - c.locationStack.markRegisterUnused(source.register) - c.pushRuntimeValueLocationOnRegister(result, runtimeValueTypeI64) - return nil -} - -// compileFConvertFromI implements compiler.compileFConvertFromI for the amd64 architecture. -func (c *amd64Compiler) compileFConvertFromI(o *wazeroir.UnionOperation) (err error) { - inputType := wazeroir.SignedInt(o.B1) - outputType := wazeroir.Float(o.B2) - if outputType == wazeroir.Float32 && inputType == wazeroir.SignedInt32 { - err = c.compileSimpleConversion(amd64.CVTSL2SS, registerTypeVector, runtimeValueTypeF32) // = CVTSI2SS for 32bit int - } else if outputType == wazeroir.Float32 && inputType == wazeroir.SignedInt64 { - err = c.compileSimpleConversion(amd64.CVTSQ2SS, registerTypeVector, runtimeValueTypeF32) // = CVTSI2SS for 64bit int - } else if outputType == wazeroir.Float64 && inputType == wazeroir.SignedInt32 { - err = c.compileSimpleConversion(amd64.CVTSL2SD, registerTypeVector, runtimeValueTypeF64) // = CVTSI2SD for 32bit int - } else if outputType == wazeroir.Float64 && inputType == wazeroir.SignedInt64 { - err = c.compileSimpleConversion(amd64.CVTSQ2SD, registerTypeVector, runtimeValueTypeF64) // = CVTSI2SD for 64bit int - } else if outputType == wazeroir.Float32 && inputType == wazeroir.SignedUint32 { - // See the following link for why we use 64bit conversion for unsigned 32bit integer sources: - // https://stackoverflow.com/questions/41495498/fpu-operations-generated-by-gcc-during-casting-integer-to-float. - // - // Here's the summary: - // >> CVTSI2SS is indeed designed for converting a signed integer to a scalar single-precision float, - // >> not an unsigned integer like you have here. So what gives? Well, a 64-bit processor has 64-bit wide - // >> registers available, so the unsigned 32-bit input values can be stored as signed 64-bit intermediate values, - // >> which allows CVTSI2SS to be used after all. - err = c.compileSimpleConversion(amd64.CVTSQ2SS, registerTypeVector, runtimeValueTypeF32) // = CVTSI2SS for 64bit int. - } else if outputType == wazeroir.Float64 && inputType == wazeroir.SignedUint32 { - // For the same reason above, we use 64bit conversion for unsigned 32bit. - err = c.compileSimpleConversion(amd64.CVTSQ2SD, registerTypeVector, runtimeValueTypeF64) // = CVTSI2SD for 64bit int. - } else if outputType == wazeroir.Float32 && inputType == wazeroir.SignedUint64 { - err = c.emitUnsignedInt64ToFloatConversion(true) - } else if outputType == wazeroir.Float64 && inputType == wazeroir.SignedUint64 { - err = c.emitUnsignedInt64ToFloatConversion(false) - } - return -} - -// emitUnsignedInt64ToFloatConversion is handling the case of unsigned 64-bit integer -// in compileFConvertFromI. -func (c *amd64Compiler) emitUnsignedInt64ToFloatConversion(isFloat32bit bool) error { - // The logic here is exactly the same as GCC emits for the following code: - // - // float convert(int num) { - // float foo; - // uint64_t ptr1 = 100; - // foo = (float)(ptr1); - // return foo; - // } - // - // which is compiled by GCC as - // - // convert: - // push rbp - // mov rbp, rsp - // mov DWORD PTR [rbp-20], edi - // mov DWORD PTR [rbp-4], 100 - // mov eax, DWORD PTR [rbp-4] - // test rax, rax - // js .handle_sign_bit_case - // cvtsi2ss xmm0, rax - // jmp .exit - // .handle_sign_bit_case: - // mov rdx, rax - // shr rdx - // and eax, 1 - // or rdx, rax - // cvtsi2ss xmm0, rdx - // addsd xmm0, xmm0 - // .exit: ... - // - // tl;dr is that we have a branch depending on whether or not sign bit is set. - - origin := c.locationStack.pop() - if err := c.compileEnsureOnRegister(origin); err != nil { - return err - } - - dest, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - - c.locationStack.markRegisterUsed(dest) - - tmpReg, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - - // Check if the most significant bit (sign bit) is set. - c.assembler.CompileRegisterToRegister(amd64.TESTQ, origin.register, origin.register) - - // Jump if the sign bit is set. - jmpIfSignbitSet := c.assembler.CompileJump(amd64.JMI) - - // Otherwise, we could fit the unsigned int into float32. - // So, we convert it to float32 and emit jump instruction to exit from this branch. - if isFloat32bit { - c.assembler.CompileRegisterToRegister(amd64.CVTSQ2SS, origin.register, dest) - } else { - c.assembler.CompileRegisterToRegister(amd64.CVTSQ2SD, origin.register, dest) - } - exitFromSignbitUnSet := c.assembler.CompileJump(amd64.JMP) - - // Now handling the case where sign-bit is set. - // We emit the following sequences: - // mov tmpReg, origin - // shr tmpReg, 1 - // and origin, 1 - // or tmpReg, origin - // cvtsi2ss xmm0, tmpReg - // addsd xmm0, xmm0 - - c.assembler.SetJumpTargetOnNext(jmpIfSignbitSet) - c.assembler.CompileRegisterToRegister(amd64.MOVQ, origin.register, tmpReg) - c.assembler.CompileConstToRegister(amd64.SHRQ, 1, tmpReg) - c.assembler.CompileConstToRegister(amd64.ANDQ, 1, origin.register) - c.assembler.CompileRegisterToRegister(amd64.ORQ, origin.register, tmpReg) - if isFloat32bit { - c.assembler.CompileRegisterToRegister(amd64.CVTSQ2SS, tmpReg, dest) - } else { - c.assembler.CompileRegisterToRegister(amd64.CVTSQ2SD, tmpReg, dest) - } - if isFloat32bit { - c.assembler.CompileRegisterToRegister(amd64.ADDSS, dest, dest) - } else { - c.assembler.CompileRegisterToRegister(amd64.ADDSD, dest, dest) - } - - // Now, we finished the sign-bit set branch. - // We have to make the exit jump target of sign-bit unset branch - // towards the next instruction. - c.assembler.SetJumpTargetOnNext(exitFromSignbitUnSet) - - // We consumed the origin's register and placed the conversion result - // in the dest register. - c.locationStack.markRegisterUnused(origin.register) - if isFloat32bit { - c.pushRuntimeValueLocationOnRegister(dest, runtimeValueTypeF32) - } else { - c.pushRuntimeValueLocationOnRegister(dest, runtimeValueTypeF64) - } - return nil -} - -// compileSimpleConversion pops a value type from the stack, and applies the -// given instruction on it, and push the result onto a register of the given type. -func (c *amd64Compiler) compileSimpleConversion(convInstruction asm.Instruction, - destinationRegisterType registerType, destinationValueType runtimeValueType, -) error { - origin := c.locationStack.pop() - if err := c.compileEnsureOnRegister(origin); err != nil { - return err - } - - dest, err := c.allocateRegister(destinationRegisterType) - if err != nil { - return err - } - - c.assembler.CompileRegisterToRegister(convInstruction, origin.register, dest) - - c.locationStack.markRegisterUnused(origin.register) - c.pushRuntimeValueLocationOnRegister(dest, destinationValueType) - return nil -} - -// compileF32DemoteFromF64 implements compiler.compileF32DemoteFromF64 for the amd64 architecture. -func (c *amd64Compiler) compileF32DemoteFromF64() error { - target := c.locationStack.peek() // Note this is peek! - if err := c.compileEnsureOnRegister(target); err != nil { - return err - } - - c.assembler.CompileRegisterToRegister(amd64.CVTSD2SS, target.register, target.register) - target.valueType = runtimeValueTypeF32 - return nil -} - -// compileF64PromoteFromF32 implements compiler.compileF64PromoteFromF32 for the amd64 architecture. -func (c *amd64Compiler) compileF64PromoteFromF32() error { - target := c.locationStack.peek() // Note this is peek! - if err := c.compileEnsureOnRegister(target); err != nil { - return err - } - - c.assembler.CompileRegisterToRegister(amd64.CVTSS2SD, target.register, target.register) - target.valueType = runtimeValueTypeF64 - return nil -} - -// compileI32ReinterpretFromF32 implements compiler.compileI32ReinterpretFromF32 for the amd64 architecture. -func (c *amd64Compiler) compileI32ReinterpretFromF32() error { - if peek := c.locationStack.peek(); peek.onStack() { - // If the value is on the stack, this is no-op as there is nothing to do for converting type. - peek.valueType = runtimeValueTypeI32 - return nil - } - return c.compileSimpleConversion(amd64.MOVL, registerTypeGeneralPurpose, runtimeValueTypeI32) -} - -// compileI64ReinterpretFromF64 implements compiler.compileI64ReinterpretFromF64 for the amd64 architecture. -func (c *amd64Compiler) compileI64ReinterpretFromF64() error { - if peek := c.locationStack.peek(); peek.onStack() { - // If the value is on the stack, this is no-op as there is nothing to do for converting type. - peek.valueType = runtimeValueTypeI64 - return nil - } - return c.compileSimpleConversion(amd64.MOVQ, registerTypeGeneralPurpose, runtimeValueTypeI64) -} - -// compileF32ReinterpretFromI32 implements compiler.compileF32ReinterpretFromI32 for the amd64 architecture. -func (c *amd64Compiler) compileF32ReinterpretFromI32() error { - if peek := c.locationStack.peek(); peek.onStack() { - // If the value is on the stack, this is no-op as there is nothing to do for converting type. - peek.valueType = runtimeValueTypeF32 - return nil - } - return c.compileSimpleConversion(amd64.MOVL, registerTypeVector, runtimeValueTypeF32) -} - -// compileF64ReinterpretFromI64 implements compiler.compileF64ReinterpretFromI64 for the amd64 architecture. -func (c *amd64Compiler) compileF64ReinterpretFromI64() error { - if peek := c.locationStack.peek(); peek.onStack() { - // If the value is on the stack, this is no-op as there is nothing to do for converting type. - peek.valueType = runtimeValueTypeF64 - return nil - } - return c.compileSimpleConversion(amd64.MOVQ, registerTypeVector, runtimeValueTypeF64) -} - -// compileExtend implements compiler.compileExtend for the amd64 architecture. -func (c *amd64Compiler) compileExtend(o *wazeroir.UnionOperation) error { - var inst asm.Instruction - signed := o.B1 != 0 - if signed { - inst = amd64.MOVLQSX // = MOVSXD https://www.felixcloutier.com/x86/movsx:movsxd - } else { - inst = amd64.MOVL - } - return c.compileExtendImpl(inst, runtimeValueTypeI64) -} - -// compileSignExtend32From8 implements compiler.compileSignExtend32From8 for the amd64 architecture. -func (c *amd64Compiler) compileSignExtend32From8() error { - return c.compileExtendImpl(amd64.MOVBLSX, runtimeValueTypeI32) -} - -// compileSignExtend32From16 implements compiler.compileSignExtend32From16 for the amd64 architecture. -func (c *amd64Compiler) compileSignExtend32From16() error { - return c.compileExtendImpl(amd64.MOVWLSX, runtimeValueTypeI32) -} - -// compileSignExtend64From8 implements compiler.compileSignExtend64From8 for the amd64 architecture. -func (c *amd64Compiler) compileSignExtend64From8() error { - return c.compileExtendImpl(amd64.MOVBQSX, runtimeValueTypeI64) -} - -// compileSignExtend64From16 implements compiler.compileSignExtend64From16 for the amd64 architecture. -func (c *amd64Compiler) compileSignExtend64From16() error { - return c.compileExtendImpl(amd64.MOVWQSX, runtimeValueTypeI64) -} - -// compileSignExtend64From32 implements compiler.compileSignExtend64From32 for the amd64 architecture. -func (c *amd64Compiler) compileSignExtend64From32() error { - return c.compileExtendImpl(amd64.MOVLQSX, runtimeValueTypeI64) -} - -func (c *amd64Compiler) compileExtendImpl(inst asm.Instruction, destinationType runtimeValueType) error { - target := c.locationStack.peek() // Note this is peek! - if err := c.compileEnsureOnRegister(target); err != nil { - return err - } - - c.assembler.CompileRegisterToRegister(inst, target.register, target.register) - target.valueType = destinationType - return nil -} - -// compileEq implements compiler.compileEq for the amd64 architecture. -func (c *amd64Compiler) compileEq(o *wazeroir.UnionOperation) error { - return c.compileEqOrNe(wazeroir.UnsignedType(o.B1), true) -} - -// compileNe implements compiler.compileNe for the amd64 architecture. -func (c *amd64Compiler) compileNe(o *wazeroir.UnionOperation) error { - return c.compileEqOrNe(wazeroir.UnsignedType(o.B1), false) -} - -func (c *amd64Compiler) compileEqOrNe(t wazeroir.UnsignedType, shouldEqual bool) (err error) { - x2 := c.locationStack.pop() - if err := c.compileEnsureOnRegister(x2); err != nil { - return err - } - - x1 := c.locationStack.pop() - if err := c.compileEnsureOnRegister(x1); err != nil { - return err - } - - x1r, x2r := x1.register, x2.register - - // x1 and x2 are temporary registers only used for the cmp operation. Release them. - c.locationStack.releaseRegister(x1) - c.locationStack.releaseRegister(x2) - - switch t { - case wazeroir.UnsignedTypeI32: - err = c.compileEqOrNeForInts(x1r, x2r, amd64.CMPL, shouldEqual) - case wazeroir.UnsignedTypeI64: - err = c.compileEqOrNeForInts(x1r, x2r, amd64.CMPQ, shouldEqual) - case wazeroir.UnsignedTypeF32: - err = c.compileEqOrNeForFloats(x1r, x2r, amd64.UCOMISS, shouldEqual) - case wazeroir.UnsignedTypeF64: - err = c.compileEqOrNeForFloats(x1r, x2r, amd64.UCOMISD, shouldEqual) - } - if err != nil { - return - } - return -} - -func (c *amd64Compiler) compileEqOrNeForInts(x1Reg, x2Reg asm.Register, cmpInstruction asm.Instruction, - shouldEqual bool, -) error { - c.assembler.CompileRegisterToRegister(cmpInstruction, x2Reg, x1Reg) - - // Record that the result is on the conditional register. - var condReg asm.ConditionalRegisterState - if shouldEqual { - condReg = amd64.ConditionalRegisterStateE - } else { - condReg = amd64.ConditionalRegisterStateNE - } - loc := c.locationStack.pushRuntimeValueLocationOnConditionalRegister(condReg) - loc.valueType = runtimeValueTypeI32 - return nil -} - -// For float EQ and NE, we have to take NaN values into account. -// Notably, Wasm specification states that if one of targets is NaN, -// the result must be zero for EQ or one for NE. -func (c *amd64Compiler) compileEqOrNeForFloats(x1Reg, x2Reg asm.Register, cmpInstruction asm.Instruction, shouldEqual bool) error { - // Before we allocate the result, we have to reserve two int registers. - nanFragReg, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - c.locationStack.markRegisterUsed(nanFragReg) - cmpResultReg, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - - // Then, execute the comparison. - c.assembler.CompileRegisterToRegister(cmpInstruction, x2Reg, x1Reg) - - // First, we get the parity flag which indicates whether one of values was NaN. - if shouldEqual { - // Set 1 if two values are NOT NaN. - c.assembler.CompileNoneToRegister(amd64.SETPC, nanFragReg) - } else { - // Set 1 if one of values is NaN. - c.assembler.CompileNoneToRegister(amd64.SETPS, nanFragReg) - } - - // next, we get the usual comparison flag. - if shouldEqual { - // Set 1 if equal. - c.assembler.CompileNoneToRegister(amd64.SETEQ, cmpResultReg) - } else { - // Set 1 if not equal. - c.assembler.CompileNoneToRegister(amd64.SETNE, cmpResultReg) - } - - // Do "and" or "or" operations on these two flags to get the actual result. - if shouldEqual { - c.assembler.CompileRegisterToRegister(amd64.ANDL, nanFragReg, cmpResultReg) - } else { - c.assembler.CompileRegisterToRegister(amd64.ORL, nanFragReg, cmpResultReg) - } - - // Clear the unnecessary bits by zero extending the first byte. - // This is necessary the upper bits (5 to 32 bits) of SET* instruction result is undefined. - c.assembler.CompileRegisterToRegister(amd64.MOVBLZX, cmpResultReg, cmpResultReg) - - // Now we have the result in cmpResultReg register, so we record it. - c.pushRuntimeValueLocationOnRegister(cmpResultReg, runtimeValueTypeI32) - // Also, we no longer need nanFragRegister. - c.locationStack.markRegisterUnused(nanFragReg) - return nil -} - -// compileEqz implements compiler.compileEqz for the amd64 architecture. -func (c *amd64Compiler) compileEqz(o *wazeroir.UnionOperation) (err error) { - v := c.locationStack.pop() - if err = c.compileEnsureOnRegister(v); err != nil { - return err - } - - unsignedInt := wazeroir.UnsignedInt(o.B1) - switch unsignedInt { - case wazeroir.UnsignedInt32: - err = c.assembler.CompileStaticConstToRegister(amd64.CMPL, c.fourZeros, v.register) - case wazeroir.UnsignedInt64: - err = c.assembler.CompileStaticConstToRegister(amd64.CMPQ, c.eightZeros, v.register) - } - if err != nil { - return err - } - - // v is consumed by the cmp operation so release it. - c.locationStack.releaseRegister(v) - - // Finally, record that the result is on the conditional register. - loc := c.locationStack.pushRuntimeValueLocationOnConditionalRegister(amd64.ConditionalRegisterStateE) - loc.valueType = runtimeValueTypeI32 - return nil -} - -// compileLt implements compiler.compileLt for the amd64 architecture. -func (c *amd64Compiler) compileLt(o *wazeroir.UnionOperation) error { - x2 := c.locationStack.pop() - if err := c.compileEnsureOnRegister(x2); err != nil { - return err - } - - x1 := c.locationStack.pop() - if err := c.compileEnsureOnRegister(x1); err != nil { - return err - } - - // Emit the compare instruction. - var resultConditionState asm.ConditionalRegisterState - var inst asm.Instruction - signedType := wazeroir.SignedType(o.B1) - switch signedType { - case wazeroir.SignedTypeInt32: - resultConditionState = amd64.ConditionalRegisterStateL - inst = amd64.CMPL - case wazeroir.SignedTypeUint32: - resultConditionState = amd64.ConditionalRegisterStateB - inst = amd64.CMPL - case wazeroir.SignedTypeInt64: - inst = amd64.CMPQ - resultConditionState = amd64.ConditionalRegisterStateL - case wazeroir.SignedTypeUint64: - resultConditionState = amd64.ConditionalRegisterStateB - inst = amd64.CMPQ - case wazeroir.SignedTypeFloat32: - resultConditionState = amd64.ConditionalRegisterStateA - inst = amd64.COMISS - case wazeroir.SignedTypeFloat64: - resultConditionState = amd64.ConditionalRegisterStateA - inst = amd64.COMISD - } - c.assembler.CompileRegisterToRegister(inst, x1.register, x2.register) - - // x1 and x2 are temporary registers only used for the cmp operation. Release them. - c.locationStack.releaseRegister(x1) - c.locationStack.releaseRegister(x2) - - // Finally, record that the result is on the conditional register. - loc := c.locationStack.pushRuntimeValueLocationOnConditionalRegister(resultConditionState) - loc.valueType = runtimeValueTypeI32 - return nil -} - -// compileGt implements compiler.compileGt for the amd64 architecture. -func (c *amd64Compiler) compileGt(o *wazeroir.UnionOperation) error { - x2 := c.locationStack.pop() - if err := c.compileEnsureOnRegister(x2); err != nil { - return err - } - - x1 := c.locationStack.pop() - if err := c.compileEnsureOnRegister(x1); err != nil { - return err - } - - // Emit the compare instruction. - var resultConditionState asm.ConditionalRegisterState - signedType := wazeroir.SignedType(o.B1) - switch signedType { - case wazeroir.SignedTypeInt32: - resultConditionState = amd64.ConditionalRegisterStateG - c.assembler.CompileRegisterToRegister(amd64.CMPL, x1.register, x2.register) - case wazeroir.SignedTypeUint32: - c.assembler.CompileRegisterToRegister(amd64.CMPL, x1.register, x2.register) - resultConditionState = amd64.ConditionalRegisterStateA - case wazeroir.SignedTypeInt64: - c.assembler.CompileRegisterToRegister(amd64.CMPQ, x1.register, x2.register) - resultConditionState = amd64.ConditionalRegisterStateG - case wazeroir.SignedTypeUint64: - c.assembler.CompileRegisterToRegister(amd64.CMPQ, x1.register, x2.register) - resultConditionState = amd64.ConditionalRegisterStateA - case wazeroir.SignedTypeFloat32: - c.assembler.CompileRegisterToRegister(amd64.UCOMISS, x2.register, x1.register) - resultConditionState = amd64.ConditionalRegisterStateA - case wazeroir.SignedTypeFloat64: - c.assembler.CompileRegisterToRegister(amd64.UCOMISD, x2.register, x1.register) - resultConditionState = amd64.ConditionalRegisterStateA - } - - // x1 and x2 are temporary registers only used for the cmp operation. Release them. - c.locationStack.releaseRegister(x1) - c.locationStack.releaseRegister(x2) - - // Finally, record that the result is on the conditional register. - loc := c.locationStack.pushRuntimeValueLocationOnConditionalRegister(resultConditionState) - loc.valueType = runtimeValueTypeI32 - return nil -} - -// compileLe implements compiler.compileLe for the amd64 architecture. -func (c *amd64Compiler) compileLe(o *wazeroir.UnionOperation) error { - x2 := c.locationStack.pop() - if err := c.compileEnsureOnRegister(x2); err != nil { - return err - } - - x1 := c.locationStack.pop() - if err := c.compileEnsureOnRegister(x1); err != nil { - return err - } - - // Emit the compare instruction. - var inst asm.Instruction - var resultConditionState asm.ConditionalRegisterState - signedType := wazeroir.SignedType(o.B1) - switch signedType { - case wazeroir.SignedTypeInt32: - resultConditionState = amd64.ConditionalRegisterStateLE - inst = amd64.CMPL - case wazeroir.SignedTypeUint32: - resultConditionState = amd64.ConditionalRegisterStateBE - inst = amd64.CMPL - case wazeroir.SignedTypeInt64: - resultConditionState = amd64.ConditionalRegisterStateLE - inst = amd64.CMPQ - case wazeroir.SignedTypeUint64: - resultConditionState = amd64.ConditionalRegisterStateBE - inst = amd64.CMPQ - case wazeroir.SignedTypeFloat32: - resultConditionState = amd64.ConditionalRegisterStateAE - inst = amd64.UCOMISS - case wazeroir.SignedTypeFloat64: - resultConditionState = amd64.ConditionalRegisterStateAE - inst = amd64.UCOMISD - } - c.assembler.CompileRegisterToRegister(inst, x1.register, x2.register) - - // x1 and x2 are temporary registers only used for the cmp operation. Release them. - c.locationStack.releaseRegister(x1) - c.locationStack.releaseRegister(x2) - - // Finally, record that the result is on the conditional register. - loc := c.locationStack.pushRuntimeValueLocationOnConditionalRegister(resultConditionState) - loc.valueType = runtimeValueTypeI32 - return nil -} - -// compileGe implements compiler.compileGe for the amd64 architecture. -func (c *amd64Compiler) compileGe(o *wazeroir.UnionOperation) error { - x2 := c.locationStack.pop() - if err := c.compileEnsureOnRegister(x2); err != nil { - return err - } - - x1 := c.locationStack.pop() - if err := c.compileEnsureOnRegister(x1); err != nil { - return err - } - - // Emit the compare instruction. - var resultConditionState asm.ConditionalRegisterState - signedType := wazeroir.SignedType(o.B1) - switch signedType { - case wazeroir.SignedTypeInt32: - c.assembler.CompileRegisterToRegister(amd64.CMPL, x1.register, x2.register) - resultConditionState = amd64.ConditionalRegisterStateGE - case wazeroir.SignedTypeUint32: - c.assembler.CompileRegisterToRegister(amd64.CMPL, x1.register, x2.register) - resultConditionState = amd64.ConditionalRegisterStateAE - case wazeroir.SignedTypeInt64: - c.assembler.CompileRegisterToRegister(amd64.CMPQ, x1.register, x2.register) - resultConditionState = amd64.ConditionalRegisterStateGE - case wazeroir.SignedTypeUint64: - c.assembler.CompileRegisterToRegister(amd64.CMPQ, x1.register, x2.register) - resultConditionState = amd64.ConditionalRegisterStateAE - case wazeroir.SignedTypeFloat32: - c.assembler.CompileRegisterToRegister(amd64.COMISS, x2.register, x1.register) - resultConditionState = amd64.ConditionalRegisterStateAE - case wazeroir.SignedTypeFloat64: - c.assembler.CompileRegisterToRegister(amd64.COMISD, x2.register, x1.register) - resultConditionState = amd64.ConditionalRegisterStateAE - } - - // x1 and x2 are temporary registers only used for the cmp operation. Release them. - c.locationStack.releaseRegister(x1) - c.locationStack.releaseRegister(x2) - - // Finally, record that the result is on the conditional register. - loc := c.locationStack.pushRuntimeValueLocationOnConditionalRegister(resultConditionState) - loc.valueType = runtimeValueTypeI32 - return nil -} - -// compileLoad implements compiler.compileLoad for the amd64 architecture. -func (c *amd64Compiler) compileLoad(o *wazeroir.UnionOperation) error { - var ( - isIntType bool - movInst asm.Instruction - targetSizeInBytes int64 - vt runtimeValueType - ) - - unsignedType := wazeroir.UnsignedType(o.B1) - offset := uint32(o.U2) - - switch unsignedType { - case wazeroir.UnsignedTypeI32: - isIntType = true - movInst = amd64.MOVL - targetSizeInBytes = 32 / 8 - vt = runtimeValueTypeI32 - case wazeroir.UnsignedTypeI64: - isIntType = true - movInst = amd64.MOVQ - targetSizeInBytes = 64 / 8 - vt = runtimeValueTypeI64 - case wazeroir.UnsignedTypeF32: - isIntType = false - movInst = amd64.MOVL - targetSizeInBytes = 32 / 8 - vt = runtimeValueTypeF32 - case wazeroir.UnsignedTypeF64: - isIntType = false - movInst = amd64.MOVQ - targetSizeInBytes = 64 / 8 - vt = runtimeValueTypeF64 - } - - reg, err := c.compileMemoryAccessCeilSetup(offset, targetSizeInBytes) - if err != nil { - return err - } - - if isIntType { - // For integer types, read the corresponding bytes from the offset to the memory - // and store the value to the int register. - c.assembler.CompileMemoryWithIndexToRegister(movInst, - // we access memory as memory.Buffer[ceil-targetSizeInBytes: ceil]. - amd64ReservedRegisterForMemory, -targetSizeInBytes, reg, 1, - reg) - c.pushRuntimeValueLocationOnRegister(reg, vt) - } else { - // For float types, we read the value to the float register. - floatReg, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - c.assembler.CompileMemoryWithIndexToRegister(movInst, - // we access memory as memory.Buffer[ceil-targetSizeInBytes: ceil]. - amd64ReservedRegisterForMemory, -targetSizeInBytes, reg, 1, - floatReg) - c.pushRuntimeValueLocationOnRegister(floatReg, vt) - // We no longer need the int register so mark it unused. - c.locationStack.markRegisterUnused(reg) - } - return nil -} - -// compileLoad8 implements compiler.compileLoad8 for the amd64 architecture. -func (c *amd64Compiler) compileLoad8(o *wazeroir.UnionOperation) error { - const targetSizeInBytes = 1 - offset := uint32(o.U2) - reg, err := c.compileMemoryAccessCeilSetup(offset, targetSizeInBytes) - if err != nil { - return err - } - - // Then move a byte at the offset to the register. - // Note that Load8 is only for integer types. - var inst asm.Instruction - var vt runtimeValueType - signedInt := wazeroir.SignedInt(o.B1) - switch signedInt { - case wazeroir.SignedInt32: - inst = amd64.MOVBLSX - vt = runtimeValueTypeI32 - case wazeroir.SignedUint32: - inst = amd64.MOVBLZX - vt = runtimeValueTypeI32 - case wazeroir.SignedInt64: - inst = amd64.MOVBQSX - vt = runtimeValueTypeI64 - case wazeroir.SignedUint64: - inst = amd64.MOVBQZX - vt = runtimeValueTypeI64 - } - - c.assembler.CompileMemoryWithIndexToRegister(inst, - // we access memory as memory.Buffer[ceil-targetSizeInBytes: ceil]. - amd64ReservedRegisterForMemory, -targetSizeInBytes, reg, 1, - reg) - - c.pushRuntimeValueLocationOnRegister(reg, vt) - return nil -} - -// compileLoad16 implements compiler.compileLoad16 for the amd64 architecture. -func (c *amd64Compiler) compileLoad16(o *wazeroir.UnionOperation) error { - const targetSizeInBytes = 16 / 8 - offset := uint32(o.U2) - reg, err := c.compileMemoryAccessCeilSetup(offset, targetSizeInBytes) - if err != nil { - return err - } - - // Then move 2 bytes at the offset to the register. - // Note that Load16 is only for integer types. - var inst asm.Instruction - var vt runtimeValueType - signedInt := wazeroir.SignedInt(o.B1) - switch signedInt { - case wazeroir.SignedInt32: - inst = amd64.MOVWLSX - vt = runtimeValueTypeI32 - case wazeroir.SignedInt64: - inst = amd64.MOVWQSX - vt = runtimeValueTypeI64 - case wazeroir.SignedUint32: - inst = amd64.MOVWLZX - vt = runtimeValueTypeI32 - case wazeroir.SignedUint64: - inst = amd64.MOVWQZX - vt = runtimeValueTypeI64 - } - - c.assembler.CompileMemoryWithIndexToRegister(inst, - // we access memory as memory.Buffer[ceil-targetSizeInBytes: ceil]. - amd64ReservedRegisterForMemory, -targetSizeInBytes, reg, 1, - reg) - - c.pushRuntimeValueLocationOnRegister(reg, vt) - return nil -} - -// compileLoad32 implements compiler.compileLoad32 for the amd64 architecture. -func (c *amd64Compiler) compileLoad32(o *wazeroir.UnionOperation) error { - const targetSizeInBytes = 32 / 8 - offset := uint32(o.U2) - reg, err := c.compileMemoryAccessCeilSetup(offset, targetSizeInBytes) - if err != nil { - return err - } - - // Then move 4 bytes at the offset to the register. - var inst asm.Instruction - signed := o.B1 == 1 - if signed { - inst = amd64.MOVLQSX - } else { - inst = amd64.MOVLQZX - } - c.assembler.CompileMemoryWithIndexToRegister(inst, - // We access memory as memory.Buffer[ceil-targetSizeInBytes: ceil]. - amd64ReservedRegisterForMemory, -targetSizeInBytes, reg, 1, - reg) - c.pushRuntimeValueLocationOnRegister(reg, runtimeValueTypeI64) - return nil -} - -// compileMemoryAccessCeilSetup pops the top value from the stack (called "base"), stores "base + offsetArg + targetSizeInBytes" -// into a register, and returns the stored register. We call the result "ceil" because we access the memory -// as memory.Buffer[ceil-targetSizeInBytes: ceil]. -// -// Note: this also emits the instructions to check the out-of-bounds memory access. -// In other words, if the ceil exceeds the memory size, the code exits with nativeCallStatusCodeMemoryOutOfBounds status. -func (c *amd64Compiler) compileMemoryAccessCeilSetup(offsetArg uint32, targetSizeInBytes int64) (asm.Register, error) { - base := c.locationStack.pop() - if err := c.compileEnsureOnRegister(base); err != nil { - return asm.NilRegister, err - } - - result := base.register - if offsetConst := int64(offsetArg) + targetSizeInBytes; offsetConst <= math.MaxInt32 { - c.assembler.CompileConstToRegister(amd64.ADDQ, offsetConst, result) - } else if offsetConst <= math.MaxUint32 { - // Note: in practice, this branch rarely happens as in this case, the wasm binary know that - // memory has more than 1 GBi or at least tries to access above 1 GBi memory region. - // - // This case, we cannot directly add the offset to a register by ADDQ(const) instruction. - // That is because the imm32 const is sign-extended to 64-bit in ADDQ(const), and we end up - // making offsetConst as the negative number, which is wrong. - tmp, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return asm.NilRegister, err - } - c.assembler.CompileConstToRegister(amd64.MOVL, int64(uint32(offsetConst)), tmp) - c.assembler.CompileRegisterToRegister(amd64.ADDQ, tmp, result) - } else { - // If the offset const is too large, we exit with nativeCallStatusCodeMemoryOutOfBounds. - c.compileExitFromNativeCode(nativeCallStatusCodeMemoryOutOfBounds) - return result, nil - } - - // Now we compare the value with the memory length which is held by callEngine. - if err := c.compileCompareWithMemorySliceLen(result); err != nil { - return asm.NilRegister, err - } - - // Trap if the value is out-of-bounds of memory length. - c.compileMaybeExitFromNativeCode(amd64.JCC, nativeCallStatusCodeMemoryOutOfBounds) - - c.locationStack.markRegisterUnused(result) - return result, nil -} - -// compileStore implements compiler.compileStore for the amd64 architecture. -func (c *amd64Compiler) compileStore(o *wazeroir.UnionOperation) error { - var movInst asm.Instruction - var targetSizeInByte int64 - unsignedType := wazeroir.UnsignedType(o.B1) - offset := uint32(o.U2) - switch unsignedType { - case wazeroir.UnsignedTypeI32, wazeroir.UnsignedTypeF32: - movInst = amd64.MOVL - targetSizeInByte = 32 / 8 - case wazeroir.UnsignedTypeI64, wazeroir.UnsignedTypeF64: - movInst = amd64.MOVQ - targetSizeInByte = 64 / 8 - } - return c.compileStoreImpl(offset, movInst, targetSizeInByte) -} - -// compileStore8 implements compiler.compileStore8 for the amd64 architecture. -func (c *amd64Compiler) compileStore8(o *wazeroir.UnionOperation) error { - return c.compileStoreImpl(uint32(o.U2), amd64.MOVB, 1) -} - -// compileStore32 implements compiler.compileStore32 for the amd64 architecture. -func (c *amd64Compiler) compileStore16(o *wazeroir.UnionOperation) error { - return c.compileStoreImpl(uint32(o.U2), amd64.MOVW, 16/8) -} - -// compileStore32 implements compiler.compileStore32 for the amd64 architecture. -func (c *amd64Compiler) compileStore32(o *wazeroir.UnionOperation) error { - return c.compileStoreImpl(uint32(o.U2), amd64.MOVL, 32/8) -} - -func (c *amd64Compiler) compileStoreImpl(offsetConst uint32, inst asm.Instruction, targetSizeInBytes int64) error { - val := c.locationStack.pop() - if err := c.compileEnsureOnRegister(val); err != nil { - return err - } - - reg, err := c.compileMemoryAccessCeilSetup(offsetConst, targetSizeInBytes) - if err != nil { - return err - } - - c.assembler.CompileRegisterToMemoryWithIndex( - inst, val.register, - amd64ReservedRegisterForMemory, -targetSizeInBytes, reg, 1, - ) - - // We no longer need both the value and base registers. - c.locationStack.releaseRegister(val) - c.locationStack.markRegisterUnused(reg) - return nil -} - -// compileMemoryGrow implements compiler.compileMemoryGrow for the amd64 architecture. -func (c *amd64Compiler) compileMemoryGrow() error { - if err := c.maybeCompileMoveTopConditionalToGeneralPurposeRegister(); err != nil { - return err - } - - if err := c.compileCallBuiltinFunction(builtinFunctionIndexMemoryGrow); err != nil { - return err - } - - // After the function call, we have to initialize the stack base pointer and memory reserved registers. - c.compileReservedStackBasePointerInitialization() - c.compileReservedMemoryPointerInitialization() - return nil -} - -// compileMemorySize implements compiler.compileMemorySize for the amd64 architecture. -func (c *amd64Compiler) compileMemorySize() error { - if err := c.maybeCompileMoveTopConditionalToGeneralPurposeRegister(); err != nil { - return err - } - - reg, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - loc := c.pushRuntimeValueLocationOnRegister(reg, runtimeValueTypeI32) - - if c.ir.Memory != wazeroir.MemoryTypeShared { - // No concurrent accesses so the length we cached during the preamble is still valid. - c.assembler.CompileMemoryToRegister(amd64.MOVQ, amd64ReservedRegisterForCallEngine, callEngineModuleContextMemorySliceLenOffset, loc.register) - } else { - c.assembler.CompileMemoryToRegister(amd64.MOVQ, - amd64ReservedRegisterForCallEngine, callEngineModuleContextMemoryInstanceOffset, - loc.register) - c.assembler.CompileMemoryToRegister(amd64.MOVQ, loc.register, memoryInstanceBufferLenOffset, loc.register) - } - - // WebAssembly's memory.size returns the page size (65536) of memory region. - // That is equivalent to divide the len of memory slice by 65536 and - // that can be calculated as SHR by 16 bits as 65536 = 2^16. - c.assembler.CompileConstToRegister(amd64.SHRQ, wasm.MemoryPageSizeInBits, loc.register) - return nil -} - -// compileMemoryInit implements compiler.compileMemoryInit for the amd64 architecture. -func (c *amd64Compiler) compileMemoryInit(o *wazeroir.UnionOperation) error { - dataIndex := uint32(o.U1) - return c.compileInitImpl(false, dataIndex, 0) -} - -// compileInitImpl implements compileTableInit and compileMemoryInit. -// -// TODO: the compiled code in this function should be reused and compile at once as -// the code is independent of any module. -func (c *amd64Compiler) compileInitImpl(isTable bool, index, tableIndex uint32) error { - outOfBoundsErrorStatus := nativeCallStatusCodeMemoryOutOfBounds - if isTable { - outOfBoundsErrorStatus = nativeCallStatusCodeInvalidTableAccess - } - - copySize := c.locationStack.pop() - if err := c.compileEnsureOnRegister(copySize); err != nil { - return err - } - - sourceOffset := c.locationStack.pop() - if err := c.compileEnsureOnRegister(sourceOffset); err != nil { - return err - } - - destinationOffset := c.locationStack.pop() - if err := c.compileEnsureOnRegister(destinationOffset); err != nil { - return err - } - - instanceAddr, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - c.locationStack.markRegisterUsed(instanceAddr) - if isTable { - c.compileLoadElemInstanceAddress(index, instanceAddr) - } else { - c.compileLoadDataInstanceAddress(index, instanceAddr) - } - - tmp, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - c.locationStack.markRegisterUsed(tmp) - - // sourceOffset += size. - c.assembler.CompileRegisterToRegister(amd64.ADDQ, copySize.register, sourceOffset.register) - // destinationOffset += size. - c.assembler.CompileRegisterToRegister(amd64.ADDQ, copySize.register, destinationOffset.register) - - // Check instance bounds and if exceeds the length, exit with out of bounds error. - c.assembler.CompileMemoryToRegister(amd64.CMPQ, - instanceAddr, 8, // DataInstance and Element instance holds the length is stored at offset 8. - sourceOffset.register) - c.compileMaybeExitFromNativeCode(amd64.JCC, outOfBoundsErrorStatus) - - // Check destination bounds and if exceeds the length, exit with out of bounds error. - if isTable { - // Load the target table's address. - c.assembler.CompileMemoryToRegister(amd64.MOVQ, amd64ReservedRegisterForCallEngine, callEngineModuleContextTablesElement0AddressOffset, tmp) - c.assembler.CompileMemoryToRegister(amd64.MOVQ, tmp, int64(tableIndex*8), tmp) - // Compare length. - c.assembler.CompileMemoryToRegister(amd64.CMPQ, tmp, tableInstanceTableLenOffset, destinationOffset.register) - } else { - if err := c.compileCompareWithMemorySliceLen(destinationOffset.register); err != nil { - return err - } - } - - c.compileMaybeExitFromNativeCode(amd64.JCC, outOfBoundsErrorStatus) - - // Otherwise, ready to copy the value from source to destination. - // - // If the copy size equal zero, we skip the entire instructions below. - c.assembler.CompileRegisterToRegister(amd64.TESTQ, copySize.register, copySize.register) - skipJump := c.assembler.CompileJump(amd64.JEQ) - - var scale int16 - var memToReg, regToMem asm.Instruction - if isTable { - // Each element is of type uintptr; 2^3 = 1 << pointerSizeLog2. - c.assembler.CompileConstToRegister(amd64.SHLQ, pointerSizeLog2, sourceOffset.register) - c.assembler.CompileConstToRegister(amd64.SHLQ, pointerSizeLog2, destinationOffset.register) - // destinationOffset += table buffer's absolute address. - c.assembler.CompileMemoryToRegister(amd64.ADDQ, - tmp, tableInstanceTableOffset, destinationOffset.register) - // sourceOffset += data buffer's absolute address. - c.assembler.CompileMemoryToRegister(amd64.ADDQ, - instanceAddr, 0, sourceOffset.register) - - // For tables, we move 8 bytes at once. - memToReg = amd64.MOVQ - regToMem = memToReg - scale = 8 - } else { - // destinationOffset += memory buffer's absolute address. - c.assembler.CompileRegisterToRegister(amd64.ADDQ, amd64ReservedRegisterForMemory, destinationOffset.register) - - // sourceOffset += data buffer's absolute address. - c.assembler.CompileMemoryToRegister(amd64.ADDQ, instanceAddr, 0, sourceOffset.register) - - // Move one byte at once. - memToReg = amd64.MOVBQZX - regToMem = amd64.MOVB - scale = 1 - } - - // Negate the counter. - c.assembler.CompileNoneToRegister(amd64.NEGQ, copySize.register) - - beginCopyLoop := c.assembler.CompileStandAlone(amd64.NOP) - - c.assembler.CompileMemoryWithIndexToRegister(memToReg, - sourceOffset.register, 0, copySize.register, scale, - tmp) - // [destinationOffset + (size.register)] = tmp. - c.assembler.CompileRegisterToMemoryWithIndex(regToMem, - tmp, - destinationOffset.register, 0, copySize.register, scale, - ) - - // size += 1 - c.assembler.CompileNoneToRegister(amd64.INCQ, copySize.register) - c.assembler.CompileJump(amd64.JMI).AssignJumpTarget(beginCopyLoop) - - c.locationStack.markRegisterUnused(copySize.register, sourceOffset.register, - destinationOffset.register, instanceAddr, tmp) - c.assembler.SetJumpTargetOnNext(skipJump) - return nil -} - -// compileDataDrop implements compiler.compileDataDrop for the amd64 architecture. -func (c *amd64Compiler) compileDataDrop(o *wazeroir.UnionOperation) error { - if err := c.maybeCompileMoveTopConditionalToGeneralPurposeRegister(); err != nil { - return err - } - - tmp, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - - dataIndex := uint32(o.U1) - c.compileLoadDataInstanceAddress(dataIndex, tmp) - - // Clears the content of DataInstance[o.DataIndex] (== []byte type). - c.assembler.CompileConstToMemory(amd64.MOVQ, 0, tmp, 0) - c.assembler.CompileConstToMemory(amd64.MOVQ, 0, tmp, 8) - c.assembler.CompileConstToMemory(amd64.MOVQ, 0, tmp, 16) - return nil -} - -func (c *amd64Compiler) compileLoadDataInstanceAddress(dataIndex uint32, dst asm.Register) { - // dst = dataIndex * dataInstanceStructSize. - c.assembler.CompileConstToRegister(amd64.MOVQ, int64(dataIndex)*dataInstanceStructSize, dst) - - // dst = &moduleInstance.DataInstances[0] + dst - // = &moduleInstance.DataInstances[0] + dataIndex*dataInstanceStructSize - // = &moduleInstance.DataInstances[dataIndex] - c.assembler.CompileMemoryToRegister(amd64.ADDQ, - amd64ReservedRegisterForCallEngine, callEngineModuleContextDataInstancesElement0AddressOffset, - dst, - ) -} - -// compileCopyLoopImpl implements a REP MOVSQ memory copy for the given range with support for both directions. -func (c *amd64Compiler) compileCopyLoopImpl(destinationOffset, sourceOffset, copySize *runtimeValueLocation, backwards bool, bwOffset uint8) { - // skip if nothing to copy - c.assembler.CompileRegisterToRegister(amd64.TESTQ, copySize.register, copySize.register) - emptyEightGroupsJump := c.assembler.CompileJump(amd64.JEQ) - - // Prepare registers for swaps. There will never be more than 3 XCHGs in total. - restoreCrossing := c.compilePreventCrossedTargetRegisters( - []*runtimeValueLocation{destinationOffset, sourceOffset, copySize}, - []asm.Register{amd64.RegDI, amd64.RegSI, amd64.RegCX}) - - // Prepare registers for REP MOVSQ: copy from rsi to rdi, rcx times. - c.compileMaybeSwapRegisters(destinationOffset.register, amd64.RegDI) - c.compileMaybeSwapRegisters(sourceOffset.register, amd64.RegSI) - c.compileMaybeSwapRegisters(copySize.register, amd64.RegCX) - - // Point on first byte of first quadword to copy. - if backwards { - c.assembler.CompileConstToRegister(amd64.ADDQ, -int64(bwOffset), amd64.RegDI) - c.assembler.CompileConstToRegister(amd64.ADDQ, -int64(bwOffset), amd64.RegSI) - // Set REP prefix direction backwards. - c.assembler.CompileStandAlone(amd64.STD) - } - - c.assembler.CompileStandAlone(amd64.REPMOVSQ) - - if backwards { - // Reset direction. - c.assembler.CompileStandAlone(amd64.CLD) - } - - // Restore registers. - c.compileMaybeSwapRegisters(destinationOffset.register, amd64.RegDI) - c.compileMaybeSwapRegisters(sourceOffset.register, amd64.RegSI) - c.compileMaybeSwapRegisters(copySize.register, amd64.RegCX) - restoreCrossing() - - c.assembler.SetJumpTargetOnNext(emptyEightGroupsJump) - c.assembler.CompileStandAlone(amd64.NOP) -} - -// compileMemoryCopyLoopImpl is used for directly copying after bounds/direction check. -func (c *amd64Compiler) compileMemoryCopyLoopImpl(destinationOffset, sourceOffset, copySize *runtimeValueLocation, tmp asm.Register, backwards bool) { - // Point on first byte to be copied depending on direction. - if backwards { - c.assembler.CompileNoneToRegister(amd64.DECQ, sourceOffset.register) - c.assembler.CompileNoneToRegister(amd64.DECQ, destinationOffset.register) - } else { - c.assembler.CompileRegisterToRegister(amd64.SUBQ, copySize.register, sourceOffset.register) - c.assembler.CompileRegisterToRegister(amd64.SUBQ, copySize.register, destinationOffset.register) - } - - // destinationOffset += memory buffer's absolute address. - c.assembler.CompileRegisterToRegister(amd64.ADDQ, amd64ReservedRegisterForMemory, destinationOffset.register) - // sourceOffset += memory buffer's absolute address. - c.assembler.CompileRegisterToRegister(amd64.ADDQ, amd64ReservedRegisterForMemory, sourceOffset.register) - - // Copy copySize % 8 bytes in loop to allow copying in 8 byte groups afterward. - beginLoop := c.assembler.CompileStandAlone(amd64.NOP) - - // Check copySize % 8 == 0. - c.assembler.CompileConstToRegister(amd64.TESTQ, 7, copySize.register) - breakLoop := c.assembler.CompileJump(amd64.JEQ) - - c.assembler.CompileMemoryToRegister(amd64.MOVBQZX, sourceOffset.register, 0, tmp) - c.assembler.CompileRegisterToMemory(amd64.MOVB, tmp, destinationOffset.register, 0) - - if backwards { - c.assembler.CompileNoneToRegister(amd64.DECQ, sourceOffset.register) - c.assembler.CompileNoneToRegister(amd64.DECQ, destinationOffset.register) - } else { - c.assembler.CompileNoneToRegister(amd64.INCQ, sourceOffset.register) - c.assembler.CompileNoneToRegister(amd64.INCQ, destinationOffset.register) - } - - c.assembler.CompileNoneToRegister(amd64.DECQ, copySize.register) - c.assembler.CompileJump(amd64.JMP).AssignJumpTarget(beginLoop) - c.assembler.SetJumpTargetOnNext(breakLoop) - - // compileCopyLoopImpl counts in groups of 8 bytes, so we have to divide the copySize by 8. - c.assembler.CompileConstToRegister(amd64.SHRQ, 3, copySize.register) - - c.compileCopyLoopImpl(destinationOffset, sourceOffset, copySize, backwards, 7) -} - -// compileMemoryCopy implements compiler.compileMemoryCopy for the amd64 architecture. -// -// This uses efficient `REP MOVSQ` instructions to copy in quadword (8 bytes) batches. The remaining bytes -// are copied with a simple `MOV` loop. It uses backward copying for overlapped segments. -func (c *amd64Compiler) compileMemoryCopy() error { - copySize := c.locationStack.pop() - if err := c.compileEnsureOnRegister(copySize); err != nil { - return err - } - - sourceOffset := c.locationStack.pop() - if err := c.compileEnsureOnRegister(sourceOffset); err != nil { - return err - } - - destinationOffset := c.locationStack.pop() - if err := c.compileEnsureOnRegister(destinationOffset); err != nil { - return err - } - - tmp, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - c.locationStack.markRegisterUsed(tmp) - - // sourceOffset += size. - c.assembler.CompileRegisterToRegister(amd64.ADDQ, copySize.register, sourceOffset.register) - // destinationOffset += size. - c.assembler.CompileRegisterToRegister(amd64.ADDQ, copySize.register, destinationOffset.register) - // tmp = max(sourceOffset, destinationOffset). - c.assembler.CompileRegisterToRegister(amd64.CMPQ, sourceOffset.register, destinationOffset.register) - c.assembler.CompileRegisterToRegister(amd64.MOVQ, sourceOffset.register, tmp) - c.assembler.CompileRegisterToRegister(amd64.CMOVQCS, destinationOffset.register, tmp) - - // Check maximum bounds and if exceeds the length, exit with out of bounds error. - if err := c.compileCompareWithMemorySliceLen(tmp); err != nil { - return err - } - c.compileMaybeExitFromNativeCode(amd64.JCC, nativeCallStatusCodeMemoryOutOfBounds) - - // Skip zero size. - c.assembler.CompileRegisterToRegister(amd64.TESTQ, copySize.register, copySize.register) - skipJump := c.assembler.CompileJump(amd64.JEQ) - - // If dest < source, we can copy forwards - c.assembler.CompileRegisterToRegister(amd64.CMPQ, destinationOffset.register, sourceOffset.register) - destLowerThanSourceJump := c.assembler.CompileJump(amd64.JLS) - - // If source + size < dest, we can copy forwards - c.assembler.CompileRegisterToRegister(amd64.MOVQ, destinationOffset.register, tmp) - c.assembler.CompileRegisterToRegister(amd64.SUBQ, copySize.register, tmp) - c.assembler.CompileRegisterToRegister(amd64.CMPQ, sourceOffset.register, tmp) - sourceBoundLowerThanDestJump := c.assembler.CompileJump(amd64.JLS) - - // Copy backwards. - c.compileMemoryCopyLoopImpl(destinationOffset, sourceOffset, copySize, tmp, true) - endJump := c.assembler.CompileJump(amd64.JMP) - - // Copy forwards. - c.assembler.SetJumpTargetOnNext(destLowerThanSourceJump) - c.assembler.SetJumpTargetOnNext(sourceBoundLowerThanDestJump) - c.compileMemoryCopyLoopImpl(destinationOffset, sourceOffset, copySize, tmp, false) - - c.locationStack.markRegisterUnused(copySize.register, sourceOffset.register, - destinationOffset.register, tmp) - c.assembler.SetJumpTargetOnNext(skipJump) - c.assembler.SetJumpTargetOnNext(endJump) - - return nil -} - -// compileFillLoopImpl implements a REP STOSQ fill loop. -func (c *amd64Compiler) compileFillLoopImpl(destinationOffset, value, fillSize *runtimeValueLocation, tmp asm.Register, replicateByte bool) { - // Skip if nothing to fill. - c.assembler.CompileRegisterToRegister(amd64.TESTQ, fillSize.register, fillSize.register) - emptyEightGroupsJump := c.assembler.CompileJump(amd64.JEQ) - - if replicateByte { - // Truncate value.register to a single byte - c.assembler.CompileConstToRegister(amd64.ANDQ, 0xff, value.register) - // Replicate single byte onto full 8-byte register. - c.assembler.CompileConstToRegister(amd64.MOVQ, 0x0101010101010101, tmp) - c.assembler.CompileRegisterToRegister(amd64.IMULQ, tmp, value.register) - } - - // Prepare registers for swaps. There will never be more than 3 XCHGs in total. - restoreCrossing := c.compilePreventCrossedTargetRegisters( - []*runtimeValueLocation{destinationOffset, value, fillSize}, - []asm.Register{amd64.RegDI, amd64.RegAX, amd64.RegCX}) - - // Prepare registers for REP STOSQ: fill at [rdi] with rax, rcx times. - c.compileMaybeSwapRegisters(destinationOffset.register, amd64.RegDI) - c.compileMaybeSwapRegisters(value.register, amd64.RegAX) - c.compileMaybeSwapRegisters(fillSize.register, amd64.RegCX) - - c.assembler.CompileStandAlone(amd64.REPSTOSQ) - - // Restore registers. - c.compileMaybeSwapRegisters(destinationOffset.register, amd64.RegDI) - c.compileMaybeSwapRegisters(value.register, amd64.RegAX) - c.compileMaybeSwapRegisters(fillSize.register, amd64.RegCX) - restoreCrossing() - - c.assembler.SetJumpTargetOnNext(emptyEightGroupsJump) -} - -// compileMemoryFill implements compiler.compileMemoryFill for the amd64 architecture. -// -// This function uses efficient `REP STOSQ` instructions to copy in quadword (8 bytes) batches -// if the size if above 15 bytes. For smaller sizes, a simple MOVB copy loop is the best -// option. -// -// TODO: the compiled code in this function should be reused and compile at once as -// the code is independent of any module. -func (c *amd64Compiler) compileFillImpl(isTable bool, tableIndex uint32) error { - copySize := c.locationStack.pop() - if err := c.compileEnsureOnRegister(copySize); err != nil { - return err - } - - value := c.locationStack.pop() - if err := c.compileEnsureOnRegister(value); err != nil { - return err - } - - destinationOffset := c.locationStack.pop() - if err := c.compileEnsureOnRegister(destinationOffset); err != nil { - return err - } - - tmp, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - c.locationStack.markRegisterUsed(tmp) - - // destinationOffset += size. - c.assembler.CompileRegisterToRegister(amd64.ADDQ, copySize.register, destinationOffset.register) - - // Check destination bounds and if exceeds the length, exit with out of bounds error. - if isTable { - // tmp = &tables[0] - c.assembler.CompileMemoryToRegister(amd64.MOVQ, - amd64ReservedRegisterForCallEngine, callEngineModuleContextTablesElement0AddressOffset, - tmp) - - // tmp = [tmp + TableIndex*8] - // = [&tables[0] + TableIndex*sizeOf(*tableInstance)] - // = [&tables[TableIndex]] = tables[TableIndex]. - c.assembler.CompileMemoryToRegister(amd64.MOVQ, tmp, int64(tableIndex)*8, tmp) - - c.assembler.CompileMemoryToRegister(amd64.CMPQ, - tmp, tableInstanceTableLenOffset, - destinationOffset.register) - } else { - if err := c.compileCompareWithMemorySliceLen(destinationOffset.register); err != nil { - return err - } - } - if isTable { - c.compileMaybeExitFromNativeCode(amd64.JCC, nativeCallStatusCodeInvalidTableAccess) - } else { - c.compileMaybeExitFromNativeCode(amd64.JCC, nativeCallStatusCodeMemoryOutOfBounds) - } - - // Otherwise, ready to copy the value from source to destination. - // - // If the copy size equal zero, we skip the entire instructions below. - c.assembler.CompileRegisterToRegister(amd64.TESTQ, copySize.register, copySize.register) - skipJump := c.assembler.CompileJump(amd64.JEQ) - - // destinationOffset -= size. - c.assembler.CompileRegisterToRegister(amd64.SUBQ, copySize.register, destinationOffset.register) - - if isTable { - // Each element is of type uintptr; 2^3 = 1 << pointerSizeLog2. - c.assembler.CompileConstToRegister(amd64.SHLQ, pointerSizeLog2, destinationOffset.register) - // destinationOffset += table buffer's absolute address. - c.assembler.CompileMemoryToRegister(amd64.ADDQ, tmp, tableInstanceTableOffset, destinationOffset.register) - - } else { - // destinationOffset += memory buffer's absolute address. - c.assembler.CompileRegisterToRegister(amd64.ADDQ, amd64ReservedRegisterForMemory, destinationOffset.register) - - // Copy first % 16 bytes with simple MOVB instruction. - beginCopyLoop := c.assembler.CompileStandAlone(amd64.NOP) - c.assembler.CompileConstToRegister(amd64.TESTQ, 15, copySize.register) - breakLoop := c.assembler.CompileJump(amd64.JEQ) - - c.assembler.CompileRegisterToMemory(amd64.MOVB, value.register, destinationOffset.register, 0) - - c.assembler.CompileNoneToRegister(amd64.INCQ, destinationOffset.register) - c.assembler.CompileNoneToRegister(amd64.DECQ, copySize.register) - c.assembler.CompileJump(amd64.JMP).AssignJumpTarget(beginCopyLoop) - - c.assembler.SetJumpTargetOnNext(breakLoop) - // compileFillLoopImpl counts in groups of 8 bytes, so we have to divide the copySize by 8. - c.assembler.CompileConstToRegister(amd64.SHRQ, 3, copySize.register) - } - - c.compileFillLoopImpl(destinationOffset, value, copySize, tmp, !isTable) - - c.locationStack.markRegisterUnused(copySize.register, value.register, - destinationOffset.register, tmp) - c.assembler.SetJumpTargetOnNext(skipJump) - return nil -} - -// compileMemoryFill implements compiler.compileMemoryFill for the amd64 architecture. -// -// TODO: the compiled code in this function should be reused and compile at once as -// the code is independent of any module. -func (c *amd64Compiler) compileMemoryFill() error { - return c.compileFillImpl(false, 0) -} - -// compileTableInit implements compiler.compileTableInit for the amd64 architecture. -func (c *amd64Compiler) compileTableInit(o *wazeroir.UnionOperation) error { - elemIndex := uint32(o.U1) - tableIndex := uint32(o.U2) - return c.compileInitImpl(true, elemIndex, tableIndex) -} - -// compileTableCopyLoopImpl is used for directly copying after bounds/direction check. -func (c *amd64Compiler) compileTableCopyLoopImpl(srcTableIndex, dstTableIndex uint32, destinationOffset, sourceOffset, copySize *runtimeValueLocation, tmp asm.Register, backwards bool) { - // Point on first byte to be copied. - if !backwards { - c.assembler.CompileRegisterToRegister(amd64.SUBQ, copySize.register, sourceOffset.register) - c.assembler.CompileRegisterToRegister(amd64.SUBQ, copySize.register, destinationOffset.register) - } - - // Each element is of type uintptr; 2^3 = 1 << pointerSizeLog2. - c.assembler.CompileConstToRegister(amd64.SHLQ, pointerSizeLog2, sourceOffset.register) - c.assembler.CompileConstToRegister(amd64.SHLQ, pointerSizeLog2, destinationOffset.register) - // destinationOffset += table buffer's absolute address. - c.assembler.CompileMemoryToRegister(amd64.MOVQ, amd64ReservedRegisterForCallEngine, callEngineModuleContextTablesElement0AddressOffset, tmp) - c.assembler.CompileMemoryToRegister(amd64.MOVQ, tmp, int64(dstTableIndex*8), tmp) - c.assembler.CompileMemoryToRegister(amd64.ADDQ, tmp, tableInstanceTableOffset, destinationOffset.register) - // sourceOffset += table buffer's absolute address. - c.assembler.CompileMemoryToRegister(amd64.MOVQ, amd64ReservedRegisterForCallEngine, callEngineModuleContextTablesElement0AddressOffset, tmp) - c.assembler.CompileMemoryToRegister(amd64.MOVQ, tmp, int64(srcTableIndex*8), tmp) - c.assembler.CompileMemoryToRegister(amd64.ADDQ, tmp, tableInstanceTableOffset, sourceOffset.register) - - c.compileCopyLoopImpl(destinationOffset, sourceOffset, copySize, backwards, 8) -} - -// compileTableCopy implements compiler.compileTableCopy for the amd64 architecture. -// -// It uses efficient `REP MOVSB` instructions for optimized copying. It uses backward copying for -// overlapped segments. -func (c *amd64Compiler) compileTableCopy(o *wazeroir.UnionOperation) error { - copySize := c.locationStack.pop() - if err := c.compileEnsureOnRegister(copySize); err != nil { - return err - } - - sourceOffset := c.locationStack.pop() - if err := c.compileEnsureOnRegister(sourceOffset); err != nil { - return err - } - - destinationOffset := c.locationStack.pop() - if err := c.compileEnsureOnRegister(destinationOffset); err != nil { - return err - } - - tmp, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - - // sourceOffset += size. - c.assembler.CompileRegisterToRegister(amd64.ADDQ, copySize.register, sourceOffset.register) - // destinationOffset += size. - c.assembler.CompileRegisterToRegister(amd64.ADDQ, copySize.register, destinationOffset.register) - - srcTableIndex := uint32(o.U1) - dstTableIndex := uint32(o.U2) - - // Check source bounds and if exceeds the length, exit with out of bounds error. - c.assembler.CompileMemoryToRegister(amd64.MOVQ, amd64ReservedRegisterForCallEngine, callEngineModuleContextTablesElement0AddressOffset, tmp) - c.assembler.CompileMemoryToRegister(amd64.MOVQ, tmp, int64(srcTableIndex*8), tmp) - c.assembler.CompileMemoryToRegister(amd64.CMPQ, tmp, tableInstanceTableLenOffset, sourceOffset.register) - c.compileMaybeExitFromNativeCode(amd64.JCC, nativeCallStatusCodeInvalidTableAccess) - - // Check destination bounds and if exceeds the length, exit with out of bounds error. - c.assembler.CompileMemoryToRegister(amd64.MOVQ, amd64ReservedRegisterForCallEngine, callEngineModuleContextTablesElement0AddressOffset, tmp) - c.assembler.CompileMemoryToRegister(amd64.MOVQ, tmp, int64(dstTableIndex*8), tmp) - c.assembler.CompileMemoryToRegister(amd64.CMPQ, tmp, tableInstanceTableLenOffset, destinationOffset.register) - c.compileMaybeExitFromNativeCode(amd64.JCC, nativeCallStatusCodeInvalidTableAccess) - - // Skip zero size. - c.assembler.CompileRegisterToRegister(amd64.TESTQ, copySize.register, copySize.register) - skipJump := c.assembler.CompileJump(amd64.JEQ) - - // If dest < source, we can copy forwards. - c.assembler.CompileRegisterToRegister(amd64.CMPQ, destinationOffset.register, sourceOffset.register) - destLowerThanSourceJump := c.assembler.CompileJump(amd64.JLS) - - // If source + size < dest, we can copy forwards. - c.assembler.CompileRegisterToRegister(amd64.MOVQ, destinationOffset.register, tmp) - c.assembler.CompileRegisterToRegister(amd64.SUBQ, copySize.register, tmp) - c.assembler.CompileRegisterToRegister(amd64.CMPQ, sourceOffset.register, tmp) - sourceBoundLowerThanDestJump := c.assembler.CompileJump(amd64.JLS) - - // Copy backwards. - c.compileTableCopyLoopImpl(srcTableIndex, dstTableIndex, destinationOffset, sourceOffset, copySize, tmp, true) - endJump := c.assembler.CompileJump(amd64.JMP) - - // Copy forwards. - c.assembler.SetJumpTargetOnNext(destLowerThanSourceJump) - c.assembler.SetJumpTargetOnNext(sourceBoundLowerThanDestJump) - c.compileTableCopyLoopImpl(srcTableIndex, dstTableIndex, destinationOffset, sourceOffset, copySize, tmp, false) - - c.locationStack.markRegisterUnused(copySize.register, sourceOffset.register, - destinationOffset.register, tmp) - c.assembler.SetJumpTargetOnNext(skipJump) - c.assembler.SetJumpTargetOnNext(endJump) - return nil -} - -// compileElemDrop implements compiler.compileElemDrop for the amd64 architecture. -func (c *amd64Compiler) compileElemDrop(o *wazeroir.UnionOperation) error { - if err := c.maybeCompileMoveTopConditionalToGeneralPurposeRegister(); err != nil { - return err - } - - tmp, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - - elemIndex := uint32(o.U1) - c.compileLoadElemInstanceAddress(elemIndex, tmp) - - // Clears the content of ElementInstances[o.ElemIndex].References (== []uintptr{} type). - c.assembler.CompileConstToMemory(amd64.MOVQ, 0, tmp, 0) - c.assembler.CompileConstToMemory(amd64.MOVQ, 0, tmp, 8) - c.assembler.CompileConstToMemory(amd64.MOVQ, 0, tmp, 16) - return nil -} - -func (c *amd64Compiler) compileLoadElemInstanceAddress(elemIndex uint32, dst asm.Register) { - // dst = elemIndex * elementInstanceStructSize - c.assembler.CompileConstToRegister(amd64.MOVQ, int64(elemIndex)*elementInstanceStructSize, dst) - - // dst = &moduleInstance.ElementInstances[0] + dst - // = &moduleInstance.ElementInstances[0] + elemIndex*elementInstanceStructSize - // = &moduleInstance.ElementInstances[elemIndex] - c.assembler.CompileMemoryToRegister(amd64.ADDQ, - amd64ReservedRegisterForCallEngine, callEngineModuleContextElementInstancesElement0AddressOffset, - dst, - ) -} - -// compileTableGet implements compiler.compileTableGet for the amd64 architecture. -func (c *amd64Compiler) compileTableGet(o *wazeroir.UnionOperation) error { - ref, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - - c.locationStack.markRegisterUsed(ref) - - offset := c.locationStack.pop() - if err := c.compileEnsureOnRegister(offset); err != nil { - return err - } - - // ref = &tables[0] - c.assembler.CompileMemoryToRegister(amd64.MOVQ, - amd64ReservedRegisterForCallEngine, callEngineModuleContextTablesElement0AddressOffset, - ref) - - // ref = [ref + TableIndex*8] - // = [&tables[0] + TableIndex*sizeOf(*tableInstance)] - // = [&tables[TableIndex]] = tables[TableIndex]. - tableIndex := int64(o.U1) - c.assembler.CompileMemoryToRegister(amd64.MOVQ, ref, tableIndex*8, ref) - - // Out of bounds check. - c.assembler.CompileMemoryToRegister(amd64.CMPQ, ref, tableInstanceTableLenOffset, offset.register) - c.compileMaybeExitFromNativeCode(amd64.JHI, nativeCallStatusCodeInvalidTableAccess) - - // ref = [&tables[TableIndex] + tableInstanceTableOffset] = &tables[TableIndex].References[0] - c.assembler.CompileMemoryToRegister(amd64.MOVQ, ref, tableInstanceTableOffset, ref) - - // ref = [ref + 0 + offset.register * 8] - // = [&tables[TableIndex].References[0] + sizeOf(uintptr) * offset] - // = [&tables[TableIndex].References[offset]] - // = tables[TableIndex].References[offset] - c.assembler.CompileMemoryWithIndexToRegister(amd64.MOVQ, ref, - 0, offset.register, 8, ref, - ) - - c.locationStack.markRegisterUnused(offset.register) - c.pushRuntimeValueLocationOnRegister(ref, runtimeValueTypeI64) // table elements are opaque 64-bit at runtime. - return nil -} - -// compileTableSet implements compiler.compileTableSet for the amd64 architecture. -func (c *amd64Compiler) compileTableSet(o *wazeroir.UnionOperation) error { - ref := c.locationStack.pop() - if err := c.compileEnsureOnRegister(ref); err != nil { - return err - } - - offset := c.locationStack.pop() - if err := c.compileEnsureOnRegister(offset); err != nil { - return err - } - - tmp, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - - // tmp = &tables[0] - c.assembler.CompileMemoryToRegister(amd64.MOVQ, - amd64ReservedRegisterForCallEngine, callEngineModuleContextTablesElement0AddressOffset, - tmp) - - // ref = [ref + TableIndex*8] - // = [&tables[0] + TableIndex*sizeOf(*tableInstance)] - // = [&tables[TableIndex]] = tables[TableIndex]. - tableIndex := int64(o.U1) - c.assembler.CompileMemoryToRegister(amd64.MOVQ, tmp, tableIndex*8, tmp) - - // Out of bounds check. - c.assembler.CompileMemoryToRegister(amd64.CMPQ, tmp, tableInstanceTableLenOffset, offset.register) - c.compileMaybeExitFromNativeCode(amd64.JHI, nativeCallStatusCodeInvalidTableAccess) - - // tmp = [&tables[TableIndex] + tableInstanceTableOffset] = &tables[TableIndex].References[0] - c.assembler.CompileMemoryToRegister(amd64.MOVQ, tmp, tableInstanceTableOffset, tmp) - - // [tmp + 0 + offset.register * 8] = ref - // [&tables[TableIndex].References[0] + sizeOf(uintptr) * offset] = ref - // [&tables[TableIndex].References[offset]] = ref - // tables[TableIndex].References[offset] = ref - c.assembler.CompileRegisterToMemoryWithIndex(amd64.MOVQ, - ref.register, - tmp, 0, offset.register, 8) - - c.locationStack.markRegisterUnused(offset.register, ref.register) - return nil -} - -// compileTableGrow implements compiler.compileTableGrow for the amd64 architecture. -func (c *amd64Compiler) compileTableGrow(o *wazeroir.UnionOperation) error { - if err := c.maybeCompileMoveTopConditionalToGeneralPurposeRegister(); err != nil { - return err - } - - // Pushes the table index. - tableIndex := uint32(o.U1) - if err := c.compileConstI32Impl(tableIndex); err != nil { - return err - } - - // Table grow cannot be done in assembly just like memory grow as it involves with allocation in Go. - // Therefore, call out to the built function for this purpose. - if err := c.compileCallBuiltinFunction(builtinFunctionIndexTableGrow); err != nil { - return err - } - - // TableGrow consumes three values (table index, number of items, initial value). - for i := 0; i < 3; i++ { - c.locationStack.pop() - } - - // Then, the previous length was pushed as the result. - loc := c.locationStack.pushRuntimeValueLocationOnStack() - loc.valueType = runtimeValueTypeI32 - - // After return, we re-initialize reserved registers just like preamble of functions. - c.compileReservedStackBasePointerInitialization() - c.compileReservedMemoryPointerInitialization() - return nil -} - -// compileTableSize implements compiler.compileTableSize for the amd64 architecture. -func (c *amd64Compiler) compileTableSize(o *wazeroir.UnionOperation) error { - if err := c.maybeCompileMoveTopConditionalToGeneralPurposeRegister(); err != nil { - return err - } - - result, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - - // result = &tables[0] - c.assembler.CompileMemoryToRegister(amd64.MOVQ, - amd64ReservedRegisterForCallEngine, callEngineModuleContextTablesElement0AddressOffset, - result) - - // result = [result + TableIndex*8] - // = [&tables[0] + TableIndex*sizeOf(*tableInstance)] - // = [&tables[TableIndex]] = tables[TableIndex]. - tableIndex := int64(o.U1) - c.assembler.CompileMemoryToRegister(amd64.MOVQ, result, tableIndex*8, result) - - // result = [result + tableInstanceTableLenOffset] - // = [tables[TableIndex] + tableInstanceTableLenOffset] - // = len(tables[TableIndex]) - c.assembler.CompileMemoryToRegister(amd64.MOVQ, result, tableInstanceTableLenOffset, result) - - c.pushRuntimeValueLocationOnRegister(result, runtimeValueTypeI32) - return nil -} - -// compileTableFill implements compiler.compileTableFill for the amd64 architecture. -func (c *amd64Compiler) compileTableFill(o *wazeroir.UnionOperation) error { - tableIndex := uint32(o.U1) - return c.compileFillImpl(true, tableIndex) -} - -// compileRefFunc implements compiler.compileRefFunc for the amd64 architecture. -func (c *amd64Compiler) compileRefFunc(o *wazeroir.UnionOperation) error { - if err := c.maybeCompileMoveTopConditionalToGeneralPurposeRegister(); err != nil { - return err - } - - ref, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - - functionIndex := int64(o.U1) - c.assembler.CompileConstToRegister(amd64.MOVQ, functionIndex*functionSize, ref) - - // ref = [amd64ReservedRegisterForCallEngine + callEngineModuleContextFunctionsElement0AddressOffset + int64(o.FunctionIndex)*functionSize] - // = &moduleEngine.functions[index] - c.assembler.CompileMemoryToRegister( - amd64.ADDQ, amd64ReservedRegisterForCallEngine, callEngineModuleContextFunctionsElement0AddressOffset, - ref, - ) - - c.pushRuntimeValueLocationOnRegister(ref, runtimeValueTypeI64) - return nil -} - -// compileConstI32 implements compiler.compileConstI32 for the amd64 architecture. -func (c *amd64Compiler) compileConstI32(o *wazeroir.UnionOperation) error { - return c.compileConstI32Impl(uint32(o.U1)) -} - -func (c *amd64Compiler) compileConstI32Impl(v uint32) error { - if err := c.maybeCompileMoveTopConditionalToGeneralPurposeRegister(); err != nil { - return err - } - - reg, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - c.pushRuntimeValueLocationOnRegister(reg, runtimeValueTypeI32) - c.assembler.CompileConstToRegister(amd64.MOVL, int64(v), reg) - return nil -} - -// compileConstI64 implements compiler.compileConstI64 for the amd64 architecture. -func (c *amd64Compiler) compileConstI64(o *wazeroir.UnionOperation) error { - if err := c.maybeCompileMoveTopConditionalToGeneralPurposeRegister(); err != nil { - return err - } - - reg, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - c.pushRuntimeValueLocationOnRegister(reg, runtimeValueTypeI64) - - c.assembler.CompileConstToRegister(amd64.MOVQ, int64(o.U1), reg) - return nil -} - -// compileConstF32 implements compiler.compileConstF32 for the amd64 architecture. -func (c *amd64Compiler) compileConstF32(o *wazeroir.UnionOperation) error { - if err := c.maybeCompileMoveTopConditionalToGeneralPurposeRegister(); err != nil { - return err - } - - reg, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - c.pushRuntimeValueLocationOnRegister(reg, runtimeValueTypeF32) - - // We cannot directly load the value from memory to float regs, - // so we move it to int reg temporarily. - tmpReg, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - - c.assembler.CompileConstToRegister(amd64.MOVL, int64(o.U1) /*math.Float32bits(o.Value)*/, tmpReg) - c.assembler.CompileRegisterToRegister(amd64.MOVL, tmpReg, reg) - return nil -} - -// compileConstF64 implements compiler.compileConstF64 for the amd64 architecture. -func (c *amd64Compiler) compileConstF64(o *wazeroir.UnionOperation) error { - if err := c.maybeCompileMoveTopConditionalToGeneralPurposeRegister(); err != nil { - return err - } - - reg, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - c.pushRuntimeValueLocationOnRegister(reg, runtimeValueTypeF64) - - // We cannot directly load the value from memory to float regs, - // so we move it to int reg temporarily. - tmpReg, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - - c.assembler.CompileConstToRegister(amd64.MOVQ, int64(o.U1) /* math.Float64bits(o.Value) */, tmpReg) - c.assembler.CompileRegisterToRegister(amd64.MOVQ, tmpReg, reg) - return nil -} - -// compileLoadValueOnStackToRegister implements compiler.compileLoadValueOnStackToRegister for amd64. -func (c *amd64Compiler) compileLoadValueOnStackToRegister(loc *runtimeValueLocation) { - var inst asm.Instruction - switch loc.valueType { - case runtimeValueTypeV128Lo: - inst = amd64.MOVDQU - case runtimeValueTypeV128Hi: - panic("BUG: V128Hi must be be loaded to a register along with V128Lo") - case runtimeValueTypeI32, runtimeValueTypeF32: - inst = amd64.MOVL - case runtimeValueTypeI64, runtimeValueTypeF64: - inst = amd64.MOVQ - default: - panic("BUG: unknown runtime value type") - } - - // Copy the value from the stack. - c.assembler.CompileMemoryToRegister(inst, - // Note: stack pointers are ensured not to exceed 2^27 so this offset never exceeds 32-bit range. - amd64ReservedRegisterForStackBasePointerAddress, int64(loc.stackPointer)*8, - loc.register) - - if loc.valueType == runtimeValueTypeV128Lo { - // Higher 64-bits are loaded as well ^^. - hi := &c.locationStack.stack[loc.stackPointer+1] - hi.setRegister(loc.register) - } -} - -// maybeCompileMoveTopConditionalToGeneralPurposeRegister moves the top value on the stack -// if the value is located on a conditional register. -// -// This is usually called at the beginning of methods on compiler interface where we possibly -// compile instructions without saving the conditional register value. -// The compileXXX functions without calling this function is saving the conditional -// value to the stack or register by invoking compileEnsureOnRegister for the top. -func (c *amd64Compiler) maybeCompileMoveTopConditionalToGeneralPurposeRegister() (err error) { - if c.locationStack.sp > 0 { - if loc := c.locationStack.peek(); loc.onConditionalRegister() { - if err = c.compileLoadConditionalRegisterToGeneralPurposeRegister(loc); err != nil { - return err - } - } - } - return -} - -// loadConditionalRegisterToGeneralPurposeRegister saves the conditional register value -// to a general purpose register. -func (c *amd64Compiler) compileLoadConditionalRegisterToGeneralPurposeRegister(loc *runtimeValueLocation) error { - reg, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - c.compileMoveConditionalToGeneralPurposeRegister(loc, reg) - return nil -} - -func (c *amd64Compiler) compileMoveConditionalToGeneralPurposeRegister(loc *runtimeValueLocation, reg asm.Register) { - // Set the flag bit to the destination. See - // - https://c9x.me/x86/html/file_module_x86_id_288.html - // - https://github.com/golang/go/blob/master/src/cmd/internal/obj/x86/asm6.go#L1453-L1468 - // to translate conditionalRegisterState* to amd64.SET* - var inst asm.Instruction - switch loc.conditionalRegister { - case amd64.ConditionalRegisterStateE: - inst = amd64.SETEQ - case amd64.ConditionalRegisterStateNE: - inst = amd64.SETNE - case amd64.ConditionalRegisterStateS: - inst = amd64.SETMI - case amd64.ConditionalRegisterStateNS: - inst = amd64.SETPL - case amd64.ConditionalRegisterStateG: - inst = amd64.SETGT - case amd64.ConditionalRegisterStateGE: - inst = amd64.SETGE - case amd64.ConditionalRegisterStateL: - inst = amd64.SETLT - case amd64.ConditionalRegisterStateLE: - inst = amd64.SETLE - case amd64.ConditionalRegisterStateA: - inst = amd64.SETHI - case amd64.ConditionalRegisterStateAE: - inst = amd64.SETCC - case amd64.ConditionalRegisterStateB: - inst = amd64.SETCS - case amd64.ConditionalRegisterStateBE: - inst = amd64.SETLS - } - - c.assembler.CompileNoneToRegister(inst, reg) - - // Then we reset the unnecessary bit. - c.assembler.CompileConstToRegister(amd64.ANDQ, 0x1, reg) - - // Mark it uses the register. - loc.setRegister(reg) - c.locationStack.markRegisterUsed(reg) -} - -// allocateRegister implements compiler.allocateRegister for amd64. -func (c *amd64Compiler) allocateRegister(t registerType) (reg asm.Register, err error) { - var ok bool - // Try to get the unused register. - reg, ok = c.locationStack.takeFreeRegister(t) - if ok { - return - } - - // If not found, we have to steal the register. - stealTarget, ok := c.locationStack.takeStealTargetFromUsedRegister(t) - if !ok { - err = fmt.Errorf("cannot steal register") - return - } - - // Release the steal target register value onto stack location. - reg = stealTarget.register - c.compileReleaseRegisterToStack(stealTarget) - return -} - -// callFunction adds instructions to call a function whose address equals either addr parameter or the value on indexReg. -// -// Note: this is the counterpart for returnFunction, and see the comments there as well -// to understand how the function calls are achieved. -func (c *amd64Compiler) compileCallFunctionImpl(functionAddressRegister asm.Register, functype *wasm.FunctionType) error { - // Release all the registers as our calling convention requires the caller-save. - if err := c.compileReleaseAllRegistersToStack(); err != nil { - return err - } - - c.locationStack.markRegisterUsed(functionAddressRegister) - - // Obtain a temporary register to be used in the followings. - tmpRegister, found := c.locationStack.takeFreeRegister(registerTypeGeneralPurpose) - if !found { - // This in theory never happen as all the registers must be free except codeAddressRegister. - return fmt.Errorf("could not find enough free registers") - } - - // The stack should look like: - // - // reserved slots for results (if len(results) > len(args)) - // | | - // ,arg0, ..., argN, ..., _, .returnAddress, .returnStackBasePointerInBytes, .function, .... - // | | | - // | callFrame{^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^} - // | - // nextStackBasePointerOffset - // - // where callFrame is used to return to this currently executed function. - - nextStackBasePointerOffset := int64(c.locationStack.sp) - int64(functype.ParamNumInUint64) - - callFrameReturnAddressLoc, callFrameStackBasePointerInBytesLoc, callFrameFunctionLoc := c.locationStack.pushCallFrame(functype) - - // Save the current stack base pointer at callFrameStackBasePointerInBytesLoc. - c.assembler.CompileMemoryToRegister(amd64.MOVQ, - amd64ReservedRegisterForCallEngine, callEngineStackContextStackBasePointerInBytesOffset, - tmpRegister) - callFrameStackBasePointerInBytesLoc.setRegister(tmpRegister) - c.compileReleaseRegisterToStack(callFrameStackBasePointerInBytesLoc) - - // Set callEngine.stackContext.stackBasePointer for the next function. - c.assembler.CompileConstToRegister(amd64.ADDQ, nextStackBasePointerOffset<<3, tmpRegister) - - // Write the calculated value to callEngine.stackContext.stackBasePointer. - c.assembler.CompileRegisterToMemory(amd64.MOVQ, tmpRegister, - amd64ReservedRegisterForCallEngine, callEngineStackContextStackBasePointerInBytesOffset) - - // Save the currently executed *function (placed at callEngine.moduleContext.fn) into callFrameFunctionLoc. - c.assembler.CompileMemoryToRegister(amd64.MOVQ, - amd64ReservedRegisterForCallEngine, callEngineModuleContextFnOffset, - tmpRegister) - callFrameFunctionLoc.setRegister(tmpRegister) - c.compileReleaseRegisterToStack(callFrameFunctionLoc) - - // Set callEngine.moduleContext.fn to the next *function. - c.assembler.CompileRegisterToMemory(amd64.MOVQ, functionAddressRegister, - amd64ReservedRegisterForCallEngine, callEngineModuleContextFnOffset) - - // Write the return address into callFrameReturnAddressLoc. - c.assembler.CompileReadInstructionAddress(tmpRegister, amd64.JMP) - callFrameReturnAddressLoc.setRegister(tmpRegister) - c.compileReleaseRegisterToStack(callFrameReturnAddressLoc) - - if amd64CallingConventionDestinationFunctionModuleInstanceAddressRegister == functionAddressRegister { - // This case we must move the value on targetFunctionAddressRegister to another register, otherwise - // the address (jump target below) will be modified and result in segfault. - // See #526. - c.assembler.CompileRegisterToRegister(amd64.MOVQ, functionAddressRegister, tmpRegister) - functionAddressRegister = tmpRegister - } - - // Also, we have to put the target function's *wasm.ModuleInstance into amd64CallingConventionDestinationFunctionModuleInstanceAddressRegister. - c.assembler.CompileMemoryToRegister(amd64.MOVQ, functionAddressRegister, functionModuleInstanceOffset, - amd64CallingConventionDestinationFunctionModuleInstanceAddressRegister) - - // And jump into the initial address of the target function. - c.assembler.CompileJumpToMemory(amd64.JMP, functionAddressRegister, functionCodeInitialAddressOffset) - - // All the registers used are temporary, so we mark them unused. - c.locationStack.markRegisterUnused(tmpRegister, functionAddressRegister) - - // On the function return, we have to initialize the state. - if err := c.compileModuleContextInitialization(); err != nil { - return err - } - - // Due to the change to callEngine.stackContext.stackBasePointer. - c.compileReservedStackBasePointerInitialization() - - // Due to the change to callEngine.moduleContext.moduleInstance as that might result in - // the memory instance manipulation. - c.compileReservedMemoryPointerInitialization() - - // We consumed the function parameters, the call frame stack and reserved slots during the call. - c.locationStack.sp = uint64(nextStackBasePointerOffset) - - // Now the function results are pushed by the call. - for _, t := range functype.Results { - loc := c.locationStack.pushRuntimeValueLocationOnStack() - switch t { - case wasm.ValueTypeI32: - loc.valueType = runtimeValueTypeI32 - case wasm.ValueTypeI64, wasm.ValueTypeFuncref, wasm.ValueTypeExternref: - loc.valueType = runtimeValueTypeI64 - case wasm.ValueTypeF32: - loc.valueType = runtimeValueTypeF32 - case wasm.ValueTypeF64: - loc.valueType = runtimeValueTypeF64 - case wasm.ValueTypeV128: - loc.valueType = runtimeValueTypeV128Lo - hi := c.locationStack.pushRuntimeValueLocationOnStack() - hi.valueType = runtimeValueTypeV128Hi - default: - panic("BUG: invalid type: " + wasm.ValueTypeName(t)) - } - } - return nil -} - -// returnFunction adds instructions to return from the current callframe back to the caller's frame. -// If this is the current one is the origin, we return to the callEngine.execWasmFunction with the Returned status. -// Otherwise, we jump into the callers' return address stored in callFrame.returnAddress while setting -// up all the necessary change on the callEngine's state. -// -// Note: this is the counterpart for callFunction, and see the comments there as well -// to understand how the function calls are achieved. -func (c *amd64Compiler) compileReturnFunction() error { - // Release all the registers as our calling convention requires the caller-save. - if err := c.compileReleaseAllRegistersToStack(); err != nil { - return err - } - - if c.withListener { - if err := c.compileCallBuiltinFunction(builtinFunctionIndexFunctionListenerAfter); err != nil { - return err - } - // After return, we re-initialize the stack base pointer as that is used to return to the caller below. - c.compileReservedStackBasePointerInitialization() - } - - // amd64CallingConventionDestinationFunctionModuleInstanceAddressRegister holds the module instance's address - // so mark it used so that it won't be used as a free register. - c.locationStack.markRegisterUsed(amd64CallingConventionDestinationFunctionModuleInstanceAddressRegister) - defer c.locationStack.markRegisterUnused(amd64CallingConventionDestinationFunctionModuleInstanceAddressRegister) - - // Obtain a temporary register to be used in the following. - returnAddressRegister, found := c.locationStack.takeFreeRegister(registerTypeGeneralPurpose) - if !found { - panic("BUG: all the registers should be free at this point: " + c.locationStack.String()) - } - - returnAddress, callerStackBasePointerInBytes, callerFunction := c.locationStack.getCallFrameLocations(c.typ) - - // A zero return address means return from the execution. - c.assembler.CompileMemoryToRegister(amd64.MOVQ, - amd64ReservedRegisterForStackBasePointerAddress, int64(returnAddress.stackPointer)*8, - returnAddressRegister, - ) - c.assembler.CompileRegisterToRegister(amd64.TESTQ, returnAddressRegister, returnAddressRegister) - - c.compileMaybeExitFromNativeCode(amd64.JNE, nativeCallStatusCodeReturned) - - // Alias for readability. - tmpRegister := amd64CallingConventionDestinationFunctionModuleInstanceAddressRegister - - // First, restore the stackContext.stackBasePointerInBytesOffset from callerStackBasePointerInBytes. - callerStackBasePointerInBytes.setRegister(tmpRegister) - c.compileLoadValueOnStackToRegister(callerStackBasePointerInBytes) - c.assembler.CompileRegisterToMemory(amd64.MOVQ, - tmpRegister, amd64ReservedRegisterForCallEngine, callEngineStackContextStackBasePointerInBytesOffset) - - // Next, restore moduleContext.fn from callerFunction. - callerFunction.setRegister(tmpRegister) - c.compileLoadValueOnStackToRegister(callerFunction) - c.assembler.CompileRegisterToMemory(amd64.MOVQ, - tmpRegister, amd64ReservedRegisterForCallEngine, callEngineModuleContextFnOffset) - - // Also, we have to put the target function's *wasm.ModuleInstance into amd64CallingConventionDestinationFunctionModuleInstanceAddressRegister. - c.assembler.CompileMemoryToRegister(amd64.MOVQ, - tmpRegister, functionModuleInstanceOffset, - amd64CallingConventionDestinationFunctionModuleInstanceAddressRegister) - - // Then, jump into the return address! - c.assembler.CompileJumpToRegister(amd64.JMP, returnAddressRegister) - return nil -} - -func (c *amd64Compiler) compileCallGoHostFunction() error { - return c.compileCallGoFunction(nativeCallStatusCodeCallGoHostFunction) -} - -func (c *amd64Compiler) compileCallBuiltinFunction(index wasm.Index) error { - // Set the functionAddress to the callEngine.exitContext functionCallAddress. - c.assembler.CompileConstToMemory(amd64.MOVL, int64(index), amd64ReservedRegisterForCallEngine, callEngineExitContextBuiltinFunctionCallIndexOffset) - return c.compileCallGoFunction(nativeCallStatusCodeCallBuiltInFunction) -} - -func (c *amd64Compiler) compileCallGoFunction(compilerStatus nativeCallStatusCode) error { - // Release all the registers as our calling convention requires the caller-save. - if err := c.compileReleaseAllRegistersToStack(); err != nil { - return err - } - - c.compileExitFromNativeCode(compilerStatus) - return nil -} - -// compileReleaseAllRegistersToStack add the instructions to release all the LIVE value -// in the value location stack at this point into the stack memory location. -func (c *amd64Compiler) compileReleaseAllRegistersToStack() (err error) { - for i := uint64(0); i < c.locationStack.sp; i++ { - if loc := &c.locationStack.stack[i]; loc.onRegister() { - c.compileReleaseRegisterToStack(loc) - } else if loc.onConditionalRegister() { - if err = c.compileLoadConditionalRegisterToGeneralPurposeRegister(loc); err != nil { - return - } - c.compileReleaseRegisterToStack(loc) - } - } - return -} - -func (c *amd64Compiler) onValueReleaseRegisterToStack(reg asm.Register) { - for i := uint64(0); i < c.locationStack.sp; i++ { - prevValue := &c.locationStack.stack[i] - if prevValue.register == reg { - c.compileReleaseRegisterToStack(prevValue) - break - } - } -} - -// compileReleaseRegisterToStack implements compiler.compileReleaseRegisterToStack for amd64. -func (c *amd64Compiler) compileReleaseRegisterToStack(loc *runtimeValueLocation) { - var inst asm.Instruction - switch loc.valueType { - case runtimeValueTypeV128Lo: - inst = amd64.MOVDQU - case runtimeValueTypeV128Hi: - panic("BUG: V128Hi must be released to the stack along with V128Lo") - case runtimeValueTypeI32, runtimeValueTypeF32: - inst = amd64.MOVL - case runtimeValueTypeI64, runtimeValueTypeF64: - inst = amd64.MOVQ - default: - panic("BUG: unknown runtime value type") - } - - c.assembler.CompileRegisterToMemory(inst, loc.register, - // Note: stack pointers are ensured not to exceed 2^27 so this offset never exceeds 32-bit range. - amd64ReservedRegisterForStackBasePointerAddress, int64(loc.stackPointer)*8) - - // Mark the register is free. - c.locationStack.releaseRegister(loc) - - if loc.valueType == runtimeValueTypeV128Lo { - // Higher 64-bits are released as well ^^. - hi := &c.locationStack.stack[loc.stackPointer+1] - c.locationStack.releaseRegister(hi) - } -} - -func (c *amd64Compiler) compileMaybeExitFromNativeCode(skipCondition asm.Instruction, status nativeCallStatusCode) { - if target := c.compiledTrapTargets[status]; target != nil { - // We've already compiled this. - // Invert the return condition to jump into the appropriate target. - var returnCondition asm.Instruction - switch skipCondition { - case amd64.JHI: - returnCondition = amd64.JLS - case amd64.JLS: - returnCondition = amd64.JHI - case amd64.JNE: - returnCondition = amd64.JEQ - case amd64.JEQ: - returnCondition = amd64.JNE - case amd64.JCC: - returnCondition = amd64.JCS - case amd64.JCS: - returnCondition = amd64.JCC - case amd64.JPC: - returnCondition = amd64.JPS - case amd64.JPS: - returnCondition = amd64.JPC - case amd64.JPL: - returnCondition = amd64.JMI - case amd64.JMI: - returnCondition = amd64.JPL - default: - panic("BUG: couldn't invert condition") - } - c.assembler.CompileJump(returnCondition).AssignJumpTarget(target) - } else { - skip := c.assembler.CompileJump(skipCondition) - c.compileExitFromNativeCode(status) - c.assembler.SetJumpTargetOnNext(skip) - } -} - -func (c *amd64Compiler) compileExitFromNativeCode(status nativeCallStatusCode) { - if target := c.compiledTrapTargets[status]; target != nil { - c.assembler.CompileJump(amd64.JMP).AssignJumpTarget(target) - return - } - - switch status { - case nativeCallStatusCodeReturned: - // Save the target for reuse. - c.compiledTrapTargets[status] = c.compileNOP() - case nativeCallStatusCodeCallGoHostFunction, nativeCallStatusCodeCallBuiltInFunction: - // Read the return address, and write it to callEngine.exitContext.returnAddress. - returnAddressReg, ok := c.locationStack.takeFreeRegister(registerTypeGeneralPurpose) - if !ok { - panic("BUG: cannot take free register") - } - c.assembler.CompileReadInstructionAddress(returnAddressReg, amd64.RET) - c.assembler.CompileRegisterToMemory(amd64.MOVQ, - returnAddressReg, amd64ReservedRegisterForCallEngine, callEngineExitContextReturnAddressOffset) - default: - if c.ir.IROperationSourceOffsetsInWasmBinary != nil { - // This case, the execution traps and we want the top frame's source position in the stack trace. - // Take RegR15 and store the instruction address onto callEngine.returnAddress. - returnAddressReg := amd64.RegR15 - c.assembler.CompileReadInstructionAddress(returnAddressReg, amd64.MOVQ) - c.assembler.CompileRegisterToMemory(amd64.MOVQ, - returnAddressReg, amd64ReservedRegisterForCallEngine, callEngineExitContextReturnAddressOffset) - } else { - // We won't use the source position, so just save the target for reuse. - c.compiledTrapTargets[status] = c.compileNOP() - } - } - - // Write the status to callEngine.exitContext.statusCode. - c.assembler.CompileConstToMemory(amd64.MOVB, int64(status), - amd64ReservedRegisterForCallEngine, callEngineExitContextNativeCallStatusCodeOffset) - - // Write back the cached SP to the actual eng.stackPointer. - c.assembler.CompileConstToMemory(amd64.MOVQ, int64(c.locationStack.sp), - amd64ReservedRegisterForCallEngine, callEngineStackContextStackPointerOffset) - - c.assembler.CompileStandAlone(amd64.RET) -} - -func (c *amd64Compiler) compilePreamble() (err error) { - // We assume all function parameters are already pushed onto the stack by - // the caller. - c.locationStack.init(c.typ) - - if err := c.compileModuleContextInitialization(); err != nil { - return err - } - - // Check if it's necessary to grow the value stack by using max stack pointer. - if err = c.compileMaybeGrowStack(); err != nil { - return err - } - - if c.withListener { - if err = c.compileCallBuiltinFunction(builtinFunctionIndexFunctionListenerBefore); err != nil { - return err - } - } - - c.compileReservedStackBasePointerInitialization() - - // Finally, we initialize the reserved memory register based on the module context. - c.compileReservedMemoryPointerInitialization() - return -} - -func (c *amd64Compiler) compileReservedStackBasePointerInitialization() { - // First, make reservedRegisterForStackBasePointer point to the beginning of the slice backing array. - c.assembler.CompileMemoryToRegister(amd64.MOVQ, - amd64ReservedRegisterForCallEngine, callEngineStackContextStackElement0AddressOffset, - amd64ReservedRegisterForStackBasePointerAddress) - - // next we move the base pointer (callEngine.stackBasePointer) to the tmp register. - c.assembler.CompileMemoryToRegister(amd64.ADDQ, - amd64ReservedRegisterForCallEngine, callEngineStackContextStackBasePointerInBytesOffset, - amd64ReservedRegisterForStackBasePointerAddress, - ) -} - -func (c *amd64Compiler) compileReservedMemoryPointerInitialization() { - if c.ir.Memory != wazeroir.MemoryTypeNone || c.ir.UsesMemory { - c.assembler.CompileMemoryToRegister(amd64.MOVQ, - amd64ReservedRegisterForCallEngine, callEngineModuleContextMemoryElement0AddressOffset, - amd64ReservedRegisterForMemory, - ) - } -} - -// compileMaybeGrowStack adds instructions to check the necessity to grow the value stack, -// and if so, make the builtin function call to do so. These instructions are called in the function's -// preamble. -func (c *amd64Compiler) compileMaybeGrowStack() error { - tmpRegister, ok := c.locationStack.takeFreeRegister(registerTypeGeneralPurpose) - if !ok { - panic("BUG: cannot take free register") - } - - c.assembler.CompileMemoryToRegister(amd64.MOVQ, - amd64ReservedRegisterForCallEngine, callEngineStackContextStackLenInBytesOffset, tmpRegister) - c.assembler.CompileMemoryToRegister(amd64.SUBQ, - amd64ReservedRegisterForCallEngine, callEngineStackContextStackBasePointerInBytesOffset, tmpRegister) - - // If stack base pointer + max stack pointer > stackLen, we need to grow the stack. - cmpWithStackPointerCeil := c.assembler.CompileRegisterToConst(amd64.CMPQ, tmpRegister, 0) - c.assignStackPointerCeilNeeded = cmpWithStackPointerCeil - - // Jump if we have no need to grow. - jmpIfNoNeedToGrowStack := c.assembler.CompileJump(amd64.JCC) - - // Otherwise, we have to make the builtin function call to grow the call stack. - if err := c.compileCallBuiltinFunction(builtinFunctionIndexGrowStack); err != nil { - return err - } - - c.assembler.SetJumpTargetOnNext(jmpIfNoNeedToGrowStack) - return nil -} - -// compileModuleContextInitialization adds instructions to initialize callEngine.ModuleContext's fields based on -// callEngine.ModuleContext.ModuleInstanceAddress. -// This is called in two cases: in function preamble, and on the return from (non-Go) function calls. -func (c *amd64Compiler) compileModuleContextInitialization() error { - // amd64CallingConventionDestinationFunctionModuleInstanceAddressRegister holds the module instance's address - // so mark it used so that it won't be used as a free register until the module context initialization finishes. - c.locationStack.markRegisterUsed(amd64CallingConventionDestinationFunctionModuleInstanceAddressRegister) - defer c.locationStack.markRegisterUnused(amd64CallingConventionDestinationFunctionModuleInstanceAddressRegister) - - // Obtain the temporary registers to be used in the followings. - tmpRegister, found := c.locationStack.takeFreeRegister(registerTypeGeneralPurpose) - if !found { - // This in theory never happen as all the registers must be free except indexReg. - return fmt.Errorf("could not find enough free registers") - } - c.locationStack.markRegisterUsed(tmpRegister) - tmpRegister2, found := c.locationStack.takeFreeRegister(registerTypeGeneralPurpose) - if !found { - // This in theory never happen as all the registers must be free except indexReg. - return fmt.Errorf("could not find enough free registers") - } - c.locationStack.markRegisterUsed(tmpRegister2) - - // If the module instance address stays the same, we could skip the entire code below. - // The rationale/idea for this is that, in almost all use cases, users instantiate a single - // Wasm binary and run the functions from it, rather than doing import/export on multiple - // binaries. As a result, this cmp and jmp instruction sequence below must be easy for - // x64 CPU to do branch prediction since almost 100% jump happens across function calls. - c.assembler.CompileMemoryToRegister(amd64.CMPQ, - amd64ReservedRegisterForCallEngine, callEngineModuleContextModuleInstanceOffset, amd64CallingConventionDestinationFunctionModuleInstanceAddressRegister) - jmpIfModuleNotChange := c.assembler.CompileJump(amd64.JEQ) - - // If engine.ModuleContext.ModuleInstance is not equal the value on amd64CallingConventionDestinationFunctionModuleInstanceAddressRegister, - // we have to put the new value there. - c.assembler.CompileRegisterToMemory(amd64.MOVQ, amd64CallingConventionDestinationFunctionModuleInstanceAddressRegister, - amd64ReservedRegisterForCallEngine, callEngineModuleContextModuleInstanceOffset) - - // Also, we have to update the following fields: - // * callEngine.moduleContext.globalElement0Address - // * callEngine.moduleContext.tableElement0Address - // * callEngine.moduleContext.memoryInstance - // * callEngine.moduleContext.memoryElement0Address - // * callEngine.moduleContext.memorySliceLen - // * callEngine.moduleContext.codesElement0Address - // * callEngine.moduleContext.typeIDsElement0Address - // * callEngine.moduleContext.dataInstancesElement0Address - // * callEngine.moduleContext.elementInstancesElement0Address - - // Update globalElement0Address. - // - // Note: if there's global.get or set instruction in the function, the existence of the globals - // is ensured by function validation at module instantiation phase, and that's why it is ok to - // skip the initialization if the module's globals slice is empty. - if len(c.ir.Globals) > 0 { - // Since ModuleInstance.Globals is []*globalInstance, internally - // the address of the first item in the underlying array lies exactly on the globals offset. - // See https://go.dev/blog/slices-intro if unfamiliar. - c.assembler.CompileMemoryToRegister(amd64.MOVQ, amd64CallingConventionDestinationFunctionModuleInstanceAddressRegister, moduleInstanceGlobalsOffset, tmpRegister) - - c.assembler.CompileRegisterToMemory(amd64.MOVQ, tmpRegister, amd64ReservedRegisterForCallEngine, callEngineModuleContextGlobalElement0AddressOffset) - } - - // Update tableElement0Address. - // - // Note: if there's table instruction in the function, the existence of the table - // is ensured by function validation at module instantiation phase, and that's - // why it is ok to skip the initialization if the module's table doesn't exist. - if c.ir.HasTable { - // First, we need to read the *wasm.Table. - c.assembler.CompileMemoryToRegister(amd64.MOVQ, amd64CallingConventionDestinationFunctionModuleInstanceAddressRegister, moduleInstanceTablesOffset, tmpRegister) - - // At this point, tmpRegister holds the address of ModuleInstance.Table. - // So we are ready to read and put the first item's address stored in Table.Table. - // Here we read the value into tmpRegister2. - c.assembler.CompileRegisterToMemory(amd64.MOVQ, tmpRegister, - amd64ReservedRegisterForCallEngine, callEngineModuleContextTablesElement0AddressOffset) - - // Finally, we put &ModuleInstance.TypeIDs[0] into moduleContext.typeIDsElement0Address. - c.assembler.CompileMemoryToRegister(amd64.MOVQ, - amd64CallingConventionDestinationFunctionModuleInstanceAddressRegister, moduleInstanceTypeIDsOffset, tmpRegister) - c.assembler.CompileRegisterToMemory(amd64.MOVQ, - tmpRegister, amd64ReservedRegisterForCallEngine, callEngineModuleContextTypeIDsElement0AddressOffset) - } - - // Update memoryElement0Address and memorySliceLen. - // - // Note: if there's memory instruction in the function, memory instance must be non-nil. - // That is ensured by function validation at module instantiation phase, and that's - // why it is ok to skip the initialization if the module's memory instance is nil. - if c.ir.Memory != wazeroir.MemoryTypeNone { - c.assembler.CompileMemoryToRegister(amd64.MOVQ, - amd64CallingConventionDestinationFunctionModuleInstanceAddressRegister, moduleInstanceMemoryOffset, - tmpRegister) - - // Set memory instance. - c.assembler.CompileRegisterToMemory(amd64.MOVQ, tmpRegister, - amd64ReservedRegisterForCallEngine, callEngineModuleContextMemoryInstanceOffset) - - // Set length. - c.assembler.CompileMemoryToRegister(amd64.MOVQ, tmpRegister, memoryInstanceBufferLenOffset, tmpRegister2) - c.assembler.CompileRegisterToMemory(amd64.MOVQ, tmpRegister2, - amd64ReservedRegisterForCallEngine, callEngineModuleContextMemorySliceLenOffset) - - // Set element zero address. - c.assembler.CompileMemoryToRegister(amd64.MOVQ, tmpRegister, memoryInstanceBufferOffset, tmpRegister2) - c.assembler.CompileRegisterToMemory(amd64.MOVQ, tmpRegister2, - amd64ReservedRegisterForCallEngine, callEngineModuleContextMemoryElement0AddressOffset) - } - - // Update moduleContext.codesElement0Address - { - // "tmpRegister = [moduleInstanceAddressRegister + moduleInstanceEngineOffset + interfaceDataOffset] (== *moduleEngine)" - // - // Go's interface is laid out on memory as two quad words as struct {tab, data uintptr} - // where tab points to the interface table, and the latter points to the actual - // implementation of interface. This case, we extract "data" pointer as *moduleEngine. - // See the following references for detail: - // * https://research.swtch.com/interfaces - // * https://github.com/golang/go/blob/release-branch.go1.20/src/runtime/runtime2.go#L207-L210 - c.assembler.CompileMemoryToRegister(amd64.MOVQ, amd64CallingConventionDestinationFunctionModuleInstanceAddressRegister, moduleInstanceEngineOffset+interfaceDataOffset, tmpRegister) - - // "tmpRegister = [tmpRegister + moduleEnginecodesOffset] (== &moduleEngine.codes[0])" - c.assembler.CompileMemoryToRegister(amd64.MOVQ, tmpRegister, moduleEngineFunctionsOffset, tmpRegister) - - // "callEngine.moduleContext.functionsElement0Address = tmpRegister". - c.assembler.CompileRegisterToMemory(amd64.MOVQ, tmpRegister, amd64ReservedRegisterForCallEngine, - callEngineModuleContextFunctionsElement0AddressOffset) - } - - // Update dataInstancesElement0Address. - if c.ir.HasDataInstances { - // "tmpRegister = &moduleInstance.DataInstances[0]" - c.assembler.CompileMemoryToRegister( - amd64.MOVQ, - amd64CallingConventionDestinationFunctionModuleInstanceAddressRegister, moduleInstanceDataInstancesOffset, - tmpRegister, - ) - // "callEngine.moduleContext.dataInstancesElement0Address = tmpRegister". - c.assembler.CompileRegisterToMemory( - amd64.MOVQ, - tmpRegister, - amd64ReservedRegisterForCallEngine, callEngineModuleContextDataInstancesElement0AddressOffset, - ) - } - - // Update callEngine.moduleContext.elementInstancesElement0Address - if c.ir.HasElementInstances { - // "tmpRegister = &moduleInstance.ElementInstnaces[0]" - c.assembler.CompileMemoryToRegister( - amd64.MOVQ, - amd64CallingConventionDestinationFunctionModuleInstanceAddressRegister, moduleInstanceElementInstancesOffset, - tmpRegister, - ) - // "callEngine.moduleContext.dataInstancesElement0Address = tmpRegister". - c.assembler.CompileRegisterToMemory( - amd64.MOVQ, - tmpRegister, - amd64ReservedRegisterForCallEngine, callEngineModuleContextElementInstancesElement0AddressOffset, - ) - } - - c.locationStack.markRegisterUnused(tmpRegister, tmpRegister2) - - // Set the jump target towards the next instruction for the case where module instance address hasn't changed. - c.assembler.SetJumpTargetOnNext(jmpIfModuleNotChange) - return nil -} - -// compileEnsureOnRegister ensures that the given value is located on a -// general purpose register of an appropriate type. -func (c *amd64Compiler) compileEnsureOnRegister(loc *runtimeValueLocation) (err error) { - if loc.onStack() { - // Allocate the register. - reg, err := c.allocateRegister(loc.getRegisterType()) - if err != nil { - return err - } - - // Mark it uses the register. - loc.setRegister(reg) - c.locationStack.markRegisterUsed(reg) - - c.compileLoadValueOnStackToRegister(loc) - } else if loc.onConditionalRegister() { - err = c.compileLoadConditionalRegisterToGeneralPurposeRegister(loc) - } - return -} - -// compileMaybeSwapRegisters swaps two registers if they're not equal. -func (c *amd64Compiler) compileMaybeSwapRegisters(reg1, reg2 asm.Register) { - if reg1 != reg2 { - c.assembler.CompileRegisterToRegister(amd64.XCHGQ, reg1, reg2) - } -} - -func (c *amd64Compiler) compileCompareWithMemorySliceLen(addrReg asm.Register) error { - if c.ir.Memory != wazeroir.MemoryTypeShared { - // No concurrent accesses so the length we cached during the preamble is still valid. - c.assembler.CompileMemoryToRegister(amd64.CMPQ, - amd64ReservedRegisterForCallEngine, callEngineModuleContextMemorySliceLenOffset, addrReg) - return nil - } - // Obtain the temporary registers to be used in the followings. - tmpRegister, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - - c.assembler.CompileMemoryToRegister(amd64.MOVQ, - amd64ReservedRegisterForCallEngine, callEngineModuleContextMemoryInstanceOffset, - tmpRegister) - - c.assembler.CompileMemoryToRegister(amd64.CMPQ, tmpRegister, memoryInstanceBufferLenOffset, addrReg) - - c.locationStack.markRegisterUnused(tmpRegister) - - return nil -} - -// compilePreventCrossedTargetRegisters swaps registers in such a way, that for neither runtimeValueLocation from locs its -// corresponding register with the same index from targets is occupied by some other runtimeValueLocation from locs. It returns a -// closure to restore the original register placement. -// -// This function makes it possible to safely exchange one set of registers with another, where a register might be in both sets. -// Each register will correspond either to itself or another register not present in its own set. -// -// For example, if we have locs = [AX, BX, CX], targets = [BX, SI, AX], then it'll do two swaps -// to make locs = [BX, CX, AX]. -func (c *amd64Compiler) compilePreventCrossedTargetRegisters(locs []*runtimeValueLocation, targets []asm.Register) (restore func()) { - type swap struct{ srcIndex, dstIndex int } - var swaps []swap - for i := range locs { - targetLocation := -1 // -1 means not found. - for j := range locs { - if locs[j].register == targets[i] { - targetLocation = j - break - } - } - if targetLocation != -1 && targetLocation != i { - c.compileMaybeSwapRegisters(locs[i].register, locs[targetLocation].register) - locs[i].register, locs[targetLocation].register = locs[targetLocation].register, locs[i].register - swaps = append(swaps, swap{i, targetLocation}) - } - } - return func() { - // Restore in reverse order because a register can be moved multiple times. - for i := len(swaps) - 1; i >= 0; i -= 1 { - r1, r2 := swaps[i].srcIndex, swaps[i].dstIndex - c.compileMaybeSwapRegisters(locs[r1].register, locs[r2].register) - locs[r1].register, locs[r2].register = locs[r2].register, locs[r1].register - } - } -} diff --git a/internal/engine/compiler/impl_amd64_test.go b/internal/engine/compiler/impl_amd64_test.go deleted file mode 100644 index f6a8a6ae7c..0000000000 --- a/internal/engine/compiler/impl_amd64_test.go +++ /dev/null @@ -1,744 +0,0 @@ -package compiler - -import ( - "encoding/hex" - "testing" - "unsafe" - - "github.com/tetratelabs/wazero/internal/asm" - "github.com/tetratelabs/wazero/internal/asm/amd64" - "github.com/tetratelabs/wazero/internal/platform" - "github.com/tetratelabs/wazero/internal/testing/require" - "github.com/tetratelabs/wazero/internal/wasm" - "github.com/tetratelabs/wazero/internal/wazeroir" -) - -// TestAmd64Compiler_indirectCallWithTargetOnCallingConvReg is the regression test for #526. -// In short, the offset register for call_indirect might be the same as amd64CallingConventionDestinationFunctionModuleInstanceAddressRegister -// and that must not be a failure. -func TestAmd64Compiler_indirectCallWithTargetOnCallingConvReg(t *testing.T) { - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - env := newCompilerEnvironment() - table := make([]wasm.Reference, 1) - env.addTable(&wasm.TableInstance{References: table}) - // Ensure that the module instance has the type information for targetOperation.TypeIndex, - // and the typeID matches the table[targetOffset]'s type ID. - operation := operationPtr(wazeroir.NewOperationCallIndirect(0, 0)) - env.module().TypeIDs = []wasm.FunctionTypeID{0} - env.module().Engine = &moduleEngine{functions: []function{}} - - me := env.moduleEngine() - { // Compiling call target. - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, nil) - err := compiler.compilePreamble() - require.NoError(t, err) - err = compiler.compileReturnFunction() - require.NoError(t, err) - - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - - executable := code.Bytes() - makeExecutable(executable) - - f := function{ - parent: &compiledFunction{parent: &compiledCode{executable: code}}, - codeInitialAddress: code.Addr(), - moduleInstance: env.moduleInstance, - typeID: 0, - } - me.functions = append(me.functions, f) - table[0] = uintptr(unsafe.Pointer(&f)) - } - - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, &wazeroir.CompilationResult{ - Types: []wasm.FunctionType{{}}, - HasTable: true, - }).(*amd64Compiler) - err := compiler.compilePreamble() - require.NoError(t, err) - - // Place the offset into the calling-convention reserved register. - offsetLoc := compiler.pushRuntimeValueLocationOnRegister(amd64CallingConventionDestinationFunctionModuleInstanceAddressRegister, - runtimeValueTypeI32) - compiler.assembler.CompileConstToRegister(amd64.MOVQ, 0, offsetLoc.register) - - require.NoError(t, compiler.compileCallIndirect(operation)) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - // Generate the code under test and run. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) -} - -func TestAmd64Compiler_compile_Mul_Div_Rem(t *testing.T) { - for _, kind := range []wazeroir.OperationKind{ - wazeroir.OperationKindMul, - wazeroir.OperationKindDiv, - wazeroir.OperationKindRem, - } { - kind := kind - t.Run(kind.String(), func(t *testing.T) { - t.Run("int32", func(t *testing.T) { - tests := []struct { - name string - x1Reg, x2Reg asm.Register - }{ - { - name: "x1:ax,x2:random_reg", - x1Reg: amd64.RegAX, - x2Reg: amd64.RegR10, - }, - { - name: "x1:ax,x2:stack", - x1Reg: amd64.RegAX, - x2Reg: asm.NilRegister, - }, - { - name: "x1:random_reg,x2:ax", - x1Reg: amd64.RegR10, - x2Reg: amd64.RegAX, - }, - { - name: "x1:stack,x2:ax", - x1Reg: asm.NilRegister, - x2Reg: amd64.RegAX, - }, - { - name: "x1:random_reg,x2:random_reg", - x1Reg: amd64.RegR10, - x2Reg: amd64.RegR9, - }, - { - name: "x1:stack,x2:random_reg", - x1Reg: asm.NilRegister, - x2Reg: amd64.RegR9, - }, - { - name: "x1:random_reg,x2:stack", - x1Reg: amd64.RegR9, - x2Reg: asm.NilRegister, - }, - { - name: "x1:stack,x2:stack", - x1Reg: asm.NilRegister, - x2Reg: asm.NilRegister, - }, - } - - for _, tt := range tests { - tc := tt - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - - const x1Value uint32 = 1 << 11 - const x2Value uint32 = 51 - const dxValue uint64 = 111111 - - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newAmd64Compiler, nil).(*amd64Compiler) - - // To make the assertion below stable, we preallocate the underlying stack, - // so that the pointer to the entry will be stale. - compiler.runtimeValueLocationStack().stack = make([]runtimeValueLocation, 100) - - err := compiler.compilePreamble() - require.NoError(t, err) - - // Pretend there was an existing value on the DX register. We expect compileMul to save this to the stack. - // Here, we put it just before two operands as ["any value used by DX", x1, x2] - // but in reality, it can exist in any position of stack. - compiler.assembler.CompileConstToRegister(amd64.MOVQ, int64(dxValue), amd64.RegDX) - prevOnDX := compiler.pushRuntimeValueLocationOnRegister(amd64.RegDX, runtimeValueTypeI32) - - // Setup values. - if tc.x1Reg != asm.NilRegister { - compiler.assembler.CompileConstToRegister(amd64.MOVQ, int64(x1Value), tc.x1Reg) - compiler.pushRuntimeValueLocationOnRegister(tc.x1Reg, runtimeValueTypeI32) - } else { - loc := compiler.runtimeValueLocationStack().pushRuntimeValueLocationOnStack() - loc.valueType = runtimeValueTypeI32 - env.stack()[loc.stackPointer] = uint64(x1Value) - } - if tc.x2Reg != asm.NilRegister { - compiler.assembler.CompileConstToRegister(amd64.MOVQ, int64(x2Value), tc.x2Reg) - compiler.pushRuntimeValueLocationOnRegister(tc.x2Reg, runtimeValueTypeI32) - } else { - loc := compiler.runtimeValueLocationStack().pushRuntimeValueLocationOnStack() - loc.valueType = runtimeValueTypeI32 - env.stack()[loc.stackPointer] = uint64(x2Value) - } - - switch kind { - case wazeroir.OperationKindDiv: - err = compiler.compileDiv(operationPtr(wazeroir.NewOperationDiv(wazeroir.SignedTypeUint32))) - case wazeroir.OperationKindMul: - err = compiler.compileMul(operationPtr(wazeroir.NewOperationMul(wazeroir.UnsignedTypeI32))) - case wazeroir.OperationKindRem: - err = compiler.compileRem(operationPtr(wazeroir.NewOperationRem(wazeroir.SignedUint32))) - } - require.NoError(t, err) - - require.Equal(t, registerTypeGeneralPurpose, compiler.runtimeValueLocationStack().peek().getRegisterType()) - requireRuntimeLocationStackPointerEqual(t, uint64(2), compiler) - require.Equal(t, 1, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - // At this point, the previous value on the DX register is saved to the stack. - require.True(t, prevOnDX.onStack()) - - // We add the value previously on the DX with the multiplication result - // in order to ensure that not saving existing DX value would cause - // the failure in a subsequent instruction. - err = compiler.compileAdd(operationPtr(wazeroir.NewOperationAdd(wazeroir.UnsignedTypeI32))) - require.NoError(t, err) - require.NoError(t, compiler.compileReturnFunction()) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - // Run code. - env.exec(code.Bytes()) - - // Verify the stack is in the form of ["any value previously used by DX" + the result of operation] - require.Equal(t, uint64(1), env.stackPointer()) - switch kind { - case wazeroir.OperationKindDiv: - require.Equal(t, x1Value/x2Value+uint32(dxValue), env.stackTopAsUint32()) - case wazeroir.OperationKindMul: - require.Equal(t, x1Value*x2Value+uint32(dxValue), env.stackTopAsUint32()) - case wazeroir.OperationKindRem: - require.Equal(t, x1Value%x2Value+uint32(dxValue), env.stackTopAsUint32()) - } - }) - } - }) - t.Run("int64", func(t *testing.T) { - tests := []struct { - name string - x1Reg, x2Reg asm.Register - }{ - { - name: "x1:ax,x2:random_reg", - x1Reg: amd64.RegAX, - x2Reg: amd64.RegR10, - }, - { - name: "x1:ax,x2:stack", - x1Reg: amd64.RegAX, - x2Reg: asm.NilRegister, - }, - { - name: "x1:random_reg,x2:ax", - x1Reg: amd64.RegR10, - x2Reg: amd64.RegAX, - }, - { - name: "x1:stack,x2:ax", - x1Reg: asm.NilRegister, - x2Reg: amd64.RegAX, - }, - { - name: "x1:random_reg,x2:random_reg", - x1Reg: amd64.RegR10, - x2Reg: amd64.RegR9, - }, - { - name: "x1:stack,x2:random_reg", - x1Reg: asm.NilRegister, - x2Reg: amd64.RegR9, - }, - { - name: "x1:random_reg,x2:stack", - x1Reg: amd64.RegR9, - x2Reg: asm.NilRegister, - }, - { - name: "x1:stack,x2:stack", - x1Reg: asm.NilRegister, - x2Reg: asm.NilRegister, - }, - } - - for _, tt := range tests { - tc := tt - t.Run(tc.name, func(t *testing.T) { - const x1Value uint64 = 1 << 35 - const x2Value uint64 = 51 - const dxValue uint64 = 111111 - - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newAmd64Compiler, nil).(*amd64Compiler) - - // To make the assertion below stable, we preallocate the underlying stack, - // so that the pointer to the entry will be stale. - compiler.runtimeValueLocationStack().stack = make([]runtimeValueLocation, 100) - - err := compiler.compilePreamble() - require.NoError(t, err) - - // Pretend there was an existing value on the DX register. We expect compileMul to save this to the stack. - // Here, we put it just before two operands as ["any value used by DX", x1, x2] - // but in reality, it can exist in any position of stack. - compiler.assembler.CompileConstToRegister(amd64.MOVQ, int64(dxValue), amd64.RegDX) - prevOnDX := compiler.pushRuntimeValueLocationOnRegister(amd64.RegDX, runtimeValueTypeI64) - - // Setup values. - if tc.x1Reg != asm.NilRegister { - compiler.assembler.CompileConstToRegister(amd64.MOVQ, int64(x1Value), tc.x1Reg) - compiler.pushRuntimeValueLocationOnRegister(tc.x1Reg, runtimeValueTypeI64) - } else { - loc := compiler.runtimeValueLocationStack().pushRuntimeValueLocationOnStack() - loc.valueType = runtimeValueTypeI64 - env.stack()[loc.stackPointer] = uint64(x1Value) - } - if tc.x2Reg != asm.NilRegister { - compiler.assembler.CompileConstToRegister(amd64.MOVQ, int64(x2Value), tc.x2Reg) - compiler.pushRuntimeValueLocationOnRegister(tc.x2Reg, runtimeValueTypeI64) - } else { - loc := compiler.runtimeValueLocationStack().pushRuntimeValueLocationOnStack() - loc.valueType = runtimeValueTypeI64 - env.stack()[loc.stackPointer] = uint64(x2Value) - } - - switch kind { - case wazeroir.OperationKindDiv: - err = compiler.compileDiv(operationPtr(wazeroir.NewOperationDiv(wazeroir.SignedTypeInt64))) - case wazeroir.OperationKindMul: - err = compiler.compileMul(operationPtr(wazeroir.NewOperationMul(wazeroir.UnsignedTypeI64))) - case wazeroir.OperationKindRem: - err = compiler.compileRem(operationPtr(wazeroir.NewOperationRem(wazeroir.SignedUint64))) - } - require.NoError(t, err) - - require.Equal(t, registerTypeGeneralPurpose, compiler.runtimeValueLocationStack().peek().getRegisterType()) - requireRuntimeLocationStackPointerEqual(t, uint64(2), compiler) - require.Equal(t, 1, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - // At this point, the previous value on the DX register is saved to the stack. - require.True(t, prevOnDX.onStack()) - - // We add the value previously on the DX with the multiplication result - // in order to ensure that not saving existing DX value would cause - // the failure in a subsequent instruction. - err = compiler.compileAdd(operationPtr(wazeroir.NewOperationAdd(wazeroir.UnsignedTypeI64))) - require.NoError(t, err) - require.NoError(t, compiler.compileReturnFunction()) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - - // Run code. - env.exec(code.Bytes()) - - // Verify the stack is in the form of ["any value previously used by DX" + the result of operation] - switch kind { - case wazeroir.OperationKindDiv: - require.Equal(t, uint64(1), env.stackPointer()) - require.Equal(t, uint64(x1Value/x2Value)+dxValue, env.stackTopAsUint64()) - case wazeroir.OperationKindMul: - require.Equal(t, uint64(1), env.stackPointer()) - require.Equal(t, uint64(x1Value*x2Value)+dxValue, env.stackTopAsUint64()) - case wazeroir.OperationKindRem: - require.Equal(t, uint64(1), env.stackPointer()) - require.Equal(t, x1Value%x2Value+dxValue, env.stackTopAsUint64()) - } - }) - } - }) - }) - } -} - -func TestAmd64Compiler_readInstructionAddress(t *testing.T) { - t.Run("invalid", func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newAmd64Compiler, nil).(*amd64Compiler) - - err := compiler.compilePreamble() - require.NoError(t, err) - - // Set the acquisition target instruction to the one after JMP. - compiler.assembler.CompileReadInstructionAddress(amd64.RegAX, amd64.JMP) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // If generate the code without JMP after readInstructionAddress, - // the call back added must return error. - _, err = compiler.compile(code.NextCodeSection()) - require.Error(t, err) - }) - - t.Run("ok", func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newAmd64Compiler, nil).(*amd64Compiler) - - err := compiler.compilePreamble() - require.NoError(t, err) - - const destinationRegister = amd64.RegAX - // Set the acquisition target instruction to the one after RET, - // and read the absolute address into destinationRegister. - compiler.assembler.CompileReadInstructionAddress(destinationRegister, amd64.RET) - - // Jump to the instruction after RET below via the absolute - // address stored in destinationRegister. - compiler.assembler.CompileJumpToRegister(amd64.JMP, destinationRegister) - - compiler.assembler.CompileStandAlone(amd64.RET) - - // This could be the read instruction target as this is the - // right after RET. Therefore, the jmp instruction above - // must target here. - const expectedReturnValue uint32 = 10000 - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(expectedReturnValue))) - require.NoError(t, err) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - - // Run code. - env.exec(code.Bytes()) - - require.Equal(t, nativeCallStatusCodeReturned, env.compilerStatus()) - require.Equal(t, uint64(1), env.stackPointer()) - require.Equal(t, expectedReturnValue, env.stackTopAsUint32()) - }) -} - -func TestAmd64Compiler_preventCrossedTargetdRegisters(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newAmd64Compiler, nil).(*amd64Compiler) - - tests := []struct { - initial []*runtimeValueLocation - desired, expected []asm.Register - }{ - { - initial: []*runtimeValueLocation{{register: amd64.RegAX}, {register: amd64.RegCX}, {register: amd64.RegDX}}, - desired: []asm.Register{amd64.RegDX, amd64.RegCX, amd64.RegAX}, - expected: []asm.Register{amd64.RegDX, amd64.RegCX, amd64.RegAX}, - }, - { - initial: []*runtimeValueLocation{{register: amd64.RegAX}, {register: amd64.RegCX}, {register: amd64.RegDX}}, - desired: []asm.Register{amd64.RegDX, amd64.RegAX, amd64.RegCX}, - expected: []asm.Register{amd64.RegDX, amd64.RegAX, amd64.RegCX}, - }, - { - initial: []*runtimeValueLocation{{register: amd64.RegR8}, {register: amd64.RegR9}, {register: amd64.RegR10}}, - desired: []asm.Register{amd64.RegR8, amd64.RegR9, amd64.RegR10}, - expected: []asm.Register{amd64.RegR8, amd64.RegR9, amd64.RegR10}, - }, - { - initial: []*runtimeValueLocation{{register: amd64.RegBX}, {register: amd64.RegDX}, {register: amd64.RegCX}}, - desired: []asm.Register{amd64.RegR8, amd64.RegR9, amd64.RegR10}, - expected: []asm.Register{amd64.RegBX, amd64.RegDX, amd64.RegCX}, - }, - { - initial: []*runtimeValueLocation{{register: amd64.RegR8}, {register: amd64.RegR9}, {register: amd64.RegR10}}, - desired: []asm.Register{amd64.RegAX, amd64.RegCX, amd64.RegR9}, - expected: []asm.Register{amd64.RegR8, amd64.RegR10, amd64.RegR9}, - }, - } - - for _, tt := range tests { - initialRegisters := collectRegistersFromRuntimeValues(tt.initial) - restoreCrossing := compiler.compilePreventCrossedTargetRegisters(tt.initial, tt.desired) - // Required expected state after prevented crossing. - require.Equal(t, tt.expected, collectRegistersFromRuntimeValues(tt.initial)) - restoreCrossing() - // Require initial state after restoring. - require.Equal(t, initialRegisters, collectRegistersFromRuntimeValues(tt.initial)) - } -} - -// mockCpuFlags implements platform.CpuFeatureFlags -type mockCpuFlags struct { - flags platform.CpuFeature - extraFlags platform.CpuFeature -} - -// Has implements the method of the same name in platform.CpuFeatureFlags -func (f *mockCpuFlags) Has(flag platform.CpuFeature) bool { - return (f.flags & flag) != 0 -} - -// HasExtra implements the method of the same name in platform.CpuFeatureFlags -func (f *mockCpuFlags) HasExtra(flag platform.CpuFeature) bool { - return (f.extraFlags & flag) != 0 -} - -// Relates to #1111 (Clz): older AMD64 CPUs do not support the LZCNT instruction -// CPUID should be used instead. We simulate presence/absence of the feature -// by overriding the field in the corresponding struct. -func TestAmd64Compiler_ensureClz_ABM(t *testing.T) { - tests := []struct { - name string - cpuFeatures platform.CpuFeatureFlags - expectedCode string - }{ - { - name: "with ABM", - expectedCode: "b80a000000f3480fbdc0", - cpuFeatures: &mockCpuFlags{ - flags: 0, - extraFlags: platform.CpuExtraFeatureAmd64ABM, - }, - }, - { - name: "without ABM", - expectedCode: "b80a0000004885c07507b840000000eb08480fbdc04883f03f", - cpuFeatures: &mockCpuFlags{ - flags: 0, - extraFlags: 0, // no flags, thus no ABM, i.e. no LZCNT - }, - }, - } - for _, tt := range tests { - t.Run(tt.name, func(t *testing.T) { - env := newCompilerEnvironment() - - newCompiler := func() compiler { - c := newCompiler().(*amd64Compiler) - // override auto-detected CPU features with the test case - c.cpuFeatures = tt.cpuFeatures - return c - } - - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, nil) - - err := compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(10))) - require.NoError(t, err) - - err = compiler.compileClz(operationPtr(wazeroir.NewOperationClz(wazeroir.UnsignedInt64))) - require.NoError(t, err) - - compiler.compileNOP() // pad for jump target (when no ABM) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - buf := code.NextCodeSection() - _, err = compiler.compile(buf) - require.NoError(t, err) - require.Equal(t, tt.expectedCode, hex.EncodeToString(buf.Bytes())) - }) - } -} - -// Relates to #1111 (Ctz): older AMD64 CPUs do not support the LZCNT instruction -// CPUID should be used instead. We simulate presence/absence of the feature -// by overriding the field in the corresponding struct. -func TestAmd64Compiler_ensureCtz_ABM(t *testing.T) { - tests := []struct { - name string - cpuFeatures platform.CpuFeatureFlags - expectedCode string - }{ - { - name: "with ABM", - expectedCode: "b80a000000f3480fbcc0", - cpuFeatures: &mockCpuFlags{ - flags: 0, - extraFlags: platform.CpuExtraFeatureAmd64ABM, - }, - }, - { - name: "without ABM", - expectedCode: "b80a0000004885c07507b840000000eb05f3480fbcc0", - cpuFeatures: &mockCpuFlags{ - flags: 0, - extraFlags: 0, // no flags, thus no ABM, i.e. no LZCNT - }, - }, - } - for _, tt := range tests { - t.Run(tt.name, func(t *testing.T) { - env := newCompilerEnvironment() - - newCompiler := func() compiler { - c := newCompiler().(*amd64Compiler) - // override auto-detected CPU features with the test case - c.cpuFeatures = tt.cpuFeatures - return c - } - - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, nil) - - err := compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(10))) - require.NoError(t, err) - - err = compiler.compileCtz(operationPtr(wazeroir.NewOperationCtz(wazeroir.UnsignedInt64))) - require.NoError(t, err) - - compiler.compileNOP() // pad for jump target (when no ABM) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - buf := code.NextCodeSection() - _, err = compiler.compile(buf) - require.NoError(t, err) - require.Equal(t, tt.expectedCode, hex.EncodeToString(buf.Bytes())) - }) - } -} - -// collectRegistersFromRuntimeValues returns the registers occupied by locs. -func collectRegistersFromRuntimeValues(locs []*runtimeValueLocation) []asm.Register { - out := make([]asm.Register, len(locs)) - for i := range locs { - out[i] = locs[i].register - } - return out -} - -// compile implements compilerImpl.setStackPointerCeil for the amd64 architecture. -func (c *amd64Compiler) setStackPointerCeil(v uint64) { - c.stackPointerCeil = v -} - -// compile implements compilerImpl.setRuntimeValueLocationStack for the amd64 architecture. -func (c *amd64Compiler) setRuntimeValueLocationStack(s *runtimeValueLocationStack) { - c.locationStack = s -} - -func TestAmd64Compiler_label(t *testing.T) { - c := &amd64Compiler{} - c.label(wazeroir.NewLabel(wazeroir.LabelKindContinuation, 100)) - require.Equal(t, 100, c.frameIDMax) - require.Equal(t, 101, len(c.labels[wazeroir.LabelKindContinuation])) - - // frameIDMax is for all LabelKind, so this shouldn't change frameIDMax. - c.label(wazeroir.NewLabel(wazeroir.LabelKindHeader, 2)) - require.Equal(t, 100, c.frameIDMax) - require.Equal(t, 3, len(c.labels[wazeroir.LabelKindHeader])) -} - -func TestAmd64Compiler_Init(t *testing.T) { - c := &amd64Compiler{ - locationStackForEntrypoint: newRuntimeValueLocationStack(), - assembler: amd64.NewAssembler(), - } - const stackCap = 12345 - c.locationStackForEntrypoint.stack = make([]runtimeValueLocation, stackCap) - c.locationStackForEntrypoint.sp = 5555 - - c.Init(&wasm.FunctionType{}, nil, false) - - // locationStack is the pointer to locationStackForEntrypoint after init. - require.Equal(t, c.locationStack, &c.locationStackForEntrypoint) - // And the underlying stack must be reused (the capacity preserved). - require.Equal(t, stackCap, cap(c.locationStack.stack)) - require.Equal(t, stackCap, cap(c.locationStackForEntrypoint.stack)) -} - -func TestAmd64Compiler_resetLabels(t *testing.T) { - c := newAmd64Compiler().(*amd64Compiler) - nop := c.compileNOP() - - const ( - frameIDMax = 50 - capacity = 12345 - ) - c.frameIDMax = frameIDMax - for i := range c.labels { - ifs := make([]amd64LabelInfo, frameIDMax*2) - c.labels[i] = ifs - for j := 0; j <= frameIDMax; j++ { - ifs[j].stackInitialized = true - ifs[j].initialInstruction = nop - ifs[j].initialStack = newRuntimeValueLocationStack() - ifs[j].initialStack.sp = 5555 // should be cleared via runtimeLocationStack.Reset(). - ifs[j].initialStack.stack = make([]runtimeValueLocation, 0, capacity) - } - } - c.resetLabels() - for i := range c.labels { - for j := 0; j < len(c.labels[i]); j++ { - l := &c.labels[i][j] - require.False(t, l.stackInitialized) - require.Nil(t, l.initialInstruction) - require.Equal(t, 0, len(l.initialStack.stack)) - if j > frameIDMax { - require.Equal(t, 0, cap(l.initialStack.stack)) - } else { - require.Equal(t, capacity, cap(l.initialStack.stack)) - } - require.Equal(t, uint64(0), l.initialStack.sp) - } - } -} - -func TestAmd64Compiler_getSavedTemporaryLocationStack(t *testing.T) { - t.Run("len(brTableTmp)len(current)", func(t *testing.T) { - const temporarySliceSize = 100 - st := newRuntimeValueLocationStack() - c := &amd64Compiler{locationStack: &st, brTableTmp: make([]runtimeValueLocation, temporarySliceSize)} - - c.locationStack.sp = 3 - c.locationStack.stack = []runtimeValueLocation{ - {stackPointer: 150}, - {stackPointer: 200}, - {stackPointer: 300}, - {}, - {}, - {}, - {}, - {stackPointer: 1231455}, // Entries here shouldn't be copied as they are avobe sp. - } - - actual := c.getSavedTemporaryLocationStack() - require.Equal(t, uint64(3), actual.sp) - require.Equal(t, temporarySliceSize, len(actual.stack)) - require.Equal(t, c.locationStack.stack[:3], actual.stack[:3]) - for i := int(actual.sp); i < len(actual.stack); i++ { - // Above the stack pointer, the values must not be copied. - require.Zero(t, actual.stack[i].stackPointer) - } - }) -} diff --git a/internal/engine/compiler/impl_arm64.go b/internal/engine/compiler/impl_arm64.go deleted file mode 100644 index ef65b5ae36..0000000000 --- a/internal/engine/compiler/impl_arm64.go +++ /dev/null @@ -1,4332 +0,0 @@ -// This file implements the compiler for arm64 target. -// Please refer to https://developer.arm.com/documentation/102374/latest/ -// if unfamiliar with arm64 instructions and semantics. -package compiler - -import ( - "bytes" - "errors" - "fmt" - "math" - - "github.com/tetratelabs/wazero/internal/asm" - "github.com/tetratelabs/wazero/internal/asm/arm64" - "github.com/tetratelabs/wazero/internal/wasm" - "github.com/tetratelabs/wazero/internal/wazeroir" -) - -type arm64Compiler struct { - assembler arm64.Assembler - ir *wazeroir.CompilationResult - // locationStack holds the state of wazeroir virtual stack. - // and each item is either placed in register or the actual memory stack. - locationStack *runtimeValueLocationStack - // labels maps a label (e.g. ".L1_then") to *arm64LabelInfo. - labels [wazeroir.LabelKindNum][]arm64LabelInfo - // stackPointerCeil is the greatest stack pointer value (from runtimeValueLocationStack) seen during compilation. - stackPointerCeil uint64 - // assignStackPointerCeilNeeded holds an asm.Node whose AssignDestinationConstant must be called with the determined stack pointer ceiling. - assignStackPointerCeilNeeded asm.Node - compiledTrapTargets [nativeCallStatusModuleClosed]asm.Node - withListener bool - typ *wasm.FunctionType - br *bytes.Reader - // locationStackForEntrypoint is the initial location stack for all functions. To reuse the allocated stack, - // we cache it here, and reset and set to .locationStack in the Init method. - locationStackForEntrypoint runtimeValueLocationStack - // frameIDMax tracks the maximum value of frame id per function. - frameIDMax int - brTableTmp []runtimeValueLocation -} - -func newArm64Compiler() compiler { - return &arm64Compiler{ - assembler: arm64.NewAssembler(arm64ReservedRegisterForTemporary), - locationStackForEntrypoint: newRuntimeValueLocationStack(), - br: bytes.NewReader(nil), - } -} - -// Init implements compiler.Init. -func (c *arm64Compiler) Init(typ *wasm.FunctionType, ir *wazeroir.CompilationResult, withListener bool) { - c.assembler.Reset() - c.locationStackForEntrypoint.reset() - c.resetLabels() - - *c = arm64Compiler{ - ir: ir, - withListener: withListener, - typ: typ, - assembler: c.assembler, - labels: c.labels, - br: c.br, - brTableTmp: c.brTableTmp, - locationStackForEntrypoint: c.locationStackForEntrypoint, - } - - // Reuses the initial location stack for the compilation of subsequent functions. - c.locationStack = &c.locationStackForEntrypoint -} - -// resetLabels resets the existing content in arm64Compiler.labels so that -// we could reuse the allocated slices and stacks in the subsequent compilations. -func (c *arm64Compiler) resetLabels() { - for i := range c.labels { - for j := range c.labels[i] { - if j > c.frameIDMax { - // Only need to reset until the maximum frame id. This makes the compilation faster for large binary. - break - } - l := &c.labels[i][j] - l.initialInstruction = nil - l.stackInitialized = false - l.initialStack.reset() - } - } -} - -var ( - arm64UnreservedVectorRegisters = []asm.Register{ - arm64.RegV0, arm64.RegV1, arm64.RegV2, arm64.RegV3, - arm64.RegV4, arm64.RegV5, arm64.RegV6, arm64.RegV7, arm64.RegV8, - arm64.RegV9, arm64.RegV10, arm64.RegV11, arm64.RegV12, arm64.RegV13, - arm64.RegV14, arm64.RegV15, arm64.RegV16, arm64.RegV17, arm64.RegV18, - arm64.RegV19, arm64.RegV20, arm64.RegV21, arm64.RegV22, arm64.RegV23, - arm64.RegV24, arm64.RegV25, arm64.RegV26, arm64.RegV27, arm64.RegV28, - arm64.RegV29, arm64.RegV30, arm64.RegV31, - } - - // Note (see arm64 section in https://go.dev/doc/asm): - // * RegR18 is reserved as a platform register, and we don't use it in Compiler. - // * RegR28 is reserved for Goroutine by Go runtime, and we don't use it in Compiler. - arm64UnreservedGeneralPurposeRegisters = []asm.Register{ //nolint - arm64.RegR3, arm64.RegR4, arm64.RegR5, arm64.RegR6, arm64.RegR7, arm64.RegR8, - arm64.RegR9, arm64.RegR10, arm64.RegR11, arm64.RegR12, arm64.RegR13, - arm64.RegR14, arm64.RegR15, arm64.RegR16, arm64.RegR17, arm64.RegR19, - arm64.RegR20, arm64.RegR21, arm64.RegR22, arm64.RegR23, arm64.RegR24, - arm64.RegR25, arm64.RegR26, arm64.RegR29, arm64.RegR30, - } -) - -const ( - // arm64ReservedRegisterForCallEngine holds the pointer to callEngine instance (i.e. *callEngine as uintptr) - arm64ReservedRegisterForCallEngine = arm64.RegR0 - // arm64ReservedRegisterForStackBasePointerAddress holds stack base pointer's address (callEngine.stackBasePointer) in the current function call. - arm64ReservedRegisterForStackBasePointerAddress = arm64.RegR1 - // arm64ReservedRegisterForMemory holds the pointer to the memory slice's data (i.e. &memory.Buffer[0] as uintptr). - arm64ReservedRegisterForMemory = arm64.RegR2 - // arm64ReservedRegisterForTemporary is the temporary register which is available at any point of execution, but its content shouldn't be supposed to live beyond the single operation. - // Note: we choose R27 as that is the temporary register used in Go's assembler. - arm64ReservedRegisterForTemporary = arm64.RegR27 -) - -var arm64CallingConventionModuleInstanceAddressRegister = arm64.RegR29 - -const ( - // arm64CallEngineArchContextCompilerCallReturnAddressOffset is the offset of archContext.nativeCallReturnAddress in callEngine. - arm64CallEngineArchContextCompilerCallReturnAddressOffset = 144 - // arm64CallEngineArchContextMinimum32BitSignedIntOffset is the offset of archContext.minimum32BitSignedIntAddress in callEngine. - arm64CallEngineArchContextMinimum32BitSignedIntOffset = 152 - // arm64CallEngineArchContextMinimum64BitSignedIntOffset is the offset of archContext.minimum64BitSignedIntAddress in callEngine. - arm64CallEngineArchContextMinimum64BitSignedIntOffset = 160 -) - -func isZeroRegister(r asm.Register) bool { - return r == arm64.RegRZR -} - -// compileNOP implements compiler.compileNOP for the arm64 architecture. -func (c *arm64Compiler) compileNOP() asm.Node { - return c.assembler.CompileStandAlone(arm64.NOP) -} - -// compile implements compiler.compile for the arm64 architecture. -func (c *arm64Compiler) compile(buf asm.Buffer) (stackPointerCeil uint64, err error) { - // c.stackPointerCeil tracks the stack pointer ceiling (max seen) value across all runtimeValueLocationStack(s) - // used for all labels (via setLocationStack), excluding the current one. - // Hence, we check here if the final block's max one exceeds the current c.stackPointerCeil. - stackPointerCeil = c.stackPointerCeil - if stackPointerCeil < c.locationStack.stackPointerCeil { - stackPointerCeil = c.locationStack.stackPointerCeil - } - - // Now that the ceil of stack pointer is determined, we are invoking the callback. - // Note: this must be called before Assemble() below. - c.assignStackPointerCeil(stackPointerCeil) - - err = c.assembler.Assemble(buf) - return -} - -// arm64LabelInfo holds a wazeroir label specific information in this function. -type arm64LabelInfo struct { - // initialInstruction is the initial instruction for this label so other block can branch into it. - initialInstruction asm.Node - // initialStack is the initial value location stack from which we start compiling this label. - initialStack runtimeValueLocationStack - stackInitialized bool -} - -// assignStackPointerCeil implements compilerImpl.assignStackPointerCeil for the arm64 architecture. -func (c *arm64Compiler) assignStackPointerCeil(ceil uint64) { - if c.assignStackPointerCeilNeeded != nil { - c.assignStackPointerCeilNeeded.AssignSourceConstant(int64(ceil) << 3) - } -} - -func (c *arm64Compiler) label(label wazeroir.Label) *arm64LabelInfo { - kind := label.Kind() - frames := c.labels[kind] - frameID := label.FrameID() - if c.frameIDMax < frameID { - c.frameIDMax = frameID - } - // If the frameID is not allocated yet, expand the slice by twice of the diff, - // so that we could reduce the allocation in the subsequent compilation. - if diff := frameID - len(frames) + 1; diff > 0 { - for i := 0; i < diff; i++ { - frames = append(frames, arm64LabelInfo{initialStack: newRuntimeValueLocationStack()}) - } - c.labels[kind] = frames - } - return &frames[frameID] -} - -// runtimeValueLocationStack implements compilerImpl.runtimeValueLocationStack for the amd64 architecture. -func (c *arm64Compiler) runtimeValueLocationStack() *runtimeValueLocationStack { - return c.locationStack -} - -// pushRuntimeValueLocationOnRegister implements compiler.pushRuntimeValueLocationOnRegister for arm64. -func (c *arm64Compiler) pushRuntimeValueLocationOnRegister(reg asm.Register, vt runtimeValueType) (ret *runtimeValueLocation) { - ret = c.locationStack.pushRuntimeValueLocationOnRegister(reg, vt) - c.markRegisterUsed(reg) - return -} - -// pushVectorRuntimeValueLocationOnRegister implements compiler.pushVectorRuntimeValueLocationOnRegister for arm64. -func (c *arm64Compiler) pushVectorRuntimeValueLocationOnRegister(reg asm.Register) (lowerBitsLocation *runtimeValueLocation) { - lowerBitsLocation = c.locationStack.pushRuntimeValueLocationOnRegister(reg, runtimeValueTypeV128Lo) - c.locationStack.pushRuntimeValueLocationOnRegister(reg, runtimeValueTypeV128Hi) - c.markRegisterUsed(reg) - return -} - -func (c *arm64Compiler) markRegisterUsed(regs ...asm.Register) { - for _, reg := range regs { - if !isZeroRegister(reg) && reg != asm.NilRegister { - c.locationStack.markRegisterUsed(reg) - } - } -} - -func (c *arm64Compiler) markRegisterUnused(regs ...asm.Register) { - for _, reg := range regs { - if !isZeroRegister(reg) && reg != asm.NilRegister { - c.locationStack.markRegisterUnused(reg) - } - } -} - -func (c *arm64Compiler) String() (ret string) { return c.locationStack.String() } - -// compilePreamble implements compiler.compilePreamble for the arm64 architecture. -func (c *arm64Compiler) compilePreamble() error { - c.markRegisterUsed(arm64CallingConventionModuleInstanceAddressRegister) - defer c.markRegisterUnused(arm64CallingConventionModuleInstanceAddressRegister) - - c.locationStack.init(c.typ) - - // Check if it's necessary to grow the value stack before entering function body. - if err := c.compileMaybeGrowStack(); err != nil { - return err - } - - if err := c.compileModuleContextInitialization(); err != nil { - return err - } - - if c.withListener { - if err := c.compileCallGoFunction(nativeCallStatusCodeCallBuiltInFunction, builtinFunctionIndexFunctionListenerBefore); err != nil { - return err - } - } - - // We must initialize the stack base pointer register so that we can manipulate the stack properly. - c.compileReservedStackBasePointerRegisterInitialization() - - c.compileReservedMemoryRegisterInitialization() - - return nil -} - -// compileMaybeGrowStack adds instructions to check the necessity to grow the value stack, -// and if so, make the builtin function call to do so. These instructions are called in the function's -// preamble. -func (c *arm64Compiler) compileMaybeGrowStack() error { - tmpX, found := c.locationStack.takeFreeRegister(registerTypeGeneralPurpose) - if !found { - panic("BUG: all the registers should be free at this point") - } - c.markRegisterUsed(tmpX) - tmpY, found := c.locationStack.takeFreeRegister(registerTypeGeneralPurpose) - if !found { - panic("BUG: all the registers should be free at this point") - } - c.markRegisterUsed(tmpY) - - // "tmpX = len(ce.stack)" - c.assembler.CompileMemoryToRegister( - arm64.LDRD, - arm64ReservedRegisterForCallEngine, callEngineStackContextStackLenInBytesOffset, - tmpX, - ) - - // "tmpY = ce.stackBasePointer" - c.assembler.CompileMemoryToRegister( - arm64.LDRD, - arm64ReservedRegisterForCallEngine, callEngineStackContextStackBasePointerInBytesOffset, - tmpY, - ) - - // "tmpX = tmpX - tmpY", in other words "tmpX = len(ce.stack) - ce.stackBasePointer" - c.assembler.CompileRegisterToRegister( - arm64.SUB, - tmpY, - tmpX, - ) - - // "tmpY = stackPointerCeil" - loadStackPointerCeil := c.assembler.CompileConstToRegister( - arm64.MOVD, - math.MaxInt32, - tmpY, - ) - // At this point of compilation, we don't know the value of stack point ceil, - // so we lazily resolve the value later. - c.assignStackPointerCeilNeeded = loadStackPointerCeil - - // Compare tmpX (len(ce.stack) - ce.stackBasePointer) and tmpY (ce.stackPointerCeil) - c.assembler.CompileTwoRegistersToNone(arm64.CMP, tmpX, tmpY) - - // If ceil > stackLen - stack base pointer, we need to grow the stack by calling builtin Go function. - brIfStackOK := c.assembler.CompileJump(arm64.BCONDLS) - if err := c.compileCallGoFunction(nativeCallStatusCodeCallBuiltInFunction, builtinFunctionIndexGrowStack); err != nil { - return err - } - - // Otherwise, skip calling it. - c.assembler.SetJumpTargetOnNext(brIfStackOK) - - c.markRegisterUnused(tmpX, tmpY) - return nil -} - -// returnFunction emits instructions to return from the current function frame. -// If the current frame is the bottom, the code goes back to the Go code with nativeCallStatusCodeReturned status. -// Otherwise, we branch into the caller's return address. -func (c *arm64Compiler) compileReturnFunction() error { - // Release all the registers as our calling convention requires the caller-save. - if err := c.compileReleaseAllRegistersToStack(); err != nil { - return err - } - - if c.withListener { - if err := c.compileCallGoFunction(nativeCallStatusCodeCallBuiltInFunction, builtinFunctionIndexFunctionListenerAfter); err != nil { - return err - } - // After return, we re-initialize the stack base pointer as that is used to return to the caller below. - c.compileReservedStackBasePointerRegisterInitialization() - } - - // arm64CallingConventionModuleInstanceAddressRegister holds the module intstance's address - // so mark it used so that it won't be used as a free register. - c.locationStack.markRegisterUsed(arm64CallingConventionModuleInstanceAddressRegister) - defer c.locationStack.markRegisterUnused(arm64CallingConventionModuleInstanceAddressRegister) - - returnAddress, callerStackBasePointerInBytes, callerFunction := c.locationStack.getCallFrameLocations(c.typ) - - // If the return address is zero, meaning that we return from the execution. - returnAddress.setRegister(arm64ReservedRegisterForTemporary) - c.compileLoadValueOnStackToRegister(returnAddress) - c.assembler.CompileTwoRegistersToNone(arm64.CMP, arm64ReservedRegisterForTemporary, arm64.RegRZR) - - // Br if the address does not equal zero, otherwise, exit. - // If the address doesn't equal zero, return br into returnAddressRegister (caller's return address). - c.compileMaybeExitFromNativeCode(arm64.BCONDNE, nativeCallStatusCodeReturned) - - // Alias for readability. - tmp := arm64CallingConventionModuleInstanceAddressRegister - - // First, restore the stackContext.stackBasePointerInBytesOffset from callerStackBasePointerInBytes. - callerStackBasePointerInBytes.setRegister(tmp) - c.compileLoadValueOnStackToRegister(callerStackBasePointerInBytes) - c.assembler.CompileRegisterToMemory(arm64.STRD, tmp, - arm64ReservedRegisterForCallEngine, callEngineStackContextStackBasePointerInBytesOffset) - - // Next, restore moduleContext.fn from callerFunction. - callerFunction.setRegister(tmp) - c.compileLoadValueOnStackToRegister(callerFunction) - c.assembler.CompileRegisterToMemory(arm64.STRD, tmp, - arm64ReservedRegisterForCallEngine, callEngineModuleContextFnOffset) - - // Also, we have to put the target function's *wasm.ModuleInstance into arm64CallingConventionModuleInstanceAddressRegister. - c.assembler.CompileMemoryToRegister(arm64.LDRD, - tmp, functionModuleInstanceOffset, - arm64CallingConventionModuleInstanceAddressRegister) - - c.assembler.CompileJumpToRegister(arm64.B, returnAddress.register) - return nil -} - -func (c *arm64Compiler) compileMaybeExitFromNativeCode(skipCondition asm.Instruction, status nativeCallStatusCode) { - skip := c.assembler.CompileJump(skipCondition) - c.compileExitFromNativeCode(status) - c.assembler.SetJumpTargetOnNext(skip) -} - -// compileExitFromNativeCode adds instructions to give the control back to ce.exec with the given status code. -func (c *arm64Compiler) compileExitFromNativeCode(status nativeCallStatusCode) { - if target := c.compiledTrapTargets[status]; target != nil { - c.assembler.CompileJump(arm64.B).AssignJumpTarget(target) - return - } - - switch status { - case nativeCallStatusCodeReturned: - // Save the target for reuse. - c.compiledTrapTargets[status] = c.compileNOP() - case nativeCallStatusCodeCallGoHostFunction, nativeCallStatusCodeCallBuiltInFunction: - // Read the return address, and write it to callEngine.exitContext.returnAddress. - c.assembler.CompileReadInstructionAddress(arm64ReservedRegisterForTemporary, arm64.RET) - c.assembler.CompileRegisterToMemory( - arm64.STRD, arm64ReservedRegisterForTemporary, - arm64ReservedRegisterForCallEngine, callEngineExitContextReturnAddressOffset, - ) - default: - if c.ir.IROperationSourceOffsetsInWasmBinary != nil { - // This case, the execution traps, and we want the top frame's source position in the stack trace. - // We store the instruction address onto callEngine.returnAddress. - c.assembler.CompileReadInstructionAddress(arm64ReservedRegisterForTemporary, arm64.STRD) - c.assembler.CompileRegisterToMemory( - arm64.STRD, arm64ReservedRegisterForTemporary, - arm64ReservedRegisterForCallEngine, callEngineExitContextReturnAddressOffset, - ) - } else { - // We won't use the source position, so just save the target for reuse. - c.compiledTrapTargets[status] = c.compileNOP() - } - } - - // Write the current stack pointer to the ce.stackPointer. - c.assembler.CompileConstToRegister(arm64.MOVD, int64(c.locationStack.sp), arm64ReservedRegisterForTemporary) - c.assembler.CompileRegisterToMemory(arm64.STRD, arm64ReservedRegisterForTemporary, arm64ReservedRegisterForCallEngine, - callEngineStackContextStackPointerOffset) - - // Write the status to callEngine.exitContext.statusCode. - if status != 0 { - c.assembler.CompileConstToRegister(arm64.MOVW, int64(status), arm64ReservedRegisterForTemporary) - c.assembler.CompileRegisterToMemory(arm64.STRW, arm64ReservedRegisterForTemporary, - arm64ReservedRegisterForCallEngine, callEngineExitContextNativeCallStatusCodeOffset) - } else { - // If the status == 0, we use zero register to store zero. - c.assembler.CompileRegisterToMemory(arm64.STRW, arm64.RegRZR, - arm64ReservedRegisterForCallEngine, callEngineExitContextNativeCallStatusCodeOffset) - } - - // The return address to the Go code is stored in archContext.compilerReturnAddress which - // is embedded in ce. We load the value to the tmpRegister, and then - // invoke RET with that register. - c.assembler.CompileMemoryToRegister(arm64.LDRD, - arm64ReservedRegisterForCallEngine, arm64CallEngineArchContextCompilerCallReturnAddressOffset, - arm64ReservedRegisterForTemporary) - - c.assembler.CompileJumpToRegister(arm64.RET, arm64ReservedRegisterForTemporary) -} - -// compileGoHostFunction implements compiler.compileHostFunction for the arm64 architecture. -func (c *arm64Compiler) compileGoDefinedHostFunction() error { - // First we must update the location stack to reflect the number of host function inputs. - c.locationStack.init(c.typ) - - if c.withListener { - if err := c.compileCallGoFunction(nativeCallStatusCodeCallBuiltInFunction, - builtinFunctionIndexFunctionListenerBefore); err != nil { - return err - } - } - - // Host function needs access to the caller's Function Instance, and the caller's information is stored in the stack - // (as described in the doc of callEngine.stack). Here, we get the caller's *wasm.FunctionInstance from the stack, - // and save it in callEngine.exitContext.callerFunctionInstance so we can pass it to the host function - // without sacrificing the performance. - c.compileReservedStackBasePointerRegisterInitialization() - // Alias for readability. - tmp := arm64CallingConventionModuleInstanceAddressRegister - // Get the location of the callerFunction (*function) in the stack, which depends on the signature. - _, _, callerFunction := c.locationStack.getCallFrameLocations(c.typ) - // Load the value into the tmp register: tmp = &function{..} - callerFunction.setRegister(tmp) - c.compileLoadValueOnStackToRegister(callerFunction) - // tmp = *(tmp+functionModuleInstanceOffset) = &wasm.ModuleInstance{...} - c.assembler.CompileMemoryToRegister(arm64.LDRD, tmp, functionModuleInstanceOffset, tmp) - // Load it onto callEngine.exitContext.callerModuleInstance. - c.assembler.CompileRegisterToMemory(arm64.STRD, - tmp, - arm64ReservedRegisterForCallEngine, callEngineExitContextCallerModuleInstanceOffset) - // Reset the state of callerFunction value location so that we won't mess up subsequent code generation below. - c.locationStack.releaseRegister(callerFunction) - - if err := c.compileCallGoFunction(nativeCallStatusCodeCallGoHostFunction, 0); err != nil { - return err - } - - // Initializes the reserved stack base pointer which is used to retrieve the call frame stack. - c.compileReservedStackBasePointerRegisterInitialization() - - // Go function can change the module state in arbitrary way, so we have to force - // the callEngine.moduleContext initialization on the function return. To do so, - // we zero-out callEngine.moduleInstance. - c.assembler.CompileRegisterToMemory(arm64.STRD, - arm64.RegRZR, - arm64ReservedRegisterForCallEngine, callEngineModuleContextModuleInstanceOffset) - - return c.compileReturnFunction() -} - -// setLocationStack sets the given runtimeValueLocationStack to .locationStack field, -// while allowing us to track runtimeValueLocationStack.stackPointerCeil across multiple stacks. -// This is called when we branch into different block. -func (c *arm64Compiler) setLocationStack(newStack *runtimeValueLocationStack) { - if c.stackPointerCeil < c.locationStack.stackPointerCeil { - c.stackPointerCeil = c.locationStack.stackPointerCeil - } - c.locationStack = newStack -} - -// compileBuiltinFunctionCheckExitCode implements compiler.compileBuiltinFunctionCheckExitCode for the arm64 architecture. -func (c *arm64Compiler) compileBuiltinFunctionCheckExitCode() error { - if err := c.compileCallGoFunction(nativeCallStatusCodeCallBuiltInFunction, builtinFunctionIndexCheckExitCode); err != nil { - return err - } - - // After return, we re-initialize reserved registers just like preamble of functions. - c.compileReservedStackBasePointerRegisterInitialization() - c.compileReservedMemoryRegisterInitialization() - return nil -} - -// compileLabel implements compiler.compileLabel for the arm64 architecture. -func (c *arm64Compiler) compileLabel(o *wazeroir.UnionOperation) (skipThisLabel bool) { - labelKey := wazeroir.Label(o.U1) - labelInfo := c.label(labelKey) - - // If initialStack is not set, that means this label has never been reached. - if !labelInfo.stackInitialized { - skipThisLabel = true - return - } - - if labelBegin := labelInfo.initialInstruction; labelBegin == nil { - // We use NOP as a beginning of instructions in a label. - // This should be eventually optimized out by assembler. - labelInfo.initialInstruction = c.assembler.CompileStandAlone(arm64.NOP) - } else { - c.assembler.Add(labelBegin) - } - - // Set the initial stack. - c.setLocationStack(&labelInfo.initialStack) - return false -} - -// compileUnreachable implements compiler.compileUnreachable for the arm64 architecture. -func (c *arm64Compiler) compileUnreachable() error { - c.compileExitFromNativeCode(nativeCallStatusCodeUnreachable) - return nil -} - -// compileSet implements compiler.compileSet for the arm64 architecture. -func (c *arm64Compiler) compileSet(o *wazeroir.UnionOperation) error { - depth := int(o.U1) - isTargetVector := o.B3 - - setTargetIndex := int(c.locationStack.sp) - 1 - depth - - if isTargetVector { - _ = c.locationStack.pop() - } - v := c.locationStack.pop() - if err := c.compileEnsureOnRegister(v); err != nil { - return err - } - - targetLocation := &c.locationStack.stack[setTargetIndex] - if targetLocation.onRegister() { - // We no longer need the register previously used by the target location. - c.markRegisterUnused(targetLocation.register) - } - - reg := v.register - targetLocation.setRegister(reg) - targetLocation.valueType = v.valueType - if isTargetVector { - hi := &c.locationStack.stack[setTargetIndex+1] - hi.setRegister(reg) - } - return nil -} - -// compileGlobalGet implements compiler.compileGlobalGet for the arm64 architecture. -func (c *arm64Compiler) compileGlobalGet(o *wazeroir.UnionOperation) error { - if err := c.maybeCompileMoveTopConditionalToGeneralPurposeRegister(); err != nil { - return err - } - - index := uint32(o.U1) - - wasmValueType := c.ir.Globals[index].ValType - isV128 := wasmValueType == wasm.ValueTypeV128 - // Get the address of globals[index] into globalAddressReg. - globalAddressReg, err := c.compileReadGlobalAddress(index) - if err != nil { - return err - } - - if isV128 { - resultReg, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - c.assembler.CompileConstToRegister(arm64.ADD, globalInstanceValueOffset, globalAddressReg) - c.assembler.CompileMemoryToVectorRegister(arm64.VMOV, globalAddressReg, 0, - resultReg, arm64.VectorArrangementQ) - - c.pushVectorRuntimeValueLocationOnRegister(resultReg) - } else { - ldr := arm64.NOP - var result asm.Register - var vt runtimeValueType - switch wasmValueType { - case wasm.ValueTypeI32: - ldr = arm64.LDRW - vt = runtimeValueTypeI32 - result = globalAddressReg - case wasm.ValueTypeI64, wasm.ValueTypeExternref, wasm.ValueTypeFuncref: - ldr = arm64.LDRD - vt = runtimeValueTypeI64 - result = globalAddressReg - case wasm.ValueTypeF32: - result, err = c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - ldr = arm64.FLDRS - vt = runtimeValueTypeF32 - case wasm.ValueTypeF64: - result, err = c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - ldr = arm64.FLDRD - vt = runtimeValueTypeF64 - } - - // "result = [globalAddressReg + globalInstanceValueOffset] (== globals[index].Val)" - c.assembler.CompileMemoryToRegister( - ldr, - globalAddressReg, globalInstanceValueOffset, - result, - ) - - c.pushRuntimeValueLocationOnRegister(result, vt) - } - return nil -} - -// compileGlobalSet implements compiler.compileGlobalSet for the arm64 architecture. -func (c *arm64Compiler) compileGlobalSet(o *wazeroir.UnionOperation) error { - index := uint32(o.U1) - - wasmValueType := c.ir.Globals[index].ValType - isV128 := wasmValueType == wasm.ValueTypeV128 - - var val *runtimeValueLocation - if isV128 { - val = c.locationStack.popV128() - } else { - val = c.locationStack.pop() - } - if err := c.compileEnsureOnRegister(val); err != nil { - return err - } - - globalInstanceAddressRegister, err := c.compileReadGlobalAddress(index) - if err != nil { - return err - } - - if isV128 { - c.assembler.CompileVectorRegisterToMemory(arm64.VMOV, - val.register, globalInstanceAddressRegister, globalInstanceValueOffset, - arm64.VectorArrangementQ) - } else { - var str asm.Instruction - switch c.ir.Globals[index].ValType { - case wasm.ValueTypeI32: - str = arm64.STRW - case wasm.ValueTypeI64, wasm.ValueTypeExternref, wasm.ValueTypeFuncref: - str = arm64.STRD - case wasm.ValueTypeF32: - str = arm64.FSTRS - case wasm.ValueTypeF64: - str = arm64.FSTRD - } - - // At this point "globalInstanceAddressRegister = globals[index]". - // Therefore, this means "globals[index].Val = val.register" - c.assembler.CompileRegisterToMemory( - str, - val.register, - globalInstanceAddressRegister, globalInstanceValueOffset, - ) - } - - c.markRegisterUnused(val.register) - return nil -} - -// compileReadGlobalAddress adds instructions to store the absolute address of the global instance at globalIndex into a register -func (c *arm64Compiler) compileReadGlobalAddress(globalIndex uint32) (destinationRegister asm.Register, err error) { - // TODO: rethink about the type used in store `globals []*GlobalInstance`. - // If we use `[]GlobalInstance` instead, we could reduce one MOV instruction here. - - destinationRegister, err = c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return - } - - // "destinationRegister = globalIndex * 8" - c.assembler.CompileConstToRegister( - // globalIndex is an index to []*GlobalInstance, therefore - // we have to multiply it by the size of *GlobalInstance == the pointer size == 8. - arm64.MOVD, int64(globalIndex)*8, destinationRegister, - ) - - // "arm64ReservedRegisterForTemporary = &globals[0]" - c.assembler.CompileMemoryToRegister( - arm64.LDRD, - arm64ReservedRegisterForCallEngine, callEngineModuleContextGlobalElement0AddressOffset, - arm64ReservedRegisterForTemporary, - ) - - // "destinationRegister = [arm64ReservedRegisterForTemporary + destinationRegister] (== globals[globalIndex])". - c.assembler.CompileMemoryWithRegisterOffsetToRegister( - arm64.LDRD, - arm64ReservedRegisterForTemporary, destinationRegister, - destinationRegister, - ) - return -} - -// compileBr implements compiler.compileBr for the arm64 architecture. -func (c *arm64Compiler) compileBr(o *wazeroir.UnionOperation) error { - if err := c.maybeCompileMoveTopConditionalToGeneralPurposeRegister(); err != nil { - return err - } - return c.compileBranchInto(wazeroir.Label(o.U1)) -} - -// compileBrIf implements compiler.compileBrIf for the arm64 architecture. -func (c *arm64Compiler) compileBrIf(o *wazeroir.UnionOperation) error { - cond := c.locationStack.pop() - - var conditionalBR asm.Node - if cond.onConditionalRegister() { - // If the cond is on a conditional register, it corresponds to one of "conditional codes" - // https://developer.arm.com/documentation/dui0801/a/Condition-Codes/Condition-code-suffixes - // Here we represent the conditional codes by using arm64.COND_** registers, and that means the - // conditional jump can be performed if we use arm64.B**. - // For example, if we have arm64.CondEQ on cond, that means we performed compileEq right before - // this compileBrIf and BrIf can be achieved by arm64.BCONDEQ. - var brInst asm.Instruction - switch cond.conditionalRegister { - case arm64.CondEQ: - brInst = arm64.BCONDEQ - case arm64.CondNE: - brInst = arm64.BCONDNE - case arm64.CondHS: - brInst = arm64.BCONDHS - case arm64.CondLO: - brInst = arm64.BCONDLO - case arm64.CondMI: - brInst = arm64.BCONDMI - case arm64.CondHI: - brInst = arm64.BCONDHI - case arm64.CondLS: - brInst = arm64.BCONDLS - case arm64.CondGE: - brInst = arm64.BCONDGE - case arm64.CondLT: - brInst = arm64.BCONDLT - case arm64.CondGT: - brInst = arm64.BCONDGT - case arm64.CondLE: - brInst = arm64.BCONDLE - default: - // BUG: This means that we use the cond.conditionalRegister somewhere in this file, - // but not covered in switch ^. That shouldn't happen. - return fmt.Errorf("unsupported condition for br_if: %v", cond.conditionalRegister) - } - conditionalBR = c.assembler.CompileJump(brInst) - } else { - // If the value is not on the conditional register, we compare the value with the zero register, - // and then do the conditional BR if the value doesn't equal zero. - if err := c.compileEnsureOnRegister(cond); err != nil { - return err - } - // Compare the value with zero register. Note that the value is ensured to be i32 by function validation phase, - // so we use CMPW (32-bit compare) here. - c.assembler.CompileTwoRegistersToNone(arm64.CMPW, cond.register, arm64.RegRZR) - - conditionalBR = c.assembler.CompileJump(arm64.BCONDNE) - - c.markRegisterUnused(cond.register) - } - - // Emit the code for branching into else branch. - elseTarget := wazeroir.Label(o.U2) - if err := c.compileBranchInto(elseTarget); err != nil { - return err - } - // We branch into here from the original conditional BR (conditionalBR). - c.assembler.SetJumpTargetOnNext(conditionalBR) - thenTarget := wazeroir.Label(o.U1) - if err := compileDropRange(c, o.U3); err != nil { - return err - } - return c.compileBranchInto(thenTarget) -} - -func (c *arm64Compiler) compileBranchInto(target wazeroir.Label) error { - if target.IsReturnTarget() { - return c.compileReturnFunction() - } else { - if c.ir.LabelCallers[target] > 1 { - // We can only re-use register state if when there's a single call-site. - // Release existing values on registers to the stack if there's multiple ones to have - // the consistent value location state at the beginning of label. - if err := c.compileReleaseAllRegistersToStack(); err != nil { - return err - } - } - // Set the initial stack of the target label, so we can start compiling the label - // with the appropriate value locations. Note we clone the stack here as we maybe - // manipulate the stack before compiler reaches the label. - targetLabel := c.label(target) - if !targetLabel.stackInitialized { - targetLabel.initialStack.cloneFrom(*c.locationStack) - targetLabel.stackInitialized = true - } - - br := c.assembler.CompileJump(arm64.B) - c.assignBranchTarget(target, br) - return nil - } -} - -// assignBranchTarget assigns the given label's initial instruction to the destination of br. -func (c *arm64Compiler) assignBranchTarget(label wazeroir.Label, br asm.Node) { - target := c.label(label) - - targetInst := target.initialInstruction - if targetInst == nil { - // If the label isn't compiled yet, allocate the NOP node, and set as the initial instruction. - targetInst = c.assembler.AllocateNOP() - target.initialInstruction = targetInst - } - - br.AssignJumpTarget(targetInst) -} - -// compileBrTable implements compiler.compileBrTable for the arm64 architecture. -func (c *arm64Compiler) compileBrTable(o *wazeroir.UnionOperation) error { - // If the operation only consists of the default target, we branch into it and return early. - if len(o.Us) == 2 { - loc := c.locationStack.pop() - if loc.onRegister() { - c.markRegisterUnused(loc.register) - } - if err := compileDropRange(c, o.Us[1]); err != nil { - return err - } - return c.compileBranchInto(wazeroir.Label(o.Us[0])) - } - - index := c.locationStack.pop() - if err := c.compileEnsureOnRegister(index); err != nil { - return err - } - - if isZeroRegister(index.register) { - reg, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - index.setRegister(reg) - c.markRegisterUsed(reg) - - // Zero the value on a picked register. - c.assembler.CompileRegisterToRegister(arm64.MOVD, arm64.RegRZR, reg) - } - - tmpReg, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - - // Load the branch table's length. - // "tmpReg = len(o.Targets)" - c.assembler.CompileConstToRegister(arm64.MOVW, int64(len(o.Us)/2-1), tmpReg) - // Compare the length with offset. - c.assembler.CompileTwoRegistersToNone(arm64.CMPW, tmpReg, index.register) - // If the value exceeds the length, we will branch into the default target (corresponding to len(o.Targets) index). - brDefaultIndex := c.assembler.CompileJump(arm64.BCONDLO) - c.assembler.CompileRegisterToRegister(arm64.MOVW, tmpReg, index.register) - c.assembler.SetJumpTargetOnNext(brDefaultIndex) - - // We prepare the asm.StaticConst which holds the offset of - // each target's first instruction (incl. default) - // relative to the beginning of label tables. - // - // For example, if we have targets=[L0, L1] and default=L_DEFAULT, - // we emit the code like this at [Emit the code for each target and default branch] below. - // - // L0: - // 0x123001: XXXX, ... - // ..... - // L1: - // 0x123005: YYY, ... - // ..... - // L_DEFAULT: - // 0x123009: ZZZ, ... - // - // then offsetData becomes like [0x0, 0x5, 0x8]. - // By using this offset list, we could jump into the label for the index by - // "jmp offsetData[index]+0x123001" and "0x123001" can be acquired by ADR instruction. - // - // Note: We store each offset of 32-bit unsigned integer as 4 consecutive bytes. So more precisely, - // the above example's offsetData would be [0x0, 0x0, 0x0, 0x0, 0x5, 0x0, 0x0, 0x0, 0x8, 0x0, 0x0, 0x0]. - // - // Note: this is similar to how GCC implements Switch statements in C. - offsetData := asm.NewStaticConst(make([]byte, 4*(len(o.Us)/2))) - - // "tmpReg = &offsetData[0]" - c.assembler.CompileStaticConstToRegister(arm64.ADR, offsetData, tmpReg) - - // "index.register = tmpReg + (index.register << 2) (== &offsetData[offset])" - c.assembler.CompileLeftShiftedRegisterToRegister(arm64.ADD, index.register, 2, tmpReg, index.register) - - // "index.register = *index.register (== offsetData[offset])" - c.assembler.CompileMemoryToRegister(arm64.LDRW, index.register, 0, index.register) - - // Now we read the address of the beginning of the jump table. - // In the above example, this corresponds to reading the address of 0x123001. - c.assembler.CompileReadInstructionAddress(tmpReg, arm64.B) - - // Now we have the address of L0 in tmp register, and the offset to the target label in the index.register. - // So we could achieve the br_table jump by adding them and jump into the resulting address. - c.assembler.CompileRegisterToRegister(arm64.ADD, tmpReg, index.register) - - c.assembler.CompileJumpToRegister(arm64.B, index.register) - - // We no longer need the index's register, so mark it unused. - c.markRegisterUnused(index.register) - - // [Emit the code for each targets and default branch] - labelInitialInstructions := make([]asm.Node, len(o.Us)/2) - - // Since we might end up having the different stack state in each branch, - // we need to save the initial stack state here, and use the same initial state - // for each iteration. - initialLocationStack := c.getSavedTemporaryLocationStack() - - for i := range labelInitialInstructions { - // Emit the initial instruction of each target where - // we use NOP as we don't yet know the next instruction in each label. - init := c.assembler.CompileStandAlone(arm64.NOP) - labelInitialInstructions[i] = init - - targetLabel := wazeroir.Label(o.Us[i*2]) - targetToDrop := o.Us[i*2+1] - if err = compileDropRange(c, targetToDrop); err != nil { - return err - } - if err = c.compileBranchInto(targetLabel); err != nil { - return err - } - // After the iteration, reset the stack's state with initialLocationStack. - c.locationStack.cloneFrom(initialLocationStack) - } - - c.assembler.BuildJumpTable(offsetData, labelInitialInstructions) - return nil -} - -func (c *arm64Compiler) getSavedTemporaryLocationStack() runtimeValueLocationStack { - initialLocationStack := *c.locationStack // Take copy! - // Use c.brTableTmp for the underlying stack so that we could reduce the allocations. - if diff := int(initialLocationStack.sp) - len(c.brTableTmp); diff > 0 { - c.brTableTmp = append(c.brTableTmp, make([]runtimeValueLocation, diff)...) - } - copy(c.brTableTmp, initialLocationStack.stack[:initialLocationStack.sp]) - initialLocationStack.stack = c.brTableTmp - return initialLocationStack -} - -// compileCall implements compiler.compileCall for the arm64 architecture. -func (c *arm64Compiler) compileCall(o *wazeroir.UnionOperation) error { - if err := c.maybeCompileMoveTopConditionalToGeneralPurposeRegister(); err != nil { - return err - } - - functionIndex := o.U1 - - tp := &c.ir.Types[c.ir.Functions[functionIndex]] - - targetFunctionAddressReg, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - c.markRegisterUsed(targetFunctionAddressReg) - defer c.markRegisterUnused(targetFunctionAddressReg) - - // 3) Set rc.next to specify which function is executed on the current call frame. - // - // First, we read the address of the first item of ce.functions slice (= &ce.functions[0]) - // into tmp. - c.assembler.CompileMemoryToRegister(arm64.LDRD, - arm64ReservedRegisterForCallEngine, callEngineModuleContextFunctionsElement0AddressOffset, - targetFunctionAddressReg) - - c.assembler.CompileConstToRegister( - arm64.ADD, - int64(functionIndex)*functionSize, // * 8 because the size of *function equals 8 bytes. - targetFunctionAddressReg) - - return c.compileCallImpl(targetFunctionAddressReg, tp) -} - -// compileCallImpl implements compiler.compileCall and compiler.compileCallIndirect for the arm64 architecture. -func (c *arm64Compiler) compileCallImpl(targetFunctionAddressRegister asm.Register, functype *wasm.FunctionType) error { - // Release all the registers as our calling convention requires the caller-save. - if err := c.compileReleaseAllRegistersToStack(); err != nil { - return err - } - - tmp, ok := c.locationStack.takeFreeRegister(registerTypeGeneralPurpose) - if !ok { - panic("BUG: cannot take a free register") - } - - // The stack should look like: - // - // reserved slots for results (if len(results) > len(args)) - // | | - // ,arg0, ..., argN, ..., _, .returnAddress, .returnStackBasePointerInBytes, .function, .... - // | | | - // | callFrame{^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^} - // | - // nextStackBasePointerOffset - // - // where callFrame is used to return to this currently executed function. - - nextStackBasePointerOffset := int64(c.locationStack.sp) - int64(functype.ParamNumInUint64) - - callFrameReturnAddressLoc, callFrameStackBasePointerInBytesLoc, callFrameFunctionLoc := c.locationStack.pushCallFrame(functype) - - // Save the current stack base pointer at callFrameStackBasePointerInBytesLoc. - c.assembler.CompileMemoryToRegister(arm64.LDRD, - arm64ReservedRegisterForCallEngine, callEngineStackContextStackBasePointerInBytesOffset, - tmp) - callFrameStackBasePointerInBytesLoc.setRegister(tmp) - c.compileReleaseRegisterToStack(callFrameStackBasePointerInBytesLoc) - - // Set callEngine.stackContext.stackBasePointer for the next function. - c.assembler.CompileConstToRegister(arm64.ADD, nextStackBasePointerOffset<<3, tmp) - c.assembler.CompileRegisterToMemory(arm64.STRD, - tmp, - arm64ReservedRegisterForCallEngine, callEngineStackContextStackBasePointerInBytesOffset) - - // Save the currently executed *function (placed at callEngine.moduleContext.fn) into callFrameFunctionLoc. - c.assembler.CompileMemoryToRegister(arm64.LDRD, - arm64ReservedRegisterForCallEngine, callEngineModuleContextFnOffset, - tmp) - callFrameFunctionLoc.setRegister(tmp) - c.compileReleaseRegisterToStack(callFrameFunctionLoc) - - // Set callEngine.moduleContext.fn to the next *function. - c.assembler.CompileRegisterToMemory(arm64.STRD, - targetFunctionAddressRegister, - arm64ReservedRegisterForCallEngine, callEngineModuleContextFnOffset) - - // Write the return address into callFrameReturnAddressLoc. - c.assembler.CompileReadInstructionAddress(tmp, arm64.B) - callFrameReturnAddressLoc.setRegister(tmp) - c.compileReleaseRegisterToStack(callFrameReturnAddressLoc) - - if targetFunctionAddressRegister == arm64CallingConventionModuleInstanceAddressRegister { - // This case we must move the value on targetFunctionAddressRegister to another register, otherwise - // the address (jump target below) will be modified and result in segfault. - // See #526. - c.assembler.CompileRegisterToRegister(arm64.MOVD, targetFunctionAddressRegister, tmp) - targetFunctionAddressRegister = tmp - } - - // Also, we have to put the code's moduleInstance address into arm64CallingConventionModuleInstanceAddressRegister. - c.assembler.CompileMemoryToRegister(arm64.LDRD, - targetFunctionAddressRegister, functionModuleInstanceOffset, - arm64CallingConventionModuleInstanceAddressRegister, - ) - - // Then, br into the target function's initial address. - c.assembler.CompileMemoryToRegister(arm64.LDRD, - targetFunctionAddressRegister, functionCodeInitialAddressOffset, - targetFunctionAddressRegister) - - c.assembler.CompileJumpToRegister(arm64.B, targetFunctionAddressRegister) - - // We consumed the function parameters, the call frame stack and reserved slots during the call. - c.locationStack.sp = uint64(nextStackBasePointerOffset) - - // Also, the function results were pushed by the call. - for _, t := range functype.Results { - loc := c.locationStack.pushRuntimeValueLocationOnStack() - switch t { - case wasm.ValueTypeI32: - loc.valueType = runtimeValueTypeI32 - case wasm.ValueTypeI64, wasm.ValueTypeFuncref, wasm.ValueTypeExternref: - loc.valueType = runtimeValueTypeI64 - case wasm.ValueTypeF32: - loc.valueType = runtimeValueTypeF32 - case wasm.ValueTypeF64: - loc.valueType = runtimeValueTypeF64 - case wasm.ValueTypeV128: - loc.valueType = runtimeValueTypeV128Lo - hi := c.locationStack.pushRuntimeValueLocationOnStack() - hi.valueType = runtimeValueTypeV128Hi - } - } - - if err := c.compileModuleContextInitialization(); err != nil { - return err - } - - // On the function return, we initialize the state for this function. - c.compileReservedStackBasePointerRegisterInitialization() - - c.compileReservedMemoryRegisterInitialization() - return nil -} - -// compileCallIndirect implements compiler.compileCallIndirect for the arm64 architecture. -func (c *arm64Compiler) compileCallIndirect(o *wazeroir.UnionOperation) (err error) { - offset := c.locationStack.pop() - if err = c.compileEnsureOnRegister(offset); err != nil { - return err - } - typeIndex := o.U1 - tableIndex := o.U2 - - offsetReg := offset.register - if isZeroRegister(offsetReg) { - offsetReg, err = c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - c.markRegisterUsed(offsetReg) - - // Zero the value on a picked register. - c.assembler.CompileRegisterToRegister(arm64.MOVD, arm64.RegRZR, offsetReg) - } - - tmp, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - c.markRegisterUsed(tmp) - - tmp2, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - c.markRegisterUsed(tmp2) - - // First, we need to check if the offset doesn't exceed the length of table. - // "tmp = &Tables[0]" - c.assembler.CompileMemoryToRegister(arm64.LDRD, - arm64ReservedRegisterForCallEngine, callEngineModuleContextTablesElement0AddressOffset, - tmp, - ) - // tmp = [tmp + TableIndex*8] = [&Tables[0] + TableIndex*sizeOf(*tableInstance)] = Tables[tableIndex] - c.assembler.CompileMemoryToRegister(arm64.LDRD, - tmp, int64(tableIndex)*8, - tmp, - ) - // tmp2 = [tmp + tableInstanceTableLenOffset] = len(Tables[tableIndex]) - c.assembler.CompileMemoryToRegister(arm64.LDRD, tmp, tableInstanceTableLenOffset, tmp2) - - // "cmp tmp2, offset" - c.assembler.CompileTwoRegistersToNone(arm64.CMP, tmp2, offsetReg) - - // If it exceeds len(table), we trap. - c.compileMaybeExitFromNativeCode(arm64.BCONDLO, nativeCallStatusCodeInvalidTableAccess) - // Otherwise, we proceed to do function type check. - - // We need to obtain the absolute address of table element. - // "tmp = &Tables[tableIndex].table[0]" - c.assembler.CompileMemoryToRegister( - arm64.LDRD, - tmp, tableInstanceTableOffset, - tmp, - ) - // "offset = tmp + (offset << pointerSizeLog2) (== &table[offset])" - // Here we left shifting by 3 in order to get the offset in bytes, - // and the table element type is uintptr which is 8 bytes. - c.assembler.CompileLeftShiftedRegisterToRegister( - arm64.ADD, - offsetReg, pointerSizeLog2, - tmp, - offsetReg, - ) - - // "offset = (*offset) (== table[offset])" - c.assembler.CompileMemoryToRegister(arm64.LDRD, offsetReg, 0, offsetReg) - - // Check if the value of table[offset] equals zero, meaning that the target element is uninitialized. - c.assembler.CompileTwoRegistersToNone(arm64.CMP, arm64.RegRZR, offsetReg) - - // Skipped if the target is initialized. - c.compileMaybeExitFromNativeCode(arm64.BCONDNE, nativeCallStatusCodeInvalidTableAccess) - - // next we check the type matches, i.e. table[offset].source.TypeID == targetFunctionType. - // "tmp = table[offset].typeID" - c.assembler.CompileMemoryToRegister( - arm64.LDRD, - offsetReg, functionTypeIDOffset, - tmp, - ) - // "tmp2 = ModuleInstance.TypeIDs[index]" - c.assembler.CompileMemoryToRegister(arm64.LDRD, - arm64ReservedRegisterForCallEngine, callEngineModuleContextTypeIDsElement0AddressOffset, - tmp2) - c.assembler.CompileMemoryToRegister(arm64.LDRW, tmp2, int64(typeIndex)*4, tmp2) - - // Compare these two values, and if they equal, we are ready to make function call. - c.assembler.CompileTwoRegistersToNone(arm64.CMPW, tmp, tmp2) - // Skipped if the type matches. - c.compileMaybeExitFromNativeCode(arm64.BCONDEQ, nativeCallStatusCodeTypeMismatchOnIndirectCall) - - targetFunctionType := &c.ir.Types[typeIndex] - if err := c.compileCallImpl(offsetReg, targetFunctionType); err != nil { - return err - } - - // The offset register should be marked as un-used as we consumed in the function call. - c.markRegisterUnused(offsetReg, tmp, tmp2) - return nil -} - -// compileDrop implements compiler.compileDrop for the arm64 architecture. -func (c *arm64Compiler) compileDrop(o *wazeroir.UnionOperation) error { - return compileDropRange(c, o.U1) -} - -func (c *arm64Compiler) compileSelectV128Impl(selectorRegister asm.Register) error { - x2 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x2); err != nil { - return err - } - - x1 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x1); err != nil { - return err - } - - c.assembler.CompileTwoRegistersToNone(arm64.CMPW, arm64.RegRZR, selectorRegister) - brIfNotZero := c.assembler.CompileJump(arm64.BCONDNE) - - // In this branch, we select the value of x2, so we move the value into x1.register so that - // we can have the result in x1.register regardless of the selection. - c.assembler.CompileTwoVectorRegistersToVectorRegister(arm64.VORR, - x2.register, x2.register, x1.register, arm64.VectorArrangement16B) - - c.assembler.SetJumpTargetOnNext(brIfNotZero) - - // As noted, the result exists in x1.register regardless of the selector. - c.pushVectorRuntimeValueLocationOnRegister(x1.register) - // Plus, x2.register is no longer used. - c.markRegisterUnused(x2.register) - return nil -} - -// compileSelect implements compiler.compileSelect for the arm64 architecture. -func (c *arm64Compiler) compileSelect(o *wazeroir.UnionOperation) error { - cv, err := c.popValueOnRegister() - if err != nil { - return err - } - - isTargetVector := o.B3 - if isTargetVector { - return c.compileSelectV128Impl(cv.register) - } - - c.markRegisterUsed(cv.register) - - x1, x2, err := c.popTwoValuesOnRegisters() - if err != nil { - return err - } - - if isZeroRegister(x1.register) && isZeroRegister(x2.register) { - // If both values are zero, the result is always zero. - c.pushRuntimeValueLocationOnRegister(arm64.RegRZR, x1.valueType) - c.markRegisterUnused(cv.register) - return nil - } - - // In the following, we emit the code so that x1's register contains the chosen value - // no matter which of original x1 or x2 is selected. - // - // If x1 is currently on zero register, we cannot place the result because - // "MOV arm64.RegRZR x2.register" results in arm64.RegRZR regardless of the value. - // So we explicitly assign a general purpose register to x1 here. - if isZeroRegister(x1.register) { - // Mark x2 and cv's registers are used so they won't be chosen. - c.markRegisterUsed(x2.register) - // Pick the non-zero register for x1. - x1Reg, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - x1.setRegister(x1Reg) - // And zero our the picked register. - c.assembler.CompileRegisterToRegister(arm64.MOVD, arm64.RegRZR, x1Reg) - } - - // At this point, x1 is non-zero register, and x2 is either general purpose or zero register. - - c.assembler.CompileTwoRegistersToNone(arm64.CMPW, arm64.RegRZR, cv.register) - brIfNotZero := c.assembler.CompileJump(arm64.BCONDNE) - - // If cv == 0, we move the value of x2 to the x1.register. - - switch x1.valueType { - case runtimeValueTypeI32: - // TODO: use 32-bit mov - c.assembler.CompileRegisterToRegister(arm64.MOVD, x2.register, x1.register) - case runtimeValueTypeI64: - c.assembler.CompileRegisterToRegister(arm64.MOVD, x2.register, x1.register) - case runtimeValueTypeF32: - // TODO: use 32-bit mov - c.assembler.CompileRegisterToRegister(arm64.FMOVD, x2.register, x1.register) - case runtimeValueTypeF64: - c.assembler.CompileRegisterToRegister(arm64.FMOVD, x2.register, x1.register) - default: - return errors.New("TODO: implement vector type select") - } - - c.pushRuntimeValueLocationOnRegister(x1.register, x1.valueType) - - // Otherwise, nothing to do for select. - c.assembler.SetJumpTargetOnNext(brIfNotZero) - - // Only x1.register is reused. - c.markRegisterUnused(cv.register, x2.register) - return nil -} - -// compilePick implements compiler.compilePick for the arm64 architecture. -func (c *arm64Compiler) compilePick(o *wazeroir.UnionOperation) error { - if err := c.maybeCompileMoveTopConditionalToGeneralPurposeRegister(); err != nil { - return err - } - depth := o.U1 - isTargetVector := o.B3 - - pickTarget := &c.locationStack.stack[c.locationStack.sp-1-uint64(depth)] - pickedRegister, err := c.allocateRegister(pickTarget.getRegisterType()) - if err != nil { - return err - } - - if pickTarget.onRegister() { // Copy the value to the pickedRegister. - switch pickTarget.valueType { - case runtimeValueTypeI32: - c.assembler.CompileRegisterToRegister(arm64.MOVW, pickTarget.register, pickedRegister) - case runtimeValueTypeI64: - c.assembler.CompileRegisterToRegister(arm64.MOVD, pickTarget.register, pickedRegister) - case runtimeValueTypeF32: - c.assembler.CompileRegisterToRegister(arm64.FMOVS, pickTarget.register, pickedRegister) - case runtimeValueTypeF64: - c.assembler.CompileRegisterToRegister(arm64.FMOVD, pickTarget.register, pickedRegister) - case runtimeValueTypeV128Lo: - c.assembler.CompileTwoVectorRegistersToVectorRegister(arm64.VORR, - pickTarget.register, pickTarget.register, pickedRegister, arm64.VectorArrangement16B) - case runtimeValueTypeV128Hi: - panic("BUG") // since pick target must point to the lower 64-bits of vectors. - } - } else if pickTarget.onStack() { - // Temporarily assign a register to the pick target, and then load the value. - pickTarget.setRegister(pickedRegister) - c.compileLoadValueOnStackToRegister(pickTarget) - - // After the load, we revert the register assignment to the pick target. - pickTarget.setRegister(asm.NilRegister) - if isTargetVector { - hi := &c.locationStack.stack[pickTarget.stackPointer+1] - hi.setRegister(asm.NilRegister) - } - } - - // Now we have the value of the target on the pickedRegister, - // so push the location. - c.pushRuntimeValueLocationOnRegister(pickedRegister, pickTarget.valueType) - if isTargetVector { - c.pushRuntimeValueLocationOnRegister(pickedRegister, runtimeValueTypeV128Hi) - } - return nil -} - -// compileAdd implements compiler.compileAdd for the arm64 architecture. -func (c *arm64Compiler) compileAdd(o *wazeroir.UnionOperation) error { - x1, x2, err := c.popTwoValuesOnRegisters() - if err != nil { - return err - } - - // Addition can be nop if one of operands is zero. - if isZeroRegister(x1.register) { - c.pushRuntimeValueLocationOnRegister(x2.register, x1.valueType) - return nil - } else if isZeroRegister(x2.register) { - c.pushRuntimeValueLocationOnRegister(x1.register, x1.valueType) - return nil - } - - var inst asm.Instruction - unsignedType := wazeroir.UnsignedType(o.B1) - switch unsignedType { - case wazeroir.UnsignedTypeI32: - inst = arm64.ADDW - case wazeroir.UnsignedTypeI64: - inst = arm64.ADD - case wazeroir.UnsignedTypeF32: - inst = arm64.FADDS - case wazeroir.UnsignedTypeF64: - inst = arm64.FADDD - } - - c.assembler.CompileRegisterToRegister(inst, x2.register, x1.register) - // The result is placed on a register for x1, so record it. - c.pushRuntimeValueLocationOnRegister(x1.register, x1.valueType) - return nil -} - -// compileSub implements compiler.compileSub for the arm64 architecture. -func (c *arm64Compiler) compileSub(o *wazeroir.UnionOperation) error { - x1, x2, err := c.popTwoValuesOnRegisters() - if err != nil { - return err - } - - // If both of registers are zeros, this can be nop and push the zero register. - if isZeroRegister(x1.register) && isZeroRegister(x2.register) { - c.pushRuntimeValueLocationOnRegister(arm64.RegRZR, x1.valueType) - return nil - } - - // At this point, at least one of x1 or x2 registers is non zero. - // Choose the non-zero register as destination. - destinationReg := x1.register - if isZeroRegister(x1.register) { - destinationReg = x2.register - } - - var inst asm.Instruction - var vt runtimeValueType - unsignedType := wazeroir.UnsignedType(o.B1) - switch unsignedType { - case wazeroir.UnsignedTypeI32: - inst = arm64.SUBW - vt = runtimeValueTypeI32 - case wazeroir.UnsignedTypeI64: - inst = arm64.SUB - vt = runtimeValueTypeI64 - case wazeroir.UnsignedTypeF32: - inst = arm64.FSUBS - vt = runtimeValueTypeF32 - case wazeroir.UnsignedTypeF64: - inst = arm64.FSUBD - vt = runtimeValueTypeF64 - } - - c.assembler.CompileTwoRegistersToRegister(inst, x2.register, x1.register, destinationReg) - c.pushRuntimeValueLocationOnRegister(destinationReg, vt) - return nil -} - -// compileMul implements compiler.compileMul for the arm64 architecture. -func (c *arm64Compiler) compileMul(o *wazeroir.UnionOperation) error { - x1, x2, err := c.popTwoValuesOnRegisters() - if err != nil { - return err - } - - // Multiplication can be done by putting a zero register if one of operands is zero. - if isZeroRegister(x1.register) || isZeroRegister(x2.register) { - c.pushRuntimeValueLocationOnRegister(arm64.RegRZR, x1.valueType) - return nil - } - - var inst asm.Instruction - var vt runtimeValueType - unsignedType := wazeroir.UnsignedType(o.B1) - switch unsignedType { - case wazeroir.UnsignedTypeI32: - inst = arm64.MULW - vt = runtimeValueTypeI32 - case wazeroir.UnsignedTypeI64: - inst = arm64.MUL - vt = runtimeValueTypeI64 - case wazeroir.UnsignedTypeF32: - inst = arm64.FMULS - vt = runtimeValueTypeF32 - case wazeroir.UnsignedTypeF64: - inst = arm64.FMULD - vt = runtimeValueTypeF64 - } - - c.assembler.CompileRegisterToRegister(inst, x2.register, x1.register) - // The result is placed on a register for x1, so record it. - c.pushRuntimeValueLocationOnRegister(x1.register, vt) - return nil -} - -// compileClz implements compiler.compileClz for the arm64 architecture. -func (c *arm64Compiler) compileClz(o *wazeroir.UnionOperation) error { - v, err := c.popValueOnRegister() - if err != nil { - return err - } - - unsignedInt := wazeroir.UnsignedInt(o.B1) - if isZeroRegister(v.register) { - // If the target is zero register, the result is always 32 (or 64 for 64-bits), - // so we allocate a register and put the const on it. - reg, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - var vt runtimeValueType - if unsignedInt == wazeroir.UnsignedInt32 { - vt = runtimeValueTypeI32 - c.assembler.CompileConstToRegister(arm64.MOVW, 32, reg) - } else { - vt = runtimeValueTypeI64 - c.assembler.CompileConstToRegister(arm64.MOVD, 64, reg) - } - c.pushRuntimeValueLocationOnRegister(reg, vt) - return nil - } - - reg := v.register - var vt runtimeValueType - if unsignedInt == wazeroir.UnsignedInt32 { - vt = runtimeValueTypeI32 - c.assembler.CompileRegisterToRegister(arm64.CLZW, reg, reg) - } else { - vt = runtimeValueTypeI64 - c.assembler.CompileRegisterToRegister(arm64.CLZ, reg, reg) - } - c.pushRuntimeValueLocationOnRegister(reg, vt) - return nil -} - -// compileCtz implements compiler.compileCtz for the arm64 architecture. -func (c *arm64Compiler) compileCtz(o *wazeroir.UnionOperation) error { - v, err := c.popValueOnRegister() - if err != nil { - return err - } - - unsignedInt := wazeroir.UnsignedInt(o.B1) - reg := v.register - if isZeroRegister(reg) { - // If the target is zero register, the result is always 32 (or 64 for 64-bits), - // so we allocate a register and put the const on it. - reg, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - var vt runtimeValueType - if unsignedInt == wazeroir.UnsignedInt32 { - vt = runtimeValueTypeI32 - c.assembler.CompileConstToRegister(arm64.MOVW, 32, reg) - } else { - vt = runtimeValueTypeI64 - c.assembler.CompileConstToRegister(arm64.MOVD, 64, reg) - } - c.pushRuntimeValueLocationOnRegister(reg, vt) - return nil - } - - // Since arm64 doesn't have an instruction directly counting trailing zeros, - // we reverse the bits first, and then do CLZ, which is exactly the same as - // gcc implements __builtin_ctz for arm64. - var vt runtimeValueType - if unsignedInt == wazeroir.UnsignedInt32 { - vt = runtimeValueTypeI32 - c.assembler.CompileRegisterToRegister(arm64.RBITW, reg, reg) - c.assembler.CompileRegisterToRegister(arm64.CLZW, reg, reg) - } else { - vt = runtimeValueTypeI64 - c.assembler.CompileRegisterToRegister(arm64.RBIT, reg, reg) - c.assembler.CompileRegisterToRegister(arm64.CLZ, reg, reg) - } - c.pushRuntimeValueLocationOnRegister(reg, vt) - return nil -} - -// compilePopcnt implements compiler.compilePopcnt for the arm64 architecture. -func (c *arm64Compiler) compilePopcnt(o *wazeroir.UnionOperation) error { - v, err := c.popValueOnRegister() - if err != nil { - return err - } - - reg := v.register - if isZeroRegister(reg) { - c.pushRuntimeValueLocationOnRegister(reg, v.valueType) - return nil - } - - freg, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - - // arm64 doesn't have an instruction for population count on scalar register, - // so we use the vector one (VCNT). - // This exactly what the official Go implements bits.OneCount. - // For example, "func () int { return bits.OneCount(10) }" is compiled as - // - // MOVD $10, R0 ;; Load 10. - // FMOVD R0, F0 - // VCNT V0.B8, V0.B8 - // UADDLV V0.B8, V0 - // - var movInst asm.Instruction - unsignedInt := wazeroir.UnsignedInt(o.B1) - if unsignedInt == wazeroir.UnsignedInt32 { - movInst = arm64.FMOVS - } else { - movInst = arm64.FMOVD - } - c.assembler.CompileRegisterToRegister(movInst, reg, freg) - c.assembler.CompileVectorRegisterToVectorRegister(arm64.VCNT, freg, freg, - arm64.VectorArrangement16B, arm64.VectorIndexNone, arm64.VectorIndexNone) - c.assembler.CompileVectorRegisterToVectorRegister(arm64.UADDLV, freg, freg, arm64.VectorArrangement8B, - arm64.VectorIndexNone, arm64.VectorIndexNone) - - c.assembler.CompileRegisterToRegister(movInst, freg, reg) - - c.pushRuntimeValueLocationOnRegister(reg, v.valueType) - return nil -} - -// compileDiv implements compiler.compileDiv for the arm64 architecture. -func (c *arm64Compiler) compileDiv(o *wazeroir.UnionOperation) error { - dividend, divisor, err := c.popTwoValuesOnRegisters() - if err != nil { - return err - } - - signedType := wazeroir.SignedType(o.B1) - - // If the divisor is on the zero register, exit from the function deterministically. - if isZeroRegister(divisor.register) { - // Push any value so that the subsequent instruction can have a consistent location stack state. - v := c.locationStack.pushRuntimeValueLocationOnStack() - switch signedType { - case wazeroir.SignedTypeInt32, wazeroir.SignedTypeUint32: - v.valueType = runtimeValueTypeI32 - case wazeroir.SignedTypeUint64, wazeroir.SignedTypeInt64: - v.valueType = runtimeValueTypeI64 - } - c.compileExitFromNativeCode(nativeCallStatusIntegerDivisionByZero) - return nil - } - - var inst asm.Instruction - var vt runtimeValueType - switch signedType { - case wazeroir.SignedTypeUint32: - inst = arm64.UDIVW - if err := c.compileIntegerDivPrecheck(true, false, dividend.register, divisor.register); err != nil { - return err - } - vt = runtimeValueTypeI32 - case wazeroir.SignedTypeUint64: - if err := c.compileIntegerDivPrecheck(false, false, dividend.register, divisor.register); err != nil { - return err - } - inst = arm64.UDIV - vt = runtimeValueTypeI64 - case wazeroir.SignedTypeInt32: - if err := c.compileIntegerDivPrecheck(true, true, dividend.register, divisor.register); err != nil { - return err - } - inst = arm64.SDIVW - vt = runtimeValueTypeI32 - case wazeroir.SignedTypeInt64: - if err := c.compileIntegerDivPrecheck(false, true, dividend.register, divisor.register); err != nil { - return err - } - inst = arm64.SDIV - vt = runtimeValueTypeI64 - case wazeroir.SignedTypeFloat32: - inst = arm64.FDIVS - vt = runtimeValueTypeF32 - case wazeroir.SignedTypeFloat64: - inst = arm64.FDIVD - vt = runtimeValueTypeF64 - } - - c.assembler.CompileRegisterToRegister(inst, divisor.register, dividend.register) - - c.pushRuntimeValueLocationOnRegister(dividend.register, vt) - return nil -} - -// compileIntegerDivPrecheck adds instructions to check if the divisor and dividend are sound for division operation. -// First, this adds instructions to check if the divisor equals zero, and if so, exits the function. -// Plus, for signed divisions, check if the result might result in overflow or not. -func (c *arm64Compiler) compileIntegerDivPrecheck(is32Bit, isSigned bool, dividend, divisor asm.Register) error { - // We check the divisor value equals zero. - var cmpInst, movInst, loadInst asm.Instruction - var minValueOffsetInVM int64 - if is32Bit { - cmpInst = arm64.CMPW - movInst = arm64.MOVW - loadInst = arm64.LDRW - minValueOffsetInVM = arm64CallEngineArchContextMinimum32BitSignedIntOffset - } else { - cmpInst = arm64.CMP - movInst = arm64.MOVD - loadInst = arm64.LDRD - minValueOffsetInVM = arm64CallEngineArchContextMinimum64BitSignedIntOffset - } - c.assembler.CompileTwoRegistersToNone(cmpInst, arm64.RegRZR, divisor) - - // If it is zero, we exit with nativeCallStatusIntegerDivisionByZero. - c.compileMaybeExitFromNativeCode(arm64.BCONDNE, nativeCallStatusIntegerDivisionByZero) - // Otherwise, we proceed. - - // If the operation is a signed integer div, we have to do an additional check on overflow. - if isSigned { - // For signed division, we have to have branches for "math.MinInt{32,64} / -1" - // case which results in the overflow. - - // First, we compare the divisor with -1. - c.assembler.CompileConstToRegister(movInst, -1, arm64ReservedRegisterForTemporary) - c.assembler.CompileTwoRegistersToNone(cmpInst, arm64ReservedRegisterForTemporary, divisor) - - // If they not equal, we skip the following check. - brIfDivisorNonMinusOne := c.assembler.CompileJump(arm64.BCONDNE) - - // Otherwise, we further check if the dividend equals math.MinInt32 or MinInt64. - c.assembler.CompileMemoryToRegister( - loadInst, - arm64ReservedRegisterForCallEngine, minValueOffsetInVM, - arm64ReservedRegisterForTemporary, - ) - c.assembler.CompileTwoRegistersToNone(cmpInst, arm64ReservedRegisterForTemporary, dividend) - - // If they not equal, we are safe to execute the division. - // Otherwise, we raise overflow error. - c.compileMaybeExitFromNativeCode(arm64.BCONDNE, nativeCallStatusIntegerOverflow) - - c.assembler.SetJumpTargetOnNext(brIfDivisorNonMinusOne) - } - return nil -} - -// compileRem implements compiler.compileRem for the arm64 architecture. -func (c *arm64Compiler) compileRem(o *wazeroir.UnionOperation) error { - dividend, divisor, err := c.popTwoValuesOnRegisters() - if err != nil { - return err - } - - dividendReg := dividend.register - divisorReg := divisor.register - - // If the divisor is on the zero register, exit from the function deterministically. - if isZeroRegister(divisor.register) { - // Push any value so that the subsequent instruction can have a consistent location stack state. - v := c.locationStack.pushRuntimeValueLocationOnStack() - v.valueType = runtimeValueTypeI32 - c.compileExitFromNativeCode(nativeCallStatusIntegerDivisionByZero) - return nil - } - - var divInst, msubInst, cmpInst asm.Instruction - signedInt := wazeroir.SignedInt(o.B1) - switch signedInt { - case wazeroir.SignedUint32: - divInst = arm64.UDIVW - msubInst = arm64.MSUBW - cmpInst = arm64.CMPW - case wazeroir.SignedUint64: - divInst = arm64.UDIV - msubInst = arm64.MSUB - cmpInst = arm64.CMP - case wazeroir.SignedInt32: - divInst = arm64.SDIVW - msubInst = arm64.MSUBW - cmpInst = arm64.CMPW - case wazeroir.SignedInt64: - divInst = arm64.SDIV - msubInst = arm64.MSUB - cmpInst = arm64.CMP - } - - // We check the divisor value equals zero. - c.assembler.CompileTwoRegistersToNone(cmpInst, arm64.RegRZR, divisorReg) - - // If it is zero, we exit with nativeCallStatusIntegerDivisionByZero. - c.compileMaybeExitFromNativeCode(arm64.BCONDNE, nativeCallStatusIntegerDivisionByZero) - // Otherwise, we proceed. - - // Temporarily mark them used to allocate a result register while keeping these values. - c.markRegisterUsed(dividend.register, divisor.register) - - resultReg, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - - // arm64 doesn't have an instruction for rem, we use calculate it by two instructions: UDIV (SDIV for signed) and MSUB. - // This exactly the same code that Clang emits. - // [input: x0=dividend, x1=divisor] - // >> UDIV x2, x0, x1 - // >> MSUB x3, x2, x1, x0 - // [result: x2=quotient, x3=remainder] - // - c.assembler.CompileTwoRegistersToRegister(divInst, divisorReg, dividendReg, resultReg) - // ResultReg = dividendReg - (divisorReg * resultReg) - c.assembler.CompileThreeRegistersToRegister(msubInst, divisorReg, dividendReg, resultReg, resultReg) - - c.markRegisterUnused(dividend.register, divisor.register) - c.pushRuntimeValueLocationOnRegister(resultReg, dividend.valueType) - return nil -} - -// compileAnd implements compiler.compileAnd for the arm64 architecture. -func (c *arm64Compiler) compileAnd(o *wazeroir.UnionOperation) error { - x1, x2, err := c.popTwoValuesOnRegisters() - if err != nil { - return err - } - - // If either of the registers x1 or x2 is zero, - // the result will always be zero. - if isZeroRegister(x1.register) || isZeroRegister(x2.register) { - c.pushRuntimeValueLocationOnRegister(arm64.RegRZR, x1.valueType) - return nil - } - - // At this point, at least one of x1 or x2 registers is non zero. - // Choose the non-zero register as destination. - destinationReg := x1.register - if isZeroRegister(x1.register) { - destinationReg = x2.register - } - - var inst asm.Instruction - unsignedInt := wazeroir.UnsignedInt(o.B1) - switch unsignedInt { - case wazeroir.UnsignedInt32: - inst = arm64.ANDW - case wazeroir.UnsignedInt64: - inst = arm64.AND - } - - c.assembler.CompileTwoRegistersToRegister(inst, x2.register, x1.register, destinationReg) - c.pushRuntimeValueLocationOnRegister(x1.register, x1.valueType) - return nil -} - -// compileOr implements compiler.compileOr for the arm64 architecture. -func (c *arm64Compiler) compileOr(o *wazeroir.UnionOperation) error { - x1, x2, err := c.popTwoValuesOnRegisters() - if err != nil { - return err - } - - if isZeroRegister(x1.register) { - c.pushRuntimeValueLocationOnRegister(x2.register, x2.valueType) - return nil - } - if isZeroRegister(x2.register) { - c.pushRuntimeValueLocationOnRegister(x1.register, x1.valueType) - return nil - } - - var inst asm.Instruction - unsignedInt := wazeroir.UnsignedInt(o.B1) - switch unsignedInt { - case wazeroir.UnsignedInt32: - inst = arm64.ORRW - case wazeroir.UnsignedInt64: - inst = arm64.ORR - } - - c.assembler.CompileTwoRegistersToRegister(inst, x2.register, x1.register, x1.register) - c.pushRuntimeValueLocationOnRegister(x1.register, x1.valueType) - return nil -} - -// compileXor implements compiler.compileXor for the arm64 architecture. -func (c *arm64Compiler) compileXor(o *wazeroir.UnionOperation) error { - x1, x2, err := c.popTwoValuesOnRegisters() - if err != nil { - return err - } - - // At this point, at least one of x1 or x2 registers is non zero. - // Choose the non-zero register as destination. - destinationReg := x1.register - if isZeroRegister(x1.register) { - destinationReg = x2.register - } - - var inst asm.Instruction - unsignedInt := wazeroir.UnsignedInt(o.B1) - switch unsignedInt { - case wazeroir.UnsignedInt32: - inst = arm64.EORW - case wazeroir.UnsignedInt64: - inst = arm64.EOR - } - - c.assembler.CompileTwoRegistersToRegister(inst, x2.register, x1.register, destinationReg) - c.pushRuntimeValueLocationOnRegister(destinationReg, x1.valueType) - return nil -} - -// compileShl implements compiler.compileShl for the arm64 architecture. -func (c *arm64Compiler) compileShl(o *wazeroir.UnionOperation) error { - x1, x2, err := c.popTwoValuesOnRegisters() - if err != nil { - return err - } - - if isZeroRegister(x1.register) || isZeroRegister(x2.register) { - c.pushRuntimeValueLocationOnRegister(x1.register, x1.valueType) - return nil - } - - var inst asm.Instruction - unsignedInt := wazeroir.UnsignedInt(o.B1) - switch unsignedInt { - case wazeroir.UnsignedInt32: - inst = arm64.LSLW - case wazeroir.UnsignedInt64: - inst = arm64.LSL - } - - c.assembler.CompileTwoRegistersToRegister(inst, x2.register, x1.register, x1.register) - c.pushRuntimeValueLocationOnRegister(x1.register, x1.valueType) - return nil -} - -// compileShr implements compiler.compileShr for the arm64 architecture. -func (c *arm64Compiler) compileShr(o *wazeroir.UnionOperation) error { - x1, x2, err := c.popTwoValuesOnRegisters() - if err != nil { - return err - } - - if isZeroRegister(x1.register) || isZeroRegister(x2.register) { - c.pushRuntimeValueLocationOnRegister(x1.register, x1.valueType) - return nil - } - - var inst asm.Instruction - signedInt := wazeroir.SignedInt(o.B1) - switch signedInt { - case wazeroir.SignedInt32: - inst = arm64.ASRW - case wazeroir.SignedInt64: - inst = arm64.ASR - case wazeroir.SignedUint32: - inst = arm64.LSRW - case wazeroir.SignedUint64: - inst = arm64.LSR - } - - c.assembler.CompileTwoRegistersToRegister(inst, x2.register, x1.register, x1.register) - c.pushRuntimeValueLocationOnRegister(x1.register, x1.valueType) - return nil -} - -// compileRotl implements compiler.compileRotl for the arm64 architecture. -func (c *arm64Compiler) compileRotl(o *wazeroir.UnionOperation) error { - x1, x2, err := c.popTwoValuesOnRegisters() - if err != nil { - return err - } - - if isZeroRegister(x1.register) || isZeroRegister(x2.register) { - c.pushRuntimeValueLocationOnRegister(x1.register, x1.valueType) - return nil - } - - var inst, neginst asm.Instruction - unsignedInt := wazeroir.UnsignedInt(o.B1) - switch unsignedInt { - case wazeroir.UnsignedInt32: - inst = arm64.RORW - neginst = arm64.NEGW - case wazeroir.UnsignedInt64: - inst = arm64.ROR - neginst = arm64.NEG - } - - // Arm64 doesn't have rotate left instruction. - // The shift amount needs to be converted to a negative number, similar to assembly output of bits.RotateLeft. - c.assembler.CompileRegisterToRegister(neginst, x2.register, x2.register) - - c.assembler.CompileTwoRegistersToRegister(inst, x2.register, x1.register, x1.register) - c.pushRuntimeValueLocationOnRegister(x1.register, x1.valueType) - return nil -} - -// compileRotr implements compiler.compileRotr for the arm64 architecture. -func (c *arm64Compiler) compileRotr(o *wazeroir.UnionOperation) error { - x1, x2, err := c.popTwoValuesOnRegisters() - if err != nil { - return err - } - - if isZeroRegister(x1.register) || isZeroRegister(x2.register) { - c.pushRuntimeValueLocationOnRegister(x1.register, x1.valueType) - return nil - } - - var inst asm.Instruction - unsignedInt := wazeroir.UnsignedInt(o.B1) - switch unsignedInt { - case wazeroir.UnsignedInt32: - inst = arm64.RORW - case wazeroir.UnsignedInt64: - inst = arm64.ROR - } - - c.assembler.CompileTwoRegistersToRegister(inst, x2.register, x1.register, x1.register) - c.pushRuntimeValueLocationOnRegister(x1.register, x1.valueType) - return nil -} - -// compileAbs implements compiler.compileAbs for the arm64 architecture. -func (c *arm64Compiler) compileAbs(o *wazeroir.UnionOperation) error { - if wazeroir.Float(o.B1) == wazeroir.Float32 { - return c.compileSimpleUnop(arm64.FABSS, runtimeValueTypeF32) - } else { - return c.compileSimpleUnop(arm64.FABSD, runtimeValueTypeF64) - } -} - -// compileNeg implements compiler.compileNeg for the arm64 architecture. -func (c *arm64Compiler) compileNeg(o *wazeroir.UnionOperation) error { - if wazeroir.Float(o.B1) == wazeroir.Float32 { - return c.compileSimpleUnop(arm64.FNEGS, runtimeValueTypeF32) - } else { - return c.compileSimpleUnop(arm64.FNEGD, runtimeValueTypeF64) - } -} - -// compileCeil implements compiler.compileCeil for the arm64 architecture. -func (c *arm64Compiler) compileCeil(o *wazeroir.UnionOperation) error { - if wazeroir.Float(o.B1) == wazeroir.Float32 { - return c.compileSimpleUnop(arm64.FRINTPS, runtimeValueTypeF32) - } else { - return c.compileSimpleUnop(arm64.FRINTPD, runtimeValueTypeF64) - } -} - -// compileFloor implements compiler.compileFloor for the arm64 architecture. -func (c *arm64Compiler) compileFloor(o *wazeroir.UnionOperation) error { - if wazeroir.Float(o.B1) == wazeroir.Float32 { - return c.compileSimpleUnop(arm64.FRINTMS, runtimeValueTypeF32) - } else { - return c.compileSimpleUnop(arm64.FRINTMD, runtimeValueTypeF64) - } -} - -// compileTrunc implements compiler.compileTrunc for the arm64 architecture. -func (c *arm64Compiler) compileTrunc(o *wazeroir.UnionOperation) error { - if wazeroir.Float(o.B1) == wazeroir.Float32 { - return c.compileSimpleUnop(arm64.FRINTZS, runtimeValueTypeF32) - } else { - return c.compileSimpleUnop(arm64.FRINTZD, runtimeValueTypeF64) - } -} - -// compileNearest implements compiler.compileNearest for the arm64 architecture. -func (c *arm64Compiler) compileNearest(o *wazeroir.UnionOperation) error { - if wazeroir.Float(o.B1) == wazeroir.Float32 { - return c.compileSimpleUnop(arm64.FRINTNS, runtimeValueTypeF32) - } else { - return c.compileSimpleUnop(arm64.FRINTND, runtimeValueTypeF64) - } -} - -// compileSqrt implements compiler.compileSqrt for the arm64 architecture. -func (c *arm64Compiler) compileSqrt(o *wazeroir.UnionOperation) error { - if wazeroir.Float(o.B1) == wazeroir.Float32 { - return c.compileSimpleUnop(arm64.FSQRTS, runtimeValueTypeF32) - } else { - return c.compileSimpleUnop(arm64.FSQRTD, runtimeValueTypeF64) - } -} - -// compileMin implements compiler.compileMin for the arm64 architecture. -func (c *arm64Compiler) compileMin(o *wazeroir.UnionOperation) error { - if wazeroir.Float(o.B1) == wazeroir.Float32 { - return c.compileSimpleFloatBinop(arm64.FMINS) - } else { - return c.compileSimpleFloatBinop(arm64.FMIND) - } -} - -// compileMax implements compiler.compileMax for the arm64 architecture. -func (c *arm64Compiler) compileMax(o *wazeroir.UnionOperation) error { - if wazeroir.Float(o.B1) == wazeroir.Float32 { - return c.compileSimpleFloatBinop(arm64.FMAXS) - } else { - return c.compileSimpleFloatBinop(arm64.FMAXD) - } -} - -func (c *arm64Compiler) compileSimpleFloatBinop(inst asm.Instruction) error { - x1, x2, err := c.popTwoValuesOnRegisters() - if err != nil { - return err - } - c.assembler.CompileRegisterToRegister(inst, x2.register, x1.register) - c.pushRuntimeValueLocationOnRegister(x1.register, x1.valueType) - return nil -} - -// compileCopysign implements compiler.compileCopysign for the arm64 architecture. -func (c *arm64Compiler) compileCopysign(o *wazeroir.UnionOperation) error { - x1, x2, err := c.popTwoValuesOnRegisters() - if err != nil { - return err - } - - var ldr asm.Instruction - var minValueOffsetInVM int64 - if wazeroir.Float(o.B1) == wazeroir.Float32 { - ldr = arm64.FLDRS - minValueOffsetInVM = arm64CallEngineArchContextMinimum32BitSignedIntOffset - } else { - ldr = arm64.FLDRD - minValueOffsetInVM = arm64CallEngineArchContextMinimum64BitSignedIntOffset - } - - c.markRegisterUsed(x1.register, x2.register) - freg, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - - // This is exactly the same code emitted by GCC for "__builtin_copysign": - // - // mov x0, -9223372036854775808 - // fmov d2, x0 - // vbit v0.8b, v1.8b, v2.8b - // - // "mov freg, -9223372036854775808 (stored at ce.minimum64BitSignedInt)" - c.assembler.CompileMemoryToRegister( - ldr, - arm64ReservedRegisterForCallEngine, minValueOffsetInVM, - freg, - ) - - // VBIT inserts each bit from the first operand into the destination if the corresponding bit of the second operand is 1, - // otherwise it leaves the destination bit unchanged. - // See https://developer.arm.com/documentation/dui0801/g/Advanced-SIMD-Instructions--32-bit-/VBIT - // - // "vbit vreg.8b, x2vreg.8b, x1vreg.8b" == "inserting 64th bit of x2 into x1". - c.assembler.CompileTwoVectorRegistersToVectorRegister(arm64.VBIT, - freg, x2.register, x1.register, arm64.VectorArrangement16B) - - c.markRegisterUnused(x2.register) - c.pushRuntimeValueLocationOnRegister(x1.register, x1.valueType) - return nil -} - -// compileI32WrapFromI64 implements compiler.compileI32WrapFromI64 for the arm64 architecture. -func (c *arm64Compiler) compileI32WrapFromI64() error { - return c.compileSimpleUnop(arm64.MOVW, runtimeValueTypeI32) -} - -// compileITruncFromF implements compiler.compileITruncFromF for the arm64 architecture. -func (c *arm64Compiler) compileITruncFromF(o *wazeroir.UnionOperation) error { - // Clear the floating point status register (FPSR). - c.assembler.CompileRegisterToRegister(arm64.MSR, arm64.RegRZR, arm64.RegFPSR) - - var vt runtimeValueType - var convinst asm.Instruction - inputType := wazeroir.Float(o.B1) - outputType := wazeroir.SignedInt(o.B2) - nonTrapping := o.B3 - - is32bitFloat := inputType == wazeroir.Float32 - if is32bitFloat && outputType == wazeroir.SignedInt32 { - convinst = arm64.FCVTZSSW - vt = runtimeValueTypeI32 - } else if is32bitFloat && outputType == wazeroir.SignedInt64 { - convinst = arm64.FCVTZSS - vt = runtimeValueTypeI64 - } else if !is32bitFloat && outputType == wazeroir.SignedInt32 { - convinst = arm64.FCVTZSDW - vt = runtimeValueTypeI32 - } else if !is32bitFloat && outputType == wazeroir.SignedInt64 { - convinst = arm64.FCVTZSD - vt = runtimeValueTypeI64 - } else if is32bitFloat && outputType == wazeroir.SignedUint32 { - convinst = arm64.FCVTZUSW - vt = runtimeValueTypeI32 - } else if is32bitFloat && outputType == wazeroir.SignedUint64 { - convinst = arm64.FCVTZUS - vt = runtimeValueTypeI64 - } else if !is32bitFloat && outputType == wazeroir.SignedUint32 { - convinst = arm64.FCVTZUDW - vt = runtimeValueTypeI32 - } else if !is32bitFloat && outputType == wazeroir.SignedUint64 { - convinst = arm64.FCVTZUD - vt = runtimeValueTypeI64 - } - - source, err := c.popValueOnRegister() - if err != nil { - return err - } - sourceReg := source.register - - destinationReg, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - - c.assembler.CompileRegisterToRegister(convinst, sourceReg, destinationReg) - c.pushRuntimeValueLocationOnRegister(destinationReg, vt) - - if !nonTrapping { - // Obtain the floating point status register value into the general purpose register, - // so that we can check if the conversion resulted in undefined behavior. - c.assembler.CompileRegisterToRegister(arm64.MRS, arm64.RegFPSR, arm64ReservedRegisterForTemporary) - // Check if the conversion was undefined by comparing the status with 1. - // See https://developer.arm.com/documentation/ddi0595/2020-12/AArch64-Registers/FPSR--Floating-point-Status-Register - c.assembler.CompileRegisterAndConstToNone(arm64.CMP, arm64ReservedRegisterForTemporary, 1) - - brOK := c.assembler.CompileJump(arm64.BCONDNE) - - // If so, exit the execution with errors depending on whether or not the source value is NaN. - var floatcmp asm.Instruction - if is32bitFloat { - floatcmp = arm64.FCMPS - } else { - floatcmp = arm64.FCMPD - } - c.assembler.CompileTwoRegistersToNone(floatcmp, sourceReg, sourceReg) - // VS flag is set if at least one of values for FCMP is NaN. - // https://developer.arm.com/documentation/dui0801/g/Condition-Codes/Comparison-of-condition-code-meanings-in-integer-and-floating-point-code - // If the source value is not NaN, the operation was overflow. - c.compileMaybeExitFromNativeCode(arm64.BCONDVS, nativeCallStatusIntegerOverflow) - - // Otherwise, the operation was invalid as this is trying to convert NaN to integer. - c.compileExitFromNativeCode(nativeCallStatusCodeInvalidFloatToIntConversion) - - // Otherwise, we branch into the next instruction. - c.assembler.SetJumpTargetOnNext(brOK) - } - return nil -} - -// compileFConvertFromI implements compiler.compileFConvertFromI for the arm64 architecture. -func (c *arm64Compiler) compileFConvertFromI(o *wazeroir.UnionOperation) error { - var convinst asm.Instruction - inputType := wazeroir.SignedInt(o.B1) - outputType := wazeroir.Float(o.B2) - - if outputType == wazeroir.Float32 && inputType == wazeroir.SignedInt32 { - convinst = arm64.SCVTFWS - } else if outputType == wazeroir.Float32 && inputType == wazeroir.SignedInt64 { - convinst = arm64.SCVTFS - } else if outputType == wazeroir.Float64 && inputType == wazeroir.SignedInt32 { - convinst = arm64.SCVTFWD - } else if outputType == wazeroir.Float64 && inputType == wazeroir.SignedInt64 { - convinst = arm64.SCVTFD - } else if outputType == wazeroir.Float32 && inputType == wazeroir.SignedUint32 { - convinst = arm64.UCVTFWS - } else if outputType == wazeroir.Float32 && inputType == wazeroir.SignedUint64 { - convinst = arm64.UCVTFS - } else if outputType == wazeroir.Float64 && inputType == wazeroir.SignedUint32 { - convinst = arm64.UCVTFWD - } else if outputType == wazeroir.Float64 && inputType == wazeroir.SignedUint64 { - convinst = arm64.UCVTFD - } - - var vt runtimeValueType - if outputType == wazeroir.Float32 { - vt = runtimeValueTypeF32 - } else { - vt = runtimeValueTypeF64 - } - return c.compileSimpleConversion(convinst, registerTypeVector, vt) -} - -// compileF32DemoteFromF64 implements compiler.compileF32DemoteFromF64 for the arm64 architecture. -func (c *arm64Compiler) compileF32DemoteFromF64() error { - return c.compileSimpleUnop(arm64.FCVTDS, runtimeValueTypeF32) -} - -// compileF64PromoteFromF32 implements compiler.compileF64PromoteFromF32 for the arm64 architecture. -func (c *arm64Compiler) compileF64PromoteFromF32() error { - return c.compileSimpleUnop(arm64.FCVTSD, runtimeValueTypeF64) -} - -// compileI32ReinterpretFromF32 implements compiler.compileI32ReinterpretFromF32 for the arm64 architecture. -func (c *arm64Compiler) compileI32ReinterpretFromF32() error { - if peek := c.locationStack.peek(); peek.onStack() { - // If the value is on the stack, this is no-op as there is nothing to do for converting type. - peek.valueType = runtimeValueTypeI32 - return nil - } - return c.compileSimpleConversion(arm64.FMOVS, registerTypeGeneralPurpose, runtimeValueTypeI32) -} - -// compileI64ReinterpretFromF64 implements compiler.compileI64ReinterpretFromF64 for the arm64 architecture. -func (c *arm64Compiler) compileI64ReinterpretFromF64() error { - if peek := c.locationStack.peek(); peek.onStack() { - // If the value is on the stack, this is no-op as there is nothing to do for converting type. - peek.valueType = runtimeValueTypeI64 - return nil - } - return c.compileSimpleConversion(arm64.FMOVD, registerTypeGeneralPurpose, runtimeValueTypeI64) -} - -// compileF32ReinterpretFromI32 implements compiler.compileF32ReinterpretFromI32 for the arm64 architecture. -func (c *arm64Compiler) compileF32ReinterpretFromI32() error { - if peek := c.locationStack.peek(); peek.onStack() { - // If the value is on the stack, this is no-op as there is nothing to do for converting type. - peek.valueType = runtimeValueTypeF32 - return nil - } - return c.compileSimpleConversion(arm64.FMOVS, registerTypeVector, runtimeValueTypeF32) -} - -// compileF64ReinterpretFromI64 implements compiler.compileF64ReinterpretFromI64 for the arm64 architecture. -func (c *arm64Compiler) compileF64ReinterpretFromI64() error { - if peek := c.locationStack.peek(); peek.onStack() { - // If the value is on the stack, this is no-op as there is nothing to do for converting type. - peek.valueType = runtimeValueTypeF64 - return nil - } - return c.compileSimpleConversion(arm64.FMOVD, registerTypeVector, runtimeValueTypeF64) -} - -func (c *arm64Compiler) compileSimpleConversion(inst asm.Instruction, destinationRegType registerType, resultRuntimeValueType runtimeValueType) error { - source, err := c.popValueOnRegister() - if err != nil { - return err - } - - destinationReg, err := c.allocateRegister(destinationRegType) - if err != nil { - return err - } - - c.assembler.CompileRegisterToRegister(inst, source.register, destinationReg) - c.pushRuntimeValueLocationOnRegister(destinationReg, resultRuntimeValueType) - return nil -} - -// compileExtend implements compiler.compileExtend for the arm64 architecture. -func (c *arm64Compiler) compileExtend(o *wazeroir.UnionOperation) error { - signed := o.B1 != 0 - if signed { - return c.compileSimpleUnop(arm64.SXTW, runtimeValueTypeI64) - } else { - return c.compileSimpleUnop(arm64.MOVW, runtimeValueTypeI64) - } -} - -// compileSignExtend32From8 implements compiler.compileSignExtend32From8 for the arm64 architecture. -func (c *arm64Compiler) compileSignExtend32From8() error { - return c.compileSimpleUnop(arm64.SXTBW, runtimeValueTypeI32) -} - -// compileSignExtend32From16 implements compiler.compileSignExtend32From16 for the arm64 architecture. -func (c *arm64Compiler) compileSignExtend32From16() error { - return c.compileSimpleUnop(arm64.SXTHW, runtimeValueTypeI32) -} - -// compileSignExtend64From8 implements compiler.compileSignExtend64From8 for the arm64 architecture. -func (c *arm64Compiler) compileSignExtend64From8() error { - return c.compileSimpleUnop(arm64.SXTB, runtimeValueTypeI64) -} - -// compileSignExtend64From16 implements compiler.compileSignExtend64From16 for the arm64 architecture. -func (c *arm64Compiler) compileSignExtend64From16() error { - return c.compileSimpleUnop(arm64.SXTH, runtimeValueTypeI64) -} - -// compileSignExtend64From32 implements compiler.compileSignExtend64From32 for the arm64 architecture. -func (c *arm64Compiler) compileSignExtend64From32() error { - return c.compileSimpleUnop(arm64.SXTW, runtimeValueTypeI64) -} - -func (c *arm64Compiler) compileSimpleUnop(inst asm.Instruction, resultRuntimeValueType runtimeValueType) error { - v, err := c.popValueOnRegister() - if err != nil { - return err - } - reg := v.register - c.assembler.CompileRegisterToRegister(inst, reg, reg) - c.pushRuntimeValueLocationOnRegister(reg, resultRuntimeValueType) - return nil -} - -// compileEq implements compiler.compileEq for the arm64 architecture. -func (c *arm64Compiler) compileEq(o *wazeroir.UnionOperation) error { - return c.emitEqOrNe(true, wazeroir.UnsignedType(o.B1)) -} - -// compileNe implements compiler.compileNe for the arm64 architecture. -func (c *arm64Compiler) compileNe(o *wazeroir.UnionOperation) error { - return c.emitEqOrNe(false, wazeroir.UnsignedType(o.B1)) -} - -// emitEqOrNe implements compiler.compileEq and compiler.compileNe for the arm64 architecture. -func (c *arm64Compiler) emitEqOrNe(isEq bool, unsignedType wazeroir.UnsignedType) error { - x1, x2, err := c.popTwoValuesOnRegisters() - if err != nil { - return err - } - - var inst asm.Instruction - switch unsignedType { - case wazeroir.UnsignedTypeI32: - inst = arm64.CMPW - case wazeroir.UnsignedTypeI64: - inst = arm64.CMP - case wazeroir.UnsignedTypeF32: - inst = arm64.FCMPS - case wazeroir.UnsignedTypeF64: - inst = arm64.FCMPD - } - - c.assembler.CompileTwoRegistersToNone(inst, x2.register, x1.register) - - // Push the comparison result as a conditional register value. - cond := arm64.CondNE - if isEq { - cond = arm64.CondEQ - } - c.locationStack.pushRuntimeValueLocationOnConditionalRegister(cond) - return nil -} - -// compileEqz implements compiler.compileEqz for the arm64 architecture. -func (c *arm64Compiler) compileEqz(o *wazeroir.UnionOperation) error { - x1, err := c.popValueOnRegister() - if err != nil { - return err - } - - var inst asm.Instruction - unsignedInt := wazeroir.UnsignedInt(o.B1) - switch unsignedInt { - case wazeroir.UnsignedInt32: - inst = arm64.CMPW - case wazeroir.UnsignedInt64: - inst = arm64.CMP - } - - c.assembler.CompileTwoRegistersToNone(inst, arm64.RegRZR, x1.register) - - // Push the comparison result as a conditional register value. - c.locationStack.pushRuntimeValueLocationOnConditionalRegister(arm64.CondEQ) - return nil -} - -// compileLt implements compiler.compileLt for the arm64 architecture. -func (c *arm64Compiler) compileLt(o *wazeroir.UnionOperation) error { - x1, x2, err := c.popTwoValuesOnRegisters() - if err != nil { - return err - } - - var inst asm.Instruction - var conditionalRegister asm.ConditionalRegisterState - signedType := wazeroir.SignedType(o.B1) - switch signedType { - case wazeroir.SignedTypeUint32: - inst = arm64.CMPW - conditionalRegister = arm64.CondLO - case wazeroir.SignedTypeUint64: - inst = arm64.CMP - conditionalRegister = arm64.CondLO - case wazeroir.SignedTypeInt32: - inst = arm64.CMPW - conditionalRegister = arm64.CondLT - case wazeroir.SignedTypeInt64: - inst = arm64.CMP - conditionalRegister = arm64.CondLT - case wazeroir.SignedTypeFloat32: - inst = arm64.FCMPS - conditionalRegister = arm64.CondMI - case wazeroir.SignedTypeFloat64: - inst = arm64.FCMPD - conditionalRegister = arm64.CondMI - } - - c.assembler.CompileTwoRegistersToNone(inst, x2.register, x1.register) - - // Push the comparison result as a conditional register value. - c.locationStack.pushRuntimeValueLocationOnConditionalRegister(conditionalRegister) - return nil -} - -// compileGt implements compiler.compileGt for the arm64 architecture. -func (c *arm64Compiler) compileGt(o *wazeroir.UnionOperation) error { - x1, x2, err := c.popTwoValuesOnRegisters() - if err != nil { - return err - } - - var inst asm.Instruction - var conditionalRegister asm.ConditionalRegisterState - signedType := wazeroir.SignedType(o.B1) - switch signedType { - case wazeroir.SignedTypeUint32: - inst = arm64.CMPW - conditionalRegister = arm64.CondHI - case wazeroir.SignedTypeUint64: - inst = arm64.CMP - conditionalRegister = arm64.CondHI - case wazeroir.SignedTypeInt32: - inst = arm64.CMPW - conditionalRegister = arm64.CondGT - case wazeroir.SignedTypeInt64: - inst = arm64.CMP - conditionalRegister = arm64.CondGT - case wazeroir.SignedTypeFloat32: - inst = arm64.FCMPS - conditionalRegister = arm64.CondGT - case wazeroir.SignedTypeFloat64: - inst = arm64.FCMPD - conditionalRegister = arm64.CondGT - } - - c.assembler.CompileTwoRegistersToNone(inst, x2.register, x1.register) - - // Push the comparison result as a conditional register value. - c.locationStack.pushRuntimeValueLocationOnConditionalRegister(conditionalRegister) - return nil -} - -// compileLe implements compiler.compileLe for the arm64 architecture. -func (c *arm64Compiler) compileLe(o *wazeroir.UnionOperation) error { - x1, x2, err := c.popTwoValuesOnRegisters() - if err != nil { - return err - } - - var inst asm.Instruction - var conditionalRegister asm.ConditionalRegisterState - signedType := wazeroir.SignedType(o.B1) - switch signedType { - case wazeroir.SignedTypeUint32: - inst = arm64.CMPW - conditionalRegister = arm64.CondLS - case wazeroir.SignedTypeUint64: - inst = arm64.CMP - conditionalRegister = arm64.CondLS - case wazeroir.SignedTypeInt32: - inst = arm64.CMPW - conditionalRegister = arm64.CondLE - case wazeroir.SignedTypeInt64: - inst = arm64.CMP - conditionalRegister = arm64.CondLE - case wazeroir.SignedTypeFloat32: - inst = arm64.FCMPS - conditionalRegister = arm64.CondLS - case wazeroir.SignedTypeFloat64: - inst = arm64.FCMPD - conditionalRegister = arm64.CondLS - } - - c.assembler.CompileTwoRegistersToNone(inst, x2.register, x1.register) - - // Push the comparison result as a conditional register value. - c.locationStack.pushRuntimeValueLocationOnConditionalRegister(conditionalRegister) - return nil -} - -// compileGe implements compiler.compileGe for the arm64 architecture. -func (c *arm64Compiler) compileGe(o *wazeroir.UnionOperation) error { - x1, x2, err := c.popTwoValuesOnRegisters() - if err != nil { - return err - } - - var inst asm.Instruction - var conditionalRegister asm.ConditionalRegisterState - signedType := wazeroir.SignedType(o.B1) - switch signedType { - case wazeroir.SignedTypeUint32: - inst = arm64.CMPW - conditionalRegister = arm64.CondHS - case wazeroir.SignedTypeUint64: - inst = arm64.CMP - conditionalRegister = arm64.CondHS - case wazeroir.SignedTypeInt32: - inst = arm64.CMPW - conditionalRegister = arm64.CondGE - case wazeroir.SignedTypeInt64: - inst = arm64.CMP - conditionalRegister = arm64.CondGE - case wazeroir.SignedTypeFloat32: - inst = arm64.FCMPS - conditionalRegister = arm64.CondGE - case wazeroir.SignedTypeFloat64: - inst = arm64.FCMPD - conditionalRegister = arm64.CondGE - } - - c.assembler.CompileTwoRegistersToNone(inst, x2.register, x1.register) - - // Push the comparison result as a conditional register value. - c.locationStack.pushRuntimeValueLocationOnConditionalRegister(conditionalRegister) - return nil -} - -// compileLoad implements compiler.compileLoad for the arm64 architecture. -func (c *arm64Compiler) compileLoad(o *wazeroir.UnionOperation) error { - var ( - isFloat bool - loadInst asm.Instruction - targetSizeInBytes int64 - vt runtimeValueType - ) - - unsignedType := wazeroir.UnsignedType(o.B1) - offset := uint32(o.U2) - - switch unsignedType { - case wazeroir.UnsignedTypeI32: - loadInst = arm64.LDRW - targetSizeInBytes = 32 / 8 - vt = runtimeValueTypeI32 - case wazeroir.UnsignedTypeI64: - loadInst = arm64.LDRD - targetSizeInBytes = 64 / 8 - vt = runtimeValueTypeI64 - case wazeroir.UnsignedTypeF32: - loadInst = arm64.FLDRS - isFloat = true - targetSizeInBytes = 32 / 8 - vt = runtimeValueTypeF32 - case wazeroir.UnsignedTypeF64: - loadInst = arm64.FLDRD - isFloat = true - targetSizeInBytes = 64 / 8 - vt = runtimeValueTypeF64 - } - return c.compileLoadImpl(offset, loadInst, targetSizeInBytes, isFloat, vt) -} - -// compileLoad8 implements compiler.compileLoad8 for the arm64 architecture. -func (c *arm64Compiler) compileLoad8(o *wazeroir.UnionOperation) error { - var loadInst asm.Instruction - var vt runtimeValueType - - signedInt := wazeroir.SignedInt(o.B1) - offset := uint32(o.U2) - - switch signedInt { - case wazeroir.SignedInt32: - loadInst = arm64.LDRSBW - vt = runtimeValueTypeI32 - case wazeroir.SignedInt64: - loadInst = arm64.LDRSBD - vt = runtimeValueTypeI64 - case wazeroir.SignedUint32: - loadInst = arm64.LDRB - vt = runtimeValueTypeI32 - case wazeroir.SignedUint64: - loadInst = arm64.LDRB - vt = runtimeValueTypeI64 - } - return c.compileLoadImpl(offset, loadInst, 1, false, vt) -} - -// compileLoad16 implements compiler.compileLoad16 for the arm64 architecture. -func (c *arm64Compiler) compileLoad16(o *wazeroir.UnionOperation) error { - var loadInst asm.Instruction - var vt runtimeValueType - - signedInt := wazeroir.SignedInt(o.B1) - offset := uint32(o.U2) - - switch signedInt { - case wazeroir.SignedInt32: - loadInst = arm64.LDRSHW - vt = runtimeValueTypeI32 - case wazeroir.SignedInt64: - loadInst = arm64.LDRSHD - vt = runtimeValueTypeI64 - case wazeroir.SignedUint32: - loadInst = arm64.LDRH - vt = runtimeValueTypeI32 - case wazeroir.SignedUint64: - loadInst = arm64.LDRH - vt = runtimeValueTypeI64 - } - return c.compileLoadImpl(offset, loadInst, 16/8, false, vt) -} - -// compileLoad32 implements compiler.compileLoad32 for the arm64 architecture. -func (c *arm64Compiler) compileLoad32(o *wazeroir.UnionOperation) error { - var loadInst asm.Instruction - signed := o.B1 == 1 - offset := uint32(o.U2) - - if signed { - loadInst = arm64.LDRSW - } else { - loadInst = arm64.LDRW - } - return c.compileLoadImpl(offset, loadInst, 32/8, false, runtimeValueTypeI64) -} - -// compileLoadImpl implements compileLoadImpl* variants for arm64 architecture. -func (c *arm64Compiler) compileLoadImpl(offsetArg uint32, loadInst asm.Instruction, - targetSizeInBytes int64, isFloat bool, resultRuntimeValueType runtimeValueType, -) error { - offsetReg, err := c.compileMemoryAccessOffsetSetup(offsetArg, targetSizeInBytes) - if err != nil { - return err - } - - resultRegister := offsetReg - if isFloat { - resultRegister, err = c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - } - - // "resultRegister = [arm64ReservedRegisterForMemory + offsetReg]" - // In other words, "resultRegister = memory.Buffer[offset: offset+targetSizeInBytes]" - c.assembler.CompileMemoryWithRegisterOffsetToRegister( - loadInst, - arm64ReservedRegisterForMemory, offsetReg, - resultRegister, - ) - - c.pushRuntimeValueLocationOnRegister(resultRegister, resultRuntimeValueType) - return nil -} - -// compileStore implements compiler.compileStore for the arm64 architecture. -func (c *arm64Compiler) compileStore(o *wazeroir.UnionOperation) error { - var movInst asm.Instruction - var targetSizeInBytes int64 - unsignedType := wazeroir.UnsignedType(o.B1) - offset := uint32(o.U2) - switch unsignedType { - case wazeroir.UnsignedTypeI32: - movInst = arm64.STRW - targetSizeInBytes = 32 / 8 - case wazeroir.UnsignedTypeI64: - movInst = arm64.STRD - targetSizeInBytes = 64 / 8 - case wazeroir.UnsignedTypeF32: - movInst = arm64.FSTRS - targetSizeInBytes = 32 / 8 - case wazeroir.UnsignedTypeF64: - movInst = arm64.FSTRD - targetSizeInBytes = 64 / 8 - } - return c.compileStoreImpl(offset, movInst, targetSizeInBytes) -} - -// compileStore8 implements compiler.compileStore8 for the arm64 architecture. -func (c *arm64Compiler) compileStore8(o *wazeroir.UnionOperation) error { - return c.compileStoreImpl(uint32(o.U2), arm64.STRB, 1) -} - -// compileStore16 implements compiler.compileStore16 for the arm64 architecture. -func (c *arm64Compiler) compileStore16(o *wazeroir.UnionOperation) error { - return c.compileStoreImpl(uint32(o.U2), arm64.STRH, 16/8) -} - -// compileStore32 implements compiler.compileStore32 for the arm64 architecture. -func (c *arm64Compiler) compileStore32(o *wazeroir.UnionOperation) error { - return c.compileStoreImpl(uint32(o.U2), arm64.STRW, 32/8) -} - -// compileStoreImpl implements compleStore* variants for arm64 architecture. -func (c *arm64Compiler) compileStoreImpl(offsetArg uint32, storeInst asm.Instruction, targetSizeInBytes int64) error { - val, err := c.popValueOnRegister() - if err != nil { - return err - } - // Mark temporarily used as compileMemoryAccessOffsetSetup might try allocating register. - c.markRegisterUsed(val.register) - - offsetReg, err := c.compileMemoryAccessOffsetSetup(offsetArg, targetSizeInBytes) - if err != nil { - return err - } - - // "[arm64ReservedRegisterForMemory + offsetReg] = val.register" - // In other words, "memory.Buffer[offset: offset+targetSizeInBytes] = val.register" - c.assembler.CompileRegisterToMemoryWithRegisterOffset( - storeInst, val.register, - arm64ReservedRegisterForMemory, offsetReg, - ) - - c.markRegisterUnused(val.register) - return nil -} - -// compileMemoryAccessOffsetSetup pops the top value from the stack (called "base"), stores "base + offsetArg" -// into a register, and returns the stored register. We call the result "offset" because we access the memory -// as memory.Buffer[offset: offset+targetSizeInBytes]. -// -// Note: this also emits the instructions to check the out of bounds memory access. -// In other words, if the offset+targetSizeInBytes exceeds the memory size, the code exits with nativeCallStatusCodeMemoryOutOfBounds status. -func (c *arm64Compiler) compileMemoryAccessOffsetSetup(offsetArg uint32, targetSizeInBytes int64) (offsetRegister asm.Register, err error) { - base, err := c.popValueOnRegister() - if err != nil { - return 0, err - } - - offsetRegister = base.register - if isZeroRegister(base.register) { - offsetRegister, err = c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return - } - c.assembler.CompileRegisterToRegister(arm64.MOVD, arm64.RegRZR, offsetRegister) - } - - if offsetConst := int64(offsetArg) + targetSizeInBytes; offsetConst <= math.MaxUint32 { - // "offsetRegister = base + offsetArg + targetSizeInBytes" - c.assembler.CompileConstToRegister(arm64.ADD, offsetConst, offsetRegister) - } else { - // If the offset const is too large, we exit with nativeCallStatusCodeMemoryOutOfBounds. - c.compileExitFromNativeCode(nativeCallStatusCodeMemoryOutOfBounds) - return - } - - // "arm64ReservedRegisterForTemporary = len(memory.Buffer)" - c.compileLoadMemoryBufferLen(arm64ReservedRegisterForTemporary) - - // Check if offsetRegister(= base+offsetArg+targetSizeInBytes) > len(memory.Buffer). - c.assembler.CompileTwoRegistersToNone(arm64.CMP, arm64ReservedRegisterForTemporary, offsetRegister) - - // If offsetRegister(= base+offsetArg+targetSizeInBytes) exceeds the memory length, - // we exit the function with nativeCallStatusCodeMemoryOutOfBounds. - c.compileMaybeExitFromNativeCode(arm64.BCONDLS, nativeCallStatusCodeMemoryOutOfBounds) - - // Otherwise, we subtract targetSizeInBytes from offsetRegister. - c.assembler.CompileConstToRegister(arm64.SUB, targetSizeInBytes, offsetRegister) - return offsetRegister, nil -} - -// compileMemoryGrow implements compileMemoryGrow variants for arm64 architecture. -func (c *arm64Compiler) compileMemoryGrow() error { - if err := c.maybeCompileMoveTopConditionalToGeneralPurposeRegister(); err != nil { - return err - } - - if err := c.compileCallGoFunction(nativeCallStatusCodeCallBuiltInFunction, builtinFunctionIndexMemoryGrow); err != nil { - return err - } - - // After return, we re-initialize reserved registers just like preamble of functions. - c.compileReservedStackBasePointerRegisterInitialization() - c.compileReservedMemoryRegisterInitialization() - return nil -} - -// compileMemorySize implements compileMemorySize variants for arm64 architecture. -func (c *arm64Compiler) compileMemorySize() error { - if err := c.maybeCompileMoveTopConditionalToGeneralPurposeRegister(); err != nil { - return err - } - - reg, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - - // "reg = len(memory.Buffer)" - c.compileLoadMemoryBufferLen(reg) - - // memory.size loads the page size of memory, so we have to divide by the page size. - // "reg = reg >> wasm.MemoryPageSizeInBits (== reg / wasm.MemoryPageSize) " - c.assembler.CompileConstToRegister( - arm64.LSR, - wasm.MemoryPageSizeInBits, - reg, - ) - - c.pushRuntimeValueLocationOnRegister(reg, runtimeValueTypeI32) - return nil -} - -// compileCallGoFunction adds instructions to call a Go function whose address equals the addr parameter. -// compilerStatus is set before making call, and it should be either nativeCallStatusCodeCallBuiltInFunction or -// nativeCallStatusCodeCallGoHostFunction. -func (c *arm64Compiler) compileCallGoFunction(compilerStatus nativeCallStatusCode, builtinFunction wasm.Index) error { - // Release all the registers as our calling convention requires the caller-save. - if err := c.compileReleaseAllRegistersToStack(); err != nil { - return err - } - - if compilerStatus == nativeCallStatusCodeCallBuiltInFunction { - // Set the target function address to ce.functionCallAddress - // "tmp = $index" - c.assembler.CompileConstToRegister( - arm64.MOVD, - int64(builtinFunction), - arm64ReservedRegisterForTemporary, - ) - // "[arm64ReservedRegisterForCallEngine + callEngineExitContextFunctionCallAddressOffset] = tmp" - // In other words, "ce.functionCallAddress = tmp (== $addr)" - c.assembler.CompileRegisterToMemory( - arm64.STRW, - arm64ReservedRegisterForTemporary, - arm64ReservedRegisterForCallEngine, callEngineExitContextBuiltinFunctionCallIndexOffset, - ) - } - - c.compileExitFromNativeCode(compilerStatus) - return nil -} - -// compileConstI32 implements compiler.compileConstI32 for the arm64 architecture. -func (c *arm64Compiler) compileConstI32(o *wazeroir.UnionOperation) error { - return c.compileIntConstant(true, o.U1) -} - -// compileConstI64 implements compiler.compileConstI64 for the arm64 architecture. -func (c *arm64Compiler) compileConstI64(o *wazeroir.UnionOperation) error { - return c.compileIntConstant(false, o.U1) -} - -// compileIntConstant adds instructions to load an integer constant. -// is32bit is true if the target value is originally 32-bit const, false otherwise. -// value holds the (zero-extended for 32-bit case) load target constant. -func (c *arm64Compiler) compileIntConstant(is32bit bool, value uint64) error { - if err := c.maybeCompileMoveTopConditionalToGeneralPurposeRegister(); err != nil { - return err - } - - var inst asm.Instruction - var vt runtimeValueType - if is32bit { - inst = arm64.MOVW - vt = runtimeValueTypeI32 - } else { - inst = arm64.MOVD - vt = runtimeValueTypeI64 - } - - if value == 0 { - c.pushRuntimeValueLocationOnRegister(arm64.RegRZR, vt) - } else { - // Take a register to load the value. - reg, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - - c.assembler.CompileConstToRegister(inst, int64(value), reg) - - c.pushRuntimeValueLocationOnRegister(reg, vt) - } - return nil -} - -// compileConstF32 implements compiler.compileConstF32 for the arm64 architecture. -func (c *arm64Compiler) compileConstF32(o *wazeroir.UnionOperation) error { - return c.compileFloatConstant(true, o.U1 /*uint64(math.Float32bits(o.Value))*/) -} - -// compileConstF64 implements compiler.compileConstF64 for the arm64 architecture. -func (c *arm64Compiler) compileConstF64(o *wazeroir.UnionOperation) error { - return c.compileFloatConstant(false, o.U1 /*math.Float64bits(o.Value)*/) -} - -// compileFloatConstant adds instructions to load a float constant. -// is32bit is true if the target value is originally 32-bit const, false otherwise. -// value holds the (zero-extended for 32-bit case) bit representation of load target float constant. -func (c *arm64Compiler) compileFloatConstant(is32bit bool, value uint64) error { - if err := c.maybeCompileMoveTopConditionalToGeneralPurposeRegister(); err != nil { - return err - } - - // Take a register to load the value. - reg, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - - tmpReg := arm64.RegRZR - if value != 0 { - tmpReg = arm64ReservedRegisterForTemporary - var inst asm.Instruction - if is32bit { - inst = arm64.MOVW - } else { - inst = arm64.MOVD - } - c.assembler.CompileConstToRegister(inst, int64(value), tmpReg) - } - - // Use FMOV instruction to move the value on integer register into the float one. - var inst asm.Instruction - var vt runtimeValueType - if is32bit { - vt = runtimeValueTypeF32 - inst = arm64.FMOVS - } else { - vt = runtimeValueTypeF64 - inst = arm64.FMOVD - } - c.assembler.CompileRegisterToRegister(inst, tmpReg, reg) - - c.pushRuntimeValueLocationOnRegister(reg, vt) - return nil -} - -// compileMemoryInit implements compiler.compileMemoryInit for the arm64 architecture. -func (c *arm64Compiler) compileMemoryInit(o *wazeroir.UnionOperation) error { - dataIndex := uint32(o.U1) - return c.compileInitImpl(false, dataIndex, 0) -} - -// compileInitImpl implements compileTableInit and compileMemoryInit. -// -// TODO: the compiled code in this function should be reused and compile at once as -// the code is independent of any module. -func (c *arm64Compiler) compileInitImpl(isTable bool, index, tableIndex uint32) error { - outOfBoundsErrorStatus := nativeCallStatusCodeMemoryOutOfBounds - if isTable { - outOfBoundsErrorStatus = nativeCallStatusCodeInvalidTableAccess - } - - copySize, err := c.popValueOnRegister() - if err != nil { - return err - } - c.markRegisterUsed(copySize.register) - - sourceOffset, err := c.popValueOnRegister() - if err != nil { - return err - } - if isZeroRegister(sourceOffset.register) { - sourceOffset.register, err = c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - c.assembler.CompileRegisterToRegister(arm64.MOVD, arm64.RegRZR, sourceOffset.register) - } - c.markRegisterUsed(sourceOffset.register) - - destinationOffset, err := c.popValueOnRegister() - if err != nil { - return err - } - if isZeroRegister(destinationOffset.register) { - destinationOffset.register, err = c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - c.assembler.CompileRegisterToRegister(arm64.MOVD, arm64.RegRZR, destinationOffset.register) - } - c.markRegisterUsed(destinationOffset.register) - - tableInstanceAddressReg := asm.NilRegister - if isTable { - tableInstanceAddressReg, err = c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - c.markRegisterUsed(tableInstanceAddressReg) - } - - if !isZeroRegister(copySize.register) { - // sourceOffset += size. - c.assembler.CompileRegisterToRegister(arm64.ADD, copySize.register, sourceOffset.register) - // destinationOffset += size. - c.assembler.CompileRegisterToRegister(arm64.ADD, copySize.register, destinationOffset.register) - } - - instanceAddr, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - - if isTable { - c.compileLoadElemInstanceAddress(index, instanceAddr) - } else { - c.compileLoadDataInstanceAddress(index, instanceAddr) - } - - // Check data instance bounds. - c.assembler.CompileMemoryToRegister(arm64.LDRD, - instanceAddr, 8, // DataInstance and Element instance holds the length is stored at offset 8. - arm64ReservedRegisterForTemporary) - - c.assembler.CompileTwoRegistersToNone(arm64.CMP, arm64ReservedRegisterForTemporary, sourceOffset.register) - // If not, raise out of bounds memory access error. - c.compileMaybeExitFromNativeCode(arm64.BCONDLS, outOfBoundsErrorStatus) - - // Otherwise, ready to copy the value from destination to source. - // Check destination bounds. - if isTable { - // arm64ReservedRegisterForTemporary = &tables[0] - c.assembler.CompileMemoryToRegister(arm64.LDRD, - arm64ReservedRegisterForCallEngine, callEngineModuleContextTablesElement0AddressOffset, - arm64ReservedRegisterForTemporary) - // tableInstanceAddressReg = arm64ReservedRegisterForTemporary + tableIndex*8 - // = &tables[0] + sizeOf(*tableInstance)*8 - // = &tables[tableIndex] - c.assembler.CompileMemoryToRegister(arm64.LDRD, - arm64ReservedRegisterForTemporary, int64(tableIndex)*8, - tableInstanceAddressReg) - // arm64ReservedRegisterForTemporary = [tableInstanceAddressReg+tableInstanceTableLenOffset] = len(tables[tableIndex]) - c.assembler.CompileMemoryToRegister(arm64.LDRD, - tableInstanceAddressReg, tableInstanceTableLenOffset, - arm64ReservedRegisterForTemporary) - } else { - c.compileLoadMemoryBufferLen(arm64ReservedRegisterForTemporary) - } - - c.assembler.CompileTwoRegistersToNone(arm64.CMP, arm64ReservedRegisterForTemporary, destinationOffset.register) - // If not, raise out of bounds memory access error. - c.compileMaybeExitFromNativeCode(arm64.BCONDLS, outOfBoundsErrorStatus) - - // Otherwise, ready to copy the value from source to destination. - if !isZeroRegister(copySize.register) { - // If the size equals zero, we can skip the entire instructions beflow. - c.assembler.CompileTwoRegistersToNone(arm64.CMP, arm64.RegRZR, copySize.register) - skipCopyJump := c.assembler.CompileJump(arm64.BCONDEQ) - - var ldr, str asm.Instruction - var movSize int64 - if isTable { - ldr, str = arm64.LDRD, arm64.STRD - movSize = 8 - - // arm64ReservedRegisterForTemporary = &Table[0] - c.assembler.CompileMemoryToRegister(arm64.LDRD, tableInstanceAddressReg, - tableInstanceTableOffset, arm64ReservedRegisterForTemporary) - // destinationOffset = (destinationOffset<< pointerSizeLog2) + arm64ReservedRegisterForTemporary - c.assembler.CompileLeftShiftedRegisterToRegister(arm64.ADD, - destinationOffset.register, pointerSizeLog2, - arm64ReservedRegisterForTemporary, destinationOffset.register) - - // arm64ReservedRegisterForTemporary = &ElementInstance.References[0] - c.assembler.CompileMemoryToRegister(arm64.LDRD, instanceAddr, 0, arm64ReservedRegisterForTemporary) - // sourceOffset = (sourceOffset<< pointerSizeLog2) + arm64ReservedRegisterForTemporary - c.assembler.CompileLeftShiftedRegisterToRegister(arm64.ADD, - sourceOffset.register, pointerSizeLog2, - arm64ReservedRegisterForTemporary, sourceOffset.register) - - // copySize = copySize << pointerSizeLog2 - c.assembler.CompileConstToRegister(arm64.LSL, pointerSizeLog2, copySize.register) - } else { - ldr, str = arm64.LDRB, arm64.STRB - movSize = 1 - - // destinationOffset += memory buffer's absolute address. - c.assembler.CompileRegisterToRegister(arm64.ADD, arm64ReservedRegisterForMemory, destinationOffset.register) - - // sourceOffset += data buffer's absolute address. - c.assembler.CompileMemoryToRegister(arm64.LDRD, instanceAddr, 0, arm64ReservedRegisterForTemporary) - c.assembler.CompileRegisterToRegister(arm64.ADD, arm64ReservedRegisterForTemporary, sourceOffset.register) - - } - - // Negate the counter. - c.assembler.CompileRegisterToRegister(arm64.NEG, copySize.register, copySize.register) - - beginCopyLoop := c.assembler.CompileStandAlone(arm64.NOP) - - // arm64ReservedRegisterForTemporary = [sourceOffset + (size.register)] - c.assembler.CompileMemoryWithRegisterOffsetToRegister(ldr, - sourceOffset.register, copySize.register, - arm64ReservedRegisterForTemporary) - // [destinationOffset + (size.register)] = arm64ReservedRegisterForTemporary. - c.assembler.CompileRegisterToMemoryWithRegisterOffset(str, - arm64ReservedRegisterForTemporary, - destinationOffset.register, copySize.register, - ) - - // Decrement the size counter and if the value is still negative, continue the loop. - c.assembler.CompileConstToRegister(arm64.ADDS, movSize, copySize.register) - c.assembler.CompileJump(arm64.BCONDMI).AssignJumpTarget(beginCopyLoop) - - c.assembler.SetJumpTargetOnNext(skipCopyJump) - } - - c.markRegisterUnused(copySize.register, sourceOffset.register, - destinationOffset.register, instanceAddr, tableInstanceAddressReg) - return nil -} - -// compileDataDrop implements compiler.compileDataDrop for the arm64 architecture. -func (c *arm64Compiler) compileDataDrop(o *wazeroir.UnionOperation) error { - if err := c.maybeCompileMoveTopConditionalToGeneralPurposeRegister(); err != nil { - return err - } - - tmp, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - - dataIndex := uint32(o.U1) - c.compileLoadDataInstanceAddress(dataIndex, tmp) - - // Clears the content of DataInstance[o.DataIndex] (== []byte type). - c.assembler.CompileRegisterToMemory(arm64.STRD, arm64.RegRZR, tmp, 0) - c.assembler.CompileRegisterToMemory(arm64.STRD, arm64.RegRZR, tmp, 8) - c.assembler.CompileRegisterToMemory(arm64.STRD, arm64.RegRZR, tmp, 16) - return nil -} - -func (c *arm64Compiler) compileLoadDataInstanceAddress(dataIndex uint32, dst asm.Register) { - // dst = dataIndex * dataInstanceStructSize - c.assembler.CompileConstToRegister(arm64.MOVD, int64(dataIndex)*dataInstanceStructSize, dst) - - // arm64ReservedRegisterForTemporary = &moduleInstance.DataInstances[0] - c.assembler.CompileMemoryToRegister(arm64.LDRD, - arm64ReservedRegisterForCallEngine, callEngineModuleContextDataInstancesElement0AddressOffset, - arm64ReservedRegisterForTemporary, - ) - - // dst = arm64ReservedRegisterForTemporary + dst - // = &moduleInstance.DataInstances[0] + dataIndex*dataInstanceStructSize - // = &moduleInstance.DataInstances[dataIndex] - c.assembler.CompileRegisterToRegister(arm64.ADD, arm64ReservedRegisterForTemporary, dst) -} - -// compileMemoryCopy implements compiler.compileMemoryCopy for the arm64 architecture. -func (c *arm64Compiler) compileMemoryCopy() error { - return c.compileCopyImpl(false, 0, 0) -} - -// compileCopyImpl implements compileTableCopy and compileMemoryCopy. -// -// TODO: the compiled code in this function should be reused and compile at once as -// the code is independent of any module. -func (c *arm64Compiler) compileCopyImpl(isTable bool, srcTableIndex, dstTableIndex uint32) error { - outOfBoundsErrorStatus := nativeCallStatusCodeMemoryOutOfBounds - if isTable { - outOfBoundsErrorStatus = nativeCallStatusCodeInvalidTableAccess - } - - copySize, err := c.popValueOnRegister() - if err != nil { - return err - } - c.markRegisterUsed(copySize.register) - - sourceOffset, err := c.popValueOnRegister() - if err != nil { - return err - } - if isZeroRegister(sourceOffset.register) { - sourceOffset.register, err = c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - c.assembler.CompileRegisterToRegister(arm64.MOVD, arm64.RegRZR, sourceOffset.register) - } - c.markRegisterUsed(sourceOffset.register) - - destinationOffset, err := c.popValueOnRegister() - if err != nil { - return err - } - if isZeroRegister(destinationOffset.register) { - destinationOffset.register, err = c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - c.assembler.CompileRegisterToRegister(arm64.MOVD, arm64.RegRZR, destinationOffset.register) - } - c.markRegisterUsed(destinationOffset.register) - - if !isZeroRegister(copySize.register) { - // sourceOffset += size. - c.assembler.CompileRegisterToRegister(arm64.ADD, copySize.register, sourceOffset.register) - // destinationOffset += size. - c.assembler.CompileRegisterToRegister(arm64.ADD, copySize.register, destinationOffset.register) - } - - if isTable { - // arm64ReservedRegisterForTemporary = &tables[0] - c.assembler.CompileMemoryToRegister(arm64.LDRD, - arm64ReservedRegisterForCallEngine, callEngineModuleContextTablesElement0AddressOffset, - arm64ReservedRegisterForTemporary) - // arm64ReservedRegisterForTemporary = arm64ReservedRegisterForTemporary + srcTableIndex*8 - // = &tables[0] + sizeOf(*tableInstance)*8 - // = &tables[srcTableIndex] - c.assembler.CompileMemoryToRegister(arm64.LDRD, - arm64ReservedRegisterForTemporary, int64(srcTableIndex)*8, - arm64ReservedRegisterForTemporary) - // arm64ReservedRegisterForTemporary = [arm64ReservedRegisterForTemporary+tableInstanceTableLenOffset] = len(tables[srcTableIndex]) - c.assembler.CompileMemoryToRegister(arm64.LDRD, - arm64ReservedRegisterForTemporary, tableInstanceTableLenOffset, - arm64ReservedRegisterForTemporary) - } else { - // arm64ReservedRegisterForTemporary = len(memoryInst.Buffer). - c.compileLoadMemoryBufferLen(arm64ReservedRegisterForTemporary) - } - - // Check memory len >= sourceOffset. - c.assembler.CompileTwoRegistersToNone(arm64.CMP, arm64ReservedRegisterForTemporary, sourceOffset.register) - // If not, raise out of bounds memory access error. - c.compileMaybeExitFromNativeCode(arm64.BCONDLS, outOfBoundsErrorStatus) - - // Otherwise, check memory len >= destinationOffset. - if isTable { - // arm64ReservedRegisterForTemporary = &tables[0] - c.assembler.CompileMemoryToRegister(arm64.LDRD, - arm64ReservedRegisterForCallEngine, callEngineModuleContextTablesElement0AddressOffset, - arm64ReservedRegisterForTemporary) - // arm64ReservedRegisterForTemporary = arm64ReservedRegisterForTemporary + dstTableIndex*8 - // = &tables[0] + sizeOf(*tableInstance)*8 - // = &tables[dstTableIndex] - c.assembler.CompileMemoryToRegister(arm64.LDRD, - arm64ReservedRegisterForTemporary, int64(dstTableIndex)*8, - arm64ReservedRegisterForTemporary) - // arm64ReservedRegisterForTemporary = [arm64ReservedRegisterForTemporary+tableInstanceTableLenOffset] = len(tables[dstTableIndex]) - c.assembler.CompileMemoryToRegister(arm64.LDRD, - arm64ReservedRegisterForTemporary, tableInstanceTableLenOffset, - arm64ReservedRegisterForTemporary) - } - - c.assembler.CompileTwoRegistersToNone(arm64.CMP, arm64ReservedRegisterForTemporary, destinationOffset.register) - // If not, raise out of bounds memory access error. - c.compileMaybeExitFromNativeCode(arm64.BCONDLS, outOfBoundsErrorStatus) - - // Otherwise, ready to copy the value from source to destination. - var ldr, str asm.Instruction - var movSize int64 - if isTable { - ldr, str = arm64.LDRD, arm64.STRD - movSize = 8 - } else { - ldr, str = arm64.LDRB, arm64.STRB - movSize = 1 - } - - // If the size equals zero, we can skip the entire instructions beflow. - if !isZeroRegister(copySize.register) { - c.assembler.CompileTwoRegistersToNone(arm64.CMP, arm64.RegRZR, copySize.register) - skipCopyJump := c.assembler.CompileJump(arm64.BCONDEQ) - - // If source offet < destination offset: for (i = size-1; i >= 0; i--) dst[i] = src[i]; - c.assembler.CompileTwoRegistersToNone(arm64.CMP, sourceOffset.register, destinationOffset.register) - destLowerThanSourceJump := c.assembler.CompileJump(arm64.BCONDLS) - var endJump asm.Node - { - // sourceOffset -= size. - c.assembler.CompileRegisterToRegister(arm64.SUB, copySize.register, sourceOffset.register) - // destinationOffset -= size. - c.assembler.CompileRegisterToRegister(arm64.SUB, copySize.register, destinationOffset.register) - - if isTable { - // arm64ReservedRegisterForTemporary = &Tables[dstTableIndex].Table[0] - c.assembler.CompileMemoryToRegister(arm64.LDRD, arm64ReservedRegisterForCallEngine, - callEngineModuleContextTablesElement0AddressOffset, arm64ReservedRegisterForTemporary) - c.assembler.CompileMemoryToRegister(arm64.LDRD, - arm64ReservedRegisterForTemporary, int64(dstTableIndex)*8, - arm64ReservedRegisterForTemporary) - c.assembler.CompileMemoryToRegister(arm64.LDRD, - arm64ReservedRegisterForTemporary, tableInstanceTableOffset, - arm64ReservedRegisterForTemporary) - // destinationOffset = (destinationOffset<< pointerSizeLog2) + &Table[dstTableIndex].Table[0] - c.assembler.CompileLeftShiftedRegisterToRegister(arm64.ADD, - destinationOffset.register, pointerSizeLog2, - arm64ReservedRegisterForTemporary, destinationOffset.register) - - // arm64ReservedRegisterForTemporary = &Tables[srcTableIndex] - c.assembler.CompileMemoryToRegister(arm64.LDRD, arm64ReservedRegisterForCallEngine, - callEngineModuleContextTablesElement0AddressOffset, arm64ReservedRegisterForTemporary) - c.assembler.CompileMemoryToRegister(arm64.LDRD, - arm64ReservedRegisterForTemporary, int64(srcTableIndex)*8, - arm64ReservedRegisterForTemporary) - c.assembler.CompileMemoryToRegister(arm64.LDRD, - arm64ReservedRegisterForTemporary, tableInstanceTableOffset, - arm64ReservedRegisterForTemporary) - // sourceOffset = (sourceOffset<< 3) + &Table[0] - c.assembler.CompileLeftShiftedRegisterToRegister(arm64.ADD, - sourceOffset.register, pointerSizeLog2, - arm64ReservedRegisterForTemporary, sourceOffset.register) - - // copySize = copySize << pointerSizeLog2 as each element has 8 bytes and we copy one by one. - c.assembler.CompileConstToRegister(arm64.LSL, pointerSizeLog2, copySize.register) - } else { - // sourceOffset += memory buffer's absolute address. - c.assembler.CompileRegisterToRegister(arm64.ADD, arm64ReservedRegisterForMemory, sourceOffset.register) - // destinationOffset += memory buffer's absolute address. - c.assembler.CompileRegisterToRegister(arm64.ADD, arm64ReservedRegisterForMemory, destinationOffset.register) - } - - beginCopyLoop := c.assembler.CompileStandAlone(arm64.NOP) - - // size -= 1 - c.assembler.CompileConstToRegister(arm64.SUBS, movSize, copySize.register) - - // arm64ReservedRegisterForTemporary = [sourceOffset + (size.register)] - c.assembler.CompileMemoryWithRegisterOffsetToRegister(ldr, - sourceOffset.register, copySize.register, - arm64ReservedRegisterForTemporary) - // [destinationOffset + (size.register)] = arm64ReservedRegisterForTemporary. - c.assembler.CompileRegisterToMemoryWithRegisterOffset(str, - arm64ReservedRegisterForTemporary, - destinationOffset.register, copySize.register, - ) - - // If the value on the copySize.register is not equal zero, continue the loop. - c.assembler.CompileJump(arm64.BCONDNE).AssignJumpTarget(beginCopyLoop) - - // Otherwise, exit the loop. - endJump = c.assembler.CompileJump(arm64.B) - } - - // Else (destination offet < source offset): for (i = 0; i < size; i++) dst[counter-1-i] = src[counter-1-i]; - c.assembler.SetJumpTargetOnNext(destLowerThanSourceJump) - { - - if isTable { - // arm64ReservedRegisterForTemporary = &Tables[dstTableIndex].Table[0] - c.assembler.CompileMemoryToRegister(arm64.LDRD, arm64ReservedRegisterForCallEngine, - callEngineModuleContextTablesElement0AddressOffset, arm64ReservedRegisterForTemporary) - c.assembler.CompileMemoryToRegister(arm64.LDRD, - arm64ReservedRegisterForTemporary, int64(dstTableIndex)*8, - arm64ReservedRegisterForTemporary) - c.assembler.CompileMemoryToRegister(arm64.LDRD, - arm64ReservedRegisterForTemporary, tableInstanceTableOffset, - arm64ReservedRegisterForTemporary) - // destinationOffset = (destinationOffset<< interfaceDataySizeLog2) + &Table[dstTableIndex].Table[0] - c.assembler.CompileLeftShiftedRegisterToRegister(arm64.ADD, - destinationOffset.register, pointerSizeLog2, - arm64ReservedRegisterForTemporary, destinationOffset.register) - - // arm64ReservedRegisterForTemporary = &Tables[srcTableIndex] - c.assembler.CompileMemoryToRegister(arm64.LDRD, arm64ReservedRegisterForCallEngine, - callEngineModuleContextTablesElement0AddressOffset, arm64ReservedRegisterForTemporary) - c.assembler.CompileMemoryToRegister(arm64.LDRD, - arm64ReservedRegisterForTemporary, int64(srcTableIndex)*8, - arm64ReservedRegisterForTemporary) - c.assembler.CompileMemoryToRegister(arm64.LDRD, - arm64ReservedRegisterForTemporary, tableInstanceTableOffset, - arm64ReservedRegisterForTemporary) - // sourceOffset = (sourceOffset<< 3) + &Table[0] - c.assembler.CompileLeftShiftedRegisterToRegister(arm64.ADD, - sourceOffset.register, pointerSizeLog2, - arm64ReservedRegisterForTemporary, sourceOffset.register) - - // copySize = copySize << pointerSizeLog2 as each element has 8 bytes and we copy one by one. - c.assembler.CompileConstToRegister(arm64.LSL, pointerSizeLog2, copySize.register) - } else { - // sourceOffset += memory buffer's absolute address. - c.assembler.CompileRegisterToRegister(arm64.ADD, arm64ReservedRegisterForMemory, sourceOffset.register) - // destinationOffset += memory buffer's absolute address. - c.assembler.CompileRegisterToRegister(arm64.ADD, arm64ReservedRegisterForMemory, destinationOffset.register) - } - - // Negate the counter. - c.assembler.CompileRegisterToRegister(arm64.NEG, copySize.register, copySize.register) - - beginCopyLoop := c.assembler.CompileStandAlone(arm64.NOP) - - // arm64ReservedRegisterForTemporary = [sourceOffset + (size.register)] - c.assembler.CompileMemoryWithRegisterOffsetToRegister(ldr, - sourceOffset.register, copySize.register, - arm64ReservedRegisterForTemporary) - // [destinationOffset + (size.register)] = arm64ReservedRegisterForTemporary. - c.assembler.CompileRegisterToMemoryWithRegisterOffset(str, - arm64ReservedRegisterForTemporary, - destinationOffset.register, copySize.register, - ) - - // size += 1 - c.assembler.CompileConstToRegister(arm64.ADDS, movSize, copySize.register) - c.assembler.CompileJump(arm64.BCONDMI).AssignJumpTarget(beginCopyLoop) - } - c.assembler.SetJumpTargetOnNext(skipCopyJump) - c.assembler.SetJumpTargetOnNext(endJump) - } - - // Mark all of the operand registers. - c.markRegisterUnused(copySize.register, sourceOffset.register, destinationOffset.register) - - return nil -} - -// compileMemoryFill implements compiler.compileMemoryCopy for the arm64 architecture. -func (c *arm64Compiler) compileMemoryFill() error { - return c.compileFillImpl(false, 0) -} - -// compileFillImpl implements TableFill and MemoryFill. -// -// TODO: the compiled code in this function should be reused and compile at once as -// the code is independent of any module. -func (c *arm64Compiler) compileFillImpl(isTable bool, tableIndex uint32) error { - outOfBoundsErrorStatus := nativeCallStatusCodeMemoryOutOfBounds - if isTable { - outOfBoundsErrorStatus = nativeCallStatusCodeInvalidTableAccess - } - - fillSize, err := c.popValueOnRegister() - if err != nil { - return err - } - c.markRegisterUsed(fillSize.register) - - value, err := c.popValueOnRegister() - if err != nil { - return err - } - c.markRegisterUsed(value.register) - - destinationOffset, err := c.popValueOnRegister() - if err != nil { - return err - } - if isZeroRegister(destinationOffset.register) { - destinationOffset.register, err = c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - c.assembler.CompileRegisterToRegister(arm64.MOVD, arm64.RegRZR, destinationOffset.register) - } - c.markRegisterUsed(destinationOffset.register) - - // destinationOffset += size. - c.assembler.CompileRegisterToRegister(arm64.ADD, fillSize.register, destinationOffset.register) - - if isTable { - // arm64ReservedRegisterForTemporary = &tables[0] - c.assembler.CompileMemoryToRegister(arm64.LDRD, - arm64ReservedRegisterForCallEngine, callEngineModuleContextTablesElement0AddressOffset, - arm64ReservedRegisterForTemporary) - // arm64ReservedRegisterForTemporary = arm64ReservedRegisterForTemporary + srcTableIndex*8 - // = &tables[0] + sizeOf(*tableInstance)*8 - // = &tables[srcTableIndex] - c.assembler.CompileMemoryToRegister(arm64.LDRD, - arm64ReservedRegisterForTemporary, int64(tableIndex)*8, - arm64ReservedRegisterForTemporary) - // arm64ReservedRegisterForTemporary = [arm64ReservedRegisterForTemporary+tableInstanceTableLenOffset] = len(tables[srcTableIndex]) - c.assembler.CompileMemoryToRegister(arm64.LDRD, - arm64ReservedRegisterForTemporary, tableInstanceTableLenOffset, - arm64ReservedRegisterForTemporary) - } else { - // arm64ReservedRegisterForTemporary = len(memoryInst.Buffer). - c.compileLoadMemoryBufferLen(arm64ReservedRegisterForTemporary) - } - - // Check len >= destinationOffset. - c.assembler.CompileTwoRegistersToNone(arm64.CMP, arm64ReservedRegisterForTemporary, destinationOffset.register) - - // If not, raise the runtime error. - c.compileMaybeExitFromNativeCode(arm64.BCONDLS, outOfBoundsErrorStatus) - - // Otherwise, ready to copy the value from destination to source. - // If the size equals zero, we can skip the entire instructions below. - c.assembler.CompileTwoRegistersToNone(arm64.CMP, arm64.RegRZR, fillSize.register) - skipCopyJump := c.assembler.CompileJump(arm64.BCONDEQ) - - // destinationOffset -= size. - c.assembler.CompileRegisterToRegister(arm64.SUB, fillSize.register, destinationOffset.register) - - var str asm.Instruction - var movSize int64 - if isTable { - str = arm64.STRD - movSize = 8 - - // arm64ReservedRegisterForTemporary = &Tables[dstTableIndex].Table[0] - c.assembler.CompileMemoryToRegister(arm64.LDRD, arm64ReservedRegisterForCallEngine, - callEngineModuleContextTablesElement0AddressOffset, arm64ReservedRegisterForTemporary) - c.assembler.CompileMemoryToRegister(arm64.LDRD, - arm64ReservedRegisterForTemporary, int64(tableIndex)*8, - arm64ReservedRegisterForTemporary) - c.assembler.CompileMemoryToRegister(arm64.LDRD, - arm64ReservedRegisterForTemporary, tableInstanceTableOffset, - arm64ReservedRegisterForTemporary) - // destinationOffset = (destinationOffset<< pointerSizeLog2) + &Table[dstTableIndex].Table[0] - c.assembler.CompileLeftShiftedRegisterToRegister(arm64.ADD, - destinationOffset.register, pointerSizeLog2, - arm64ReservedRegisterForTemporary, destinationOffset.register) - - // copySize = copySize << pointerSizeLog2 as each element has 8 bytes and we copy one by one. - c.assembler.CompileConstToRegister(arm64.LSL, pointerSizeLog2, fillSize.register) - } else { - str = arm64.STRB - movSize = 1 - - // destinationOffset += memory buffer's absolute address. - c.assembler.CompileRegisterToRegister(arm64.ADD, arm64ReservedRegisterForMemory, destinationOffset.register) - } - - // Naively implement the copy with "for loop" by copying byte one by one. - beginCopyLoop := c.assembler.CompileStandAlone(arm64.NOP) - - // size -= 1 - c.assembler.CompileConstToRegister(arm64.SUBS, movSize, fillSize.register) - - // [destinationOffset + (size.register)] = arm64ReservedRegisterForTemporary. - c.assembler.CompileRegisterToMemoryWithRegisterOffset(str, - value.register, - destinationOffset.register, fillSize.register, - ) - - // If the value on the copySizeRgister.register is not equal zero, continue the loop. - continueJump := c.assembler.CompileJump(arm64.BCONDNE) - continueJump.AssignJumpTarget(beginCopyLoop) - - // Mark all of the operand registers. - c.markRegisterUnused(fillSize.register, value.register, destinationOffset.register) - - c.assembler.SetJumpTargetOnNext(skipCopyJump) - return nil -} - -// compileTableInit implements compiler.compileTableInit for the arm64 architecture. -func (c *arm64Compiler) compileTableInit(o *wazeroir.UnionOperation) error { - elemIndex := uint32(o.U1) - tableIndex := uint32(o.U2) - return c.compileInitImpl(true, elemIndex, tableIndex) -} - -// compileTableCopy implements compiler.compileTableCopy for the arm64 architecture. -func (c *arm64Compiler) compileTableCopy(o *wazeroir.UnionOperation) error { - return c.compileCopyImpl(true, uint32(o.U1), uint32(o.U2)) -} - -// compileElemDrop implements compiler.compileElemDrop for the arm64 architecture. -func (c *arm64Compiler) compileElemDrop(o *wazeroir.UnionOperation) error { - if err := c.maybeCompileMoveTopConditionalToGeneralPurposeRegister(); err != nil { - return err - } - - tmp, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - - elemIndex := uint32(o.U1) - c.compileLoadElemInstanceAddress(elemIndex, tmp) - - // Clears the content of ElementInstances[o.ElemIndex] (== []interface{} type). - c.assembler.CompileRegisterToMemory(arm64.STRD, arm64.RegRZR, tmp, 0) - c.assembler.CompileRegisterToMemory(arm64.STRD, arm64.RegRZR, tmp, 8) - c.assembler.CompileRegisterToMemory(arm64.STRD, arm64.RegRZR, tmp, 16) - return nil -} - -func (c *arm64Compiler) compileLoadElemInstanceAddress(elemIndex uint32, dst asm.Register) { - // dst = dataIndex * elementInstanceStructSize - c.assembler.CompileConstToRegister(arm64.MOVD, int64(elemIndex)*elementInstanceStructSize, dst) - - // arm64ReservedRegisterForTemporary = &moduleInstance.ElementInstances[0] - c.assembler.CompileMemoryToRegister(arm64.LDRD, - arm64ReservedRegisterForCallEngine, callEngineModuleContextElementInstancesElement0AddressOffset, - arm64ReservedRegisterForTemporary, - ) - - // dst = arm64ReservedRegisterForTemporary + dst - // = &moduleInstance.ElementInstances[0] + elemIndex*elementInstanceStructSize - // = &moduleInstance.ElementInstances[elemIndex] - c.assembler.CompileRegisterToRegister(arm64.ADD, arm64ReservedRegisterForTemporary, dst) -} - -// compileRefFunc implements compiler.compileRefFunc for the arm64 architecture. -func (c *arm64Compiler) compileRefFunc(o *wazeroir.UnionOperation) error { - if err := c.maybeCompileMoveTopConditionalToGeneralPurposeRegister(); err != nil { - return err - } - - ref, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - // arm64ReservedRegisterForTemporary = [arm64ReservedRegisterForCallEngine + callEngineModuleContextFunctionsElement0AddressOffset] - // = &moduleEngine.functions[0] - c.assembler.CompileMemoryToRegister(arm64.LDRD, - arm64ReservedRegisterForCallEngine, callEngineModuleContextFunctionsElement0AddressOffset, - ref) - - // ref = ref + int64(o.FunctionIndex)*sizeOf(function) - // = &moduleEngine.functions[index] - functionIndex := int64(o.U1) - c.assembler.CompileConstToRegister(arm64.ADD, - functionIndex*functionSize, - ref, - ) - - c.pushRuntimeValueLocationOnRegister(ref, runtimeValueTypeI64) - return nil -} - -// compileTableGet implements compiler.compileTableGet for the arm64 architecture. -func (c *arm64Compiler) compileTableGet(o *wazeroir.UnionOperation) error { - ref, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - c.markRegisterUsed(ref) - - offset, err := c.popValueOnRegister() - if err != nil { - return err - } - - // arm64ReservedRegisterForTemporary = &tables[0] - c.assembler.CompileMemoryToRegister(arm64.LDRD, - arm64ReservedRegisterForCallEngine, callEngineModuleContextTablesElement0AddressOffset, - arm64ReservedRegisterForTemporary) - // arm64ReservedRegisterForTemporary = [arm64ReservedRegisterForTemporary + TableIndex*8] - // = [&tables[0] + TableIndex*sizeOf(*tableInstance)] - // = [&tables[TableIndex]] = tables[TableIndex]. - tableIndex := int64(o.U1) - c.assembler.CompileMemoryToRegister(arm64.LDRD, - arm64ReservedRegisterForTemporary, tableIndex*8, - arm64ReservedRegisterForTemporary) - - // Out of bounds check. - // ref = [&tables[TableIndex] + tableInstanceTableLenOffset] = len(tables[TableIndex]) - c.assembler.CompileMemoryToRegister(arm64.LDRD, - arm64ReservedRegisterForTemporary, tableInstanceTableLenOffset, - ref, - ) - // "cmp ref, offset" - c.assembler.CompileTwoRegistersToNone(arm64.CMP, ref, offset.register) - - // If it exceeds len(table), we exit the execution. - c.compileMaybeExitFromNativeCode(arm64.BCONDLO, nativeCallStatusCodeInvalidTableAccess) - - // ref = [&tables[TableIndex] + tableInstanceTableOffset] = &tables[TableIndex].References[0] - c.assembler.CompileMemoryToRegister(arm64.LDRD, - arm64ReservedRegisterForTemporary, tableInstanceTableOffset, - ref, - ) - - // ref = (offset << pointerSizeLog2) + ref - // = &tables[TableIndex].References[0] + sizeOf(uintptr) * offset - // = &tables[TableIndex].References[offset] - c.assembler.CompileLeftShiftedRegisterToRegister(arm64.ADD, - offset.register, pointerSizeLog2, ref, ref) - - // ref = [&tables[TableIndex]] = load the Reference's pointer as uint64. - c.assembler.CompileMemoryToRegister(arm64.LDRD, ref, 0, ref) - - c.pushRuntimeValueLocationOnRegister(ref, runtimeValueTypeI64) // table elements are opaque 64-bit at runtime. - return nil -} - -// compileTableSet implements compiler.compileTableSet for the arm64 architecture. -func (c *arm64Compiler) compileTableSet(o *wazeroir.UnionOperation) error { - ref := c.locationStack.pop() - if err := c.compileEnsureOnRegister(ref); err != nil { - return err - } - - offset := c.locationStack.pop() - if err := c.compileEnsureOnRegister(offset); err != nil { - return err - } - - tmp, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - - // arm64ReservedRegisterForTemporary = &tables[0] - c.assembler.CompileMemoryToRegister(arm64.LDRD, - arm64ReservedRegisterForCallEngine, callEngineModuleContextTablesElement0AddressOffset, - arm64ReservedRegisterForTemporary) - // arm64ReservedRegisterForTemporary = arm64ReservedRegisterForTemporary + TableIndex*8 - // = &tables[0] + TableIndex*sizeOf(*tableInstance) - // = &tables[TableIndex] - tableIndex := int64(o.U1) - c.assembler.CompileMemoryToRegister(arm64.LDRD, - arm64ReservedRegisterForTemporary, tableIndex*8, - arm64ReservedRegisterForTemporary) - - // Out of bounds check. - // tmp = [&tables[TableIndex] + tableInstanceTableLenOffset] = len(tables[TableIndex]) - c.assembler.CompileMemoryToRegister(arm64.LDRD, - arm64ReservedRegisterForTemporary, tableInstanceTableLenOffset, - tmp, - ) - // "cmp tmp, offset" - c.assembler.CompileTwoRegistersToNone(arm64.CMP, tmp, offset.register) - - // If it exceeds len(table), we exit the execution. - c.compileMaybeExitFromNativeCode(arm64.BCONDLO, nativeCallStatusCodeInvalidTableAccess) - - // tmp = [&tables[TableIndex] + tableInstanceTableOffset] = &tables[TableIndex].References[0] - c.assembler.CompileMemoryToRegister(arm64.LDRD, - arm64ReservedRegisterForTemporary, tableInstanceTableOffset, - tmp, - ) - - // tmp = (offset << pointerSizeLog2) + tmp - // = &tables[TableIndex].References[0] + sizeOf(uintptr) * offset - // = &tables[TableIndex].References[offset] - c.assembler.CompileLeftShiftedRegisterToRegister(arm64.ADD, offset.register, pointerSizeLog2, tmp, tmp) - - // Set the reference's raw pointer. - c.assembler.CompileRegisterToMemory(arm64.STRD, ref.register, tmp, 0) - - c.markRegisterUnused(offset.register, ref.register, tmp) - return nil -} - -// compileTableGrow implements compiler.compileTableGrow for the arm64 architecture. -func (c *arm64Compiler) compileTableGrow(o *wazeroir.UnionOperation) error { - if err := c.maybeCompileMoveTopConditionalToGeneralPurposeRegister(); err != nil { - return err - } - - // Pushes the table index. - tableIndex := o.U1 - if err := c.compileIntConstant(true, tableIndex); err != nil { - return err - } - - // Table grow cannot be done in assembly just like memory grow as it involves with allocation in Go. - // Therefore, call out to the built function for this purpose. - if err := c.compileCallGoFunction(nativeCallStatusCodeCallBuiltInFunction, builtinFunctionIndexTableGrow); err != nil { - return err - } - - // TableGrow consumes three values (table index, number of items, initial value). - for i := 0; i < 3; i++ { - c.locationStack.pop() - } - - // Then, the previous length was pushed as the result. - v := c.locationStack.pushRuntimeValueLocationOnStack() - v.valueType = runtimeValueTypeI32 - - // After return, we re-initialize reserved registers just like preamble of functions. - c.compileReservedStackBasePointerRegisterInitialization() - c.compileReservedMemoryRegisterInitialization() - return nil -} - -// compileTableSize implements compiler.compileTableSize for the arm64 architecture. -func (c *arm64Compiler) compileTableSize(o *wazeroir.UnionOperation) error { - if err := c.maybeCompileMoveTopConditionalToGeneralPurposeRegister(); err != nil { - return err - } - result, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - c.markRegisterUsed(result) - - // arm64ReservedRegisterForTemporary = &tables[0] - c.assembler.CompileMemoryToRegister(arm64.LDRD, - arm64ReservedRegisterForCallEngine, callEngineModuleContextTablesElement0AddressOffset, - arm64ReservedRegisterForTemporary) - // arm64ReservedRegisterForTemporary = [arm64ReservedRegisterForTemporary + TableIndex*8] - // = [&tables[0] + TableIndex*sizeOf(*tableInstance)] - // = [&tables[TableIndex]] = tables[TableIndex]. - tableIndex := int64(o.U1) - c.assembler.CompileMemoryToRegister(arm64.LDRD, - arm64ReservedRegisterForTemporary, tableIndex*8, - arm64ReservedRegisterForTemporary) - - // result = [&tables[TableIndex] + tableInstanceTableLenOffset] = len(tables[TableIndex]) - c.assembler.CompileMemoryToRegister(arm64.LDRD, - arm64ReservedRegisterForTemporary, tableInstanceTableLenOffset, - result, - ) - - c.pushRuntimeValueLocationOnRegister(result, runtimeValueTypeI32) - return nil -} - -// compileTableFill implements compiler.compileTableFill for the arm64 architecture. -func (c *arm64Compiler) compileTableFill(o *wazeroir.UnionOperation) error { - tableIndex := uint32(o.U1) - return c.compileFillImpl(true, tableIndex) -} - -// popTwoValuesOnRegisters pops two values from the location stacks, ensures -// these two values are located on registers, and mark them unused. -// -// TODO: we’d usually prefix this with compileXXX as this might end up emitting instructions, -// but the name seems awkward. -func (c *arm64Compiler) popTwoValuesOnRegisters() (x1, x2 *runtimeValueLocation, err error) { - x2 = c.locationStack.pop() - if err = c.compileEnsureOnRegister(x2); err != nil { - return - } - - x1 = c.locationStack.pop() - if err = c.compileEnsureOnRegister(x1); err != nil { - return - } - - c.markRegisterUnused(x2.register) - c.markRegisterUnused(x1.register) - return -} - -// popValueOnRegister pops one value from the location stack, ensures -// that it is located on a register, and mark it unused. -// -// TODO: we’d usually prefix this with compileXXX as this might end up emitting instructions, -// but the name seems awkward. -func (c *arm64Compiler) popValueOnRegister() (v *runtimeValueLocation, err error) { - v = c.locationStack.pop() - if err = c.compileEnsureOnRegister(v); err != nil { - return - } - - c.markRegisterUnused(v.register) - return -} - -// compileEnsureOnRegister emits instructions to ensure that a value is located on a register. -func (c *arm64Compiler) compileEnsureOnRegister(loc *runtimeValueLocation) (err error) { - if loc.onStack() { - reg, err := c.allocateRegister(loc.getRegisterType()) - if err != nil { - return err - } - - // Record that the value holds the register and the register is marked used. - loc.setRegister(reg) - c.markRegisterUsed(reg) - - c.compileLoadValueOnStackToRegister(loc) - } else if loc.onConditionalRegister() { - err = c.compileLoadConditionalRegisterToGeneralPurposeRegister(loc) - } - return -} - -// maybeCompileMoveTopConditionalToGeneralPurposeRegister moves the top value on the stack -// if the value is located on a conditional register. -// -// This is usually called at the beginning of methods on compiler interface where we possibly -// compile instructions without saving the conditional register value. -// compile* functions without calling this function is saving the conditional -// value to the stack or register by invoking ensureOnGeneralPurposeRegister for the top. -func (c *arm64Compiler) maybeCompileMoveTopConditionalToGeneralPurposeRegister() (err error) { - if c.locationStack.sp > 0 { - if loc := c.locationStack.peek(); loc.onConditionalRegister() { - err = c.compileLoadConditionalRegisterToGeneralPurposeRegister(loc) - } - } - return -} - -// loadConditionalRegisterToGeneralPurposeRegister saves the conditional register value -// to a general purpose register. -func (c *arm64Compiler) compileLoadConditionalRegisterToGeneralPurposeRegister(loc *runtimeValueLocation) error { - reg, err := c.allocateRegister(loc.getRegisterType()) - if err != nil { - return err - } - - c.markRegisterUsed(reg) - c.assembler.CompileConditionalRegisterSet(loc.conditionalRegister, reg) - - // Record that now the value is located on a general purpose register. - loc.setRegister(reg) - return nil -} - -// compileLoadValueOnStackToRegister implements compiler.compileLoadValueOnStackToRegister for arm64. -func (c *arm64Compiler) compileLoadValueOnStackToRegister(loc *runtimeValueLocation) { - switch loc.valueType { - case runtimeValueTypeI32: - c.assembler.CompileMemoryToRegister(arm64.LDRW, arm64ReservedRegisterForStackBasePointerAddress, - int64(loc.stackPointer)*8, loc.register) - case runtimeValueTypeI64: - c.assembler.CompileMemoryToRegister(arm64.LDRD, arm64ReservedRegisterForStackBasePointerAddress, - int64(loc.stackPointer)*8, loc.register) - case runtimeValueTypeF32: - c.assembler.CompileMemoryToRegister(arm64.FLDRS, arm64ReservedRegisterForStackBasePointerAddress, - int64(loc.stackPointer)*8, loc.register) - case runtimeValueTypeF64: - c.assembler.CompileMemoryToRegister(arm64.FLDRD, arm64ReservedRegisterForStackBasePointerAddress, - int64(loc.stackPointer)*8, loc.register) - case runtimeValueTypeV128Lo: - c.assembler.CompileMemoryToVectorRegister(arm64.VMOV, - arm64ReservedRegisterForStackBasePointerAddress, int64(loc.stackPointer)*8, loc.register, - arm64.VectorArrangementQ) - // Higher 64-bits are loaded as well ^^. - hi := &c.locationStack.stack[loc.stackPointer+1] - hi.setRegister(loc.register) - case runtimeValueTypeV128Hi: - panic("BUG: V128Hi must be be loaded to a register along with V128Lo") - } -} - -// allocateRegister implements compiler.allocateRegister for arm64. -func (c *arm64Compiler) allocateRegister(t registerType) (reg asm.Register, err error) { - var ok bool - // Try to get the unused register. - reg, ok = c.locationStack.takeFreeRegister(t) - if ok { - return - } - - // If not found, we have to steal the register. - stealTarget, ok := c.locationStack.takeStealTargetFromUsedRegister(t) - if !ok { - err = fmt.Errorf("cannot steal register") - return - } - - // Release the steal target register value onto stack location. - reg = stealTarget.register - c.compileReleaseRegisterToStack(stealTarget) - return -} - -func (c *arm64Compiler) compileLoadMemoryBufferLen(destReg asm.Register) { - if c.ir.Memory != wazeroir.MemoryTypeShared { - // No concurrent accesses so the length we cached during the preamble is still valid. - c.assembler.CompileMemoryToRegister(arm64.LDRD, - arm64ReservedRegisterForCallEngine, callEngineModuleContextMemorySliceLenOffset, - destReg) - return - } - // destReg = ce.moduleContext.MemoryInstance (pointer) - c.assembler.CompileMemoryToRegister(arm64.LDRD, arm64ReservedRegisterForCallEngine, callEngineModuleContextMemoryInstanceOffset, destReg) - // destReg = len(mem.Buffer) - c.assembler.CompileConstToRegister(arm64.ADD, memoryInstanceBufferLenOffset, destReg) - c.assembler.CompileMemoryWithRegisterSourceToRegister(arm64.LDARD, destReg, destReg) -} - -// compileReleaseAllRegistersToStack adds instructions to store all the values located on -// either general purpose or conditional registers onto the memory stack. -// See releaseRegisterToStack. -func (c *arm64Compiler) compileReleaseAllRegistersToStack() (err error) { - for i := uint64(0); i < c.locationStack.sp; i++ { - if loc := &c.locationStack.stack[i]; loc.onRegister() { - c.compileReleaseRegisterToStack(loc) - } else if loc.onConditionalRegister() { - if err = c.compileLoadConditionalRegisterToGeneralPurposeRegister(loc); err != nil { - return - } - c.compileReleaseRegisterToStack(loc) - } - } - return -} - -// releaseRegisterToStack adds an instruction to write the value on a register back to memory stack region. -func (c *arm64Compiler) compileReleaseRegisterToStack(loc *runtimeValueLocation) { - switch loc.valueType { - case runtimeValueTypeI32: - c.assembler.CompileRegisterToMemory(arm64.STRW, loc.register, arm64ReservedRegisterForStackBasePointerAddress, int64(loc.stackPointer)*8) - case runtimeValueTypeI64: - c.assembler.CompileRegisterToMemory(arm64.STRD, loc.register, arm64ReservedRegisterForStackBasePointerAddress, int64(loc.stackPointer)*8) - case runtimeValueTypeF32: - c.assembler.CompileRegisterToMemory(arm64.FSTRS, loc.register, arm64ReservedRegisterForStackBasePointerAddress, int64(loc.stackPointer)*8) - case runtimeValueTypeF64: - c.assembler.CompileRegisterToMemory(arm64.FSTRD, loc.register, arm64ReservedRegisterForStackBasePointerAddress, int64(loc.stackPointer)*8) - case runtimeValueTypeV128Lo: - c.assembler.CompileVectorRegisterToMemory(arm64.VMOV, - loc.register, arm64ReservedRegisterForStackBasePointerAddress, int64(loc.stackPointer)*8, - arm64.VectorArrangementQ) - // Higher 64-bits are released as well ^^. - hi := &c.locationStack.stack[loc.stackPointer+1] - c.locationStack.releaseRegister(hi) - case runtimeValueTypeV128Hi: - panic("BUG: V128Hi must be released to the stack along with V128Lo") - default: - panic("BUG") - } - - // Mark the register is free. - c.locationStack.releaseRegister(loc) -} - -// compileReservedStackBasePointerRegisterInitialization adds instructions to initialize arm64ReservedRegisterForStackBasePointerAddress -// so that it points to the absolute address of the stack base for this function. -func (c *arm64Compiler) compileReservedStackBasePointerRegisterInitialization() { - // First, load the address of the first element in the value stack into arm64ReservedRegisterForStackBasePointerAddress temporarily. - c.assembler.CompileMemoryToRegister(arm64.LDRD, - arm64ReservedRegisterForCallEngine, callEngineStackContextStackElement0AddressOffset, - arm64ReservedRegisterForStackBasePointerAddress) - - // next we move the base pointer (ce.stackBasePointer) to arm64ReservedRegisterForTemporary. - c.assembler.CompileMemoryToRegister(arm64.LDRD, - arm64ReservedRegisterForCallEngine, callEngineStackContextStackBasePointerInBytesOffset, - arm64ReservedRegisterForTemporary) - - // Finally, we calculate "callEngineStackContextStackBasePointerInBytesOffset + arm64ReservedRegisterForTemporary" - c.assembler.CompileRegisterToRegister(arm64.ADD, arm64ReservedRegisterForTemporary, arm64ReservedRegisterForStackBasePointerAddress) -} - -func (c *arm64Compiler) compileReservedMemoryRegisterInitialization() { - if c.ir.Memory != wazeroir.MemoryTypeNone || c.ir.UsesMemory { - // "arm64ReservedRegisterForMemory = ce.MemoryElement0Address" - c.assembler.CompileMemoryToRegister( - arm64.LDRD, - arm64ReservedRegisterForCallEngine, callEngineModuleContextMemoryElement0AddressOffset, - arm64ReservedRegisterForMemory, - ) - } -} - -// compileModuleContextInitialization adds instructions to initialize ce.moduleContext's fields based on -// ce.moduleContext.ModuleInstanceAddress. -// This is called in two cases: in function preamble, and on the return from (non-Go) function calls. -func (c *arm64Compiler) compileModuleContextInitialization() error { - tmpX, found := c.locationStack.takeFreeRegister(registerTypeGeneralPurpose) - if !found { - panic("BUG: all the registers should be free at this point") - } - c.markRegisterUsed(tmpX) - tmpY, found := c.locationStack.takeFreeRegister(registerTypeGeneralPurpose) - if !found { - panic("BUG: all the registers should be free at this point") - } - c.markRegisterUsed(tmpY) - - // "tmpX = ce.ModuleInstanceAddress" - c.assembler.CompileMemoryToRegister(arm64.LDRD, arm64ReservedRegisterForCallEngine, callEngineModuleContextModuleInstanceOffset, tmpX) - - // If the module instance address stays the same, we could skip the entire code below. - c.assembler.CompileTwoRegistersToNone(arm64.CMP, arm64CallingConventionModuleInstanceAddressRegister, tmpX) - brIfModuleUnchanged := c.assembler.CompileJump(arm64.BCONDEQ) - - // Otherwise, update the moduleEngine.moduleContext.ModuleInstanceAddress. - c.assembler.CompileRegisterToMemory(arm64.STRD, - arm64CallingConventionModuleInstanceAddressRegister, - arm64ReservedRegisterForCallEngine, callEngineModuleContextModuleInstanceOffset, - ) - - // Also, we have to update the following fields: - // * callEngine.moduleContext.globalElement0Address - // * callEngine.moduleContext.memoryElement0Address - // * callEngine.moduleContext.memorySliceLen - // * callEngine.moduleContext.memoryInstance - // * callEngine.moduleContext.tableElement0Address - // * callEngine.moduleContext.tableSliceLen - // * callEngine.moduleContext.functionsElement0Address - // * callEngine.moduleContext.typeIDsElement0Address - // * callEngine.moduleContext.dataInstancesElement0Address - // * callEngine.moduleContext.elementInstancesElement0Address - - // Update globalElement0Address. - // - // Note: if there's global.get or set instruction in the function, the existence of the globals - // is ensured by function validation at module instantiation phase, and that's why it is ok to - // skip the initialization if the module's globals slice is empty. - if len(c.ir.Globals) > 0 { - // "tmpX = &moduleInstance.Globals[0]" - c.assembler.CompileMemoryToRegister(arm64.LDRD, - arm64CallingConventionModuleInstanceAddressRegister, moduleInstanceGlobalsOffset, - tmpX, - ) - - // "ce.GlobalElement0Address = tmpX (== &moduleInstance.Globals[0])" - c.assembler.CompileRegisterToMemory( - arm64.STRD, tmpX, - arm64ReservedRegisterForCallEngine, callEngineModuleContextGlobalElement0AddressOffset, - ) - } - - // Update memoryElement0Address and memorySliceLen. - // - // Note: if there's memory instruction in the function, memory instance must be non-nil. - // That is ensured by function validation at module instantiation phase, and that's - // why it is ok to skip the initialization if the module's memory instance is nil. - if c.ir.Memory != wazeroir.MemoryTypeNone { - // "tmpX = moduleInstance.Memory" - c.assembler.CompileMemoryToRegister( - arm64.LDRD, - arm64CallingConventionModuleInstanceAddressRegister, moduleInstanceMemoryOffset, - tmpX, - ) - - // First, set ce.memoryInstance - c.assembler.CompileRegisterToMemory( - arm64.STRD, - tmpX, - arm64ReservedRegisterForCallEngine, callEngineModuleContextMemoryInstanceOffset, - ) - - // Next, we write the memory length into ce.MemorySliceLen. - // - // "tmpY = [tmpX + memoryInstanceBufferLenOffset] (== len(memory.Buffer))" - c.assembler.CompileMemoryToRegister( - arm64.LDRD, - tmpX, memoryInstanceBufferLenOffset, - tmpY, - ) - // "ce.MemorySliceLen = tmpY". - c.assembler.CompileRegisterToMemory( - arm64.STRD, - tmpY, - arm64ReservedRegisterForCallEngine, callEngineModuleContextMemorySliceLenOffset, - ) - - // Finally, we write ce.memoryElement0Address. - // - // "tmpY = *tmpX (== &memory.Buffer[0])" - c.assembler.CompileMemoryToRegister( - arm64.LDRD, - tmpX, memoryInstanceBufferOffset, - tmpY, - ) - // "ce.memoryElement0Address = tmpY". - c.assembler.CompileRegisterToMemory( - arm64.STRD, - tmpY, - arm64ReservedRegisterForCallEngine, callEngineModuleContextMemoryElement0AddressOffset, - ) - } - - // Update tableElement0Address, tableSliceLen and typeIDsElement0Address. - // - // Note: if there's table instruction in the function, the existence of the table - // is ensured by function validation at module instantiation phase, and that's - // why it is ok to skip the initialization if the module's table doesn't exist. - if c.ir.HasTable { - // "tmpX = &tables[0] (type of **wasm.Table)" - c.assembler.CompileMemoryToRegister( - arm64.LDRD, - arm64CallingConventionModuleInstanceAddressRegister, moduleInstanceTablesOffset, - tmpX, - ) - - // Update ce.tableElement0Address. - // "ce.tableElement0Address = tmpX". - c.assembler.CompileRegisterToMemory( - arm64.STRD, - tmpX, - arm64ReservedRegisterForCallEngine, callEngineModuleContextTablesElement0AddressOffset, - ) - - // Finally, we put &ModuleInstance.TypeIDs[0] into moduleContext.typeIDsElement0Address. - c.assembler.CompileMemoryToRegister(arm64.LDRD, - arm64CallingConventionModuleInstanceAddressRegister, moduleInstanceTypeIDsOffset, tmpX) - c.assembler.CompileRegisterToMemory(arm64.STRD, - tmpX, arm64ReservedRegisterForCallEngine, callEngineModuleContextTypeIDsElement0AddressOffset) - } - - // Update callEngine.moduleContext.functionsElement0Address - { - // "tmpX = [moduleInstanceAddressRegister + moduleInstanceEngineOffset + interfaceDataOffset] (== *moduleEngine)" - // - // Go's interface is laid out on memory as two quad words as struct {tab, data uintptr} - // where tab points to the interface table, and the latter points to the actual - // implementation of interface. This case, we extract "data" pointer as *moduleEngine. - // See the following references for detail: - // * https://research.swtch.com/interfaces - // * https://github.com/golang/go/blob/release-branch.go1.20/src/runtime/runtime2.go#L207-L210 - c.assembler.CompileMemoryToRegister( - arm64.LDRD, - arm64CallingConventionModuleInstanceAddressRegister, moduleInstanceEngineOffset+interfaceDataOffset, - tmpX, - ) - - // "tmpY = [tmpX + moduleEngineFunctionsOffset] (== &moduleEngine.functions[0])" - c.assembler.CompileMemoryToRegister( - arm64.LDRD, - tmpX, moduleEngineFunctionsOffset, - tmpY, - ) - - // "callEngine.moduleContext.functionsElement0Address = tmpY". - c.assembler.CompileRegisterToMemory( - arm64.STRD, - tmpY, - arm64ReservedRegisterForCallEngine, callEngineModuleContextFunctionsElement0AddressOffset, - ) - } - - // Update dataInstancesElement0Address. - if c.ir.HasDataInstances { - // "tmpX = &moduleInstance.DataInstances[0]" - c.assembler.CompileMemoryToRegister( - arm64.LDRD, - arm64CallingConventionModuleInstanceAddressRegister, moduleInstanceDataInstancesOffset, - tmpX, - ) - // "callEngine.moduleContext.dataInstancesElement0Address = tmpX". - c.assembler.CompileRegisterToMemory( - arm64.STRD, - tmpX, - arm64ReservedRegisterForCallEngine, callEngineModuleContextDataInstancesElement0AddressOffset, - ) - } - - // Update callEngine.moduleContext.elementInstancesElement0Address - if c.ir.HasElementInstances { - // "tmpX = &moduleInstance.DataInstances[0]" - c.assembler.CompileMemoryToRegister( - arm64.LDRD, - arm64CallingConventionModuleInstanceAddressRegister, moduleInstanceElementInstancesOffset, - tmpX, - ) - // "callEngine.moduleContext.dataInstancesElement0Address = tmpX". - c.assembler.CompileRegisterToMemory( - arm64.STRD, - tmpX, - arm64ReservedRegisterForCallEngine, callEngineModuleContextElementInstancesElement0AddressOffset, - ) - } - - c.assembler.SetJumpTargetOnNext(brIfModuleUnchanged) - c.markRegisterUnused(tmpX, tmpY) - return nil -} diff --git a/internal/engine/compiler/impl_arm64_test.go b/internal/engine/compiler/impl_arm64_test.go deleted file mode 100644 index da59b58f59..0000000000 --- a/internal/engine/compiler/impl_arm64_test.go +++ /dev/null @@ -1,293 +0,0 @@ -package compiler - -import ( - "testing" - "unsafe" - - "github.com/tetratelabs/wazero/internal/asm" - arm64 "github.com/tetratelabs/wazero/internal/asm/arm64" - "github.com/tetratelabs/wazero/internal/testing/require" - "github.com/tetratelabs/wazero/internal/wasm" - "github.com/tetratelabs/wazero/internal/wazeroir" -) - -// TestArm64Compiler_indirectCallWithTargetOnCallingConvReg is the regression test for #526. -// In short, the offset register for call_indirect might be the same as arm64CallingConventionModuleInstanceAddressRegister -// and that must not be a failure. -func TestArm64Compiler_indirectCallWithTargetOnCallingConvReg(t *testing.T) { - env := newCompilerEnvironment() - table := make([]wasm.Reference, 1) - env.addTable(&wasm.TableInstance{References: table}) - // Ensure that the module instance has the type information for targetOperation.TypeIndex, - // and the typeID matches the table[targetOffset]'s type ID. - operation := operationPtr(wazeroir.NewOperationCallIndirect(0, 0)) - env.module().TypeIDs = []wasm.FunctionTypeID{0} - env.module().Engine = &moduleEngine{functions: []function{}} - - me := env.moduleEngine() - { // Compiling call target. - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, nil) - err := compiler.compilePreamble() - require.NoError(t, err) - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - - executable := code.Bytes() - makeExecutable(executable) - - f := function{ - parent: &compiledFunction{parent: &compiledCode{executable: code}}, - codeInitialAddress: code.Addr(), - moduleInstance: env.moduleInstance, - } - me.functions = append(me.functions, f) - table[0] = uintptr(unsafe.Pointer(&f)) - } - - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, &wazeroir.CompilationResult{ - Types: []wasm.FunctionType{{}}, - HasTable: true, - }).(*arm64Compiler) - err := compiler.compilePreamble() - require.NoError(t, err) - - // Place the offset into the calling-convention reserved register. - offsetLoc := compiler.pushRuntimeValueLocationOnRegister(arm64CallingConventionModuleInstanceAddressRegister, - runtimeValueTypeI32) - compiler.assembler.CompileConstToRegister(arm64.MOVD, 0, offsetLoc.register) - - require.NoError(t, compiler.compileCallIndirect(operation)) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate the code under test and run. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) -} - -func TestArm64Compiler_readInstructionAddress(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newArm64Compiler, nil).(*arm64Compiler) - - err := compiler.compilePreamble() - require.NoError(t, err) - - // Set the acquisition target instruction to the one after RET, - // and read the absolute address into destinationRegister. - const addressReg = arm64ReservedRegisterForTemporary - compiler.assembler.CompileReadInstructionAddress(addressReg, arm64.RET) - - // Branch to the instruction after RET below via the absolute - // address stored in destinationRegister. - compiler.assembler.CompileJumpToRegister(arm64.B, addressReg) - - // If we fail to branch, we reach here and exit with unreachable status, - // so the assertion would fail. - compiler.compileExitFromNativeCode(nativeCallStatusCodeUnreachable) - - // This could be the read instruction target as this is the - // right after RET. Therefore, the branch instruction above - // must target here. - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - require.Equal(t, nativeCallStatusCodeReturned, env.compilerStatus()) -} - -func TestArm64Compiler_label(t *testing.T) { - c := &arm64Compiler{} - c.label(wazeroir.NewLabel(wazeroir.LabelKindContinuation, 100)) - require.Equal(t, 100, c.frameIDMax) - require.Equal(t, 101, len(c.labels[wazeroir.LabelKindContinuation])) - - // frameIDMax is for all LabelKind, so this shouldn't change frameIDMax. - c.label(wazeroir.NewLabel(wazeroir.LabelKindHeader, 2)) - require.Equal(t, 100, c.frameIDMax) - require.Equal(t, 3, len(c.labels[wazeroir.LabelKindHeader])) -} - -func TestArm64Compiler_Init(t *testing.T) { - c := &arm64Compiler{ - locationStackForEntrypoint: newRuntimeValueLocationStack(), - assembler: arm64.NewAssembler(0), - } - const stackCap = 12345 - c.locationStackForEntrypoint.stack = make([]runtimeValueLocation, stackCap) - c.locationStackForEntrypoint.sp = 5555 - - c.Init(&wasm.FunctionType{}, nil, false) - - // locationStack is the pointer to locationStackForEntrypoint after init. - require.Equal(t, c.locationStack, &c.locationStackForEntrypoint) - // And the underlying stack must be reused (the capacity preserved). - require.Equal(t, stackCap, cap(c.locationStack.stack)) - require.Equal(t, stackCap, cap(c.locationStackForEntrypoint.stack)) -} - -func TestArm64Compiler_resetLabels(t *testing.T) { - c := newArm64Compiler().(*arm64Compiler) - nop := c.compileNOP() - - const ( - frameIDMax = 50 - capacity = 12345 - ) - c.frameIDMax = frameIDMax - for i := range c.labels { - ifs := make([]arm64LabelInfo, frameIDMax*2) - c.labels[i] = ifs - for j := 0; j <= frameIDMax; j++ { - ifs[j].stackInitialized = true - ifs[j].initialInstruction = nop - ifs[j].initialStack = newRuntimeValueLocationStack() - ifs[j].initialStack.sp = 5555 // should be cleared via runtimeLocationStack.Reset(). - ifs[j].initialStack.stack = make([]runtimeValueLocation, 0, capacity) - } - } - c.resetLabels() - for i := range c.labels { - for j := 0; j < len(c.labels[i]); j++ { - l := &c.labels[i][j] - require.False(t, l.stackInitialized) - require.Nil(t, l.initialInstruction) - require.Equal(t, 0, len(l.initialStack.stack)) - if j > frameIDMax { - require.Equal(t, 0, cap(l.initialStack.stack)) - } else { - require.Equal(t, capacity, cap(l.initialStack.stack)) - } - require.Equal(t, uint64(0), l.initialStack.sp) - } - } -} - -func TestArm64Compiler_getSavedTemporaryLocationStack(t *testing.T) { - t.Run("len(brTableTmp)len(current)", func(t *testing.T) { - const temporarySliceSize = 100 - st := newRuntimeValueLocationStack() - c := &arm64Compiler{locationStack: &st, brTableTmp: make([]runtimeValueLocation, temporarySliceSize)} - - c.locationStack.sp = 3 - c.locationStack.stack = []runtimeValueLocation{ - {stackPointer: 150}, - {stackPointer: 200}, - {stackPointer: 300}, - {}, - {}, - {}, - {}, - {stackPointer: 1231455}, // Entries here shouldn't be copied as they are avobe sp. - } - - actual := c.getSavedTemporaryLocationStack() - require.Equal(t, uint64(3), actual.sp) - require.Equal(t, temporarySliceSize, len(actual.stack)) - require.Equal(t, c.locationStack.stack[:3], actual.stack[:3]) - for i := int(actual.sp); i < len(actual.stack); i++ { - // Above the stack pointer, the values must not be copied. - require.Zero(t, actual.stack[i].stackPointer) - } - }) -} - -// https://github.com/tetratelabs/wazero/issues/1522 -func TestArm64Compiler_LargeTrapOffsets(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, &wazeroir.CompilationResult{ - Types: []wasm.FunctionType{{}}, - }) - err := compiler.compilePreamble() - require.NoError(t, err) - - one := operationPtr(wazeroir.NewOperationConstI32(uint32(1))) - five := operationPtr(wazeroir.NewOperationConstI32(uint32(5))) - div := operationPtr(wazeroir.NewOperationDiv(wazeroir.SignedTypeInt32)) - - // Place the offset value. - err = compiler.compileConstI32(one) - require.NoError(t, err) - - // Repeat enough times that jump labels are not within (-524288, 524287). - // Relative offset -2097164/4(=-524291). - // At the time of writing, 52429 is empirically the value that starts - // triggering the bug on arm64. We impose an arbitrarily higher value - // to account for possible future improvement to the number of instructions - // we emit. - for i := 0; i < 80_000; i++ { - err = compiler.compileConstI32(five) - require.NoError(t, err) - - err = compiler.compileDiv(div) - require.NoError(t, err) - } - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate the code under test and run. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - - env.exec(code.Bytes()) - - require.Equal(t, nativeCallStatusCodeReturned.String(), env.compilerStatus().String()) -} - -// compile implements compilerImpl.setStackPointerCeil for the amd64 architecture. -func (c *arm64Compiler) setStackPointerCeil(v uint64) { - c.stackPointerCeil = v -} - -// compile implements compilerImpl.setRuntimeValueLocationStack for the amd64 architecture. -func (c *arm64Compiler) setRuntimeValueLocationStack(s *runtimeValueLocationStack) { - c.locationStack = s -} diff --git a/internal/engine/compiler/impl_threads_amd64.go b/internal/engine/compiler/impl_threads_amd64.go deleted file mode 100644 index 35049469d1..0000000000 --- a/internal/engine/compiler/impl_threads_amd64.go +++ /dev/null @@ -1,659 +0,0 @@ -package compiler - -import ( - "github.com/tetratelabs/wazero/internal/asm" - "github.com/tetratelabs/wazero/internal/asm/amd64" - "github.com/tetratelabs/wazero/internal/wasm" - "github.com/tetratelabs/wazero/internal/wazeroir" -) - -func (c *amd64Compiler) compileAtomicLoad(o *wazeroir.UnionOperation) error { - var ( - inst asm.Instruction - targetSizeInBytes int64 - vt runtimeValueType - ) - - unsignedType := wazeroir.UnsignedType(o.B1) - offset := uint32(o.U2) - - switch unsignedType { - case wazeroir.UnsignedTypeI32: - inst = amd64.MOVL - targetSizeInBytes = 32 / 8 - vt = runtimeValueTypeI32 - case wazeroir.UnsignedTypeI64: - inst = amd64.MOVQ - targetSizeInBytes = 64 / 8 - vt = runtimeValueTypeI64 - } - - return c.compileAtomicLoadImpl(inst, offset, targetSizeInBytes, vt) -} - -func (c *amd64Compiler) compileAtomicLoad8(o *wazeroir.UnionOperation) error { - var ( - inst asm.Instruction - vt runtimeValueType - ) - - unsignedType := wazeroir.UnsignedType(o.B1) - offset := uint32(o.U2) - - switch unsignedType { - case wazeroir.UnsignedTypeI32: - inst = amd64.MOVBLZX - vt = runtimeValueTypeI32 - case wazeroir.UnsignedTypeI64: - inst = amd64.MOVBQZX - vt = runtimeValueTypeI64 - } - - return c.compileAtomicLoadImpl(inst, offset, 1, vt) -} - -func (c *amd64Compiler) compileAtomicLoad16(o *wazeroir.UnionOperation) error { - var ( - inst asm.Instruction - vt runtimeValueType - ) - - unsignedType := wazeroir.UnsignedType(o.B1) - offset := uint32(o.U2) - - switch unsignedType { - case wazeroir.UnsignedTypeI32: - inst = amd64.MOVWLZX - vt = runtimeValueTypeI32 - case wazeroir.UnsignedTypeI64: - inst = amd64.MOVWQZX - vt = runtimeValueTypeI64 - } - - return c.compileAtomicLoadImpl(inst, offset, 16/8, vt) -} - -func (c *amd64Compiler) compileAtomicLoadImpl( - inst asm.Instruction, offset uint32, targetSizeInBytes int64, resultRuntimeValueType runtimeValueType, -) error { - reg, err := c.compileMemoryAccessCeilSetup(offset, targetSizeInBytes) - if err != nil { - return err - } - - c.compileMemoryAlignmentCheck(reg, targetSizeInBytes) - - c.assembler.CompileMemoryWithIndexToRegister(inst, - // we access memory as memory.Buffer[ceil-targetSizeInBytes: ceil]. - amd64ReservedRegisterForMemory, -targetSizeInBytes, reg, 1, - reg) - c.pushRuntimeValueLocationOnRegister(reg, resultRuntimeValueType) - - return nil -} - -func (c *amd64Compiler) compileAtomicStore(o *wazeroir.UnionOperation) error { - var inst asm.Instruction - var targetSizeInByte int64 - unsignedType := wazeroir.UnsignedType(o.B1) - offset := uint32(o.U2) - switch unsignedType { - case wazeroir.UnsignedTypeI32: - inst = amd64.XCHGL - targetSizeInByte = 32 / 8 - case wazeroir.UnsignedTypeI64: - inst = amd64.XCHGQ - targetSizeInByte = 64 / 8 - } - return c.compileAtomicStoreImpl(inst, offset, targetSizeInByte) -} - -func (c *amd64Compiler) compileAtomicStore8(o *wazeroir.UnionOperation) error { - return c.compileAtomicStoreImpl(amd64.XCHGB, uint32(o.U2), 1) -} - -func (c *amd64Compiler) compileAtomicStore16(o *wazeroir.UnionOperation) error { - return c.compileAtomicStoreImpl(amd64.XCHGW, uint32(o.U2), 16/8) -} - -func (c *amd64Compiler) compileAtomicStoreImpl( - inst asm.Instruction, offset uint32, targetSizeInBytes int64, -) error { - val := c.locationStack.pop() - if err := c.compileEnsureOnRegister(val); err != nil { - return err - } - - reg, err := c.compileMemoryAccessCeilSetup(offset, targetSizeInBytes) - if err != nil { - return err - } - - c.compileMemoryAlignmentCheck(reg, targetSizeInBytes) - - c.assembler.CompileRegisterToMemoryWithIndex( - inst, val.register, - amd64ReservedRegisterForMemory, -targetSizeInBytes, reg, 1, - ) - - // We no longer need both the value and base registers. - c.locationStack.releaseRegister(val) - c.locationStack.markRegisterUnused(reg) - return nil -} - -func (c *amd64Compiler) compileAtomicRMW(o *wazeroir.UnionOperation) error { - var ( - inst asm.Instruction - targetSizeInBytes int64 - vt runtimeValueType - ) - - unsignedType := wazeroir.UnsignedType(o.B1) - op := wazeroir.AtomicArithmeticOp(o.B2) - offset := uint32(o.U2) - - switch unsignedType { - case wazeroir.UnsignedTypeI32: - targetSizeInBytes = 32 / 8 - vt = runtimeValueTypeI32 - switch op { - case wazeroir.AtomicArithmeticOpAdd: - return c.compileAtomicAddImpl(amd64.XADDL, offset, false, targetSizeInBytes, vt) - case wazeroir.AtomicArithmeticOpSub: - return c.compileAtomicAddImpl(amd64.XADDL, offset, true, targetSizeInBytes, vt) - case wazeroir.AtomicArithmeticOpAnd: - inst = amd64.ANDL - case wazeroir.AtomicArithmeticOpOr: - inst = amd64.ORL - case wazeroir.AtomicArithmeticOpXor: - inst = amd64.XORL - case wazeroir.AtomicArithmeticOpNop: - return c.compileAtomicXchgImpl(amd64.XCHGL, offset, targetSizeInBytes, vt) - } - case wazeroir.UnsignedTypeI64: - targetSizeInBytes = 64 / 8 - vt = runtimeValueTypeI64 - switch op { - case wazeroir.AtomicArithmeticOpAdd: - return c.compileAtomicAddImpl(amd64.XADDQ, offset, false, targetSizeInBytes, vt) - case wazeroir.AtomicArithmeticOpSub: - return c.compileAtomicAddImpl(amd64.XADDQ, offset, true, targetSizeInBytes, vt) - case wazeroir.AtomicArithmeticOpAnd: - inst = amd64.ANDQ - case wazeroir.AtomicArithmeticOpOr: - inst = amd64.ORQ - case wazeroir.AtomicArithmeticOpXor: - inst = amd64.XORQ - case wazeroir.AtomicArithmeticOpNop: - return c.compileAtomicXchgImpl(amd64.XCHGQ, offset, targetSizeInBytes, vt) - } - } - - return c.compileAtomicRMWCASLoopImpl(inst, offset, targetSizeInBytes, vt) -} - -func (c *amd64Compiler) compileAtomicRMW8(o *wazeroir.UnionOperation) error { - var ( - inst asm.Instruction - vt runtimeValueType - ) - - unsignedType := wazeroir.UnsignedType(o.B1) - op := wazeroir.AtomicArithmeticOp(o.B2) - offset := uint32(o.U2) - - switch unsignedType { - case wazeroir.UnsignedTypeI32: - vt = runtimeValueTypeI32 - case wazeroir.UnsignedTypeI64: - vt = runtimeValueTypeI64 - } - - switch op { - case wazeroir.AtomicArithmeticOpAdd: - return c.compileAtomicAddImpl(amd64.XADDB, offset, false, 1, vt) - case wazeroir.AtomicArithmeticOpSub: - return c.compileAtomicAddImpl(amd64.XADDB, offset, true, 1, vt) - case wazeroir.AtomicArithmeticOpAnd: - inst = amd64.ANDL - case wazeroir.AtomicArithmeticOpOr: - inst = amd64.ORL - case wazeroir.AtomicArithmeticOpXor: - inst = amd64.XORL - case wazeroir.AtomicArithmeticOpNop: - return c.compileAtomicXchgImpl(amd64.XCHGB, offset, 1, vt) - } - - return c.compileAtomicRMWCASLoopImpl(inst, offset, 1, vt) -} - -func (c *amd64Compiler) compileAtomicRMW16(o *wazeroir.UnionOperation) error { - var ( - inst asm.Instruction - vt runtimeValueType - ) - - unsignedType := wazeroir.UnsignedType(o.B1) - op := wazeroir.AtomicArithmeticOp(o.B2) - offset := uint32(o.U2) - - switch unsignedType { - case wazeroir.UnsignedTypeI32: - vt = runtimeValueTypeI32 - case wazeroir.UnsignedTypeI64: - vt = runtimeValueTypeI64 - } - - switch op { - case wazeroir.AtomicArithmeticOpAdd: - return c.compileAtomicAddImpl(amd64.XADDW, offset, false, 16/8, vt) - case wazeroir.AtomicArithmeticOpSub: - return c.compileAtomicAddImpl(amd64.XADDW, offset, true, 16/8, vt) - case wazeroir.AtomicArithmeticOpAnd: - inst = amd64.ANDL - case wazeroir.AtomicArithmeticOpOr: - inst = amd64.ORL - case wazeroir.AtomicArithmeticOpXor: - inst = amd64.XORL - case wazeroir.AtomicArithmeticOpNop: - return c.compileAtomicXchgImpl(amd64.XCHGW, offset, 16/8, vt) - } - - return c.compileAtomicRMWCASLoopImpl(inst, offset, 16/8, vt) -} - -func (c *amd64Compiler) compileAtomicAddImpl(inst asm.Instruction, offsetConst uint32, negateArg bool, targetSizeInBytes int64, resultRuntimeValueType runtimeValueType) error { - val := c.locationStack.pop() - if err := c.compileEnsureOnRegister(val); err != nil { - return err - } - - if negateArg { - var negArg asm.Instruction - switch targetSizeInBytes { - case 1: - negArg = amd64.NEGB - case 2: - negArg = amd64.NEGW - case 4: - negArg = amd64.NEGL - case 8: - negArg = amd64.NEGQ - } - c.assembler.CompileNoneToRegister(negArg, val.register) - } - - reg, err := c.compileMemoryAccessCeilSetup(offsetConst, targetSizeInBytes) - if err != nil { - return err - } - - c.compileMemoryAlignmentCheck(reg, targetSizeInBytes) - - c.assembler.CompileRegisterToMemoryWithIndexAndLock( - inst, val.register, - amd64ReservedRegisterForMemory, -targetSizeInBytes, reg, 1, - ) - - if targetSizeInBytes < 4 { - mask := (1 << (8 * targetSizeInBytes)) - 1 - c.assembler.CompileConstToRegister(amd64.ANDQ, int64(mask), val.register) - } - - c.locationStack.markRegisterUnused(reg) - c.locationStack.pushRuntimeValueLocationOnRegister(val.register, resultRuntimeValueType) - - return nil -} - -func (c *amd64Compiler) compileAtomicXchgImpl(inst asm.Instruction, offsetConst uint32, targetSizeInBytes int64, resultRuntimeValueType runtimeValueType) error { - val := c.locationStack.pop() - if err := c.compileEnsureOnRegister(val); err != nil { - return err - } - - reg, err := c.compileMemoryAccessCeilSetup(offsetConst, targetSizeInBytes) - if err != nil { - return err - } - - c.compileMemoryAlignmentCheck(reg, targetSizeInBytes) - - c.assembler.CompileRegisterToMemoryWithIndex( - inst, val.register, - amd64ReservedRegisterForMemory, -targetSizeInBytes, reg, 1, - ) - - if targetSizeInBytes < 4 { - mask := (1 << (8 * targetSizeInBytes)) - 1 - c.assembler.CompileConstToRegister(amd64.ANDQ, int64(mask), val.register) - } - - c.locationStack.markRegisterUnused(reg) - c.locationStack.pushRuntimeValueLocationOnRegister(val.register, resultRuntimeValueType) - - return nil -} - -func (c *amd64Compiler) compileAtomicRMWCASLoopImpl(rmwInst asm.Instruction, - offsetConst uint32, targetSizeInBytes int64, resultRuntimeValueType runtimeValueType, -) error { - const resultRegister = amd64.RegAX - - var copyInst asm.Instruction - var loadInst asm.Instruction - var cmpXchgInst asm.Instruction - - switch targetSizeInBytes { - case 8: - copyInst = amd64.MOVQ - loadInst = amd64.MOVQ - cmpXchgInst = amd64.CMPXCHGQ - case 4: - copyInst = amd64.MOVL - loadInst = amd64.MOVL - cmpXchgInst = amd64.CMPXCHGL - case 2: - copyInst = amd64.MOVL - loadInst = amd64.MOVWLZX - cmpXchgInst = amd64.CMPXCHGW - case 1: - copyInst = amd64.MOVL - loadInst = amd64.MOVBLZX - cmpXchgInst = amd64.CMPXCHGB - } - - c.onValueReleaseRegisterToStack(resultRegister) - c.locationStack.markRegisterUsed(resultRegister) - - tmp, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - c.locationStack.markRegisterUsed(tmp) - - val := c.locationStack.pop() - if err := c.compileEnsureOnRegister(val); err != nil { - return err - } - - reg, err := c.compileMemoryAccessCeilSetup(offsetConst, targetSizeInBytes) - if err != nil { - return err - } - - c.compileMemoryAlignmentCheck(reg, targetSizeInBytes) - - if targetSizeInBytes < 32 { - mask := (1 << (8 * targetSizeInBytes)) - 1 - c.assembler.CompileConstToRegister(amd64.ANDQ, int64(mask), val.register) - } - - beginLoop := c.assembler.CompileStandAlone(amd64.NOP) - c.assembler.CompileRegisterToRegister(copyInst, val.register, tmp) - c.assembler.CompileMemoryWithIndexToRegister( - loadInst, amd64ReservedRegisterForMemory, -targetSizeInBytes, reg, 1, resultRegister) - if targetSizeInBytes < 32 { - mask := (1 << (8 * targetSizeInBytes)) - 1 - c.assembler.CompileConstToRegister(amd64.ANDQ, int64(mask), resultRegister) - } - c.assembler.CompileRegisterToRegister(rmwInst, resultRegister, tmp) - c.assembler.CompileRegisterToMemoryWithIndexAndLock( - cmpXchgInst, tmp, - amd64ReservedRegisterForMemory, -targetSizeInBytes, reg, 1, - ) - c.assembler.CompileJump(amd64.JNE).AssignJumpTarget(beginLoop) - - if targetSizeInBytes < 32 { - mask := (1 << (8 * targetSizeInBytes)) - 1 - c.assembler.CompileConstToRegister(amd64.ANDQ, int64(mask), resultRegister) - } - - c.locationStack.markRegisterUnused(reg) - c.locationStack.markRegisterUnused(tmp) - c.locationStack.markRegisterUnused(val.register) - c.locationStack.pushRuntimeValueLocationOnRegister(resultRegister, resultRuntimeValueType) - - return nil -} - -func (c *amd64Compiler) compileAtomicRMWCmpxchg(o *wazeroir.UnionOperation) error { - var ( - casInst asm.Instruction - targetSizeInBytes int64 - vt runtimeValueType - ) - - unsignedType := wazeroir.UnsignedType(o.B1) - offset := uint32(o.U2) - - switch unsignedType { - case wazeroir.UnsignedTypeI32: - casInst = amd64.CMPXCHGL - targetSizeInBytes = 32 / 8 - vt = runtimeValueTypeI32 - case wazeroir.UnsignedTypeI64: - casInst = amd64.CMPXCHGQ - targetSizeInBytes = 64 / 8 - vt = runtimeValueTypeI64 - } - return c.compileAtomicRMWCmpxchgImpl(casInst, offset, targetSizeInBytes, vt) -} - -func (c *amd64Compiler) compileAtomicRMW8Cmpxchg(o *wazeroir.UnionOperation) error { - var vt runtimeValueType - - unsignedType := wazeroir.UnsignedType(o.B1) - offset := uint32(o.U2) - - switch unsignedType { - case wazeroir.UnsignedTypeI32: - vt = runtimeValueTypeI32 - case wazeroir.UnsignedTypeI64: - vt = runtimeValueTypeI64 - } - return c.compileAtomicRMWCmpxchgImpl(amd64.CMPXCHGB, offset, 1, vt) -} - -func (c *amd64Compiler) compileAtomicRMW16Cmpxchg(o *wazeroir.UnionOperation) error { - var vt runtimeValueType - - unsignedType := wazeroir.UnsignedType(o.B1) - offset := uint32(o.U2) - - switch unsignedType { - case wazeroir.UnsignedTypeI32: - vt = runtimeValueTypeI32 - case wazeroir.UnsignedTypeI64: - vt = runtimeValueTypeI64 - } - return c.compileAtomicRMWCmpxchgImpl(amd64.CMPXCHGW, offset, 16/8, vt) -} - -func (c *amd64Compiler) compileAtomicRMWCmpxchgImpl(inst asm.Instruction, offsetArg uint32, targetSizeInBytes int64, resultRuntimeValueType runtimeValueType) error { - const resultRegister = amd64.RegAX - - repl := c.locationStack.pop() - exp := c.locationStack.pop() - - // expected value must be in accumulator register, which will also hold the loaded result. - if exp.register != resultRegister { - c.onValueReleaseRegisterToStack(resultRegister) - if exp.onConditionalRegister() { - c.compileMoveConditionalToGeneralPurposeRegister(exp, resultRegister) - } else if exp.onStack() { - exp.setRegister(resultRegister) - c.compileLoadValueOnStackToRegister(exp) - c.locationStack.markRegisterUnused(resultRegister) - } else { - c.assembler.CompileRegisterToRegister(amd64.MOVQ, exp.register, resultRegister) - c.locationStack.releaseRegister(exp) - exp.setRegister(resultRegister) - c.locationStack.markRegisterUsed(resultRegister) - } - } - - if err := c.compileEnsureOnRegister(repl); err != nil { - return err - } - - reg, err := c.compileMemoryAccessCeilSetup(offsetArg, targetSizeInBytes) - if err != nil { - return err - } - - c.compileMemoryAlignmentCheck(reg, targetSizeInBytes) - - c.assembler.CompileRegisterToMemoryWithIndexAndLock( - inst, repl.register, - amd64ReservedRegisterForMemory, -targetSizeInBytes, reg, 1, - ) - - if targetSizeInBytes < 4 { - mask := (1 << (8 * targetSizeInBytes)) - 1 - c.assembler.CompileConstToRegister(amd64.ANDQ, int64(mask), resultRegister) - } - - c.locationStack.markRegisterUnused(reg) - c.locationStack.markRegisterUnused(repl.register) - c.locationStack.pushRuntimeValueLocationOnRegister(resultRegister, resultRuntimeValueType) - - return nil -} - -func (c *amd64Compiler) compileAtomicMemoryWait(o *wazeroir.UnionOperation) error { - if err := c.maybeCompileMoveTopConditionalToGeneralPurposeRegister(); err != nil { - return err - } - - var ( - vt runtimeValueType - targetSizeInBytes int64 - waitFunc wasm.Index - ) - - unsignedType := wazeroir.UnsignedType(o.B1) - offset := uint32(o.U2) - - switch unsignedType { - case wazeroir.UnsignedTypeI32: - vt = runtimeValueTypeI32 - targetSizeInBytes = 32 / 8 - waitFunc = builtinFunctionMemoryWait32 - case wazeroir.UnsignedTypeI64: - vt = runtimeValueTypeI64 - targetSizeInBytes = 64 / 8 - waitFunc = builtinFunctionMemoryWait64 - } - - timeout := c.locationStack.pop() - if err := c.compileEnsureOnRegister(timeout); err != nil { - return err - } - exp := c.locationStack.pop() - if err := c.compileEnsureOnRegister(exp); err != nil { - return err - } - - reg, err := c.compileMemoryAccessCeilSetup(offset, targetSizeInBytes) - if err != nil { - return err - } - c.locationStack.markRegisterUsed(reg) - c.compileMemoryAlignmentCheck(reg, targetSizeInBytes) - c.assembler.CompileRegisterToRegister(amd64.ADDQ, amd64ReservedRegisterForMemory, reg) - c.assembler.CompileConstToRegister(amd64.ADDQ, -targetSizeInBytes, reg) - - // Push address, values, and timeout back to read in Go - c.pushRuntimeValueLocationOnRegister(reg, runtimeValueTypeI64) - c.pushRuntimeValueLocationOnRegister(exp.register, vt) - c.pushRuntimeValueLocationOnRegister(timeout.register, runtimeValueTypeI64) - if err := c.compileCallBuiltinFunction(waitFunc); err != nil { - return err - } - // Address, values and timeout consumed in Go - c.locationStack.pop() - c.locationStack.pop() - c.locationStack.pop() - - // Then, the result was pushed. - v := c.locationStack.pushRuntimeValueLocationOnStack() - v.valueType = runtimeValueTypeI32 - - c.locationStack.markRegisterUnused(reg) - c.locationStack.releaseRegister(exp) - c.locationStack.releaseRegister(timeout) - - // After return, we re-initialize reserved registers just like preamble of functions. - c.compileReservedStackBasePointerInitialization() - c.compileReservedMemoryPointerInitialization() - - return nil -} - -func (c *amd64Compiler) compileAtomicMemoryNotify(o *wazeroir.UnionOperation) error { - offset := uint32(o.U2) - - if err := c.maybeCompileMoveTopConditionalToGeneralPurposeRegister(); err != nil { - return err - } - - count := c.locationStack.pop() - if err := c.compileEnsureOnRegister(count); err != nil { - return err - } - - reg, err := c.compileMemoryAccessCeilSetup(offset, 4) - if err != nil { - return err - } - c.compileMemoryAlignmentCheck(reg, 4) - c.assembler.CompileRegisterToRegister(amd64.ADDQ, amd64ReservedRegisterForMemory, reg) - c.assembler.CompileConstToRegister(amd64.ADDQ, -4, reg) - - // Push address and count back to read in Go - c.pushRuntimeValueLocationOnRegister(reg, runtimeValueTypeI64) - c.pushRuntimeValueLocationOnRegister(count.register, runtimeValueTypeI32) - if err := c.compileCallBuiltinFunction(builtinFunctionMemoryNotify); err != nil { - return err - } - - // Address and count consumed by Go - c.locationStack.pop() - c.locationStack.pop() - - // Then, the result was pushed. - v := c.locationStack.pushRuntimeValueLocationOnStack() - v.valueType = runtimeValueTypeI32 - - // After return, we re-initialize reserved registers just like preamble of functions. - c.compileReservedStackBasePointerInitialization() - c.compileReservedMemoryPointerInitialization() - return nil -} - -func (c *amd64Compiler) compileAtomicFence(_ *wazeroir.UnionOperation) error { - c.assembler.CompileStandAlone(amd64.MFENCE) - return nil -} - -func (c *amd64Compiler) compileMemoryAlignmentCheck(baseRegister asm.Register, targetSizeInBytes int64) { - if targetSizeInBytes == 1 { - return // No alignment restrictions when accessing a byte - } - var checkBits asm.ConstantValue - switch targetSizeInBytes { - case 2: - checkBits = 0b1 - case 4: - checkBits = 0b11 - case 8: - checkBits = 0b111 - } - c.assembler.CompileConstToRegister(amd64.TESTQ, checkBits, baseRegister) - aligned := c.assembler.CompileJump(amd64.JEQ) - - c.compileExitFromNativeCode(nativeCallStatusUnalignedAtomic) - c.assembler.SetJumpTargetOnNext(aligned) -} diff --git a/internal/engine/compiler/impl_threads_arm64.go b/internal/engine/compiler/impl_threads_arm64.go deleted file mode 100644 index 99612a3b52..0000000000 --- a/internal/engine/compiler/impl_threads_arm64.go +++ /dev/null @@ -1,552 +0,0 @@ -package compiler - -import ( - "github.com/tetratelabs/wazero/internal/asm" - "github.com/tetratelabs/wazero/internal/asm/arm64" - "github.com/tetratelabs/wazero/internal/wasm" - "github.com/tetratelabs/wazero/internal/wazeroir" -) - -// compileMemoryAccessBaseSetup pops the top value from the stack (called "base"), stores "memoryBufferStart + base + offsetArg" -// into a register, and returns the stored register. We call the result "base" because it refers to "base addressing" as -// per arm docs, which are reads from addresses without offsets. The result is equivalent to &memory.Buffer[offset]. -// -// Note: this also emits the instructions to check the out of bounds memory access. -// In other words, if the offset+targetSizeInBytes exceeds the memory size, the code exits with nativeCallStatusCodeMemoryOutOfBounds status. -func (c *arm64Compiler) compileMemoryAccessBaseSetup(offsetArg uint32, targetSizeInBytes int64) (baseRegister asm.Register, err error) { - offsetReg, err := c.compileMemoryAccessOffsetSetup(offsetArg, targetSizeInBytes) - if err != nil { - return - } - - c.assembler.CompileRegisterToRegister(arm64.ADD, arm64ReservedRegisterForMemory, offsetReg) - baseRegister = offsetReg - return -} - -func (c *arm64Compiler) compileMemoryAlignmentCheck(baseRegister asm.Register, targetSizeInBytes int64) { - if targetSizeInBytes == 1 { - return // No alignment restrictions when accessing a byte - } - var checkBits asm.ConstantValue - switch targetSizeInBytes { - case 2: - checkBits = 0b1 - case 4: - checkBits = 0b11 - case 8: - checkBits = 0b111 - } - c.assembler.CompileRegisterAndConstToRegister(arm64.ANDS, baseRegister, checkBits, arm64.RegRZR) - c.compileMaybeExitFromNativeCode(arm64.BCONDEQ, nativeCallStatusUnalignedAtomic) -} - -func (c *arm64Compiler) compileAtomicLoad(o *wazeroir.UnionOperation) error { - var ( - loadInst asm.Instruction - targetSizeInBytes int64 - vt runtimeValueType - ) - - unsignedType := wazeroir.UnsignedType(o.B1) - offset := uint32(o.U2) - - switch unsignedType { - case wazeroir.UnsignedTypeI32: - loadInst = arm64.LDARW - targetSizeInBytes = 32 / 8 - vt = runtimeValueTypeI32 - case wazeroir.UnsignedTypeI64: - loadInst = arm64.LDARD - targetSizeInBytes = 64 / 8 - vt = runtimeValueTypeI64 - } - return c.compileAtomicLoadImpl(offset, loadInst, targetSizeInBytes, vt) -} - -// compileAtomicLoad8 implements compiler.compileAtomicLoad8 for the arm64 architecture. -func (c *arm64Compiler) compileAtomicLoad8(o *wazeroir.UnionOperation) error { - var vt runtimeValueType - - unsignedType := wazeroir.UnsignedType(o.B1) - offset := uint32(o.U2) - - switch unsignedType { - case wazeroir.UnsignedTypeI32: - vt = runtimeValueTypeI32 - case wazeroir.UnsignedTypeI64: - vt = runtimeValueTypeI64 - } - return c.compileAtomicLoadImpl(offset, arm64.LDARB, 1, vt) -} - -// compileAtomicLoad16 implements compiler.compileAtomicLoad16 for the arm64 architecture. -func (c *arm64Compiler) compileAtomicLoad16(o *wazeroir.UnionOperation) error { - var vt runtimeValueType - - unsignedType := wazeroir.UnsignedType(o.B1) - offset := uint32(o.U2) - - switch unsignedType { - case wazeroir.UnsignedTypeI32: - vt = runtimeValueTypeI32 - case wazeroir.UnsignedTypeI64: - vt = runtimeValueTypeI64 - } - return c.compileAtomicLoadImpl(offset, arm64.LDARH, 16/8, vt) -} - -func (c *arm64Compiler) compileAtomicLoadImpl(offsetArg uint32, loadInst asm.Instruction, - targetSizeInBytes int64, resultRuntimeValueType runtimeValueType, -) error { - baseReg, err := c.compileMemoryAccessBaseSetup(offsetArg, targetSizeInBytes) - if err != nil { - return err - } - - c.compileMemoryAlignmentCheck(baseReg, targetSizeInBytes) - - resultRegister := baseReg - c.assembler.CompileMemoryWithRegisterSourceToRegister(loadInst, baseReg, resultRegister) - - c.pushRuntimeValueLocationOnRegister(resultRegister, resultRuntimeValueType) - return nil -} - -func (c *arm64Compiler) compileAtomicStore(o *wazeroir.UnionOperation) error { - var ( - storeInst asm.Instruction - targetSizeInBytes int64 - ) - - unsignedType := wazeroir.UnsignedType(o.B1) - offset := uint32(o.U2) - - switch unsignedType { - case wazeroir.UnsignedTypeI32: - storeInst = arm64.STLRW - targetSizeInBytes = 32 / 8 - case wazeroir.UnsignedTypeI64: - storeInst = arm64.STLRD - targetSizeInBytes = 64 / 8 - } - return c.compileAtomicStoreImpl(offset, storeInst, targetSizeInBytes) -} - -// compileAtomicStore8 implements compiler.compileAtomiStore8 for the arm64 architecture. -func (c *arm64Compiler) compileAtomicStore8(o *wazeroir.UnionOperation) error { - offset := uint32(o.U2) - return c.compileAtomicStoreImpl(offset, arm64.STLRB, 1) -} - -// compileAtomicStore16 implements compiler.compileAtomicStore16 for the arm64 architecture. -func (c *arm64Compiler) compileAtomicStore16(o *wazeroir.UnionOperation) error { - offset := uint32(o.U2) - return c.compileAtomicStoreImpl(offset, arm64.STLRH, 16/8) -} - -func (c *arm64Compiler) compileAtomicStoreImpl(offsetArg uint32, storeInst asm.Instruction, targetSizeInBytes int64) error { - val, err := c.popValueOnRegister() - if err != nil { - return err - } - // Mark temporarily used as compileMemoryAccessOffsetSetup might try allocating register. - c.markRegisterUsed(val.register) - - baseReg, err := c.compileMemoryAccessBaseSetup(offsetArg, targetSizeInBytes) - if err != nil { - return err - } - c.compileMemoryAlignmentCheck(baseReg, targetSizeInBytes) - - c.assembler.CompileRegisterToMemoryWithRegisterDest( - storeInst, - val.register, - baseReg, - ) - - c.markRegisterUnused(val.register) - return nil -} - -func (c *arm64Compiler) compileAtomicRMW(o *wazeroir.UnionOperation) error { - var ( - inst asm.Instruction - targetSizeInBytes int64 - vt runtimeValueType - negateArg bool - flipArg bool - ) - - unsignedType := wazeroir.UnsignedType(o.B1) - op := wazeroir.AtomicArithmeticOp(o.B2) - offset := uint32(o.U2) - - switch unsignedType { - case wazeroir.UnsignedTypeI32: - targetSizeInBytes = 32 / 8 - vt = runtimeValueTypeI32 - switch op { - case wazeroir.AtomicArithmeticOpAdd: - inst = arm64.LDADDALW - case wazeroir.AtomicArithmeticOpSub: - inst = arm64.LDADDALW - negateArg = true - case wazeroir.AtomicArithmeticOpAnd: - inst = arm64.LDCLRALW - flipArg = true - case wazeroir.AtomicArithmeticOpOr: - inst = arm64.LDSETALW - case wazeroir.AtomicArithmeticOpXor: - inst = arm64.LDEORALW - case wazeroir.AtomicArithmeticOpNop: - inst = arm64.SWPALW - } - case wazeroir.UnsignedTypeI64: - targetSizeInBytes = 64 / 8 - vt = runtimeValueTypeI64 - switch op { - case wazeroir.AtomicArithmeticOpAdd: - inst = arm64.LDADDALD - case wazeroir.AtomicArithmeticOpSub: - inst = arm64.LDADDALD - negateArg = true - case wazeroir.AtomicArithmeticOpAnd: - inst = arm64.LDCLRALD - flipArg = true - case wazeroir.AtomicArithmeticOpOr: - inst = arm64.LDSETALD - case wazeroir.AtomicArithmeticOpXor: - inst = arm64.LDEORALD - case wazeroir.AtomicArithmeticOpNop: - inst = arm64.SWPALD - } - } - return c.compileAtomicRMWImpl(inst, offset, negateArg, flipArg, targetSizeInBytes, vt) -} - -func (c *arm64Compiler) compileAtomicRMW8(o *wazeroir.UnionOperation) error { - var ( - inst asm.Instruction - vt runtimeValueType - negateArg bool - flipArg bool - ) - - unsignedType := wazeroir.UnsignedType(o.B1) - op := wazeroir.AtomicArithmeticOp(o.B2) - offset := uint32(o.U2) - - switch op { - case wazeroir.AtomicArithmeticOpAdd: - inst = arm64.LDADDALB - case wazeroir.AtomicArithmeticOpSub: - inst = arm64.LDADDALB - negateArg = true - case wazeroir.AtomicArithmeticOpAnd: - inst = arm64.LDCLRALB - flipArg = true - case wazeroir.AtomicArithmeticOpOr: - inst = arm64.LDSETALB - case wazeroir.AtomicArithmeticOpXor: - inst = arm64.LDEORALB - case wazeroir.AtomicArithmeticOpNop: - inst = arm64.SWPALB - } - - switch unsignedType { - case wazeroir.UnsignedTypeI32: - vt = runtimeValueTypeI32 - case wazeroir.UnsignedTypeI64: - vt = runtimeValueTypeI64 - } - return c.compileAtomicRMWImpl(inst, offset, negateArg, flipArg, 1, vt) -} - -func (c *arm64Compiler) compileAtomicRMW16(o *wazeroir.UnionOperation) error { - var ( - inst asm.Instruction - vt runtimeValueType - negateArg bool - flipArg bool - ) - - unsignedType := wazeroir.UnsignedType(o.B1) - op := wazeroir.AtomicArithmeticOp(o.B2) - offset := uint32(o.U2) - - switch op { - case wazeroir.AtomicArithmeticOpAdd: - inst = arm64.LDADDALH - case wazeroir.AtomicArithmeticOpSub: - inst = arm64.LDADDALH - negateArg = true - case wazeroir.AtomicArithmeticOpAnd: - inst = arm64.LDCLRALH - flipArg = true - case wazeroir.AtomicArithmeticOpOr: - inst = arm64.LDSETALH - case wazeroir.AtomicArithmeticOpXor: - inst = arm64.LDEORALH - case wazeroir.AtomicArithmeticOpNop: - inst = arm64.SWPALH - } - - switch unsignedType { - case wazeroir.UnsignedTypeI32: - vt = runtimeValueTypeI32 - case wazeroir.UnsignedTypeI64: - vt = runtimeValueTypeI64 - } - return c.compileAtomicRMWImpl(inst, offset, negateArg, flipArg, 16/8, vt) -} - -func (c *arm64Compiler) compileAtomicRMWImpl(inst asm.Instruction, offsetArg uint32, negateArg bool, flipArg bool, - targetSizeInBytes int64, resultRuntimeValueType runtimeValueType, -) error { - val, err := c.popValueOnRegister() - if err != nil { - return err - } - // Mark temporarily used as compileMemoryAccessOffsetSetup might try allocating register. - c.markRegisterUsed(val.register) - - if negateArg { - switch resultRuntimeValueType { - case runtimeValueTypeI32: - c.assembler.CompileRegisterToRegister(arm64.NEGW, val.register, val.register) - case runtimeValueTypeI64: - c.assembler.CompileRegisterToRegister(arm64.NEG, val.register, val.register) - } - } - - if flipArg { - switch resultRuntimeValueType { - case runtimeValueTypeI32: - c.assembler.CompileTwoRegistersToRegister(arm64.ORNW, val.register, arm64.RegRZR, val.register) - case runtimeValueTypeI64: - c.assembler.CompileTwoRegistersToRegister(arm64.ORN, val.register, arm64.RegRZR, val.register) - } - } - - addrReg, err := c.compileMemoryAccessBaseSetup(offsetArg, targetSizeInBytes) - if err != nil { - return err - } - c.compileMemoryAlignmentCheck(addrReg, targetSizeInBytes) - - resultRegister := addrReg - c.assembler.CompileTwoRegistersToRegister(inst, val.register, addrReg, resultRegister) - - c.markRegisterUnused(val.register) - - c.pushRuntimeValueLocationOnRegister(resultRegister, resultRuntimeValueType) - return nil -} - -func (c *arm64Compiler) compileAtomicRMWCmpxchg(o *wazeroir.UnionOperation) error { - var ( - casInst asm.Instruction - targetSizeInBytes int64 - vt runtimeValueType - ) - - unsignedType := wazeroir.UnsignedType(o.B1) - offset := uint32(o.U2) - - switch unsignedType { - case wazeroir.UnsignedTypeI32: - casInst = arm64.CASALW - targetSizeInBytes = 32 / 8 - vt = runtimeValueTypeI32 - case wazeroir.UnsignedTypeI64: - casInst = arm64.CASALD - targetSizeInBytes = 64 / 8 - vt = runtimeValueTypeI64 - } - return c.compileAtomicRMWCmpxchgImpl(casInst, offset, targetSizeInBytes, vt) -} - -func (c *arm64Compiler) compileAtomicRMW8Cmpxchg(o *wazeroir.UnionOperation) error { - var vt runtimeValueType - - unsignedType := wazeroir.UnsignedType(o.B1) - offset := uint32(o.U2) - - switch unsignedType { - case wazeroir.UnsignedTypeI32: - vt = runtimeValueTypeI32 - case wazeroir.UnsignedTypeI64: - vt = runtimeValueTypeI64 - } - return c.compileAtomicRMWCmpxchgImpl(arm64.CASALB, offset, 1, vt) -} - -func (c *arm64Compiler) compileAtomicRMW16Cmpxchg(o *wazeroir.UnionOperation) error { - var vt runtimeValueType - - unsignedType := wazeroir.UnsignedType(o.B1) - offset := uint32(o.U2) - - switch unsignedType { - case wazeroir.UnsignedTypeI32: - vt = runtimeValueTypeI32 - case wazeroir.UnsignedTypeI64: - vt = runtimeValueTypeI64 - } - return c.compileAtomicRMWCmpxchgImpl(arm64.CASALH, offset, 16/8, vt) -} - -func (c *arm64Compiler) compileAtomicRMWCmpxchgImpl(inst asm.Instruction, offsetArg uint32, targetSizeInBytes int64, resultRuntimeValueType runtimeValueType) error { - repl, err := c.popValueOnRegister() - if err != nil { - return err - } - c.markRegisterUsed(repl.register) - // CAS instruction loads the old value into the register with the comparison value. - exp, err := c.popValueOnRegister() - if err != nil { - return err - } - if isZeroRegister(exp.register) { - // exp is also used to load, so if it's set to the zero register we need to move to a - // loadable register. - reg, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - c.assembler.CompileRegisterToRegister(arm64.MOVD, arm64.RegRZR, reg) - exp.register = reg - } - // Mark temporarily used as compileMemoryAccessOffsetSetup might try allocating register. - c.markRegisterUsed(exp.register) - - addrReg, err := c.compileMemoryAccessBaseSetup(offsetArg, targetSizeInBytes) - if err != nil { - return err - } - c.compileMemoryAlignmentCheck(addrReg, targetSizeInBytes) - - c.assembler.CompileTwoRegistersToRegister(inst, exp.register, addrReg, repl.register) - - c.markRegisterUnused(repl.register) - c.pushRuntimeValueLocationOnRegister(exp.register, resultRuntimeValueType) - return nil -} - -func (c *arm64Compiler) compileAtomicMemoryWait(o *wazeroir.UnionOperation) error { - if err := c.maybeCompileMoveTopConditionalToGeneralPurposeRegister(); err != nil { - return err - } - - var ( - vt runtimeValueType - targetSizeInBytes int64 - waitFunc wasm.Index - ) - - unsignedType := wazeroir.UnsignedType(o.B1) - offset := uint32(o.U2) - - switch unsignedType { - case wazeroir.UnsignedTypeI32: - vt = runtimeValueTypeI32 - targetSizeInBytes = 32 / 8 - waitFunc = builtinFunctionMemoryWait32 - case wazeroir.UnsignedTypeI64: - vt = runtimeValueTypeI64 - targetSizeInBytes = 64 / 8 - waitFunc = builtinFunctionMemoryWait64 - } - - timeout, err := c.popValueOnRegister() - if err != nil { - return err - } - c.markRegisterUsed(timeout.register) - exp, err := c.popValueOnRegister() - if err != nil { - return err - } - c.markRegisterUsed(exp.register) - - baseReg, err := c.compileMemoryAccessBaseSetup(offset, targetSizeInBytes) - if err != nil { - return err - } - c.markRegisterUsed(baseReg) - c.compileMemoryAlignmentCheck(baseReg, targetSizeInBytes) - - // Push address, values, and timeout back to read in Go - c.pushRuntimeValueLocationOnRegister(baseReg, runtimeValueTypeI64) - c.pushRuntimeValueLocationOnRegister(exp.register, vt) - c.pushRuntimeValueLocationOnRegister(timeout.register, runtimeValueTypeI64) - if err := c.compileCallGoFunction(nativeCallStatusCodeCallBuiltInFunction, waitFunc); err != nil { - return err - } - // Address, values and timeout consumed in Go - c.locationStack.pop() - c.locationStack.pop() - c.locationStack.pop() - - // Then, the result was pushed. - v := c.locationStack.pushRuntimeValueLocationOnStack() - v.valueType = runtimeValueTypeI32 - - c.markRegisterUnused(baseReg) - c.markRegisterUnused(exp.register) - c.markRegisterUnused(timeout.register) - - // After return, we re-initialize reserved registers just like preamble of functions. - c.compileReservedStackBasePointerRegisterInitialization() - c.compileReservedMemoryRegisterInitialization() - - return nil -} - -func (c *arm64Compiler) compileAtomicMemoryNotify(o *wazeroir.UnionOperation) error { - offset := uint32(o.U2) - - if err := c.maybeCompileMoveTopConditionalToGeneralPurposeRegister(); err != nil { - return err - } - - count, err := c.popValueOnRegister() - if err != nil { - return err - } - c.markRegisterUsed(count.register) - - baseReg, err := c.compileMemoryAccessBaseSetup(offset, 4) - if err != nil { - return err - } - c.compileMemoryAlignmentCheck(baseReg, 4) - - // Push address and count back to read in Go - c.pushRuntimeValueLocationOnRegister(baseReg, runtimeValueTypeI64) - c.pushRuntimeValueLocationOnRegister(count.register, runtimeValueTypeI32) - if err := c.compileCallGoFunction(nativeCallStatusCodeCallBuiltInFunction, builtinFunctionMemoryNotify); err != nil { - return err - } - - // Address and count consumed by Go - c.locationStack.pop() - c.locationStack.pop() - - // Then, the result was pushed. - v := c.locationStack.pushRuntimeValueLocationOnStack() - v.valueType = runtimeValueTypeI32 - - c.markRegisterUnused(count.register) - - // After return, we re-initialize reserved registers just like preamble of functions. - c.compileReservedStackBasePointerRegisterInitialization() - c.compileReservedMemoryRegisterInitialization() - return nil -} - -func (c *arm64Compiler) compileAtomicFence(_ *wazeroir.UnionOperation) error { - c.assembler.CompileStandAlone(arm64.DMB) - return nil -} diff --git a/internal/engine/compiler/impl_vec_amd64.go b/internal/engine/compiler/impl_vec_amd64.go deleted file mode 100644 index d6c111db4e..0000000000 --- a/internal/engine/compiler/impl_vec_amd64.go +++ /dev/null @@ -1,2812 +0,0 @@ -package compiler - -import ( - "errors" - - "github.com/tetratelabs/wazero/internal/asm" - "github.com/tetratelabs/wazero/internal/asm/amd64" - "github.com/tetratelabs/wazero/internal/wazeroir" -) - -// compileV128Const implements compiler.compileV128Const for amd64 architecture. -func (c *amd64Compiler) compileV128Const(o *wazeroir.UnionOperation) error { - if err := c.maybeCompileMoveTopConditionalToGeneralPurposeRegister(); err != nil { - return err - } - - lo, hi := o.U1, o.U2 - - result, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - - // We cannot directly load the value from memory to float regs, - // so we move it to int reg temporarily. - tmpReg, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - - // Move the lower 64-bits. - if lo == 0 { - c.assembler.CompileRegisterToRegister(amd64.XORQ, tmpReg, tmpReg) - } else { - c.assembler.CompileConstToRegister(amd64.MOVQ, int64(lo), tmpReg) - } - c.assembler.CompileRegisterToRegister(amd64.MOVQ, tmpReg, result) - - if lo != 0 && hi == 0 { - c.assembler.CompileRegisterToRegister(amd64.XORQ, tmpReg, tmpReg) - } else if hi != 0 { - c.assembler.CompileConstToRegister(amd64.MOVQ, int64(hi), tmpReg) - } - // Move the higher 64-bits with PINSRQ at the second element of 64x2 vector. - c.assembler.CompileRegisterToRegisterWithArg(amd64.PINSRQ, tmpReg, result, 1) - - c.pushVectorRuntimeValueLocationOnRegister(result) - return nil -} - -// compileV128Add implements compiler.compileV128Add for amd64 architecture. -func (c *amd64Compiler) compileV128Add(o *wazeroir.UnionOperation) error { - x2 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x2); err != nil { - return err - } - - x1 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x1); err != nil { - return err - } - var inst asm.Instruction - shape := o.B1 - switch shape { - case wazeroir.ShapeI8x16: - inst = amd64.PADDB - case wazeroir.ShapeI16x8: - inst = amd64.PADDW - case wazeroir.ShapeI32x4: - inst = amd64.PADDD - case wazeroir.ShapeI64x2: - inst = amd64.PADDQ - case wazeroir.ShapeF32x4: - inst = amd64.ADDPS - case wazeroir.ShapeF64x2: - inst = amd64.ADDPD - } - c.assembler.CompileRegisterToRegister(inst, x2.register, x1.register) - - c.pushVectorRuntimeValueLocationOnRegister(x1.register) - c.locationStack.markRegisterUnused(x2.register) - return nil -} - -// compileV128Sub implements compiler.compileV128Sub for amd64 architecture. -func (c *amd64Compiler) compileV128Sub(o *wazeroir.UnionOperation) error { - x2 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x2); err != nil { - return err - } - - x1 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x1); err != nil { - return err - } - var inst asm.Instruction - shape := o.B1 - switch shape { - case wazeroir.ShapeI8x16: - inst = amd64.PSUBB - case wazeroir.ShapeI16x8: - inst = amd64.PSUBW - case wazeroir.ShapeI32x4: - inst = amd64.PSUBD - case wazeroir.ShapeI64x2: - inst = amd64.PSUBQ - case wazeroir.ShapeF32x4: - inst = amd64.SUBPS - case wazeroir.ShapeF64x2: - inst = amd64.SUBPD - } - c.assembler.CompileRegisterToRegister(inst, x2.register, x1.register) - - c.pushVectorRuntimeValueLocationOnRegister(x1.register) - c.locationStack.markRegisterUnused(x2.register) - return nil -} - -// compileV128Load implements compiler.compileV128Load for amd64 architecture. -func (c *amd64Compiler) compileV128Load(o *wazeroir.UnionOperation) error { - result, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - - offset := uint32(o.U2) - loadType := wazeroir.V128LoadType(o.B1) - - switch loadType { - case wazeroir.V128LoadType128: - err = c.compileV128LoadImpl(amd64.MOVDQU, offset, 16, result) - case wazeroir.V128LoadType8x8s: - err = c.compileV128LoadImpl(amd64.PMOVSXBW, offset, 8, result) - case wazeroir.V128LoadType8x8u: - err = c.compileV128LoadImpl(amd64.PMOVZXBW, offset, 8, result) - case wazeroir.V128LoadType16x4s: - err = c.compileV128LoadImpl(amd64.PMOVSXWD, offset, 8, result) - case wazeroir.V128LoadType16x4u: - err = c.compileV128LoadImpl(amd64.PMOVZXWD, offset, 8, result) - case wazeroir.V128LoadType32x2s: - err = c.compileV128LoadImpl(amd64.PMOVSXDQ, offset, 8, result) - case wazeroir.V128LoadType32x2u: - err = c.compileV128LoadImpl(amd64.PMOVZXDQ, offset, 8, result) - case wazeroir.V128LoadType8Splat: - reg, err := c.compileMemoryAccessCeilSetup(offset, 1) - if err != nil { - return err - } - c.assembler.CompileMemoryWithIndexToRegister(amd64.MOVBQZX, amd64ReservedRegisterForMemory, -1, - reg, 1, reg) - // pinsrb $0, reg, result - // pxor tmpVReg, tmpVReg - // pshufb tmpVReg, result - c.locationStack.markRegisterUsed(result) - tmpVReg, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - c.assembler.CompileRegisterToRegisterWithArg(amd64.PINSRB, reg, result, 0) - c.assembler.CompileRegisterToRegister(amd64.PXOR, tmpVReg, tmpVReg) - c.assembler.CompileRegisterToRegister(amd64.PSHUFB, tmpVReg, result) - case wazeroir.V128LoadType16Splat: - reg, err := c.compileMemoryAccessCeilSetup(offset, 2) - if err != nil { - return err - } - c.assembler.CompileMemoryWithIndexToRegister(amd64.MOVWQZX, amd64ReservedRegisterForMemory, -2, - reg, 1, reg) - // pinsrw $0, reg, result - // pinsrw $1, reg, result - // pshufd $0, result, result (result = result[0,0,0,0]) - c.assembler.CompileRegisterToRegisterWithArg(amd64.PINSRW, reg, result, 0) - c.assembler.CompileRegisterToRegisterWithArg(amd64.PINSRW, reg, result, 1) - c.assembler.CompileRegisterToRegisterWithArg(amd64.PSHUFD, result, result, 0) - case wazeroir.V128LoadType32Splat: - reg, err := c.compileMemoryAccessCeilSetup(offset, 4) - if err != nil { - return err - } - c.assembler.CompileMemoryWithIndexToRegister(amd64.MOVLQZX, amd64ReservedRegisterForMemory, -4, - reg, 1, reg) - // pinsrd $0, reg, result - // pshufd $0, result, result (result = result[0,0,0,0]) - c.assembler.CompileRegisterToRegisterWithArg(amd64.PINSRD, reg, result, 0) - c.assembler.CompileRegisterToRegisterWithArg(amd64.PSHUFD, result, result, 0) - case wazeroir.V128LoadType64Splat: - reg, err := c.compileMemoryAccessCeilSetup(offset, 8) - if err != nil { - return err - } - c.assembler.CompileMemoryWithIndexToRegister(amd64.MOVQ, amd64ReservedRegisterForMemory, -8, - reg, 1, reg) - // pinsrq $0, reg, result - // pinsrq $1, reg, result - c.assembler.CompileRegisterToRegisterWithArg(amd64.PINSRQ, reg, result, 0) - c.assembler.CompileRegisterToRegisterWithArg(amd64.PINSRQ, reg, result, 1) - case wazeroir.V128LoadType32zero: - err = c.compileV128LoadImpl(amd64.MOVL, offset, 4, result) - case wazeroir.V128LoadType64zero: - err = c.compileV128LoadImpl(amd64.MOVQ, offset, 8, result) - } - - if err != nil { - return err - } - - c.pushVectorRuntimeValueLocationOnRegister(result) - return nil -} - -func (c *amd64Compiler) compileV128LoadImpl(inst asm.Instruction, offset uint32, targetSizeInBytes int64, dst asm.Register) error { - offsetReg, err := c.compileMemoryAccessCeilSetup(offset, targetSizeInBytes) - if err != nil { - return err - } - c.assembler.CompileMemoryWithIndexToRegister(inst, amd64ReservedRegisterForMemory, -targetSizeInBytes, - offsetReg, 1, dst) - return nil -} - -// compileV128LoadLane implements compiler.compileV128LoadLane for amd64. -func (c *amd64Compiler) compileV128LoadLane(o *wazeroir.UnionOperation) error { - targetVector := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(targetVector); err != nil { - return err - } - - laneSize, laneIndex := o.B1, o.B2 - offset := uint32(o.U2) - - var insertInst asm.Instruction - switch laneSize { - case 8: - insertInst = amd64.PINSRB - case 16: - insertInst = amd64.PINSRW - case 32: - insertInst = amd64.PINSRD - case 64: - insertInst = amd64.PINSRQ - } - - targetSizeInBytes := int64(laneSize / 8) - offsetReg, err := c.compileMemoryAccessCeilSetup(offset, targetSizeInBytes) - if err != nil { - return err - } - c.assembler.CompileMemoryWithIndexAndArgToRegister(insertInst, amd64ReservedRegisterForMemory, -targetSizeInBytes, - offsetReg, 1, targetVector.register, laneIndex) - - c.pushVectorRuntimeValueLocationOnRegister(targetVector.register) - return nil -} - -// compileV128Store implements compiler.compileV128Store for amd64. -func (c *amd64Compiler) compileV128Store(o *wazeroir.UnionOperation) error { - val := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(val); err != nil { - return err - } - - const targetSizeInBytes = 16 - offset := uint32(o.U2) - offsetReg, err := c.compileMemoryAccessCeilSetup(offset, targetSizeInBytes) - if err != nil { - return err - } - - c.assembler.CompileRegisterToMemoryWithIndex(amd64.MOVDQU, val.register, - amd64ReservedRegisterForMemory, -targetSizeInBytes, offsetReg, 1) - - c.locationStack.markRegisterUnused(val.register, offsetReg) - return nil -} - -// compileV128StoreLane implements compiler.compileV128StoreLane for amd64. -func (c *amd64Compiler) compileV128StoreLane(o *wazeroir.UnionOperation) error { - var storeInst asm.Instruction - laneSize := o.B1 - laneIndex := o.B2 - offset := uint32(o.U2) - switch laneSize { - case 8: - storeInst = amd64.PEXTRB - case 16: - storeInst = amd64.PEXTRW - case 32: - storeInst = amd64.PEXTRD - case 64: - storeInst = amd64.PEXTRQ - } - - val := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(val); err != nil { - return err - } - - targetSizeInBytes := int64(laneSize / 8) - offsetReg, err := c.compileMemoryAccessCeilSetup(offset, targetSizeInBytes) - if err != nil { - return err - } - - c.assembler.CompileRegisterToMemoryWithIndexAndArg(storeInst, val.register, - amd64ReservedRegisterForMemory, -targetSizeInBytes, offsetReg, 1, laneIndex) - - c.locationStack.markRegisterUnused(val.register, offsetReg) - return nil -} - -// compileV128ExtractLane implements compiler.compileV128ExtractLane for amd64. -func (c *amd64Compiler) compileV128ExtractLane(o *wazeroir.UnionOperation) error { - v := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(v); err != nil { - return err - } - vreg := v.register - shape := o.B1 - laneIndex := o.B2 - signed := o.B3 - switch shape { - case wazeroir.ShapeI8x16: - result, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - c.assembler.CompileRegisterToRegisterWithArg(amd64.PEXTRB, vreg, result, laneIndex) - if signed { - c.assembler.CompileRegisterToRegister(amd64.MOVBLSX, result, result) - } else { - c.assembler.CompileRegisterToRegister(amd64.MOVBLZX, result, result) - } - c.pushRuntimeValueLocationOnRegister(result, runtimeValueTypeI32) - c.locationStack.markRegisterUnused(vreg) - case wazeroir.ShapeI16x8: - result, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - c.assembler.CompileRegisterToRegisterWithArg(amd64.PEXTRW, vreg, result, laneIndex) - if signed { - c.assembler.CompileRegisterToRegister(amd64.MOVWLSX, result, result) - } else { - c.assembler.CompileRegisterToRegister(amd64.MOVWLZX, result, result) - } - c.pushRuntimeValueLocationOnRegister(result, runtimeValueTypeI32) - c.locationStack.markRegisterUnused(vreg) - case wazeroir.ShapeI32x4: - result, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - c.assembler.CompileRegisterToRegisterWithArg(amd64.PEXTRD, vreg, result, laneIndex) - c.pushRuntimeValueLocationOnRegister(result, runtimeValueTypeI32) - c.locationStack.markRegisterUnused(vreg) - case wazeroir.ShapeI64x2: - result, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - c.assembler.CompileRegisterToRegisterWithArg(amd64.PEXTRQ, vreg, result, laneIndex) - c.pushRuntimeValueLocationOnRegister(result, runtimeValueTypeI64) - c.locationStack.markRegisterUnused(vreg) - case wazeroir.ShapeF32x4: - if laneIndex != 0 { - c.assembler.CompileRegisterToRegisterWithArg(amd64.PSHUFD, vreg, vreg, laneIndex) - } - c.pushRuntimeValueLocationOnRegister(vreg, runtimeValueTypeF32) - case wazeroir.ShapeF64x2: - if laneIndex != 0 { - // This case we can assume LaneIndex == 1. - // We have to modify the val.register as, for example: - // 0b11 0b10 0b01 0b00 - // | | | | - // [x3, x2, x1, x0] -> [x0, x0, x3, x2] - // where val.register = [x3, x2, x1, x0] and each xN = 32bits. - // Then, we interpret the register as float64, therefore, the float64 value is obtained as [x3, x2]. - arg := byte(0b00_00_11_10) - c.assembler.CompileRegisterToRegisterWithArg(amd64.PSHUFD, vreg, vreg, arg) - } - c.pushRuntimeValueLocationOnRegister(vreg, runtimeValueTypeF64) - } - - return nil -} - -// compileV128ReplaceLane implements compiler.compileV128ReplaceLane for amd64. -func (c *amd64Compiler) compileV128ReplaceLane(o *wazeroir.UnionOperation) error { - origin := c.locationStack.pop() - if err := c.compileEnsureOnRegister(origin); err != nil { - return err - } - - vector := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(vector); err != nil { - return err - } - - shape := o.B1 - laneIndex := o.B2 - switch shape { - case wazeroir.ShapeI8x16: - c.assembler.CompileRegisterToRegisterWithArg(amd64.PINSRB, origin.register, vector.register, laneIndex) - case wazeroir.ShapeI16x8: - c.assembler.CompileRegisterToRegisterWithArg(amd64.PINSRW, origin.register, vector.register, laneIndex) - case wazeroir.ShapeI32x4: - c.assembler.CompileRegisterToRegisterWithArg(amd64.PINSRD, origin.register, vector.register, laneIndex) - case wazeroir.ShapeI64x2: - c.assembler.CompileRegisterToRegisterWithArg(amd64.PINSRQ, origin.register, vector.register, laneIndex) - case wazeroir.ShapeF32x4: - c.assembler.CompileRegisterToRegisterWithArg(amd64.INSERTPS, origin.register, vector.register, - // In INSERTPS instruction, the destination index is encoded at 4 and 5 bits of the argument. - // See https://www.felixcloutier.com/x86/insertps - laneIndex<<4, - ) - case wazeroir.ShapeF64x2: - if laneIndex == 0 { - c.assembler.CompileRegisterToRegister(amd64.MOVSD, origin.register, vector.register) - } else { - c.assembler.CompileRegisterToRegister(amd64.MOVLHPS, origin.register, vector.register) - } - } - - c.pushVectorRuntimeValueLocationOnRegister(vector.register) - c.locationStack.markRegisterUnused(origin.register) - return nil -} - -// compileV128Splat implements compiler.compileV128Splat for amd64. -func (c *amd64Compiler) compileV128Splat(o *wazeroir.UnionOperation) (err error) { - origin := c.locationStack.pop() - if err = c.compileEnsureOnRegister(origin); err != nil { - return - } - - var result asm.Register - shape := o.B1 - switch shape { - case wazeroir.ShapeI8x16: - result, err = c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - c.locationStack.markRegisterUsed(result) - - tmp, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - c.assembler.CompileRegisterToRegisterWithArg(amd64.PINSRB, origin.register, result, 0) - c.assembler.CompileRegisterToRegister(amd64.PXOR, tmp, tmp) - c.assembler.CompileRegisterToRegister(amd64.PSHUFB, tmp, result) - case wazeroir.ShapeI16x8: - result, err = c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - c.locationStack.markRegisterUsed(result) - c.assembler.CompileRegisterToRegisterWithArg(amd64.PINSRW, origin.register, result, 0) - c.assembler.CompileRegisterToRegisterWithArg(amd64.PINSRW, origin.register, result, 1) - c.assembler.CompileRegisterToRegisterWithArg(amd64.PSHUFD, result, result, 0) - case wazeroir.ShapeI32x4: - result, err = c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - c.locationStack.markRegisterUsed(result) - c.assembler.CompileRegisterToRegisterWithArg(amd64.PINSRD, origin.register, result, 0) - c.assembler.CompileRegisterToRegisterWithArg(amd64.PSHUFD, result, result, 0) - case wazeroir.ShapeI64x2: - result, err = c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - c.locationStack.markRegisterUsed(result) - c.assembler.CompileRegisterToRegisterWithArg(amd64.PINSRQ, origin.register, result, 0) - c.assembler.CompileRegisterToRegisterWithArg(amd64.PINSRQ, origin.register, result, 1) - case wazeroir.ShapeF32x4: - result = origin.register - c.assembler.CompileRegisterToRegisterWithArg(amd64.INSERTPS, origin.register, result, 0) - c.assembler.CompileRegisterToRegisterWithArg(amd64.PSHUFD, result, result, 0) - case wazeroir.ShapeF64x2: - result = origin.register - c.assembler.CompileRegisterToRegister(amd64.MOVQ, origin.register, result) - c.assembler.CompileRegisterToRegister(amd64.MOVLHPS, origin.register, result) - } - - c.locationStack.markRegisterUnused(origin.register) - c.pushVectorRuntimeValueLocationOnRegister(result) - return nil -} - -// compileV128Shuffle implements compiler.compileV128Shuffle for amd64. -func (c *amd64Compiler) compileV128Shuffle(o *wazeroir.UnionOperation) error { - w := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(w); err != nil { - return err - } - - v := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(v); err != nil { - return err - } - - wr, vr := w.register, v.register - - tmp, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - - consts := [32]byte{} - lanes := o.Us - for i, unsignedLane := range lanes { - lane := byte(unsignedLane) - if lane < 16 { - consts[i+16] = 0x80 - consts[i] = lane - } else { - consts[i+16] = lane - 16 - consts[i] = 0x80 - } - } - - err = c.assembler.CompileStaticConstToRegister(amd64.MOVDQU, asm.NewStaticConst(consts[:16]), tmp) - if err != nil { - return err - } - c.assembler.CompileRegisterToRegister(amd64.PSHUFB, tmp, vr) - err = c.assembler.CompileStaticConstToRegister(amd64.MOVDQU, asm.NewStaticConst(consts[16:]), tmp) - if err != nil { - return err - } - c.assembler.CompileRegisterToRegister(amd64.PSHUFB, tmp, wr) - c.assembler.CompileRegisterToRegister(amd64.ORPS, vr, wr) - - c.pushVectorRuntimeValueLocationOnRegister(wr) - c.locationStack.markRegisterUnused(vr) - return nil -} - -var swizzleConst = [16]byte{ - 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, - 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, -} - -// compileV128Swizzle implements compiler.compileV128Swizzle for amd64. -func (c *amd64Compiler) compileV128Swizzle(*wazeroir.UnionOperation) error { - index := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(index); err != nil { - return err - } - - base := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(base); err != nil { - return err - } - - idxReg, baseReg := index.register, base.register - - tmp, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - - err = c.assembler.CompileStaticConstToRegister(amd64.MOVDQU, asm.NewStaticConst(swizzleConst[:]), tmp) - if err != nil { - return err - } - - c.assembler.CompileRegisterToRegister(amd64.PADDUSB, tmp, idxReg) - c.assembler.CompileRegisterToRegister(amd64.PSHUFB, idxReg, baseReg) - - c.pushVectorRuntimeValueLocationOnRegister(baseReg) - c.locationStack.markRegisterUnused(idxReg) - return nil -} - -// compileV128AnyTrue implements compiler.compileV128AnyTrue for amd64. -func (c *amd64Compiler) compileV128AnyTrue(*wazeroir.UnionOperation) error { - v := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(v); err != nil { - return err - } - vreg := v.register - - c.assembler.CompileRegisterToRegister(amd64.PTEST, vreg, vreg) - - c.locationStack.pushRuntimeValueLocationOnConditionalRegister(amd64.ConditionalRegisterStateNE) - c.locationStack.markRegisterUnused(vreg) - return nil -} - -// compileV128AllTrue implements compiler.compileV128AllTrue for amd64. -func (c *amd64Compiler) compileV128AllTrue(o *wazeroir.UnionOperation) error { - v := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(v); err != nil { - return err - } - - tmp, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - - var cmpInst asm.Instruction - shape := o.B1 - switch shape { - case wazeroir.ShapeI8x16: - cmpInst = amd64.PCMPEQB - case wazeroir.ShapeI16x8: - cmpInst = amd64.PCMPEQW - case wazeroir.ShapeI32x4: - cmpInst = amd64.PCMPEQD - case wazeroir.ShapeI64x2: - cmpInst = amd64.PCMPEQQ - } - - c.assembler.CompileRegisterToRegister(amd64.PXOR, tmp, tmp) - c.assembler.CompileRegisterToRegister(cmpInst, v.register, tmp) - c.assembler.CompileRegisterToRegister(amd64.PTEST, tmp, tmp) - c.locationStack.markRegisterUnused(v.register, tmp) - c.locationStack.pushRuntimeValueLocationOnConditionalRegister(amd64.ConditionalRegisterStateE) - return nil -} - -// compileV128BitMask implements compiler.compileV128BitMask for amd64. -func (c *amd64Compiler) compileV128BitMask(o *wazeroir.UnionOperation) error { - v := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(v); err != nil { - return err - } - - result, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - - shape := o.B1 - switch shape { - case wazeroir.ShapeI8x16: - c.assembler.CompileRegisterToRegister(amd64.PMOVMSKB, v.register, result) - case wazeroir.ShapeI16x8: - // When we have: - // R1 = [R1(w1), R1(w2), R1(w3), R1(w4), R1(w5), R1(w6), R1(w7), R1(v8)] - // R2 = [R2(w1), R2(w2), R2(w3), R2(v4), R2(w5), R2(w6), R2(w7), R2(v8)] - // where RX(wn) is n-th signed word (16-bit) of RX register, - // - // "PACKSSWB R1, R2" produces - // R1 = [ - // byte_sat(R1(w1)), byte_sat(R1(w2)), byte_sat(R1(w3)), byte_sat(R1(w4)), - // byte_sat(R1(w5)), byte_sat(R1(w6)), byte_sat(R1(w7)), byte_sat(R1(w8)), - // byte_sat(R2(w1)), byte_sat(R2(w2)), byte_sat(R2(w3)), byte_sat(R2(w4)), - // byte_sat(R2(w5)), byte_sat(R2(w6)), byte_sat(R2(w7)), byte_sat(R2(w8)), - // ] - // where R1 is the destination register, and - // byte_sat(w) = int8(w) if w fits as signed 8-bit, - // 0x80 if w is less than 0x80 - // 0x7F if w is greater than 0x7f - // - // See https://www.felixcloutier.com/x86/packsswb:packssdw for detail. - // - // Therefore, v.register ends up having i-th and (i+8)-th bit set if i-th lane is negative (for i in 0..8). - c.assembler.CompileRegisterToRegister(amd64.PACKSSWB, v.register, v.register) - c.assembler.CompileRegisterToRegister(amd64.PMOVMSKB, v.register, result) - // Clear the higher bits than 8. - c.assembler.CompileConstToRegister(amd64.SHRQ, 8, result) - case wazeroir.ShapeI32x4: - c.assembler.CompileRegisterToRegister(amd64.MOVMSKPS, v.register, result) - case wazeroir.ShapeI64x2: - c.assembler.CompileRegisterToRegister(amd64.MOVMSKPD, v.register, result) - } - - c.locationStack.markRegisterUnused(v.register) - c.pushRuntimeValueLocationOnRegister(result, runtimeValueTypeI32) - return nil -} - -// compileV128And implements compiler.compileV128And for amd64. -func (c *amd64Compiler) compileV128And(*wazeroir.UnionOperation) error { - x2 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x2); err != nil { - return err - } - - x1 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x1); err != nil { - return err - } - - c.assembler.CompileRegisterToRegister(amd64.PAND, x2.register, x1.register) - - c.locationStack.markRegisterUnused(x2.register) - c.pushVectorRuntimeValueLocationOnRegister(x1.register) - return nil -} - -// compileV128Not implements compiler.compileV128Not for amd64. -func (c *amd64Compiler) compileV128Not(*wazeroir.UnionOperation) error { - v := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(v); err != nil { - return err - } - - tmp, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - - // Set all bits on tmp register. - c.assembler.CompileRegisterToRegister(amd64.PCMPEQD, tmp, tmp) - // Then XOR with tmp to reverse all bits on v.register. - c.assembler.CompileRegisterToRegister(amd64.PXOR, tmp, v.register) - c.pushVectorRuntimeValueLocationOnRegister(v.register) - return nil -} - -// compileV128Or implements compiler.compileV128Or for amd64. -func (c *amd64Compiler) compileV128Or(*wazeroir.UnionOperation) error { - x2 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x2); err != nil { - return err - } - - x1 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x1); err != nil { - return err - } - - c.assembler.CompileRegisterToRegister(amd64.POR, x2.register, x1.register) - - c.locationStack.markRegisterUnused(x2.register) - c.pushVectorRuntimeValueLocationOnRegister(x1.register) - return nil -} - -// compileV128Xor implements compiler.compileV128Xor for amd64. -func (c *amd64Compiler) compileV128Xor(*wazeroir.UnionOperation) error { - x2 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x2); err != nil { - return err - } - - x1 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x1); err != nil { - return err - } - - c.assembler.CompileRegisterToRegister(amd64.PXOR, x2.register, x1.register) - - c.locationStack.markRegisterUnused(x2.register) - c.pushVectorRuntimeValueLocationOnRegister(x1.register) - return nil -} - -// compileV128Bitselect implements compiler.compileV128Bitselect for amd64. -func (c *amd64Compiler) compileV128Bitselect(*wazeroir.UnionOperation) error { - selector := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(selector); err != nil { - return err - } - - x2 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x2); err != nil { - return err - } - - x1 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x1); err != nil { - return err - } - - // The following logic is equivalent to v128.or(v128.and(v1, selector), v128.and(v2, v128.not(selector))) - // See https://github.com/WebAssembly/spec/blob/wg-2.0.draft1/proposals/simd/SIMD.md#bitwise-select - c.assembler.CompileRegisterToRegister(amd64.PAND, selector.register, x1.register) - c.assembler.CompileRegisterToRegister(amd64.PANDN, x2.register, selector.register) - c.assembler.CompileRegisterToRegister(amd64.POR, selector.register, x1.register) - - c.locationStack.markRegisterUnused(x2.register, selector.register) - c.pushVectorRuntimeValueLocationOnRegister(x1.register) - return nil -} - -// compileV128AndNot implements compiler.compileV128AndNot for amd64. -func (c *amd64Compiler) compileV128AndNot(*wazeroir.UnionOperation) error { - x2 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x2); err != nil { - return err - } - - x1 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x1); err != nil { - return err - } - - c.assembler.CompileRegisterToRegister(amd64.PANDN, x1.register, x2.register) - - c.locationStack.markRegisterUnused(x1.register) - c.pushVectorRuntimeValueLocationOnRegister(x2.register) - return nil -} - -// compileV128Shr implements compiler.compileV128Shr for amd64. -func (c *amd64Compiler) compileV128Shr(o *wazeroir.UnionOperation) error { - // https://stackoverflow.com/questions/35002937/sse-simd-shift-with-one-byte-element-size-granularity - shape := o.B1 - signed := o.B3 - if shape == wazeroir.ShapeI8x16 { - return c.compileV128ShrI8x16Impl(signed) - } else if shape == wazeroir.ShapeI64x2 && signed { - return c.compileV128ShrI64x2SignedImpl() - } else { - return c.compileV128ShrImpl(o) - } -} - -// compileV128ShrImpl implements shift right instructions except for i8x16 (logical/arithmetic) and i64x2 (arithmetic). -func (c *amd64Compiler) compileV128ShrImpl(o *wazeroir.UnionOperation) error { - s := c.locationStack.pop() - if err := c.compileEnsureOnRegister(s); err != nil { - return err - } - - x1 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x1); err != nil { - return err - } - - vecTmp, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - - var moduleConst int64 - var shift asm.Instruction - shape := o.B1 - signed := o.B3 - switch shape { - case wazeroir.ShapeI16x8: - moduleConst = 0xf // modulo 16. - if signed { - shift = amd64.PSRAW - } else { - shift = amd64.PSRLW - } - case wazeroir.ShapeI32x4: - moduleConst = 0x1f // modulo 32. - if signed { - shift = amd64.PSRAD - } else { - shift = amd64.PSRLD - } - case wazeroir.ShapeI64x2: - moduleConst = 0x3f // modulo 64. - shift = amd64.PSRLQ - } - - gpShiftAmount := s.register - c.assembler.CompileConstToRegister(amd64.ANDQ, moduleConst, gpShiftAmount) - c.assembler.CompileRegisterToRegister(amd64.MOVL, gpShiftAmount, vecTmp) - c.assembler.CompileRegisterToRegister(shift, vecTmp, x1.register) - - c.locationStack.markRegisterUnused(gpShiftAmount) - c.pushVectorRuntimeValueLocationOnRegister(x1.register) - return nil -} - -// compileV128ShrI64x2SignedImpl implements compiler.compileV128Shr for i64x2 signed (arithmetic) shift. -// PSRAQ instruction requires AVX, so we emulate it without AVX instructions. https://www.felixcloutier.com/x86/psraw:psrad:psraq -func (c *amd64Compiler) compileV128ShrI64x2SignedImpl() error { - const shiftCountRegister = amd64.RegCX - - s := c.locationStack.pop() - if s.register != shiftCountRegister { - // If another value lives on the CX register, we release it to the stack. - c.onValueReleaseRegisterToStack(shiftCountRegister) - if s.onStack() { - s.setRegister(shiftCountRegister) - c.compileLoadValueOnStackToRegister(s) - } else if s.onConditionalRegister() { - c.compileMoveConditionalToGeneralPurposeRegister(s, shiftCountRegister) - } else { // already on register. - old := s.register - c.assembler.CompileRegisterToRegister(amd64.MOVL, old, shiftCountRegister) - s.setRegister(shiftCountRegister) - c.locationStack.markRegisterUnused(old) - } - } - - c.locationStack.markRegisterUsed(shiftCountRegister) - tmp, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - - x1 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x1); err != nil { - return err - } - - // Extract each lane into tmp, execute SHR on tmp, and write it back to the lane. - c.assembler.CompileRegisterToRegisterWithArg(amd64.PEXTRQ, x1.register, tmp, 0) - c.assembler.CompileRegisterToRegister(amd64.SARQ, shiftCountRegister, tmp) - c.assembler.CompileRegisterToRegisterWithArg(amd64.PINSRQ, tmp, x1.register, 0) - c.assembler.CompileRegisterToRegisterWithArg(amd64.PEXTRQ, x1.register, tmp, 1) - c.assembler.CompileRegisterToRegister(amd64.SARQ, shiftCountRegister, tmp) - c.assembler.CompileRegisterToRegisterWithArg(amd64.PINSRQ, tmp, x1.register, 1) - - c.locationStack.markRegisterUnused(shiftCountRegister) - c.pushVectorRuntimeValueLocationOnRegister(x1.register) - return nil -} - -// i8x16LogicalSHRMaskTable is necessary for emulating non-existent packed bytes logical right shifts on amd64. -// The mask is applied after performing packed word shifts on the value to clear out the unnecessary bits. -var i8x16LogicalSHRMaskTable = [8 * 16]byte{ // (the number of possible shift amount 0, 1, ..., 7.) * 16 bytes. - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, // for 0 shift - 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, // for 1 shift - 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, // for 2 shift - 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, // for 3 shift - 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, // for 4 shift - 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, // for 5 shift - 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, // for 6 shift - 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, // for 7 shift -} - -// compileV128ShrI64x2SignedImpl implements compiler.compileV128Shr for i8x16 signed logical/arithmetic shifts. -// amd64 doesn't have packed byte shifts, so we need this special casing. -// See https://stackoverflow.com/questions/35002937/sse-simd-shift-with-one-byte-element-size-granularity -func (c *amd64Compiler) compileV128ShrI8x16Impl(signed bool) error { - s := c.locationStack.pop() - if err := c.compileEnsureOnRegister(s); err != nil { - return err - } - - v := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(v); err != nil { - return err - } - - vecTmp, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - - gpShiftAmount := s.register - c.assembler.CompileConstToRegister(amd64.ANDQ, 0x7, gpShiftAmount) // mod 8. - - if signed { - c.locationStack.markRegisterUsed(vecTmp) - vecTmp2, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - - vreg := v.register - - // Copy the value from v.register to vecTmp. - c.assembler.CompileRegisterToRegister(amd64.MOVDQA, vreg, vecTmp) - - // Assuming that we have - // vreg = [b1, ..., b16] - // vecTmp = [b1, ..., b16] - // at this point, then we use PUNPCKLBW and PUNPCKHBW to produce: - // vreg = [b1, b1, b2, b2, ..., b8, b8] - // vecTmp = [b9, b9, b10, b10, ..., b16, b16] - c.assembler.CompileRegisterToRegister(amd64.PUNPCKLBW, vreg, vreg) - c.assembler.CompileRegisterToRegister(amd64.PUNPCKHBW, vecTmp, vecTmp) - - // Adding 8 to the shift amount, and then move the amount to vecTmp2. - c.assembler.CompileConstToRegister(amd64.ADDQ, 0x8, gpShiftAmount) - c.assembler.CompileRegisterToRegister(amd64.MOVL, gpShiftAmount, vecTmp2) - - // Perform the word packed arithmetic right shifts on vreg and vecTmp. - // This changes these two registers as: - // vreg = [xxx, b1 >> s, xxx, b2 >> s, ..., xxx, b8 >> s] - // vecTmp = [xxx, b9 >> s, xxx, b10 >> s, ..., xxx, b16 >> s] - // where xxx is 1 or 0 depending on each byte's sign, and ">>" is the arithmetic shift on a byte. - c.assembler.CompileRegisterToRegister(amd64.PSRAW, vecTmp2, vreg) - c.assembler.CompileRegisterToRegister(amd64.PSRAW, vecTmp2, vecTmp) - - // Finally, we can get the result by packing these two word vectors. - c.assembler.CompileRegisterToRegister(amd64.PACKSSWB, vecTmp, vreg) - - c.locationStack.markRegisterUnused(gpShiftAmount, vecTmp) - c.pushVectorRuntimeValueLocationOnRegister(vreg) - } else { - c.assembler.CompileRegisterToRegister(amd64.MOVL, gpShiftAmount, vecTmp) - // amd64 doesn't have packed byte shifts, so we packed word shift here, and then mark-out - // the unnecessary bits below. - c.assembler.CompileRegisterToRegister(amd64.PSRLW, vecTmp, v.register) - - gpTmp, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - - // Read the initial address of the mask table into gpTmp register. - err = c.assembler.CompileStaticConstToRegister(amd64.LEAQ, asm.NewStaticConst(i8x16LogicalSHRMaskTable[:]), gpTmp) - if err != nil { - return err - } - - // We have to get the mask according to the shift amount, so we first have to do - // gpShiftAmount << 4 = gpShiftAmount*16 to get the initial offset of the mask (16 is the size of each mask in bytes). - c.assembler.CompileConstToRegister(amd64.SHLQ, 4, gpShiftAmount) - - // Now ready to read the content of the mask into the vecTmp. - c.assembler.CompileMemoryWithIndexToRegister(amd64.MOVDQU, - gpTmp, 0, gpShiftAmount, 1, - vecTmp, - ) - - // Finally, clear out the unnecessary - c.assembler.CompileRegisterToRegister(amd64.PAND, vecTmp, v.register) - - c.locationStack.markRegisterUnused(gpShiftAmount) - c.pushVectorRuntimeValueLocationOnRegister(v.register) - } - return nil -} - -// i8x16SHLMaskTable is necessary for emulating non-existent packed bytes left shifts on amd64. -// The mask is applied after performing packed word shifts on the value to clear out the unnecessary bits. -var i8x16SHLMaskTable = [8 * 16]byte{ // (the number of possible shift amount 0, 1, ..., 7.) * 16 bytes. - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, // for 0 shift - 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, // for 1 shift - 0xfc, 0xfc, 0xfc, 0xfc, 0xfc, 0xfc, 0xfc, 0xfc, 0xfc, 0xfc, 0xfc, 0xfc, 0xfc, 0xfc, 0xfc, 0xfc, // for 2 shift - 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, // for 3 shift - 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, // for 4 shift - 0xe0, 0xe0, 0xe0, 0xe0, 0xe0, 0xe0, 0xe0, 0xe0, 0xe0, 0xe0, 0xe0, 0xe0, 0xe0, 0xe0, 0xe0, 0xe0, // for 5 shift - 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, // for 6 shift - 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, // for 7 shift -} - -// compileV128Shl implements compiler.compileV128Shl for amd64. -func (c *amd64Compiler) compileV128Shl(o *wazeroir.UnionOperation) error { - s := c.locationStack.pop() - if err := c.compileEnsureOnRegister(s); err != nil { - return err - } - - x1 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x1); err != nil { - return err - } - - vecTmp, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - - var modulo int64 - var shift asm.Instruction - shape := o.B1 - switch shape { - case wazeroir.ShapeI8x16: - modulo = 0x7 // modulo 8. - // x86 doesn't have packed bytes shift, so we use PSLLW and mask-out the redundant bits. - // See https://stackoverflow.com/questions/35002937/sse-simd-shift-with-one-byte-element-size-granularity - shift = amd64.PSLLW - case wazeroir.ShapeI16x8: - modulo = 0xf // modulo 16. - shift = amd64.PSLLW - case wazeroir.ShapeI32x4: - modulo = 0x1f // modulo 32. - shift = amd64.PSLLD - case wazeroir.ShapeI64x2: - modulo = 0x3f // modulo 64. - shift = amd64.PSLLQ - } - - gpShiftAmount := s.register - c.assembler.CompileConstToRegister(amd64.ANDQ, modulo, gpShiftAmount) - c.assembler.CompileRegisterToRegister(amd64.MOVL, gpShiftAmount, vecTmp) - c.assembler.CompileRegisterToRegister(shift, vecTmp, x1.register) - - if shape == wazeroir.ShapeI8x16 { - gpTmp, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - - // Read the initial address of the mask table into gpTmp register. - err = c.assembler.CompileStaticConstToRegister(amd64.LEAQ, asm.NewStaticConst(i8x16SHLMaskTable[:]), gpTmp) - if err != nil { - return err - } - - // We have to get the mask according to the shift amount, so we first have to do - // gpShiftAmount << 4 = gpShiftAmount*16 to get the initial offset of the mask (16 is the size of each mask in bytes). - c.assembler.CompileConstToRegister(amd64.SHLQ, 4, gpShiftAmount) - - // Now ready to read the content of the mask into the vecTmp. - c.assembler.CompileMemoryWithIndexToRegister(amd64.MOVDQU, - gpTmp, 0, gpShiftAmount, 1, - vecTmp, - ) - - // Finally, clear out the unnecessary - c.assembler.CompileRegisterToRegister(amd64.PAND, vecTmp, x1.register) - } - - c.locationStack.markRegisterUnused(gpShiftAmount) - c.pushVectorRuntimeValueLocationOnRegister(x1.register) - return nil -} - -// compileV128Cmp implements compiler.compileV128Cmp for amd64. -func (c *amd64Compiler) compileV128Cmp(o *wazeroir.UnionOperation) error { - x2 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x2); err != nil { - return err - } - - x1 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x1); err != nil { - return err - } - - const ( - // See https://www.felixcloutier.com/x86/cmppd and https://www.felixcloutier.com/x86/cmpps - floatEqualArg = 0 - floatLessThanArg = 1 - floatLessThanOrEqualArg = 2 - floatNotEqualARg = 4 - ) - - x1Reg, x2Reg, result := x1.register, x2.register, asm.NilRegister - v128CmpType := o.B1 - switch v128CmpType { - case wazeroir.V128CmpTypeF32x4Eq: - c.assembler.CompileRegisterToRegisterWithArg(amd64.CMPPS, x2Reg, x1Reg, floatEqualArg) - result = x1Reg - case wazeroir.V128CmpTypeF32x4Ne: - c.assembler.CompileRegisterToRegisterWithArg(amd64.CMPPS, x2Reg, x1Reg, floatNotEqualARg) - result = x1Reg - case wazeroir.V128CmpTypeF32x4Lt: - c.assembler.CompileRegisterToRegisterWithArg(amd64.CMPPS, x2Reg, x1Reg, floatLessThanArg) - result = x1Reg - case wazeroir.V128CmpTypeF32x4Gt: - // Without AVX, there's no float Gt instruction, so we swap the register and use Lt instead. - c.assembler.CompileRegisterToRegisterWithArg(amd64.CMPPS, x1Reg, x2Reg, floatLessThanArg) - result = x2Reg - case wazeroir.V128CmpTypeF32x4Le: - c.assembler.CompileRegisterToRegisterWithArg(amd64.CMPPS, x2Reg, x1Reg, floatLessThanOrEqualArg) - result = x1Reg - case wazeroir.V128CmpTypeF32x4Ge: - // Without AVX, there's no float Ge instruction, so we swap the register and use Le instead. - c.assembler.CompileRegisterToRegisterWithArg(amd64.CMPPS, x1Reg, x2Reg, floatLessThanOrEqualArg) - result = x2Reg - case wazeroir.V128CmpTypeF64x2Eq: - c.assembler.CompileRegisterToRegisterWithArg(amd64.CMPPD, x2Reg, x1Reg, floatEqualArg) - result = x1Reg - case wazeroir.V128CmpTypeF64x2Ne: - c.assembler.CompileRegisterToRegisterWithArg(amd64.CMPPD, x2Reg, x1Reg, floatNotEqualARg) - result = x1Reg - case wazeroir.V128CmpTypeF64x2Lt: - c.assembler.CompileRegisterToRegisterWithArg(amd64.CMPPD, x2Reg, x1Reg, floatLessThanArg) - result = x1Reg - case wazeroir.V128CmpTypeF64x2Gt: - // Without AVX, there's no float Gt instruction, so we swap the register and use Lt instead. - c.assembler.CompileRegisterToRegisterWithArg(amd64.CMPPD, x1Reg, x2Reg, floatLessThanArg) - result = x2Reg - case wazeroir.V128CmpTypeF64x2Le: - c.assembler.CompileRegisterToRegisterWithArg(amd64.CMPPD, x2Reg, x1Reg, floatLessThanOrEqualArg) - result = x1Reg - case wazeroir.V128CmpTypeF64x2Ge: - // Without AVX, there's no float Ge instruction, so we swap the register and use Le instead. - c.assembler.CompileRegisterToRegisterWithArg(amd64.CMPPD, x1Reg, x2Reg, floatLessThanOrEqualArg) - result = x2Reg - case wazeroir.V128CmpTypeI8x16Eq: - c.assembler.CompileRegisterToRegister(amd64.PCMPEQB, x2Reg, x1Reg) - result = x1Reg - case wazeroir.V128CmpTypeI8x16Ne: - c.assembler.CompileRegisterToRegister(amd64.PCMPEQB, x2Reg, x1Reg) - // Set all bits on x2Reg register. - c.assembler.CompileRegisterToRegister(amd64.PCMPEQD, x2Reg, x2Reg) - // Swap the bits on x1Reg register. - c.assembler.CompileRegisterToRegister(amd64.PXOR, x2Reg, x1Reg) - result = x1Reg - case wazeroir.V128CmpTypeI8x16LtS: - c.assembler.CompileRegisterToRegister(amd64.PCMPGTB, x1Reg, x2Reg) - result = x2Reg - case wazeroir.V128CmpTypeI8x16LtU, wazeroir.V128CmpTypeI8x16GtU: - // Take the unsigned min/max values on each byte on x1 and x2 onto x1Reg. - if v128CmpType == wazeroir.V128CmpTypeI8x16LtU { - c.assembler.CompileRegisterToRegister(amd64.PMINUB, x2Reg, x1Reg) - } else { - c.assembler.CompileRegisterToRegister(amd64.PMAXUB, x2Reg, x1Reg) - } - c.assembler.CompileRegisterToRegister(amd64.PCMPEQB, x2Reg, x1Reg) - // Set all bits on x2Reg register. - c.assembler.CompileRegisterToRegister(amd64.PCMPEQD, x2Reg, x2Reg) - // Swap the bits on x2Reg register. - c.assembler.CompileRegisterToRegister(amd64.PXOR, x2Reg, x1Reg) - result = x1Reg - case wazeroir.V128CmpTypeI8x16GtS: - c.assembler.CompileRegisterToRegister(amd64.PCMPGTB, x2Reg, x1Reg) - result = x1Reg - case wazeroir.V128CmpTypeI8x16LeS, wazeroir.V128CmpTypeI8x16LeU: - tmp, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - // Copy the value on the src to tmp. - c.assembler.CompileRegisterToRegister(amd64.MOVDQA, x1Reg, tmp) - if v128CmpType == wazeroir.V128CmpTypeI8x16LeS { - c.assembler.CompileRegisterToRegister(amd64.PMINSB, x2Reg, tmp) - } else { - c.assembler.CompileRegisterToRegister(amd64.PMINUB, x2Reg, tmp) - } - c.assembler.CompileRegisterToRegister(amd64.PCMPEQB, tmp, x1Reg) - result = x1Reg - case wazeroir.V128CmpTypeI8x16GeS, wazeroir.V128CmpTypeI8x16GeU: - tmp, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - c.assembler.CompileRegisterToRegister(amd64.MOVDQA, x1Reg, tmp) - if v128CmpType == wazeroir.V128CmpTypeI8x16GeS { - c.assembler.CompileRegisterToRegister(amd64.PMAXSB, x2Reg, tmp) - } else { - c.assembler.CompileRegisterToRegister(amd64.PMAXUB, x2Reg, tmp) - } - c.assembler.CompileRegisterToRegister(amd64.PCMPEQB, tmp, x1Reg) - result = x1Reg - case wazeroir.V128CmpTypeI16x8Eq: - c.assembler.CompileRegisterToRegister(amd64.PCMPEQW, x2Reg, x1Reg) - result = x1Reg - case wazeroir.V128CmpTypeI16x8Ne: - c.assembler.CompileRegisterToRegister(amd64.PCMPEQW, x2Reg, x1Reg) - // Set all bits on x2Reg register. - c.assembler.CompileRegisterToRegister(amd64.PCMPEQD, x2Reg, x2Reg) - // Swap the bits on x1Reg register. - c.assembler.CompileRegisterToRegister(amd64.PXOR, x2Reg, x1Reg) - result = x1Reg - case wazeroir.V128CmpTypeI16x8LtS: - c.assembler.CompileRegisterToRegister(amd64.PCMPGTW, x1Reg, x2Reg) - result = x2Reg - case wazeroir.V128CmpTypeI16x8LtU, wazeroir.V128CmpTypeI16x8GtU: - // Take the unsigned min/max values on each byte on x1 and x2 onto x1Reg. - if v128CmpType == wazeroir.V128CmpTypeI16x8LtU { - c.assembler.CompileRegisterToRegister(amd64.PMINUW, x2Reg, x1Reg) - } else { - c.assembler.CompileRegisterToRegister(amd64.PMAXUW, x2Reg, x1Reg) - } - c.assembler.CompileRegisterToRegister(amd64.PCMPEQW, x2Reg, x1Reg) - // Set all bits on x2Reg register. - c.assembler.CompileRegisterToRegister(amd64.PCMPEQD, x2Reg, x2Reg) - // Swap the bits on x2Reg register. - c.assembler.CompileRegisterToRegister(amd64.PXOR, x2Reg, x1Reg) - result = x1Reg - case wazeroir.V128CmpTypeI16x8GtS: - c.assembler.CompileRegisterToRegister(amd64.PCMPGTW, x2Reg, x1Reg) - result = x1Reg - case wazeroir.V128CmpTypeI16x8LeS, wazeroir.V128CmpTypeI16x8LeU: - tmp, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - // Copy the value on the src to tmp. - c.assembler.CompileRegisterToRegister(amd64.MOVDQA, x1Reg, tmp) - if v128CmpType == wazeroir.V128CmpTypeI16x8LeS { - c.assembler.CompileRegisterToRegister(amd64.PMINSW, x2Reg, tmp) - } else { - c.assembler.CompileRegisterToRegister(amd64.PMINUW, x2Reg, tmp) - } - c.assembler.CompileRegisterToRegister(amd64.PCMPEQW, tmp, x1Reg) - result = x1Reg - case wazeroir.V128CmpTypeI16x8GeS, wazeroir.V128CmpTypeI16x8GeU: - tmp, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - c.assembler.CompileRegisterToRegister(amd64.MOVDQA, x1Reg, tmp) - if v128CmpType == wazeroir.V128CmpTypeI16x8GeS { - c.assembler.CompileRegisterToRegister(amd64.PMAXSW, x2Reg, tmp) - } else { - c.assembler.CompileRegisterToRegister(amd64.PMAXUW, x2Reg, tmp) - } - c.assembler.CompileRegisterToRegister(amd64.PCMPEQW, tmp, x1Reg) - result = x1Reg - case wazeroir.V128CmpTypeI32x4Eq: - c.assembler.CompileRegisterToRegister(amd64.PCMPEQD, x2Reg, x1Reg) - result = x1Reg - case wazeroir.V128CmpTypeI32x4Ne: - c.assembler.CompileRegisterToRegister(amd64.PCMPEQD, x2Reg, x1Reg) - // Set all bits on x2Reg register. - c.assembler.CompileRegisterToRegister(amd64.PCMPEQD, x2Reg, x2Reg) - // Swap the bits on x1Reg register. - c.assembler.CompileRegisterToRegister(amd64.PXOR, x2Reg, x1Reg) - result = x1Reg - case wazeroir.V128CmpTypeI32x4LtS: - c.assembler.CompileRegisterToRegister(amd64.PCMPGTD, x1Reg, x2Reg) - result = x2Reg - case wazeroir.V128CmpTypeI32x4LtU, wazeroir.V128CmpTypeI32x4GtU: - // Take the unsigned min/max values on each byte on x1 and x2 onto x1Reg. - if v128CmpType == wazeroir.V128CmpTypeI32x4LtU { - c.assembler.CompileRegisterToRegister(amd64.PMINUD, x2Reg, x1Reg) - } else { - c.assembler.CompileRegisterToRegister(amd64.PMAXUD, x2Reg, x1Reg) - } - c.assembler.CompileRegisterToRegister(amd64.PCMPEQD, x2Reg, x1Reg) - // Set all bits on x2Reg register. - c.assembler.CompileRegisterToRegister(amd64.PCMPEQD, x2Reg, x2Reg) - // Swap the bits on x2Reg register. - c.assembler.CompileRegisterToRegister(amd64.PXOR, x2Reg, x1Reg) - result = x1Reg - case wazeroir.V128CmpTypeI32x4GtS: - c.assembler.CompileRegisterToRegister(amd64.PCMPGTD, x2Reg, x1Reg) - result = x1Reg - case wazeroir.V128CmpTypeI32x4LeS, wazeroir.V128CmpTypeI32x4LeU: - tmp, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - // Copy the value on the src to tmp. - c.assembler.CompileRegisterToRegister(amd64.MOVDQA, x1Reg, tmp) - if v128CmpType == wazeroir.V128CmpTypeI32x4LeS { - c.assembler.CompileRegisterToRegister(amd64.PMINSD, x2Reg, tmp) - } else { - c.assembler.CompileRegisterToRegister(amd64.PMINUD, x2Reg, tmp) - } - c.assembler.CompileRegisterToRegister(amd64.PCMPEQD, tmp, x1Reg) - result = x1Reg - case wazeroir.V128CmpTypeI32x4GeS, wazeroir.V128CmpTypeI32x4GeU: - tmp, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - c.assembler.CompileRegisterToRegister(amd64.MOVDQA, x1Reg, tmp) - if v128CmpType == wazeroir.V128CmpTypeI32x4GeS { - c.assembler.CompileRegisterToRegister(amd64.PMAXSD, x2Reg, tmp) - } else { - c.assembler.CompileRegisterToRegister(amd64.PMAXUD, x2Reg, tmp) - } - c.assembler.CompileRegisterToRegister(amd64.PCMPEQD, tmp, x1Reg) - result = x1Reg - case wazeroir.V128CmpTypeI64x2Eq: - c.assembler.CompileRegisterToRegister(amd64.PCMPEQQ, x2Reg, x1Reg) - result = x1Reg - case wazeroir.V128CmpTypeI64x2Ne: - c.assembler.CompileRegisterToRegister(amd64.PCMPEQQ, x2Reg, x1Reg) - // Set all bits on x2Reg register. - c.assembler.CompileRegisterToRegister(amd64.PCMPEQD, x2Reg, x2Reg) - // Swap the bits on x1Reg register. - c.assembler.CompileRegisterToRegister(amd64.PXOR, x2Reg, x1Reg) - result = x1Reg - case wazeroir.V128CmpTypeI64x2LtS: - c.assembler.CompileRegisterToRegister(amd64.PCMPGTQ, x1Reg, x2Reg) - result = x2Reg - case wazeroir.V128CmpTypeI64x2GtS: - c.assembler.CompileRegisterToRegister(amd64.PCMPGTQ, x2Reg, x1Reg) - result = x1Reg - case wazeroir.V128CmpTypeI64x2LeS: - c.assembler.CompileRegisterToRegister(amd64.PCMPGTQ, x2Reg, x1Reg) - // Set all bits on x2Reg register. - c.assembler.CompileRegisterToRegister(amd64.PCMPEQD, x2Reg, x2Reg) - // Swap the bits on x1Reg register. - c.assembler.CompileRegisterToRegister(amd64.PXOR, x2Reg, x1Reg) - result = x1Reg - case wazeroir.V128CmpTypeI64x2GeS: - c.assembler.CompileRegisterToRegister(amd64.PCMPGTQ, x1Reg, x2Reg) - // Set all bits on x1Reg register. - c.assembler.CompileRegisterToRegister(amd64.PCMPEQD, x1Reg, x1Reg) - // Swap the bits on x2Reg register. - c.assembler.CompileRegisterToRegister(amd64.PXOR, x1Reg, x2Reg) - result = x2Reg - } - - c.locationStack.markRegisterUnused(x1Reg, x2Reg) - c.pushVectorRuntimeValueLocationOnRegister(result) - return nil -} - -// compileV128AddSat implements compiler.compileV128AddSat for amd64. -func (c *amd64Compiler) compileV128AddSat(o *wazeroir.UnionOperation) error { - var inst asm.Instruction - shape := o.B1 - signed := o.B3 - switch shape { - case wazeroir.ShapeI8x16: - if signed { - inst = amd64.PADDSB - } else { - inst = amd64.PADDUSB - } - case wazeroir.ShapeI16x8: - if signed { - inst = amd64.PADDSW - } else { - inst = amd64.PADDUSW - } - } - - x2 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x2); err != nil { - return err - } - - x1 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x1); err != nil { - return err - } - - c.assembler.CompileRegisterToRegister(inst, x2.register, x1.register) - - c.locationStack.markRegisterUnused(x2.register) - c.pushVectorRuntimeValueLocationOnRegister(x1.register) - return nil -} - -// compileV128SubSat implements compiler.compileV128SubSat for amd64. -func (c *amd64Compiler) compileV128SubSat(o *wazeroir.UnionOperation) error { - var inst asm.Instruction - shape := o.B1 - signed := o.B3 - switch shape { - case wazeroir.ShapeI8x16: - if signed { - inst = amd64.PSUBSB - } else { - inst = amd64.PSUBUSB - } - case wazeroir.ShapeI16x8: - if signed { - inst = amd64.PSUBSW - } else { - inst = amd64.PSUBUSW - } - } - - x2 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x2); err != nil { - return err - } - - x1 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x1); err != nil { - return err - } - - c.assembler.CompileRegisterToRegister(inst, x2.register, x1.register) - - c.locationStack.markRegisterUnused(x2.register) - c.pushVectorRuntimeValueLocationOnRegister(x1.register) - return nil -} - -// compileV128Mul implements compiler.compileV128Mul for amd64. -func (c *amd64Compiler) compileV128Mul(o *wazeroir.UnionOperation) error { - var inst asm.Instruction - shape := o.B1 - switch shape { - case wazeroir.ShapeI16x8: - inst = amd64.PMULLW - case wazeroir.ShapeI32x4: - inst = amd64.PMULLD - case wazeroir.ShapeI64x2: - return c.compileV128MulI64x2() - case wazeroir.ShapeF32x4: - inst = amd64.MULPS - case wazeroir.ShapeF64x2: - inst = amd64.MULPD - } - - x2 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x2); err != nil { - return err - } - - x1 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x1); err != nil { - return err - } - - c.assembler.CompileRegisterToRegister(inst, x2.register, x1.register) - - c.locationStack.markRegisterUnused(x2.register) - c.pushVectorRuntimeValueLocationOnRegister(x1.register) - return nil -} - -// compileV128MulI64x2 implements V128Mul for i64x2. -func (c *amd64Compiler) compileV128MulI64x2() error { - x2 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x2); err != nil { - return err - } - - x1 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x1); err != nil { - return err - } - - x1r, x2r := x1.register, x2.register - - tmp1, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - - c.locationStack.markRegisterUsed(tmp1) - - tmp2, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - - // Assuming that we have - // x1r = [p1, p2] = [p1_lo, p1_hi, p2_lo, p2_high] - // x2r = [q1, q2] = [q1_lo, q1_hi, q2_lo, q2_high] - // where pN and qN are 64-bit (quad word) lane, and pN_lo, pN_hi, qN_lo and qN_hi are 32-bit (double word) lane. - - // Copy x1's value into tmp1. - c.assembler.CompileRegisterToRegister(amd64.MOVDQA, x1r, tmp1) - // And do the logical right shift by 32-bit on tmp1, which makes tmp1 = [0, p1_high, 0, p2_high] - c.assembler.CompileConstToRegister(amd64.PSRLQ, 32, tmp1) - - // Execute "pmuludq x2r,tmp1", which makes tmp1 = [p1_high*q1_lo, p2_high*q2_lo] where each lane is 64-bit. - c.assembler.CompileRegisterToRegister(amd64.PMULUDQ, x2r, tmp1) - - // Copy x2's value into tmp2. - c.assembler.CompileRegisterToRegister(amd64.MOVDQA, x2r, tmp2) - // And do the logical right shift by 32-bit on tmp2, which makes tmp2 = [0, q1_high, 0, q2_high] - c.assembler.CompileConstToRegister(amd64.PSRLQ, 32, tmp2) - - // Execute "pmuludq x1r,tmp2", which makes tmp2 = [p1_lo*q1_high, p2_lo*q2_high] where each lane is 64-bit. - c.assembler.CompileRegisterToRegister(amd64.PMULUDQ, x1r, tmp2) - - // Adds tmp1 and tmp2 and do the logical left shift by 32-bit, - // which makes tmp1 = [(p1_lo*q1_high+p1_high*q1_lo)<<32, (p2_lo*q2_high+p2_high*q2_lo)<<32] - c.assembler.CompileRegisterToRegister(amd64.PADDQ, tmp2, tmp1) - c.assembler.CompileConstToRegister(amd64.PSLLQ, 32, tmp1) - - // Execute "pmuludq x2r,x1r", which makes x1r = [p1_lo*q1_lo, p2_lo*q2_lo] where each lane is 64-bit. - c.assembler.CompileRegisterToRegister(amd64.PMULUDQ, x2r, x1r) - - // Finally, we get the result by adding x1r and tmp1, - // which makes x1r = [(p1_lo*q1_high+p1_high*q1_lo)<<32+p1_lo*q1_lo, (p2_lo*q2_high+p2_high*q2_lo)<<32+p2_lo*q2_lo] - c.assembler.CompileRegisterToRegister(amd64.PADDQ, tmp1, x1r) - - c.locationStack.markRegisterUnused(x2r, tmp1) - c.pushVectorRuntimeValueLocationOnRegister(x1r) - return nil -} - -// compileV128Div implements compiler.compileV128Div for amd64. -func (c *amd64Compiler) compileV128Div(o *wazeroir.UnionOperation) error { - x2 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x2); err != nil { - return err - } - - x1 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x1); err != nil { - return err - } - - var inst asm.Instruction - shape := o.B1 - switch shape { - case wazeroir.ShapeF32x4: - inst = amd64.DIVPS - case wazeroir.ShapeF64x2: - inst = amd64.DIVPD - } - - c.assembler.CompileRegisterToRegister(inst, x2.register, x1.register) - - c.locationStack.markRegisterUnused(x2.register) - c.pushVectorRuntimeValueLocationOnRegister(x1.register) - return nil -} - -// compileV128Neg implements compiler.compileV128Neg for amd64. -func (c *amd64Compiler) compileV128Neg(o *wazeroir.UnionOperation) error { - shape := o.B1 - if shape <= wazeroir.ShapeI64x2 { - return c.compileV128NegInt(shape) - } else { - return c.compileV128NegFloat(shape) - } -} - -// compileV128NegInt implements compiler.compileV128Neg for integer lanes. -func (c *amd64Compiler) compileV128NegInt(s wazeroir.Shape) error { - v := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(v); err != nil { - return err - } - - result, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - - var subInst asm.Instruction - switch s { - case wazeroir.ShapeI8x16: - subInst = amd64.PSUBB - case wazeroir.ShapeI16x8: - subInst = amd64.PSUBW - case wazeroir.ShapeI32x4: - subInst = amd64.PSUBD - case wazeroir.ShapeI64x2: - subInst = amd64.PSUBQ - } - - c.assembler.CompileRegisterToRegister(amd64.PXOR, result, result) - c.assembler.CompileRegisterToRegister(subInst, v.register, result) - - c.locationStack.markRegisterUnused(v.register) - c.pushVectorRuntimeValueLocationOnRegister(result) - return nil -} - -// compileV128NegInt implements compiler.compileV128Neg for float lanes. -func (c *amd64Compiler) compileV128NegFloat(s wazeroir.Shape) error { - v := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(v); err != nil { - return err - } - - tmp, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - - var leftShiftInst, xorInst asm.Instruction - var leftShiftAmount asm.ConstantValue - if s == wazeroir.ShapeF32x4 { - leftShiftInst, leftShiftAmount, xorInst = amd64.PSLLD, 31, amd64.XORPS - } else { - leftShiftInst, leftShiftAmount, xorInst = amd64.PSLLQ, 63, amd64.XORPD - } - - // Clear all bits on tmp. - c.assembler.CompileRegisterToRegister(amd64.XORPS, tmp, tmp) - // Set all bits on tmp by CMPPD with arg=0 (== pseudo CMPEQPD instruction). - // See https://www.felixcloutier.com/x86/cmpps - // - // Note: if we do not clear all the bits ^ with XORPS, this might end up not setting ones on some lane - // if the lane is NaN. - c.assembler.CompileRegisterToRegisterWithArg(amd64.CMPPD, tmp, tmp, 0x8) - // Do the left shift on each lane to set only the most significant bit in each. - c.assembler.CompileConstToRegister(leftShiftInst, leftShiftAmount, tmp) - // Get the negated result by XOR on each lane with tmp. - c.assembler.CompileRegisterToRegister(xorInst, tmp, v.register) - - c.pushVectorRuntimeValueLocationOnRegister(v.register) - return nil -} - -// compileV128Sqrt implements compiler.compileV128Sqrt for amd64. -func (c *amd64Compiler) compileV128Sqrt(o *wazeroir.UnionOperation) error { - v := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(v); err != nil { - return err - } - - var inst asm.Instruction - shape := o.B1 - switch shape { - case wazeroir.ShapeF64x2: - inst = amd64.SQRTPD - case wazeroir.ShapeF32x4: - inst = amd64.SQRTPS - } - - c.assembler.CompileRegisterToRegister(inst, v.register, v.register) - c.pushVectorRuntimeValueLocationOnRegister(v.register) - return nil -} - -// compileV128Abs implements compiler.compileV128Abs for amd64. -func (c *amd64Compiler) compileV128Abs(o *wazeroir.UnionOperation) error { - shape := o.B1 - if shape == wazeroir.ShapeI64x2 { - return c.compileV128AbsI64x2() - } - - v := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(v); err != nil { - return err - } - - result := v.register - switch shape { - case wazeroir.ShapeI8x16: - c.assembler.CompileRegisterToRegister(amd64.PABSB, result, result) - case wazeroir.ShapeI16x8: - c.assembler.CompileRegisterToRegister(amd64.PABSW, result, result) - case wazeroir.ShapeI32x4: - c.assembler.CompileRegisterToRegister(amd64.PABSD, result, result) - case wazeroir.ShapeF32x4: - tmp, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - // Set all bits on tmp. - c.assembler.CompileRegisterToRegister(amd64.PCMPEQD, tmp, tmp) - // Shift right packed single floats by 1 to clear the sign bits. - c.assembler.CompileConstToRegister(amd64.PSRLD, 1, tmp) - // Clear the sign bit of vr. - c.assembler.CompileRegisterToRegister(amd64.ANDPS, tmp, result) - case wazeroir.ShapeF64x2: - tmp, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - // Set all bits on tmp. - c.assembler.CompileRegisterToRegister(amd64.PCMPEQD, tmp, tmp) - // Shift right packed single floats by 1 to clear the sign bits. - c.assembler.CompileConstToRegister(amd64.PSRLQ, 1, tmp) - // Clear the sign bit of vr. - c.assembler.CompileRegisterToRegister(amd64.ANDPD, tmp, result) - } - - c.pushVectorRuntimeValueLocationOnRegister(result) - return nil -} - -// compileV128AbsI64x2 implements compileV128Abs for i64x2 lanes. -func (c *amd64Compiler) compileV128AbsI64x2() error { - // See https://www.felixcloutier.com/x86/blendvpd - const blendMaskReg = amd64.RegX0 - c.onValueReleaseRegisterToStack(blendMaskReg) - c.locationStack.markRegisterUsed(blendMaskReg) - - v := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(v); err != nil { - return err - } - vr := v.register - - if vr == blendMaskReg { - return errors.New("BUG: X0 must not be used") - } - - tmp, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - c.locationStack.markRegisterUsed(tmp) - - // Copy the value to tmp. - c.assembler.CompileRegisterToRegister(amd64.MOVDQA, vr, tmp) - - // Clear all bits on blendMaskReg. - c.assembler.CompileRegisterToRegister(amd64.PXOR, blendMaskReg, blendMaskReg) - // Subtract vr from blendMaskReg. - c.assembler.CompileRegisterToRegister(amd64.PSUBQ, vr, blendMaskReg) - // Copy the subtracted value ^^ back into vr. - c.assembler.CompileRegisterToRegister(amd64.MOVDQA, blendMaskReg, vr) - - c.assembler.CompileRegisterToRegister(amd64.BLENDVPD, tmp, vr) - - c.locationStack.markRegisterUnused(blendMaskReg, tmp) - c.pushVectorRuntimeValueLocationOnRegister(vr) - return nil -} - -var ( - popcntMask = [16]byte{ - 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, - 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, - } - // popcntTable holds each index's Popcnt, for example popcntTable[5] holds popcnt(0x05). - popcntTable = [16]byte{ - 0x00, 0x01, 0x01, 0x02, 0x01, 0x02, 0x02, 0x03, - 0x01, 0x02, 0x02, 0x03, 0x02, 0x03, 0x03, 0x04, - } -) - -// compileV128Popcnt implements compiler.compileV128Popcnt for amd64. -func (c *amd64Compiler) compileV128Popcnt(operation *wazeroir.UnionOperation) error { - v := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(v); err != nil { - return err - } - vr := v.register - - tmp1, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - - c.locationStack.markRegisterUsed(tmp1) - - tmp2, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - - c.locationStack.markRegisterUsed(tmp2) - - tmp3, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - - // Read the popcntMask into tmp1, and we have - // tmp1 = [0xf, ..., 0xf] - if err := c.assembler.CompileStaticConstToRegister(amd64.MOVDQU, asm.NewStaticConst(popcntMask[:]), tmp1); err != nil { - return err - } - - // Copy the original value into tmp2. - c.assembler.CompileRegisterToRegister(amd64.MOVDQA, vr, tmp2) - - // Given that we have: - // v = [b1, ..., b16] where bn = hn:ln and hn and ln are higher and lower 4-bits of bn. - // - // Take PAND on tmp1 and tmp2, and we have - // tmp2 = [l1, ..., l16]. - c.assembler.CompileRegisterToRegister(amd64.PAND, tmp1, tmp2) - - // Do logical (packed word) right shift by 4 on vr and PAND with vr and tmp1, meaning that we have - // vr = [h1, ...., h16]. - c.assembler.CompileConstToRegister(amd64.PSRLW, 4, vr) - c.assembler.CompileRegisterToRegister(amd64.PAND, tmp1, vr) - - // Read the popcntTable into tmp1, and we have - // tmp1 = [0x00, 0x01, 0x01, 0x02, 0x01, 0x02, 0x02, 0x03, 0x01, 0x02, 0x02, 0x03, 0x02, 0x03, 0x03, 0x04] - if err := c.assembler.CompileStaticConstToRegister(amd64.MOVDQU, asm.NewStaticConst(popcntTable[:]), tmp1); err != nil { - return err - } - - // Copy the tmp1 into tmp3, and we have - // tmp3 = [0x00, 0x01, 0x01, 0x02, 0x01, 0x02, 0x02, 0x03, 0x01, 0x02, 0x02, 0x03, 0x02, 0x03, 0x03, 0x04] - c.assembler.CompileRegisterToRegister(amd64.MOVDQU, tmp1, tmp3) - - // tmp3 = [popcnt(l1), ..., popcnt(l16)]. - c.assembler.CompileRegisterToRegister(amd64.PSHUFB, tmp2, tmp3) - - // tmp1 = [popcnt(h1), ..., popcnt(h16)]. - c.assembler.CompileRegisterToRegister(amd64.PSHUFB, vr, tmp1) - - // vr = tmp1 = [popcnt(h1), ..., popcnt(h16)]. - c.assembler.CompileRegisterToRegister(amd64.MOVDQA, tmp1, vr) - - // vr += tmp3 = [popcnt(h1)+popcnt(l1), ..., popcnt(h16)+popcnt(l16)] = [popcnt(b1), ..., popcnt(b16)]. - c.assembler.CompileRegisterToRegister(amd64.PADDB, tmp3, vr) - - c.locationStack.markRegisterUnused(tmp1, tmp2) - c.pushVectorRuntimeValueLocationOnRegister(vr) - return nil -} - -// compileV128Min implements compiler.compileV128Min for amd64. -func (c *amd64Compiler) compileV128Min(o *wazeroir.UnionOperation) error { - x2 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x2); err != nil { - return err - } - - x1 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x1); err != nil { - return err - } - - shape := o.B1 - if shape >= wazeroir.ShapeF32x4 { - return c.compileV128FloatMinImpl(shape == wazeroir.ShapeF32x4, x1.register, x2.register) - } - - signed := o.B3 - var inst asm.Instruction - switch shape { - case wazeroir.ShapeI8x16: - if signed { - inst = amd64.PMINSB - } else { - inst = amd64.PMINUB - } - case wazeroir.ShapeI16x8: - if signed { - inst = amd64.PMINSW - } else { - inst = amd64.PMINUW - } - case wazeroir.ShapeI32x4: - if signed { - inst = amd64.PMINSD - } else { - inst = amd64.PMINUD - } - } - - c.assembler.CompileRegisterToRegister(inst, x2.register, x1.register) - - c.locationStack.markRegisterUnused(x2.register) - c.pushVectorRuntimeValueLocationOnRegister(x1.register) - return nil -} - -// compileV128FloatMinImpl implements compiler.compileV128Min for float lanes. -func (c *amd64Compiler) compileV128FloatMinImpl(is32bit bool, x1r, x2r asm.Register) error { - tmp, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - - var min, cmp, andn, or, srl /* shit right logical */ asm.Instruction - var shiftNumToInverseNaN asm.ConstantValue - if is32bit { - min, cmp, andn, or, srl, shiftNumToInverseNaN = amd64.MINPS, amd64.CMPPS, amd64.ANDNPS, amd64.ORPS, amd64.PSRLD, 0xa - } else { - min, cmp, andn, or, srl, shiftNumToInverseNaN = amd64.MINPD, amd64.CMPPD, amd64.ANDNPD, amd64.ORPD, amd64.PSRLQ, 0xd - } - - // Let v1 and v2 be the operand values on x1r and x2r at this point. - - // Copy the value into tmp: tmp=v1 - c.assembler.CompileRegisterToRegister(amd64.MOVDQA, x1r, tmp) - // tmp=min(v1, v2) - c.assembler.CompileRegisterToRegister(min, x2r, tmp) - // x2r=min(v2, v1) - c.assembler.CompileRegisterToRegister(min, x1r, x2r) - // x1r=min(v2, v1) - c.assembler.CompileRegisterToRegister(amd64.MOVDQA, x2r, x1r) - - // x2r = -0 if (v1 == -0 || x2 == -0) && v1 != NaN && v2 !=NaN - // NaN if v1 == NaN || v2 == NaN - // min(v1, v2) otherwise - c.assembler.CompileRegisterToRegister(or, tmp, x2r) - // x1r = 0^ (set all bits) if v1 == NaN || v2 == NaN - // 0 otherwise - c.assembler.CompileRegisterToRegisterWithArg(cmp, tmp, x1r, 3) - // x2r = -0 if (v1 == -0 || x2 == -0) && v1 != NaN && v2 !=NaN - // ^0 if v1 == NaN || v2 == NaN - // min(v1, v2) otherwise - c.assembler.CompileRegisterToRegister(or, x1r, x2r) - // x1r = set all bits on the mantissa bits - // 0 otherwise - c.assembler.CompileConstToRegister(srl, shiftNumToInverseNaN, x1r) - // x1r = x2r and !x1r - // = -0 if (v1 == -0 || x2 == -0) && v1 != NaN && v2 !=NaN - // set all bits on exponential and sign bit (== NaN) if v1 == NaN || v2 == NaN - // min(v1, v2) otherwise - c.assembler.CompileRegisterToRegister(andn, x2r, x1r) - - c.locationStack.markRegisterUnused(x2r) - c.pushVectorRuntimeValueLocationOnRegister(x1r) - return nil -} - -// compileV128Max implements compiler.compileV128Max for amd64. -func (c *amd64Compiler) compileV128Max(o *wazeroir.UnionOperation) error { - x2 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x2); err != nil { - return err - } - - x1 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x1); err != nil { - return err - } - - shape := o.B1 - if shape >= wazeroir.ShapeF32x4 { - return c.compileV128FloatMaxImpl(shape == wazeroir.ShapeF32x4, x1.register, x2.register) - } - - signed := o.B3 - var inst asm.Instruction - switch shape { - case wazeroir.ShapeI8x16: - if signed { - inst = amd64.PMAXSB - } else { - inst = amd64.PMAXUB - } - case wazeroir.ShapeI16x8: - if signed { - inst = amd64.PMAXSW - } else { - inst = amd64.PMAXUW - } - case wazeroir.ShapeI32x4: - if signed { - inst = amd64.PMAXSD - } else { - inst = amd64.PMAXUD - } - } - - c.assembler.CompileRegisterToRegister(inst, x2.register, x1.register) - - c.locationStack.markRegisterUnused(x2.register) - c.pushVectorRuntimeValueLocationOnRegister(x1.register) - return nil -} - -// compileV128FloatMaxImpl implements compiler.compileV128Max for float lanes. -func (c *amd64Compiler) compileV128FloatMaxImpl(is32bit bool, x1r, x2r asm.Register) error { - tmp, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - - var max, cmp, andn, or, xor, sub, srl /* shit right logical */ asm.Instruction - var shiftNumToInverseNaN asm.ConstantValue - if is32bit { - max, cmp, andn, or, xor, sub, srl, shiftNumToInverseNaN = amd64.MAXPS, amd64.CMPPS, amd64.ANDNPS, amd64.ORPS, amd64.XORPS, amd64.SUBPS, amd64.PSRLD, 0xa - } else { - max, cmp, andn, or, xor, sub, srl, shiftNumToInverseNaN = amd64.MAXPD, amd64.CMPPD, amd64.ANDNPD, amd64.ORPD, amd64.XORPD, amd64.SUBPD, amd64.PSRLQ, 0xd - } - - // Let v1 and v2 be the operand values on x1r and x2r at this point. - - // Copy the value into tmp: tmp=v2 - c.assembler.CompileRegisterToRegister(amd64.MOVDQA, x2r, tmp) - // tmp=max(v2, v1) - c.assembler.CompileRegisterToRegister(max, x1r, tmp) - // x1r=max(v1, v2) - c.assembler.CompileRegisterToRegister(max, x2r, x1r) - // x2r=max(v1, v2) - c.assembler.CompileRegisterToRegister(amd64.MOVDQA, x1r, x2r) - - // x2r = -0 if (v1 == -0 && v2 == 0) || (v1 == 0 && v2 == -0) - // 0 if (v1 == 0 && v2 == 0) - // -0 if (v1 == -0 && v2 == -0) - // v1^v2 if v1 == NaN || v2 == NaN - // 0 otherwise - c.assembler.CompileRegisterToRegister(xor, tmp, x2r) - // x1r = -0 if (v1 == -0 && v2 == 0) || (v1 == 0 && v2 == -0) - // 0 if (v1 == 0 && v2 == 0) - // -0 if (v1 == -0 && v2 == -0) - // NaN if v1 == NaN || v2 == NaN - // max(v1, v2) otherwise - c.assembler.CompileRegisterToRegister(or, x2r, x1r) - // Copy x1r into tmp. - c.assembler.CompileRegisterToRegister(amd64.MOVDQA, x1r, tmp) - // tmp = 0 if (v1 == -0 && v2 == 0) || (v1 == 0 && v2 == -0) || (v1 == 0 && v2 == 0) - // -0 if (v1 == -0 && v2 == -0) - // NaN if v1 == NaN || v2 == NaN - // max(v1, v2) otherwise - // - // Note: -0 - (-0) = 0 (!= -0) in floating point operation. - c.assembler.CompileRegisterToRegister(sub, x2r, tmp) - // x1r = 0^ if v1 == NaN || v2 == NaN - c.assembler.CompileRegisterToRegisterWithArg(cmp, x1r, x1r, 3) - // x1r = set all bits on the mantissa bits - // 0 otherwise - c.assembler.CompileConstToRegister(srl, shiftNumToInverseNaN, x1r) - c.assembler.CompileRegisterToRegister(andn, tmp, x1r) - - c.locationStack.markRegisterUnused(x2r) - c.pushVectorRuntimeValueLocationOnRegister(x1r) - return nil -} - -// compileV128AvgrU implements compiler.compileV128AvgrU for amd64. -func (c *amd64Compiler) compileV128AvgrU(o *wazeroir.UnionOperation) error { - x2 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x2); err != nil { - return err - } - - x1 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x1); err != nil { - return err - } - - var inst asm.Instruction - shape := o.B1 - switch shape { - case wazeroir.ShapeI8x16: - inst = amd64.PAVGB - case wazeroir.ShapeI16x8: - inst = amd64.PAVGW - } - - c.assembler.CompileRegisterToRegister(inst, x2.register, x1.register) - - c.locationStack.markRegisterUnused(x2.register) - c.pushVectorRuntimeValueLocationOnRegister(x1.register) - return nil -} - -// compileV128Pmin implements compiler.compileV128Pmin for amd64. -func (c *amd64Compiler) compileV128Pmin(o *wazeroir.UnionOperation) error { - x2 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x2); err != nil { - return err - } - - x1 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x1); err != nil { - return err - } - - var min asm.Instruction - if o.B1 == wazeroir.ShapeF32x4 { - min = amd64.MINPS - } else { - min = amd64.MINPD - } - - x1r, v2r := x1.register, x2.register - - c.assembler.CompileRegisterToRegister(min, x1r, v2r) - - c.locationStack.markRegisterUnused(x1r) - c.pushVectorRuntimeValueLocationOnRegister(v2r) - return nil -} - -// compileV128Pmax implements compiler.compileV128Pmax for amd64. -func (c *amd64Compiler) compileV128Pmax(o *wazeroir.UnionOperation) error { - x2 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x2); err != nil { - return err - } - - x1 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x1); err != nil { - return err - } - - var min asm.Instruction - if o.B1 == wazeroir.ShapeF32x4 { - min = amd64.MAXPS - } else { - min = amd64.MAXPD - } - - x1r, v2r := x1.register, x2.register - - c.assembler.CompileRegisterToRegister(min, x1r, v2r) - - c.locationStack.markRegisterUnused(x1r) - c.pushVectorRuntimeValueLocationOnRegister(v2r) - return nil -} - -// compileV128Ceil implements compiler.compileV128Ceil for amd64. -func (c *amd64Compiler) compileV128Ceil(o *wazeroir.UnionOperation) error { - // See https://www.felixcloutier.com/x86/roundpd - const roundModeCeil = 0x2 - return c.compileV128RoundImpl(o.B1 == wazeroir.ShapeF32x4, roundModeCeil) -} - -// compileV128Floor implements compiler.compileV128Floor for amd64. -func (c *amd64Compiler) compileV128Floor(o *wazeroir.UnionOperation) error { - // See https://www.felixcloutier.com/x86/roundpd - const roundModeFloor = 0x1 - return c.compileV128RoundImpl(o.B1 == wazeroir.ShapeF32x4, roundModeFloor) -} - -// compileV128Trunc implements compiler.compileV128Trunc for amd64. -func (c *amd64Compiler) compileV128Trunc(o *wazeroir.UnionOperation) error { - // See https://www.felixcloutier.com/x86/roundpd - const roundModeTrunc = 0x3 - return c.compileV128RoundImpl(o.B1 == wazeroir.ShapeF32x4, roundModeTrunc) -} - -// compileV128Nearest implements compiler.compileV128Nearest for amd64. -func (c *amd64Compiler) compileV128Nearest(o *wazeroir.UnionOperation) error { - // See https://www.felixcloutier.com/x86/roundpd - const roundModeNearest = 0x0 - return c.compileV128RoundImpl(o.B1 == wazeroir.ShapeF32x4, roundModeNearest) -} - -// compileV128RoundImpl implements compileV128Nearest compileV128Trunc compileV128Floor and compileV128Ceil -// with ROUNDPS (32-bit lane) and ROUNDPD (64-bit lane). -func (c *amd64Compiler) compileV128RoundImpl(is32bit bool, mode byte) error { - v := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(v); err != nil { - return err - } - vr := v.register - - var round asm.Instruction - if is32bit { - round = amd64.ROUNDPS - } else { - round = amd64.ROUNDPD - } - - c.assembler.CompileRegisterToRegisterWithArg(round, vr, vr, mode) - c.pushVectorRuntimeValueLocationOnRegister(vr) - return nil -} - -// compileV128Extend implements compiler.compileV128Extend for amd64. -func (c *amd64Compiler) compileV128Extend(o *wazeroir.UnionOperation) error { - v := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(v); err != nil { - return err - } - vr := v.register - - originShape := o.B1 - signed := o.B2 == 1 - useLow := o.B3 - if !useLow { - // We have to shift the higher 64-bits into the lower ones before the actual extending instruction. - // Shifting right by 0x8 * 8 = 64bits and concatenate itself. - // See https://www.felixcloutier.com/x86/palignr - c.assembler.CompileRegisterToRegisterWithArg(amd64.PALIGNR, v.register, v.register, 0x8) - } - - var extend asm.Instruction - switch originShape { - case wazeroir.ShapeI8x16: - if signed { - extend = amd64.PMOVSXBW - } else { - extend = amd64.PMOVZXBW - } - case wazeroir.ShapeI16x8: - if signed { - extend = amd64.PMOVSXWD - } else { - extend = amd64.PMOVZXWD - } - case wazeroir.ShapeI32x4: - if signed { - extend = amd64.PMOVSXDQ - } else { - extend = amd64.PMOVZXDQ - } - } - - c.assembler.CompileRegisterToRegister(extend, vr, vr) - c.pushVectorRuntimeValueLocationOnRegister(vr) - return nil -} - -// compileV128ExtMul implements compiler.compileV128ExtMul for amd64. -func (c *amd64Compiler) compileV128ExtMul(o *wazeroir.UnionOperation) error { - x2 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x2); err != nil { - return err - } - - x1 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x1); err != nil { - return err - } - - x1r, x2r := x1.register, x2.register - - originShape := o.B1 - signed := o.B2 == 1 - useLow := o.B3 - switch originShape { - case wazeroir.ShapeI8x16: - if !useLow { - // We have to shift the higher 64-bits into the lower ones before the actual extending instruction. - // Shifting right by 0x8 * 8 = 64bits and concatenate itself. - // See https://www.felixcloutier.com/x86/palignr - c.assembler.CompileRegisterToRegisterWithArg(amd64.PALIGNR, x1r, x1r, 0x8) - c.assembler.CompileRegisterToRegisterWithArg(amd64.PALIGNR, x2r, x2r, 0x8) - } - - var ext asm.Instruction - if signed { - ext = amd64.PMOVSXBW - } else { - ext = amd64.PMOVZXBW - } - - // Signed or Zero extend lower half packed bytes to packed words. - c.assembler.CompileRegisterToRegister(ext, x1r, x1r) - c.assembler.CompileRegisterToRegister(ext, x2r, x2r) - - c.assembler.CompileRegisterToRegister(amd64.PMULLW, x2r, x1r) - case wazeroir.ShapeI16x8: - tmp, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - - // Copy the value on x1r to tmp. - c.assembler.CompileRegisterToRegister(amd64.MOVDQA, x1r, tmp) - - // Multiply the values and store the lower 16-bits into x1r. - c.assembler.CompileRegisterToRegister(amd64.PMULLW, x2r, x1r) - if signed { - // Signed multiply the values and store the higher 16-bits into tmp. - c.assembler.CompileRegisterToRegister(amd64.PMULHW, x2r, tmp) - } else { - // Unsigned multiply the values and store the higher 16-bits into tmp. - c.assembler.CompileRegisterToRegister(amd64.PMULHUW, x2r, tmp) - } - - // Unpack lower or higher half of vectors (tmp and x1r) and concatenate them. - if useLow { - c.assembler.CompileRegisterToRegister(amd64.PUNPCKLWD, tmp, x1r) - } else { - c.assembler.CompileRegisterToRegister(amd64.PUNPCKHWD, tmp, x1r) - } - case wazeroir.ShapeI32x4: - var shuffleOrder byte - // Given that the original state of the register is as [v1, v2, v3, v4] where vN = a word, - if useLow { - // This makes the register as [v1, v1, v2, v2] - shuffleOrder = 0b01010000 - } else { - // This makes the register as [v3, v3, v4, v4] - shuffleOrder = 0b11111010 - } - // See https://www.felixcloutier.com/x86/pshufd - c.assembler.CompileRegisterToRegisterWithArg(amd64.PSHUFD, x1r, x1r, shuffleOrder) - c.assembler.CompileRegisterToRegisterWithArg(amd64.PSHUFD, x2r, x2r, shuffleOrder) - - var mul asm.Instruction - if signed { - mul = amd64.PMULDQ - } else { - mul = amd64.PMULUDQ - } - c.assembler.CompileRegisterToRegister(mul, x2r, x1r) - } - - c.locationStack.markRegisterUnused(x2r) - c.pushVectorRuntimeValueLocationOnRegister(x1r) - return nil -} - -var q15mulrSatSMask = [16]byte{ - 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, - 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, -} - -// compileV128Q15mulrSatS implements compiler.compileV128Q15mulrSatS for amd64. -func (c *amd64Compiler) compileV128Q15mulrSatS(*wazeroir.UnionOperation) error { - x2 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x2); err != nil { - return err - } - - x1 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x1); err != nil { - return err - } - - tmp, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - - x1r, x2r := x1.register, x2.register - - // See https://github.com/WebAssembly/simd/pull/365 for the following logic. - if err := c.assembler.CompileStaticConstToRegister(amd64.MOVDQU, asm.NewStaticConst(q15mulrSatSMask[:]), tmp); err != nil { - return err - } - - c.assembler.CompileRegisterToRegister(amd64.PMULHRSW, x2r, x1r) - c.assembler.CompileRegisterToRegister(amd64.PCMPEQW, x1r, tmp) - c.assembler.CompileRegisterToRegister(amd64.PXOR, tmp, x1r) - - c.locationStack.markRegisterUnused(x2r) - c.pushVectorRuntimeValueLocationOnRegister(x1r) - return nil -} - -var ( - allOnesI8x16 = [16]byte{0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1} - allOnesI16x8 = [16]byte{0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0} - - extAddPairwiseI16x8uMask = [16 * 2]byte{ - 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, - 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, - } -) - -// compileV128ExtAddPairwise implements compiler.compileV128ExtAddPairwise for amd64. -func (c *amd64Compiler) compileV128ExtAddPairwise(o *wazeroir.UnionOperation) error { - v := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(v); err != nil { - return err - } - vr := v.register - - originShape := o.B1 - signed := o.B3 - switch originShape { - case wazeroir.ShapeI8x16: - allOnesReg, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - - if err = c.assembler.CompileStaticConstToRegister(amd64.MOVDQU, - asm.NewStaticConst(allOnesI8x16[:]), allOnesReg); err != nil { - return err - } - - var result asm.Register - // See https://www.felixcloutier.com/x86/pmaddubsw for detail. - if signed { - // Interpret vr's value as signed byte and multiply with one and add pairwise, which results in pairwise - // signed extadd. - c.assembler.CompileRegisterToRegister(amd64.PMADDUBSW, vr, allOnesReg) - result = allOnesReg - } else { - // Interpreter tmp (all ones) as signed byte meaning that all the multiply-add is unsigned. - c.assembler.CompileRegisterToRegister(amd64.PMADDUBSW, allOnesReg, vr) - result = vr - } - - if result != vr { - c.locationStack.markRegisterUnused(vr) - } - c.pushVectorRuntimeValueLocationOnRegister(result) - case wazeroir.ShapeI16x8: - tmp, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - - if signed { - // See https://www.felixcloutier.com/x86/pmaddwd - if err = c.assembler.CompileStaticConstToRegister(amd64.MOVDQU, - asm.NewStaticConst(allOnesI16x8[:]), tmp); err != nil { - return err - } - - c.assembler.CompileRegisterToRegister(amd64.PMADDWD, tmp, vr) - c.pushVectorRuntimeValueLocationOnRegister(vr) - } else { - - if err = c.assembler.CompileStaticConstToRegister(amd64.MOVDQU, - asm.NewStaticConst(extAddPairwiseI16x8uMask[:16]), tmp); err != nil { - return err - } - - // Flip the sign bits on vr. - // - // Assuming that vr = [w1, ..., w8], now we have, - // vr[i] = int8(-w1) for i = 0...8 - c.assembler.CompileRegisterToRegister(amd64.PXOR, tmp, vr) - - if err = c.assembler.CompileStaticConstToRegister(amd64.MOVDQU, - asm.NewStaticConst(allOnesI16x8[:]), tmp); err != nil { - return err - } - - // For i = 0,..4 (as this results in i32x4 lanes), now we have - // vr[i] = int32(-wn + -w(n+1)) = int32(-(wn + w(n+1))) - c.assembler.CompileRegisterToRegister(amd64.PMADDWD, tmp, vr) - - // tmp[i] = [0, 0, 1, 0] = int32(math.MaxInt16+1) - if err = c.assembler.CompileStaticConstToRegister(amd64.MOVDQU, - asm.NewStaticConst(extAddPairwiseI16x8uMask[16:]), tmp); err != nil { - return err - } - - // vr[i] = int32(-(wn + w(n+1))) + int32(math.MaxInt16+1) = int32((wn + w(n+1))) = uint32(wn + w(n+1)). - c.assembler.CompileRegisterToRegister(amd64.PADDD, tmp, vr) - c.pushVectorRuntimeValueLocationOnRegister(vr) - } - } - return nil -} - -// compileV128FloatPromote implements compiler.compileV128FloatPromote for amd64. -func (c *amd64Compiler) compileV128FloatPromote(*wazeroir.UnionOperation) error { - v := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(v); err != nil { - return err - } - vr := v.register - - c.assembler.CompileRegisterToRegister(amd64.CVTPS2PD, vr, vr) - c.pushVectorRuntimeValueLocationOnRegister(vr) - return nil -} - -// compileV128FloatDemote implements compiler.compileV128FloatDemote for amd64. -func (c *amd64Compiler) compileV128FloatDemote(*wazeroir.UnionOperation) error { - v := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(v); err != nil { - return err - } - vr := v.register - - c.assembler.CompileRegisterToRegister(amd64.CVTPD2PS, vr, vr) - c.pushVectorRuntimeValueLocationOnRegister(vr) - return nil -} - -// compileV128Dot implements compiler.compileV128Dot for amd64. -func (c *amd64Compiler) compileV128Dot(*wazeroir.UnionOperation) error { - x2 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x2); err != nil { - return err - } - - x1 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x1); err != nil { - return err - } - - c.assembler.CompileRegisterToRegister(amd64.PMADDWD, x2.register, x1.register) - - c.locationStack.markRegisterUnused(x2.register) - c.pushVectorRuntimeValueLocationOnRegister(x1.register) - return nil -} - -var fConvertFromIMask = [16]byte{ - 0x00, 0x00, 0x30, 0x43, 0x00, 0x00, 0x30, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -} - -// compileV128FConvertFromI implements compiler.compileV128FConvertFromI for amd64. -func (c *amd64Compiler) compileV128FConvertFromI(o *wazeroir.UnionOperation) error { - v := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(v); err != nil { - return err - } - vr := v.register - - destinationShape := o.B1 - signed := o.B3 - - switch destinationShape { - case wazeroir.ShapeF32x4: - if signed { - c.assembler.CompileRegisterToRegister(amd64.CVTDQ2PS, vr, vr) - } else { - tmp, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - - // Copy the value into tmp. - c.assembler.CompileRegisterToRegister(amd64.MOVDQA, vr, tmp) - - // Clear the higher 16-bits of tmp. - c.assembler.CompileConstToRegister(amd64.PSLLD, 0xa, tmp) - c.assembler.CompileConstToRegister(amd64.PSRLD, 0xa, tmp) - - // Subtract the higher 16-bits from vr == clear the lower 16-bits of vr. - c.assembler.CompileRegisterToRegister(amd64.PSUBD, tmp, vr) - - // Convert the lower 16-bits in tmp. - c.assembler.CompileRegisterToRegister(amd64.CVTDQ2PS, tmp, tmp) - - // Left shift by one and convert vr, meaning that halved conversion result of higher 16-bits in vr. - c.assembler.CompileConstToRegister(amd64.PSRLD, 1, vr) - c.assembler.CompileRegisterToRegister(amd64.CVTDQ2PS, vr, vr) - - // Double the converted halved higher 16bits. - c.assembler.CompileRegisterToRegister(amd64.ADDPS, vr, vr) - - // Get the conversion result by add tmp (holding lower 16-bit conversion) into vr. - c.assembler.CompileRegisterToRegister(amd64.ADDPS, tmp, vr) - } - case wazeroir.ShapeF64x2: - if signed { - c.assembler.CompileRegisterToRegister(amd64.CVTDQ2PD, vr, vr) - } else { - tmp, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - - // tmp = [0x00, 0x00, 0x30, 0x43, 0x00, 0x00, 0x30, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00] - if err = c.assembler.CompileStaticConstToRegister(amd64.MOVDQU, asm.NewStaticConst(fConvertFromIMask[:16]), tmp); err != nil { - return err - } - - // Given that we have vr = [d1, d2, d3, d4], this results in - // vr = [d1, [0x00, 0x00, 0x30, 0x43], d2, [0x00, 0x00, 0x30, 0x43]] - // = [float64(uint32(d1)) + 0x1.0p52, float64(uint32(d2)) + 0x1.0p52] - // ^See https://stackoverflow.com/questions/13269523/can-all-32-bit-ints-be-exactly-represented-as-a-double - c.assembler.CompileRegisterToRegister(amd64.UNPCKLPS, tmp, vr) - - // tmp = [float64(0x1.0p52), float64(0x1.0p52)] - if err = c.assembler.CompileStaticConstToRegister(amd64.MOVDQU, - asm.NewStaticConst(twop52[:]), tmp); err != nil { - return err - } - - // Now, we get the result as - // vr = [float64(uint32(d1)), float64(uint32(d2))] - // because the following equality always satisfies: - // float64(0x1.0p52 + float64(uint32(x))) - float64(0x1.0p52 + float64(uint32(y))) = float64(uint32(x)) - float64(uint32(y)) - c.assembler.CompileRegisterToRegister(amd64.SUBPD, tmp, vr) - } - } - - c.pushVectorRuntimeValueLocationOnRegister(vr) - return nil -} - -// compileV128Narrow implements compiler.compileV128Narrow for amd64. -func (c *amd64Compiler) compileV128Narrow(o *wazeroir.UnionOperation) error { - x2 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x2); err != nil { - return err - } - - x1 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x1); err != nil { - return err - } - - var narrow asm.Instruction - originShape := o.B1 - signed := o.B3 - switch originShape { - case wazeroir.ShapeI16x8: - if signed { - narrow = amd64.PACKSSWB - } else { - narrow = amd64.PACKUSWB - } - case wazeroir.ShapeI32x4: - if signed { - narrow = amd64.PACKSSDW - } else { - narrow = amd64.PACKUSDW - } - } - c.assembler.CompileRegisterToRegister(narrow, x2.register, x1.register) - - c.locationStack.markRegisterUnused(x2.register) - c.pushVectorRuntimeValueLocationOnRegister(x1.register) - return nil -} - -var ( - // i32sMaxOnF64x2 holds math.MaxInt32(=2147483647.0) on two f64 lanes. - i32sMaxOnF64x2 = [16]byte{ - 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0xdf, 0x41, // float64(2147483647.0) - 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0xdf, 0x41, // float64(2147483647.0) - } - - // i32sMaxOnF64x2 holds math.MaxUint32(=4294967295.0) on two f64 lanes. - i32uMaxOnF64x2 = [16]byte{ - 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0xef, 0x41, // float64(4294967295.0) - 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0xef, 0x41, // float64(4294967295.0) - } - - // twop52 holds two float64(0x1.0p52) on two f64 lanes. 0x1.0p52 is special in the sense that - // with this exponent, the mantissa represents a corresponding uint32 number, and arithmetics, - // like addition or subtraction, the resulted floating point holds exactly the same - // bit representations in 32-bit integer on its mantissa. - // - // Note: the name twop52 is common across various compiler ecosystem. - // E.g. https://github.com/llvm/llvm-project/blob/92ab024f81e5b64e258b7c3baaf213c7c26fcf40/compiler-rt/lib/builtins/floatdidf.c#L28 - // E.g. https://opensource.apple.com/source/clang/clang-425.0.24/src/projects/compiler-rt/lib/floatdidf.c.auto.html - twop52 = [16]byte{ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x43, // float64(0x1.0p52) - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x43, // float64(0x1.0p52) - } -) - -// compileV128ITruncSatFromF implements compiler.compileV128ITruncSatFromF for amd64. -func (c *amd64Compiler) compileV128ITruncSatFromF(o *wazeroir.UnionOperation) error { - v := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(v); err != nil { - return err - } - vr := v.register - - tmp, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - - c.locationStack.markRegisterUsed(tmp) - - originShape := o.B1 - signed := o.B3 - switch originShape { - case wazeroir.ShapeF32x4: - if signed { - // Copy the value into tmp. - c.assembler.CompileRegisterToRegister(amd64.MOVDQA, vr, tmp) - - // Assuming we have vr = [v1, v2, v3, v4]. - // - // Set all bits if lane is not NaN on tmp. - // tmp[i] = 0xffffffff if vi != NaN - // = 0 if vi == NaN - c.assembler.CompileRegisterToRegister(amd64.CMPEQPS, tmp, tmp) - - // Clear NaN lanes on vr, meaning that - // vr[i] = vi if vi != NaN - // 0 if vi == NaN - c.assembler.CompileRegisterToRegister(amd64.ANDPS, tmp, vr) - - // tmp[i] = ^vi if vi != NaN - // = 0xffffffff if vi == NaN - // which means that tmp[i] & 0x80000000 != 0 if and only if vi is negative. - c.assembler.CompileRegisterToRegister(amd64.PXOR, vr, tmp) - - // vr[i] = int32(vi) if vi != NaN and vr is not overflowing. - // = 0x80000000 if vi != NaN and vr is overflowing (See https://www.felixcloutier.com/x86/cvttps2dq) - // = 0 if vi == NaN - c.assembler.CompileRegisterToRegister(amd64.CVTTPS2DQ, vr, vr) - - // Below, we have to convert 0x80000000 into 0x7FFFFFFF for positive overflowing lane. - // - // tmp[i] = 0x80000000 if vi is positive - // = any satisfying any&0x80000000 = 0 if vi is negative or zero. - c.assembler.CompileRegisterToRegister(amd64.PAND, vr, tmp) - - // Arithmetic right shifting tmp by 31, meaning that we have - // tmp[i] = 0xffffffff if vi is positive, 0 otherwise. - c.assembler.CompileConstToRegister(amd64.PSRAD, 0x1f, tmp) - - // Flipping 0x80000000 if vi is positive, otherwise keep intact. - c.assembler.CompileRegisterToRegister(amd64.PXOR, tmp, vr) - } else { - tmp2, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - - // See https://github.com/bytecodealliance/wasmtime/pull/2440 - // Note: even v8 doesn't seem to have support for this i32x4.tranc_sat_f32x4_u. - c.assembler.CompileRegisterToRegister(amd64.PXOR, tmp, tmp) - c.assembler.CompileRegisterToRegister(amd64.MAXPS, tmp, vr) - c.assembler.CompileRegisterToRegister(amd64.PCMPEQD, tmp, tmp) - c.assembler.CompileConstToRegister(amd64.PSRLD, 0x1, tmp) - c.assembler.CompileRegisterToRegister(amd64.CVTDQ2PS, tmp, tmp) - c.assembler.CompileRegisterToRegister(amd64.MOVDQA, vr, tmp2) - c.assembler.CompileRegisterToRegister(amd64.CVTTPS2DQ, vr, vr) - c.assembler.CompileRegisterToRegister(amd64.SUBPS, tmp, tmp2) - c.assembler.CompileRegisterToRegisterWithArg(amd64.CMPPS, tmp2, tmp, 0x2) // == CMPLEPS - c.assembler.CompileRegisterToRegister(amd64.CVTTPS2DQ, tmp2, tmp2) - c.assembler.CompileRegisterToRegister(amd64.PXOR, tmp, tmp2) - c.assembler.CompileRegisterToRegister(amd64.PXOR, tmp, tmp) - c.assembler.CompileRegisterToRegister(amd64.PMAXSD, tmp, tmp2) - c.assembler.CompileRegisterToRegister(amd64.PADDD, tmp2, vr) - } - case wazeroir.ShapeF64x2: - tmp2, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - - if signed { - // Copy the value into tmp. - c.assembler.CompileRegisterToRegister(amd64.MOVDQA, vr, tmp) - - // Set all bits for non-NaN lanes, zeros otherwise. - // I.e. tmp[i] = 0xffffffff_ffffffff if vi != NaN, 0 otherwise. - c.assembler.CompileRegisterToRegister(amd64.CMPEQPD, tmp, tmp) - - // Load the 2147483647 into tmp2's each lane. - if err = c.assembler.CompileStaticConstToRegister(amd64.MOVUPD, asm.NewStaticConst(i32sMaxOnF64x2[:]), tmp2); err != nil { - return err - } - - // tmp[i] = 2147483647 if vi != NaN, 0 otherwise. - c.assembler.CompileRegisterToRegister(amd64.ANDPS, tmp2, tmp) - - // MINPD returns the source register's value as-is, so we have - // vr[i] = vi if vi != NaN - // = 0 if vi == NaN - c.assembler.CompileRegisterToRegister(amd64.MINPD, tmp, vr) - - c.assembler.CompileRegisterToRegister(amd64.CVTTPD2DQ, vr, vr) - } else { - // Clears all bits on tmp. - c.assembler.CompileRegisterToRegister(amd64.PXOR, tmp, tmp) - - // vr[i] = vi if vi != NaN && vi > 0 - // = 0 if vi == NaN || vi <= 0 - c.assembler.CompileRegisterToRegister(amd64.MAXPD, tmp, vr) - - // tmp2[i] = float64(math.MaxUint32) = math.MaxUint32 - if err = c.assembler.CompileStaticConstToRegister(amd64.MOVUPD, asm.NewStaticConst(i32uMaxOnF64x2[:]), tmp2); err != nil { - return err - } - - // vr[i] = vi if vi != NaN && vi > 0 && vi <= math.MaxUint32 - // = 0 otherwise - c.assembler.CompileRegisterToRegister(amd64.MINPD, tmp2, vr) - - // Round the floating points into integer. - c.assembler.CompileRegisterToRegisterWithArg(amd64.ROUNDPD, vr, vr, 0x3) - - // tmp2[i] = float64(0x1.0p52) - if err = c.assembler.CompileStaticConstToRegister(amd64.MOVUPD, asm.NewStaticConst(twop52[:]), tmp2); err != nil { - return err - } - - // vr[i] = float64(0x1.0p52) + float64(uint32(vi)) if vi != NaN && vi > 0 && vi <= math.MaxUint32 - // = 0 otherwise - // - // This means that vr[i] holds exactly the same bit of uint32(vi) in its lower 32-bits. - c.assembler.CompileRegisterToRegister(amd64.ADDPD, tmp2, vr) - - // At this point, we have - // vr = [uint32(v0), float64(0x1.0p52), uint32(v1), float64(0x1.0p52)] - // tmp = [0, 0, 0, 0] - // as 32x4 lanes. Therefore, SHUFPS with 0b00_00_10_00 results in - // vr = [vr[00], vr[10], tmp[00], tmp[00]] = [vr[00], vr[10], 0, 0] - // meaning that for i = 0 and 1, we have - // vr[i] = uint32(vi) if vi != NaN && vi > 0 && vi <= math.MaxUint32 - // = 0 otherwise. - c.assembler.CompileRegisterToRegisterWithArg(amd64.SHUFPS, tmp, vr, 0b00_00_10_00) - } - } - - c.locationStack.markRegisterUnused(tmp) - c.pushVectorRuntimeValueLocationOnRegister(vr) - return nil -} diff --git a/internal/engine/compiler/impl_vec_amd64_test.go b/internal/engine/compiler/impl_vec_amd64_test.go deleted file mode 100644 index e7180b1709..0000000000 --- a/internal/engine/compiler/impl_vec_amd64_test.go +++ /dev/null @@ -1,324 +0,0 @@ -package compiler - -import ( - "encoding/binary" - "math" - "testing" - - "github.com/tetratelabs/wazero/internal/asm" - "github.com/tetratelabs/wazero/internal/asm/amd64" - "github.com/tetratelabs/wazero/internal/testing/require" - "github.com/tetratelabs/wazero/internal/wasm" - "github.com/tetratelabs/wazero/internal/wazeroir" -) - -// TestAmd64Compiler_V128Shuffle_ConstTable_MiddleOfFunction ensures that flushing constant table in the middle of -// function works well by intentionally setting amd64.AssemblerImpl MaxDisplacementForConstantPool = 0. -func TestAmd64Compiler_V128Shuffle_ConstTable_MiddleOfFunction(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, - &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - lanes := []uint64{1, 1, 1, 1, 0, 0, 0, 0, 10, 10, 10, 10, 0, 0, 0, 0} - v := [16]byte{0: 0xa, 1: 0xb, 10: 0xc} - w := [16]byte{0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - exp := [16]byte{ - 0xb, 0xb, 0xb, 0xb, - 0xa, 0xa, 0xa, 0xa, - 0xc, 0xc, 0xc, 0xc, - 0xa, 0xa, 0xa, 0xa, - } - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(v[:8]), binary.LittleEndian.Uint64(v[8:])))) - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(w[:8]), binary.LittleEndian.Uint64(w[8:])))) - require.NoError(t, err) - - err = compiler.compileV128Shuffle(operationPtr(wazeroir.NewOperationV128Shuffle(lanes))) - require.NoError(t, err) - - assembler := compiler.(*amd64Compiler).assembler.(*amd64.AssemblerImpl) - assembler.MaxDisplacementForConstantPool = 0 // Ensures that constant table for shuffle will be flushed immediately. - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - lo, hi := env.stackTopAsV128() - var actual [16]byte - binary.LittleEndian.PutUint64(actual[:8], lo) - binary.LittleEndian.PutUint64(actual[8:], hi) - require.Equal(t, exp, actual) -} - -func TestAmd64Compiler_compileV128ShrI64x2SignedImpl(t *testing.T) { - x := [16]byte{ - 0, 0, 0, 0x80, 0, 0, 0, 0x80, - 0, 0, 0, 0x80, 0, 0, 0, 0x80, - } - exp := [16]byte{ - 0, 0, 0, 0x40, 0, 0, 0, 0x80 | 0x80>>1, - 0, 0, 0, 0x40, 0, 0, 0, 0x80 | 0x80>>1, - } - shiftAmount := uint32(1) - - tests := []struct { - name string - shiftAmountSetupFn func(t *testing.T, c *amd64Compiler) - verifyFn func(t *testing.T, env *compilerEnv) - }{ - { - name: "RegR10/CX not in use", - shiftAmountSetupFn: func(t *testing.T, c *amd64Compiler) { - // Move the shift amount to R10. - loc := c.locationStack.peek() - oldReg, newReg := loc.register, amd64.RegR10 - c.assembler.CompileRegisterToRegister(amd64.MOVQ, oldReg, newReg) - loc.setRegister(newReg) - c.locationStack.markRegisterUnused(oldReg) - c.locationStack.markRegisterUsed(newReg) - }, - verifyFn: func(t *testing.T, env *compilerEnv) {}, - }, - { - name: "RegR10/CX not in use and CX is next free register", - shiftAmountSetupFn: func(t *testing.T, c *amd64Compiler) { - // Move the shift amount to R10. - loc := c.locationStack.peek() - oldReg, newReg := loc.register, amd64.RegR10 - c.assembler.CompileRegisterToRegister(amd64.MOVQ, oldReg, newReg) - loc.setRegister(newReg) - c.locationStack.markRegisterUnused(oldReg) - c.locationStack.markRegisterUsed(newReg) - - // Ensures that the next free becomes CX. - newUnreservedRegs := make([]asm.Register, len(c.locationStack.unreservedVectorRegisters)) - copy(newUnreservedRegs, c.locationStack.unreservedGeneralPurposeRegisters) - for i, r := range newUnreservedRegs { - // If CX register is found, we swap it with the first register in the list. - // This forces runtimeLocationStack to take CX as a first free register. - if r == amd64.RegCX { - newUnreservedRegs[0], newUnreservedRegs[i] = newUnreservedRegs[i], newUnreservedRegs[0] - } - } - c.locationStack.unreservedGeneralPurposeRegisters = newUnreservedRegs - }, - verifyFn: func(t *testing.T, env *compilerEnv) {}, - }, - { - name: "RegR10/CX in use", - shiftAmountSetupFn: func(t *testing.T, c *amd64Compiler) { - // Pop the shift amount and vector values temporarily. - shiftAmountLocation := c.locationStack.pop() - vecReg := c.locationStack.popV128().register - - // Move the shift amount to R10. - oldReg, newReg := shiftAmountLocation.register, amd64.RegR10 - c.assembler.CompileRegisterToRegister(amd64.MOVQ, oldReg, newReg) - c.locationStack.markRegisterUnused(oldReg) - c.locationStack.markRegisterUsed(newReg) - - // Create the previous usage of CX register. - c.pushRuntimeValueLocationOnRegister(amd64.RegCX, runtimeValueTypeI32) - c.assembler.CompileConstToRegister(amd64.MOVQ, 100, amd64.RegCX) - - // push the operands back to the location registers. - c.pushVectorRuntimeValueLocationOnRegister(vecReg) - c.pushRuntimeValueLocationOnRegister(newReg, runtimeValueTypeI32) - }, - verifyFn: func(t *testing.T, env *compilerEnv) { - // at the bottom of stack, the previous value on the CX register must be saved. - actual := env.stack()[callFrameDataSizeInUint64] - require.Equal(t, uint64(100), actual) - }, - }, - { - name: "Stack/CX not in use", - shiftAmountSetupFn: func(t *testing.T, c *amd64Compiler) { - // Release the shift amount value to the stack. - loc := c.locationStack.peek() - c.compileReleaseRegisterToStack(loc) - }, - verifyFn: func(t *testing.T, env *compilerEnv) {}, - }, - { - name: "Stack/CX in use", - shiftAmountSetupFn: func(t *testing.T, c *amd64Compiler) { - // Pop the shift amount and vector values temporarily. - shiftAmountReg := c.locationStack.pop().register - require.NotEqual(t, amd64.RegCX, shiftAmountReg) - vecReg := c.locationStack.popV128().register - - // Create the previous usage of CX register. - c.pushRuntimeValueLocationOnRegister(amd64.RegCX, runtimeValueTypeI32) - c.assembler.CompileConstToRegister(amd64.MOVQ, 100, amd64.RegCX) - - // push the operands back to the location registers. - c.pushVectorRuntimeValueLocationOnRegister(vecReg) - // Release the shift amount value to the stack. - loc := c.pushRuntimeValueLocationOnRegister(shiftAmountReg, runtimeValueTypeI32) - c.compileReleaseRegisterToStack(loc) - }, - verifyFn: func(t *testing.T, env *compilerEnv) { - // at the bottom of stack, the previous value on the CX register must be saved. - actual := env.stack()[callFrameDataSizeInUint64] - require.Equal(t, uint64(100), actual) - }, - }, - { - name: "CondReg/CX not in use", - shiftAmountSetupFn: func(t *testing.T, c *amd64Compiler) { - // Ignore the pushed const. - loc := c.locationStack.pop() - c.locationStack.markRegisterUnused(loc.register) - - // Instead, push the conditional flag value which is supposed be interpreted as 1 (=shiftAmount). - err := c.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(0))) - require.NoError(t, err) - err = c.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(0))) - require.NoError(t, err) - err = c.compileEq(operationPtr(wazeroir.NewOperationEq(wazeroir.UnsignedTypeI32))) - require.NoError(t, err) - }, - verifyFn: func(t *testing.T, env *compilerEnv) {}, - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, - &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(x[:8]), binary.LittleEndian.Uint64(x[8:])))) - require.NoError(t, err) - - err = compiler.compileConstI32(operationPtr(wazeroir.NewOperationConstI32(shiftAmount))) - require.NoError(t, err) - - amdCompiler := compiler.(*amd64Compiler) - tc.shiftAmountSetupFn(t, amdCompiler) - - err = amdCompiler.compileV128ShrI64x2SignedImpl() - require.NoError(t, err) - - require.Equal(t, 1, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - lo, hi := env.stackTopAsV128() - var actual [16]byte - binary.LittleEndian.PutUint64(actual[:8], lo) - binary.LittleEndian.PutUint64(actual[8:], hi) - require.Equal(t, exp, actual) - - tc.verifyFn(t, env) - }) - } -} - -// TestAmd64Compiler_compileV128Neg_NaNOnTemporary ensures compileV128Neg for floating point variants works well -// even if the temporary register used by the instruction holds NaN values previously. -func TestAmd64Compiler_compileV128Neg_NaNOnTemporary(t *testing.T) { - tests := []struct { - name string - shape wazeroir.Shape - v, exp [16]byte - }{ - { - name: "f32x4", - shape: wazeroir.ShapeF32x4, - v: f32x4(51234.12341, -123, float32(math.Inf(1)), 0.1), - exp: f32x4(-51234.12341, 123, float32(math.Inf(-1)), -0.1), - }, - { - name: "f32x4", - shape: wazeroir.ShapeF32x4, - v: f32x4(51234.12341, 0, float32(math.Inf(1)), 0.1), - exp: f32x4(-51234.12341, float32(math.Copysign(0, -1)), float32(math.Inf(-1)), -0.1), - }, - { - name: "f64x2", - shape: wazeroir.ShapeF64x2, - v: f64x2(1.123, math.Inf(-1)), - exp: f64x2(-1.123, math.Inf(1)), - }, - { - name: "f64x2", - shape: wazeroir.ShapeF64x2, - v: f64x2(0, math.Inf(-1)), - exp: f64x2(math.Copysign(0, -1), math.Inf(1)), - }, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, - &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(tc.v[:8]), binary.LittleEndian.Uint64(tc.v[8:])))) - require.NoError(t, err) - - // Ensures that the previous state of temporary register used by Neg holds - // NaN values. - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(math.Float64bits(math.NaN()), math.Float64bits(math.NaN())))) - require.NoError(t, err) - - // Mark that the temp register is available for Neg instruction below. - loc := compiler.runtimeValueLocationStack().popV128() - compiler.runtimeValueLocationStack().markRegisterUnused(loc.register) - - // Now compiling Neg where it uses temporary register holding NaN values at this point. - err = compiler.compileV128Neg(operationPtr(wazeroir.NewOperationV128Neg(tc.shape))) - require.NoError(t, err) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - env.exec(code.Bytes()) - - require.Equal(t, nativeCallStatusCodeReturned, env.callEngine().statusCode) - - lo, hi := env.stackTopAsV128() - var actual [16]byte - binary.LittleEndian.PutUint64(actual[:8], lo) - binary.LittleEndian.PutUint64(actual[8:], hi) - require.Equal(t, tc.exp, actual) - }) - } -} diff --git a/internal/engine/compiler/impl_vec_arm64.go b/internal/engine/compiler/impl_vec_arm64.go deleted file mode 100644 index 70aa4a0190..0000000000 --- a/internal/engine/compiler/impl_vec_arm64.go +++ /dev/null @@ -1,1592 +0,0 @@ -package compiler - -import ( - "github.com/tetratelabs/wazero/internal/asm" - "github.com/tetratelabs/wazero/internal/asm/arm64" - "github.com/tetratelabs/wazero/internal/wazeroir" -) - -// compileV128Const implements compiler.compileV128Const for arm64. -func (c *arm64Compiler) compileV128Const(o *wazeroir.UnionOperation) error { - if err := c.maybeCompileMoveTopConditionalToGeneralPurposeRegister(); err != nil { - return err - } - - lo, hi := o.U1, o.U2 - - result, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - - // Moves the lower 64-bits as a scalar float. - intReg := arm64ReservedRegisterForTemporary - if lo == 0 { - intReg = arm64.RegRZR - } else { - c.assembler.CompileConstToRegister(arm64.MOVD, int64(lo), arm64ReservedRegisterForTemporary) - } - c.assembler.CompileRegisterToRegister(arm64.FMOVD, intReg, result) - - // Then, insert the higher bits with INS(vector,general). - intReg = arm64ReservedRegisterForTemporary - if hi == 0 { - intReg = arm64.RegRZR - } else { - c.assembler.CompileConstToRegister(arm64.MOVD, int64(hi), arm64ReservedRegisterForTemporary) - } - // "ins Vn.D[1], intReg" - c.assembler.CompileRegisterToVectorRegister(arm64.INSGEN, intReg, result, arm64.VectorArrangementD, 1) - - c.pushVectorRuntimeValueLocationOnRegister(result) - return nil -} - -// compileV128Add implements compiler.compileV128Add for arm64. -func (c *arm64Compiler) compileV128Add(o *wazeroir.UnionOperation) error { - x2 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x2); err != nil { - return err - } - - x1 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x1); err != nil { - return err - } - - x1r, x2r := x1.register, x2.register - - var arr arm64.VectorArrangement - var inst asm.Instruction - shape := o.B1 - switch shape { - case wazeroir.ShapeI8x16: - inst = arm64.VADD - arr = arm64.VectorArrangement16B - case wazeroir.ShapeI16x8: - inst = arm64.VADD - arr = arm64.VectorArrangement8H - case wazeroir.ShapeI32x4: - inst = arm64.VADD - arr = arm64.VectorArrangement4S - case wazeroir.ShapeI64x2: - inst = arm64.VADD - arr = arm64.VectorArrangement2D - case wazeroir.ShapeF32x4: - inst = arm64.VFADDS - arr = arm64.VectorArrangement4S - case wazeroir.ShapeF64x2: - inst = arm64.VFADDD - arr = arm64.VectorArrangement2D - } - - c.assembler.CompileVectorRegisterToVectorRegister(inst, x1r, x2r, arr, - arm64.VectorIndexNone, arm64.VectorIndexNone) - - c.pushVectorRuntimeValueLocationOnRegister(x2r) - c.markRegisterUnused(x1r) - return nil -} - -// compileV128Sub implements compiler.compileV128Sub for arm64. -func (c *arm64Compiler) compileV128Sub(o *wazeroir.UnionOperation) (err error) { - x2 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x2); err != nil { - return err - } - - x1 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x1); err != nil { - return err - } - - x1r, x2r := x1.register, x2.register - - var arr arm64.VectorArrangement - var inst asm.Instruction - shape := o.B1 - switch shape { - case wazeroir.ShapeI8x16: - inst = arm64.VSUB - arr = arm64.VectorArrangement16B - case wazeroir.ShapeI16x8: - inst = arm64.VSUB - arr = arm64.VectorArrangement8H - case wazeroir.ShapeI32x4: - inst = arm64.VSUB - arr = arm64.VectorArrangement4S - case wazeroir.ShapeI64x2: - inst = arm64.VSUB - arr = arm64.VectorArrangement2D - case wazeroir.ShapeF32x4: - inst = arm64.VFSUBS - arr = arm64.VectorArrangement4S - case wazeroir.ShapeF64x2: - inst = arm64.VFSUBD - arr = arm64.VectorArrangement2D - } - - c.assembler.CompileVectorRegisterToVectorRegister(inst, x2r, x1r, arr, - arm64.VectorIndexNone, arm64.VectorIndexNone) - - c.pushVectorRuntimeValueLocationOnRegister(x1r) - c.markRegisterUnused(x2r) - return -} - -// compileV128Load implements compiler.compileV128Load for arm64. -func (c *arm64Compiler) compileV128Load(o *wazeroir.UnionOperation) (err error) { - if err := c.maybeCompileMoveTopConditionalToGeneralPurposeRegister(); err != nil { - return err - } - result, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - - offset := uint32(o.U2) - loadType := wazeroir.V128LoadType(o.B1) - - switch loadType { - case wazeroir.V128LoadType128: - offset, err := c.compileMemoryAccessOffsetSetup(offset, 16) - if err != nil { - return err - } - c.assembler.CompileMemoryWithRegisterOffsetToVectorRegister(arm64.VMOV, - arm64ReservedRegisterForMemory, offset, result, arm64.VectorArrangementQ, - ) - case wazeroir.V128LoadType8x8s: - offset, err := c.compileMemoryAccessOffsetSetup(offset, 8) - if err != nil { - return err - } - c.assembler.CompileMemoryWithRegisterOffsetToVectorRegister(arm64.VMOV, - arm64ReservedRegisterForMemory, offset, result, arm64.VectorArrangementD, - ) - c.assembler.CompileVectorRegisterToVectorRegister(arm64.SSHLL, result, result, - arm64.VectorArrangement8B, arm64.VectorIndexNone, arm64.VectorIndexNone) - case wazeroir.V128LoadType8x8u: - offset, err := c.compileMemoryAccessOffsetSetup(offset, 8) - if err != nil { - return err - } - c.assembler.CompileMemoryWithRegisterOffsetToVectorRegister(arm64.VMOV, - arm64ReservedRegisterForMemory, offset, result, arm64.VectorArrangementD, - ) - c.assembler.CompileVectorRegisterToVectorRegister(arm64.USHLL, result, result, - arm64.VectorArrangement8B, arm64.VectorIndexNone, arm64.VectorIndexNone) - case wazeroir.V128LoadType16x4s: - offset, err := c.compileMemoryAccessOffsetSetup(offset, 8) - if err != nil { - return err - } - c.assembler.CompileMemoryWithRegisterOffsetToVectorRegister(arm64.VMOV, - arm64ReservedRegisterForMemory, offset, result, arm64.VectorArrangementD, - ) - c.assembler.CompileVectorRegisterToVectorRegister(arm64.SSHLL, result, result, - arm64.VectorArrangement4H, arm64.VectorIndexNone, arm64.VectorIndexNone) - case wazeroir.V128LoadType16x4u: - offset, err := c.compileMemoryAccessOffsetSetup(offset, 8) - if err != nil { - return err - } - c.assembler.CompileMemoryWithRegisterOffsetToVectorRegister(arm64.VMOV, - arm64ReservedRegisterForMemory, offset, result, arm64.VectorArrangementD, - ) - c.assembler.CompileVectorRegisterToVectorRegister(arm64.USHLL, result, result, - arm64.VectorArrangement4H, arm64.VectorIndexNone, arm64.VectorIndexNone) - case wazeroir.V128LoadType32x2s: - offset, err := c.compileMemoryAccessOffsetSetup(offset, 8) - if err != nil { - return err - } - c.assembler.CompileMemoryWithRegisterOffsetToVectorRegister(arm64.VMOV, - arm64ReservedRegisterForMemory, offset, result, arm64.VectorArrangementD, - ) - c.assembler.CompileVectorRegisterToVectorRegister(arm64.SSHLL, result, result, - arm64.VectorArrangement2S, arm64.VectorIndexNone, arm64.VectorIndexNone) - case wazeroir.V128LoadType32x2u: - offset, err := c.compileMemoryAccessOffsetSetup(offset, 8) - if err != nil { - return err - } - c.assembler.CompileMemoryWithRegisterOffsetToVectorRegister(arm64.VMOV, - arm64ReservedRegisterForMemory, offset, result, arm64.VectorArrangementD, - ) - c.assembler.CompileVectorRegisterToVectorRegister(arm64.USHLL, result, result, - arm64.VectorArrangement2S, arm64.VectorIndexNone, arm64.VectorIndexNone) - case wazeroir.V128LoadType8Splat: - offset, err := c.compileMemoryAccessOffsetSetup(offset, 1) - if err != nil { - return err - } - c.assembler.CompileRegisterToRegister(arm64.ADD, arm64ReservedRegisterForMemory, offset) - c.assembler.CompileMemoryToVectorRegister(arm64.LD1R, offset, 0, result, arm64.VectorArrangement16B) - case wazeroir.V128LoadType16Splat: - offset, err := c.compileMemoryAccessOffsetSetup(offset, 2) - if err != nil { - return err - } - c.assembler.CompileRegisterToRegister(arm64.ADD, arm64ReservedRegisterForMemory, offset) - c.assembler.CompileMemoryToVectorRegister(arm64.LD1R, offset, 0, result, arm64.VectorArrangement8H) - case wazeroir.V128LoadType32Splat: - offset, err := c.compileMemoryAccessOffsetSetup(offset, 4) - if err != nil { - return err - } - c.assembler.CompileRegisterToRegister(arm64.ADD, arm64ReservedRegisterForMemory, offset) - c.assembler.CompileMemoryToVectorRegister(arm64.LD1R, offset, 0, result, arm64.VectorArrangement4S) - case wazeroir.V128LoadType64Splat: - offset, err := c.compileMemoryAccessOffsetSetup(offset, 8) - if err != nil { - return err - } - c.assembler.CompileRegisterToRegister(arm64.ADD, arm64ReservedRegisterForMemory, offset) - c.assembler.CompileMemoryToVectorRegister(arm64.LD1R, offset, 0, result, arm64.VectorArrangement2D) - case wazeroir.V128LoadType32zero: - offset, err := c.compileMemoryAccessOffsetSetup(offset, 4) - if err != nil { - return err - } - c.assembler.CompileMemoryWithRegisterOffsetToVectorRegister(arm64.VMOV, - arm64ReservedRegisterForMemory, offset, result, arm64.VectorArrangementS, - ) - case wazeroir.V128LoadType64zero: - offset, err := c.compileMemoryAccessOffsetSetup(offset, 8) - if err != nil { - return err - } - c.assembler.CompileMemoryWithRegisterOffsetToVectorRegister(arm64.VMOV, - arm64ReservedRegisterForMemory, offset, result, arm64.VectorArrangementD, - ) - } - - c.pushVectorRuntimeValueLocationOnRegister(result) - return -} - -// compileV128LoadLane implements compiler.compileV128LoadLane for arm64. -func (c *arm64Compiler) compileV128LoadLane(o *wazeroir.UnionOperation) (err error) { - targetVector := c.locationStack.popV128() - if err = c.compileEnsureOnRegister(targetVector); err != nil { - return - } - - laneSize, laneIndex := o.B1, o.B2 - offset := uint32(o.U2) - - targetSizeInBytes := int64(laneSize / 8) - source, err := c.compileMemoryAccessOffsetSetup(offset, targetSizeInBytes) - if err != nil { - return err - } - - var loadInst asm.Instruction - var arr arm64.VectorArrangement - switch laneSize { - case 8: - arr = arm64.VectorArrangementB - loadInst = arm64.LDRB - case 16: - arr = arm64.VectorArrangementH - loadInst = arm64.LDRH - case 32: - loadInst = arm64.LDRW - arr = arm64.VectorArrangementS - case 64: - loadInst = arm64.LDRD - arr = arm64.VectorArrangementD - } - - c.assembler.CompileMemoryWithRegisterOffsetToRegister(loadInst, arm64ReservedRegisterForMemory, source, source) - c.assembler.CompileRegisterToVectorRegister(arm64.INSGEN, source, targetVector.register, arr, arm64.VectorIndex(laneIndex)) - - c.pushVectorRuntimeValueLocationOnRegister(targetVector.register) - c.locationStack.markRegisterUnused(source) - return -} - -// compileV128Store implements compiler.compileV128Store for arm64. -func (c *arm64Compiler) compileV128Store(o *wazeroir.UnionOperation) (err error) { - v := c.locationStack.popV128() - if err = c.compileEnsureOnRegister(v); err != nil { - return - } - - const targetSizeInBytes = 16 - offset := uint32(o.U2) - offsetReg, err := c.compileMemoryAccessOffsetSetup(offset, targetSizeInBytes) - if err != nil { - return err - } - - c.assembler.CompileVectorRegisterToMemoryWithRegisterOffset(arm64.VMOV, - v.register, arm64ReservedRegisterForMemory, offsetReg, arm64.VectorArrangementQ) - - c.markRegisterUnused(v.register) - return -} - -// compileV128StoreLane implements compiler.compileV128StoreLane for arm64. -func (c *arm64Compiler) compileV128StoreLane(o *wazeroir.UnionOperation) (err error) { - var arr arm64.VectorArrangement - var storeInst asm.Instruction - laneSize := o.B1 - laneIndex := o.B2 - offset := uint32(o.U2) - switch laneSize { - case 8: - storeInst = arm64.STRB - arr = arm64.VectorArrangementB - case 16: - storeInst = arm64.STRH - arr = arm64.VectorArrangementH - case 32: - storeInst = arm64.STRW - arr = arm64.VectorArrangementS - case 64: - storeInst = arm64.STRD - arr = arm64.VectorArrangementD - } - - v := c.locationStack.popV128() - if err = c.compileEnsureOnRegister(v); err != nil { - return - } - - targetSizeInBytes := int64(laneSize / 8) - offsetReg, err := c.compileMemoryAccessOffsetSetup(offset, targetSizeInBytes) - if err != nil { - return err - } - - c.assembler.CompileVectorRegisterToRegister(arm64.UMOV, v.register, arm64ReservedRegisterForTemporary, arr, - arm64.VectorIndex(laneIndex)) - - c.assembler.CompileRegisterToMemoryWithRegisterOffset(storeInst, - arm64ReservedRegisterForTemporary, arm64ReservedRegisterForMemory, offsetReg) - - c.locationStack.markRegisterUnused(v.register) - return -} - -// compileV128ExtractLane implements compiler.compileV128ExtractLane for arm64. -func (c *arm64Compiler) compileV128ExtractLane(o *wazeroir.UnionOperation) (err error) { - v := c.locationStack.popV128() - if err = c.compileEnsureOnRegister(v); err != nil { - return - } - - shape := o.B1 - laneIndex := o.B2 - signed := o.B3 - switch shape { - case wazeroir.ShapeI8x16: - result, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - var inst asm.Instruction - if signed { - inst = arm64.SMOV32 - } else { - inst = arm64.UMOV - } - c.assembler.CompileVectorRegisterToRegister(inst, v.register, result, - arm64.VectorArrangementB, arm64.VectorIndex(laneIndex)) - - c.locationStack.markRegisterUnused(v.register) - c.pushRuntimeValueLocationOnRegister(result, runtimeValueTypeI32) - case wazeroir.ShapeI16x8: - result, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - var inst asm.Instruction - if signed { - inst = arm64.SMOV32 - } else { - inst = arm64.UMOV - } - c.assembler.CompileVectorRegisterToRegister(inst, v.register, result, - arm64.VectorArrangementH, arm64.VectorIndex(laneIndex)) - - c.locationStack.markRegisterUnused(v.register) - c.pushRuntimeValueLocationOnRegister(result, runtimeValueTypeI32) - case wazeroir.ShapeI32x4: - result, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - c.assembler.CompileVectorRegisterToRegister(arm64.UMOV, v.register, result, - arm64.VectorArrangementS, arm64.VectorIndex(laneIndex)) - - c.locationStack.markRegisterUnused(v.register) - c.pushRuntimeValueLocationOnRegister(result, runtimeValueTypeI32) - case wazeroir.ShapeI64x2: - result, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - c.assembler.CompileVectorRegisterToRegister(arm64.UMOV, v.register, result, - arm64.VectorArrangementD, arm64.VectorIndex(laneIndex)) - - c.locationStack.markRegisterUnused(v.register) - c.pushRuntimeValueLocationOnRegister(result, runtimeValueTypeI64) - case wazeroir.ShapeF32x4: - c.assembler.CompileVectorRegisterToVectorRegister(arm64.INSELEM, v.register, v.register, - arm64.VectorArrangementS, arm64.VectorIndex(laneIndex), 0) - c.pushRuntimeValueLocationOnRegister(v.register, runtimeValueTypeF32) - case wazeroir.ShapeF64x2: - c.assembler.CompileVectorRegisterToVectorRegister(arm64.INSELEM, v.register, v.register, - arm64.VectorArrangementD, arm64.VectorIndex(laneIndex), 0) - c.pushRuntimeValueLocationOnRegister(v.register, runtimeValueTypeF64) - } - return -} - -// compileV128ReplaceLane implements compiler.compileV128ReplaceLane for arm64. -func (c *arm64Compiler) compileV128ReplaceLane(o *wazeroir.UnionOperation) (err error) { - origin := c.locationStack.pop() - if err = c.compileEnsureOnRegister(origin); err != nil { - return - } - - vector := c.locationStack.popV128() - if err = c.compileEnsureOnRegister(vector); err != nil { - return - } - - shape := o.B1 - laneIndex := o.B2 - switch shape { - case wazeroir.ShapeI8x16: - c.assembler.CompileRegisterToVectorRegister(arm64.INSGEN, origin.register, vector.register, - arm64.VectorArrangementB, arm64.VectorIndex(laneIndex)) - case wazeroir.ShapeI16x8: - c.assembler.CompileRegisterToVectorRegister(arm64.INSGEN, origin.register, vector.register, - arm64.VectorArrangementH, arm64.VectorIndex(laneIndex)) - case wazeroir.ShapeI32x4: - c.assembler.CompileRegisterToVectorRegister(arm64.INSGEN, origin.register, vector.register, - arm64.VectorArrangementS, arm64.VectorIndex(laneIndex)) - case wazeroir.ShapeI64x2: - c.assembler.CompileRegisterToVectorRegister(arm64.INSGEN, origin.register, vector.register, - arm64.VectorArrangementD, arm64.VectorIndex(laneIndex)) - case wazeroir.ShapeF32x4: - c.assembler.CompileVectorRegisterToVectorRegister(arm64.INSELEM, origin.register, vector.register, - arm64.VectorArrangementS, 0, arm64.VectorIndex(laneIndex)) - case wazeroir.ShapeF64x2: - c.assembler.CompileVectorRegisterToVectorRegister(arm64.INSELEM, origin.register, vector.register, - arm64.VectorArrangementD, 0, arm64.VectorIndex(laneIndex)) - } - - c.locationStack.markRegisterUnused(origin.register) - c.pushVectorRuntimeValueLocationOnRegister(vector.register) - return -} - -// compileV128Splat implements compiler.compileV128Splat for arm64. -func (c *arm64Compiler) compileV128Splat(o *wazeroir.UnionOperation) (err error) { - origin := c.locationStack.pop() - if err = c.compileEnsureOnRegister(origin); err != nil { - return - } - - var result asm.Register - shape := o.B1 - switch shape { - case wazeroir.ShapeI8x16: - result, err = c.allocateRegister(registerTypeVector) - if err != nil { - return - } - c.assembler.CompileRegisterToVectorRegister(arm64.DUPGEN, origin.register, result, - arm64.VectorArrangement16B, arm64.VectorIndexNone) - case wazeroir.ShapeI16x8: - result, err = c.allocateRegister(registerTypeVector) - if err != nil { - return - } - c.assembler.CompileRegisterToVectorRegister(arm64.DUPGEN, origin.register, result, - arm64.VectorArrangement8H, arm64.VectorIndexNone) - case wazeroir.ShapeI32x4: - result, err = c.allocateRegister(registerTypeVector) - if err != nil { - return - } - c.assembler.CompileRegisterToVectorRegister(arm64.DUPGEN, origin.register, result, - arm64.VectorArrangement4S, arm64.VectorIndexNone) - case wazeroir.ShapeI64x2: - result, err = c.allocateRegister(registerTypeVector) - if err != nil { - return - } - c.assembler.CompileRegisterToVectorRegister(arm64.DUPGEN, origin.register, result, - arm64.VectorArrangement2D, arm64.VectorIndexNone) - case wazeroir.ShapeF32x4: - result = origin.register - c.assembler.CompileVectorRegisterToVectorRegister(arm64.DUPELEM, origin.register, result, - arm64.VectorArrangementS, 0, arm64.VectorIndexNone) - case wazeroir.ShapeF64x2: - result = origin.register - c.assembler.CompileVectorRegisterToVectorRegister(arm64.DUPELEM, origin.register, result, - arm64.VectorArrangementD, 0, arm64.VectorIndexNone) - } - - c.locationStack.markRegisterUnused(origin.register) - c.pushVectorRuntimeValueLocationOnRegister(result) - return -} - -func (c *arm64Compiler) onValueReleaseRegisterToStack(reg asm.Register) { - for i := uint64(0); i < c.locationStack.sp; i++ { - prevValue := &c.locationStack.stack[i] - if prevValue.register == reg { - c.compileReleaseRegisterToStack(prevValue) - break - } - } -} - -// compileV128Shuffle implements compiler.compileV128Shuffle for arm64. -func (c *arm64Compiler) compileV128Shuffle(o *wazeroir.UnionOperation) (err error) { - // Shuffle needs two operands (v, w) must be next to each other. - // For simplicity, we use V29 for v and V30 for w values respectively. - const vReg, wReg = arm64.RegV29, arm64.RegV30 - - // Ensures that w value is placed on wReg. - w := c.locationStack.popV128() - if w.register != wReg { - // If wReg is already in use, save the value onto the stack. - c.onValueReleaseRegisterToStack(wReg) - - if w.onRegister() { - c.assembler.CompileTwoVectorRegistersToVectorRegister(arm64.VORR, - w.register, w.register, wReg, arm64.VectorArrangement16B) - // We no longer use the old register. - c.markRegisterUnused(w.register) - } else { // on stack - w.setRegister(wReg) - c.compileLoadValueOnStackToRegister(w) - } - } - - // Ensures that v value is placed on wReg. - v := c.locationStack.popV128() - if v.register != vReg { - // If vReg is already in use, save the value onto the stack. - c.onValueReleaseRegisterToStack(vReg) - - if v.onRegister() { - c.assembler.CompileTwoVectorRegistersToVectorRegister(arm64.VORR, - v.register, v.register, vReg, arm64.VectorArrangement16B) - // We no longer use the old register. - c.markRegisterUnused(v.register) - } else { // on stack - v.setRegister(vReg) - c.compileLoadValueOnStackToRegister(v) - } - } - - c.locationStack.markRegisterUsed(vReg, wReg) - result, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - - lanes := make([]byte, len(o.Us)) - for i, lane := range o.Us { - lanes[i] = byte(lane) - } - c.assembler.CompileStaticConstToVectorRegister(arm64.VMOV, asm.NewStaticConst(lanes), result, arm64.VectorArrangementQ) - c.assembler.CompileVectorRegisterToVectorRegister(arm64.TBL2, vReg, result, arm64.VectorArrangement16B, - arm64.VectorIndexNone, arm64.VectorIndexNone) - - c.locationStack.markRegisterUnused(vReg, wReg) - c.pushVectorRuntimeValueLocationOnRegister(result) - return -} - -// compileV128Swizzle implements compiler.compileV128Swizzle for arm64. -func (c *arm64Compiler) compileV128Swizzle(*wazeroir.UnionOperation) (err error) { - indexVec := c.locationStack.popV128() - if err = c.compileEnsureOnRegister(indexVec); err != nil { - return - } - baseVec := c.locationStack.popV128() - if err = c.compileEnsureOnRegister(baseVec); err != nil { - return - } - - c.assembler.CompileVectorRegisterToVectorRegister(arm64.TBL1, baseVec.register, indexVec.register, - arm64.VectorArrangement16B, arm64.VectorIndexNone, arm64.VectorIndexNone) - - c.markRegisterUnused(baseVec.register) - c.pushVectorRuntimeValueLocationOnRegister(indexVec.register) - return -} - -// compileV128AnyTrue implements compiler.compileV128AnyTrue for arm64. -func (c *arm64Compiler) compileV128AnyTrue(*wazeroir.UnionOperation) (err error) { - vector := c.locationStack.popV128() - if err = c.compileEnsureOnRegister(vector); err != nil { - return - } - - v := vector.register - c.assembler.CompileVectorRegisterToVectorRegister(arm64.UMAXP, v, v, - arm64.VectorArrangement16B, arm64.VectorIndexNone, arm64.VectorIndexNone) - c.assembler.CompileVectorRegisterToRegister(arm64.UMOV, v, arm64ReservedRegisterForTemporary, - arm64.VectorArrangementD, 0) - c.assembler.CompileTwoRegistersToNone(arm64.CMP, arm64.RegRZR, arm64ReservedRegisterForTemporary) - c.locationStack.pushRuntimeValueLocationOnConditionalRegister(arm64.CondNE) - - c.locationStack.markRegisterUnused(v) - return -} - -// compileV128AllTrue implements compiler.compileV128AllTrue for arm64. -func (c *arm64Compiler) compileV128AllTrue(o *wazeroir.UnionOperation) (err error) { - vector := c.locationStack.popV128() - if err = c.compileEnsureOnRegister(vector); err != nil { - return - } - - v := vector.register - shape := o.B1 - if shape == wazeroir.ShapeI64x2 { - c.assembler.CompileVectorRegisterToVectorRegister(arm64.CMEQZERO, arm64.RegRZR, v, - arm64.VectorArrangement2D, arm64.VectorIndexNone, arm64.VectorIndexNone) - c.assembler.CompileVectorRegisterToVectorRegister(arm64.ADDP, v, v, - arm64.VectorArrangement2D, arm64.VectorIndexNone, arm64.VectorIndexNone) - c.assembler.CompileTwoRegistersToNone(arm64.FCMPD, v, v) - c.locationStack.pushRuntimeValueLocationOnConditionalRegister(arm64.CondEQ) - } else { - var arr arm64.VectorArrangement - switch shape { - case wazeroir.ShapeI8x16: - arr = arm64.VectorArrangement16B - case wazeroir.ShapeI16x8: - arr = arm64.VectorArrangement8H - case wazeroir.ShapeI32x4: - arr = arm64.VectorArrangement4S - } - - c.assembler.CompileVectorRegisterToVectorRegister(arm64.UMINV, v, v, - arr, arm64.VectorIndexNone, arm64.VectorIndexNone) - c.assembler.CompileVectorRegisterToRegister(arm64.UMOV, v, arm64ReservedRegisterForTemporary, - arm64.VectorArrangementD, 0) - c.assembler.CompileTwoRegistersToNone(arm64.CMP, arm64.RegRZR, arm64ReservedRegisterForTemporary) - c.locationStack.pushRuntimeValueLocationOnConditionalRegister(arm64.CondNE) - } - c.markRegisterUnused(v) - return -} - -var ( - i8x16BitmaskConst = [16]byte{ - 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, - 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, - } - i16x8BitmaskConst = [16]byte{ - 0x01, 0x00, 0x02, 0x00, 0x04, 0x00, 0x08, 0x00, - 0x10, 0x00, 0x20, 0x00, 0x40, 0x00, 0x80, 0x00, - } - i32x4BitmaskConst = [16]byte{ - 0x01, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, - 0x04, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, - } -) - -// compileV128BitMask implements compiler.compileV128BitMask for arm64. -func (c *arm64Compiler) compileV128BitMask(o *wazeroir.UnionOperation) (err error) { - vector := c.locationStack.popV128() - if err = c.compileEnsureOnRegister(vector); err != nil { - return - } - - v := vector.register - - result, err := c.allocateRegister(registerTypeGeneralPurpose) - if err != nil { - return err - } - - shape := o.B1 - switch shape { - case wazeroir.ShapeI8x16: - vecTmp, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - // Right arithmetic shift on the original vector and store the result into vecTmp. So we have: - // v[i] = 0xff if vi<0, 0 otherwise. - c.assembler.CompileVectorRegisterToVectorRegisterWithConst(arm64.SSHR, v, v, arm64.VectorArrangement16B, 7) - - // Load the bit mask into vecTmp. - c.assembler.CompileStaticConstToVectorRegister(arm64.VMOV, asm.NewStaticConst(i8x16BitmaskConst[:]), vecTmp, arm64.VectorArrangementQ) - - // Lane-wise logical AND with i8x16BitmaskConst, meaning that we have - // v[i] = (1 << i) if vi<0, 0 otherwise. - // - // Below, we use the following notation: - // wi := (1 << i) if vi<0, 0 otherwise. - c.assembler.CompileVectorRegisterToVectorRegister(arm64.VAND, vecTmp, v, arm64.VectorArrangement16B, - arm64.VectorIndexNone, arm64.VectorIndexNone) - - // Swap the lower and higher 8 byte elements, and write it into vecTmp, meaning that we have - // vecTmp[i] = w(i+8) if i < 8, w(i-8) otherwise. - // - c.assembler.CompileTwoVectorRegistersToVectorRegisterWithConst(arm64.EXT, v, v, vecTmp, arm64.VectorArrangement16B, 0x8) - - // v = [w0, w8, ..., w7, w15] - c.assembler.CompileTwoVectorRegistersToVectorRegister(arm64.ZIP1, vecTmp, v, v, arm64.VectorArrangement16B) - - // v.h[0] = w0 + ... + w15 - c.assembler.CompileVectorRegisterToVectorRegister(arm64.ADDV, v, v, - arm64.VectorArrangement8H, arm64.VectorIndexNone, arm64.VectorIndexNone) - - // Extract the v.h[0] as the result. - c.assembler.CompileVectorRegisterToRegister(arm64.UMOV, v, result, arm64.VectorArrangementH, 0) - case wazeroir.ShapeI16x8: - vecTmp, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - // Right arithmetic shift on the original vector and store the result into vecTmp. So we have: - // v[i] = 0xffff if vi<0, 0 otherwise. - c.assembler.CompileVectorRegisterToVectorRegisterWithConst(arm64.SSHR, v, v, arm64.VectorArrangement8H, 15) - - // Load the bit mask into vecTmp. - c.assembler.CompileStaticConstToVectorRegister(arm64.VMOV, asm.NewStaticConst(i16x8BitmaskConst[:]), vecTmp, arm64.VectorArrangementQ) - - // Lane-wise logical AND with i16x8BitmaskConst, meaning that we have - // v[i] = (1 << i) if vi<0, 0 otherwise for i=0..3 - // = (1 << (i+4)) if vi<0, 0 otherwise for i=3..7 - c.assembler.CompileVectorRegisterToVectorRegister(arm64.VAND, vecTmp, v, arm64.VectorArrangement16B, - arm64.VectorIndexNone, arm64.VectorIndexNone) - - c.assembler.CompileVectorRegisterToVectorRegister(arm64.ADDV, v, v, - arm64.VectorArrangement8H, arm64.VectorIndexNone, arm64.VectorIndexNone) - - c.assembler.CompileVectorRegisterToRegister(arm64.UMOV, v, result, arm64.VectorArrangementH, 0) - case wazeroir.ShapeI32x4: - vecTmp, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - - // Right arithmetic shift on the original vector and store the result into vecTmp. So we have: - // v[i] = 0xffffffff if vi<0, 0 otherwise. - c.assembler.CompileVectorRegisterToVectorRegisterWithConst(arm64.SSHR, v, v, arm64.VectorArrangement4S, 32) - - // Load the bit mask into vecTmp. - c.assembler.CompileStaticConstToVectorRegister(arm64.VMOV, - asm.NewStaticConst(i32x4BitmaskConst[:]), vecTmp, arm64.VectorArrangementQ) - - // Lane-wise logical AND with i16x8BitmaskConst, meaning that we have - // v[i] = (1 << i) if vi<0, 0 otherwise for i in [0, 1] - // = (1 << (i+4)) if vi<0, 0 otherwise for i in [2, 3] - c.assembler.CompileVectorRegisterToVectorRegister(arm64.VAND, vecTmp, v, arm64.VectorArrangement16B, - arm64.VectorIndexNone, arm64.VectorIndexNone) - - c.assembler.CompileVectorRegisterToVectorRegister(arm64.ADDV, v, v, - arm64.VectorArrangement4S, arm64.VectorIndexNone, arm64.VectorIndexNone) - - c.assembler.CompileVectorRegisterToRegister(arm64.UMOV, v, result, arm64.VectorArrangementS, 0) - case wazeroir.ShapeI64x2: - // Move the lower 64-bit int into result, - c.assembler.CompileVectorRegisterToRegister(arm64.UMOV, v, result, - arm64.VectorArrangementD, 0) - // Move the higher 64-bit int into arm64ReservedRegisterForTemporary. - c.assembler.CompileVectorRegisterToRegister(arm64.UMOV, v, arm64ReservedRegisterForTemporary, - arm64.VectorArrangementD, 1) - - // Move the sign bit into the least significant bit. - c.assembler.CompileConstToRegister(arm64.LSR, 63, result) - c.assembler.CompileConstToRegister(arm64.LSR, 63, arm64ReservedRegisterForTemporary) - - // result = (arm64ReservedRegisterForTemporary<<1) | result - c.assembler.CompileLeftShiftedRegisterToRegister(arm64.ADD, - arm64ReservedRegisterForTemporary, 1, result, result) - } - - c.markRegisterUnused(v) - c.pushRuntimeValueLocationOnRegister(result, runtimeValueTypeI32) - return -} - -// compileV128And implements compiler.compileV128And for arm64. -func (c *arm64Compiler) compileV128And(*wazeroir.UnionOperation) error { - return c.compileV128x2BinOp(arm64.VAND, arm64.VectorArrangement16B) -} - -// compileV128Not implements compiler.compileV128Not for arm64. -func (c *arm64Compiler) compileV128Not(*wazeroir.UnionOperation) error { - return c.compileV128UniOp(arm64.NOT, arm64.VectorArrangement16B) -} - -// compileV128Or implements compiler.compileV128Or for arm64. -func (c *arm64Compiler) compileV128Or(*wazeroir.UnionOperation) error { - return c.compileV128x2BinOp(arm64.VORR, arm64.VectorArrangement16B) -} - -// compileV128Xor implements compiler.compileV128Xor for arm64. -func (c *arm64Compiler) compileV128Xor(*wazeroir.UnionOperation) error { - return c.compileV128x2BinOp(arm64.EOR, arm64.VectorArrangement16B) -} - -// compileV128Bitselect implements compiler.compileV128Bitselect for arm64. -func (c *arm64Compiler) compileV128Bitselect(*wazeroir.UnionOperation) error { - selector := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(selector); err != nil { - return err - } - - x2 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x2); err != nil { - return err - } - - x1 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x1); err != nil { - return err - } - - c.assembler.CompileTwoVectorRegistersToVectorRegister(arm64.BSL, - x2.register, x1.register, selector.register, arm64.VectorArrangement16B) - - c.markRegisterUnused(x1.register, x2.register) - c.pushVectorRuntimeValueLocationOnRegister(selector.register) - return nil -} - -// compileV128AndNot implements compiler.compileV128AndNot for arm64. -func (c *arm64Compiler) compileV128AndNot(*wazeroir.UnionOperation) error { - return c.compileV128x2BinOp(arm64.BIC, arm64.VectorArrangement16B) -} - -func (c *arm64Compiler) compileV128UniOp(inst asm.Instruction, arr arm64.VectorArrangement) error { - v := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(v); err != nil { - return err - } - - c.assembler.CompileVectorRegisterToVectorRegister(inst, v.register, v.register, arr, arm64.VectorIndexNone, arm64.VectorIndexNone) - - c.pushVectorRuntimeValueLocationOnRegister(v.register) - return nil -} - -func (c *arm64Compiler) compileV128x2BinOp(inst asm.Instruction, arr arm64.VectorArrangement) error { - x2 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x2); err != nil { - return err - } - - x1 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x1); err != nil { - return err - } - - c.assembler.CompileVectorRegisterToVectorRegister(inst, x2.register, x1.register, arr, arm64.VectorIndexNone, arm64.VectorIndexNone) - - c.markRegisterUnused(x2.register) - c.pushVectorRuntimeValueLocationOnRegister(x1.register) - return nil -} - -// compileV128Shr implements compiler.compileV128Shr for arm64. -func (c *arm64Compiler) compileV128Shr(o *wazeroir.UnionOperation) error { - var inst asm.Instruction - shape := o.B1 - signed := o.B3 - if signed { - inst = arm64.SSHL - } else { - inst = arm64.USHL - } - return c.compileV128ShiftImpl(shape, inst, true) -} - -// compileV128Shl implements compiler.compileV128Shl for arm64. -func (c *arm64Compiler) compileV128Shl(o *wazeroir.UnionOperation) error { - return c.compileV128ShiftImpl(o.B1 /*shape*/, arm64.SSHL, false) -} - -func (c *arm64Compiler) compileV128ShiftImpl(shape wazeroir.Shape, ins asm.Instruction, rightShift bool) error { - s := c.locationStack.pop() - if s.register == arm64.RegRZR { - // If the shift amount is zero register, nothing to do here. - return nil - } - - var modulo asm.ConstantValue - var arr arm64.VectorArrangement - switch shape { - case wazeroir.ShapeI8x16: - modulo = 0x7 // modulo 8. - arr = arm64.VectorArrangement16B - case wazeroir.ShapeI16x8: - modulo = 0xf // modulo 16. - arr = arm64.VectorArrangement8H - case wazeroir.ShapeI32x4: - modulo = 0x1f // modulo 32. - arr = arm64.VectorArrangement4S - case wazeroir.ShapeI64x2: - modulo = 0x3f // modulo 64. - arr = arm64.VectorArrangement2D - } - - if err := c.compileEnsureOnRegister(s); err != nil { - return err - } - - v := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(v); err != nil { - return err - } - - tmp, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - - c.assembler.CompileConstToRegister(arm64.ANDIMM32, modulo, s.register) - - if rightShift { - // Negate the amount to make this as right shift. - c.assembler.CompileRegisterToRegister(arm64.NEG, s.register, s.register) - } - - // Copy the shift amount into a vector register as SSHL requires it to be there. - c.assembler.CompileRegisterToVectorRegister(arm64.DUPGEN, s.register, tmp, - arr, arm64.VectorIndexNone) - - c.assembler.CompileVectorRegisterToVectorRegister(ins, tmp, v.register, arr, - arm64.VectorIndexNone, arm64.VectorIndexNone) - - c.markRegisterUnused(s.register) - c.pushVectorRuntimeValueLocationOnRegister(v.register) - return nil -} - -// compileV128Cmp implements compiler.compileV128Cmp for arm64. -func (c *arm64Compiler) compileV128Cmp(o *wazeroir.UnionOperation) error { - x2 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x2); err != nil { - return err - } - - x1 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x1); err != nil { - return err - } - - var arr arm64.VectorArrangement - v128CmpType := o.B1 - if v128CmpType <= wazeroir.V128CmpTypeI8x16GeU { - arr = arm64.VectorArrangement16B - } else if v128CmpType <= wazeroir.V128CmpTypeI16x8GeU { - arr = arm64.VectorArrangement8H - } else if v128CmpType <= wazeroir.V128CmpTypeI32x4GeU { - arr = arm64.VectorArrangement4S - } else if v128CmpType <= wazeroir.V128CmpTypeI64x2GeS { - arr = arm64.VectorArrangement2D - } else if v128CmpType <= wazeroir.V128CmpTypeF32x4Ge { - arr = arm64.VectorArrangement4S - } else { // f64x2 - arr = arm64.VectorArrangement2D - } - - result := x1.register - switch v128CmpType { - case wazeroir.V128CmpTypeI8x16Eq, wazeroir.V128CmpTypeI16x8Eq, wazeroir.V128CmpTypeI32x4Eq, wazeroir.V128CmpTypeI64x2Eq: - c.assembler.CompileTwoVectorRegistersToVectorRegister(arm64.CMEQ, x1.register, x2.register, result, arr) - case wazeroir.V128CmpTypeI8x16Ne, wazeroir.V128CmpTypeI16x8Ne, wazeroir.V128CmpTypeI32x4Ne, wazeroir.V128CmpTypeI64x2Ne: - c.assembler.CompileTwoVectorRegistersToVectorRegister(arm64.CMEQ, x1.register, x2.register, result, arr) - // Reverse the condition by flipping all bits. - c.assembler.CompileVectorRegisterToVectorRegister(arm64.NOT, result, result, - arm64.VectorArrangement16B, arm64.VectorIndexNone, arm64.VectorIndexNone) - case wazeroir.V128CmpTypeI8x16LtS, wazeroir.V128CmpTypeI16x8LtS, wazeroir.V128CmpTypeI32x4LtS, wazeroir.V128CmpTypeI64x2LtS: - c.assembler.CompileTwoVectorRegistersToVectorRegister(arm64.CMGT, x1.register, x2.register, result, arr) - case wazeroir.V128CmpTypeI8x16LtU, wazeroir.V128CmpTypeI16x8LtU, wazeroir.V128CmpTypeI32x4LtU: - c.assembler.CompileTwoVectorRegistersToVectorRegister(arm64.CMHI, x1.register, x2.register, result, arr) - case wazeroir.V128CmpTypeI8x16GtS, wazeroir.V128CmpTypeI16x8GtS, wazeroir.V128CmpTypeI32x4GtS, wazeroir.V128CmpTypeI64x2GtS: - c.assembler.CompileTwoVectorRegistersToVectorRegister(arm64.CMGT, x2.register, x1.register, result, arr) - case wazeroir.V128CmpTypeI8x16GtU, wazeroir.V128CmpTypeI16x8GtU, wazeroir.V128CmpTypeI32x4GtU: - c.assembler.CompileTwoVectorRegistersToVectorRegister(arm64.CMHI, x2.register, x1.register, result, arr) - case wazeroir.V128CmpTypeI8x16LeS, wazeroir.V128CmpTypeI16x8LeS, wazeroir.V128CmpTypeI32x4LeS, wazeroir.V128CmpTypeI64x2LeS: - c.assembler.CompileTwoVectorRegistersToVectorRegister(arm64.CMGE, x1.register, x2.register, result, arr) - case wazeroir.V128CmpTypeI8x16LeU, wazeroir.V128CmpTypeI16x8LeU, wazeroir.V128CmpTypeI32x4LeU: - c.assembler.CompileTwoVectorRegistersToVectorRegister(arm64.CMHS, x1.register, x2.register, result, arr) - case wazeroir.V128CmpTypeI8x16GeS, wazeroir.V128CmpTypeI16x8GeS, wazeroir.V128CmpTypeI32x4GeS, wazeroir.V128CmpTypeI64x2GeS: - c.assembler.CompileTwoVectorRegistersToVectorRegister(arm64.CMGE, x2.register, x1.register, result, arr) - case wazeroir.V128CmpTypeI8x16GeU, wazeroir.V128CmpTypeI16x8GeU, wazeroir.V128CmpTypeI32x4GeU: - c.assembler.CompileTwoVectorRegistersToVectorRegister(arm64.CMHS, x2.register, x1.register, result, arr) - case wazeroir.V128CmpTypeF32x4Eq, wazeroir.V128CmpTypeF64x2Eq: - c.assembler.CompileTwoVectorRegistersToVectorRegister(arm64.FCMEQ, x2.register, x1.register, result, arr) - case wazeroir.V128CmpTypeF32x4Ne, wazeroir.V128CmpTypeF64x2Ne: - c.assembler.CompileTwoVectorRegistersToVectorRegister(arm64.FCMEQ, x2.register, x1.register, result, arr) - // Reverse the condition by flipping all bits. - c.assembler.CompileVectorRegisterToVectorRegister(arm64.NOT, result, result, - arm64.VectorArrangement16B, arm64.VectorIndexNone, arm64.VectorIndexNone) - case wazeroir.V128CmpTypeF32x4Lt, wazeroir.V128CmpTypeF64x2Lt: - c.assembler.CompileTwoVectorRegistersToVectorRegister(arm64.FCMGT, x1.register, x2.register, result, arr) - case wazeroir.V128CmpTypeF32x4Le, wazeroir.V128CmpTypeF64x2Le: - c.assembler.CompileTwoVectorRegistersToVectorRegister(arm64.FCMGE, x1.register, x2.register, result, arr) - case wazeroir.V128CmpTypeF32x4Gt, wazeroir.V128CmpTypeF64x2Gt: - c.assembler.CompileTwoVectorRegistersToVectorRegister(arm64.FCMGT, x2.register, x1.register, result, arr) - case wazeroir.V128CmpTypeF32x4Ge, wazeroir.V128CmpTypeF64x2Ge: - c.assembler.CompileTwoVectorRegistersToVectorRegister(arm64.FCMGE, x2.register, x1.register, result, arr) - } - - c.markRegisterUnused(x2.register) - c.pushVectorRuntimeValueLocationOnRegister(result) - return nil -} - -// compileV128AddSat implements compiler.compileV128AddSat for arm64. -func (c *arm64Compiler) compileV128AddSat(o *wazeroir.UnionOperation) error { - var inst asm.Instruction - shape := o.B1 - signed := o.B3 - if signed { - inst = arm64.VSQADD - } else { - inst = arm64.VUQADD - } - return c.compileV128x2BinOp(inst, defaultArrangementForShape(shape)) -} - -// compileV128SubSat implements compiler.compileV128SubSat for arm64. -func (c *arm64Compiler) compileV128SubSat(o *wazeroir.UnionOperation) error { - var inst asm.Instruction - shape := o.B1 - signed := o.B3 - if signed { - inst = arm64.VSQSUB - } else { - inst = arm64.VUQSUB - } - return c.compileV128x2BinOp(inst, defaultArrangementForShape(shape)) -} - -// compileV128Mul implements compiler.compileV128Mul for arm64. -func (c *arm64Compiler) compileV128Mul(o *wazeroir.UnionOperation) (err error) { - shape := o.B1 - switch shape { - case wazeroir.ShapeI8x16, wazeroir.ShapeI16x8, wazeroir.ShapeI32x4: - err = c.compileV128x2BinOp(arm64.VMUL, defaultArrangementForShape(shape)) - case wazeroir.ShapeF32x4, wazeroir.ShapeF64x2: - err = c.compileV128x2BinOp(arm64.VFMUL, defaultArrangementForShape(shape)) - case wazeroir.ShapeI64x2: - x2 := c.locationStack.popV128() - if err = c.compileEnsureOnRegister(x2); err != nil { - return - } - - x1 := c.locationStack.popV128() - if err = c.compileEnsureOnRegister(x1); err != nil { - return - } - - src1, src2 := x1.register, x2.register - - tmp1, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - c.markRegisterUsed(tmp1) - - tmp2, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - - c.markRegisterUsed(tmp2) - - tmp3, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - - // Following the algorithm in https://chromium-review.googlesource.com/c/v8/v8/+/1781696 - c.assembler.CompileVectorRegisterToVectorRegister(arm64.REV64, src2, tmp2, - arm64.VectorArrangement4S, arm64.VectorIndexNone, arm64.VectorIndexNone) - c.assembler.CompileTwoVectorRegistersToVectorRegister(arm64.VMUL, src1, tmp2, tmp2, arm64.VectorArrangement4S) - - c.assembler.CompileVectorRegisterToVectorRegister(arm64.XTN, src1, tmp1, - arm64.VectorArrangement2D, arm64.VectorIndexNone, arm64.VectorIndexNone) - - c.assembler.CompileVectorRegisterToVectorRegister(arm64.VADDP, tmp2, tmp2, arm64.VectorArrangement4S, - arm64.VectorIndexNone, arm64.VectorIndexNone, - ) - - c.assembler.CompileVectorRegisterToVectorRegister(arm64.XTN, src2, tmp3, - arm64.VectorArrangement2D, arm64.VectorIndexNone, arm64.VectorIndexNone) - - c.assembler.CompileVectorRegisterToVectorRegister(arm64.SHLL, tmp2, src1, - arm64.VectorArrangement2S, arm64.VectorIndexNone, arm64.VectorIndexNone) - - c.assembler.CompileTwoVectorRegistersToVectorRegister(arm64.VUMLAL, tmp3, tmp1, src1, arm64.VectorArrangement2S) - - c.markRegisterUnused(src2, tmp1, tmp2) - c.pushVectorRuntimeValueLocationOnRegister(src1) - } - return -} - -// compileV128Div implements compiler.compileV128Div for arm64. -func (c *arm64Compiler) compileV128Div(o *wazeroir.UnionOperation) error { - var arr arm64.VectorArrangement - var inst asm.Instruction - shape := o.B1 - switch shape { - case wazeroir.ShapeF32x4: - arr = arm64.VectorArrangement4S - inst = arm64.VFDIV - case wazeroir.ShapeF64x2: - arr = arm64.VectorArrangement2D - inst = arm64.VFDIV - } - return c.compileV128x2BinOp(inst, arr) -} - -// compileV128Neg implements compiler.compileV128Neg for arm64. -func (c *arm64Compiler) compileV128Neg(o *wazeroir.UnionOperation) error { - var inst asm.Instruction - shape := o.B1 - if shape <= wazeroir.ShapeI64x2 { // Integer lanes - inst = arm64.VNEG - } else { // Floating point lanes - inst = arm64.VFNEG - } - return c.compileV128UniOp(inst, defaultArrangementForShape(shape)) -} - -// compileV128Sqrt implements compiler.compileV128Sqrt for arm64. -func (c *arm64Compiler) compileV128Sqrt(o *wazeroir.UnionOperation) error { - var arr arm64.VectorArrangement - shape := o.B1 - switch shape { - case wazeroir.ShapeF32x4: - arr = arm64.VectorArrangement4S - case wazeroir.ShapeF64x2: - arr = arm64.VectorArrangement2D - } - return c.compileV128UniOp(arm64.VFSQRT, arr) -} - -// compileV128Abs implements compiler.compileV128Abs for arm64. -func (c *arm64Compiler) compileV128Abs(o *wazeroir.UnionOperation) error { - var inst asm.Instruction - shape := o.B1 - if shape <= wazeroir.ShapeI64x2 { // Integer lanes - inst = arm64.VABS - } else { // Floating point lanes - inst = arm64.VFABS - } - return c.compileV128UniOp(inst, defaultArrangementForShape(shape)) -} - -// compileV128Popcnt implements compiler.compileV128Popcnt for arm64. -func (c *arm64Compiler) compileV128Popcnt(o *wazeroir.UnionOperation) error { - return c.compileV128UniOp(arm64.VCNT, defaultArrangementForShape(o.B1)) -} - -// compileV128Min implements compiler.compileV128Min for arm64. -func (c *arm64Compiler) compileV128Min(o *wazeroir.UnionOperation) error { - var inst asm.Instruction - shape := o.B1 - signed := o.B3 - if shape <= wazeroir.ShapeI64x2 { // Integer lanes - if signed { - inst = arm64.SMIN - } else { - inst = arm64.UMIN - } - } else { // Floating point lanes - inst = arm64.VFMIN - } - return c.compileV128x2BinOp(inst, defaultArrangementForShape(shape)) -} - -func defaultArrangementForShape(s wazeroir.Shape) (arr arm64.VectorArrangement) { - switch s { - case wazeroir.ShapeI8x16: - arr = arm64.VectorArrangement16B - case wazeroir.ShapeI16x8: - arr = arm64.VectorArrangement8H - case wazeroir.ShapeI32x4: - arr = arm64.VectorArrangement4S - case wazeroir.ShapeI64x2: - arr = arm64.VectorArrangement2D - case wazeroir.ShapeF32x4: - arr = arm64.VectorArrangement4S - case wazeroir.ShapeF64x2: - arr = arm64.VectorArrangement2D - } - return -} - -// compileV128Max implements compiler.compileV128Max for arm64. -func (c *arm64Compiler) compileV128Max(o *wazeroir.UnionOperation) error { - var inst asm.Instruction - shape := o.B1 - signed := o.B3 - if shape <= wazeroir.ShapeI64x2 { // Integer lanes - if signed { - inst = arm64.SMAX - } else { - inst = arm64.UMAX - } - } else { // Floating point lanes - inst = arm64.VFMAX - } - return c.compileV128x2BinOp(inst, defaultArrangementForShape(shape)) -} - -// compileV128AvgrU implements compiler.compileV128AvgrU for arm64. -func (c *arm64Compiler) compileV128AvgrU(o *wazeroir.UnionOperation) error { - return c.compileV128x2BinOp(arm64.URHADD, defaultArrangementForShape(o.B1)) -} - -// compileV128Pmin implements compiler.compileV128Pmin for arm64. -func (c *arm64Compiler) compileV128Pmin(o *wazeroir.UnionOperation) error { - return c.compileV128PseudoMinOrMax(defaultArrangementForShape(o.B1), false) -} - -// compileV128Pmax implements compiler.compileV128Pmax for arm64. -func (c *arm64Compiler) compileV128Pmax(o *wazeroir.UnionOperation) error { - return c.compileV128PseudoMinOrMax(defaultArrangementForShape(o.B1), true) -} - -// compileV128PseudoMinOrMax implements compileV128Pmax and compileV128Pmin. -func (c *arm64Compiler) compileV128PseudoMinOrMax(arr arm64.VectorArrangement, max bool) error { - x2 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x2); err != nil { - return err - } - - x1 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x1); err != nil { - return err - } - - result, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - - x1r, x2r := x1.register, x2.register - - // Sets all bits on each lane if x1r's lane satisfies the condition (min or max), zeros otherwise. - if max { - c.assembler.CompileTwoVectorRegistersToVectorRegister(arm64.FCMGT, x1r, x2r, result, arr) - } else { - c.assembler.CompileTwoVectorRegistersToVectorRegister(arm64.FCMGT, x2r, x1r, result, arr) - } - // Select each bit based on the result bits ^. - c.assembler.CompileTwoVectorRegistersToVectorRegister(arm64.BSL, x1r, x2r, result, arm64.VectorArrangement16B) - - c.markRegisterUnused(x1r, x2r) - c.pushVectorRuntimeValueLocationOnRegister(result) - return nil -} - -// compileV128Ceil implements compiler.compileV128Ceil for arm64. -func (c *arm64Compiler) compileV128Ceil(o *wazeroir.UnionOperation) error { - var arr arm64.VectorArrangement - shape := o.B1 - switch shape { - case wazeroir.ShapeF32x4: - arr = arm64.VectorArrangement4S - case wazeroir.ShapeF64x2: - arr = arm64.VectorArrangement2D - } - return c.compileV128UniOp(arm64.VFRINTP, arr) -} - -// compileV128Floor implements compiler.compileV128Floor for arm64. -func (c *arm64Compiler) compileV128Floor(o *wazeroir.UnionOperation) error { - var arr arm64.VectorArrangement - shape := o.B1 - switch shape { - case wazeroir.ShapeF32x4: - arr = arm64.VectorArrangement4S - case wazeroir.ShapeF64x2: - arr = arm64.VectorArrangement2D - } - return c.compileV128UniOp(arm64.VFRINTM, arr) -} - -// compileV128Trunc implements compiler.compileV128Trunc for arm64. -func (c *arm64Compiler) compileV128Trunc(o *wazeroir.UnionOperation) error { - var arr arm64.VectorArrangement - shape := o.B1 - switch shape { - case wazeroir.ShapeF32x4: - arr = arm64.VectorArrangement4S - case wazeroir.ShapeF64x2: - arr = arm64.VectorArrangement2D - } - return c.compileV128UniOp(arm64.VFRINTZ, arr) -} - -// compileV128Nearest implements compiler.compileV128Nearest for arm64. -func (c *arm64Compiler) compileV128Nearest(o *wazeroir.UnionOperation) error { - var arr arm64.VectorArrangement - shape := o.B1 - switch shape { - case wazeroir.ShapeF32x4: - arr = arm64.VectorArrangement4S - case wazeroir.ShapeF64x2: - arr = arm64.VectorArrangement2D - } - return c.compileV128UniOp(arm64.VFRINTN, arr) -} - -// compileV128Extend implements compiler.compileV128Extend for arm64. -func (c *arm64Compiler) compileV128Extend(o *wazeroir.UnionOperation) error { - var inst asm.Instruction - var arr arm64.VectorArrangement - originShape := o.B1 - signed := o.B2 == 1 - useLow := o.B3 - if useLow { - if signed { - inst = arm64.SSHLL - } else { - inst = arm64.USHLL - } - - switch originShape { - case wazeroir.ShapeI8x16: - arr = arm64.VectorArrangement8B - case wazeroir.ShapeI16x8: - arr = arm64.VectorArrangement4H - case wazeroir.ShapeI32x4: - arr = arm64.VectorArrangement2S - } - } else { - if signed { - inst = arm64.SSHLL2 - } else { - inst = arm64.USHLL2 - } - arr = defaultArrangementForShape(originShape) - } - - return c.compileV128UniOp(inst, arr) -} - -// compileV128ExtMul implements compiler.compileV128ExtMul for arm64. -func (c *arm64Compiler) compileV128ExtMul(o *wazeroir.UnionOperation) error { - var inst asm.Instruction - var arr arm64.VectorArrangement - originShape := o.B1 - signed := o.B2 == 1 - useLow := o.B3 - if useLow { - if signed { - inst = arm64.SMULL - } else { - inst = arm64.UMULL - } - - switch originShape { - case wazeroir.ShapeI8x16: - arr = arm64.VectorArrangement8B - case wazeroir.ShapeI16x8: - arr = arm64.VectorArrangement4H - case wazeroir.ShapeI32x4: - arr = arm64.VectorArrangement2S - } - } else { - if signed { - inst = arm64.SMULL2 - } else { - inst = arm64.UMULL2 - } - arr = defaultArrangementForShape(originShape) - } - - return c.compileV128x2BinOp(inst, arr) -} - -// compileV128Q15mulrSatS implements compiler.compileV128Q15mulrSatS for arm64. -func (c *arm64Compiler) compileV128Q15mulrSatS(*wazeroir.UnionOperation) error { - return c.compileV128x2BinOp(arm64.SQRDMULH, arm64.VectorArrangement8H) -} - -// compileV128ExtAddPairwise implements compiler.compileV128ExtAddPairwise for arm64. -func (c *arm64Compiler) compileV128ExtAddPairwise(o *wazeroir.UnionOperation) error { - var inst asm.Instruction - originShape := o.B1 - signed := o.B3 - if signed { - inst = arm64.SADDLP - } else { - inst = arm64.UADDLP - } - return c.compileV128UniOp(inst, defaultArrangementForShape(originShape)) -} - -// compileV128FloatPromote implements compiler.compileV128FloatPromote for arm64. -func (c *arm64Compiler) compileV128FloatPromote(*wazeroir.UnionOperation) error { - return c.compileV128UniOp(arm64.FCVTL, arm64.VectorArrangement2S) -} - -// compileV128FloatDemote implements compiler.compileV128FloatDemote for arm64. -func (c *arm64Compiler) compileV128FloatDemote(*wazeroir.UnionOperation) error { - return c.compileV128UniOp(arm64.FCVTN, arm64.VectorArrangement2S) -} - -// compileV128FConvertFromI implements compiler.compileV128FConvertFromI for arm64. -func (c *arm64Compiler) compileV128FConvertFromI(o *wazeroir.UnionOperation) (err error) { - destinationShape := o.B1 - signed := o.B3 - - if destinationShape == wazeroir.ShapeF32x4 { - if signed { - err = c.compileV128UniOp(arm64.VSCVTF, defaultArrangementForShape(destinationShape)) - } else { - err = c.compileV128UniOp(arm64.VUCVTF, defaultArrangementForShape(destinationShape)) - } - return - } else { // f64x2 - v := c.locationStack.popV128() - if err = c.compileEnsureOnRegister(v); err != nil { - return - } - vr := v.register - - var expand, convert asm.Instruction - if signed { - expand, convert = arm64.SSHLL, arm64.VSCVTF - } else { - expand, convert = arm64.USHLL, arm64.VUCVTF - } - - // Expand lower two 32-bit lanes as two 64-bit lanes. - c.assembler.CompileVectorRegisterToVectorRegisterWithConst(expand, vr, vr, arm64.VectorArrangement2S, 0) - // Convert these two 64-bit (integer) values on each lane as double precision values. - c.assembler.CompileVectorRegisterToVectorRegister(convert, vr, vr, arm64.VectorArrangement2D, - arm64.VectorIndexNone, arm64.VectorIndexNone) - c.pushVectorRuntimeValueLocationOnRegister(vr) - } - return -} - -// compileV128Dot implements compiler.compileV128Dot for arm64. -func (c *arm64Compiler) compileV128Dot(*wazeroir.UnionOperation) error { - x2 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x2); err != nil { - return err - } - - x1 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x1); err != nil { - return err - } - - tmp, err := c.allocateRegister(registerTypeVector) - if err != nil { - return err - } - - x1r, x2r := x1.register, x2.register - - // Multiply lower integers and get the 32-bit results into tmp. - c.assembler.CompileTwoVectorRegistersToVectorRegister(arm64.SMULL, x1r, x2r, tmp, arm64.VectorArrangement4H) - // Multiply higher integers and get the 32-bit results into x1r. - c.assembler.CompileTwoVectorRegistersToVectorRegister(arm64.SMULL2, x1r, x2r, x1r, arm64.VectorArrangement8H) - // Adds these two results into x1r. - c.assembler.CompileTwoVectorRegistersToVectorRegister(arm64.VADDP, x1r, tmp, x1r, arm64.VectorArrangement4S) - - c.markRegisterUnused(x2r) - c.pushVectorRuntimeValueLocationOnRegister(x1r) - - return nil -} - -// compileV128Narrow implements compiler.compileV128Narrow for arm64. -func (c *arm64Compiler) compileV128Narrow(o *wazeroir.UnionOperation) error { - x2 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x2); err != nil { - return err - } - - x1 := c.locationStack.popV128() - if err := c.compileEnsureOnRegister(x1); err != nil { - return err - } - - x1r, x2r := x1.register, x2.register - - var arr, arr2 arm64.VectorArrangement - originShape := o.B1 - signed := o.B3 - switch originShape { - case wazeroir.ShapeI16x8: - arr = arm64.VectorArrangement8B - arr2 = arm64.VectorArrangement16B - case wazeroir.ShapeI32x4: - arr = arm64.VectorArrangement4H - arr2 = arm64.VectorArrangement8H - } - - var lo, hi asm.Instruction - if signed { - lo, hi = arm64.SQXTN, arm64.SQXTN2 - } else { - lo, hi = arm64.SQXTUN, arm64.SQXTUN2 - } - - // Narrow lanes on x1r and write them into lower-half of x1r. - c.assembler.CompileVectorRegisterToVectorRegister(lo, x1r, x1r, arr, arm64.VectorIndexNone, arm64.VectorIndexNone) - // Narrow lanes on x2r and write them into higher-half of x1r. - c.assembler.CompileVectorRegisterToVectorRegister(hi, x2r, x1r, arr2, arm64.VectorIndexNone, arm64.VectorIndexNone) - - c.markRegisterUnused(x2r) - c.pushVectorRuntimeValueLocationOnRegister(x1r) - return nil -} - -// compileV128ITruncSatFromF implements compiler.compileV128ITruncSatFromF for arm64. -func (c *arm64Compiler) compileV128ITruncSatFromF(o *wazeroir.UnionOperation) (err error) { - v := c.locationStack.popV128() - if err = c.compileEnsureOnRegister(v); err != nil { - return err - } - - originShape := o.B1 - signed := o.B3 - var cvt asm.Instruction - if signed { - cvt = arm64.VFCVTZS - } else { - cvt = arm64.VFCVTZU - } - - c.assembler.CompileVectorRegisterToVectorRegister(cvt, v.register, v.register, - defaultArrangementForShape(originShape), arm64.VectorIndexNone, arm64.VectorIndexNone, - ) - - if originShape == wazeroir.ShapeF64x2 { - var narrow asm.Instruction - if signed { - narrow = arm64.SQXTN - } else { - narrow = arm64.UQXTN - } - c.assembler.CompileVectorRegisterToVectorRegister(narrow, v.register, v.register, - arm64.VectorArrangement2S, arm64.VectorIndexNone, arm64.VectorIndexNone, - ) - } - - c.pushVectorRuntimeValueLocationOnRegister(v.register) - return -} diff --git a/internal/engine/compiler/impl_vec_arm64_test.go b/internal/engine/compiler/impl_vec_arm64_test.go deleted file mode 100644 index caa0c17cd9..0000000000 --- a/internal/engine/compiler/impl_vec_arm64_test.go +++ /dev/null @@ -1,207 +0,0 @@ -package compiler - -import ( - "encoding/binary" - "testing" - - "github.com/tetratelabs/wazero/internal/asm" - "github.com/tetratelabs/wazero/internal/asm/arm64" - "github.com/tetratelabs/wazero/internal/testing/require" - "github.com/tetratelabs/wazero/internal/wasm" - "github.com/tetratelabs/wazero/internal/wazeroir" -) - -// TestArm64Compiler_V128Shuffle_ConstTable_MiddleOfFunction ensures that flushing constant table in the middle of -// function works well by intentionally setting arm64.AssemblerImpl MaxDisplacementForConstantPool = 0. -func TestArm64Compiler_V128Shuffle_ConstTable_MiddleOfFunction(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, - &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - lanes := []uint64{1, 1, 1, 1, 0, 0, 0, 0, 10, 10, 10, 10, 0, 0, 0, 0} - v := [16]byte{0: 0xa, 1: 0xb, 10: 0xc} - w := [16]byte{0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - exp := [16]byte{ - 0xb, 0xb, 0xb, 0xb, - 0xa, 0xa, 0xa, 0xa, - 0xc, 0xc, 0xc, 0xc, - 0xa, 0xa, 0xa, 0xa, - } - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(v[:8]), binary.LittleEndian.Uint64(v[8:])))) - require.NoError(t, err) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(w[:8]), binary.LittleEndian.Uint64(w[8:])))) - require.NoError(t, err) - - err = compiler.compileV128Shuffle(operationPtr(wazeroir.NewOperationV128Shuffle(lanes))) - require.NoError(t, err) - - assembler := compiler.(*arm64Compiler).assembler.(*arm64.AssemblerImpl) - assembler.MaxDisplacementForConstantPool = 0 // Ensures that constant table for shuffle will be flushed immediately. - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - - env.exec(code.Bytes()) - - lo, hi := env.stackTopAsV128() - var actual [16]byte - binary.LittleEndian.PutUint64(actual[:8], lo) - binary.LittleEndian.PutUint64(actual[8:], hi) - require.Equal(t, exp, actual) -} - -func TestArm64Compiler_V128Shuffle_combinations(t *testing.T) { - movValueRegisterToRegister := func(t *testing.T, c *arm64Compiler, src *runtimeValueLocation, dst asm.Register) { - c.assembler.CompileTwoVectorRegistersToVectorRegister(arm64.VORR, src.register, src.register, dst, - arm64.VectorArrangement16B) - c.locationStack.markRegisterUnused(src.register) - src.setRegister(dst) - // We have to set the lower 64-bits' location as well. - c.locationStack.stack[src.stackPointer-1].setRegister(dst) - c.locationStack.markRegisterUsed(dst) - } - - tests := []struct { - name string - init func(t *testing.T, c *arm64Compiler) - wReg, vReg asm.Register - verifyFnc func(t *testing.T, env *compilerEnv) - expStackPointerAfterShuffle uint64 - }{ - { - name: "w=v1, v=v2", - wReg: arm64.RegV1, - vReg: arm64.RegV2, - init: func(t *testing.T, c *arm64Compiler) {}, - verifyFnc: func(t *testing.T, env *compilerEnv) {}, - expStackPointerAfterShuffle: 2, - }, - { - name: "w=v2, v=v1", - wReg: arm64.RegV2, - vReg: arm64.RegV1, - init: func(t *testing.T, c *arm64Compiler) {}, - verifyFnc: func(t *testing.T, env *compilerEnv) {}, - expStackPointerAfterShuffle: 2, - }, - { - name: "w=v29, v=v30", - wReg: arm64.RegV29, // will be moved to v30. - vReg: arm64.RegV30, // will be moved to v29. - init: func(t *testing.T, c *arm64Compiler) {}, - verifyFnc: func(t *testing.T, env *compilerEnv) {}, - expStackPointerAfterShuffle: 2, - }, - { - name: "w=v12, v=v30", - wReg: arm64.RegV12, // will be moved to v30. - vReg: arm64.RegV30, // will be moved to v29. - init: func(t *testing.T, c *arm64Compiler) { - // Set up the previous value on the v3 register. - err := c.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(1234, 5678))) - require.NoError(t, err) - movValueRegisterToRegister(t, c, c.locationStack.peek(), arm64.RegV29) - }, - verifyFnc: func(t *testing.T, env *compilerEnv) { - // Previous value on the V3 register must be saved onto the stack. - lo, hi := env.stack()[callFrameDataSizeInUint64], env.stack()[callFrameDataSizeInUint64+1] - require.Equal(t, uint64(1234), lo) - require.Equal(t, uint64(5678), hi) - }, - expStackPointerAfterShuffle: 4, - }, - { - name: "w=v29, v=v12", - wReg: arm64.RegV29, // will be moved to v30. - vReg: arm64.RegV12, // will be moved to v29. - init: func(t *testing.T, c *arm64Compiler) { - // Set up the previous value on the v3 register. - err := c.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(1234, 5678))) - require.NoError(t, err) - movValueRegisterToRegister(t, c, c.locationStack.peek(), arm64.RegV30) - }, - verifyFnc: func(t *testing.T, env *compilerEnv) { - // Previous value on the V3 register must be saved onto the stack. - lo, hi := env.stack()[callFrameDataSizeInUint64], env.stack()[callFrameDataSizeInUint64+1] - require.Equal(t, uint64(1234), lo) - require.Equal(t, uint64(5678), hi) - }, - expStackPointerAfterShuffle: 4, - }, - } - - lanes := []uint64{1, 1, 1, 1, 0, 0, 0, 0, 10, 10, 10, 10, 0, 0, 0, 31} - v := [16]byte{0: 0xa, 1: 0xb, 10: 0xc} - w := [16]byte{0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 1} - exp := [16]byte{ - 0xb, 0xb, 0xb, 0xb, - 0xa, 0xa, 0xa, 0xa, - 0xc, 0xc, 0xc, 0xc, - 0xa, 0xa, 0xa, 1, - } - - for _, tc := range tests { - tc := tc - t.Run(tc.name, func(t *testing.T) { - env := newCompilerEnvironment() - compiler := env.requireNewCompiler(t, &wasm.FunctionType{}, newCompiler, - &wazeroir.CompilationResult{Memory: wazeroir.MemoryTypeStandard}) - - err := compiler.compilePreamble() - require.NoError(t, err) - - ac := compiler.(*arm64Compiler) - tc.init(t, ac) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(v[:8]), binary.LittleEndian.Uint64(v[8:])))) - require.NoError(t, err) - - vLocation := compiler.runtimeValueLocationStack().peek() - movValueRegisterToRegister(t, ac, vLocation, tc.vReg) - - err = compiler.compileV128Const(operationPtr(wazeroir.NewOperationV128Const(binary.LittleEndian.Uint64(w[:8]), binary.LittleEndian.Uint64(w[8:])))) - require.NoError(t, err) - - wLocation := compiler.runtimeValueLocationStack().peek() - movValueRegisterToRegister(t, ac, wLocation, tc.wReg) - - err = compiler.compileV128Shuffle(operationPtr(wazeroir.NewOperationV128Shuffle(lanes))) - require.NoError(t, err) - - requireRuntimeLocationStackPointerEqual(t, tc.expStackPointerAfterShuffle, compiler) - require.Equal(t, 1, len(compiler.runtimeValueLocationStack().usedRegisters.list())) - - err = compiler.compileReturnFunction() - require.NoError(t, err) - - code := asm.CodeSegment{} - defer func() { require.NoError(t, code.Unmap()) }() - - // Generate and run the code under test. - _, err = compiler.compile(code.NextCodeSection()) - require.NoError(t, err) - - env.exec(code.Bytes()) - - lo, hi := env.stackTopAsV128() - var actual [16]byte - binary.LittleEndian.PutUint64(actual[:8], lo) - binary.LittleEndian.PutUint64(actual[8:], hi) - require.Equal(t, exp, actual) - - tc.verifyFnc(t, env) - }) - } -} diff --git a/internal/engine/interpreter/interpreter.go b/internal/engine/interpreter/interpreter.go index caecfee38f..cb4c823472 100644 --- a/internal/engine/interpreter/interpreter.go +++ b/internal/engine/interpreter/interpreter.go @@ -92,6 +92,11 @@ func (e *moduleEngine) GetGlobalValue(wasm.Index) (lo, hi uint64) { panic("BUG: GetGlobalValue should never be called on interpreter mode") } +// SetGlobalValue implements the same method as documented on wasm.ModuleEngine. +func (e *moduleEngine) SetGlobalValue(idx wasm.Index, lo, hi uint64) { + panic("BUG: SetGlobalValue should never be called on interpreter mode") +} + // OwnsGlobals implements the same method as documented on wasm.ModuleEngine. func (e *moduleEngine) OwnsGlobals() bool { return false } @@ -212,16 +217,10 @@ type function struct { parent *compiledFunction } -// functionFromUintptr resurrects the original *function from the given uintptr +// functionFromReference resurrects the original *function from the given wasm.Reference // which comes from either funcref table or OpcodeRefFunc instruction. -func functionFromUintptr(ptr uintptr) *function { - // Wraps ptrs as the double pointer in order to avoid the unsafe access as detected by race detector. - // - // For example, if we have (*function)(unsafe.Pointer(ptr)) instead, then the race detector's "checkptr" - // subroutine wanrs as "checkptr: pointer arithmetic result points to invalid allocation" - // https://github.com/golang/go/blob/1ce7fcf139417d618c2730010ede2afb41664211/src/runtime/checkptr.go#L69 - var wrapped *uintptr = &ptr - return *(**function)(unsafe.Pointer(wrapped)) +func functionFromReference(ptr wasm.Reference) *function { + return (*function)(ptr) } type snapshot struct { @@ -497,7 +496,7 @@ func (e *moduleEngine) DoneInstantiation() {} // FunctionInstanceReference implements the same method as documented on wasm.ModuleEngine. func (e *moduleEngine) FunctionInstanceReference(funcIndex wasm.Index) wasm.Reference { - return uintptr(unsafe.Pointer(&e.functions[funcIndex])) + return unsafe.Pointer(&e.functions[funcIndex]) } // NewFunction implements the same method as documented on wasm.ModuleEngine. @@ -514,11 +513,11 @@ func (e *moduleEngine) LookupFunction(t *wasm.TableInstance, typeId wasm.Functio panic(wasmruntime.ErrRuntimeInvalidTableAccess) } rawPtr := t.References[tableOffset] - if rawPtr == 0 { + if rawPtr == nil { panic(wasmruntime.ErrRuntimeInvalidTableAccess) } - tf := functionFromUintptr(rawPtr) + tf := functionFromReference(rawPtr) if tf.typeID != typeId { panic(wasmruntime.ErrRuntimeIndirectCallTypeMismatch) } @@ -762,11 +761,11 @@ func (ce *callEngine) callNativeFunc(ctx context.Context, m *wasm.ModuleInstance panic(wasmruntime.ErrRuntimeInvalidTableAccess) } rawPtr := table.References[offset] - if rawPtr == 0 { + if rawPtr == nil { panic(wasmruntime.ErrRuntimeInvalidTableAccess) } - tf := functionFromUintptr(rawPtr) + tf := (*function)(rawPtr) if tf.typeID != typeIDs[op.U1] { panic(wasmruntime.ErrRuntimeIndirectCallTypeMismatch) } @@ -1769,7 +1768,7 @@ func (ce *callEngine) callNativeFunc(ctx context.Context, m *wasm.ModuleInstance panic(wasmruntime.ErrRuntimeInvalidTableAccess) } - ce.pushValue(uint64(table.References[offset])) + ce.pushValue(uint64(uintptr(table.References[offset]))) frame.pc++ case wazeroir.OperationKindTableSet: table := tables[op.U1] @@ -1780,7 +1779,7 @@ func (ce *callEngine) callNativeFunc(ctx context.Context, m *wasm.ModuleInstance panic(wasmruntime.ErrRuntimeInvalidTableAccess) } - table.References[offset] = uintptr(ref) // externrefs are opaque uint64. + table.References[offset] = asReference(ref) // externrefs are opaque uint64. frame.pc++ case wazeroir.OperationKindTableSize: table := tables[op.U1] @@ -1789,13 +1788,13 @@ func (ce *callEngine) callNativeFunc(ctx context.Context, m *wasm.ModuleInstance case wazeroir.OperationKindTableGrow: table := tables[op.U1] num, ref := ce.popValue(), ce.popValue() - ret := table.Grow(uint32(num), uintptr(ref)) + ret := table.Grow(uint32(num), asReference(ref)) ce.pushValue(uint64(ret)) frame.pc++ case wazeroir.OperationKindTableFill: table := tables[op.U1] num := ce.popValue() - ref := uintptr(ce.popValue()) + ref := asReference(ce.popValue()) offset := ce.popValue() if num+offset > uint64(len(table.References)) { panic(wasmruntime.ErrRuntimeInvalidTableAccess) @@ -4581,3 +4580,7 @@ func (ce *callEngine) callGoFuncWithStack(ctx context.Context, m *wasm.ModuleIns ce.stack = ce.stack[0 : len(ce.stack)-shrinkLen] } } + +func asReference(ptr uint64) wasm.Reference { + return unsafe.Pointer(uintptr(ptr)) +} diff --git a/internal/engine/wazevo/call_engine.go b/internal/engine/wazevo/call_engine.go index 6ddaca49d2..a3c1a66ba8 100644 --- a/internal/engine/wazevo/call_engine.go +++ b/internal/engine/wazevo/call_engine.go @@ -315,7 +315,7 @@ func (c *callEngine) callWithStack(ctx context.Context, paramResultStack []uint6 s := goCallStackView(c.execCtx.stackPointerBeforeGoCall) tableIndex, num, ref := uint32(s[0]), uint32(s[1]), uintptr(s[2]) table := mod.Tables[tableIndex] - s[0] = uint64(uint32(int32(table.Grow(num, ref)))) + s[0] = uint64(uint32(int32(table.Grow(num, unsafe.Pointer(ref))))) c.execCtx.exitCode = wazevoapi.ExitCodeOK afterGoFunctionCallEntrypoint(c.execCtx.goCallReturnAddress, c.execCtxPtr, uintptr(unsafe.Pointer(c.execCtx.stackPointerBeforeGoCall)), c.execCtx.framePointerBeforeGoCall) @@ -409,7 +409,7 @@ func (c *callEngine) callWithStack(ctx context.Context, paramResultStack []uint6 s := goCallStackView(c.execCtx.stackPointerBeforeGoCall) funcIndex := wasm.Index(s[0]) ref := mod.Engine.FunctionInstanceReference(funcIndex) - s[0] = uint64(ref) + s[0] = uint64(uintptr(ref)) c.execCtx.exitCode = wazevoapi.ExitCodeOK afterGoFunctionCallEntrypoint(c.execCtx.goCallReturnAddress, c.execCtxPtr, uintptr(unsafe.Pointer(c.execCtx.stackPointerBeforeGoCall)), c.execCtx.framePointerBeforeGoCall) diff --git a/internal/engine/wazevo/e2e_test.go b/internal/engine/wazevo/e2e_test.go index 6536f9159d..98ba2ce7a1 100644 --- a/internal/engine/wazevo/e2e_test.go +++ b/internal/engine/wazevo/e2e_test.go @@ -12,7 +12,6 @@ import ( "github.com/tetratelabs/wazero/api" "github.com/tetratelabs/wazero/experimental" "github.com/tetratelabs/wazero/experimental/logging" - "github.com/tetratelabs/wazero/experimental/opt" "github.com/tetratelabs/wazero/internal/engine/wazevo/testcases" "github.com/tetratelabs/wazero/internal/leb128" "github.com/tetratelabs/wazero/internal/testing/binaryencoding" @@ -854,7 +853,7 @@ func TestE2E(t *testing.T) { t.Run(name, func(t *testing.T) { cache, err := wazero.NewCompilationCacheWithDir(tmp) require.NoError(t, err) - config := opt.NewRuntimeConfigOptimizingCompiler().WithCompilationCache(cache) + config := wazero.NewRuntimeConfigCompiler().WithCompilationCache(cache) if tc.features != 0 { config = config.WithCoreFeatures(tc.features) } @@ -926,7 +925,7 @@ func TestE2E_host_functions(t *testing.T) { t.Run(tc.name, func(t *testing.T) { ctx := tc.ctx - config := opt.NewRuntimeConfigOptimizingCompiler() + config := wazero.NewRuntimeConfigCompiler() r := wazero.NewRuntimeWithConfig(ctx, config) defer func() { @@ -1008,7 +1007,7 @@ func TestE2E_host_functions(t *testing.T) { } func TestE2E_stores(t *testing.T) { - config := opt.NewRuntimeConfigOptimizingCompiler() + config := wazero.NewRuntimeConfigCompiler() ctx := context.Background() r := wazero.NewRuntimeWithConfig(ctx, config) @@ -1095,7 +1094,7 @@ func TestE2E_reexported_memory(t *testing.T) { CodeSection: []wasm.Code{{Body: []byte{wasm.OpcodeI32Const, 10, wasm.OpcodeMemoryGrow, 0, wasm.OpcodeEnd}}}, } - config := opt.NewRuntimeConfigOptimizingCompiler() + config := wazero.NewRuntimeConfigCompiler() ctx := context.Background() r := wazero.NewRuntimeWithConfig(ctx, config) @@ -1144,7 +1143,7 @@ func TestStackUnwind_panic_in_host(t *testing.T) { }, } - config := opt.NewRuntimeConfigOptimizingCompiler() + config := wazero.NewRuntimeConfigCompiler() ctx := context.Background() r := wazero.NewRuntimeWithConfig(ctx, config) @@ -1194,7 +1193,7 @@ func TestStackUnwind_unreachable(t *testing.T) { }, } - config := opt.NewRuntimeConfigOptimizingCompiler() + config := wazero.NewRuntimeConfigCompiler() ctx := context.Background() r := wazero.NewRuntimeWithConfig(ctx, config) defer func() { @@ -1216,7 +1215,7 @@ wasm stack trace: func TestListener_local(t *testing.T) { var buf bytes.Buffer - config := opt.NewRuntimeConfigOptimizingCompiler() + config := wazero.NewRuntimeConfigCompiler() ctx := context.WithValue(context.Background(), experimental.FunctionListenerFactoryKey{}, logging.NewLoggingListenerFactory(&buf)) r := wazero.NewRuntimeWithConfig(ctx, config) @@ -1244,7 +1243,7 @@ func TestListener_local(t *testing.T) { func TestListener_imported(t *testing.T) { var buf bytes.Buffer - config := opt.NewRuntimeConfigOptimizingCompiler() + config := wazero.NewRuntimeConfigCompiler() ctx := context.WithValue(context.Background(), experimental.FunctionListenerFactoryKey{}, logging.NewLoggingListenerFactory(&buf)) r := wazero.NewRuntimeWithConfig(ctx, config) @@ -1295,7 +1294,7 @@ func TestListener_long(t *testing.T) { }) var buf bytes.Buffer - config := opt.NewRuntimeConfigOptimizingCompiler() + config := wazero.NewRuntimeConfigCompiler() ctx := context.WithValue(context.Background(), experimental.FunctionListenerFactoryKey{}, logging.NewLoggingListenerFactory(&buf)) r := wazero.NewRuntimeWithConfig(ctx, config) @@ -1345,7 +1344,7 @@ func TestListener_long_as_is(t *testing.T) { }) var buf bytes.Buffer - config := opt.NewRuntimeConfigOptimizingCompiler() + config := wazero.NewRuntimeConfigCompiler() ctx := context.WithValue(context.Background(), experimental.FunctionListenerFactoryKey{}, logging.NewLoggingListenerFactory(&buf)) r := wazero.NewRuntimeWithConfig(ctx, config) @@ -1394,7 +1393,7 @@ func TestListener_long_many_consts(t *testing.T) { }) var buf bytes.Buffer - config := opt.NewRuntimeConfigOptimizingCompiler() + config := wazero.NewRuntimeConfigCompiler() ctx := context.WithValue(context.Background(), experimental.FunctionListenerFactoryKey{}, logging.NewLoggingListenerFactory(&buf)) r := wazero.NewRuntimeWithConfig(ctx, config) @@ -1419,7 +1418,7 @@ func TestListener_long_many_consts(t *testing.T) { // TestDWARF verifies that the DWARF based stack traces work as expected before/after compilation cache. func TestDWARF(t *testing.T) { - config := opt.NewRuntimeConfigOptimizingCompiler() + config := wazero.NewRuntimeConfigCompiler() ctx := context.Background() bin := dwarftestdata.ZigWasm diff --git a/internal/engine/wazevo/module_engine.go b/internal/engine/wazevo/module_engine.go index b72ac2b162..8db23be548 100644 --- a/internal/engine/wazevo/module_engine.go +++ b/internal/engine/wazevo/module_engine.go @@ -213,6 +213,17 @@ func (m *moduleEngine) GetGlobalValue(i wasm.Index) (lo, hi uint64) { return binary.LittleEndian.Uint64(buf), binary.LittleEndian.Uint64(buf[8:]) } +// SetGlobalValue implements the same method as documented on wasm.ModuleEngine. +func (m *moduleEngine) SetGlobalValue(i wasm.Index, lo, hi uint64) { + offset := m.parent.offsets.GlobalInstanceOffset(i) + buf := m.opaque[offset:] + if i < m.module.Source.ImportGlobalCount { + panic("GetGlobalValue should not be called for imported globals") + } + binary.LittleEndian.PutUint64(buf, lo) + binary.LittleEndian.PutUint64(buf[8:], hi) +} + // OwnsGlobals implements the same method as documented on wasm.ModuleEngine. func (m *moduleEngine) OwnsGlobals() bool { return true } @@ -294,7 +305,7 @@ func (m *moduleEngine) DoneInstantiation() { func (m *moduleEngine) FunctionInstanceReference(funcIndex wasm.Index) wasm.Reference { if funcIndex < m.module.Source.ImportFunctionCount { begin, _, _ := m.parent.offsets.ImportedFunctionOffset(funcIndex) - return uintptr(unsafe.Pointer(&m.opaque[begin])) + return unsafe.Pointer(&m.opaque[begin]) } localIndex := funcIndex - m.module.Source.ImportFunctionCount p := m.parent @@ -308,7 +319,7 @@ func (m *moduleEngine) FunctionInstanceReference(funcIndex wasm.Index) wasm.Refe indexInModule: funcIndex, } m.localFunctionInstances = append(m.localFunctionInstances, lf) - return uintptr(unsafe.Pointer(lf)) + return unsafe.Pointer(lf) } // LookupFunction implements wasm.ModuleEngine. @@ -317,11 +328,11 @@ func (m *moduleEngine) LookupFunction(t *wasm.TableInstance, typeId wasm.Functio panic(wasmruntime.ErrRuntimeInvalidTableAccess) } rawPtr := t.References[tableOffset] - if rawPtr == 0 { + if rawPtr == nil { panic(wasmruntime.ErrRuntimeInvalidTableAccess) } - tf := wazevoapi.PtrFromUintptr[functionInstance](rawPtr) + tf := (*functionInstance)(rawPtr) if tf.typeID != typeId { panic(wasmruntime.ErrRuntimeIndirectCallTypeMismatch) } diff --git a/internal/integration_test/bench/hostfunc_bench_test.go b/internal/integration_test/bench/hostfunc_bench_test.go index cd0a597c5e..5bfcd2a3c0 100644 --- a/internal/integration_test/bench/hostfunc_bench_test.go +++ b/internal/integration_test/bench/hostfunc_bench_test.go @@ -7,9 +7,10 @@ import ( "math" "testing" + "github.com/tetratelabs/wazero" "github.com/tetratelabs/wazero/api" - "github.com/tetratelabs/wazero/internal/engine/compiler" "github.com/tetratelabs/wazero/internal/platform" + "github.com/tetratelabs/wazero/internal/testing/binaryencoding" "github.com/tetratelabs/wazero/internal/testing/require" "github.com/tetratelabs/wazero/internal/wasm" ) @@ -130,67 +131,37 @@ func getCallEngine(m *wasm.ModuleInstance, name string) (ce api.Function) { } func setupHostCallBench(requireNoError func(error)) *wasm.ModuleInstance { - eng := compiler.NewEngine(context.Background(), api.CoreFeaturesV2, nil) - - ft := wasm.FunctionType{ - Params: []wasm.ValueType{wasm.ValueTypeI32}, - Results: []wasm.ValueType{wasm.ValueTypeF32}, - ParamNumInUint64: 1, ResultNumInUint64: 1, - } - - // Build the host module. - hostModule := &wasm.Module{ - TypeSection: []wasm.FunctionType{ft}, - FunctionSection: []wasm.Index{0, 0}, - CodeSection: []wasm.Code{ - { - GoFunc: api.GoModuleFunc(func(_ context.Context, mod api.Module, stack []uint64) { - ret, ok := mod.Memory().ReadUint32Le(uint32(stack[0])) - if !ok { - panic("couldn't read memory") - } - stack[0] = uint64(ret) - }), - }, - wasm.MustParseGoReflectFuncCode( - func(_ context.Context, m api.Module, pos uint32) float32 { - ret, ok := m.Memory().ReadUint32Le(pos) - if !ok { - panic("couldn't read memory") - } - return math.Float32frombits(ret) - }, - ), - }, - ExportSection: []wasm.Export{ - {Name: "go", Type: wasm.ExternTypeFunc, Index: 0}, - {Name: "go-reflect", Type: wasm.ExternTypeFunc, Index: 1}, - }, - Exports: map[string]*wasm.Export{ - "go": {Name: "go", Type: wasm.ExternTypeFunc, Index: 0}, - "go-reflect": {Name: "go-reflect", Type: wasm.ExternTypeFunc, Index: 1}, - }, - ID: wasm.ModuleID{1, 2, 3, 4, 5}, - } - - host := &wasm.ModuleInstance{ModuleName: "host", TypeIDs: []wasm.FunctionTypeID{0}} - host.Exports = hostModule.Exports - - err := eng.CompileModule(testCtx, hostModule, nil, false) - requireNoError(err) - - hostMe, err := eng.NewModuleEngine(hostModule, host) + ctx := context.Background() + r := wazero.NewRuntime(ctx) + + const i32, f32 = api.ValueTypeI32, api.ValueTypeF32 + _, err := r.NewHostModuleBuilder("host"). + NewFunctionBuilder().WithGoModuleFunction(api.GoModuleFunc(func(ctx context.Context, mod api.Module, stack []uint64) { + ret, ok := mod.Memory().ReadUint32Le(uint32(stack[0])) + if !ok { + panic("couldn't read memory") + } + stack[0] = uint64(ret) + }), []api.ValueType{i32}, []api.ValueType{f32}).Export("go"). + NewFunctionBuilder().WithFunc(func(ctx context.Context, m api.Module, pos uint32) float32 { + ret, ok := m.Memory().ReadUint32Le(pos) + if !ok { + panic("couldn't read memory") + } + return math.Float32frombits(ret) + }).Export("go-reflect").Instantiate(ctx) requireNoError(err) - linkModuleToEngine(host, hostMe) // Build the importing module. - importingModule := &wasm.Module{ - ImportFunctionCount: 2, - TypeSection: []wasm.FunctionType{ft}, + importingModuleBin := binaryencoding.EncodeModule(&wasm.Module{ + TypeSection: []wasm.FunctionType{{ + Params: []wasm.ValueType{i32}, + Results: []wasm.ValueType{f32}, + }}, ImportSection: []wasm.Import{ // Placeholders for imports from hostModule. - {Type: wasm.ExternTypeFunc}, - {Type: wasm.ExternTypeFunc}, + {Type: wasm.ExternTypeFunc, Module: "host", Name: "go"}, + {Type: wasm.ExternTypeFunc, Module: "host", Name: "go-reflect"}, }, FunctionSection: []wasm.Index{0, 0}, ExportSection: []wasm.Export{ @@ -205,27 +176,10 @@ func setupHostCallBench(requireNoError func(error)) *wasm.ModuleInstance { {Body: []byte{wasm.OpcodeLocalGet, 0, wasm.OpcodeCall, 0, wasm.OpcodeEnd}}, // Calling the index 0 = host.go. {Body: []byte{wasm.OpcodeLocalGet, 0, wasm.OpcodeCall, 1, wasm.OpcodeEnd}}, // Calling the index 1 = host.go-reflect. }, - // Indicates that this module has a memory so that compilers are able to assemble memory-related initialization. MemorySection: &wasm.Memory{Min: 1}, - ID: wasm.ModuleID{1}, - } - - err = eng.CompileModule(testCtx, importingModule, nil, false) - requireNoError(err) - - importing := &wasm.ModuleInstance{TypeIDs: []wasm.FunctionTypeID{0}} - importing.Exports = importingModule.Exports + }) - importingMe, err := eng.NewModuleEngine(importingModule, importing) + importing, err := r.Instantiate(ctx, importingModuleBin) requireNoError(err) - linkModuleToEngine(importing, importingMe) - importingMe.ResolveImportedFunction(0, 0, hostMe) - importingMe.ResolveImportedFunction(1, 1, hostMe) - - importing.MemoryInstance = &wasm.MemoryInstance{Buffer: make([]byte, wasm.MemoryPageSize), Min: 1, Cap: 1, Max: 1} - return importing -} - -func linkModuleToEngine(module *wasm.ModuleInstance, me wasm.ModuleEngine) { - module.Engine = me + return importing.(*wasm.ModuleInstance) } diff --git a/internal/integration_test/engine/adhoc_test.go b/internal/integration_test/engine/adhoc_test.go index 30db57da52..c678710efb 100644 --- a/internal/integration_test/engine/adhoc_test.go +++ b/internal/integration_test/engine/adhoc_test.go @@ -7,6 +7,7 @@ import ( "errors" "fmt" "math" + "runtime" "strconv" "strings" "testing" @@ -17,7 +18,6 @@ import ( "github.com/tetratelabs/wazero/api" "github.com/tetratelabs/wazero/experimental" "github.com/tetratelabs/wazero/experimental/logging" - "github.com/tetratelabs/wazero/experimental/opt" "github.com/tetratelabs/wazero/experimental/table" "github.com/tetratelabs/wazero/internal/leb128" "github.com/tetratelabs/wazero/internal/platform" @@ -72,6 +72,7 @@ var tests = map[string]testCase{ "many params many results / main / listener": {f: testManyParamsResultsMainListener}, "many params many results / call_many_consts_and_pick_last_vector": {f: testManyParamsResultsCallManyConstsAndPickLastVector}, "many params many results / call_many_consts_and_pick_last_vector / listener": {f: testManyParamsResultsCallManyConstsAndPickLastVectorListener}, + "linking a closed module should not segfault": {f: testLinking}, } func TestEngineCompiler(t *testing.T) { @@ -92,14 +93,6 @@ const i32, i64, f32, f64, v128 = wasm.ValueTypeI32, wasm.ValueTypeI64, wasm.Valu var memoryCapacityPages = uint32(2) -func TestEngineWazevo(t *testing.T) { - if !platform.CompilerSupported() { - t.Skip() - } - config := opt.NewRuntimeConfigOptimizingCompiler() - runAllTests(t, tests, config.WithCloseOnContextDone(true), true) -} - func runAllTests(t *testing.T, tests map[string]testCase, config wazero.RuntimeConfig, isWazevo bool) { for name, tc := range tests { name := name @@ -132,6 +125,10 @@ var ( infiniteLoopWasm []byte //go:embed testdata/huge_call_stack_unwind.wasm hugeCallStackUnwind []byte + //go:embed testdata/linking1.wasm + linking1 []byte + //go:embed testdata/linking2.wasm + linking2 []byte ) func testEnsureTerminationOnClose(t *testing.T, r wazero.Runtime) { @@ -2183,3 +2180,34 @@ wasm stack trace: .$0() ... maybe followed by omitted frames`, err.Error()) } + +// testLinking links two modules where the first exports a table and the second module imports it, +// overwriting one of the table entries with one of its functions. +// The first module exposes a function that invokes the functionref in the table. +// If the functionref belongs to failed or closed module, then the call should not fail. +func testLinking(t *testing.T, r wazero.Runtime) { + if !platform.CompilerSupported() { + t.Skip() + } + ctx := context.Background() + // Instantiate the first module. + mod, err := r.InstantiateWithConfig(ctx, linking1, wazero.NewModuleConfig().WithName("Ms")) + defer mod.Close(ctx) //nolint + require.NoError(t, err) + // The second module builds successfully. + m, err := r.CompileModule(ctx, linking2) + require.NoError(t, err) + // The second module instantiates and sets the table[0] field to point to its own $f function. + _, err = r.InstantiateModule(ctx, m, wazero.NewModuleConfig()) + // However it traps upon instantiation. + require.Error(t, err) + m.Close(ctx) + // Force a GC cycle. This should not cause the memory segment to become invalid. + // If the segment is invalid, the next function call will SIGSEGV. + runtime.GC() + time.Sleep(200 * time.Millisecond) + // The result is expected to be 0xdead, i.e., the result of linking2.$f. + res, err := mod.ExportedFunction("get table[0]").Call(ctx) + require.NoError(t, err) + require.Equal(t, uint64(0xdead), res[0]) +} diff --git a/internal/integration_test/engine/dwarf_test.go b/internal/integration_test/engine/dwarf_test.go index b477013fb5..fa8670ff3f 100644 --- a/internal/integration_test/engine/dwarf_test.go +++ b/internal/integration_test/engine/dwarf_test.go @@ -7,7 +7,6 @@ import ( "testing" "github.com/tetratelabs/wazero" - "github.com/tetratelabs/wazero/experimental/opt" "github.com/tetratelabs/wazero/imports/wasi_snapshot_preview1" "github.com/tetratelabs/wazero/internal/platform" "github.com/tetratelabs/wazero/internal/testing/dwarftestdata" @@ -32,14 +31,6 @@ func TestEngineInterpreter_DWARF(t *testing.T) { runAllTests(t, dwarfTests, wazero.NewRuntimeConfigInterpreter(), false) } -func TestEngineWazevo_DWARF(t *testing.T) { - if !platform.CompilerSupported() { - t.Skip() - } - config := opt.NewRuntimeConfigOptimizingCompiler() - runAllTests(t, dwarfTests, config, true) -} - func testTinyGoDWARF(t *testing.T, r wazero.Runtime) { runDWARFTest(t, r, dwarftestdata.TinyGoWasm, `module[] function[_start] failed: wasm error: unreachable wasm stack trace: diff --git a/internal/integration_test/engine/hammer_test.go b/internal/integration_test/engine/hammer_test.go index 3189550a1f..6b8191f63d 100644 --- a/internal/integration_test/engine/hammer_test.go +++ b/internal/integration_test/engine/hammer_test.go @@ -7,7 +7,6 @@ import ( "github.com/tetratelabs/wazero" "github.com/tetratelabs/wazero/api" - "github.com/tetratelabs/wazero/experimental/opt" "github.com/tetratelabs/wazero/internal/platform" "github.com/tetratelabs/wazero/internal/testing/hammer" "github.com/tetratelabs/wazero/internal/testing/require" @@ -16,8 +15,9 @@ import ( var hammers = map[string]testCase{ // Tests here are similar to what's described in /RATIONALE.md, but deviate as they involve blocking functions. - "close importing module while in use": {f: closeImportingModuleWhileInUse}, - "close imported module while in use": {f: closeImportedModuleWhileInUse}, + "close importing module while in use": {f: closeImportingModuleWhileInUse}, + "close imported module while in use": {f: closeImportedModuleWhileInUse}, + "linking a closed module should not segfault": {f: testLinkingHammer}, } func TestEngineCompiler_hammer(t *testing.T) { @@ -31,14 +31,6 @@ func TestEngineInterpreter_hammer(t *testing.T) { runAllTests(t, hammers, wazero.NewRuntimeConfigInterpreter(), false) } -func TestEngineWazevo_hammer(t *testing.T) { - if !platform.CompilerSupported() { - t.Skip() - } - c := opt.NewRuntimeConfigOptimizingCompiler() - runAllTests(t, hammers, c, true) -} - func closeImportingModuleWhileInUse(t *testing.T, r wazero.Runtime) { closeModuleWhileInUse(t, r, func(imported, importing api.Module) (api.Module, api.Module) { // Close the importing module, despite calls being in-flight. @@ -125,6 +117,19 @@ func closeModuleWhileInUse(t *testing.T, r wazero.Runtime, closeFn func(imported requireFunctionCall(t, importing.ExportedFunction("call_return_input")) } +// testLinkingHammer links two modules where the first exports a table and the second module imports it, +// overwriting one of the table entries with one of its functions. +// The first module exposes a function that invokes the functionref in the table. +// If the functionref belongs to failed or closed module, then the call should not fail. +func testLinkingHammer(t *testing.T, r wazero.Runtime) { + if !platform.CompilerSupported() { + t.Skip() + } + hammer.NewHammer(t, 1, 10).Run(func(name string) { + testLinking(t, r) + }, func() {}) +} + func requireFunctionCall(t *testing.T, fn api.Function) { res, err := fn.Call(testCtx, 3) require.NoError(t, err) diff --git a/internal/integration_test/engine/memleak_test.go b/internal/integration_test/engine/memleak_test.go index 8401b99789..7ec97774f0 100644 --- a/internal/integration_test/engine/memleak_test.go +++ b/internal/integration_test/engine/memleak_test.go @@ -10,7 +10,6 @@ import ( "time" "github.com/tetratelabs/wazero" - "github.com/tetratelabs/wazero/experimental/opt" "github.com/tetratelabs/wazero/internal/platform" ) @@ -23,50 +22,32 @@ func TestMemoryLeak(t *testing.T) { t.Skip() } - for _, tc := range []struct { - name string - isWazevo bool - }{ - {"compiler", false}, - {"wazevo", true}, - } { - tc := tc + duration := 5 * time.Second + t.Logf("running memory leak test for %s", duration) - t.Run(tc.name, func(t *testing.T) { - duration := 5 * time.Second - t.Logf("running memory leak test for %s", duration) + ctx, cancel := context.WithTimeout(context.Background(), duration) + defer cancel() - ctx, cancel := context.WithTimeout(context.Background(), duration) - defer cancel() - - for ctx.Err() == nil { - if err := testMemoryLeakInstantiateRuntimeAndModule(tc.isWazevo); err != nil { - log.Panicln(err) - } - } + for ctx.Err() == nil { + if err := testMemoryLeakInstantiateRuntimeAndModule(); err != nil { + log.Panicln(err) + } + } - var stats runtime.MemStats - runtime.GC() - runtime.ReadMemStats(&stats) + var stats runtime.MemStats + runtime.GC() + runtime.ReadMemStats(&stats) - if stats.Alloc > (100 * 1024 * 1024) { - t.Errorf("wazero used more than 100 MiB after running the test for %s (alloc=%d)", duration, stats.Alloc) - } - fmt.Println(stats.Alloc) - }) + if stats.Alloc > (100 * 1024 * 1024) { + t.Errorf("wazero used more than 100 MiB after running the test for %s (alloc=%d)", duration, stats.Alloc) } + fmt.Println(stats.Alloc) } -func testMemoryLeakInstantiateRuntimeAndModule(isWazevo bool) error { +func testMemoryLeakInstantiateRuntimeAndModule() error { ctx := context.Background() - var r wazero.Runtime - if isWazevo { - c := opt.NewRuntimeConfigOptimizingCompiler() - r = wazero.NewRuntimeWithConfig(ctx, c) - } else { - r = wazero.NewRuntime(ctx) - } + r := wazero.NewRuntime(ctx) defer r.Close(ctx) hostBuilder := r.NewHostModuleBuilder("test") diff --git a/internal/integration_test/engine/testdata/linking1.wasm b/internal/integration_test/engine/testdata/linking1.wasm new file mode 100644 index 0000000000..cd57daf2e1 Binary files /dev/null and b/internal/integration_test/engine/testdata/linking1.wasm differ diff --git a/internal/integration_test/engine/testdata/linking1.wat b/internal/integration_test/engine/testdata/linking1.wat new file mode 100644 index 0000000000..bcf50d64ed --- /dev/null +++ b/internal/integration_test/engine/testdata/linking1.wat @@ -0,0 +1,12 @@ +;; Store is modified if the start function traps. +(module $Ms + (type $t (func (result i32))) + (memory (export "memory") 1) + (table (export "table") 1 funcref) + (func (export "get memory[0]") (type $t) + (i32.load8_u (i32.const 0)) + ) + (func (export "get table[0]") (type $t) + (call_indirect (type $t) (i32.const 0)) + ) +) diff --git a/internal/integration_test/engine/testdata/linking2.wasm b/internal/integration_test/engine/testdata/linking2.wasm new file mode 100644 index 0000000000..22957bf342 Binary files /dev/null and b/internal/integration_test/engine/testdata/linking2.wasm differ diff --git a/internal/integration_test/engine/testdata/linking2.wat b/internal/integration_test/engine/testdata/linking2.wat new file mode 100644 index 0000000000..832cf13a32 --- /dev/null +++ b/internal/integration_test/engine/testdata/linking2.wat @@ -0,0 +1,14 @@ + (module + (import "Ms" "memory" (memory 1)) + (import "Ms" "table" (table 1 funcref)) + (data (i32.const 0) "hello") + (elem (i32.const 0) $f) + (func $f (result i32) + (i32.const 0xdead) + ) + (func $main + (unreachable) + ) + (start $main) + ) + diff --git a/internal/integration_test/engine/threads_test.go b/internal/integration_test/engine/threads_test.go index c6a2a44c0a..338b397526 100644 --- a/internal/integration_test/engine/threads_test.go +++ b/internal/integration_test/engine/threads_test.go @@ -4,10 +4,9 @@ import ( _ "embed" "testing" - wazero "github.com/tetratelabs/wazero" + "github.com/tetratelabs/wazero" "github.com/tetratelabs/wazero/api" "github.com/tetratelabs/wazero/experimental" - "github.com/tetratelabs/wazero/experimental/opt" "github.com/tetratelabs/wazero/internal/platform" "github.com/tetratelabs/wazero/internal/testing/hammer" "github.com/tetratelabs/wazero/internal/testing/require" @@ -65,13 +64,6 @@ func TestThreadsInterpreter_hammer(t *testing.T) { runAllTests(t, threadTests, wazero.NewRuntimeConfigInterpreter().WithCoreFeatures(api.CoreFeaturesV2|experimental.CoreFeaturesThreads), false) } -func TestThreadsWazevo(t *testing.T) { - if !platform.CompilerSupported() { - t.Skip() - } - runAllTests(t, threadTests, opt.NewRuntimeConfigOptimizingCompiler().WithCoreFeatures(api.CoreFeaturesV2|experimental.CoreFeaturesThreads), false) -} - func incrementGuardedByMutex(t *testing.T, r wazero.Runtime) { P := 8 // max count of goroutines if testing.Short() { // Adjust down if `-test.short` diff --git a/internal/integration_test/filecache/filecache_test.go b/internal/integration_test/filecache/filecache_test.go index 88bb095012..b7d7d8eea4 100644 --- a/internal/integration_test/filecache/filecache_test.go +++ b/internal/integration_test/filecache/filecache_test.go @@ -14,7 +14,6 @@ import ( "github.com/tetratelabs/wazero/api" "github.com/tetratelabs/wazero/experimental" "github.com/tetratelabs/wazero/experimental/logging" - "github.com/tetratelabs/wazero/experimental/opt" "github.com/tetratelabs/wazero/internal/integration_test/spectest" v1 "github.com/tetratelabs/wazero/internal/integration_test/spectest/v1" "github.com/tetratelabs/wazero/internal/platform" @@ -30,14 +29,6 @@ func TestFileCache_compiler(t *testing.T) { runAllFileCacheTests(t, wazero.NewRuntimeConfigCompiler()) } -func TestFileCache_wazevo(t *testing.T) { - if !platform.CompilerSupported() { - return - } - config := opt.NewRuntimeConfigOptimizingCompiler() - runAllFileCacheTests(t, config) -} - func runAllFileCacheTests(t *testing.T, config wazero.RuntimeConfig) { t.Run("spectest", func(t *testing.T) { testSpecTestCompilerCache(t, config) diff --git a/internal/integration_test/fuzz/wazerolib/extern.go b/internal/integration_test/fuzz/wazerolib/extern.go index b00d3beabb..cd57b641a6 100644 --- a/internal/integration_test/fuzz/wazerolib/extern.go +++ b/internal/integration_test/fuzz/wazerolib/extern.go @@ -9,7 +9,6 @@ import ( "unsafe" "github.com/tetratelabs/wazero" - "github.com/tetratelabs/wazero/experimental/opt" "github.com/tetratelabs/wazero/internal/leb128" "github.com/tetratelabs/wazero/internal/testing/binaryencoding" "github.com/tetratelabs/wazero/internal/testing/nodiff" @@ -122,7 +121,7 @@ func test_signal_stack() { }, }) ctx := context.Background() - config := opt.NewRuntimeConfigOptimizingCompiler() + config := wazero.NewRuntimeConfigCompiler() r := wazero.NewRuntimeWithConfig(ctx, config) module, err := r.Instantiate(ctx, bin) if err != nil { diff --git a/internal/integration_test/fuzz/wazerolib/validate.go b/internal/integration_test/fuzz/wazerolib/validate.go index 4c5c187171..9b4c5757ae 100644 --- a/internal/integration_test/fuzz/wazerolib/validate.go +++ b/internal/integration_test/fuzz/wazerolib/validate.go @@ -4,13 +4,12 @@ import ( "context" "github.com/tetratelabs/wazero" - "github.com/tetratelabs/wazero/experimental/opt" ) // Ensure that validation and compilation do not panic! func tryCompile(wasmBin []byte) { ctx := context.Background() - r := wazero.NewRuntimeWithConfig(ctx, opt.NewRuntimeConfigOptimizingCompiler()) + r := wazero.NewRuntimeWithConfig(ctx, wazero.NewRuntimeConfigCompiler()) defer func() { if err := r.Close(context.Background()); err != nil { panic(err) diff --git a/internal/integration_test/fuzzcases/fuzzcases_test.go b/internal/integration_test/fuzzcases/fuzzcases_test.go index 6253fa0b0c..0aff417854 100644 --- a/internal/integration_test/fuzzcases/fuzzcases_test.go +++ b/internal/integration_test/fuzzcases/fuzzcases_test.go @@ -11,7 +11,6 @@ import ( "github.com/tetratelabs/wazero" "github.com/tetratelabs/wazero/api" - "github.com/tetratelabs/wazero/experimental/opt" "github.com/tetratelabs/wazero/internal/platform" "github.com/tetratelabs/wazero/internal/testing/binaryencoding" "github.com/tetratelabs/wazero/internal/testing/nodiff" @@ -52,22 +51,9 @@ func runWithInterpreter(t *testing.T, runner func(t *testing.T, r wazero.Runtime }) } -func runWithWazevo(t *testing.T, runner func(t *testing.T, r wazero.Runtime)) { - if !platform.CompilerSupported() { - return - } - t.Run("wazevo", func(t *testing.T) { - config := opt.NewRuntimeConfigOptimizingCompiler() - r := wazero.NewRuntimeWithConfig(ctx, config) - defer r.Close(ctx) - runner(t, r) - }) -} - func run(t *testing.T, runner func(t *testing.T, r wazero.Runtime)) { runWithInterpreter(t, runner) runWithCompiler(t, runner) - runWithWazevo(t, runner) } // Test695 requires two functions to exit with "out of bounds memory access" consistently across the implementations. @@ -1051,7 +1037,7 @@ func Test2112(t *testing.T) { return } - r := wazero.NewRuntimeWithConfig(context.Background(), opt.NewRuntimeConfigOptimizingCompiler()) + r := wazero.NewRuntimeWithConfig(context.Background(), wazero.NewRuntimeConfigCompiler()) _, err = r.Instantiate(ctx, bin) require.Error(t, err) require.Contains(t, err.Error(), "invalid function[0]: unknown misc opcode 0x30") diff --git a/internal/integration_test/libsodium/bench_test.go b/internal/integration_test/libsodium/bench_test.go index 8ae93da252..c75c6fdbd3 100644 --- a/internal/integration_test/libsodium/bench_test.go +++ b/internal/integration_test/libsodium/bench_test.go @@ -9,8 +9,8 @@ import ( "testing" "github.com/tetratelabs/wazero" - "github.com/tetratelabs/wazero/experimental/opt" "github.com/tetratelabs/wazero/imports/wasi_snapshot_preview1" + "github.com/tetratelabs/wazero/internal/platform" "github.com/tetratelabs/wazero/internal/testing/require" ) @@ -18,6 +18,10 @@ import ( var tests embed.FS func BenchmarkLibsodium(b *testing.B) { + if !platform.CompilerSupported() { + b.Skip() + } + cases, err := tests.ReadDir("testdata") require.NoError(b, err) if len(cases) < 10 { @@ -25,7 +29,7 @@ func BenchmarkLibsodium(b *testing.B) { } ctx := context.Background() - r := wazero.NewRuntimeWithConfig(ctx, opt.NewRuntimeConfigOptimizingCompiler()) + r := wazero.NewRuntimeWithConfig(ctx, wazero.NewRuntimeConfigCompiler()) defer r.Close(ctx) wasi_snapshot_preview1.MustInstantiate(ctx, r) diff --git a/internal/integration_test/spectest/threads/spec_test.go b/internal/integration_test/spectest/threads/spec_test.go index b0744e5bf6..df5a19d953 100644 --- a/internal/integration_test/spectest/threads/spec_test.go +++ b/internal/integration_test/spectest/threads/spec_test.go @@ -8,7 +8,6 @@ import ( "github.com/tetratelabs/wazero" "github.com/tetratelabs/wazero/api" "github.com/tetratelabs/wazero/experimental" - "github.com/tetratelabs/wazero/experimental/opt" "github.com/tetratelabs/wazero/internal/integration_test/spectest" "github.com/tetratelabs/wazero/internal/platform" ) @@ -29,10 +28,3 @@ func TestCompiler(t *testing.T) { func TestInterpreter(t *testing.T) { spectest.Run(t, testcases, context.Background(), wazero.NewRuntimeConfigInterpreter().WithCoreFeatures(enabledFeatures)) } - -func TestWazevo(t *testing.T) { - if !platform.CompilerSupported() { - t.Skip() - } - spectest.Run(t, testcases, context.Background(), opt.NewRuntimeConfigOptimizingCompiler().WithCoreFeatures(enabledFeatures)) -} diff --git a/internal/integration_test/spectest/v1/spec_test.go b/internal/integration_test/spectest/v1/spec_test.go index b8ce7a5a3b..d59bc1ec99 100644 --- a/internal/integration_test/spectest/v1/spec_test.go +++ b/internal/integration_test/spectest/v1/spec_test.go @@ -6,7 +6,6 @@ import ( "github.com/tetratelabs/wazero" "github.com/tetratelabs/wazero/api" - "github.com/tetratelabs/wazero/experimental/opt" "github.com/tetratelabs/wazero/internal/integration_test/spectest" "github.com/tetratelabs/wazero/internal/platform" ) @@ -21,11 +20,3 @@ func TestCompiler(t *testing.T) { func TestInterpreter(t *testing.T) { spectest.Run(t, Testcases, context.Background(), wazero.NewRuntimeConfigInterpreter().WithCoreFeatures(api.CoreFeaturesV1)) } - -func TestWazevo(t *testing.T) { - if !platform.CompilerSupported() { - t.Skip() - } - c := opt.NewRuntimeConfigOptimizingCompiler().WithCoreFeatures(api.CoreFeaturesV1) - spectest.Run(t, Testcases, context.Background(), c) -} diff --git a/internal/integration_test/spectest/v2/spec_test.go b/internal/integration_test/spectest/v2/spec_test.go index b270ed227a..55cbfbedb8 100644 --- a/internal/integration_test/spectest/v2/spec_test.go +++ b/internal/integration_test/spectest/v2/spec_test.go @@ -6,7 +6,6 @@ import ( "github.com/tetratelabs/wazero" "github.com/tetratelabs/wazero/api" - "github.com/tetratelabs/wazero/experimental/opt" "github.com/tetratelabs/wazero/internal/integration_test/spectest" "github.com/tetratelabs/wazero/internal/platform" ) @@ -23,10 +22,3 @@ func TestCompiler(t *testing.T) { func TestInterpreter(t *testing.T) { spectest.Run(t, Testcases, context.Background(), wazero.NewRuntimeConfigInterpreter().WithCoreFeatures(enabledFeatures)) } - -func TestWazevo(t *testing.T) { - if !platform.CompilerSupported() { - t.Skip() - } - spectest.Run(t, Testcases, context.Background(), opt.NewRuntimeConfigOptimizingCompiler().WithCoreFeatures(enabledFeatures)) -} diff --git a/internal/integration_test/stdlibs/README.md b/internal/integration_test/stdlibs/README.md index 380856b260..81a7d8573e 100644 --- a/internal/integration_test/stdlibs/README.md +++ b/internal/integration_test/stdlibs/README.md @@ -1,7 +1,7 @@ # Stdlibs benchmarks This directory contains a Makefile to build (a subset of) the stdlibs for Zig, TinyGo and Go (wasip1) -and test them against the baseline compiler and the optimizing compiler. +and test them against the compiler. ## Requirements @@ -15,7 +15,7 @@ First, build the test suite (the Zig source root has to be set explicitly): make all zigroot=/path/to/zig/source -Then you can run the test suite against the baseline compiler and the optimizing compiler; e.g.: +Then you can run the test suite against the compiler; e.g.: go test -bench=. diff --git a/internal/integration_test/stdlibs/bench_test.go b/internal/integration_test/stdlibs/bench_test.go index f90542c3dd..b11275b9d3 100644 --- a/internal/integration_test/stdlibs/bench_test.go +++ b/internal/integration_test/stdlibs/bench_test.go @@ -11,43 +11,24 @@ import ( "testing" "github.com/tetratelabs/wazero" - "github.com/tetratelabs/wazero/experimental/opt" "github.com/tetratelabs/wazero/imports/wasi_snapshot_preview1" "github.com/tetratelabs/wazero/internal/testing/require" "github.com/tetratelabs/wazero/sys" ) func BenchmarkZig(b *testing.B) { - b.Run("optimizing", func(b *testing.B) { - c := opt.NewRuntimeConfigOptimizingCompiler() - runtBenches(b, context.Background(), c, zigTestCase) - }) - b.Run("baseline", func(b *testing.B) { - c := wazero.NewRuntimeConfigCompiler() - runtBenches(b, context.Background(), c, zigTestCase) - }) + c := wazero.NewRuntimeConfigCompiler() + runtBenches(b, context.Background(), c, zigTestCase) } func BenchmarkTinyGo(b *testing.B) { - b.Run("optimizing", func(b *testing.B) { - c := opt.NewRuntimeConfigOptimizingCompiler() - runtBenches(b, context.Background(), c, tinyGoTestCase) - }) - b.Run("baseline", func(b *testing.B) { - c := wazero.NewRuntimeConfigCompiler() - runtBenches(b, context.Background(), c, tinyGoTestCase) - }) + c := wazero.NewRuntimeConfigCompiler() + runtBenches(b, context.Background(), c, tinyGoTestCase) } func BenchmarkWasip1(b *testing.B) { - b.Run("optimizing", func(b *testing.B) { - c := opt.NewRuntimeConfigOptimizingCompiler() - runtBenches(b, context.Background(), c, wasip1TestCase) - }) - b.Run("baseline", func(b *testing.B) { - c := wazero.NewRuntimeConfigCompiler() - runtBenches(b, context.Background(), c, wasip1TestCase) - }) + c := wazero.NewRuntimeConfigCompiler() + runtBenches(b, context.Background(), c, wasip1TestCase) } type testCase struct { diff --git a/internal/testing/nodiff/nodiff.go b/internal/testing/nodiff/nodiff.go index 6a19639ee4..8364fcbbe1 100644 --- a/internal/testing/nodiff/nodiff.go +++ b/internal/testing/nodiff/nodiff.go @@ -14,7 +14,6 @@ import ( "github.com/tetratelabs/wazero/api" "github.com/tetratelabs/wazero/experimental" "github.com/tetratelabs/wazero/experimental/logging" - "github.com/tetratelabs/wazero/experimental/opt" "github.com/tetratelabs/wazero/internal/testing/binaryencoding" "github.com/tetratelabs/wazero/internal/testing/require" "github.com/tetratelabs/wazero/internal/wasm" @@ -52,7 +51,7 @@ func RequireNoDiffT(t *testing.T, wasmBin []byte, checkMemory, loggingCheck bool // RequireNoDiff ensures that the behavior is the same between the compiler and the interpreter for any given binary. func RequireNoDiff(wasmBin []byte, checkMemory, loggingCheck bool, requireNoError func(err error)) { const features = api.CoreFeaturesV2 | experimental.CoreFeaturesThreads - compiler := wazero.NewRuntimeWithConfig(context.Background(), opt.NewRuntimeConfigOptimizingCompiler().WithCoreFeatures(features)) + compiler := wazero.NewRuntimeWithConfig(context.Background(), wazero.NewRuntimeConfigCompiler().WithCoreFeatures(features)) interpreter := wazero.NewRuntimeWithConfig(context.Background(), wazero.NewRuntimeConfigInterpreter().WithCoreFeatures(features)) defer compiler.Close(context.Background()) defer interpreter.Close(context.Background()) diff --git a/internal/wasm/engine.go b/internal/wasm/engine.go index c2f82efccc..58a4582178 100644 --- a/internal/wasm/engine.go +++ b/internal/wasm/engine.go @@ -58,6 +58,10 @@ type ModuleEngine interface { // Only called when OwnsGlobals() returns true, and must not be called for imported globals GetGlobalValue(idx Index) (lo, hi uint64) + // SetGlobalValue sets the value of the global variable at the given Index. + // Only called when OwnsGlobals() returns true, and must not be called for imported globals + SetGlobalValue(idx Index, lo, hi uint64) + // OwnsGlobals returns true if this ModuleEngine owns the global variables. If true, wasm.GlobalInstance's Val,ValHi should // not be accessed directly. OwnsGlobals() bool diff --git a/internal/wasm/global.go b/internal/wasm/global.go index f28f46ed4f..abaa2d1f99 100644 --- a/internal/wasm/global.go +++ b/internal/wasm/global.go @@ -51,5 +51,5 @@ func (g mutableGlobal) String() string { // Set implements the same method as documented on api.MutableGlobal. func (g mutableGlobal) Set(v uint64) { - g.g.Val = v + g.g.SetValue(v, 0) } diff --git a/internal/wasm/module_test.go b/internal/wasm/module_test.go index 6d8efe26ac..cded118e47 100644 --- a/internal/wasm/module_test.go +++ b/internal/wasm/module_test.go @@ -818,7 +818,7 @@ func TestModule_buildGlobals(t *testing.T) { mi.buildGlobals(m, func(funcIndex Index) Reference { require.Equal(t, localFuncRefInstructionIndex, funcIndex) - return 0x99999 + return Reference(uintptr(0x99999)) }) expectedGlobals := []*GlobalInstance{ imported[0], imported[1], diff --git a/internal/wasm/store.go b/internal/wasm/store.go index fe9d6d150d..4948c8b7c9 100644 --- a/internal/wasm/store.go +++ b/internal/wasm/store.go @@ -222,7 +222,7 @@ func (m *ModuleInstance) applyElements(elems []ElementSegment) { if table.Type == RefTypeExternref { for i := 0; i < len(elem.Init); i++ { - references[offset+uint32(i)] = Reference(0) + references[offset+uint32(i)] = nil } } else { for i, init := range elem.Init { @@ -233,7 +233,7 @@ func (m *ModuleInstance) applyElements(elems []ElementSegment) { var ref Reference if index, ok := unwrapElementInitGlobalReference(init); ok { global := m.Globals[index] - ref = Reference(global.Val) + ref = Reference(uintptr(global.Val)) } else { ref = m.Engine.FunctionInstanceReference(index) } @@ -558,7 +558,7 @@ func (g *GlobalInstance) initialize(importedGlobals []*GlobalInstance, expr *Con } case OpcodeRefFunc: v, _, _ := leb128.LoadUint32(expr.Data) - g.Val = uint64(funcRefResolver(v)) + g.Val = uint64(uintptr(funcRefResolver(v))) case OpcodeVecV128Const: g.Val, g.ValHi = binary.LittleEndian.Uint64(expr.Data[0:8]), binary.LittleEndian.Uint64(expr.Data[8:16]) } @@ -585,6 +585,14 @@ func (g *GlobalInstance) Value() (uint64, uint64) { return g.Val, g.ValHi } +func (g *GlobalInstance) SetValue(lo, hi uint64) { + if g.Me != nil { + g.Me.SetGlobalValue(g.Index, lo, hi) + } else { + g.Val, g.ValHi = lo, hi + } +} + func (s *Store) GetFunctionTypeIDs(ts []FunctionType) ([]FunctionTypeID, error) { ret := make([]FunctionTypeID, len(ts)) for i := range ts { diff --git a/internal/wasm/store_test.go b/internal/wasm/store_test.go index 41fc4f1718..91d9e945db 100644 --- a/internal/wasm/store_test.go +++ b/internal/wasm/store_test.go @@ -466,6 +466,9 @@ func (e *mockEngine) NewModuleEngine(_ *Module, _ *ModuleInstance) (ModuleEngine // GetGlobalValue implements the same method as documented on wasm.ModuleEngine. func (e *mockModuleEngine) GetGlobalValue(idx Index) (lo, hi uint64) { panic("BUG") } +// SetGlobalValue implements the same method as documented on wasm.ModuleEngine. +func (e *mockModuleEngine) SetGlobalValue(idx Index, lo, hi uint64) { panic("BUG") } + // OwnsGlobals implements the same method as documented on wasm.ModuleEngine. func (e *mockModuleEngine) OwnsGlobals() bool { return false } @@ -628,7 +631,7 @@ func TestGlobalInstance_initialize(t *testing.T) { &ConstantExpression{Opcode: OpcodeRefFunc, Data: []byte{1}}, func(funcIndex Index) Reference { require.Equal(t, Index(1), funcIndex) - return 0xdeadbeaf + return asReference(0xdeadbeaf) }, ) require.Equal(t, uint64(0xdeadbeaf), g.Val) @@ -967,7 +970,7 @@ func TestModuleInstance_applyElements(t *testing.T) { m := &ModuleInstance{} m.Tables = []*TableInstance{{Type: RefTypeExternref, References: make([]Reference, 10)}} for i := range m.Tables[0].References { - m.Tables[0].References[i] = 0xffff // non-null ref. + m.Tables[0].References[i] = asReference(0xffff) // non-null ref. } // This shouldn't panic. @@ -977,23 +980,23 @@ func TestModuleInstance_applyElements(t *testing.T) { {Mode: ElementModeActive, OffsetExpr: ConstantExpression{Opcode: OpcodeI32Const, Data: leb128_100}, Init: make([]Index, 5)}, // Iteration stops at this point, so the offset:5 below shouldn't be applied. {Mode: ElementModeActive, OffsetExpr: ConstantExpression{Opcode: OpcodeI32Const, Data: []byte{5}}, Init: make([]Index, 5)}, }) - require.Equal(t, []Reference{0, 0, 0, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff}, + require.Equal(t, []Reference{nil, nil, nil, asReference(0xffff), asReference(0xffff), asReference(0xffff), asReference(0xffff), asReference(0xffff), asReference(0xffff), asReference(0xffff)}, m.Tables[0].References) m.applyElements([]ElementSegment{ {Mode: ElementModeActive, OffsetExpr: ConstantExpression{Opcode: OpcodeI32Const, Data: []byte{5}}, Init: make([]Index, 5)}, }) - require.Equal(t, []Reference{0, 0, 0, 0xffff, 0xffff, 0, 0, 0, 0, 0}, m.Tables[0].References) + require.Equal(t, []Reference{nil, nil, nil, asReference(0xffff), asReference(0xffff), nil, nil, nil, nil, nil}, m.Tables[0].References) }) t.Run("funcref", func(t *testing.T) { e := &mockEngine{} me, err := e.NewModuleEngine(nil, nil) - me.(*mockModuleEngine).functionRefs = map[Index]Reference{0: 0xa, 1: 0xaa, 2: 0xaaa, 3: 0xaaaa} + me.(*mockModuleEngine).functionRefs = map[Index]Reference{0: asReference(0xa), 1: asReference(0xaa), 2: asReference(0xaaa), 3: asReference(0xaaaa)} require.NoError(t, err) m := &ModuleInstance{Engine: me, Globals: []*GlobalInstance{{}, {Val: 0xabcde}}} m.Tables = []*TableInstance{{Type: RefTypeFuncref, References: make([]Reference, 10)}} for i := range m.Tables[0].References { - m.Tables[0].References[i] = 0xffff // non-null ref. + m.Tables[0].References[i] = asReference(0xffff) // non-null ref. } // This shouldn't panic. @@ -1004,12 +1007,16 @@ func TestModuleInstance_applyElements(t *testing.T) { {Mode: ElementModeActive, OffsetExpr: ConstantExpression{Opcode: OpcodeI32Const, Data: leb128_100}, Init: make([]Index, 5)}, // Iteration stops at this point, so the offset:5 below shouldn't be applied. {Mode: ElementModeActive, OffsetExpr: ConstantExpression{Opcode: OpcodeI32Const, Data: []byte{5}}, Init: make([]Index, 5)}, }) - require.Equal(t, []Reference{0xa, 0xaa, 0xaaa, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xabcde}, + require.Equal(t, []Reference{asReference(0xa), asReference(0xaa), asReference(0xaaa), asReference(0xffff), asReference(0xffff), asReference(0xffff), asReference((0xffff)), asReference(0xffff), asReference(0xffff), asReference(0xabcde)}, m.Tables[0].References) m.applyElements([]ElementSegment{ {Mode: ElementModeActive, OffsetExpr: ConstantExpression{Opcode: OpcodeI32Const, Data: []byte{5}}, Init: []Index{0, ElementInitNullReference, 2}}, }) - require.Equal(t, []Reference{0xa, 0xaa, 0xaaa, 0xffff, 0xffff, 0xa, 0xffff, 0xaaa, 0xffff, 0xabcde}, + require.Equal(t, []Reference{asReference(0xa), asReference(0xaa), asReference(0xaaa), asReference(0xffff), asReference(0xffff), asReference(0xa), asReference((0xffff)), asReference(0xaaa), asReference(0xffff), asReference(0xabcde)}, m.Tables[0].References) }) } + +func asReference(u uint) Reference { + return Reference(uintptr(u)) +} diff --git a/internal/wasm/table.go b/internal/wasm/table.go index ac9fc49862..6c3840038f 100644 --- a/internal/wasm/table.go +++ b/internal/wasm/table.go @@ -3,6 +3,7 @@ package wasm import ( "fmt" "math" + "unsafe" "github.com/tetratelabs/wazero/api" "github.com/tetratelabs/wazero/internal/leb128" @@ -133,7 +134,7 @@ type TableInstance struct { type ElementInstance = []Reference // Reference is the runtime representation of RefType which is either RefTypeFuncref or RefTypeExternref. -type Reference = uintptr +type Reference = unsafe.Pointer // validateTable ensures any ElementSegment is valid. This caches results via Module.validatedActiveElementSegments. // Note: limitsType are validated by decoders, so not re-validated here. @@ -314,7 +315,7 @@ func (t *TableInstance) Grow(delta uint32, initialRef Reference) (currentLen uin newLen >= math.MaxUint32 || (t.Max != nil && newLen > int64(*t.Max)) { return 0xffffffff // = -1 in signed 32-bit integer. } - t.References = append(t.References, make([]uintptr, delta)...) + t.References = append(t.References, make([]Reference, delta)...) // Uses the copy trick for faster filling the new region with the initial value. // https://gist.github.com/taylorza/df2f89d5f9ab3ffd06865062a4cf015d diff --git a/internal/wasm/table_test.go b/internal/wasm/table_test.go index 1c5b255969..61531c6097 100644 --- a/internal/wasm/table_test.go +++ b/internal/wasm/table_test.go @@ -836,7 +836,7 @@ func TestModule_buildTables(t *testing.T) { }, importedGlobals: []*GlobalInstance{{Type: GlobalType{ValType: ValueTypeI32}, Val: 1}}, importedTables: []*TableInstance{{References: make([]Reference, 2), Min: 2}}, - expectedTables: []*TableInstance{{Min: 2, References: []Reference{0, 0}}}, + expectedTables: []*TableInstance{{Min: 2, References: []Reference{nil, nil}}}, }, { name: "imported global derived element offset - ignores min on imported table", @@ -854,7 +854,7 @@ func TestModule_buildTables(t *testing.T) { }, importedGlobals: []*GlobalInstance{{Type: GlobalType{ValType: ValueTypeI32}, Val: 1}}, importedTables: []*TableInstance{{References: make([]Reference, 2), Min: 2}}, - expectedTables: []*TableInstance{{Min: 2, References: []Reference{0, 0}}}, + expectedTables: []*TableInstance{{Min: 2, References: []Reference{nil, nil}}}, }, { name: "imported global derived element offset - two indices", @@ -1066,8 +1066,8 @@ func TestTableInstance_Grow(t *testing.T) { for _, tt := range tests { tc := tt t.Run(tc.name, func(t *testing.T) { - table := &TableInstance{References: make([]uintptr, tc.currentLen), Max: tc.max} - actual := table.Grow(tc.delta, 0) + table := &TableInstance{References: make([]Reference, tc.currentLen), Max: tc.max} + actual := table.Grow(tc.delta, nil) require.Equal(t, tc.exp, actual) }) } diff --git a/site/content/docs/how_do_compiler_functions_work.md b/site/content/docs/how_do_compiler_functions_work.md index 0dffe7dbd1..dd0c6785fa 100644 --- a/site/content/docs/how_do_compiler_functions_work.md +++ b/site/content/docs/how_do_compiler_functions_work.md @@ -203,15 +203,12 @@ we call `panic` with a corresponding error. This jumping is why the strategy is called a trampoline, and only used between the guest wasm and the host running it. -For more details, see [RATIONALE.md][compiler-rationale]. - [call-stack]: https://en.wikipedia.org/wiki/Call_stack [api-function]: https://pkg.go.dev/github.com/tetratelabs/wazero@v1.0.0-rc.1/api#Function [api-module]: https://pkg.go.dev/github.com/tetratelabs/wazero@v1.0.0-rc.1/api#Module [spec-function-instance]: https://www.w3.org/TR/2019/REC-wasm-core-1-20191205/#function-instances%E2%91%A0 [spec-trap]: https://www.w3.org/TR/2019/REC-wasm-core-1-20191205/#trap [spec-unreachable]: https://www.w3.org/TR/2019/REC-wasm-core-1-20191205/#syntax-instr-control -[compiler-rationale]: https://github.com/tetratelabs/wazero/blob/v1.0.0-rc.1/internal/engine/compiler/RATIONALE.md [signal-handler-discussion]: https://gophers.slack.com/archives/C1C1YSQBT/p1675992411241409 [cgo-not-go]: https://www.youtube.com/watch?v=PAAkCSZUG1c&t=757s