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How to generate the bit-file for fpga #600

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shankar59 opened this issue Nov 18, 2024 · 3 comments
Open

How to generate the bit-file for fpga #600

shankar59 opened this issue Nov 18, 2024 · 3 comments
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fpga fpga related issue question Further information is requested

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@shankar59
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I've setup the flow using docker and I'm able to run commands like make mcu-gen and get the outputs in respective directory. However, whilst using the command make vivado-fpga FPGA_BOARD=pynq-z2 the log file shows vivado command not found. I've installed vivado in my local machine. I've added the vivado installation path to docker path and it was able to fetch the license. However i was unable to run vivado because of the error stating unsupported architecture. I'm attaching the screenshots before and after adding the vivado path to the docker for your persual.

Thanks and Regards,
Shankar.
Screenshot from 2024-11-18 17-36-12
Screenshot from 2024-11-18 17-28-25

@davideschiavone davideschiavone added fpga fpga related issue question Further information is requested labels Nov 18, 2024
@dsjdx
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dsjdx commented Dec 10, 2024

maybe you can try this commnd:

> sudo apt-get update
> sudo apt-get install coreutils

because the docker some base tools may be missing,but I don‘t know if this tone will work. If you have time,you can try Manual setup, I can generate the bit-file in my own ubuntu20.04 virtual machine.

@shankar59
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For the manual flow,
Did you follow the flow as mentioned in the readme or did some additional modifications ?

Regards,
Shankaranarayanan H.

@dsjdx
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dsjdx commented Dec 12, 2024

In the ubuntu 18.04, 20.04 and 22.04, I both follow the flow as mentioned,you don't need to do some additional modifications, At least this is the case during the simulation stage, but I recommend using ubuntu20.04, because some ip(OpenTitan) in this project use the ubuntu 20.04 setting.

If you use ubuntu 20.04 , I can confirm that there are no problems with these chapters in the doc:
1: Compile with Makefile
2: DEBUG(ubuntu18.04 need to set up gcc10 manully, a little diffcult)
3: Run on FPGA
4: Simulate

There is a problem with this chapter:
Implement on ASIC:using DC flow maybe no problem(I just use the FPGA flow), but the Openroad flow has some problem(The sv2v tool will report some errors, an issue mentioned this question)

I'm still studying the other chapters, So I can’t guarantee whether there will be any problems. Hope it helps you.

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